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MPC8555E powerquicc? iii integrated processor family reference manual supports: MPC8555E mpc8541e MPC8555Erm rev. 2 10/2006 4 datasheet u .com
freescale? and the freescale logo are trademarks of freescale semiconductor, inc. the power architecture and power.org word marks and the power and power.org logos and related marks are trademarks and service marks licensed by power.org. the described product contains a powerpc processor core. the powerpc name is a trademark of ibm corp. and used under license.ieee 802.3, 802.3u, 802.3x, 802.3z, 802.3ac, and 802.11i are registered trademarks of the institute of electrical and electronics engineers, inc. (ieee). this product is not endorsed or approved by the ieee. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc., 2004, 2006. all rights reserved. information in this document is provid ed solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental da mages. ?typical? parameters which may be provided in freescale semiconductor data sheets and/or spec ifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. how to reach us: home page: www.freescale.com email: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 (800) 521-6274 480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku tokyo 153-0064, japan 0120 191014 +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate, tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 (800) 441-2447 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor @hibbertgroup.com how to reach us: home page: www.freescale.com email: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 (800) 521-6274 480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku tokyo 153-0064, japan 0120 191014 +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate, tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 (800) 441-2447 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor @hibbertgroup.com document number: MPC8555Erm rev. 2, 10/2006 4 datasheet u .com
part i? overview i overview 1 memory map 2 signal descriptions 3 reset, clocking, and initialization 4 part ii? e500 core complex and l2 cache ii core complex overview 5 core register summary 6 l2 look-aside cache/sram 7 part iii? memory, security, and i/o interfaces iii e500 coherency module 8 ddr memory controller 9 programmable interrupt controller 10 i 2 c interface 11 duart 12 local bus controller 13 three-speed ethernet controllers 14 dma controller 15 pci bus interface 16 security engine (sec) 2.0 17 part iv? global functions and debug iv global utilities 18 performance monitor 19 debug features and watchpoint facility 20 4 datasheet u .com
i part i? overview 1 overview 2 memory map 3 signal descriptions 4 reset, clocking, and initialization ii part ii? e500 core complex and l2 cache 5 core complex overview 6 core register summary 7 l2 look-aside cache/sram iii part iii? memory, security, and i/o interfaces 8 e500 coherency module 9 ddr memory controller 10 programmable interrupt controller 11 i 2 c interface 12 duart 13 local bus controller 14 three-speed ethernet controllers 15 dma controller 16 pci bus interface 17 security engine (sec) 2.0 iv part iv? global functions and debug 18 global utilities 19 performance monitor 20 debug features and watchpoint facility 4 datasheet u .com
part v? cpm features v communications proce ssor module overview 21 cpm interrupt controller 22 serial interface with time-slot assigner 23 cpm multiplexing 24 baud-rate generators (brgs) 25 cpm timers 26 sdma channels 27 serial communications controllers (sccs) 28 scc uart mode 29 scc hdlc mode 30 scc bisync mode 31 scc transparent mode 32 scc appletalk mode 33 quicc multi-channel controller (qmc) 34 universal serial bus controller 35 serial management controllers (smcs) 36 fast communications controllers (fccs) 37 fcc hdlc controller 38 fcc transparent controller 39 cpm fast ethernet controller 40 atm controller 41 at m a a l 2 42 serial peripheral interface (spi) 43 i 2 c controller 44 parallel i/o ports 45 appendix a?mpc8541e a appendix b?revision history b glossary glo index 1 register index (memory-mapped registers) reg index 2 general index ind index 3 cpm index cpm 4 datasheet u .com
v part v?cpm features 21 communications processor module overview 22 cpm interrupt controller 23 serial interface with time-slot assigner 24 cpm multiplexing 25 baud-rate generators (brgs) 26 cpm timers 27 sdma channels 28 serial communications controllers (sccs) 29 scc uart mode 30 scc hdlc mode 31 scc bisync mode 32 scc transparent mode 33 scc appletalk mode 34 quicc multi-channel controller (qmc) 35 universal serial bus controller 36 serial management controllers (smcs) 37 fast communications controllers (fccs) 38 fcc hdlc controller 39 fcc transparent controller 40 cpm fast ethernet controller 41 atm controller 42 atm aal2 43 serial peripheral interface (spi) 44 i 2 c controller 45 parallel i/o ports a appendix a?mpc8541e b appendix b?revision history glo glossary reg index 1 register index (memory-mapped registers) ind index 2 general index cpm index 3 cpm index 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor vii contents paragraph number title page number contents about this book audience ....................................................................................................................... ....cix organization................................................................................................................... ...cix suggested reading......................................................................................................... cxiii general informa tion................................................................................................... cxiii related documentat ion.............................................................................................. cxiii conventions .................................................................................................................... cxiv signal conventi ons ......................................................................................................cxv acronyms and abbrev iations ..........................................................................................cxv part i overview chapter 1 overview 1.1 introducti on................................................................................................................ ...... 1-1 1.2 MPC8555E overvi ew...................................................................................................... 1-2 1.2.1 key features .............................................................................................................. .. 1-2 1.3 MPC8555E architecture overview................................................................................. 1-9 1.3.1 e500 core overview .................................................................................................... 1-9 1.3.2 integrated security engine (sec).............................................................................. 1-12 1.3.3 communications processo r module (cpm) .............................................................. 1-13 1.3.4 on-chip memory unit............................................................................................... 1-14 1.3.4.1 on-chip memory as memory-mapped sram..................................................... 1-15 1.3.4.2 on-chip memory as l2 cache.............................................................................. 1-15 1.3.5 e500 coherency m odule (ecm)................................................................................ 1-16 1.3.6 ddr sdram contro ller .......................................................................................... 1-16 1.3.7 programmable interrupt co ntroller (pic).................................................................. 1-17 1.3.8 i 2 c controllers ........................................................................................................... 1-17 1.3.9 boot sequencer .......................................................................................................... 1- 17 1.3.10 dual universal asynchronous recei ver/transmitter (duart) ............................... 1-17 1.3.11 local bus controller (lbc) ...................................................................................... 1-18 1.3.12 three-speed ethernet cont rollers (10/100/ 1gb)....................................................... 1-18 1.3.13 integrated dma......................................................................................................... 1- 19 1.3.14 pci contro ller........................................................................................................... .1-19 1.3.15 power manageme nt ................................................................................................... 1-19 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 viii freescale semiconductor contents paragraph number title page number 1.3.16 clocking................................................................................................................. .... 1-20 1.3.17 address ma p .............................................................................................................. 1-20 1.3.18 ocean switch fabric ................................................................................................ 1-20 1.4 data processing ov erview............................................................................................. 1-20 1.4.1 processing between the cp m and local bus............................................................ 1-21 1.4.2 processing across the on-chip fabric...................................................................... 1-22 1.4.3 data processing with the e500 coherency module ................................................... 1-23 1.5 compatibility issues ...................................................................................................... 1- 23 1.5.1 software .................................................................................................................. ... 1-23 1.5.2 MPC8555E hardwa re................................................................................................ 1-23 1.5.3 communications protoc ol table................................................................................ 1-24 1.5.4 MPC8555E configur ations........................................................................................ 1-24 1.5.5 pin configurat ions ..................................................................................................... 1-2 4 1.5.6 communications perf ormance................................................................................... 1-24 1.6 reference manual revisi on history .............................................................................. 1-25 chapter 2 memory map 2.1 local memory map overvi ew and example .................................................................. 2-1 2.2 address translation and mapping ................................................................................... 2-3 2.2.1 sram windows .......................................................................................................... 2-4 2.2.2 window into configur ation space............................................................................... 2-4 2.2.3 local access windows................................................................................................ 2-4 2.2.3.1 local access register memory map ...................................................................... 2-5 2.2.3.2 local access window n base address registers (lawbar0?lawbar7)........ 2-5 2.2.3.3 local access window n attributes registers (lawar0?lawar7).................... 2-6 2.2.3.4 precedence of local access windows .................................................................... 2-7 2.2.3.5 configuring local ac cess windows ....................................................................... 2-7 2.2.3.6 distinguishing local access windows from other mapping functions ................ 2-7 2.2.3.7 illegal interaction between lo cal access windows and ddr sdram chip selects ......................................................................................................... 2-7 2.2.4 outbound address translati on and mapping windows.............................................. 2-8 2.2.5 inbound address translation and mapping windows ................................................ 2-8 2.2.5.1 pci inbound atmu ................................................................................................ 2-8 2.2.5.2 illegal interaction between inbound atmus and local access windows ............ 2-8 2.3 configuration, control, and status register map............................................................ 2-8 2.3.1 accessing ccsr memory fr om the e500 core........................................................... 2-9 2.3.2 accessing ccsr memory from external masters .................................................... 2-10 2.3.3 organization of cc sr memory ................................................................................ 2-10 2.3.4 general utilities registers ......................................................................................... 2-11 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor ix contents paragraph number title page number 2.3.5 interrupt controller and ccsr .................................................................................. 2-12 2.3.6 communications processor module and ccsr ........................................................ 2-13 2.3.7 device-specific ut ilities.......................................... .................................................. 2-13 2.4 complete ccsr map .................................................................................................... 2-14 chapter 3 signal descriptions 3.1 signals overview ............................................................................................................ .3-1 3.2 configuration signals sa mpled at reset ....................................................................... 3-13 3.3 output signal states during reset ................................................................................ 3-15 chapter 4 reset, clocking, an d initialization 4.1 overview.................................................................................................................... ...... 4-1 4.2 external signal desc ription ............................................................................................. 4-1 4.2.1 system control signals................................................................................................ 4-1 4.2.2 clock signa ls ............................................................................................................. .. 4-2 4.3 memory map/register definition ................................................................................... 4-3 4.3.1 local configurati on control........................................................................................ 4-3 4.3.1.1 accessing configuration, control, and status registers......................................... 4-4 4.3.1.1.1 updating ccsrbar........................................................................................... 4-4 4.3.1.1.2 configuration, control, and status base address register (ccsrbar) .................................................................................................... 4-5 4.3.1.2 accessing alternate conf iguration space ............................................................... 4-5 4.3.1.2.1 alternate configurat ion base address regist er (altcbar)............................ 4-6 4.3.1.2.2 alternate configur ation attribute regist er (altcar)...................................... 4-6 4.3.1.3 boot page transl ation.............................................................................................. 4-7 4.3.1.3.1 boot page translation register (bptr).............................................................. 4-7 4.3.2 boot sequencer ............................................................................................................ 4-8 4.4 functional descri ption..................................................................................................... 4 -8 4.4.1 reset operat ions .......................................................................................................... 4-8 4.4.1.1 soft reset.............................................................................................................. ... 4-8 4.4.1.2 hard reset .............................................................................................................. .4-8 4.4.2 power-on reset sequence........................................................................................... 4-9 4.4.3 power-on reset conf iguration.................................................................................. 4-11 4.4.3.1 system pll ra tio.................................................................................................. 4-11 4.4.3.2 e500 core pll ratio ........................................... .................................................. 4-12 4.4.3.3 boot rom locat ion .............................................................................................. 4-12 4.4.3.4 host/agent confi guration ..................................................................................... 4-13 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 x freescale semiconductor contents paragraph number title page number 4.4.3.5 cpu boot confi guration ....................................................................................... 4-14 4.4.3.6 boot sequencer conf iguration .............................................................................. 4-14 4.4.3.7 tsec width ........................................................................................................... 4-1 5 4.4.3.8 tsec1 protoc ol ..................................................................................................... 4-15 4.4.3.9 tsec2 protoc ol ..................................................................................................... 4-16 4.4.3.10 pci clock selec tion............................................. .................................................. 4-16 4.4.3.11 pci width confi guration....................................................................................... 4-17 4.4.3.12 pci i/o impeda nce ................................................................................................ 4-17 4.4.3.13 pci arbiter config uration ..................................................................................... 4-18 4.4.3.14 pci debug configur ation .................................... .................................................. 4-18 4.4.3.15 memory debug config uration .............................................................................. 4-19 4.4.3.16 ddr debug configuration.................................................................................... 4-19 4.4.3.17 pci output hold c onfiguration............................................................................. 4-19 4.4.3.18 local bus output hold configuration .................................................................. 4-20 4.4.3.19 general-purpose por c onfiguration .................................................................... 4-20 4.4.4 clocking.................................................................................................................. ... 4-21 4.4.4.1 system clock and pci clocks............................................................................... 4-21 4.4.4.2 ethernet cloc ks...................................................................................................... 4-2 2 4.4.4.3 real time cl ock .................................................................................................... 4-22 part ii e500 core complex and l2 cache chapter 5 core complex overview 5.1 overview.................................................................................................................... ...... 5-1 5.1.1 upward compatib ility ............................................. .................................................... 5-3 5.1.2 core complex su mmary ............................................................................................. 5-3 5.2 e500 processor and system version numbers................................................................. 5-4 5.3 features .................................................................................................................... ........ 5-5 5.4 instruction set ............................................................................................................. ... 5-10 5.5 instruction flow ............................................................................................................ .5-12 5.5.1 initial instructi on fetch..... ......................................................................................... 5-1 2 5.5.2 branch detection and prediction ............................................................................... 5-12 5.5.3 e500 execution pi peline .......................................... .................................................. 5-13 5.6 programming model ...................................................................................................... 5-15 5.7 on-chip cache implementation .................................................................................... 5-17 5.8 interrupts and except ion handling ................................................................................ 5-17 5.8.1 exception hand ling ................................................. .................................................. 5-17 5.8.2 interrupt classes ........................................................................................................ 5 -18 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor xi contents paragraph number title page number 5.8.3 interrupt types ........................................................................................................... 5-18 5.8.4 upper bound on interrupt latencies ......................................................................... 5-19 5.8.5 interrupt regi sters...................................................................................................... 5 -19 5.9 memory manage ment.................................................. .................................................. 5-21 5.9.1 address transla tion ................................................. .................................................. 5-22 5.9.2 mmu assist registers (m as0?mas4 and mas6) ................................................. 5-23 5.9.3 process id register s (pid0?pid2)............................................................................ 5-24 5.9.4 tlb coherenc y.......................................................................................................... 5-2 4 5.10 memory cohere ncy ..................................................... .................................................. 5-24 5.10.1 atomic update memory references ......................................................................... 5-24 5.10.2 memory access or dering.......................................................................................... 5-25 5.10.3 cache control inst ructions ........................................................................................ 5-25 5.10.4 programmable page ch aracteristics .......................................................................... 5-25 5.11 core complex bus (ccb) ........................................... .................................................. 5-25 5.12 performance moni toring................................................................................................ 5-26 5.12.1 global control re gister ............................................................................................. 5-26 5.12.2 performance monitor count er register s ................................................................... 5-26 5.12.3 local control regi sters ............................................................................................. 5-26 5.13 legacy support of power arch itecture technology...................................................... 5-27 5.13.1 instruction set comp atibility ..................................................................................... 5-27 5.13.1.1 user instructi on set ............................................. .................................................. 5-27 5.13.1.2 supervisor instru ction set...................................................................................... 5-27 5.13.2 memory subsys tem ................................................................................................... 5-28 5.13.3 exception hand ling ................................................. .................................................. 5-28 5.13.4 memory manage ment.............................................. .................................................. 5-28 5.13.5 reset.................................................................................................................... ....... 5-28 5.13.6 little-endian mode.................................................................................................... 5-2 9 5.14 powerquicc iii implemen tation details ..................................................................... 5-29 chapter 6 core register summary 6.1 overview.................................................................................................................... ...... 6-1 6.1.1 register set .............................................................................................................. .... 6-1 6.2 register model for 32-bi t implementations .................................................................... 6-3 6.2.1 special-purpose regi sters (sprs) ............................................................................... 6-4 6.3 registers for computati onal operations.......................................................................... 6-8 6.3.1 general-purpose regi sters (gprs) .............................................................................. 6-8 6.3.2 integer exception regi ster (xer)............................................................................... 6-8 6.4 registers for branch operations...................................................................................... 6-9 6.4.1 condition register (cr) .............................................................................................. 6-9 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 xii freescale semiconductor contents paragraph number title page number 6.4.2 link register (lr)..................................................................................................... 6-1 1 6.4.3 count register (ctr)................................................................................................ 6-11 6.5 processor control re gisters.. ......................................................................................... 6-11 6.5.1 machine state register (msr) .................................................................................. 6-11 6.5.2 processor id regist er (pir) ...................................................................................... 6-13 6.5.3 processor version regi ster (pvr)............................................................................. 6-13 6.5.4 system version regi ster (svr)................................................................................. 6-14 6.6 timer regist ers ............................................................................................................. .6-14 6.6.1 timer control regist er (tcr)................................................................................... 6-14 6.6.2 timer status register (tsr)...................................................................................... 6-15 6.6.3 time base regi sters .................................................................................................. 6-16 6.6.4 decrementer regi ster ................................................................................................ 6-16 6.6.5 decrementer auto-reload re gister (decar ).......................................................... 6-17 6.7 interrupt regi sters......................................................................................................... .6-17 6.7.1 interrupt registers defined by the em bedded and base categories ......................... 6-17 6.7.1.1 save/restore regist er 0 (srr0)............................................................................ 6-17 6.7.1.2 save/restore regist er 1 (srr1)............................................................................ 6-17 6.7.1.3 critical save/restore re gister 0 (csrr0) ............................................................ 6-17 6.7.1.4 critical save/restore re gister 1 (csrr1) ............................................................ 6-18 6.7.1.5 data exception address re gister (dea r)............................................................ 6-18 6.7.1.6 interrupt vector prefix register (ivpr) ................................................................ 6-18 6.7.1.7 interrupt vector offset registers (ivor n )............................................................ 6-18 6.7.1.8 exception syndrome re gister (esr) .................................................................... 6-19 6.7.2 additional interrupt registers ................................................................................... 6-20 6.7.2.1 machine check save/restore register 0 (mcsrr0) ........................................... 6-20 6.7.2.2 machine check save/restore register 1 (mcsrr1) ........................................... 6-20 6.7.2.3 machine check address re gister (mcar) .......................................................... 6-21 6.7.2.4 machine check syndrome re gister (mcsr)........................................................ 6-21 6.8 software-use sprs (sprg0? sprg7 and usprg0) ................................................... 6-22 6.9 branch target buffer (btb) register s .......................................................................... 6-23 6.9.1 branch buffer entry addres s register (bbear) ..................................................... 6-23 6.9.2 branch buffer target addres s register (bbtar) .................................................... 6-23 6.9.3 branch unit control and stat us register (bucsr) .................................................. 6-24 6.10 hardware implementation-de pendent regist ers........................................................... 6-25 6.10.1 hardware implementation-depende nt register 0 (hid0)......................................... 6-25 6.10.2 hardware implementation-depende nt register 1 (hid1)......................................... 6-26 6.11 l1 cache configurati on registers................................................................................. 6-28 6.11.1 l1 cache control and status register 0 (l1csr0) .................................................. 6-28 6.11.2 l1 cache control and status register 1 (l1csr1) .................................................. 6-29 6.11.3 l1 cache configuration re gister 0 (l1cfg0) ......................................................... 6-30 6.11.4 l1 cache configuration re gister 1 (l1cfg1) ......................................................... 6-31 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor xiii contents paragraph number title page number 6.12 mmu regist ers.............................................................................................................. 6-32 6.12.1 process id register s (pid0?pid2)............................................................................ 6-32 6.12.2 mmu control and status re gister 0 (mmucsr0) .................................................. 6-32 6.12.3 mmu configuration regi ster (mmucfg) .............................................................. 6-32 6.12.4 tlb configuration registers (tlb n cfg)................................................................ 6-33 6.12.4.1 tlb0 configuration regist er 0 (tlb0cfg) ........................................................ 6-33 6.12.4.2 tlb1 configuration regist er 1 (tlb1cfg) ........................................................ 6-34 6.12.5 mmu assist regi sters............................................................................................... 6-34 6.12.5.1 mas register 0 (mas0) ....................................................................................... 6-34 6.12.5.2 mas register 1 (mas1) ....................................................................................... 6-35 6.12.5.3 mas register 2 (mas2) ....................................................................................... 6-36 6.12.5.4 mas register 3 (mas3) ....................................................................................... 6-37 6.12.5.5 mas register 4 (mas4) ....................................................................................... 6-37 6.12.5.6 mas register 6 (mas6) ....................................................................................... 6-38 6.13 debug registers ............................................................................................................ .6-39 6.13.1 debug control registers (dbcr0?dbcr2) ............................................................ 6-39 6.13.1.1 debug control register 0 (dbcr0)...................................................................... 6-39 6.13.1.2 debug control register 1 (dbcr1)...................................................................... 6-40 6.13.1.3 debug control register 2 (dbcr2)...................................................................... 6-41 6.13.2 debug status regist er (dbsr).................................................................................. 6-42 6.13.3 instruction address compare registers (iac1?iac2) ............................................. 6-44 6.13.4 data address compare registers (dac1?dac2).................................................... 6-44 6.14 signal processing and embedded floati ng-point status and control register (spefscr) ....................... ......................................................................................... 6-44 6.14.1 accumulator (a cc)................................................................................................... 6-46 6.15 performance monitor re gisters (pmrs) ....................................................................... 6-47 6.15.1 global control register 0 (pmgc0, upmgc0)....................................................... 6-48 6.15.2 local control a registers (pmlca 0?pmlca3, upmlca0?upmlca3) ............... 6-48 6.15.3 local control b registers (pml cb0?pmlcb3, upmlcb0?upmlcb3) .............. 6-49 6.15.4 performance monitor counter regi sters (pmc0?pmc3, upmc0?upmc3).......... 6-50 chapter 7 l2 look-aside cache/sram 7.1 l2 cache overview ......................................................................................................... 7- 1 7.1.1 l2 cache and sram features .................................................................................... 7-2 7.2 cache organi zation............... ........................................................................................... 7-3 7.3 memory map/register definition ................................................................................... 7-6 7.3.1 l2/sram register de scriptions ................................................................................. 7-7 7.3.1.1 l2 control register (l2ctl).................................................................................. 7-7 7.3.1.2 l2 cache external write address registers 0?3 (l2cewar n ) .......................... 7-10 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 xiv freescale semiconductor contents paragraph number title page number 7.3.1.3 l2 cache external write control registers 0?3 (l2cewcr n ) ........................... 7-10 7.3.1.4 l2 memory-mapped sram base address registers 0?1 (l2srbar n ) ............ 7-11 7.3.1.5 l2 error registers.................................................................................................. 7-12 7.3.1.5.1 error injection registers .................................................................................... 7-12 7.3.1.5.2 error control and capt ure registers ................................................................. 7-14 7.4 external writes to the l2 cache (cache stashing)........................................................ 7-20 7.5 l2 cache timing ........................................................................................................... 7- 21 7.6 l2 cache and sram coherency................................................................................... 7-22 7.6.1 l2 cache coherenc y rules........................................................................................ 7-22 7.6.2 memory-mapped sram c oherency rules .............................................................. 7-23 7.7 l2 cache locking.......................................................................................................... 7- 23 7.7.1 locking the entire l2 cache ..................................................................................... 7-24 7.7.2 locking programmed memory ranges..................................................................... 7-24 7.7.3 locking selected lines.............................................................................................. 7-24 7.7.4 clearing locks on sel ected lines ............................................................................. 7-25 7.7.5 flash clearing of instruct ion and data locks ........................................................... 7-25 7.7.6 locks with stal e data ................................................................................................ 7-26 7.8 plru l2 replacement policy....................................................................................... 7-26 7.8.1 plru bit update c onsiderations .............................................................................. 7-27 7.8.2 allocation of li nes .................................................................................................... 7-2 7 7.9 l2 cache operat ion ....................................................................................................... 7-2 8 7.9.1 l2 cache states ......................................................................................................... 7- 28 7.9.2 flash invalidation of the l2 cache............................................................................ 7-29 7.9.3 l2 state transi tions ................................................................................................... 7-2 9 7.10 initialization/applicati on informatio n ........................................................................... 7-33 7.10.1 initializa tion ........................................................................................................... .... 7-33 7.10.1.1 l2 cache initia lization .......................................................................................... 7-33 7.10.1.2 memory-mapped sram in itialization ................................................................. 7-33 7.10.2 managing er rors ........................................................................................................ 7- 33 7.10.2.1 ecc errors............................................................................................................. 7-33 7.10.2.2 tag parity errors.................................................................................................... 7- 34 part iii memory, security, and i/o interfaces chapter 8 e500 coherency module 8.1 introducti on................................................................................................................ ...... 8-1 8.1.1 overview.................................................................................................................. .... 8-1 8.1.2 features.................................................................................................................. ...... 8-2 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor xv contents paragraph number title page number 8.2 memory map/register definition ................................................................................... 8-2 8.2.1 register descri ptions................................................................................................... 8- 3 8.2.1.1 ecm ccb address configurati on register (eebacr) ........................................ 8-3 8.2.1.2 ecm ccb port configurati on register (eebpcr) ............................................... 8-4 8.2.1.3 ecm error detect regi ster (eedr) ....................................................................... 8-4 8.2.1.4 ecm error enable regi ster (eeer) ....................................................................... 8-5 8.2.1.5 ecm error attributes captur e register (eeatr) .................................................. 8-6 8.2.1.6 ecm error address capture register (eeadr) .................................................... 8-7 8.3 functional descri ption..................................................................................................... 8 -7 8.3.1 i/o arbiter............................................................................................................... ..... 8-7 8.3.2 ccb arbiter............................................................................................................... .. 8-8 8.3.3 transaction queue ....................................................................................................... 8- 8 8.3.4 global data multip lexer .............................................................................................. 8-8 8.3.5 ccb interface ............................................................................................................. .8-8 8.4 initialization/applicati on informatio n ............................................................................. 8-9 chapter 9 ddr memory controller 9.1 introducti on................................................................................................................ ...... 9-1 9.2 features .................................................................................................................... ........ 9-2 9.2.1 modes of operat ion ..................................................................................................... 9-3 9.3 external signal de scriptions ........................................................................................... 9-3 9.3.1 signals over view......................................................................................................... 9 -3 9.3.2 detailed signal de scriptions ....................................................................................... 9-4 9.3.2.1 memory interface signals........................................................................................ 9-5 9.3.2.2 clock interface signals............................................................................................ 9-8 9.3.2.3 debug signals.......................................................................................................... 9 -8 9.4 memory map/register definition ................................................................................... 9-8 9.4.1 register descri ptions................................................................................................... 9- 9 9.4.1.1 chip select memory bounds (cs n _bnds)............................................................ 9-9 9.4.1.2 chip select configuration (cs n _config).......................................................... 9-10 9.4.1.3 ddr sdram timing configurat ion 1 (timing_cfg_1)................................. 9-11 9.4.1.4 ddr sdram timing configurat ion 2 (timing_cfg_2)................................. 9-12 9.4.1.5 ddr sdram control configurat ion (ddr_sdram_cfg)............................. 9-13 9.4.1.6 ddr sdram mode configurat ion (ddr_sdram_mode)............................ 9-14 9.4.1.7 ddr sdram interval configurat ion (ddr_sdram_interval) ................. 9-15 9.4.1.8 ddr sdram clock control ( ddr_sdram_clk_cntl) ............................. 9-16 9.4.1.9 memory data path error injection mask high (data_err_inject_hi) ........ 9-17 9.4.1.10 memory data path error injection mask low (data_err_inject_lo)........ 9-17 9.4.1.11 memory data path error injectio n mask ecc (ecc_err_inject) ................. 9-18 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 xvi freescale semiconductor contents paragraph number title page number 9.4.1.12 memory data path read captur e high (capture_d ata_hi)......................... 9-19 9.4.1.13 memory data path read captur e low (capture_data_lo) ........................ 9-19 9.4.1.14 memory data path read capt ure ecc (capture_ecc).................................. 9-20 9.4.1.15 memory error detect (err_detect)................................................................ 9-20 9.4.1.16 memory error disable (err_disable)............................................................. 9-21 9.4.1.17 memory error interrupt en able (err_int_en).................................................. 9-22 9.4.1.18 memory error attributes capt ure (capture_attributes).......................... 9-22 9.4.1.19 memory error address capt ure (capture_address) .................................. 9-23 9.4.1.20 single-bit ecc memory error management (err_sbe) ................................... 9-24 9.5 functional descri ption................................................................................................... 9-2 4 9.5.1 ddr sdram interface operation............................................................................ 9-29 9.5.1.1 supported ddr sdram or ganizations............................................................... 9-29 9.5.2 ddr sdram address mu ltiplexing........................................................................ 9-30 9.5.3 jedec standard ddr sdram interface commands ............................................. 9-31 9.5.4 sdram interface timing ......................................................................................... 9-33 9.5.4.1 clock distribut ion ................................................................................................. 9-36 9.5.5 ddr sdram mode-set co mmand timing............................................................. 9-37 9.5.6 ddr sdram registered dimm mode ................................................................... 9-38 9.5.7 ddr sdram source synchronous clock control .................................................. 9-38 9.5.8 ddr sdram write timing adjustments ................................................................ 9-38 9.5.9 ddr sdram refr esh ............................................ .................................................. 9-39 9.5.9.1 ddr sdram refres h timing.............................................................................. 9-40 9.5.9.2 ddr sdram refresh and power-saving modes ................................................ 9-41 9.5.9.2.1 self-refresh in sleep mode............................................................................... 9-42 9.5.10 ddr data beat or dering........................................................................................... 9-42 9.5.11 page mode and logical bank retentio n ................................................................... 9-43 9.5.12 error checking and corr ecting (ecc) ...................................................................... 9-44 9.5.13 error manageme nt ..................................................................................................... 9-46 9.6 initialization/applicati on informatio n ........................................................................... 9-46 9.6.1 ddr sdram initializa tion sequence ...................................................................... 9-47 chapter 10 programmable interrupt controller 10.1 introducti on............................................................................................................... ..... 10-1 10.1.1 overview................................................................................................................. ... 10-1 10.1.2 features................................................................................................................. ..... 10-3 10.1.3 interrupts to the processor core................................................................................. 10-3 10.1.4 modes of operat ion ................................................................................................... 10-4 10.1.4.1 mixed mode (gcr [m] = 1) .................................................................................. 10-4 10.1.4.2 pass-through mode (g cr[m] = 0) ...................................................................... 10-5 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor xvii contents paragraph number title page number 10.1.5 interrupt s ources........................................................................................................ 10-5 10.1.5.1 interrupt routing? mixed mode........................................................................... 10-6 10.1.5.2 internal interrupt sources ...................................................................................... 10-6 10.2 external signal desc ription ........................................................................................... 10-6 10.2.1 signal over view ........................................................................................................ 10 -7 10.2.2 detailed signal de scriptions ..................................................................................... 10-7 10.3 memory map/register definition ................................................................................. 10-8 10.3.1 global regist ers....................................................................................................... 10 -14 10.3.1.1 feature reporting regi ster (frr)....................................................................... 10-15 10.3.1.2 global configuration re gister (gcr)................................................................. 10-15 10.3.1.3 vendor identification re gister (vir ) .................................................................. 10-16 10.3.1.4 processor initialization register (pir) ................................................................ 10-16 10.3.1.5 ipi vector/priorit y registers (ipivpr n ) ............................................................. 10-17 10.3.1.6 spurious vector regi ster (svr).......................................................................... 10-18 10.3.2 global timer regi sters ............................................................................................ 10-18 10.3.2.1 timer frequency reporting register (tfrr)..................................................... 10-19 10.3.2.2 global timer current count registers (gtccr n ) ............................................. 10-19 10.3.2.3 global timer base c ount registers (gtbcr n ).................................................. 10-20 10.3.2.4 global timer vector/pri ority registers (gtvpr n )............................................. 10-20 10.3.2.5 global timer destinat ion registers (gtdr n ) .................................................... 10-21 10.3.2.6 timer control regist er (tcr)............................................................................. 10-22 10.3.3 summary regist ers .................................................................................................. 10-24 10.3.3.1 irq_out summary register 0 (irqsr0)......................................................... 10-24 10.3.3.2 irq_out summary register 1 (irqsr1)......................................................... 10-25 10.3.3.3 critical interrupt summary register 0 (cis r0).................................................. 10-26 10.3.3.4 critical interrupt summary register 1 (cis r1).................................................. 10-26 10.3.4 performance monitor mask registers (pmmr s).................................................... 10-27 10.3.4.1 performance monitor mask register (lower) (pm n mr0)................................. 10-27 10.3.4.2 performance monitor mask registers (upper) (pm n mr1)................................ 10-28 10.3.5 message regist ers.................................................................................................... 10-2 8 10.3.5.1 message registers (m sgr0?msgr3) ............................................................... 10-28 10.3.5.2 message enable regi ster (mer)......................................................................... 10-29 10.3.5.3 message status regi ster (msr) .......................................................................... 10-29 10.3.6 interrupt source configur ation registers ................................................................ 10-30 10.3.6.1 external interrupt vector/priorit y registers (eivpr0?eivpr11) ..................... 10-30 10.3.6.2 external interrupt destination registers (eidr 0?eidr11) ............................... 10-31 10.3.6.3 internal interrupt vector/priorit y registers (iivpr 0?iivpr31)......................... 10-32 10.3.6.4 internal interrupt destination registers (iidr0?iidr31) .................................. 10-33 10.3.6.5 messaging interrupt vector/priorit y registers (mivpr0?mivpr3) ................. 10-34 10.3.6.6 messaging interrupt destination registers (midr 0?midr3) ........................... 10-35 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 xviii freescale semiconductor contents paragraph number title page number 10.3.7 per-cpu regist ers ................................................................................................... 10-36 10.3.7.1 interprocessor interrupt dispatch register (ipidr 0?ipidr3) ........................... 10-37 10.3.7.2 processor current task prio rity register (ctpr)............................................... 10-38 10.3.7.3 who am i register (whoami)......................................................................... 10-39 10.3.7.4 processor interrupt acknowle dge register (iack)............................................ 10-39 10.3.7.5 processor end of interrupt register (eoi) .......................................................... 10-40 10.4 functional descri ption................................................................................................. 10-4 1 10.4.1 flow of interrupt control......................................................................................... 10-41 10.4.1.1 interrupt source priority ...................................................................................... 10-42 10.4.1.2 processor current ta sk priority........................................................................... 10-43 10.4.1.3 interrupt acknow ledge ........................................................................................ 10-43 10.4.2 nesting of inte rrupts ................................................................................................ 10-4 3 10.4.3 processor initiali zation ............................................................................................ 10-44 10.4.4 spurious vector generation ..................................................................................... 10-44 10.4.5 messaging interr upts................................................................................................ 10-44 10.4.6 global timers .......................................................................................................... 10 -44 10.4.7 reset of the pic ....................................................................................................... 10 -45 10.5 initialization/applicati on informatio n ......................................................................... 10-45 10.5.1 programming guid elines ......................................................................................... 10-45 10.5.1.1 pic registers ....................................................................................................... 10- 45 10.5.1.2 changing interrupt source configuration ........................................................... 10-47 chapter 11 i 2 c interface 11.1 introducti on............................................................................................................... ..... 11-1 11.1.1 overview................................................................................................................. ... 11-2 11.1.2 features................................................................................................................. ..... 11-2 11.1.3 modes of operation ................................................................................................... 11-2 11.2 external signal descriptions ......................................................................................... 11-3 11.2.1 signal over view ........................................................................................................ 11 -3 11.2.2 detailed signal descriptions ..................................................................................... 11-3 11.3 memory map/register definition ................................................................................. 11-4 11.3.1 register descri ptions................................................................................................. 11- 5 11.3.1.1 i 2 c address register (i2cadr) ........................................................................... 11-5 11.3.1.2 i 2 c frequency divider regi ster (i2cfdr)........................................................... 11-6 11.3.1.3 i 2 c control register (i2ccr) ............................................................................... 11-7 11.3.1.4 i 2 c status register (i2csr) .................................................................................. 11-9 11.3.1.5 i 2 c data register (i2cdr).................................................................................. 11-10 11.3.1.6 digital filter sampling rate register (i2cdfsrr) ............................................11-11 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor xix contents paragraph number title page number 11.4 functional descri ption..................................................................................................11- 11 11.4.1 transaction pr otocol .................................................................................................11-1 1 11.4.1.1 start condition ................................................................................................ 11-12 11.4.1.2 slave address tran smission ................................................................................ 11-12 11.4.1.3 repeated start condition ................................................................................ 11-13 11.4.1.4 stop condition................................................................................................... 11-13 11.4.1.5 protocol implementa tion details ......................................................................... 11-13 11.4.1.5.1 transaction monitoring?implementation details.......................................... 11-13 11.4.1.5.2 control transfer?impleme ntation details ..................................................... 11-14 11.4.1.6 address compare?implemen tation details....................................................... 11-15 11.4.2 arbitration proc edure .............................................................................................. 11-15 11.4.2.1 arbitration cont rol .............................................................................................. 11-15 11.4.3 handshaking ............................................................................................................ 11 -16 11.4.4 clock cont rol........................................................................................................... 1 1-16 11.4.4.1 clock synchronizat ion......................................................................................... 11-16 11.4.4.2 input synchronization and digital filter ............................................................. 11-16 11.4.4.2.1 input signal synchronization .......................................................................... 11-16 11.4.4.2.2 filtering of scl a nd sda lines ..................................................................... 11-17 11.4.4.3 clock stretching .................................................................................................. 11-17 11.4.5 boot sequencer mode.............................................................................................. 11-17 11.4.5.1 eeprom calling address .................................................................................. 11-18 11.4.5.2 eeprom data format ........................................................................................ 11-18 11.5 initialization/applicati on information ......................................................................... 11-20 11.5.1 initialization se quence............................................................................................. 11-20 11.5.2 generation of start .............................................................................................. 11-21 11.5.3 post-transfer softwa re response ............................................................................ 11-21 11.5.4 generation of stop................................................................................................. 11-22 11.5.5 generation of repeated start .............................................................................. 11-22 11.5.6 generation of scl when sda low ....................................................................... 11-22 11.5.7 slave mode interrupt se rvice routine..................................................................... 11-22 11.5.7.1 slave transmitter and received acknowledge ................................................... 11-23 11.5.7.2 loss of arbitration and fo rcing of slave mode.................................................. 11-23 11.5.8 interrupt service rout ine flowchart........................................................................ 11-23 chapter 12 duart 12.1 overview................................................................................................................... ..... 12-1 12.1.1 features................................................................................................................. ..... 12-1 12.1.2 modes of operat ion ................................................................................................... 12-2 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 xx freescale semiconductor contents paragraph number title page number 12.2 external signal de scriptions ......................................................................................... 12-3 12.2.1 signal over view ........................................................................................................ 12 -3 12.2.2 detailed signal de scriptions ..................................................................................... 12-3 12.3 memory map/register definition ................................................................................. 12-4 12.3.1 register descri ptions................................................................................................. 12- 6 12.3.1.1 receiver buffer registers (ur br0, urbr1) (ulcr[dlab] = 0) .................... 12-6 12.3.1.2 transmitter holding registers (uth r0, uthr1) (ulcr[dlab] = 0) ............. 12-6 12.3.1.3 divisor most and least significan t byte registers (udmb and udlb) (ulcr[dlab] = 1) .......................................................................................... 12-7 12.3.1.4 interrupt enable register (uier) (ulcr[dl ab] = 0)........................................ 12-9 12.3.1.5 interrupt id registers (uiir 0, uiir1) (ulcr[dlab] = 0) ................................ 12-9 12.3.1.6 fifo control registers (ufcr0 , ufcr1) (ulcr[dlab] = 0)....................... 12-11 12.3.1.7 line control registers (ulcr0, ulcr1).......................................................... 12-12 12.3.1.8 modem control registers (umcr0, umcr1)................................................... 12-14 12.3.1.9 line status registers (ulsr0, ulsr1) ............................................................. 12-14 12.3.1.10 modem status register s (umsr0, umsr1) ...................................................... 12-16 12.3.1.11 scratch registers (u scr0, uscr1)................................................................... 12-17 12.3.1.12 alternate function registers (uaf r0, uafr1) (ulcr[dlab] = 1) .............. 12-17 12.3.1.13 dma status registers (udsr0, udsr1) .......................................................... 12-18 12.4 functional descri ption................................................................................................. 12-1 9 12.4.1 serial inte rface......................................................................................................... 12-20 12.4.1.1 start bit ........................................................................................................... 12- 20 12.4.1.2 data transfer ....................................................................................................... 12- 21 12.4.1.3 parity bit............................................................................................................. . 12-21 12.4.1.4 stop bit.............................................................................................................. 1 2-21 12.4.2 baud-rate generator logic ..................................................................................... 12-21 12.4.3 local loopback mode ............................................................................................. 12-22 12.4.4 errors ................................................................................................................... .... 12-22 12.4.4.1 framing erro r ...................................................................................................... 12-2 2 12.4.4.2 parity error .......................................................................................................... 1 2-22 12.4.4.3 overrun error....................................................................................................... 12- 22 12.4.5 fifo mode .............................................................................................................. 12 -22 12.4.5.1 fifo interrupt s .................................................................................................... 12-2 3 12.4.5.2 dma mode sel ect............................................................................................... 12-23 12.4.5.3 interrupt control logic........................................................................................ 12-23 12.5 duart initialization/applic ation informat ion .......................................................... 12-24 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor xxi contents paragraph number title page number chapter 13 local bus controller 13.1 introducti on............................................................................................................... ..... 13-1 13.1.1 overview................................................................................................................. ... 13-2 13.1.2 features................................................................................................................. ..... 13-2 13.1.3 modes of operat ion ................................................................................................... 13-3 13.1.3.1 lbc bus clock and cl ock ratios ......................................................................... 13-3 13.1.3.2 source id debug mode ......................................................................................... 13-4 13.1.4 power-down m ode.................................................................................................... 13-4 13.2 external signal de scriptions ......................................................................................... 13-4 13.3 memory map/register definition ................................................................................. 13-8 13.3.1 register descri ptions............................................................................................... 13-10 13.3.1.1 base registers (b r0?br7) ................................................................................. 13-10 13.3.1.2 option registers (o r0?or7).............................................................................. 13-12 13.3.1.2.1 address ma sk .................................................................................................. 13-12 13.3.1.2.2 option registers (or n )?gpcm mode ......................................................... 13-13 13.3.1.2.3 option registers (or n )?upm mode ............................................................ 13-15 13.3.1.2.4 option registers (or n )?sdram mode ...................................................... 13-16 13.3.1.3 upm memory address re gister (mar)............................................................. 13-17 13.3.1.4 upm mode registers (m x mr) ........................................................................... 13-18 13.3.1.5 memory refresh timer presca ler register (mrtpr) ........................................ 13-20 13.3.1.6 upm data register (mdr) ................................................................................. 13-21 13.3.1.7 sdram machine mode regi ster (lsdmr) ...................................................... 13-21 13.3.1.8 upm refresh timer (lurt)............................................................................... 13-23 13.3.1.9 sdram refresh time r (lsrt).......................................................................... 13-24 13.3.1.10 transfer error status re gister (ltesr) .............................................................. 13-25 13.3.1.11 transfer error check disa ble register (ltedr)................................................ 13-26 13.3.1.12 transfer error interrupt en able register (lteir) .............................................. 13-27 13.3.1.13 transfer error attributes register (ltea tr) ..................................................... 13-28 13.3.1.14 transfer error address re gister (ltear).......................................................... 13-29 13.3.1.15 local bus configuration register (lbcr) ......................................................... 13-29 13.3.1.16 clock ratio regist er (lcrr).............................................................................. 13-31 13.4 functional descri ption................................................................................................. 13-3 2 13.4.1 basic architecture.................................................................................................... 13- 33 13.4.1.1 address and address sp ace checking ................................................................ 13-33 13.4.1.2 external address latch en able signal (l ale) .................................................. 13-33 13.4.1.3 data transfer acknow ledge (ta) ....................................................................... 13-35 13.4.1.4 data buffer cont rol (lbctl)............................................................................. 13-36 13.4.1.5 atomic operat ion ................................................................................................ 13-36 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 xxii freescale semiconductor contents paragraph number title page number 13.4.1.6 parity generation and checking (ldp)............................................................... 13-36 13.4.1.7 bus monitor ......................................................................................................... 13- 37 13.4.2 general-purpose chip-selec t machine (gpcm)..................................................... 13-37 13.4.2.1 timing configurat ion .......................................................................................... 13-38 13.4.2.2 chip-select assert ion timing ............................................................................. 13-42 13.4.2.2.1 programmable wait stat e configuration......................................................... 13-42 13.4.2.2.2 chip-select and write en able negation timing ............................................. 13-43 13.4.2.2.3 relaxed timi ng ............................................................................................... 13-43 13.4.2.2.4 output enable (loe ) timing .......................................................................... 13-45 13.4.2.2.5 extended hold time on read accesses .......................................................... 13-46 13.4.2.3 external access termination (lgta ) ................................................................. 13-47 13.4.2.4 boot chip-select operation................................................................................. 13-48 13.4.3 sdram machin e .................................................................................................... 13-49 13.4.3.1 supported sdram conf igurations..................................................................... 13-49 13.4.3.2 sdram power-on init ialization ........................................................................ 13-49 13.4.3.3 intel pc133 and jedec-standard sdram interface commands ..................... 13-50 13.4.3.4 page hit check ing ............................................................................................... 13-51 13.4.3.5 page manageme nt................................................................................................ 13-51 13.4.3.6 sdram address multi plexing ........................................................................... 13-51 13.4.3.7 sdram device-specific parameters.................................................................. 13-52 13.4.3.7.1 precharge-to-activate interval......................................................................... 13-53 13.4.3.7.2 activate-to-read/wr ite interval ...................................................................... 13-53 13.4.3.7.3 column address to first data out?cas latency......................................... 13-54 13.4.3.7.4 last data in to prechar ge?write recovery ................................................... 13-54 13.4.3.7.5 refresh recovery in terval (rfr c) ................................................................. 13-55 13.4.3.7.6 external address and comm and buffers (bufcmd).................................... 13-55 13.4.3.8 sdram interface timing ................................................................................... 13-55 13.4.3.9 sdram read/write tr ansactions....................................................................... 13-58 13.4.3.10 sdram mode-set comm and timing............................................................ 13-58 13.4.3.11 sdram refres h.................................................................................................. 13-58 13.4.3.11.1 sdram refresh timing ................................................................................. 13-59 13.4.4 user-programmable mach ines (upms)................................................................... 13-59 13.4.4.1 upm requests ..................................................................................................... 13-60 13.4.4.1.1 memory access requests................................................................................ 13-61 13.4.4.1.2 upm refresh time r requests ......................................................................... 13-62 13.4.4.1.3 software requests ?run command ............................................................. 13-62 13.4.4.1.4 exception requ ests.......................................................................................... 13-63 13.4.4.2 programming th e upms ...................................................................................... 13-63 13.4.4.2.1 upm programming example (two sequent ial writes to the ram array).... 13-64 13.4.4.2.2 upm programming example (two sequential reads from the ram array) .......................................................................................................... 13-64 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor xxiii contents paragraph number title page number 13.4.4.3 upm signal timi ng............................................................................................. 13-65 13.4.4.4 ram array .......................................................................................................... 13-6 6 13.4.4.4.1 ram words ..................................................................................................... 13-66 13.4.4.4.2 chip-select signal timing (cst n ) ................................................................. 13-69 13.4.4.4.3 byte select signal timing (bst n ) .................................................................. 13-70 13.4.4.4.4 general-purpose signals (g n t n , go n )........................................................... 13-71 13.4.4.4.5 loop control (loop) ..................................................................................... 13-71 13.4.4.4.6 repeat execution of curr ent ram word (redo)......................................... 13-71 13.4.4.4.7 address multiple xing (amx) ......................................................................... 13-72 13.4.4.4.8 data valid and data samp le control (uta) ................................................... 13-72 13.4.4.4.9 lgpl[0:5] signal negation (last) ............................................................... 13-73 13.4.4.4.10 wait mechanis m (waen)............................................................................... 13-73 13.4.4.5 synchronous sampling of lupwait fo r early transfer acknowledge ............ 13-74 13.4.4.6 extended hold time on read accesses .............................................................. 13-74 13.4.4.7 memory system interface example using upm ................................................ 13-75 13.5 initialization/applicati on informatio n ......................................................................... 13-81 13.5.1 interfacing to pe ripherals.. ....................................................................................... 13-81 13.5.1.1 multiplexed address/data bus and n on-multiplexed address signals ............. 13-81 13.5.1.2 peripheral hierarchy on the local bus................................................................ 13-82 13.5.1.3 peripheral hierarchy on the local bus for very high bus speeds..................... 13-82 13.5.1.4 gpcm timings .................................................................................................... 13-83 13.5.2 bus turnaround ....................................................................................................... 13-8 4 13.5.2.1 address phase after pr evious read .................................................................... 13-84 13.5.2.2 read data phase after address phase ................................................................ 13-84 13.5.2.3 read-modify-write cycle for par ity protected memory banks ......................... 13-85 13.5.2.4 upm cycles with additiona l address phas es..................................................... 13-85 13.5.3 interface to different port-size devices.................................................................. 13-85 13.5.4 interfacing to sdram............................................................................................. 13-87 13.5.4.1 basic sdram capabilities of the local bus...................................................... 13-87 13.5.4.2 maximum amount of sd ram supported.......................................................... 13-88 13.5.4.3 sdram machine li mitations............................................................................. 13-88 13.5.4.3.1 analysis of maximum row number du e to bank select multiplexing......... 13-89 13.5.4.3.2 bank select si gnals ......................................................................................... 13-89 13.5.4.3.3 128-mbyte sd ram ........................................................................................ 13-90 13.5.4.3.4 256-mbyte sd ram ........................................................................................ 13-92 13.5.4.3.5 512-mbyte sd ram ........................................................................................ 13-92 13.5.4.3.6 power-down mode.......................................... ................................................ 13-93 13.5.4.3.7 self-refre sh ..................................................................................................... 13-9 4 13.5.4.3.8 sdram timi ng .............................................................................................. 13-95 13.5.4.4 parity support fo r sdram ................................................................................. 13-97 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 xxiv freescale semiconductor contents paragraph number title page number 13.5.5 interfacing to zbt sram....................................................................................... 13-98 13.5.6 interfacing to dsp host ports................................................................................ 13-100 13.5.6.1 interfacing to ms c8101 hdi16 ........................................................................ 13-100 13.5.6.1.1 hdi16 periphe rals ......................................................................................... 13-100 13.5.6.1.2 physical interc onnections .............................................................................. 13-101 13.5.6.1.3 supporting burst tr ansfers............................................................................ 13-103 13.5.6.1.4 host 60x bus: hdi16 peripheral interface hardware timings..................... 13-103 13.5.6.2 interfacing to msc8102 dsi............................................................................. 13-104 13.5.6.2.1 dsi in asynchronous sram-like mode ..................................................... 13-104 13.5.6.2.2 dsi in synchr onous mode ............................................................................ 13-107 13.5.6.2.3 broadcast acces ses........................................................................................ 13-113 13.5.6.3 interfacing to ehpi from texas instruments tms320cxxxx dsps ................. 13-114 13.5.6.3.1 expansion to mult iple dsps.......................................................................... 13-117 chapter 14 three-speed ethernet controllers 14.1 introducti on............................................................................................................... ..... 14-1 14.1.1 three-speed ethernet cont roller overview .............................................................. 14-6 14.2 features ................................................................................................................... ....... 14-7 14.3 modes of oper ation ....................................................................................................... 14 -8 14.4 external signals de scription ......................................................................................... 14-9 14.4.1 detailed signal de scriptions ..................................................................................... 14-9 14.5 memory map/register definition ............................................................................... 14-12 14.5.1 top-level module me mory map ............................................................................ 14-13 14.5.2 detailed memory map?control/ status regist ers.................................................. 14-13 14.5.3 memory-mapped register descriptions.................................................................. 14-19 14.5.3.1 tsec general control and status regist ers ....................................................... 14-19 14.5.3.1.1 interrupt event regi ster (ievent) ................................................................ 14-19 14.5.3.1.2 interrupt mask regi ster (imask) .................................................................. 14-22 14.5.3.1.3 error disabled regi ster (edis)....................................................................... 14-24 14.5.3.1.4 ethernet control regi ster (ecntrl) ............................................................. 14-25 14.5.3.1.5 minimum frame length re gister (minflr)................................................. 14-26 14.5.3.1.6 pause time value re gister (ptv) ................................................................... 14-26 14.5.3.1.7 dma control register (dmactrl) ............................................................. 14-27 14.5.3.1.8 tbi physical address re gister (tbipa) ......................................................... 14-28 14.5.3.2 tsec fifo control and st atus register s ........................................................... 14-29 14.5.3.2.1 fifo pause control regist er (fifo_pause_ctrl) ................................... 14-30 14.5.3.2.2 fifo transmit threshold re gister (fifo_tx_thr) .................................... 14-30 14.5.3.2.3 fifo transmit starve regi ster (fifo_tx_starve) ................................... 14-31 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor xxv contents paragraph number title page number 14.5.3.2.4 fifo transmit starve shutoff register (fifo_tx_starve_shutoff).............................................................. 14-31 14.5.3.3 tsec transmit control and status registers...................................................... 14-32 14.5.3.3.1 transmit control regi ster (tctrl) ............................................................... 14-32 14.5.3.3.2 transmit status regi ster (tstat)................................................................... 14-33 14.5.3.3.3 txbd data length regi ster (tbdlen)......................................................... 14-34 14.5.3.3.4 transmit interrupt coalescing c onfiguration register (txic) ...................... 14-34 14.5.3.3.5 current transmit buffer descript or pointer register (ctbptr) ................... 14-35 14.5.3.3.6 transmit buffer descriptor pointer register (tbptr) ................................... 14-35 14.5.3.3.7 transmit descriptor base a ddress register (tbase) ................................... 14-36 14.5.3.3.8 out-of-sequence txbd re gister (ostbd).................................................... 14-36 14.5.3.3.9 out-of-sequence tx data buffer pointer register (ostbdp)....................... 14-38 14.5.3.4 tsec receive control and status registers ....................................................... 14-39 14.5.3.4.1 receive control regi ster (rctrl) ................................................................ 14-39 14.5.3.4.2 receive status regi ster (rstat).................................................................... 14-40 14.5.3.4.3 rxbd data length regi ster (rbdlen) ........................................................ 14-40 14.5.3.4.4 receive interrupt coalescing c onfiguration regist er (rxic)........................ 14-41 14.5.3.4.5 current receive buffer descriptor pointer register (crbptr) .................... 14-42 14.5.3.4.6 maximum receive buffer le ngth register (mrblr) ................................... 14-42 14.5.3.4.7 receive buffer descriptor po inter register (rbptr) .................................... 14-43 14.5.3.4.8 receive descriptor base a ddress register (rbase)..................................... 14-44 14.5.3.5 mac functional ity.............................................................................................. 14-44 14.5.3.5.1 configuring th e mac...................................................................................... 14-44 14.5.3.5.2 controlling cs ma/cd.................................................................................... 14-44 14.5.3.5.3 handling packet collisions ............................................................................. 14-45 14.5.3.5.4 controlling pack et flow.................................................................................. 14-45 14.5.3.5.5 controlling ph y links.................................................................................... 14-46 14.5.3.6 mac register s .................................................................................................... 14-46 14.5.3.6.1 mac configuration regi ster 1 (maccfg1)................................................. 14-47 14.5.3.6.2 mac configuration regi ster 2 (maccfg2)................................................. 14-48 14.5.3.6.3 inter-packet gap/inter-fram e gap register (ipgifg) ................................... 14-49 14.5.3.6.4 half-duplex regist er (hafdup) ................................................................... 14-50 14.5.3.6.5 maximum frame length re gister (max frm) ............................................. 14-51 14.5.3.6.6 mii management configurat ion register (miimcfg) .................................. 14-52 14.5.3.6.7 mii management command register (miimcom)....................................... 14-53 14.5.3.6.8 mii management address register (miimadd)........................................... 14-53 14.5.3.6.9 mii management control register (miimcon)............................................ 14-54 14.5.3.6.10 mii management status register (miimstat) ............................................. 14-55 14.5.3.6.11 mii management indicator register (miimind)........................................... 14-55 14.5.3.6.12 interface status regi ster (ifstat).................................................................. 14-56 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 xxvi freescale semiconductor contents paragraph number title page number 14.5.3.6.13 station address register part 1 (macstnaddr1) ..................................... 14-56 14.5.3.6.14 station address register part 2 (macstnaddr2) ..................................... 14-57 14.5.3.7 mib register s...................................................................................................... 14-5 8 14.5.3.7.1 transmit and receive 64-byte fr ame counter register (tr64) .................... 14-58 14.5.3.7.2 transmit and receive 65- to 127-byte frame counter register (tr127) ....................................................................................................... 14-58 14.5.3.7.3 transmit and receive 128- to 255-byte frame counter register (tr255) ....................................................................................................... 14-59 14.5.3.7.4 transmit and receive 256- to 511-byte frame counter register (tr511)........................................................................................................ 14-59 14.5.3.7.5 transmit and receive 512- to 1023-byte frame counter register (tr1k) ........................................................................................................ 14-60 14.5.3.7.6 transmit and receive 1024- to 1518-byte frame counter register (trmax) .................................................................................................... 14-60 14.5.3.7.7 transmit and receive 1519- to 1522-byte vlan frame counter register (trmgv)...................................................................................... 14-61 14.5.3.7.8 receive byte counter register (rby t) ......................................................... 14-61 14.5.3.7.9 receive packet counter register (rpkt)....................................................... 14-62 14.5.3.7.10 receive fcs error counter register (rfcs) ................................................. 14-62 14.5.3.7.11 receive multicast packet counter regi ster (rmca) ..................................... 14-63 14.5.3.7.12 receive broadcast packet c ounter register (rbca) ..................................... 14-63 14.5.3.7.13 receive control frame packet counter register (rxcf) .............................. 14-64 14.5.3.7.14 receive pause frame packet counter register (rxpf) ................................. 14-64 14.5.3.7.15 receive unknown opcode packet counter register (rxuo) ....................... 14-65 14.5.3.7.16 receive alignment error c ounter register (raln) ...................................... 14-65 14.5.3.7.17 receive frame length error c ounter register (rflr) ................................. 14-66 14.5.3.7.18 receive code error count er register (rcde) ............................................... 14-66 14.5.3.7.19 receive carrier sense error counter register (rcse) .................................. 14-67 14.5.3.7.20 receive undersize packet c ounter register (rund) .................................... 14-67 14.5.3.7.21 receive oversize packet c ounter register (rovr) ...................................... 14-68 14.5.3.7.22 receive fragme nts counter register (rfrg) ................................................ 14-68 14.5.3.7.23 receive jabber counter register (rjbr) ....................................................... 14-69 14.5.3.7.24 receive dropped packet c ounter register (rdrp) ....................................... 14-69 14.5.3.7.25 transmit byte counter register (tby t) ........................................................ 14-70 14.5.3.7.26 transmit packet counter register (tpkt) ..................................................... 14-70 14.5.3.7.27 transmit multicast packet counter register (tmca).................................... 14-71 14.5.3.7.28 transmit broadcast packet counter register (tbca).................................... 14-71 14.5.3.7.29 transmit pause control frame counter register (txpf) .............................. 14-72 14.5.3.7.30 transmit deferral packet counter register (tdfr)....................................... 14-72 14.5.3.7.31 transmit excessive deferral pack et counter register (tedf) ...................... 14-73 14.5.3.7.32 transmit single collision packet counter register (tscl)........................... 14-73 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor xxvii contents paragraph number title page number 14.5.3.7.33 transmit multiple collision pack et counter regist er (tmcl)...................... 14-74 14.5.3.7.34 transmit late collision packet counter register (tlcl).............................. 14-74 14.5.3.7.35 transmit excessive collision pack et counter regist er (txcl) .................... 14-75 14.5.3.7.36 transmit total collision c ounter register (tncl)........................................ 14-75 14.5.3.7.37 transmit drop frame count er register (tdrp) ............................................ 14-76 14.5.3.7.38 transmit jabber frame count er register (tjbr) ........................................... 14-76 14.5.3.7.39 transmit fcs error count er register (tfcs) ................................................ 14-77 14.5.3.7.40 transmit control frame co unter register (txcf) ........................................ 14-77 14.5.3.7.41 transmit oversize frame c ounter register (tovr)...................................... 14-78 14.5.3.7.42 transmit undersize frame c ounter register (tund) ................................... 14-78 14.5.3.7.43 transmit fragment count er register (tfrg) ................................................ 14-79 14.5.3.7.44 carry register 1 (car1)................................................................................. 14-79 14.5.3.7.45 carry register 2 (car2)................................................................................. 14-80 14.5.3.7.46 carry mask regist er 1 (cam1) ...................................................................... 14-82 14.5.3.7.47 carry mask regist er 2 (cam2) ...................................................................... 14-83 14.5.3.8 hash function registers ...................................................................................... 14-84 14.5.3.8.1 individual addre ss registers 0?7 (iaddr n ) ................................................. 14-84 14.5.3.8.2 group address registers 0?7 (gaddr n ) ...................................................... 14-85 14.5.3.9 attribute regist ers ............................................................................................... 14-85 14.5.3.9.1 attribute regist er (attr)............................................................................... 14-85 14.5.3.9.2 attribute extract length and extract index register (attreli) .................. 14-87 14.5.4 ten-bit interface (tbi) ............................................................................................ 14-87 14.5.4.1 tbi mii set register descriptions ...................................................................... 14-87 14.5.4.2 control register (cr).......................................................................................... 14-88 14.5.4.3 status register (sr) ........................................................................................... 14-89 14.5.4.4 an advertisement re gister (ana) .................................................................... 14-90 14.5.4.5 an link partner base page abil ity register (anlpbpa)................................. 14-92 14.5.4.6 an expansion regist er (anex)......................................................................... 14-93 14.5.4.7 an next page transmit register (annpt)........................................................ 14-94 14.5.4.8 an link partner ability next pa ge register (anlpanp) ................................ 14-95 14.5.4.9 extended status regi ster (exst)........................................................................ 14-96 14.5.4.10 jitter diagnostics re gister (jd) ........................................................................... 14-97 14.5.4.11 tbi control regist er (tbicon)......................................................................... 14-98 14.6 functional descri ption................................................................................................. 14-9 9 14.6.1 connecting to physi cal interfaces............................................................................ 14-99 14.6.1.1 media-independent inte rface (mii)................................................................... 14-100 14.6.1.2 gigabit media-independent interface (gmi i) ................................................... 14-100 14.6.1.3 reduced gigabit media-indepe ndent interface (rgmii) ................................. 14-101 14.6.1.4 ten-bit interfa ce (tbi)...................................................................................... 14-102 14.6.1.5 reduced ten-bit interface (rtbi) .................................................................... 14-103 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 xxviii freescale semiconductor contents paragraph number title page number 14.6.2 gigabit ethernet cha nnel operation...................................................................... 14-107 14.6.2.1 initialization se quence....................................................................................... 14-107 14.6.2.1.1 hardware controlled initializatio n ................................................................ 14-107 14.6.2.1.2 user initiali zation .......................................................................................... 14-107 14.6.2.2 soft reset and reconfi guring procedur e........................................................... 14-108 14.6.2.3 gigabit ethernet fram e transmission ............................................................... 14-109 14.6.2.4 gigabit ethernet fram e reception .................................................................... 14-110 14.6.2.5 rmon support ...................................................................................................14-111 14.6.2.6 frame recognition............................................................................................. 14-112 14.6.2.6.1 destination address recognition .................................................................. 14-112 14.6.2.6.2 hash table al gorithm.................................................................................... 14-114 14.6.2.6.3 crc computation ex amples ........................................................................ 14-114 14.6.2.7 flow control...................................................................................................... 14-11 5 14.6.2.8 interrupt handlin g ............................................................................................. 14-116 14.6.2.8.1 interrupt coales cing ...................................................................................... 14-117 14.6.2.8.2 interrupt coalescing by fr ame count threshold.......................................... 14-117 14.6.2.8.3 interrupt coalescing by timer threshold ..................................................... 14-117 14.6.2.9 inter-packet gap time....................................................................................... 14-118 14.6.2.10 internal and extern al loopback......................................................................... 14-118 14.6.2.11 error-handling pr ocedure.................................................................................. 14-119 14.6.3 buffer descriptors.................................................................................................. 14-12 0 14.6.3.1 transmit data buffer de scriptor (txbd).......................................................... 14-121 14.6.3.2 receive buffer descri ptor (rxbd) ................................................................... 14-123 14.6.4 data extraction to th e l2 cache............................................................................ 14-125 14.7 initialization/applicati on informatio n ....................................................................... 14-126 14.7.1 interface mode conf iguration ............................................................................... 14-126 14.7.1.1 mii interface mode............................................................................................ 14-126 14.7.1.2 gmii interface mode......................................................................................... 14-129 14.7.1.3 tbi interface mode ........................................................................................... 14-133 14.7.1.4 rgmii interface mode ...................................................................................... 14-137 14.7.1.5 rtbi interface mode ......................................................................................... 14-140 chapter 15 dma controller 15.1 introducti on............................................................................................................... ..... 15-1 15.1.1 block diagra m........................................................................................................... 1 5-1 15.1.2 overview................................................................................................................. ... 15-2 15.1.3 features................................................................................................................. ..... 15-2 15.1.4 modes of operat ion ................................................................................................... 15-2 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor xxix contents paragraph number title page number 15.2 external signal desc ription ........................................................................................... 15-4 15.2.1 signal over view ........................................................................................................ 15 -5 15.2.2 detailed signal de scriptions ..................................................................................... 15-5 15.3 memory map/register definition ................................................................................. 15-6 15.3.1 module memory map................................................................................................ 15-6 15.3.2 dma register desc riptions....................................................................................... 15-8 15.3.2.1 mode registers (mr n ) .......................................................................................... 15-9 15.3.2.2 status registers (sr n ) ......................................................................................... 15-11 15.3.2.3 current link descriptor address registers (clndar n )................................... 15-12 15.3.2.4 source attributes registers (satr n ).................................................................. 15-14 15.3.2.5 source address registers (sar n )....................................................................... 15-15 15.3.2.6 destination attributes registers (datr n ).......................................................... 15-16 15.3.2.7 destination address registers (dar n )............................................................... 15-16 15.3.2.8 byte count registers (bcr n ) ............................................................................. 15-17 15.3.2.9 next link descriptor a ddress registers (nlndar n )....................................... 15-17 15.3.2.10 current list descriptor address registers (clsdar n )..................................... 15-18 15.3.2.11 next list descriptor address regist ers (nlsdar n )......................................... 15-19 15.3.2.12 source stride registers (ssr n ) ........................................................................... 15-19 15.3.2.13 destination stride registers (dsr n ) ................................................................... 15-20 15.3.2.14 dma general status re gister (dgsr) ............................................................... 15-21 15.4 functional descri ption................................................................................................. 15-2 2 15.4.1 dma channel oper ation......................................................................................... 15-22 15.4.1.1 basic dma mode transfer ................................................................................. 15-23 15.4.1.1.1 basic direct mode ........................................... ................................................ 15-23 15.4.1.1.2 basic direct single-wr ite start mode ............................................................. 15-23 15.4.1.1.3 basic chaini ng mode ...................................................................................... 15-24 15.4.1.1.4 basic chaining single-wr ite start mode ........................................................ 15-25 15.4.1.2 extended dma mode transfer ........................................................................... 15-25 15.4.1.2.1 extended direct mode..................................................................................... 15-25 15.4.1.2.2 extended direct single- write start mode....................................................... 15-25 15.4.1.2.3 extended chaini ng mode ................................................................................ 15-25 15.4.1.2.4 extended chaining single-w rite start mode .................................................. 15-26 15.4.1.3 external control m ode transfer.......................................................................... 15-26 15.4.1.4 channel continue mode for ca scading transfer chains .................................... 15-28 15.4.1.4.1 basic mode ...................................................................................................... 15-28 15.4.1.4.2 extended mo de................................................................................................ 15-28 15.4.1.5 channel abort...................................................................................................... 15-2 8 15.4.1.6 bandwidth cont rol............................................... ................................................ 15-29 15.4.1.7 channel state ....................................................................................................... 15- 29 15.4.1.8 illustration of stride size and stride distance..................................................... 15-29 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 xxx freescale semiconductor contents paragraph number title page number 15.4.2 dma transfer inte rfaces ......................................... ................................................ 15-30 15.4.3 dma errors ............................................................................................................. 15 -30 15.4.4 dma descriptor s..................................................................................................... 15-30 15.4.5 limitations and re strictions .................................................................................... 15-33 15.5 dma system considerations ...................................................................................... 15-34 15.5.1 unusual dma scen arios ......................................................................................... 15-36 15.5.1.1 dma to core ....................................................................................................... 15-36 15.5.1.2 dma to cpm ...................................................................................................... 15-36 15.5.1.3 dma to ethernet ................................................................................................. 15-36 15.5.1.4 dma to configuration and control registers..................................................... 15-37 15.5.1.5 dma to i 2 c ......................................................................................................... 15-37 15.5.1.6 dma to duart ................................................................................................. 15-37 chapter 16 pci bus interface 16.1 introducti on............................................................................................................... ..... 16-1 16.1.1 overview................................................................................................................. ... 16-2 16.1.1.1 MPC8555E as a pci initiator ................................................................................ 16-3 16.1.1.2 MPC8555E as a pci target ................................................................................... 16-4 16.1.2 features................................................................................................................. ..... 16-4 16.1.3 modes of operat ion ................................................................................................... 16-4 16.1.3.1 host/agent mode c onfiguration ........................................................................... 16-5 16.1.3.1.1 host m ode ......................................................................................................... 16- 5 16.1.3.1.2 agent mode ....................................................................................................... 16-5 16.1.3.1.3 agent configurati on lock mode ...................................................................... 16-5 16.1.3.2 pci-64 or two pci-32 interf ace configura tion .................................................... 16-5 16.1.3.3 pci clocking confi guration .................................................................................. 16-6 16.1.3.4 pci arbiter (internal/external arbiter) confi guration.......................................... 16-6 16.1.3.5 pci signal output hold configuratio n ................................................................. 16-6 16.1.3.6 pci impedance conf iguration ............................................................................... 16-6 16.1.3.7 pci debug configur ation .................................... .................................................. 16-6 16.2 external signal de scriptions ......................................................................................... 16-7 16.3 memory map/register definitions .............................................................................. 16-14 16.3.1 pci memory mapped registers .............................................................................. 16-14 16.3.1.1 pci configuration acce ss registers ................................................................... 16-17 16.3.1.1.1 pci configurati on address register (cfg_addr) ...................................... 16-17 16.3.1.1.2 pci configuration data register (cfg_data)............................................. 16-18 16.3.1.1.3 pci interrupt acknowledge register (int_ack).......................................... 16-19 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor xxxi contents paragraph number title page number 16.3.1.2 pci atmu outbound registers.......................................................................... 16-19 16.3.1.2.1 pci outbound translati on address registers (potar n ) .............................. 16-20 16.3.1.2.2 pci outbound translation exte nded address registers (potear n )............ 16-20 16.3.1.2.3 pci outbound window base address registers (powbar n )...................... 16-21 16.3.1.2.4 pci outbound window attr ibutes registers (powar n )............................... 16-22 16.3.1.3 pci atmu inbound re gisters............................................................................. 16-23 16.3.1.3.1 pci inbound translation address registers (pitar n )................................... 16-24 16.3.1.3.2 pci inbound window base a ddress registers (piwbar n ) .......................... 16-25 16.3.1.3.3 pci inbound window base extend ed address registers (piwbear n )........ 16-26 16.3.1.3.4 pci inbound window attributes registers (piwar n ) ................................... 16-26 16.3.1.4 pci error management registers........................................................................ 16-28 16.3.1.4.1 pci error detect regi ster (err_d r)............................................................. 16-29 16.3.1.4.2 pci error capture disable register (err_cap_dr).................................... 16-30 16.3.1.4.3 pci error enable regi ster (err_en) ............................................................ 16-31 16.3.1.4.4 pci error attributes captur e register (err_attrib) ................................. 16-32 16.3.1.4.5 pci error address capture register (err_addr)....................................... 16-33 16.3.1.4.6 pci error extended address captur e register (err_ext_addr)............. 16-33 16.3.1.4.7 pci error data low captur e register (err_dl) .......................................... 16-33 16.3.1.4.8 pci error data high captur e register (err_dh)......................................... 16-34 16.3.1.4.9 pci gasket timer regi ster (gas_tim r) ...................................................... 16-35 16.3.2 pci configuratio n header ....................................................................................... 16-35 16.3.2.1 pci vendor id regist er?offset 0x00 ................................................................ 16-36 16.3.2.2 pci device id regist er?offset 0x02 ................................................................ 16-37 16.3.2.3 pci bus command regist er?offset 0x04 ......................................................... 16-37 16.3.2.4 pci bus status regist er?offset 0x06 ................................................................ 16-38 16.3.2.5 pci revision id regist er?offset 0x08 ............................................................. 16-40 16.3.2.6 pci bus programming interface register?offset 0x09 .................................... 16-40 16.3.2.7 pci subclass code regist er?offset 0x0a......................................................... 16-41 16.3.2.8 pci bus base class code register?offset 0x0b .............................................. 16-41 16.3.2.9 pci bus cache line size register?offset 0x0c............................................... 16-41 16.3.2.10 pci bus latency time r register? 0x0d ............................................................ 16-42 16.3.2.11 pci base address registers ................................................................................ 16-42 16.3.2.12 pci subsystem vendor id register ..................................................................... 16-45 16.3.2.13 pci subsystem id register ................................................................................. 16-45 16.3.2.14 pci bus capabilities pointer register................................................................. 16-46 16.3.2.15 pci bus interrupt li ne register .......................................................................... 16-46 16.3.2.16 pci bus interrupt pin register ............................................................................ 16-46 16.3.2.17 pci bus minimum grant (m in gnt) regi ster.................................................. 16-47 16.3.2.18 pci bus maximum latency (max lat) register............................................. 16-47 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 xxxii freescale semiconductor contents paragraph number title page number 16.3.2.19 pci bus function regi ster (pbfr)..................................................................... 16-48 16.3.2.20 pci bus arbiter configurat ion register (pbacr)............................................. 16-48 16.4 functional descri ption................................................................................................. 16-4 9 16.4.1 pci bus arbitrat ion ................................................................................................. 16-49 16.4.1.1 pci bus arbiter operation .................................................................................. 16-50 16.4.1.2 pci bus parking .................................................................................................. 16-51 16.4.1.3 broken master lo ck-out..................................................................................... 16-51 16.4.1.4 power-saving modes and the pci arbiter .......................................................... 16-52 16.4.2 pci bus protoc ol ..................................................................................................... 16-5 2 16.4.2.1 basic transfer c ontrol......................................................................................... 16-52 16.4.2.2 pci bus comma nds............................................................................................. 16-53 16.4.2.3 addressing ........................................................................................................... 16 -54 16.4.2.3.1 memory space addressing.............................................................................. 16-54 16.4.2.3.2 i/o space addressing ...................................................................................... 16-55 16.4.2.3.3 configuration spa ce addressing ..................................................................... 16-55 16.4.2.4 device selectio n .................................................................................................. 16-55 16.4.2.5 byte alignmen t.................................................................................................... 16-56 16.4.2.6 bus driving and turnaround ............................................................................... 16-56 16.4.2.7 pci bus transact ions........................................................................................... 16-57 16.4.2.7.1 pci read tran sactions .................................................................................... 16-57 16.4.2.7.2 pci write tran sactions.................................................................................... 16-58 16.4.2.8 transaction termination ...................................................................................... 16-59 16.4.2.8.1 master-initiated termination ........................................................................... 16-59 16.4.2.8.2 target-initiated termination ............................................................................ 16-60 16.4.2.9 fast back-to-back transactions .......................................................................... 16-63 16.4.2.10 dual address cy cles............................................................................................ 16-63 16.4.2.11 configuration cy cles ........................................................................................... 16-65 16.4.2.11.1 pci configuration space header .................................................................... 16-65 16.4.2.11.2 accessing the pci configurat ion space in host mode................................... 16-67 16.4.2.11.3 pci configuration in agent and agent lock modes ...................................... 16-68 16.4.2.11.4 pci type 0 configurat ion translation............................................................. 16-69 16.4.2.11.5 pci type 1 configurat ion translation............................................................. 16-70 16.4.2.12 other bus trans actions........................................................................................ 16-71 16.4.2.12.1 interrupt-acknowledge transactions .............................................................. 16-71 16.4.2.12.2 special-cycle tr ansactions ............................................................................. 16-71 16.4.2.13 pci error func tions............................................................................................. 16-72 16.4.2.13.1 pci pari ty ........................................................................................................ 16 -72 16.4.2.13.2 error reporti ng................................................................................................ 16-73 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor xxxiii contents paragraph number title page number 16.5 initialization/applicati on informatio n ......................................................................... 16-75 16.5.1 power-on reset confi guration modes.................................................................... 16-75 16.5.1.1 host mode ........................................................................................................... 16- 76 16.5.1.2 agent mode ......................................................................................................... 16-7 6 16.5.1.3 agent configuration lock mode......................................................................... 16-76 16.5.2 extended 64-bit pci1 si gnal connections.............................................................. 16-76 chapter 17 security engine (sec) 2.0 17.1 architecture ov erview.................................................................................................. 17- 2 17.1.1 data packet desc riptors............................................................................................. 17-4 17.1.2 execution units (eus) ............................................. .................................................. 17-5 17.1.2.1 public key execution unit (pkeu) ...................................................................... 17-5 17.1.2.1.1 elliptic curve operations .................................................................................. 17-5 17.1.2.1.2 modular exponentiati on operations ................................................................. 17-6 17.1.2.2 data encryption standard execution unit (deu)................................................. 17-6 17.1.2.3 arc four execution un it (afeu) ....................................................................... 17-6 17.1.2.4 advanced encryption standard execution unit (aesu)...................................... 17-7 17.1.2.5 message digest executi on unit (mdeu) ............................................................. 17-7 17.1.2.6 random number genera tor (rng)....................................................................... 17-7 17.1.3 crypto-channe ls ........................................................................................................ 17 -8 17.1.4 sec controller........................................................................................................... 17-9 17.1.4.1 host-controlled access ......................................................................................... 17-9 17.1.4.2 dynamic eu access .............................................................................................. 17-9 17.1.5 bus interface ............................................................................................................ .. 17-9 17.2 configuration of intern al memory space .................................................................... 17-10 17.3 descriptor over view.................................................................................................... 17-1 4 17.3.1 descriptor stru cture ................................................................................................. 17-1 5 17.3.2 descriptor format?h eader dword ........................................................................ 17-15 17.3.2.1 selecting execution units? eu_sel0 and eu_sel1....................................... 17-16 17.3.2.2 selecting descriptor type?desc_type ......................................................... 17-17 17.3.3 descriptor format?poi nter dwords....................................................................... 17-18 17.3.4 link table fo rmat ................................................................................................... 17-19 17.3.4.1 link table exam ple............................................................................................. 17-21 17.3.5 descriptor t ypes ...................................................................................................... 17- 23 17.4 execution un its............................................................................................................ 17-24 17.4.1 public key execution unit (pkeu) ........................................................................ 17-24 17.4.1.1 pkeu mode register (pkeumr)...................................................................... 17-25 17.4.1.2 pkeu key size register (pkeuksr) ............................................................... 17-26 17.4.1.3 pkeu ab size register (pkeuabs) ................................................................ 17-26 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 xxxiv freescale semiconductor contents paragraph number title page number 17.4.1.4 pkeu data size regi ster (pkeudsr) .............................................................. 17-27 17.4.1.5 pkeu reset control regi ster (pkeurcr) ....................................................... 17-28 17.4.1.6 pkeu status regist er (pkeusr)....................................................................... 17-29 17.4.1.7 pkeu interrupt status re gister (pkeuisr)....................................................... 17-30 17.4.1.8 pkeu interrupt control re gister (pkeui cr).................................................... 17-31 17.4.1.9 pkeu eu-go register (pkeueug).................................................................. 17-32 17.4.1.10 pkeu parameter memories ................................................................................ 17-32 17.4.1.10.1 pkeu parameter memory a........................................................................... 17-32 17.4.1.10.2 pkeu parameter memory b ........................................................................... 17-32 17.4.1.10.3 pkeu parameter memory e ........................................................................... 17-33 17.4.1.10.4 pkeu parameter memory n........................................................................... 17-33 17.4.2 data encryption standard ex ecution unit (deu)................................................... 17-33 17.4.2.1 deu mode register (deumr) .......................................................................... 17-33 17.4.2.2 deu key size register (deuksr).................................................................... 17-34 17.4.2.3 deu data size regist er (deudsr)................................................................... 17-35 17.4.2.4 deu reset control register (deurcr)............................................................ 17-36 17.4.2.5 deu status register (deusr) ........................................................................... 17-37 17.4.2.6 deu interrupt status re gister (deuis r) ........................................................... 17-38 17.4.2.7 deu interrupt control re gister (deuic r) ........................................................ 17-39 17.4.2.8 deu eu-go register (deueug) ...................................................................... 17-41 17.4.2.9 deu iv register (deuiv) ................................................................................. 17-41 17.4.2.10 deu key registers (d euk1?deuk3).............................................................. 17-41 17.4.2.11 deu fifos.......................................................................................................... 17- 42 17.4.3 arc four execution un it (afeu) ......................................................................... 17-42 17.4.3.1 afeu mode register (afeumr)...................................................................... 17-42 17.4.3.2 host-provided context thro ugh prevent permute .............................................. 17-42 17.4.3.2.1 dump contex t.................................................................................................. 17-42 17.4.3.3 afeu key size register (afeuksr) ............................................................... 17-43 17.4.3.4 afeu context/data size register (afeudsr) ................................................ 17-44 17.4.3.5 afeu reset control regi ster (afeurcr) ....................................................... 17-45 17.4.3.6 afeu status regist er (afeusr)....................................................................... 17-46 17.4.3.7 afeu interrupt status re gister (afeuisr)....................................................... 17-47 17.4.3.8 afeu interrupt control re gister (afeui cr).................................................... 17-48 17.4.3.9 afeu end of message regi ster (afeuemr) ................................................... 17-50 17.4.3.10 afeu contex t ..................................................................................................... 17-50 17.4.3.10.1 afeu context memory .................................................................................. 17-50 17.4.3.10.2 afeu context memory po inter registers ...................................................... 17-51 17.4.3.11 afeu key registers (a feuk0, afeuk1) ....................................................... 17-51 17.4.3.11.1 afeu fifo s.................................................................................................... 17-51 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor xxxv contents paragraph number title page number 17.4.4 message digest executi on unit (mdeu) ............................................................... 17-51 17.4.4.1 mdeu mode register (mdeumr) ................................................................... 17-51 17.4.4.2 recommended settings for mdeumr............................................................... 17-52 17.4.4.3 mdeu key size regist er (mdeuksr) ............................................................ 17-53 17.4.4.4 mdeu data size regist er (mdeudsr )............................................................ 17-54 17.4.4.5 mdeu reset control regi ster (mdeurcr)..................................................... 17-54 17.4.4.6 mdeu status regist er (mdeusr) .................................................................... 17-55 17.4.4.7 mdeu interrupt status re gister (mdeui sr).................................................... 17-56 17.4.4.8 mdeu interrupt control re gister (mdeuicr)................................................. 17-57 17.4.4.9 mdeu eu-go register (mdeueug) ............................................................... 17-58 17.4.4.10 mdeu context re gisters .................................................................................... 17-59 17.4.4.11 mdeu key regist ers .......................................................................................... 17-60 17.4.4.12 mdeu fifos ...................................................................................................... 17-60 17.4.5 random number genera tor (rng)......................................................................... 17-61 17.4.5.1 rng mode register (rngmr).......................................................................... 17-61 17.4.5.2 rng data size regist er (rngdsr) .................................................................. 17-62 17.4.5.3 rng reset control regi ster (rngrcr) ........................................................... 17-63 17.4.5.4 rng status register (rngsr)........................................................................... 17-63 17.4.5.5 rng interrupt status re gister (rngisr)........................................................... 17-64 17.4.5.6 rng interrupt control re gister (rngicr)........................................................ 17-65 17.4.5.7 rng eu-go register (rngeug)...................................................................... 17-66 17.4.5.8 rng fifo ........................................................................................................... 17-6 6 17.4.6 advanced encryption standard execution unit (aesu)........................................ 17-67 17.4.6.1 aesu mode register (aesumr)...................................................................... 17-67 17.4.6.2 aesu key size register (aesuksr) ............................................................... 17-69 17.4.6.3 aesu data size regi ster (aesudsr) .............................................................. 17-70 17.4.6.4 aesu reset control regi ster (aesurcr) ....................................................... 17-70 17.4.6.5 aesu status regist er (aesusr)....................................................................... 17-71 17.4.6.6 aesu interrupt status re gister (aesuisr)....................................................... 17-72 17.4.6.7 aesu interrupt control re gister (aesui cr).................................................... 17-73 17.4.6.8 aesu end of message regi ster (aesuemr) ................................................... 17-75 17.4.6.9 aesu context re gisters ..................................................................................... 17-75 17.4.6.9.1 context for cbc mode.................................................................................... 17-76 17.4.6.9.2 context for count er mode............................................................................... 17-76 17.4.6.9.3 context for sr t mode .................................................................................... 17-77 17.4.6.9.4 context for ccm mode................................................................................... 17-77 17.4.6.9.5 aesu key regi sters ....................................................................................... 17-79 17.4.6.9.6 aesu fifo s.................................................................................................... 17-80 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 xxxvi freescale semiconductor contents paragraph number title page number 17.5 crypto-channe ls .......................................................................................................... 17 -80 17.5.1 crypto-channel re gisters........................................................................................ 17-81 17.5.1.1 crypto-channel configurati on register (cccr) ............................................... 17-81 17.5.1.2 crypto-channel pointer status register (ccpsr).............................................. 17-83 17.5.1.3 crypto-channel current descriptor pointer register (cdpr) ........................... 17-89 17.5.1.4 fetch fifo (ff)................................................................................................... 17-90 17.5.1.5 descriptor buffer (db)........................................................................................ 17-90 17.5.2 interrupts............................................................................................................... ... 17-91 17.5.2.1 channel done interrupt ....................................................................................... 17-91 17.5.2.2 channel error interrupt........................................................................................ 17-91 17.5.2.3 channel reset ...................................................................................................... 17-9 2 17.6 sec controller............................................................................................................. 17-92 17.6.1 controller regi sters ................................................................................................. 17-9 2 17.6.2 eu assignment status re gister (euasr ) .............................................................. 17-92 17.6.2.1 interrupt mask register (imr)............................................................................ 17-93 17.6.2.2 interrupt status regi ster (isr) ............................................................................ 17-94 17.6.2.3 interrupt clear regi ster (icr) ............................................................................. 17-95 17.6.2.4 id register........................................................................................................... 1 7-97 17.6.2.5 master control regi ster (mcr) .......................................................................... 17-98 17.6.2.6 eu access ............................................................................................................ 17 -99 17.6.2.7 multiple eu a ssignment ..................................................................................... 17-99 17.6.2.8 multiple chan nels................................................................................................ 17-99 17.6.2.9 priority arbitr ation ............................................................................................ 17-100 17.6.2.10 round-robin snapshot arbiters........................................................................ 17-100 17.7 bus interface .............................................................................................................. 17-100 17.7.1 bus access ............................................................................................................. 17 -101 17.7.1.1 master read ....................................................................................................... 17-10 1 17.7.1.1.1 slave abor ts .................................................................................................. 17-101 17.7.1.2 master writ e ...................................................................................................... 17-10 2 17.7.1.2.1 slave access .................................................................................................. 17-102 17.7.2 bus arbitration priority ........................................................................................ 17-102 17.7.3 snooping by cach es............................................................................................... 17-102 17.7.4 interrupts............................................................................................................... . 17-102 17.8 power-saving mode................................................................................................... 17-103 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor xxxvii contents paragraph number title page number part iv global functions and debug chapter 18 global utilities 18.1 overview................................................................................................................... ..... 18-1 18.2 global utilities features ................................................................................................ 18 -1 18.2.1 power management and block disabl es ................................................................... 18-1 18.2.2 accessing current por conf iguration sett ings........................................................ 18-1 18.2.3 general-purpose i/o .................................................................................................. 18-1 18.2.4 interrupt and local bus si gnal multiplexing ............................................................ 18-1 18.2.5 clock cont rol............................................................................................................ . 18-2 18.3 external signal desc ription ........................................................................................... 18-2 18.3.1 signals over view....................................................................................................... 18 -2 18.3.2 detailed signal de scriptions ..................................................................................... 18-2 18.4 memory map/register definition ................................................................................. 18-3 18.4.1 register descri ptions................................................................................................. 18- 4 18.4.1.1 por pll status regist er (porpllsr) ............................................................... 18-4 18.4.1.2 por boot mode status re gister (porbm sr)..................................................... 18-5 18.4.1.3 por i/o impedance status and c ontrol register (porimpscr) ....................... 18-6 18.4.1.4 por device status regist er (pordevsr).......................................................... 18-7 18.4.1.5 por debug mode status regi ster (pordbgmsr) ............................................ 18-8 18.4.1.6 general-purpose por configurat ion register (gpporcr) ................................ 18-9 18.4.1.7 general-purpose i/o contro l register (gpiocr) .............................................. 18-10 18.4.1.8 general-purpose output data register (gpoutdr)......................................... 18-11 18.4.1.9 general-purpose input data register (gpindr)................................................ 18-12 18.4.1.10 alternate function signal multiple x control register (pmuxcr) ................... 18-13 18.4.1.11 device disable regist er (devdisr) ................................................................. 18-14 18.4.1.12 power management control and st atus register (p owmgtcsr).................... 18-16 18.4.1.13 machine check summary re gister (mcpsumr).............................................. 18-17 18.4.1.14 processor version regi ster (pvr)....................................................................... 18-18 18.4.1.15 system version regi ster (svr)........................................................................... 18-19 18.4.1.16 clock out control regi ster (clkocr) ............................................................. 18-19 18.4.1.17 local bus dll control re gister (lbdllcr)................................................... 18-20 18.5 functional descri ption................................................................................................. 18-2 1 18.5.1 power manageme nt ................................................................................................. 18-21 18.5.1.1 relationship between core and devi ce power management states................... 18-21 18.5.1.2 ckstp_in is not power management............................................................... 18-22 18.5.1.3 dynamic power management.............................................................................. 18-23 18.5.1.4 shutting down unus ed blocks............................................................................ 18-23 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 xxxviii freescale semiconductor contents paragraph number title page number 18.5.1.5 software-controlled powe r-down states............................................................ 18-23 18.5.1.5.1 doze mode ...................................................................................................... 18-23 18.5.1.5.2 nap mode ........................................................................................................ 18-24 18.5.1.5.3 sleep mode ...................................................................................................... 18-24 18.5.1.6 power management co ntrol fields ..................................................................... 18-24 18.5.1.7 power-down sequence coordination.................................................................. 18-25 18.5.1.8 interrupts and power management...................................................................... 18-27 18.5.1.8.1 interrupts and power management controlled by msr[we] ........................ 18-27 18.5.1.8.2 interrupts and power management controlled by powmgtcsr................. 18-27 18.5.1.9 snooping in power-down modes........................................................................ 18-27 18.5.1.10 software considerations for power management ............................................... 18-28 18.5.1.11 requirements for reaching and r ecovering from sleep state............................ 18-28 18.5.2 general-purpose i/ o signals ................................................................................... 18-28 18.5.3 interrupt and local bus si gnal multiplexing .......................................................... 18-29 chapter 19 performance monitor 19.1 introducti on............................................................................................................... ..... 19-1 19.1.1 overview................................................................................................................. ... 19-1 19.1.2 features................................................................................................................. ..... 19-3 19.2 signal descri ptions ........................................................................................................ 19-3 19.3 memory map and regist er definition........................................................................... 19-3 19.3.1 register su mmary...................................................................................................... 19- 3 19.3.2 control registers ....................................................................................................... 1 9-5 19.3.2.1 performance monitor global cont rol register (pmgc0) .................................... 19-5 19.3.2.2 performance monitor local control registers (pmlca n , pmlcb n )................. 19-5 19.3.3 counter regist ers....................................................................................................... 1 9-9 19.3.3.1 performance monitor count ers (pmc0?pmc 8)................................................... 19-9 19.4 functional descri ption................................................................................................. 19-1 0 19.4.1 performance monito r interrupt................................................................................ 19-10 19.4.2 event countin g ........................................................................................................ 19- 10 19.4.3 threshold even ts ..................................................................................................... 19-1 1 19.4.4 chaining................................................................................................................. .. 19-12 19.4.5 triggering ............................................................................................................... . 19-12 19.4.6 burstiness count ing................................................................................................. 19-13 19.4.7 performance monito r events ................................................................................... 19-15 19.4.8 performance monito r examples .............................................................................. 19-25 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor xxxix contents paragraph number title page number chapter 20 debug features and watchpoint facility 20.1 introducti on............................................................................................................... ..... 20-1 20.1.1 overview................................................................................................................. ... 20-1 20.1.2 features................................................................................................................. ..... 20-2 20.1.3 modes of operat ion ................................................................................................... 20-3 20.1.3.1 local bus (lbc) debug mode.............................................................................. 20-4 20.1.3.2 ddr sdram interface debug modes................................................................. 20-4 20.1.3.3 pci interface de bug modes .................................................................................. 20-4 20.1.3.4 watchpoint monito r modes ................................................................................... 20-4 20.1.3.5 trace buffer m odes ............................................. .................................................. 20-4 20.2 external signal desc ription ........................................................................................... 20-5 20.2.1 overview................................................................................................................. ... 20-5 20.2.2 detailed signal de scriptions ..................................................................................... 20-7 20.2.2.1 debug signals?det ails......................................................................................... 20-7 20.2.2.2 watchpoint monitor trigge r signals?details ...................................................... 20-8 20.2.2.3 test signals?det ails............................................................................................. 20-8 20.3 memory map/register definition ............................................................................... 20-10 20.3.1 watchpoint monitor regist er descriptions ............................................................. 20-10 20.3.1.1 watchpoint monitor control regi sters 0?1 (wmcr0, wmcr1)...................... 20-10 20.3.1.2 watchpoint monitor addre ss register (wmar)................................................ 20-12 20.3.1.3 watchpoint monitor address ma sk register (wmamr) ................................. 20-13 20.3.1.4 watchpoint monitor transaction mask register (wmtmr) ............................. 20-13 20.3.1.5 watchpoint monitor status register (wmsr) .................................................... 20-15 20.3.2 trace buffer register descriptions.......................................................................... 20-15 20.3.2.1 trace buffer control regi sters (tbcr0, tbcr1) ............................................. 20-15 20.3.2.2 trace buffer address re gister (tbar) .............................................................. 20-18 20.3.2.3 trace buffer address mask register (tbamr)................................................. 20-18 20.3.2.4 trace buffer transaction mask register (tbtmr)............................................ 20-18 20.3.2.5 trace buffer status re gister (tbsr) .................................................................. 20-19 20.3.2.6 trace buffer access contro l register (tbacr) ................................................ 20-20 20.3.2.7 trace buffer access data hi gh register (tbadhr)......................................... 20-21 20.3.2.8 trace buffer access data register (tbadr)..................................................... 20-21 20.3.3 context id regi sters................................................................................................ 20-22 20.3.3.1 programmed context id re gister (pcidr ) ........................................................ 20-22 20.3.3.2 current context id regi ster (ccidr) ................................................................ 20-22 20.3.4 trigger out func tion ............................................................................................... 20-23 20.3.4.1 trigger out source re gister (tosr) .................................................................. 20-23 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 xl freescale semiconductor contents paragraph number title page number 20.4 functional descri ption................................................................................................. 20-2 4 20.4.1 source and target id ............................................................................................... 20-24 20.4.2 pci interface debug ................................................................................................ 20-25 20.4.3 ddr sdram interfa ce debug............................................................................... 20-25 20.4.3.1 debug information on debug pins ...................................................................... 20-26 20.4.3.2 debug information on ecc pins......................................................................... 20-26 20.4.4 local bus interf ace debug ...................................... ................................................ 20-26 20.4.5 watchpoint moni tor ................................................................................................. 20-26 20.4.5.1 watchpoint monitor performa nce monitor events ............................................. 20-27 20.4.6 trace buffer ............................................................................................................. 20-27 20.4.6.1 traced data formats (as a f unction of tbcr1[ifsel]).................................... 20-28 20.5 initializa tion ............................................................................................................. .... 20-29 part v cpm features chapter 21 communications processor module overview 21.1 features ................................................................................................................... ....... 21-1 21.1.1 cpm memory ma p.................................................................................................... 21-4 21.2 communications proc essor (cp) ................................................................................. 21-16 21.2.1 features................................................................................................................. ... 21-16 21.2.2 cp block diag ram ................................................................................................... 21-16 21.2.3 e500 core inte rface.................................................. ................................................ 21-1 8 21.2.3.1 error reporting and capture ............................................................................... 21-18 21.2.3.1.1 cpm error address re gister (cea r)............................................................. 21-18 21.2.3.1.2 cpm error event regi ster (ceer)................................................................. 21-19 21.2.3.1.3 cpm error mask regi ster (cemr) ................................................................ 21-20 21.2.4 peripheral interface.................................................................................................. 21- 20 21.2.5 execution from ram .............................................................................................. 21-21 21.2.6 risc controller configurat ion register (rccr) ................................................... 21-22 21.2.7 risc time-stamp control register (rtscr) ........................................................ 21-23 21.2.8 risc time-stamp register (rtsr) ........................................................................ 21-24 21.2.9 risc microcode revi sion number......................................................................... 21-24 21.3 command set............................................................................................................... 2 1-24 21.3.1 cp command regist er (cpcr)............................................................................... 21-24 21.3.1.1 cp commands ..................................................................................................... 21-26 21.3.2 command register example ................................................................................... 21-28 21.3.3 command execution latency.................................................................................. 21-28 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor xli contents paragraph number title page number 21.4 internal ram ............................................................................................................... 21-28 21.4.1 buffer descriptor s (bds).. ....................................................................................... 21-31 21.4.2 parameter ra m ....................................................................................................... 21-31 21.5 risc timer tables....................................................................................................... 21- 32 21.5.1 risc timer table pa rameter ram......................................................................... 21-33 21.5.2 risc timer command regi ster (tm_cmd) ......................................................... 21-34 21.5.3 risc timer table entries........................................................................................ 21-35 21.5.4 risc timer event register (rter )/mask register (rtmr) ................................ 21-35 21.5.5 set timer command ............................................................................................... 21-35 21.5.6 risc timer initializa tion sequence ........................................................................ 21-35 21.5.7 risc timer initializa tion example ......................................................................... 21-36 21.5.8 risc timer interrupt handling ............................................................................... 21-36 21.5.9 risc timer table s can algorithm.......................................................................... 21-37 21.5.10 using the risc timers to track cp loading ......................................................... 21-37 chapter 22 cpm interrupt controller 22.1 interrupt confi guration .................................................................................................. 22 -1 22.2 cpm interrupt source priorities .................................................................................... 22-2 22.2.1 scc and fcc relativ e priority ................................................................................. 22-5 22.2.2 highest priority interrupt.. ......................................................................................... 22-5 22.3 masking interrupt sources........................................... .................................................. 22-5 22.4 cpm interrupt vector genera tion and calculat ion........................................................ 22-6 22.4.1 port c external interrupts .......................................................................................... 22-8 22.5 cpm interrupt program ming model.............................................................................. 22-8 22.5.1 interrupt controller registers .................................................................................... 22-9 22.5.1.1 cpm interrupt configurati on register (sicr)...................................................... 22-9 22.5.1.2 cpm interrupt priority regist ers (scprr_h, scprr_l)................................. 22-10 22.5.1.3 cpm interrupt pending register s (sipnr_h, sipnr_l) .................................. 22-11 22.5.1.4 cpm interrupt mask registers (simr_h, simr_l).......................................... 22-12 22.5.1.5 cpm interrupt vector re gister (sivec )............................................................. 22-14 22.5.1.6 cpm external interrupt cont rol register (siexr)............................................. 22-15 chapter 23 serial interface with time-slot assigner 23.1 overview................................................................................................................... ..... 23-1 23.2 features ................................................................................................................... ....... 23-2 23.3 overview................................................................................................................... ..... 23-3 23.4 enabling connections to tsa ....................................................................................... 23-6 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 xlii freescale semiconductor contents paragraph number title page number 23.5 serial interface ram..................................................................................................... 23 -7 23.5.1 one multiplexed channel wi th static fr ames ........................................................... 23-7 23.5.2 one multiplexed channel wi th dynamic frames ..................................................... 23-8 23.5.3 programming si2 ra m entries ................................................................................ 23-9 23.5.4 si2 ram programmi ng example............................................................................ 23-11 23.5.5 static and dynami c routing .................................................................................... 23-12 23.6 serial interface re gisters ...... ....................................................................................... 23-1 4 23.6.1 si global mode regist ers (si2gmr) ..................................................................... 23-14 23.6.2 si mode register s (si2mr) .................................................................................... 23-14 23.6.3 si2 ram shadow address re gisters (si2rsr) ..................................................... 23-20 23.6.4 si command register (si2cmdr)......................................................................... 23-20 23.6.5 si status registers (si2str)................................................................................... 23-21 23.7 MPC8555E serial interface id l interface support .................................................... 23-22 23.7.1 idl interface ex ample ............................................................................................ 23-22 23.7.2 idl interface programming..................................................................................... 23-25 23.8 serial interface gci support ....................................................................................... 23-26 23.8.1 si gci activation/deactiv ation procedur e ............................................................. 23-28 23.8.2 serial interface gc i programming .......................................................................... 23-28 23.8.2.1 normal mode gci programming........................................................................ 23-28 23.8.2.2 scit programmin g.............................................................................................. 23-29 chapter 24 cpm multiplexing 24.1 features ................................................................................................................... ....... 24-2 24.2 enabling connections to tsa or nmsi ........................................................................ 24-3 24.3 nmsi configur ation ...................................................................................................... 24- 3 24.4 cmx regist ers .............................................................................................................. 24-5 24.4.1 cmx utopia address regi ster (cmxuar) ......................................................... 24-5 24.4.2 cmx si2 clock route regi ster (cmxsi2cr)......................................................... 24-8 24.4.3 cmx fcc clock route regi ster (cmxfcr) .......................................................... 24-8 24.4.4 cmx scc clock route regi ster (cmxscr) ........................................................ 24-10 24.4.5 cmx smc clock route regi ster (cmxsmr) ...................................................... 24-13 chapter 25 baud-rate generators (brgs) 25.1 system clock control re gister (sccr)........................................................................ 25-2 25.2 brg configuration registers 1?8 (brgc n ) ................................................................ 25-3 25.3 autobaud operation on a uart ................................................................................... 25-5 25.4 uart baud rate ex amples .......................................................................................... 25-5 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor xliii contents paragraph number title page number chapter 26 cpm timers 26.1 features ................................................................................................................... ....... 26-1 26.2 general-purpose ti mer units ........................................................................................ 26-2 26.2.1 cascaded mo de.......................................................................................................... 26 -3 26.2.2 timer global configuration re gisters (tgcr1, tgcr2)........................................ 26-3 26.2.3 timer mode registers (tmr1?tmr4)..................................................................... 26-5 26.2.4 timer reference regist ers (trr1?trr4) ............................................................... 26-7 26.2.5 timer capture register s (tcr1?tcr4) ................................................................... 26-7 26.2.6 timer counters (tcn 1?tcn4)................................................................................. 26-7 26.2.7 timer event register s (ter1?ter4)....................................................................... 26-8 chapter 27 sdma channels 27.1 sdma regist ers ............................................................................................................ 2 7-2 27.1.1 sdma address error regist ers (smaer, lmaer) ............................................... 27-2 27.1.2 sdma event registers (smevr, lmevr) ............................................................ 27-2 27.1.3 sdma control registers (smctr, lmctr).......................................................... 27-3 chapter 28 serial communications controllers (sccs) 28.1 features ................................................................................................................... ....... 28-2 28.2 general scc mode register s (gsmr1?gsmr4)........................................................ 28-3 28.2.1 protocol-specific mode register (psmr) ................................................................ 28-8 28.2.2 data synchronization re gister (dsr)....................................................................... 28-8 28.2.3 transmit-on-demand register (todr) .................................................................... 28-9 28.3 scc buffer descript ors (bds) .................................................................................... 28-10 28.4 scc parameter ram................................................................................................... 28-12 28.4.1 scc base addres ses................................................................................................ 28-13 28.4.2 function code registers (rfcr, tfcr) ................................................................ 28-14 28.4.3 handling scc inte rrupts ......................................................................................... 28-15 28.4.4 initializing the sccs................................................................................................ 28-1 5 28.4.5 controlling scc timing with rts , cts , and cd .................................................. 28-16 28.4.5.1 synchronous prot ocols ........................................................................................ 28-16 28.4.5.2 asynchronous prot ocols ...................................................................................... 28-19 28.4.6 digital phase-locked loop (dpll) operat ion....................................................... 28-20 28.4.6.1 encoding data with a dpll................................................................................ 28-22 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 xliv freescale semiconductor contents paragraph number title page number 28.4.7 reconfiguring th e sccs .......................................................................................... 28-23 28.4.7.1 general reconfiguration sequence for an scc transmitter............................... 28-23 28.4.7.2 reset sequence for an sc c transmitter.............................................................. 28-24 28.4.7.3 general reconfiguration sequence for an scc receiver ................................... 28-24 28.4.7.4 reset sequence for an scc receiver.................................................................. 28-24 28.4.7.5 switching protoc ols ............................................................................................. 28-24 28.4.8 saving powe r ........................................................................................................... 28 -24 chapter 29 scc uart mode 29.1 features ................................................................................................................... ....... 29-2 29.2 normal asynchr onous mode......................................................................................... 29-2 29.3 synchronous m ode ........................................................................................................ 29- 3 29.4 scc uart parameter ram ......................................................................................... 29-3 29.5 data-handling methods: charac ter- or message -based ............................................... 29-5 29.6 error and status reporting.... ......................................................................................... 29-5 29.7 scc uart comma nds ................................................................................................. 29-5 29.8 multidrop systems and addr ess recogniti on ............................................................... 29-6 29.9 receiving control characters ........................................................................................ 29-7 29.10 hunt mode (rec eiver) ................................................................................................... 29- 9 29.11 inserting control characters into the transmit data stream......................................... 29-9 29.12 sending a break (tra nsmitter) ..................................................................................... 29-10 29.13 sending a preamble (t ransmitter) ............................................................................... 29-10 29.14 fractional stop bits (transmitter) ............................................................................... 29-10 29.15 handling errors in the sc c uart controller ............................................................ 29-11 29.16 uart mode register (psmr).................................................................................... 29-12 29.17 scc uart receive buffer de scriptor (rxb d) ......................................................... 29-14 29.18 scc uart transmit buffer de scriptor (txb d) ........................................................ 29-17 29.19 scc uart event register (scce) and mask register (sccm) .............................. 29-18 29.20 scc uart status regi ster (sccs)............................................................................ 29-20 29.21 s-records loader a pplication..................................................................................... 29-21 chapter 30 scc hdlc mode 30.1 scc hdlc featur es ..................................................................................................... 30-1 30.2 scc hdlc channel frame transmission .................................................................... 30-2 30.3 scc hdlc channel fram e reception ......................................................................... 30-2 30.4 scc hdlc parameter ram......................................................................................... 30-3 30.5 programming the scc in hdlc mode......................................................................... 30-4 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor xlv contents paragraph number title page number 30.6 scc hdlc comma nds................................................................................................. 30-5 30.7 handling errors in the sc c hdlc controller.............................................................. 30-6 30.8 hdlc mode register (psmr)...................................................................................... 30-7 30.9 scc hdlc receive buffer de scriptor (rxb d) ........................................................... 30-8 30.10 scc hdlc transmit buffer de scriptor (txbd)........................................................ 30-11 30.11 hdlc event register (scce)/hdl c mask register (sccm) ................................. 30-12 30.12 scc hdlc status regi ster (sccs)............................................................................ 30-13 30.13 hdlc bus mode with coll ision detection................................................................. 30-14 30.13.1 hdlc bus featur es................................................................................................. 30-16 30.13.2 accessing the hdlc bus ........................................................................................ 30-16 30.13.3 increasing perfor mance ........................................................................................... 30-17 30.13.4 delayed rts mode.................................................................................................. 30-18 30.13.5 using the time-slot as signer (tsa) ...................................................................... 30-19 30.13.6 hdlc bus protocol programming.......................................................................... 30-19 30.13.6.1 programming gsmr and psmr fo r the hdlc bus protocol ........................... 30-19 chapter 31 scc bisync mode 31.1 features ................................................................................................................... ....... 31-2 31.2 scc bisync channel fram e transmission ................................................................ 31-2 31.3 scc bisync channel frame reception ..................................................................... 31-3 31.4 scc bisync parameter ram ..................................................................................... 31-3 31.5 scc bisync commands ............................................................................................. 31-4 31.6 scc bisync control char acter recogniti on .............................................................. 31-5 31.7 bisync sync regist er (bsync).............................................................................. 31-7 31.8 scc bisync dle regi ster (bdle) ........................................................................... 31-7 31.9 sending and receiving the s ynchronization sequence ................................................. 31-8 31.10 handling errors in th e scc bisync ........................................................................... 31-9 31.11 bisync mode regist er (psmr).................................................................................. 31-9 31.12 scc bisync receive bd (rxbd) ............................................................................ 31-11 31.13 scc bisync transmit bd (txbd)........................................................................... 31-12 31.14 bisync event register (scce)/bis ync mask register (sccm).......................... 31-14 31.15 scc status regist ers (sccs)...................................................................................... 31-15 31.16 programming the scc bisy nc controller ................................................................ 31-16 chapter 32 scc transparent mode 32.1 features ................................................................................................................... ....... 32-1 32.2 scc transparent channel fram e transmission pr ocess............................................... 32-2 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 xlvi freescale semiconductor contents paragraph number title page number 32.3 scc transparent channel fram e reception pro cess .................................................... 32-2 32.4 achieving synchronization in transparent mode ......................................................... 32-3 32.4.1 synchronization in nmsi mode................................................................................ 32-3 32.4.1.1 in-line synchronization pattern............................................................................ 32-3 32.4.1.2 external synchroniza tion signals.......................................................................... 32-3 32.4.1.2.1 external synchroniza tion example ................................................................... 32-4 32.4.1.3 transparent mode without e xplicit synchronization ........................................... 32-5 32.4.2 synchronization and the tsa .................................................................................... 32-5 32.4.2.1 inline synchroniza tion pattern .............................................................................. 32-5 32.4.2.2 inherent synchr onization....................................................................................... 32-5 32.4.3 end of frame dete ction............................................................................................. 32-5 32.5 crc calculation in tr ansparent mode.......................................................................... 32-6 32.6 scc transparent parameter ram................................................................................. 32-6 32.7 scc transparent commands......................................................................................... 32-6 32.8 handling errors in the tran sparent controller .............................................................. 32-7 32.9 transparent mode a nd the psmr.................................................................................. 32-8 32.10 scc transparent receive buffer descriptor (r xbd) ................................................... 32-8 32.11 scc transparent transmit bu ffer descriptor (txbd)................................................ 32-10 32.12 scc transparent event register (s cce)/mask register (sccm)............................. 32-11 32.13 scc status register in tran sparent mode (sccs) ..................................................... 32-12 chapter 33 scc appletalk mode 33.1 operating the loca ltalk bus ......................................................................................... 33-1 33.2 features ................................................................................................................... ....... 33-2 33.3 connecting to appl etalk ............................................................................................... 33-2 33.4 programming the scc in appletalk mode................................................................... 33-3 33.4.1 programming the gsmr ........................................................................................... 33-3 33.4.2 programming the psmr............................................................................................ 33-4 33.4.3 programming the todr............................................................................................ 33-4 chapter 34 quicc multi-channel controller (qmc) 34.1 features ................................................................................................................... ....... 34-2 34.2 qmc and the serial interface ........................................................................................ 34-2 34.2.1 synchronizati on ......................................................................................................... 3 4-3 34.2.2 loopback mode ......................................................................................................... 34- 3 34.2.3 echo mode................................................................................................................ . 34-3 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor xlvii contents paragraph number title page number 34.2.4 inverted si gnals ......................................................................................................... 34-3 34.2.5 qmc routing changes on-the-fly.......................................................................... 34-3 34.3 qmc memory organization.......................................................................................... 34-4 34.3.1 qmc memory structure ............................................................................................ 34-4 34.3.2 scc base and global multi- channel parameters ..................................................... 34-4 34.3.2.1 tsatrx/tsattx pointers and time-slot assignment table .............................. 34-5 34.3.2.2 tsatrx/tsattx channel pointers...................................................................... 34-5 34.3.2.3 logical channel tbas e and rbase .................................................................. 34-5 34.3.2.4 mcbase............................................................................................................... 34 -5 34.3.2.5 buffer descriptor table ......................................................................................... 34-6 34.3.2.6 data buffer po inter.............................................. .................................................. 34-6 34.3.2.7 data buffer ............................................................................................................ 34-6 34.3.2.8 global multi-channel parameters ......................................................................... 34-6 34.3.3 multiple scc assignm ent tables............................................................................ 34-12 34.3.4 channel-specific parameters................................................................................... 34-15 34.3.4.1 channel-specific hdl c parameters................................................................... 34-15 34.3.4.1.1 chamr?channel mode re gister (hdlc) .................................................. 34-16 34.3.4.1.2 tstate?tx internal state (hdlc).............................................................. 34-18 34.3.4.1.3 intmsk?interrupt mask (hdlc) ............................................................... 34-18 34.3.4.1.4 rstate?rx internal state (hdlc) ............................................................. 34-19 34.3.4.2 channel-specific transp arent parameters........................................................... 34-19 34.3.4.2.1 chamr?channel mode register (transparent mode)................................ 34-21 34.3.4.2.2 tstate?tx internal state (transparent mode) ........................................... 34-22 34.3.4.2.3 intmsk?interrupt mask (transparent mode) ............................................. 34-23 34.3.4.2.4 trnsync?transparent synchronizat ion (transparent mode) ................... 34-23 34.3.4.2.5 rstate?rx internal state (transparent mode)........................................... 34-26 34.4 qmc commands ......................................................................................................... 34-27 34.4.1 transmit commands................................................................................................ 34-27 34.4.2 receive comma nds ................................................................................................. 34-28 34.5 qmc exceptions.......................................................................................................... 34- 28 34.5.1 global error ev ents ................................................. ................................................ 34-29 34.5.1.1 global underrun (gun)...................................................................................... 34-30 34.5.1.2 global overrun (gov) in the fifo .................................................................... 34-30 34.5.1.3 restart from a gl obal error ................................................................................. 34-30 34.5.2 scc event register (scce).................................................................................... 34-30 34.5.3 interrupt table entry................................................ ................................................ 34-3 1 34.5.4 interrupt handl ing.................................................................................................... 34- 33 34.5.5 channel interrupt pr ocessing flow.......................................................................... 34-34 34.6 buffer descriptors........................................................................................................ 3 4-34 34.6.1 receive buffer de scriptor ....................................................................................... 34-35 34.6.2 transmit buffer descriptor...................................................................................... 34-38 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 xlviii freescale semiconductor contents paragraph number title page number 34.6.3 placement of buffer descriptors.............................................................................. 34-39 34.6.3.1 parameter ram usage for qm c over several sccs ........................................ 34-40 34.6.3.2 internal memory structure................................................................................... 34-40 34.7 qmc initialization ....................................................................................................... 34 -40 34.7.1 restarting the transmitter........................................................................................ 34-41 34.7.2 restarting the r eceiver............................................ ................................................ 34-41 34.7.3 disabling receiver and transmitter ........................................................................ 34-41 chapter 35 universal serial bus controller 35.1 usb integration in the MPC8555E ............................................................................... 35-1 35.2 overview................................................................................................................... ..... 35-1 35.2.1 usb controller ke y features .................................................................................... 35-2 35.3 host controller li mitations .. ......................................................................................... 35-2 35.3.1 usb controller pin functi ons and clocki ng............................................................. 35-2 35.4 usb function descri ption............................................................................................. 35-4 35.4.1 usb function controller transmit/recei ve.............................................................. 35-5 35.5 usb host descri ption ................................................................................................... 35-7 35.5.1 usb host controller tr ansmit/receive .................................................................... 35-8 35.5.1.1 packet-level in terface ......................................... .................................................. 35-9 35.5.1.2 transaction-level interface ................................................................................... 35-9 35.5.2 sof transmission for usb host controlle r ........................................................... 35-12 35.5.3 usb function and host parameter ram memory map......................................... 35-12 35.5.4 endpoint parameters block pointer (ep n ptr) ....................................................... 35-13 35.5.5 frame number (frame_n)................................................................................... 35-14 35.5.6 usb function code register s (rfcr and tfcr) ................................................. 35-16 35.5.7 usb function program ming model ....................................................................... 35-16 35.5.7.1 usb mode register (usmod)........................................................................... 35-17 35.5.7.2 usb slave address regi ster (usadr ) .............................................................. 35-18 35.5.7.3 usb endpoint registers (usep1?usep4)......................................................... 35-18 35.5.7.4 usb command register (uscom).................................................................... 35-19 35.5.7.5 usb event register (usber) ............................................................................ 35-20 35.5.7.6 usb mask register (usbmr)............................................................................ 35-21 35.5.7.7 usb status regist er (usbs)............................................................................... 35-21 35.5.7.8 usb start of frame ti mer (ussft) ................................................................... 35-21 35.6 usb buffer descript or ring. ....................................................................................... 35-22 35.6.1 usb receive buffer descriptor (r xbd) for host and function ............................ 35-24 35.6.2 usb transmit buffer descript or (txbd) for function........................................... 35-26 35.6.3 usb transmit buffer descript or (txbd) for host ................................................. 35-27 35.6.4 usb transaction buffer descri ptor (trbd) for host.............................................. 35-29 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor xlix contents paragraph number title page number 35.7 usb cp comma nds..................................................................................................... 35-32 35.7.1 stop tx comm and................................................................................................. 35-32 35.7.2 restart tx comm and ......................................... ................................................ 35-32 35.8 usb controller errors ................................................................................................. 35-33 35.9 usb function controller init ialization exam ple ........................................................ 35-33 35.10 programming the usb host controller (packet-level) .............................................. 35-35 35.10.1 usb host controller initi alization exam ple ........................................................... 35-35 35.11 programming the usb host contro ller (transacti on-level) ...................................... 35-37 35.11.1 usb host controller initi alization exam ple ........................................................... 35-37 chapter 36 serial management controllers (smcs) 36.1 features ................................................................................................................... ....... 36-2 36.2 common smc settings and configurations ................................................................. 36-2 36.2.1 smc mode registers (s mcmr1, smcmr2).......................................................... 36-2 36.2.2 smc buffer descriptor operation............................................................................. 36-4 36.2.3 smc parameter ram................................................................................................ 36-5 36.2.3.1 smc function code registers (rfcr, tfcr) .................................................... 36-8 36.2.4 disabling smcs on-the-fly..................................................................................... 36-8 36.2.4.1 smc transmitter full sequence............................................................................ 36-9 36.2.4.2 smc transmitter shortc ut sequence .................................................................... 36-9 36.2.4.3 smc receiver full sequence................................................................................ 36-9 36.2.4.4 smc receiver shortcut sequence......................................................................... 36-9 36.2.4.5 switching protoc ols ............................................................................................... 36-9 36.2.5 saving powe r ........................................................................................................... 36 -10 36.2.6 handling interrupts in the smc............................................................................... 36-10 36.3 smc in uart mode ................................................... ................................................ 36-10 36.3.1 features................................................................................................................. ... 36-11 36.3.2 smc uart channel transmission process ........................................................... 36-11 36.3.3 smc uart channel reception process................................................................. 36-11 36.3.4 programming the smc uar t controller ............................................................... 36-11 36.3.5 smc uart transmit and receive commands ...................................................... 36-12 36.3.6 sending a break ....................................................................................................... 36- 12 36.3.7 sending a preamble ................................................................................................. 36-13 36.3.8 handling errors in the sm c uart controller ....................................................... 36-13 36.3.9 smc uart rxbd .................................................................................................. 36-14 36.3.10 smc uart txbd .................................................................................................. 36-17 36.3.11 smc uart event register (smc e)/mask register (smcm) .............................. 36-18 36.3.12 smc uart controller prog ramming example...................................................... 36-19 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 l freescale semiconductor contents paragraph number title page number 36.4 smc in transparen t mode........................................................................................... 36-20 36.4.1 features................................................................................................................. ... 36-20 36.4.2 smc transparent channel tr ansmission process ................................................... 36-21 36.4.3 smc transparent channel reception process ........................................................ 36-21 36.4.4 using smsyn for synchroniza tion ........................................................................ 36-22 36.4.5 using the time-slot assigner (t sa) for synchronization...................................... 36-23 36.4.6 smc transparent commands.................................................................................. 36-25 36.4.7 handling errors in the smc transparent controller............................................... 36-25 36.4.8 smc transparent rxbd.......................................................................................... 36-26 36.4.9 smc transparent txbd .......................................................................................... 36-27 36.4.10 smc transparent event register (s mce)/mask register (smcm)...................... 36-28 36.4.11 smc transparent nmsi pr ogramming example.................................................... 36-29 36.5 smc in gci m ode....................................................................................................... 36-30 36.5.1 smc gci parameter ram...................................................................................... 36-30 36.5.2 handling the gci monitor channel ........................................................................ 36-31 36.5.2.1 smc gci monitor channel transmission process............................................. 36-31 36.5.2.2 smc gci monitor channel r eception process .................................................. 36-31 36.5.3 handling the gci c/ i channel ................................................................................ 36-31 36.5.3.1 smc gci c/i channel tran smission process ..................................................... 36-31 36.5.3.2 smc gci c/i channel rece ption process .......................................................... 36-31 36.5.4 smc gci comma nds.............................................................................................. 36-32 36.5.5 smc gci monitor channel rxbd ......................................................................... 36-32 36.5.6 smc gci monitor channel txbd.......................................................................... 36-33 36.5.7 smc gci c/i channel rxbd ................................................................................. 36-33 36.5.8 smc gci c/i channel txbd.................................................................................. 36-34 36.5.9 smc gci event register (smce) /mask register (smcm).................................. 36-34 chapter 37 fast communications controllers (fccs) 37.1 overview................................................................................................................... ..... 37-1 37.2 general fcc mode registers (gfmr x ) ....................................................................... 37-3 37.3 general fcc expansion mode register (gfemr) ...................................................... 37-7 37.4 fcc protocol-specific mode registers (fpsmr x ) ...................................................... 37-7 37.5 fcc data synchronization registers (fdsr x )............................................................. 37-7 37.6 fcc transmit-on-demand registers (ftodr x ) .......................................................... 37-8 37.7 fcc buffer descri ptors ................................................................................................. 37-9 37.8 fcc parameter ram................................................................................................... 37-10 37.8.1 fcc function code registers (fcr x ) .................................................................... 37-12 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor li contents paragraph number title page number 37.9 interrupts from th e fccs ............................................................................................ 37-13 37.9.1 fcc event registers (fcce x ) ................................................................................ 37-13 37.9.2 fcc mask registers (fccm x )................................................................................ 37-14 37.9.3 fcc status registers (fccs x ) ................................................................................ 37-14 37.10 fcc initiali zation ................. ....................................................................................... 37-14 37.11 fcc interrupt ha ndling ............................................................................................... 37-15 37.11.1 fcc transmit errors................................................................................................ 37-15 37.11.1.1 re-initialization procedure.................................................................................. 37-15 37.11.1.2 recovery seque nce.............................................................................................. 37-16 37.11.1.3 adjusting transmitte r bd handling.................................................................... 37-16 37.12 fcc timing cont rol .................................................................................................... 37-1 6 37.13 disabling the fccs on-the-fly.................................................................................. 37-19 37.13.1 fcc transmitter fu ll sequence............................................................................... 37-20 37.13.2 fcc transmitter shortc ut sequence ....................................................................... 37-20 37.13.3 fcc receiver full sequence................................................................................... 37-20 37.13.4 fcc receiver shortc ut sequence............................................................................ 37-20 37.13.5 switching protoc ols ................................................................................................. 37-2 1 37.14 saving powe r .............................................................................................................. . 37-21 chapter 38 fcc hdlc controller 38.1 key features ............................................................................................................... ... 38-1 38.2 hdlc channel frame transm ission processi ng .......................................................... 38-2 38.3 hdlc channel frame recep tion processing ............................................................... 38-3 38.4 hdlc parameter ram ................................................................................................. 38-3 38.5 programming model ...................................................................................................... 38-5 38.5.1 hdlc command set................................................................................................. 38-5 38.5.2 hdlc error handling ............................................................................................... 38-6 38.6 hdlc mode register (fpsmr) ................................................................................... 38-8 38.7 hdlc receive buffer descriptor (rxbd).................................................................... 38-9 38.8 hdlc transmit buffer de scriptor (txbd) ................................................................ 38-12 38.9 hdlc event register (fcce)/m ask register (fccm) ............................................. 38-14 38.10 fcc status register (fccs) ....................................................................................... 38-16 chapter 39 fcc transparent controller 39.1 features ................................................................................................................... ....... 39-1 39.2 transparent channel operation ..................................................................................... 39-2 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 lii freescale semiconductor contents paragraph number title page number 39.3 achieving synchronization in transparent mode ......................................................... 39-2 39.3.1 in-line synchronization pattern................................................................................ 39-2 39.3.2 external synchroniza tion signals.............................................................................. 39-3 39.3.3 transparent synchronizat ion example ...................................................................... 39-4 chapter 40 cpm fast ethernet controller 40.1 fast ethernet on th e MPC8555E ................................................................................... 40-2 40.2 features ................................................................................................................... ....... 40-2 40.3 connecting the MPC8555E to fast ethernet ................................................................. 40-4 40.3.1 connecting the MPC8555E to ethernet (mii)........................................................... 40-4 40.3.2 connecting the MPC8555E to ethernet (rmii) ........................................................ 40-5 40.4 ethernet channel fram e transmission .......................................................................... 40-5 40.5 ethernet channel frame reception ............................................................................... 40-6 40.6 flow control ............................................................................................................... ... 40-7 40.7 cam interface .............................................................................................................. . 40-8 40.8 ethernet paramete r ram............................................................................................... 40-9 40.9 programming model .................................................................................................... 40-12 40.10 ethernet comma nd set ................................................................................................ 40-12 40.11 rmon suppor t............................................................................................................ 40 -13 40.12 ethernet address recognition ..................................................................................... 40-15 40.13 hash table algor ithm.................................................................................................. 40-1 7 40.14 interpacket gap time................................................................................................... 40- 18 40.15 handling collis ions ..................................................................................................... 40 -18 40.16 internal and external loopback................................................................................... 40-18 40.17 ethernet error-handlin g procedure ............................................................................. 40-19 40.18 fast ethernet re gisters ................................................................................................ 40- 19 40.18.1 general fcc expansion mode register (gfemr) ................................................ 40-19 40.18.2 fcc ethernet mode re gister (fpsmr) .................................................................. 40-20 40.18.3 ethernet event register (fcc e)/mask register (fccm) ...................................... 40-22 40.19 ethernet rxbds ........................................................................................................... 4 0-25 40.20 ethernet txbds ........................................................................................................... 4 0-27 chapter 41 atm controller 41.1 features ................................................................................................................... ....... 41-1 41.2 atm controller ov erview............................................................................................. 41-4 41.2.1 transmitter overview ................................................................................................ 41-4 41.2.1.1 aal5 transmitter overview................................................................................. 41-5 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor liii contents paragraph number title page number 41.2.1.2 aal1 transmitter overview................................................................................. 41-5 41.2.1.3 aal0 transmitter overview................................................................................. 41-6 41.2.1.4 aal2 transmitter overview................................................................................. 41-6 41.2.1.5 transmit external rate and internal rate modes.................................................. 41-6 41.2.2 receiver over view .................................................................................................... 41-6 41.2.2.1 aal5 receiver overview ..................................................................................... 41-6 41.2.2.2 aal1 receiver overview ..................................................................................... 41-7 41.2.2.3 aal0 receiver overview ..................................................................................... 41-7 41.2.2.4 aal2 receiver overview ..................................................................................... 41-7 41.2.3 performance moni toring............................................................................................ 41-8 41.2.4 abr flow control..................................................................................................... 41-8 41.3 atm pace control (apc) unit...................................................................................... 41-8 41.3.1 apc modes and atm se rvice types ........................................................................ 41-8 41.3.2 apc unit scheduling mechanism............................................................................. 41-9 41.3.3 determining the schedul ing table size..................................................................... 41-9 41.3.3.1 determining the cells per slot (c ps) in a scheduling table................................ 41-9 41.3.3.2 determining the number of slot s in a scheduling table .................................... 41-10 41.3.4 determining the time-slot scheduling rate of a channel ..................................... 41-10 41.3.5 atm traffic type .................................................................................................... 41-11 41.3.5.1 peak cell rate traffic type................................................................................. 41-11 41.3.5.2 determining the pcr traffi c type parameters ................................................... 41-11 41.3.5.3 peak and sustain traf fic type (vbr) ................................................................. 41-11 41.3.5.3.1 example for using vbr tr affic parameters ................................................... 41-12 41.3.5.3.2 handling the cell loss priority (clp)?vbr types 1 and 2......................... 41-12 41.3.5.4 peak and minimum cell rate traffic type (ubr+)........................................... 41-12 41.3.6 determining the priority of an atm channel ......................................................... 41-13 41.4 vci/vpi address lookup mechanism........................................................................ 41-13 41.4.1 external cam lo okup ............................................ ................................................ 41-13 41.4.2 address compress ion .............................................................................................. 41-14 41.4.2.1 vp-level address compre ssion table (vplt) .................................................. 41-16 41.4.2.2 vc-level address compressi on tables (vclts)............................................... 41-17 41.4.3 misinserted ce lls ..................................................................................................... 41- 18 41.4.4 receive raw cell queue ......................................................................................... 41-18 41.5 available bit rate (abr ) flow control...................................................................... 41-19 41.5.1 abr model.............................................................................................................. 41 -20 41.5.1.1 abr flow control source e nd-system behavior .............................................. 41-20 41.5.1.2 abr flow control destinati on end-system behavior ....................................... 41-21 41.5.1.3 abr flowcharts .................................................................................................. 41-21 41.5.2 rm cell struct ure .................................................................................................... 41-2 6 41.5.2.1 rm cell rate representation .............................................................................. 41-26 41.5.3 abr flow control setup......................................................................................... 41-27 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 liv freescale semiconductor contents paragraph number title page number 41.6 oam support .............................................................................................................. 41 -27 41.6.1 atm-layer oam de finitions ................................................................................. 41-27 41.6.2 virtual path (f4) flow mechanism ......................................................................... 41-28 41.6.3 virtual channel (f5) flow mechanism ................................................................... 41-28 41.6.4 receiving oam f4 or f5 cells............................................................................... 41-28 41.6.5 transmitting oam f4 or f5 cells........................................................................... 41-28 41.6.6 performance moni toring.......................................................................................... 41-29 41.6.6.1 running a performance block test ..................................................................... 41-30 41.6.6.2 pm block monito ring.......................................................................................... 41-30 41.6.6.3 pm block genera tion .......................................................................................... 41-31 41.6.6.4 brc performance ca lculations........................................................................... 41-32 41.7 user-defined cell s (udc) .......................................................................................... 41-32 41.7.1 udc extended address mode (uead).................................................................. 41-33 41.8 atm layer statis tics ................................................................................................... 41-3 3 41.9 interworking............................................................................................................... .. 41-33 41.9.1 atm-to-atm automatic da ta forwarding............................................................. 41-34 41.9.2 using interrupts in automati c data forwar ding ..................................................... 41-34 41.10 atm memory stru cture............................................................................................... 41-35 41.10.1 parameter ra m ....................................................................................................... 41-3 5 41.10.1.1 determining uead_offset (uead mode only) .......................................... 41-37 41.10.1.2 vci filtering (vcif)........................................................................................... 41-38 41.10.1.3 global mode entr y (gmode)............................................................................ 41-38 41.10.2 connection tables (rct, tct, and tc te) ............................................................ 41-39 41.10.2.1 atm channel code ............................................................................................. 41-40 41.10.2.2 receive connection table (rct)........................................................................ 41-41 41.10.2.2.1 aal5 protocol-s pecific rct ......................................................................... 41-43 41.10.2.2.2 aal5-abr protocol-s pecific rct................................................................ 41-44 41.10.2.2.3 aal1 protocol-s pecific rct ......................................................................... 41-45 41.10.2.2.4 aal0 protocol-s pecific rct ......................................................................... 41-46 41.10.2.2.5 aal2 protocol-s pecific rct ......................................................................... 41-47 41.10.2.3 transmit connection table (tct)....................................................................... 41-48 41.10.2.3.1 aal5 protocol-spe cific tct ......................................................................... 41-51 41.10.2.3.2 aal1 protocol-spe cific tct ......................................................................... 41-51 41.10.2.3.3 aal0 protocol-spe cific tct ......................................................................... 41-53 41.10.2.3.4 aal2 protocol-spe cific tct ......................................................................... 41-53 41.10.2.3.5 vbr protocol-spe cific tcte ......................................................................... 41-54 41.10.2.3.6 ubr+ protocol-spe cific tcte....................................................................... 41-55 41.10.2.3.7 abr protocol-spe cific tcte ......................................................................... 41-56 41.10.3 oam performance monitoring tables .................................................................... 41-58 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor lv contents paragraph number title page number 41.10.4 apc data struct ure ................................................................................................. 41-59 41.10.4.1 apc parameter tables ......................................................................................... 41-60 41.10.4.2 apc priority table .............................................................................................. 41-61 41.10.4.3 apc scheduling tables ....................................................................................... 41-61 41.10.5 atm controller buffer de scriptors (bds ) .............................................................. 41-62 41.10.5.1 transmit buffer operation................................................................................... 41-62 41.10.5.2 receive buffer operation .................................................................................... 41-63 41.10.5.2.1 static buffer allocation ................................................................................... 41-63 41.10.5.2.2 global buffer a llocation ................................................................................. 41-64 41.10.5.2.3 free buffer pools............................................................................................. 41-65 41.10.5.2.4 free buffer pool pa rameter tables.................................................................. 41-66 41.10.5.3 atm controller buffers....................................................................................... 41-67 41.10.5.4 aal5 rxbd ........................................................................................................ 41-67 41.10.5.5 aal1 rxbd ........................................................................................................ 41-69 41.10.5.6 aal0 rxbd ........................................................................................................ 41-70 41.10.5.7 aal2 rxbd ........................................................................................................ 41-71 41.10.5.8 aal5 user-defined cell? rxbd extension...................................................... 41-71 41.10.5.9 aal5 txbd s....................................................................................................... 41-72 41.10.5.10 aal1 txbd s....................................................................................................... 41-7 3 41.10.5.11 aal0 txbd s....................................................................................................... 41-7 4 41.10.5.12 aal2 txbd s....................................................................................................... 41-7 5 41.10.5.13 aal5, aal1 user-defined cell?txbd extension.......................................... 41-75 41.10.6 aal1 sequence number (sn) protection tabl e..................................................... 41-75 41.10.7 uni statistics table ................................................................................................. 41- 76 41.11 atm except ions .......................................................................................................... 41 -77 41.11.1 interrupt queues ...................................................................................................... 41 -77 41.11.2 interrupt queue entry .............................................................................................. 41-78 41.11.3 interrupt queue parameter tables ........................................................................... 41-78 41.12 utopia interface........................................................................................................ 41 -79 41.12.1 extended number of phys ..................................................................................... 41-79 41.12.2 utopia interface ma ster mode ............................................................................. 41-79 41.12.2.1 utopia master multiple phy operation.......................................................... 41-81 41.12.3 utopia interface slave mode ............................................................................... 41-81 41.12.3.1 utopia slave multiple phy operation ............................................................ 41-82 41.12.3.2 utopia clocki ng modes ................................................................................... 41-82 41.12.3.3 utopia loopback modes.................................................................................. 41-82 41.13 atm registers ............................................................................................................. 41-83 41.13.1 general fcc mode regi ster (gfmr)..................................................................... 41-83 41.13.2 general fcc expansion mode register (gfemr x ) .............................................. 41-83 41.13.3 fcc protocol-specific mode register (fpsmr).................................................... 41-84 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 lvi freescale semiconductor contents paragraph number title page number 41.13.4 atm event register (fcce)/m ask register (fccm)............................................ 41-86 41.13.5 fcc transmit internal rate registers (ftirr x ) .................................................... 41-87 41.14 atm transmit comm and ............................................................................................ 41-88 41.15 expanded internal rate................................................................................................ 41-8 9 41.15.1 transmit external rate and internal rate modes.................................................... 41-89 41.15.2 fcc transmit internal rate mode .......................................................................... 41-90 41.15.3 fcc transmit internal rate port enable register (firper) ................................. 41-90 41.15.4 fcc internal rate event register (firer) ............................................................ 41-91 41.15.5 fcc internal rate selection regi sters (firsr_hi, firsr_lo)........................... 41-92 41.15.6 fcc transmit internal rate register (ftirr x )...................................................... 41-93 41.15.6.1 exampl e ............................................................................................................... 41-94 41.15.7 internal rate progra mming model .......................................................................... 41-95 41.16 configuring the atm controller fo r maximum cpm performance ........................... 41-95 41.16.1 using transmit intern al rate mode ........................................................................ 41-95 41.16.2 apc configurat ion .................................................................................................. 41-96 41.16.3 buffer configur ation................................................................................................ 41-9 6 chapter 42 atm aal2 42.1 introducti on............................................................................................................... ..... 42-1 42.2 features ................................................................................................................... ....... 42-2 42.3 aal2 transmit ter.......................................................................................................... 4 2-4 42.3.1 transmitter overview ................................................................................................ 42-4 42.3.2 transmit priority mechanism .................................................................................... 42-5 42.3.2.1 round robin prio rity........................................... .................................................. 42-5 42.3.2.2 fixed priority ......................................................................................................... 42-6 42.3.3 partial fill mode (pfm) .......................................... .................................................. 42-7 42.3.4 no stf mode ............................................................................................................ 42 -8 42.3.5 aal2 tx data structures .......................................................................................... 42-9 42.3.5.1 aal2 protocol-spe cific tct................................................................................ 42-9 42.3.5.2 cps tx queue de scriptor ................................................................................... 42-12 42.3.5.3 cps buffer structure ........................................................................................... 42-14 42.3.5.4 sssar tx queue descriptor .............................................................................. 42-16 42.3.5.5 sssar transmit buffer descriptor..................................................................... 42-18 42.4 aal2 receiver ............................................................................................................ 42 -19 42.4.1 receiver over view .................................................................................................. 42-19 42.4.2 mapping of phy | vp | vc | cid............................................................................ 42-20 42.4.3 aal2 switchin g ...................................................................................................... 42-21 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor lvii contents paragraph number title page number 42.4.4 aal2 rx data structures........................................................................................ 42-22 42.4.4.1 aal2 protocol-specific rct ............................................................................. 42-23 42.4.4.2 cid mapping tables and rxqds........................................................................ 42-26 42.4.4.3 cps rx queue desc riptors.................................................................................. 42-26 42.4.4.4 cps receive buffer desc riptor (rxb d) ............................................................. 42-27 42.4.4.5 cps switch rx queu e descriptor ....................................................................... 42-28 42.4.4.6 switch receive/transmit buff er descriptor (rxbd)...................................... 42-29 42.4.4.7 sssar rx queue descriptor .............................................................................. 42-30 42.4.4.8 sssar receive buffer descriptor ...................................................................... 42-32 42.5 aal2 parameter ram ................................................................................................ 42-34 42.6 user-defined cells in aal2 ....................................................................................... 42-37 42.7 aal2 exceptions ........................................................................................................ 42-3 7 chapter 43 serial peripheral interface (spi) 43.1 features ................................................................................................................... ....... 43-1 43.2 spi clocking and signa l functions ............................................................................... 43-2 43.3 configuring the spi controller...................................................................................... 43-2 43.3.1 spi as a master device .............................................................................................. 43-3 43.3.2 spi as a slave device ................................................................................................ 43-4 43.3.3 spi in multiple-maste r operation ............................................................................. 43-4 43.4 programming the spi registers ..................................................................................... 43-6 43.4.1 spi mode register (spmode) ................................................................................. 43-6 43.4.1.1 spi examples with differen t spmode[len] values.......................................... 43-8 43.4.2 spi event/mask register s (spie/spim) ................................................................... 43-9 43.4.3 spi command register (spcom) .......................................................................... 43-10 43.5 spi parameter ram .................................................................................................... 43-10 43.5.1 receive/transmit function code registers (rfc r/tfcr).................................... 43-12 43.6 spi commands ............................................................................................................ 43- 12 43.7 spi buffer descriptor (bd) table ............................................................................... 43-13 43.7.1 spi buffer descript ors (bds) .................................................................................. 43-13 43.7.1.1 spi receive bd (rxbd) ..................................................................................... 43-14 43.7.1.2 spi transmit bd (txbd) .................................................................................... 43-15 43.8 spi master programmi ng example ............................................................................. 43-16 43.9 spi slave programmi ng example................................................................................ 43-17 43.10 handling interrupts in the spi ..................................................................................... 43-18 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 lviii freescale semiconductor contents paragraph number title page number chapter 44 i 2 c controller 44.1 features ................................................................................................................... ....... 44-2 44.2 i 2 c controller clocking a nd signal functions .............................................................. 44-2 44.3 i 2 c controller tran sfers ................................................................................................ 44-2 44.3.1 i 2 c master write (slave read) .................................................................................. 44-3 44.3.2 i 2 c loopback testin g ................................................................................................ 44-4 44.3.3 i 2 c master read (sla ve write) .................................................................................. 44-4 44.3.4 i 2 c multi-master consid erations .............................................................................. 44-5 44.4 i 2 c registers .................................................................................................................. 44 -6 44.4.1 i 2 c mode register (i2mod)..................................................................................... 44-6 44.4.2 i 2 c address register (i2add).................................................................................. 44-7 44.4.3 i 2 c baud rate generator re gister (i2brg) ............................................................. 44-7 44.4.4 i 2 c event/mask registers (i 2cer/i2cmr) ............................................................. 44-7 44.4.5 i 2 c command register (i2com).............................................................................. 44-8 44.5 i 2 c parameter ram....................................................................................................... 44-9 44.6 i 2 c commands............................................................................................................. 44-11 44.7 i 2 c buffer descriptor (bd) table................................................................................ 44-11 44.7.1 i 2 c buffer descriptor s (bds) .................................................................................. 44-12 44.7.1.1 i 2 c receive buffer descri ptor (rxbd)............................................................... 44-12 44.7.1.2 i 2 c transmit buffer descri ptor (txbd) ............................................................. 44-13 chapter 45 parallel i/o ports 45.1 features ................................................................................................................... ....... 45-1 45.2 port registers ............................................................................................................. .... 45-1 45.2.1 port open-drain registers (podr x )......................................................................... 45-1 45.2.1.1 port a open-drain regi ster (podra) ................................................................. 45-2 45.2.1.2 port b open-drain re gister (podrb).................................................................. 45-2 45.2.1.3 port c open-drain re gister (podrc).................................................................. 45-3 45.2.1.4 port d open-drain regi ster (podrd) ................................................................. 45-4 45.2.2 port data registers (pdat x )..................................................................................... 45-4 45.2.2.1 port a data regist er (pdata).............................................................................. 45-5 45.2.2.2 port b data regist er (pdatb).............................................................................. 45-5 45.2.2.3 port c data regist er (pdatc).............................................................................. 45-6 45.2.2.4 port d data regist er (pdatd) ............................................................................. 45-6 45.2.3 port data direc tion registers (pdir x )...................................................................... 45-7 45.2.3.1 port a data direction re gister (pdira) .............................................................. 45-7 45.2.3.2 port b data direction register (pdirb)............................................................... 45-8 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor lix contents paragraph number title page number 45.2.3.3 port c data direction register (pdirc)............................................................... 45-8 45.2.3.4 port d data direction re gister (pdird) .............................................................. 45-9 45.2.4 port pin assignment registers (ppar x ) ................................................................. 45-10 45.2.4.1 port a pin assignment re gisters (ppara) ........................................................ 45-10 45.2.4.2 port b pin assignment re gisters (pparb)......................................................... 45-11 45.2.4.3 port c pin assignment re gisters (pparc)......................................................... 45-11 45.2.4.4 port d pin assignment re gisters (ppard) ........................................................ 45-12 45.2.5 port special options registers (psor x ) ................................................................. 45-13 45.2.5.1 port a special options re gister (psora ) ......................................................... 45-13 45.2.5.2 port b special options re gisters (psorb) ........................................................ 45-14 45.2.5.3 port c special options re gisters (psorc) ........................................................ 45-14 45.2.5.4 port d special options re gisters (psord)........................................................ 45-15 45.3 port block diag ram ..................................................... ................................................ 45-1 6 45.4 port pin functions........................................................................................................ 4 5-17 45.4.1 general-purpose i/ o pins ........................................................................................ 45-17 45.4.2 dedicated pins ......................................................................................................... 45 -17 45.5 port tables ................................................................................................................ ... 45-17 45.6 interrupts from port c.................................................................................................. 45- 26 appendix a mpc8541e a.1 mpc8541e overview..................................................................................................... a-1 a.1.1 key features .............................................................................................................. .a-2 a.2 how to use this book for the mpc8541e .................................................................... a-8 a.2.1 mpc8541e cpm memory map ................................................................................. a-9 a.2.2 mpc8541e parallel i/o po rt pin assignm ents ........................................................ a-15 a.2.3 chapter advisory fo r the mpc8541e ...................................................................... a-20 appendix b revision history b.1 changes from revision 1 to revision 2 ..........................................................................b-1 b.2 changes from revision 0 to revision 1 ........................................................................b-29 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 lx freescale semiconductor contents paragraph number title page number glossary index 1 register index (memory-mapped registers) index 2 general index index 3 cpm index 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor lxi figures figure number title page number figures 1-1 MPC8555E block di agram .................................................................................................... 1- 2 1-2 integrated security engine functional bl ocks...................................................................... 1-12 1-3 MPC8555E communications processor module (cpm) block diagram............................ 1-13 1-4 data processing with in the cpm.......................................................................................... 1-22 1-5 processing transactions acro ss the on-chip fa bric............................................................ 1-22 2-1 local memory map example ................................................................................................. 2-2 2-2 local access window n base address registers (lawbar0?lawbar7) ....................... 2-5 2-3 local access window n attributes registers (lawar0?lawar7) ................................... 2-6 2-4 top-level register map example .......................................................................................... 2-9 2-5 general utilities registers mapping to configuration, control, and status memory bloc k.................................................................................................................. 2 -11 2-6 pic mapping to configuration, contro l, and status memory block ................................... 2-12 2-7 cpm mapping to configuration, contro l, and status memory block ................................. 2-13 2-8 device-specific register mapping to configuration, control, and status memory bloc k.................................................................................................................. 2 -14 3-1 MPC8555E signal groupings................................................................................................. 3- 2 4-1 configuration, control, and status regist er base address regist er (ccsrbar)................ 4-5 4-2 alternate configurat ion base address regist er (altcbar) ............................................... 4-6 4-3 alternate configur ation attribute regist er (altcar) ......................................................... 4-6 4-4 boot page translation register (bptr) ................................................................................. 4-7 4-5 power-on reset sequence ..................................................................................................... 4-10 4-6 MPC8555E clock subsystem block diagram ..................................................................... 4-22 4-7 rtc and core timer facili ties clocking op tions ................................................................ 4-23 5-1 e500 core complex bl ock diagram ....................................................................................... 5-2 5-2 four-stage mu pipeline, s howing divide bypass................................................................. 5-7 5-3 three-stage load/store unit ................................................................................................. .5-8 5-4 instruction pipe line flow ................................................................................................... ... 5-13 5-5 gpr issue queu e (giq) ....................................................................................................... 5-14 5-6 e500 core programmin g model............................................................................................ 5-16 5-7 mmu structure ............................................................................................................... ...... 5-22 5-8 effective-to-real address translation flow......................................................................... 5-23 6-1 core register model ......................................................................................................... ...... 6-2 6-2 integer exception re gister (xer) .......................................................................................... 6- 8 6-3 condition register (cr) ..................................................................................................... .... 6-9 6-4 link register (lr) .......................................................................................................... ...... 6-11 6-5 count register (ctr) ........................................................................................................ ... 6-11 6-6 machine state regist er (msr) ............................................................................................. 6-1 1 6-7 processor id regi ster (pir)................................................................................................. .6-13 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 lxii freescale semiconductor figures figure number title page number 6-8 processor version regi ster (pvr) ........................................................................................ 6-13 6-9 system version regist er (svr) ... ......................................................................................... 6-1 4 6-10 timer control regi ster (tcr) .............................................................................................. 6 -14 6-11 timer status regi ster (tsr) ................................................................................................ .6-15 6-12 time base upper/lower re gisters (tbu/t bl)................................................................... 6-16 6-13 decrementer regist er (dec) ................................................................................................ 6 -16 6-14 decrementer auto-reload register (dec ar)..................................................................... 6-17 6-15 save/restore regist er 0 (srr0) ........................................................................................... 6- 17 6-16 save/restore regist er 1 (srr1) ........................................................................................... 6- 17 6-17 critical save/restore re gister 0 (csrr0) ........................................................................... 6-17 6-18 critical save/restore re gister 1 (csrr1) ........................................................................... 6-18 6-19 data exception address register (dea r) ........................................................................... 6-18 6-20 interrupt vector prefix register (ivpr) ............................................................................... 6-18 6-21 interrupt vector offset registers (ivor n ) ........................................................................... 6-18 6-22 exception syndrome re gister (esr).................................................................................... 6-19 6-23 machine check save/restore register 0 (mcsrr0)........................................................... 6-20 6-24 machine check save/restore register 1 (mcsrr1)........................................................... 6-20 6-25 machine check address register (mcar).......................................................................... 6-21 6-26 machine check syndrome register (mcsr) ....................................................................... 6-21 6-27 software-use sprs (sprg0? sprg7 and uspr g0)........................................................... 6-22 6-28 branch buffer entry addres s register (bbear) ................................................................ 6-23 6-29 branch buffer target addr ess register (bbtar)................................................................ 6-23 6-30 branch unit control and stat us register (b ucsr) ............................................................. 6-24 6-31 hardware implementation-depende nt register 0 (hid0).................................................... 6-25 6-32 hardware implementation-depende nt register 1 (hid1).................................................... 6-26 6-33 l1 cache control and status register 0 (l1csr0).............................................................. 6-28 6-34 l1 cache control and status register 1 (l1csr1).............................................................. 6-29 6-35 l1 cache configuration re gister 0 (l1cfg0)..................................................................... 6-30 6-36 l1 cache configuration re gister 1 (l1cfg1)..................................................................... 6-31 6-37 process id register s (pid0?pid2)....................................................................................... 6-32 6-38 mmu control and status re gister 0 (mmucsr0) ............................................................. 6-32 6-39 mmu configuration regi ster (mmucfg) ......................................................................... 6-32 6-40 tlb configuration regist er 0 (tlb0cfg) ......................................................................... 6-33 6-41 tlb configuration regist er 1 (tlb1cfg) ......................................................................... 6-34 6-42 mas register 0 (mas0) ...................................................................................................... 6-34 6-43 mas register 1 (mas1) ...................................................................................................... 6-35 6-44 mas register 2 (mas2) ...................................................................................................... 6-36 6-45 mas register 3 (mas3) ...................................................................................................... 6-37 6-46 mas register 4 (mas4) ...................................................................................................... 6-37 6-47 mas register 6 (mas6) ...................................................................................................... 6-38 6-48 debug control register 0 (dbcr0)..................................................................................... 6-39 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor lxiii figures figure number title page number 6-49 debug control register 1 (dbcr1)..................................................................................... 6-40 6-50 debug control register 2 (dbcr2)..................................................................................... 6-41 6-51 debug status regist er (dbsr) ............................................................................................. 6- 42 6-52 instruction address compare registers (iac1? iac2) ........................................................ 6-44 6-53 data address compare regi sters (dac1?da c2) ............................................................... 6-44 6-54 signal processing and embedded floating-point status and control register (spefsc r) ........................................................................................................ 6-44 6-55 accumulator (acc) .......................................................................................................... .... 6-46 6-56 performance monitor global control register 0 (pmgc0), user performance monitor global cont rol register 0 (upmgc0) ................................ 6-48 6-57 local control a registers (pmlca0?pml ca3), user local control a registers (upmlca0?upmlca3 ) .................................................................................................. 6-48 6-58 local control b registers (pmlcb0?p mlcb3)/user local control b registers (upmlcb0?upmlcb3 ).................................................................................................. 6-49 6-59 performance monitor counter regi sters (pmc0?pmc3)/user performance monitor counter registers (upmc0?upmc3 )............................................................... 6-50 7-1 l2 cache/sram conf iguration ............................................................................................. 7-1 7-2 cache organi zation...................... .................................................................................... ....... 7-3 7-3 256-kbyte l2 cache address conf iguration?full cache mode.......................................... 7-4 7-4 128-kbyte l2 cache address configurat ion?half sram, half cache mode.................... 7-5 7-5 data bus connecti on of ccb ................................................................................................. 7 -5 7-6 address bus connecti on of ccb............................................................................................ 7-6 7-7 l2 control regist er (l2ctl) ................................................................................................. 7-7 7-8 l2 cache external write address registers (l2cewar n )................................................. 7-10 7-9 l2 cache external write control registers (l2cewcr 0?l2cewcr3)........................... 7-10 7-10 l2 memory-mapped sram ba se address registers (l2srbar n )................................... 7-11 7-11 l2 error injection mask high register (l2err injhi) ...................................................... 7-13 7-12 l2 error injection mask low register (l2errinjlo) ...................................................... 7-13 7-13 l2 error injection mask cont rol register (l2e rrinjctl) ............................................... 7-14 7-14 l2 error capture data high re gister (l2captdatahi)................................................... 7-15 7-15 l2 error capture data low register (l2captdatalo) .................................................. 7-15 7-16 l2 error syndrome regi ster (l2captecc) ....................................................................... 7-15 7-17 l2 error detect regi ster (l2errdet) ............................................................................... 7-16 7-18 l2 error disable regi ster (l2errdis) ............................................................................... 7-17 7-19 l2 error interrupt enable register (l2err inten) ........................................................... 7-17 7-20 l2 error attributes capture register (l2errattr) .......................................................... 7-18 7-21 l2 error address capture register (l2erraddr) ........................................................... 7-19 7-22 l2 error control regi ster (l2errctl).............................................................................. 7-20 7-23 l2 cache line replacement algorithm ............................................................................... 7-26 8-1 e500 coherency module block diagram................................................................................ 8-1 8-2 ecm ccb address configurati on register (eebacr)........................................................ 8-3 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 lxiv freescale semiconductor figures figure number title page number 8-3 ecm ccb port configurati on register (eebpcr)............................................................... 8-4 8-4 ecm error detect re gister (eedr)....................................................................................... 8-4 8-5 ecm error enable re gister (eeer) ...................................................................................... 8-5 8-6 ecm error attributes captur e register (eea tr) ................................................................. 8-6 8-7 ecm error address capture register (eeadr) ................................................................... 8-7 9-1 ddr memory controller simp lified block diagram............................................................. 9-2 9-2 chip select bounds registers (cs n _bnds).......................................................................... 9-9 9-3 chip select confi guration register (cs n _config) ........................................................... 9-10 9-4 ddr sdram timing configuration register 1 (timing_cfg_1).................................. 9-11 9-5 ddr sdram timing configuration register 2 (timing_cfg_2).................................. 9-12 9-6 ddr sdram control configuration register (ddr_sdram_cfg) .............................. 9-13 9-7 ddr sdram mode configuration register (ddr_sdram_mode)............................. 9-15 9-8 ddr sdram interval configuration register (ddr_sdram _interval) .................. 9-15 9-9 ddr sdram clock control regist er (ddr_sdram_clk_cntl) .............................. 9-16 9-10 memory data path error injection mask high register (data_err_inject_hi) ......... 9-17 9-11 memory data path error injection mask low register (data_err_inject_lo)......... 9-17 9-12 memory data path error injection ma sk ecc register (ecc _err_inject) .................. 9-18 9-13 memory data path read capture hi gh register (capture_data_hi).......................... 9-19 9-14 memory data path read capture lo w register (capture_data_lo) ......................... 9-19 9-15 memory data path read capture ecc register (capture_ecc)................................... 9-20 9-16 memory error detect re gister (err_detect) ................................................................. 9-20 9-17 memory error disable regi ster (err_disable).............................................................. 9-21 9-18 memory error interrupt enable register (err_i nt_en)................................................... 9-22 9-19 memory error attributes capture register (capture_attributes)........................... 9-22 9-20 memory error addres s capture register (capture_address) ................................... 9-23 9-21 single-bit ecc memory error mana gement register (err_sbe) .................................... 9-24 9-22 ddr memory controller block diagra m ............................................................................ 9-25 9-23 typical dual data rate sdra m internal organi zation....................................................... 9-26 9-24 typical ddr sdram in terface signals .............................................................................. 9-27 9-25 example 256-mbyte ddr sdram c onfiguration with ecc............................................. 9-28 9-26 ddr sdram burst read timing?acttorw = 3, mcas latency = 2 ........................ 9-35 9-27 ddr sdram single-b eat (double-word) write timing?acttorw = 3 ..................... 9-35 9-28 ddr sdram burst write timing?acttorw = 4 ......................................................... 9-36 9-29 ddr sdram clock distri bution exampl e ......................................................................... 9-37 9-30 ddr sdram mode-set command timing ........................................................................ 9-37 9-31 registered ddr sdram dimm burst write timing ........................................................ 9-38 9-32 write timing adjustme nts example..................................................................................... 9-39 9-33 ddr sdram bank-staggered au to-refresh timing ......................................................... 9-40 9-34 ddr sdram power- down mode ...................................................................................... 9-41 9-35 ddr sdram self-refresh entry timing ........................................................................... 9-42 9-36 ddr sdram self-refresh exit timing ............................................................................. 9-42 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor lxv figures figure number title page number 10-1 MPC8555E interrupt source s block diagram...................................................................... 10-2 10-2 pass-through mode example ............................................................................................... 10- 5 10-3 feature reporting re gister (frr) ...................................................................................... 10-15 10-4 global configuration register (gcr) ................................................................................ 10-15 10-5 vendor identification re gister (vir).................................................................................. 10-16 10-6 processor initialization register (pir) ............................................................................... 10-17 10-7 ipi vector/prior ity register (ipivpr n ) .............................................................................. 10-17 10-8 spurious vector regi ster (svr) . ........................................................................................ 10-1 8 10-9 timer frequency reporting register (tfrr) .................................................................... 10-19 10-10 global timer current count registers (gtccr n )............................................................. 10-19 10-11 global timer base count register (gtbcr n )................................................................... 10-20 10-12 global timer vector/p riority register (gtvpr n ).............................................................. 10-21 10-13 global timer destination register (gtdr n ) ..................................................................... 10-21 10-14 example calculation for cascaded timers......................................................................... 10-22 10-15 timer control regi ster (tcr) ............................................................................................ 10 -23 10-16 irq_out summary register 0 (irqsr0) ........................................................................ 10-24 10-17 irq_out summary register 1 (irqsr1) ........................................................................ 10-25 10-18 critical interrupt summary register 0 (cis r0) ................................................................. 10-26 10-19 critical interrupt summary register 1 (cis r1) ................................................................. 10-26 10-20 performance monito r mask registers (pm n mr0)............................................................. 10-27 10-21 performance monito r mask registers (pm n mr1)............................................................. 10-28 10-22 message register s (msgrs) .............................................................................................. 10- 28 10-23 message enable regi ster (mer) ........................................................................................ 10-29 10-24 message status regi ster (msr).......................................................................................... 10- 30 10-25 external interrupt vector/priorit y registers (eivpr0?eivpr11)..................................... 10-31 10-26 external interrupt destinat ion registers (e idrs) .............................................................. 10-32 10-27 internal interrupt vector/pri ority registers (i ivprs) ......................................................... 10-33 10-28 internal interrupt destinat ion registers (iidrs) ................................................................ 10-34 10-29 messaging interrupt vector/prior ity registers (mivprs).................................................. 10-34 10-30 messaging interrupt destinati on registers (mid rs) ......................................................... 10-35 10-31 per-cpu register address dec oding in a four-core device............................................. 10-37 10-32 interprocessor interrupt dispatch registers (ipidr 0?ipidr3) ......................................... 10-38 10-33 processor current task prio rity register (ctpr) .............................................................. 10-38 10-34 processor who am i re gister (whoami)........................................................................ 10-39 10-35 processor interrupt acknowle dge register (iack) ........................................................... 10-40 10-36 end of interrupt re gister (eoi) .......................................................................................... 1 0-40 10-37 pic interrupt processing flow diagra m ............................................................................. 10-42 11-1 i 2 c block diag ram................................................................................................................ 11-1 11-2 i 2 c address register (i2cadr).. ......................................................................................... 11-5 11-3 i 2 c frequency divider regi ster (i2cfdr) .......................................................................... 11-6 11-4 i 2 c control register (i2ccr)............................................................................................... 11-7 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 lxvi freescale semiconductor figures figure number title page number 11-5 i 2 c status register (i2csr) ........ ......................................................................................... 11-9 11-6 i 2 c data register (i 2cdr) ................................................................................................. 11-10 11-7 i 2 c digital filter sampling rate register (i2cdfsrr) .....................................................11-11 11-8 i 2 c interface transaction protocol...................................................................................... 11-12 11-9 eeprom data format for one re gister preload command............................................. 11-19 11-10 eeprom c ontents ........................................................................................................... .. 11-19 11-11 example i 2 c interrupt service routin e flowchart ............................................................. 11-24 12-1 uart block di agram ......................................................................................................... . 12-2 12-2 receiver buffer register s (urbr0, urbr1)...................................................................... 12-6 12-3 transmitter holding regist ers (uthr0, uthr1)............................................................... 12-7 12-4 divisor most significant byte registers (udmb0, udmb1)............................................. 12-7 12-5 divisor least significant byte registers (udlb0, udlb1)............................................... 12-8 12-6 interrupt enable re gister (uier) ......................................................................................... 12 -9 12-7 interrupt id regi sters (uii r).............................................................................................. 12-10 12-8 fifo control registers (ufcr0, ufcr1) ........................................................................ 12-11 12-9 line control regist er (ulcr) .... ....................................................................................... 12-1 2 12-10 modem control regi ster (umcr) ..................................................................................... 12-14 12-11 line status regi ster (ulsr) .............................................................................................. 1 2-15 12-12 modem status regist er (umsr) . ....................................................................................... 12-16 12-13 scratch regist er (uscr) ................................................................................................... . 12-17 12-14 alternate function re gister (uafr) .................................................................................. 12-17 12-15 dma status regist er (udsr) ..... ....................................................................................... 12-1 8 12-16 uart bus interface transacti on protocol exam ple .......................................................... 12-20 13-1 local bus controller block diagram ................................................................................... 13-1 13-2 base registers (br n ) .......................................................................................................... 13-10 13-3 option registers (or n ) in gpcm mode............................................................................ 13-13 13-4 option registers (or n ) in upm mode .............................................................................. 13-15 13-5 option registers (or n ) in sdram mode......................................................................... 13-16 13-6 upm memory address re gister (mar) ............................................................................ 13-17 13-7 upm mode registers (m x mr)........................................................................................... 13-18 13-8 memory refresh timer prescale r register (mrtpr)........................................................ 13-20 13-9 upm data register (mdr) ................................................................................................ 13-2 1 13-10 sdram machine mode re gister (lsdmr) ..................................................................... 13-21 13-11 upm refresh time r (lurt) .............................................................................................. 13-2 3 13-12 lsrt sdram refresh timer (lsrt)............................................................................... 13-24 13-13 transfer error status register (ltesr) ............................................................................. 13-25 13-14 transfer error check disa ble register (ltedr)............................................................... 13-26 13-15 transfer error interrupt en able register (lteir).............................................................. 13-27 13-16 transfer error attributes register (ltea tr) .................................................................... 13-28 13-17 transfer error address register (ltear) ......................................................................... 13-29 13-18 local bus configur ation register....................................................................................... 13- 29 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor lxvii figures figure number title page number 13-19 clock ratio regist er (lcrr) ............................................................................................. 13 -31 13-20 basic operation of memory co ntrollers in the lbc .......................................................... 13-33 13-21 example of 8-bit gpcm writi ng 32 bytes to address 0x5420 ......................................... 13-35 13-22 basic lbc bus cycle with lale, ta, and lcs n ............................................................. 13-35 13-23 local bus to gpcm de vice interface ................................................................................ 13-37 13-24 gpcm basic read timing (xacs = 0, acs = 1x, trlx = 0, clkdiv = 4, 8) ............................................................................................................. 13-38 13-25 gpcm basic write timing (xacs = 0, acs = 00, csnt = 1, scy = 1, trlx = 0, clkdiv = 4 or 8) ....................................................................................... 13-43 13-26 gpcm relaxed timing read (xac s = 0, acs = 1x, scy = 1, ehtr = 0, trlx = 1)...................................................................................................................... 13 -44 13-27 gpcm relaxed timi ng back-to-back writes (xacs = 0, acs = 1x, scy = 0, csnt = 0, trlx = 1, clkdiv = 4 or 8)..................................................... 13-44 13-28 gpcm relaxed timing write (xac s = 0, acs = 10, scy = 0, csnt = 1, trlx = 1, clkdiv = 4 or 8) ....................................................................................... 13-45 13-29 gpcm relaxed timing write (xac s = 0, acs = 00, scy = 1, csnt = 1, trlx = 1, clkdiv = 4 or 8) ....................................................................................... 13-45 13-30 gpcm read followed by read (trl x = 0, ehtr = 0, fastest timing) ......................... 13-46 13-31 gpcm read followed by write (trl x = 0, ehtr = 1, 1-cycle extended hold time on read s) .............................................................................................................. 13- 47 13-32 external termination of gpcm acces s.............................................................................. 13-48 13-33 connection to a 32-bit sdram with 12 address lines.................................................... 13-49 13-34 sdram address mult iplexing ... ....................................................................................... 13-52 13-35 pretoact = 2 (2 cl ock cycles)...................................................................................... 13-53 13-36 acttorw = 2 (2 cl ock cycles)....................................................................................... 13-53 13-37 cl = 2 (2 cloc k cycles) ................................................................................................... .. 13-54 13-38 wrc = 2 (2 cloc k cycles) ................................................................................................. 1 3-54 13-39 rfrc = 4 (6 cloc k cycles) ................................................................................................ 1 3-55 13-40 bufcmd = 1, lcrr[b ufcmdc] = 2............................................................................. 13-55 13-41 sdram single-beat read, pa ge closed, cl = 3 .............................................................. 13-56 13-42 sdram single-beat read, pa ge hit, cl = 3 .................................................................... 13-56 13-43 sdram two-beat burst read, page closed, cl = 3........................................................ 13-56 13-44 sdram four-beat burst rea d, page miss, cl = 3........................................................... 13-56 13-45 sdram single-beat writ e, page hit................................................................................. 13-57 13-46 sdram three-beat writ e, page closed............................................................................ 13-57 13-47 sdram read-after-read pipeline d, page hit, cl = 3..................................................... 13-57 13-48 sdram write-after-write pi pelined, page hit................................................................. 13-57 13-49 sdram read-after-write pi pelined, page hit ................................................................. 13-58 13-50 sdram mode-set command........................................................................................ 13-58 13-51 sdram bank-staggered auto -refresh timing ................................................................ 13-59 13-52 user-programmable machine functional bloc k diagram.................................................. 13-60 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 lxviii freescale semiconductor figures figure number title page number 13-53 ram array i ndexing ........................................................................................................ .. 13-61 13-54 memory refresh timer requ est block diagram ............................................................... 13-62 13-55 upm clock scheme for lcrr[clkdiv] = 2................................................................... 13-65 13-56 upm clock scheme for lcrr [clkdiv] = 4 or 8 ........................................................... 13-65 13-57 ram array and signa l generation .................................................................................... 13-66 13-58 ram word field de scriptions ........................................................................................... 13-6 6 13-59 lcs n signal selectio n ........................................................................................................ 13-70 13-60 lbs signal selection .......................................................................................................... 13-7 0 13-61 upm read access da ta sampling...................................................................................... 13-73 13-62 effect of lupwait signal................................................................................................. 1 3-74 13-63 single-beat read acce ss to fpm dram .......................................................................... 13-76 13-64 single-beat write acce ss to fpm dram ......................................................................... 13-77 13-65 burst read access to fpm dram us ing loop (two beats shown).............................. 13-78 13-66 refresh cycle (cbr) to fpm dram ................................................................................ 13-79 13-67 exception cycle ........................................................................................................... ....... 13-80 13-68 multiplexed addres s/data bus ........................................................................................... 13- 81 13-69 local bus periphera l hierarchy .......................................................................................... 13 -82 13-70 local bus peripheral hierarchy for very high bus speeds ............................................... 13-83 13-71 gpcm address timings ..................................................................................................... 1 3-83 13-72 gpcm data timings......................................................................................................... .. 13-84 13-73 interface to different port-size devices ............................................................................. 13-86 13-74 128-mbyte sdram di agram............................................................................................. 13-90 13-75 sdram power-down timing............................................................................................ 13-94 13-76 sdram self-refresh mode timing .................................................................................. 13-95 13-77 local bus dll operation................................................................................................... 13-97 13-78 parity support fo r sdram................................................................................................. 1 3-98 13-79 interface to zbt sram ..................................................................................................... 13-99 13-80 msc8101 hdi16 periphera l registers............................................................................. 13-101 13-81 interface to msc 8101 hdi16........................................................................................... 13-10 2 13-82 interface to msc8102 dsi in asynchronous mode ......................................................... 13-105 13-83 asynchronous write to msc8102 dsi............................................................................. 13-106 13-84 asynchronous read fro m msc8102 dsi......................................................................... 13-107 13-85 interface to msc8102 dsi in synchronous mode ........................................................... 13-108 13-86 upm synchronizati on cycle ............................................................................................ 13-10 9 13-87 synchronous single write to msc8102 dsi.................................................................... 13-110 13-88 synchronous single read fr om msc8102 dsi.................................................................13-111 13-89 synchronous burst write to msc8102 dsi ..................................................................... 13-112 13-90 synchronous burst read fr om msc8102 dsi ................................................................. 13-113 13-91 interface to texas instruments eh pi in non-multiplexed mode ..................................... 13-116 13-92 ehpi non-multiplexed read timings.............................................................................. 13-116 13-93 ehpi non-multiplexed write timings............................................................................. 13-117 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor lxix figures figure number title page number 14-1 ethernet protocol in relation to the osi pr otocol stack ...................................................... 14-2 14-2 ieee 802.3z and 802.3ab physic al standards ...................................................................... 14-3 14-3 ethernet/ieee 802.3 standard frame structure ................................................................... 14-3 14-4 ethernet/ieee 802.3 sta ndard frame structure with more details..................................... 14-4 14-5 tsec block di agram ......................................................................................................... .. 14-6 14-6 ievent register definition .............................................................................................. 14- 20 14-7 imask register definition ................................................................................................ 14 -23 14-8 error disabled regi ster (edis) .......................................................................................... 14- 24 14-9 ecntrl register de finition ...... ....................................................................................... 14-2 5 14-10 minflr register definition .............................................................................................. 14 -26 14-11 ptv register definition ................................................................................................... ... 14-26 14-12 dmactrl register definition .. ....................................................................................... 14-27 14-13 tbipa register definition................................................................................................. . 14-29 14-14 fifo_pause_ctrl regist er definition.......................................................................... 14-30 14-15 fifo_tx_thr register definition ................................................................................... 14-30 14-16 fifo_tx_starve regist er definition ............................................................................ 14-31 14-17 fifo_tx_starve_shutoff re gister definition ........................................................ 14-32 14-18 tctrl register definition ................................................................................................ 1 4-32 14-19 tstat register definition ................................................................................................. 14-33 14-20 tbdlen register definition ............................................................................................. 14- 34 14-21 txic register definition .................................................................................................. .. 14-34 14-22 ctbptr register definition .............................................................................................. 14 -35 14-23 tbptr register definition................................................................................................. 14-36 14-24 tbase register definition ................................................................................................ 1 4-36 14-25 ostbd register definition ................................................................................................ 1 4-37 14-26 ostbdp register definition .............................................................................................. 14 -38 14-27 rctrl register definition ................................................................................................ 1 4-39 14-28 rstat register definition ................................................................................................. 14-40 14-29 rbdlen register definition ............................................................................................. 14- 40 14-30 rxic register definition .................................................................................................. . 14-41 14-31 crbptr register definition .............................................................................................. 14 -42 14-32 mrbl register definition.................................................................................................. 14-42 14-33 rbptr register definition ................................................................................................ 1 4-43 14-34 rbase register definition ................................................................................................ 1 4-44 14-35 maccfg1 register definition .......................................................................................... 14-47 14-36 maccfg2 register definition .......................................................................................... 14-48 14-37 ipgifg register definition ................................................................................................ 14-49 14-38 half-duplex register definition ......................................................................................... 14 -50 14-39 maximum frame length regi ster definition..................................................................... 14-51 14-40 mii management configurati on register defi nition ......................................................... 14-52 14-41 miimcom register definition .......................................................................................... 14-53 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 lxx freescale semiconductor figures figure number title page number 14-42 miimadd register definition ... ....................................................................................... 14-53 14-43 mii management control re gister defini tion.................................................................... 14-54 14-44 miimstat register definition .......................................................................................... 14-5 5 14-45 mii management indicator register defini tion ................................................................. 14-55 14-46 interface status regi ster defini tion .................................................................................... 14 -56 14-47 station address part 1 re gister definition ......................................................................... 14-57 14-48 station address part 2 re gister definition ......................................................................... 14-57 14-49 transmit and receive 64-byte fr ame register defi nition................................................. 14-58 14-50 transmit and receive 65- to 127-by te frame register definition .................................... 14-58 14-51 transmit and receive 128- to 255-by te frame register definition .................................. 14-59 14-52 transmit and receive 256- to 511-by te frame register definition................................... 14-59 14-53 transmit and receive 512- to 1023-by te frame register definition ................................ 14-60 14-54 transmit and receive 1024- to 1518-by te frame register definition .............................. 14-60 14-55 transmit and receive 1519- to 1522-byte vlan frame register definition .................. 14-61 14-56 receive byte counter re gister defini tion.......................................................................... 14-61 14-57 receive packet counter re gister definition ...................................................................... 14-62 14-58 receive fcs error counter register defin ition................................................................. 14-62 14-59 receive multicast p acket counter register definition ...................................................... 14-63 14-60 receive broadcast packet count er register defi nition ..................................................... 14-63 14-61 receive control frame packet c ounter register de finition .............................................. 14-64 14-62 receive pause frame packet count er register definition ................................................. 14-64 14-63 receive unknown opcode packet c ounter register definition ........................................ 14-65 14-64 receive alignment error counter register definition....................................................... 14-65 14-65 receive frame length error count er register definition ................................................. 14-66 14-66 receive code error counter register definition ............................................................... 14-66 14-67 receive carrier sense error count er register definition .................................................. 14-67 14-68 receive undersize packet count er register defi nition ..................................................... 14-67 14-69 receive oversize packet count er register defi nition ....................................................... 14-68 14-70 receive fragments counter register definition ................................................................ 14-68 14-71 receive jabber counter re gister defini tion....................................................................... 14-69 14-72 receive dropped packet counter register defi nition ....................................................... 14-69 14-73 transmit byte counter re gister defini tion ........................................................................ 14-70 14-74 transmit packet counter register definition ..................................................................... 14-70 14-75 transmit multicast packet count er register definition ..................................................... 14-71 14-76 transmit broadcast packet count er register defi nition .................................................... 14-71 14-77 transmit pause control frame c ounter register definition .............................................. 14-72 14-78 transmit deferral packet count er register defi nition....................................................... 14-72 14-79 transmit excessive deferral packet counter register definition...................................... 14-73 14-80 transmit single collision packet counter register definition .......................................... 14-73 14-81 transmit multiple collision packet counter register definition....................................... 14-74 14-82 transmit late collision packet counter register definition ............................................. 14-74 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor lxxi figures figure number title page number 14-83 transmit excessive collision packet counter register definition .................................... 14-75 14-84 transmit total collision count er register defi nition........................................................ 14-75 14-85 transmit drop frame counter register defi nition ............................................................ 14-76 14-86 transmit jabber frame counter register defi nition .......................................................... 14-76 14-87 transmit fcs error counter register defin ition ............................................................... 14-77 14-88 transmit control frame counter re gister defini tion ........................................................ 14-77 14-89 transmit oversized frame count er register definition .................................................... 14-78 14-90 transmit undersize frame count er register definition .................................................... 14-78 14-91 transmit fragment counter register defini tion ................................................................ 14-79 14-92 carry register 1 (car1) register defini tion..................................................................... 14-79 14-93 carry register 2 (car2) register defini tion..................................................................... 14-80 14-94 carry mask register 1 (cam1) register definition.......................................................... 14-82 14-95 carry mask register 2 (cam2) register definition.......................................................... 14-83 14-96 iaddr n register defini tion .............................................................................................. 14-84 14-97 gaddr n register defini tion............................................. ................................................ 14-85 14-98 attr register definition .................................................................................................. . 14-86 14-99 attreli register definition ............................................................................................. 14 -87 14-100 control register definition.............................................................................................. ... 14-88 14-101 status register definiti on ............................................................................................... .... 14-89 14-102 an advertisement regist er definition............................................................................... 14-90 14-103 an link partner base page abil ity register defi nition .................................................... 14-92 14-104 an expansion register definition ..................................................................................... 14-9 3 14-105 an next page transmit re gister defini tion ...................................................................... 14-94 14-106 an link partner ability next pa ge register defi nition .................................................... 14-95 14-107 extended status regi ster definition ................................................................................... 14- 96 14-108 jitter diagnostics re gister definition ................................................................................. 14 -97 14-109 tbi control register definition ......................................................................................... 1 4-98 14-110 tsec-mii c onnection ...................................................................................................... 14-100 14-111 tsec-gmii c onnection ................................................................................................... 14 -101 14-112 tsec-rgmii conne ction ................................................................................................ 14-1 02 14-113 tsec-tbi c onnection...................................................................................................... 14-103 14-114 tsec-rtbi c onnection ................................................................................................... 14 -104 14-115 ethernet address recogni tion flowchart ......................................................................... 14-113 14-116 example of tsec memory structure for bd................................................................... 14-121 14-117 buffer descri ptor ring................................................................................................... ... 14-121 14-118 transmit buffer descript or ............................................................................................... 14-122 14-119 receive buffer descriptor................................................................................................ . 14-124 15-1 dma block diagram.......................................................................................................... .. 15-1 15-2 dma operational fl ow chart .............................................................................................. 15- 4 15-3 dma signal su mmary......................................................................................................... . 15-5 15-4 dma mode registers (mr n ) ............................................................................................... 15-9 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 lxxii freescale semiconductor figures figure number title page number 15-5 status registers (sr n )......................................................................................................... 15-11 15-6 basic chaining mode flow chart....................................................................................... 15-13 15-7 current link descriptor address registers (clndar n ) .................................................. 15-14 15-8 source attributes registers (satr n ) ................................................................................. 15-14 15-9 source address registers (sar n ) ...................................................................................... 15-15 15-10 destination attributes registers (datr n ) ......................................................................... 15-16 15-11 destination address registers (dar n ) .............................................................................. 15-17 15-12 byte count registers (bcr n )............................................................................................. 15-17 15-13 next link descriptor address registers (nlndar n ) ...................................................... 15-18 15-14 current list descriptor address registers (clsdar n ) .................................................... 15-18 15-15 next list descriptor address registers (nlsdar n ) ........................................................ 15-19 15-16 source stride registers (ssr n ) .......................................................................................... 15-20 15-17 destination stride registers (dsr n ) .................................................................................. 15-20 15-18 dma general status re gister (dgsr) .............................................................................. 15-21 15-19 external control in terface timing ...................................................................................... 15- 27 15-20 stride size and st ride distance ........................................................................................... 15-30 15-21 dma transaction flow with dma descript ors ................................................................ 15-32 15-22 list descript or format .................................................................................................... .... 15-33 15-23 link descript or format.................................................................................................... ... 15-33 15-24 dma data paths ............................................................................................................ ..... 15-35 16-1 pci controller bl ock diagram ............................................................................................. 16 -2 16-2 pci interface exte rnal signals ............................................................................................. . 16-7 16-3 pci cfg_addr re gister .................................................. ................................................ 16-1 7 16-4 pci cfg_data register ............ ....................................................................................... 16- 18 16-5 pci int_ack re gister ...................................................................................................... 1 6-19 16-6 pci outbound translation address regist ers .................................................................... 16-20 16-7 pci outbound translation exte nded address regi sters .................................................... 16-20 16-8 pci outbound window base address registers ................................................................ 16-21 16-9 pci outbound window attributes register 0 (d efault)..................................................... 16-22 16-10 pci outbound window attri butes register s 1?4 ............................................................... 16-22 16-11 pci inbound translation a ddress registers ....................................................................... 16-25 16-12 pci inbound window base a ddress registers................................................................... 16-25 16-13 pci inbound window base extende d address regist ers................................................... 16-26 16-14 pci inbound window attribut es registers......................................................................... 16-27 16-15 pci error detect regi ster (err_d r) ................................................................................ 16-29 16-16 pci error capture disable re gister (err_cap_dr) ....................................................... 16-30 16-17 pci error enable regi ster (err_en)................................................................................ 16-31 16-18 pci error attributes capture register (err_attrib)..................................................... 16-32 16-19 pci error address capture register (err_a ddr) .......................................................... 16-33 16-20 pci error extended address captur e register (err_ext_addr) ................................ 16-33 16-21 pci error data low captur e register (err _dl) ............................................................. 16-34 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor lxxiii figures figure number title page number 16-22 pci error data high captur e register (err_dh) ............................................................ 16-34 16-23 pci gasket timer regi ster (gas_tim r).......................................................................... 16-35 16-24 MPC8555E pci configur ation header............................................................................... 16-36 16-25 pci vendor id register .................................................................................................... .. 16-36 16-26 pci device id register.................................................................................................... ... 16-37 16-27 pci bus command register ............................................................................................... 16- 37 16-28 pci bus status register ................................................................................................... ... 16-39 16-29 pci revision id register.................................................................................................. .. 16-40 16-30 pci bus programming in terface register........................................................................... 16-40 16-31 pci subclass c ode regist er................................................................................................ 16-41 16-32 pci bus base class code register ..................................................................................... 16-41 16-33 pci bus cache line size register...................................................................................... 16-4 1 16-34 pci bus latency time r register . ....................................................................................... 16-4 2 16-35 pci configuration and status register base address register (pcsrbar) .................... 16-43 16-36 32?bit memory base a ddress register.............................................................................. 16-43 16-37 64-bit low memory base address regist er ...................................................................... 16-44 16-38 64-bit high memory base address regist er ..................................................................... 16-44 16-39 pci subsystem vendor id register .................................................................................... 16-45 16-40 pci subsystem id register................................................................................................. 16-45 16-41 pci bus capabilities pointer register ................................................................................ 16-46 16-42 pci bus interrupt li ne register.......................................................................................... 1 6-46 16-43 pci bus interrupt pin register............................................................................................ 16-47 16-44 pci bus minimum gr ant register...................................................................................... 16-47 16-45 pci bus maximum late ncy register ................................................................................. 16-47 16-46 pci bus functi on register................................................................................................. . 16-48 16-47 pci bus arbiter config uration register ............................................................................. 16-48 16-48 pci arbitrati on example ................................................................................................... . 16-51 16-49 pci single-beat read transaction...................................................................................... 16-5 8 16-50 pci burst read transaction................................................................................................ 16-58 16-51 pci single-beat writ e transaction..................................................................................... 16-5 9 16-52 pci burst write transactio n ............................................................................................... 16-59 16-53 pci target-initiated terminations....................................................................................... 16 -62 16-54 dac single-beat r ead example ........................................................................................ 16-64 16-55 dac burst read example .................................................................................................. 16 -64 16-56 dac single-beat wr ite example ....................................................................................... 16-64 16-57 dac burst write example ................................................................................................. 16 -65 16-58 standard pci confi guration header ................................................................................... 16-66 16-59 pci type 0 configurat ion translation ................................................................................ 16-69 16-60 pci parity op eration ...................................................................................................... ..... 16-73 17-1 sec connected to MPC8555E internal bus......................................................................... 17-3 17-2 sec functiona l modules ..................................................................................................... . 17-3 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 lxxiv freescale semiconductor figures figure number title page number 17-3 descriptor format .......................................................................................................... ..... 17-15 17-4 header dword ............................................................................................................... ...... 17-15 17-5 pointer dw ord .............................................................................................................. ....... 17-18 17-6 link table entr y format.................................................................................................... . 17-20 17-7 descriptors, link tables, and data par cels ........................................................................ 17-22 17-8 pkeu mode register (pkeumr) ..................................................................................... 17-25 17-9 pkeu key size register (pkeuksr) .............................................................................. 17-26 17-10 pkeu ab size regist er (pkeuabs)................................................................................ 17-27 17-11 pkeu data size regi ster (pkeudsr).............................................................................. 17-28 17-12 pkeu reset control re gister (pkeurcr)....................................................................... 17-28 17-13 pkeu status regist er (pkeusr) ...................................................................................... 17-29 17-14 pkeu interrupt status re gister (pkeuisr)...................................................................... 17-30 17-15 pkeu interrupt control re gister (pkeui cr) ................................................................... 17-31 17-16 pkeu eu-go register (pkeueug) ................................................................................. 17-32 17-17 deu mode register (deumr).......................................................................................... 17-33 17-18 deu key size regist er (deuksr) ................................................................................... 17-34 17-19 deu data size regi ster (deuds r) .................................................................................. 17-35 17-20 deu reset control regi ster (deurcr) ........................................................................... 17-36 17-21 deu status register (deusr).... ....................................................................................... 17-3 7 17-22 deu interrupt status re gister (deuis r) .......................................................................... 17-38 17-23 deu interrupt control re gister (deuic r) ....................................................................... 17-39 17-24 deu eu-go register (deueug) ..................................................................................... 17-41 17-25 afeu mode regist er (afeumr) ..................................................................................... 17-43 17-26 afeu key size regist er (afeuksr ) .............................................................................. 17-44 17-27 afeu data size regi ster (afeudsr).............................................................................. 17-45 17-28 afeu reset control regi ster (afeurcr)....................................................................... 17-45 17-29 afeu status regist er (afeusr) ...................................................................................... 17-46 17-30 afeu interrupt status re gister (afeuisr)...................................................................... 17-47 17-31 afeu interrupt control re gister (afeui cr) ................................................................... 17-49 17-32 afeu end of message re gister (afeuemr) .................................................................. 17-50 17-33 mdeu mode regist er (mdeumr)................................................................................... 17-52 17-34 mdeu key size regist er (mdeuksr)............................................................................ 17-53 17-35 mdeu data size regist er (mdeudsr ) ........................................................................... 17-54 17-36 mdeu reset control regi ster (mdeurcr) .................................................................... 17-54 17-37 mdeu status regist er (mdeusr).................................................................................... 17-55 17-38 mdeu interrupt status re gister (mdeui sr) ................................................................... 17-56 17-39 mdeu interrupt control re gister (mdeuicr) ................................................................ 17-57 17-40 mdeu eu-go register (mdeueug) .............................................................................. 17-59 17-41 mdeu context re gisters ................................................................................................... 1 7-60 17-42 rng mode register (rngmr) .. ....................................................................................... 17-62 17-43 rng data size regi ster (rngdsr).................................................................................. 17-62 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor lxxv figures figure number title page number 17-44 rng reset control regi ster (rngrcr)........................................................................... 17-63 17-45 rng status register (rngsr) ... ....................................................................................... 17-63 17-46 rng interrupt status re gister (rngisr).......................................................................... 17-64 17-47 rng interrupt control re gister (rngicr) ....................................................................... 17-65 17-48 rng eu-go register (rngeug) ..................................................................................... 17-66 17-49 aesu mode regist er (aesumr) ..................................................................................... 17-67 17-50 aesu key size regist er (aesuksr ) .............................................................................. 17-69 17-51 aesu data size regi ster (aesudsr).............................................................................. 17-70 17-52 aesu reset control re gister (aesurcr)....................................................................... 17-70 17-53 aesu status regist er (aesusr) ...................................................................................... 17-71 17-54 aesu interrupt status re gister (aesuisr)...................................................................... 17-72 17-55 aesu interrupt control re gister (aesui cr) ................................................................... 17-74 17-56 aesu end of messag e register ......................................................................................... 17-75 17-57 aesu context registers.................................................................................................... . 17-76 17-58 crypto-channel configurati on register (cccr)............................................................... 17-81 17-59 crypto-channel pointer status register (ccpsr) ............................................................. 17-83 17-60 crypto-channel current descriptor pointer register (cdpr)........................................... 17-89 17-61 fetch fifo ................................................................................................................ .......... 17-90 17-62 data packet descri ptor buffer ............................................................................................ 1 7-91 17-63 eu assignment status re gister (euasr ) ......................................................................... 17-93 17-64 interrupt mask regi ster (imr) ........................................................................................... 17 -94 17-65 interrupt status re gister (isr)........................................................................................... . 17-95 17-66 interrupt clear re gister (icr) ............................................................................................ 17-96 17-67 id register ............................................................................................................... ........... 17-97 17-68 master control regi ster (mcr) . ........................................................................................ 17-9 8 18-1 por pll status regist er (porpllsr) .............................................................................. 18-4 18-2 por boot mode status re gister (porbm sr) .................................................................... 18-5 18-3 por i/o impedance status and c ontrol register (porimpscr)....................................... 18-6 18-4 por device status regi ster (pordevs r) ......................................................................... 18-8 18-5 por debug mode status regi ster (pordbgm sr)............................................................ 18-9 18-6 por configuration regi ster (gpporcr ) ........................................................................... 18-9 18-7 general-purpose i/o control register (gpiocr).............................................................. 18-10 18-8 general-purpose output data register (gpoutdr) ........................................................ 18-11 18-9 general-purpose input data register (gpindr) ............................................................... 18-12 18-10 alternate function pin multiplex control register (pmuxcr) ....................................... 18-13 18-11 device disable regist er (devdisr)................................................................................. 18-14 18-12 power management control and st atus register (powmgtcsr) ................................... 18-16 18-13 machine check summary re gister (mcpsumr) ............................................................. 18-17 18-14 processor version re gister (pvr) ...................................................................................... 18-1 8 18-15 system version regi ster (svr) .......................................................................................... 18- 19 18-16 clock out control regi ster (clkocr)............................................................................. 18-19 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 lxxvi freescale semiconductor figures figure number title page number 18-17 local bus dll control re gister (lbdllcr) .................................................................. 18-20 18-18 e500 core power manageme nt state diag ram ................................................................... 18-22 18-19 MPC8555E power management handshaking si gnals...................................................... 18-26 19-1 performance monitor block diagra m................................................................................... 19-2 19-2 performance monitor global cont rol register (p mgc0).................................................... 19-5 19-3 performance monitor local cont rol register a0 (pmlca0) ............................................. 19-6 19-4 performance monitor local contro l a registers (pmlca1?pmlca8)............................ 19-6 19-5 performance monitor local cont rol register b0 (pmlcb0).............................................. 19-7 19-6 performance monitor local contro l register b (pmlcb1?pmlcb8) .............................. 19-8 19-7 performance monitor counte r register 0 (p mc0)............................................................... 19-9 19-8 performance monitor counter register (pmc1?p mc8) ................................................... 19-10 19-9 duration threshold event se quence timing diagram ....................................................... 19-12 19-10 burst size, distance, granularit y, and burstiness counting............................................... 19-13 19-11 burstiness counting ti ming diagram ................................................................................ 19-14 20-1 debug and watchpoint monito r block diagram .................................................................. 20-2 20-2 watchpoint monitor control register 0 (wmcr0) ........................................................... 20-11 20-3 watchpoint monitor control register 1 (wmcr1) ........................................................... 20-12 20-4 watchpoint monitor addre ss register (w mar) ............................................................... 20-13 20-5 watchpoint monitor address ma sk register (wmamr).................................................. 20-13 20-6 watchpoint monitor transaction mask register (wmtmr)............................................. 20-14 20-7 watchpoint monitor status register (w msr) ................................................................... 20-15 20-8 trace buffer control re gister 0 (tbcr0).......................................................................... 20-15 20-9 trace buffer control re gister 1 (tbcr1).......................................................................... 20-17 20-10 trace buffer address register (tbar).............................................................................. 20-18 20-11 trace buffer address mask register (tbamr) ................................................................ 20-18 20-12 trace buffer transaction ma sk register (tbtmr) ........................................................... 20-19 20-13 trace buffer status register (tbsr).................................................................................. 20-19 20-14 trace buffer access contro l register (tba cr) ............................................................... 20-20 20-15 trace buffer read high register (tbadhr).................................................................... 20-21 20-16 trace buffer access data register (tbadr) .................................................................... 20-21 20-17 programmed context id register (pci dr) ....................................................................... 20-22 20-18 current context id re gister (ccidr ) ............................................................................... 20-22 20-19 trigger out source re gister (tosr).................................................................................. 20-23 20-20 e500 coherency module dispatch (cmd) trace buffer entry .......................................... 20-28 20-21 ddr trace buffer entry .................................................................................................... . 20-28 20-22 pci trace buff er entry .................................................................................................... ... 20-29 21-1 MPC8555E cpm block diagram......................................................................................... 21-3 21-2 communications processor (c p) block diagram............................................................... 21-17 21-3 cpm error address re gister (cear) ................................................................................ 21-18 21-4 cpm error event register (ceer) .................................................................................... 21-19 21-5 cpm error mask regi ster (cemr).................................................................................... 21-20 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor lxxvii figures figure number title page number 21-6 risc controller c onfiguration register (rccr) .............................................................. 21-22 21-7 risc time-stamp control register (rtscr) ................................................................... 21-23 21-8 risc time-stamp regi ster (rtsr) ................................................................................... 21-24 21-9 cp command register (cpcr) .......................................................................................... 21-25 21-10 internal ram bloc k diagram ............................................................................................. 21- 29 21-11 internal instruction ram memory map............................................................................. 21-29 21-12 internal dual-port data ram memory map...................................................................... 21-30 21-13 risc timer table ram usage ... ....................................................................................... 21-33 21-14 risc timer command re gister (tm_cmd) .................................................................... 21-34 21-15 risc timer event register (r ter)/mask register (rtmr)............................................ 21-35 22-1 MPC8555E cpm interrupt structure.................................................................................... 22-2 22-2 interrupt request masking.................................................................................................. .. 22-6 22-3 cpm interrupt configurati on register (sicr) ..................................................................... 22-9 22-4 cpm high interrupt priority register (scprr _h)............................................................ 22-10 22-5 cpm low interrupt priority register (scprr_l)............................................................. 22-11 22-6 sipnr_h fi elds............................................................................................................. ..... 22-12 22-7 sipnr_l fi elds ............................................................................................................. ..... 22-12 22-8 simr_h regi ster............................................................................................................ .... 22-13 22-9 simr_l regi ster ............................................................................................................ .... 22-13 22-10 cpm interrupt vector re gister (sivec) ............................................................................ 22-14 22-11 interrupt table hand ling example ...................................................................................... 22-1 5 22-12 cpm external interrupt cont rol register (s iexr) ............................................................ 22-16 23-1 si block di agram........................................................................................................... ....... 23-1 23-2 various configurations of a single tdm channel ............................................................... 23-4 23-3 dual tdm channel example ............................................................................................... 23-5 23-4 enabling connections to the tsa......................................................................................... 23- 7 23-5 one tdm channel with static frames and independent rx an d tx routes ....................... 23-8 23-6 one tdm channel with shadow ra m for dynamic route change................................... 23-8 23-7 si2 ram entr y fields ....................................................................................................... ... 23-9 23-8 using the swtr feature .................................................................................................... 2 3-10 23-9 example: si2 ram dynamic changes, td ma and tdmc, same si2 ram size............ 23-13 23-10 si global mode regi sters (si2gmr)................................................................................. 23-14 23-11 si mode register s (si2mr) ............................................................................................... 23 -14 23-12 one-clock delay from sync to data ( x fsd = 01) ............................................................. 23-16 23-13 no delay from sync to data ( x fsd = 00).......................................................................... 23-17 23-14 falling edge (fe) effect when ce = 1 and x fsd = 01 ...................................................... 23-17 23-15 fe effect when ce = 0 and x fsd = 01 ............................................................................. 23-17 23-16 falling edge (fe) effect when ce = 1 and xfsd = 00..................................................... 23-18 23-17 falling edge (fe) ef fect when ce = 0 and x fsd = 00 ..................................................... 23-19 23-18 si2 ram shadow address registers (si2rsr) ................................................................ 23-20 23-19 si command register (si2cmdr) .................................................................................... 23-20 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 lxxviii freescale semiconductor figures figure number title page number 23-20 si status regist ers (si2str) .............................................................................................. 23-21 23-21 dual idl bus applic ation example ................................................................................... 23-22 23-22 idl terminal adaptor...................................................................................................... ... 23-23 23-23 idl bus si gnals ........................................................................................................... ....... 23-24 23-24 gci bus si gnals........................................................................................................... ....... 23-27 24-1 cpm multiplexing logic (c mx) block diag ram................................................................ 24-2 24-2 enabling connections to the tsa......................................................................................... 24- 3 24-3 bank of cl ocks............................................................................................................. ......... 24-4 24-4 cmx utopia address re gister (cmxuar) .................................................................... 24-6 24-5 multi-phy receive addr ess multiplexing........................................................................... 24-7 24-6 cmx si2 clock route regi ster (cmxsi2cr) .................................................................... 24-8 24-7 cmx fcc clock route re gister (cmxfcr) ..................................................................... 24-9 24-8 cmx scc clock route re gister (cmxscr) ................................................................... 24-10 24-9 cmx smc clock route re gister (cmxsmr) ................................................................. 24-13 25-1 baud-rate generator (brg ) block diagram ....................................................................... 25-1 25-2 system clock control re gister (sccr)............................................................................... 25-2 25-3 baud-rate generator conf iguration registers (brgc n )..................................................... 25-3 26-1 timer block diagram ........................................................................................................ ... 26-1 26-2 timer cascaded mode block diagram................................................................................. 26-3 26-3 timer global configuration register 1 (tgcr1) ................................................................ 26-4 26-4 timer global configuration register 2 (tgcr2) ................................................................ 26-5 26-5 timer mode register s (tmr1?tmr4)................................................................................ 26-6 26-6 timer reference regist ers (trr1?trr4)........................................................................... 26-7 26-7 timer capture registers (tcr1? tcr4) .............................................................................. 26-7 26-8 timer counter regist ers (tcn1?tcn4).............................................................................. 26-7 26-9 timer event register s (ter1?ter4) .................................................................................. 26-8 27-1 sdma data paths ............................................................................................................ ..... 27-1 27-2 sdma address error register s (smaer and lmaer) .................................................... 27-2 27-3 sdma event registers (s mevr and lmevr).................................................................. 27-2 27-4 sdma control registers (s mctr and lmctr) ............................................................... 27-3 28-1 scc block diagram.......................................................................................................... .... 28-2 28-2 gsmr_h?general scc mode re gister (high or der)....................................................... 28-3 28-3 gsmr_l?general scc mode re gister (low order)........................................................ 28-5 28-4 data synchronization re gister (dsr) .................................................................................. 28-9 28-5 transmit-on-demand regi ster (todr) ............................................................................... 28-9 28-6 scc buffer descri ptors (bds)............................................................................................ 28- 10 28-7 scc bd and buffer me mory structure .............................................................................. 28-11 28-8 function code registers (rfcr and tfcr) ..................................................................... 28-14 28-9 output delay from rts asserted for synchronous protocols ........................................... 28-16 28-10 output delay from cts asserted for synchronous protocols ........................................... 28-17 28-11 cts lost in synchronous protocols ................................................................................... 28-18 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor lxxix figures figure number title page number 28-12 using cd to control synchronous prot ocol reception...................................................... 28-19 28-13 dpll receiver bloc k diagram ... ....................................................................................... 28-20 28-14 dpll transmitter bl ock diagram...................................................................................... 28-21 28-15 dpll encoding examples.................................................................................................. 28 -22 29-1 uart characte r format ...................................................................................................... . 29-1 29-2 two uart multidrop configurations.................................................................................. 29-7 29-3 control character table .................................................................................................... .... 29-8 29-4 transmit out-of-sequence register (toseq) ..................................................................... 29-9 29-5 asynchronous uart tr ansmitter ...................................................................................... 29-10 29-6 protocol-specific mode regi ster for uart ( psmr) ........................................................ 29-13 29-7 scc uart receiving using rxbds ................................................................................. 29-15 29-8 scc uart receive buffer descriptor (r xbd) ................................................................ 29-16 29-9 scc uart transmit buffer descriptor (t xbd) ............................................................... 29-17 29-10 scc uart interrupt ev ent example ................................................................................. 29-19 29-11 scc uart event register (scce) and mask register (sccm) ..................................... 29-19 29-12 scc status register for uart mode (sccs) ................................................................... 29-20 30-1 hdlc framing st ructure..................................................................................................... . 30-2 30-2 hdlc address r ecognition ........ ......................................................................................... 30 -4 30-3 hdlc mode register (psmr)............................................................................................. 30-7 30-4 scc hdlc receive buffer descriptor (r xbd) .................................................................. 30-8 30-5 scc hdlc receiving using rxbds................................................................................. 30-10 30-6 scc hdlc transmit buffer descriptor (txbd) ............................................................... 30-11 30-7 hdlc event register (scce)/hdl c mask register (sccm) ........................................ 30-12 30-8 scc hdlc interrupt ev ent example................................................................................. 30-13 30-9 scc hdlc status regi ster (sccs)................................................................................... 30-13 30-10 typical hdlc bus multiple-m aster configurat ion ........................................................... 30-15 30-11 typical hdlc bus single-ma ster configurat ion............................................................... 30-16 30-12 detecting an hdlc bu s collision...................................................................................... 30-17 30-13 nonsymmetrical tx clock duty cy cle for increased pe rformance ................................... 30-17 30-14 hdlc bus transmission line configuration .................................................................... 30-18 30-15 delayed rts mode ............................................................................................................. 30-18 30-16 hdlc bus tdm transmission li ne configuration .......................................................... 30-19 31-1 classes of bisync frames .................................................................................................. 3 1-1 31-2 control character ta ble and rccm..................................................................................... 31-6 31-3 bisync sync (b sync) ................................................. .................................................. 31-7 31-4 bisync dle (b dle) ......................................................................................................... 3 1-8 31-5 protocol-specific mode regist er for bisync (psmr) ...................................................... 31-9 31-6 scc bisync rxbd .......................................................................................................... 31 -11 31-7 scc bisync transmit bd (txbd) .................................................................................. 31-13 31-8 bisync event register (scce)/bis ync mask register (sccm)................................. 31-14 31-9 scc status regist ers (sccs) ............................................................................................. 31- 15 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 lxxx freescale semiconductor figures figure number title page number 32-1 sending transparent frames between mpc 8555es ............................................................ 32-4 32-2 scc transparent receive buff er descriptor (rxbd) .......................................................... 32-8 32-3 scc transparent transmit buff er descriptor (txbd) ....................................................... 32-10 32-4 scc transparent event register (scce)/mask regist er (sccm).................................... 32-11 32-5 scc status register in tr ansparent mode (sccs) ............................................................ 32-12 33-1 localtalk fram e format..................................................................................................... .. 33-1 33-2 connecting the MPC8555E to localtalk ............................................................................. 33-3 34-1 qmc channel addressi ng capability .................................................................................. 34-1 34-2 qmc memory structure ....................................................................................................... 34-4 34-3 time-slot assignm ent table............................................................................................... 34 -10 34-4 time-slot assignment ta ble for 64-channel common rx and tx mapping .................... 34-12 34-5 rx time-slot assignment table for 32 channels over 2 sccs ........................................ 34-13 34-6 time-slot assignment tables fo r 64 channels over 2 sccs ............................................ 34-14 34-7 chamr?channel mode re gister (hdlc) ..................................................................... 34-16 34-8 tstate?tx internal state (hdlc) ................................................................................. 34-18 34-9 interrupt tabl e entry ...................................................................................................... ..... 34-18 34-10 intmsk ( hdlc)............................................................................................................. .. 34-19 34-11 rstate?rx internal state (hdlc)................................................................................. 34-19 34-12 chamr?channel mode register (transparent mode) ................................................... 34-21 34-13 tstate?tx internal state (transparent m ode)............................................................... 34-22 34-14 interrupt tabl e entry ..................................................................................................... ...... 34-23 34-15 intmsk (transpare nt mode) ............................................................................................ 34-23 34-16 examples of different t1 time-slot alloca tion................................................................. 34-26 34-17 rstate?rx internal state (transparent m ode) .............................................................. 34-26 34-18 circular interrupt table in external memory ..................................................................... 34-28 34-19 scc event register ........................................................................................................ .... 34-30 34-20 sccm regi ster ............................................................................................................. ...... 34-31 34-21 interrupt tabl e entry ..................................................................................................... ...... 34-32 34-22 channel interr upt flow .................................................................................................... ... 34-34 34-23 receive buffer desc riptor (rxbd)..................................................................................... 34-35 34-24 nonoctet alignm ent data ................................................................................................... 34-37 34-25 transmit buffer desc riptor (txbd) ................................................................................... 34-38 34-26 relation between pa d and nof........................................................................................ 34-39 35-1 usb inte rface.............................................................................................................. .......... 35-3 35-2 usb function bloc k diagram ............................................................................................. 35- 4 35-3 usb controller oper ating modes......................................................................................... 35-5 35-4 usb controller bl ock diagram ........................................................................................... 35- 8 35-5 usb controller oper ating modes......................................................................................... 35-9 35-6 endpoint pointer registers (ep n ptr) ................................................................................ 35-13 35-7 frame number (frame_n) in function mode?updated by usb controller................ 35-15 35-8 frame number (frame_n) in function m ode?updated by applic ation software ...... 35-15 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor lxxxi figures figure number title page number 35-9 usb function code registers (rfcr a nd tfcr)............................................................. 35-16 35-10 usb mode register (usmod) .......................................................................................... 35-17 35-11 usb slave address regi ster (usadr) ............................................................................. 35-18 35-12 usb endpoint registers (usep1?usep4) ........................................................................ 35-18 35-13 usb command regist er (uscom) ................................................................................... 35-19 35-14 usb event register (usber)..... ....................................................................................... 35-2 0 35-15 usb status regist er (usbs) .............................................................................................. 35 -21 35-16 usb start of frame timer (ussft)................................................................................... 35-22 35-17 usb memory st ructure...................................................................................................... . 35-23 35-18 usb receive buffer de scriptor (rxb d)............................................................................ 35-24 35-19 usb transmit buffer de scriptor (txb d)........................................................................... 35-26 35-20 usb transmit buffer de scriptor (txb d)........................................................................... 35-28 35-21 usb transaction buffer descriptor (t rbd) ....................................................................... 35-30 36-1 smc block di agram.......................................................................................................... ... 36-1 36-2 smc mode registers (s mcmr1, smcmr2) ..................................................................... 36-3 36-3 smc memory st ructure....................................................................................................... . 36-5 36-4 smc function code regist ers (rfcr, tfcr).................................................................... 36-8 36-5 smc uart frame format................................................................................................. 36-10 36-6 smc uart rxbd ............................................................................................................. 3 6-14 36-7 rxbd exam ple ............................................................................................................... .... 36-16 36-8 smc uart txbd.............................................................................................................. 36-17 36-9 smc uart event register (smc e)/mask register (smcm) ......................................... 36-18 36-10 smc uart interrupt s example......................................................................................... 36-19 36-11 synchronization with smsyn x .......................................................................................... 36-23 36-12 synchronization with the tsa ............................................................................................ 36 -24 36-13 smc transparent rxbd ..................................................................................................... 3 6-26 36-14 smc transparent txbd ..................................................................................................... 3 6-27 36-15 smc transparent event register (smce)/mask register (smcm) ................................. 36-28 36-16 smc monitor cha nnel rxbd............................................................................................. 36-32 36-17 smc monitor cha nnel txbd............................................................................................. 36-33 36-18 smc c/i channe l rxbd..................................................................................................... 3 6-33 36-19 smc c/i channe l txbd..................................................................................................... 3 6-34 36-20 smc gci event register (smc e)/mask register (smcm) ............................................. 36-34 37-1 fcc block diagram.......................................................................................................... .... 37-3 37-2 general fcc mode re gister (gfmr).................................................................................. 37-3 37-3 general fcc expansion mode register (gfemr) ............................................................. 37-7 37-4 fcc data synchronization register (fds r) ....................................................................... 37-8 37-5 fcc transmit-on-demand re gister (ftodr)..................................................................... 37-8 37-6 fcc memory structure....................................................................................................... .. 37-9 37-7 buffer descript or format................................................................................................... ... 37-9 37-8 function code register (fcr x ).......................................................................................... 37-12 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 lxxxii freescale semiconductor figures figure number title page number 37-9 output delay from rts asserted ....................................................................................... 37-16 37-10 output delay from cts asserted ....................................................................................... 37-17 37-11 cts lost .......................................................................................................................... ... 37-18 37-12 using cd to control recep tion .......................................................................................... 37-19 38-1 hdlc framing st ructure..................................................................................................... . 38-2 38-2 hdlc address recogni tion example .................................................................................. 38-5 38-3 hdlc mode register (fpsmr)........................................................................................... 38-8 38-4 fcc hdlc receiving using rxbds................................................................................. 38-10 38-5 fcc hdlc receive buffer descriptor (r xbd) ................................................................ 38-11 38-6 fcc hdlc transmit buffer descriptor (t xbd) ............................................................... 38-12 38-7 hdlc event register (fcce)/m ask register (f ccm) .................................................... 38-14 38-8 hdlc interrupt even t example .. ....................................................................................... 38-15 38-9 fcc status regist er (fccs)............................................................................................... 38 -16 39-1 in-line synchronizat ion pattern ........................................................................................... 3 9-2 39-2 sending transparent frames between mpc 8555es ............................................................ 39-4 40-1 ethernet frame structure ................................................................................................... ... 40-1 40-2 ethernet block diagram .................................................................................................... ... 40-2 40-3 connecting the MPC8555E to ethernet................................................................................ 40-4 40-4 connecting the MPC8555E to ethernet (rmii) ................................................................... 40-5 40-5 ethernet address recogni tion flowchar t ........................................................................... 40-16 40-6 general fcc expansion mode register (gfemr) ........................................................... 40-20 40-7 fcc ethernet mode register (fpsmr x )............................................................................ 40-21 40-8 ethernet event register (fcce) /mask register (fccm).................................................. 40-23 40-9 ethernet interrupt ev ents example ..................................................................................... 40-24 40-10 fast ethernet receive buffer (rxbd) ................................................................................ 40-25 40-11 ethernet receiving using rxbds....................................................................................... 40-27 40-12 fast ethernet transmit buffer (txbd) ............................................................................... 40-28 41-1 apc scheduling tabl e mechanism ...................................................................................... 41-9 41-2 vbr pacing using the gcra (l eaky bucket algorithm) ................................................ 41-11 41-3 external cam data i nput fields ........................................................................................ 41-13 41-4 external cam out put fields .............................................................................................. 41- 13 41-5 address compression mechanism...................................................................................... 41-15 41-6 general vcoffset formula fo r contiguous vclts ....................................................... 41-16 41-7 vp pointer address compression....................................................................................... 41-17 41-8 vc pointer address compression ...................................................................................... 41-18 41-9 atm address recogniti on flowchart ................................................................................ 41-19 41-10 MPC8555E abr basi c model .... ....................................................................................... 41-20 41-11 abr transm it flow ......................................................................................................... ... 41-22 41-12 abr transmit flow (continued) ........................................................................................ 41-23 41-13 abr transmit flow (continued) ........................................................................................ 41-24 41-14 abr receiv e flow .......................................................................................................... ... 41-25 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor lxxxiii figures figure number title page number 41-15 rate format for rm cells.................................................................................................. . 41-26 41-16 rate formula for rm cells................................................................................................. 41-26 41-17 performance monitoring cell st ructure (fmcs and brcs)............................................... 41-29 41-18 fmc, brc insertion ........................................................................................................ ... 41-32 41-19 format of user-def ined cells............................................................................................. 4 1-32 41-20 external cam address in ud c extended addre ss mode................................................. 41-33 41-21 atm-to-atm data forwarding.......................................................................................... 41-34 41-22 uead_offsets for extended addre sses in the udc extra header ............................... 41-38 41-23 vci filtering en able bits ................................................................................................. .. 41-38 41-24 global mode entry (gmode) .... ....................................................................................... 41-38 41-25 example of a 1024-entry recei ve connection table ......................................................... 41-40 41-26 receive connection tabl e (rct) entry ............................................................................. 41-41 41-27 aal5 protocol-spe cific rct............................................................................................. 41- 43 41-28 aal5-abr protocol-s pecific rct ................................................................................... 41-44 41-29 aal1 protocol-spe cific rct............................................................................................. 41- 45 41-30 aal0 protocol-spe cific rct............................................................................................. 41- 46 41-31 transmit connection ta ble (tct) entry ............................................................................ 41-48 41-32 aal5 protocol-spe cific tct ............................................................................................. 41- 51 41-33 aal1 protocol-spe cific tct ............................................................................................. 41- 51 41-34 aal0 protocol-spe cific tct ............................................................................................. 41- 53 41-35 transmit connection table extension (tcte)?vbr protocol-specific ......................... 41-54 41-36 ubr+ protocol-spe cific tcte .......................................................................................... 41-55 41-37 abr protocol-speci fic tcte ..... ....................................................................................... 41-5 6 41-38 oam performance moni toring table................................................................................. 41-58 41-39 atm pace control da ta structure ...................................................................................... 41-60 41-40 apc scheduling tabl e structure ........................................................................................ 41-6 1 41-41 control slot .............................................................................................................. ........... 41-61 41-42 transmit buffers and bd table example ........................................................................... 41-63 41-43 receive static buffer allocation exam ple ......................................................................... 41-64 41-44 receive global buffer allocation example ....................................................................... 41-65 41-45 free buffer pool structure ................................................................................................ .. 41-65 41-46 free buffer p ool entry .................................................................................................... .... 41-66 41-47 aal5 rxbd ................................................................................................................. ...... 41-67 41-48 aal1 rxbd ................................................................................................................. ...... 41-69 41-49 aal0 rxbd ................................................................................................................. ...... 41-70 41-50 user-defined cell?r xbd extension ................................................................................ 41-71 41-51 aal5 txbd ................................................................................................................. ...... 41-72 41-52 aal1 txbd ................................................................................................................. ...... 41-73 41-53 aal0 txbds ................................................................................................................ ...... 41-74 41-54 user-defined cell?t xbd extension ................................................................................ 41-75 41-55 aal1 sequence number (sn) protection ta ble ................................................................ 41-76 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 lxxxiv freescale semiconductor figures figure number title page number 41-56 interrupt queue structure................................................................................................. ... 41-77 41-57 interrupt queu e entry ..................................................................................................... .... 41-78 41-58 utopia master m ode signals.... ....................................................................................... 41-80 41-59 utopia slave mode signals ............................................................................................. 41-8 1 41-60 general fcc expansion mode register (gfemr) ........................................................... 41-83 41-61 fcc atm mode regi ster (fpsmr) .................................................................................. 41-84 41-62 atm event register (fcce)/fcc mask register (fccm) .............................................. 41-86 41-63 fcc transmit internal rate registers (ftirr x ) ............................................................... 41-87 41-64 fcc transmit internal rate clocking ................................................................................ 41-88 41-65 comm_info field ........................................................................................................... 41-89 41-66 fcc transmit internal rate port enable register (firper)............................................. 41-90 41-67 fcc internal rate event register (firer)........................................................................ 41-91 41-68 fcc internal rate sel ection register hi (firsr x _hi) ..................................................... 41-92 41-69 fcc internal rate sel ection register lo (firsr x _lo) ................................................... 41-93 41-70 fcc transmit internal rate register (ftirr)................................................................... 41-94 41-71 fcc transmit internal rate clocking ................................................................................ 41-94 42-1 aal2 data units ............................................................................................................ ...... 42-1 42-2 aal2 sublayer structure.................................................................................................... .. 42-2 42-3 aal2 switching example .................................................................................................... 4 2-2 42-4 round robin pr iority ....................................................................................................... ..... 42-6 42-5 fixed priori ty mode ........................................................................................................ ...... 42-7 42-6 cell in no-s tf mode ........................................................................................................ ... 42-8 42-7 aal2 protocol-specific transmit connection table (tct)................................................ 42-9 42-8 cps tx queue descri ptor (txqd) ..................................................................................... 42-13 42-9 buffer structure example for cps packet s......................................................................... 42-14 42-10 cps txbd.................................................................................................................. ......... 42-15 42-11 cps packet head er format ................................................................................................. 4 2-16 42-12 sssar tx queue descriptor.............................................................................................. 42- 16 42-13 sssar txbd ................................................................................................................ ..... 42-18 42-14 cid mapping pr ocess ....................................................................................................... .. 42-21 42-15 aal2 switch ing ............................................................................................................ ..... 42-22 42-16 aal2 protocol-specific receiv e connection table (rct)............................................... 42-23 42-17 cps rx queue descriptor ................................................................................................... 42-26 42-18 cps receive buffer descriptor .......................................................................................... 42- 27 42-19 cps switch rx queu e descriptor ...................................................................................... 42-29 42-20 switch receive/transmit buffer descriptor ....................................................................... 42-29 42-21 sssar rx queue de scriptor ...... ....................................................................................... 42-3 1 42-22 sssar receive buffer descriptor ..................................................................................... 42-32 42-23 udc header table.......................................................................................................... .... 42-37 42-24 aal2 interrupt queue entry cid 0 ................................................................................ 42-38 42-25 aal2 interrupt queue entry cid = 0 ................................................................................ 42-38 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor lxxxv figures figure number title page number 43-1 spi block di agram .......................................................................................................... ..... 43-1 43-2 single-master/m ulti-slave confi guration ............................................................................ 43-3 43-3 multiple-master c onfiguration ............................................................................................. 4 3-5 43-4 spmode?spi mode register ............................................................................................ 43-6 43-5 spi transfer format w ith spmode[cp] = 0....................................................................... 43-7 43-6 spi transfer format w ith spmode[cp] = 1....................................................................... 43-7 43-7 spie/spim?spi event/m ask registers .............................................................................. 43-9 43-8 spcom?spi command register ..................................................................................... 43-10 43-9 rfcr/tfcr?function code registers............................................................................ 43-12 43-10 spi memory structure...................................................................................................... ... 43-13 43-11 spi rxbd.................................................................................................................. .......... 43-14 43-12 spi txbd.................................................................................................................. .......... 43-15 44-1 i 2 c controller block diagram .............................................................................................. 44-1 44-2 i 2 c master/slave general configuratio n.............................................................................. 44-2 44-3 i 2 c transfer ti ming .............................................................................................................. 44-3 44-4 i 2 c master write ti ming ...................................................................................................... 44-3 44-5 i 2 c master read ti ming ....................................................................................................... 44-4 44-6 i 2 c mode register (i 2mod) ................................................................................................ 44-6 44-7 i 2 c address register (i2add) .... ......................................................................................... 44-7 44-8 i 2 c baud rate generator re gister (i2brg)......................................................................... 44-7 44-9 i2c event/mask register s (i2cer/i2cmr) ........................................................................ 44-8 44-10 i 2 c command register (i2com) ......................................................................................... 44-8 44-11 i 2 c function code registers (rfcr, tfcr)..................................................................... 44-10 44-12 i 2 c memory structure......................................................................................................... 44-1 2 44-13 i 2 c rxbd......................................................................................................................... ... 44-13 44-14 i 2 c txbd ......................................................................................................................... ... 44-14 45-1 port a open-drain re gisters (podra) ............................................................................... 45-2 45-2 port b open-drain re gisters (podrb) ............................................................................... 45-2 45-3 port c open-drain re gisters (podrc) ............................................................................... 45-3 45-4 port d open-drain re gisters (podrd) ............................................................................... 45-4 45-5 port a data regist ers (pdata) ........................................................................................... 45- 5 45-6 port b data regist ers (pdatb)............................................................................................ 45 -5 45-7 port c data regist ers (pdatc)............................................................................................ 45 -6 45-8 port d data regist ers (pdatd) ........................................................................................... 45- 6 45-9 port a data direction re gister (pdira) ............................................................................. 45-7 45-10 port b data direction register (pdirb) .............................................................................. 45-8 45-11 port c data direction register (pdirc) .............................................................................. 45-8 45-12 port d data direction register (pdird) ............................................................................. 45-9 45-13 port a pin assignment re gister (ppara) ......................................................................... 45-10 45-14 port b pin assignment re gister (pparb).......................................................................... 45-11 45-15 port c pin assignment re gister (pparc).......................................................................... 45-11 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 lxxxvi freescale semiconductor figures figure number title page number 45-16 port d pin assignment re gister (ppard) ......................................................................... 45-12 45-17 port a special options register (pso ra)......................................................................... 45-13 45-18 port b special options registers (psorb)........................................................................ 45-14 45-19 port c special options registers (psorc)........................................................................ 45-14 45-20 special options regi sters (psord)................................................................................... 45-15 45-21 port functional operation ................................................................................................. .. 45-16 45-22 primary and secondary option programmi ng .................................................................... 45-18 a-1 mpc8541e block di agram ................................................ ................................................... a-1 a-2 mpc8541e cpm block diagram.......................................................................................... a-8 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor lxxxvii tables table number title page number table s i acronyms and abbrevia ted terms..........................................................................................cxv 1-1 MPC8555E prot ocols.......................................................................................................... .. 1-24 1-2 peak cpm performance by protocol .................................................................................... 1-25 2-1 target interfac e codes ...................................................................................................... ...... 2-1 2-2 local access windows example............................................................................................ 2-2 2-3 format of atmu window definitions................................................................................... 2-3 2-4 local access register memory map...................................................................................... 2-5 2-5 lawbar n bit settings .......................................................................................................... 2-6 2-6 lawar n bit settings ............................................................................................................. 2-6 2-7 overlapping local ac cess windows ...................................................................................... 2-7 2-8 local memory configuration, control, and status register summary................................ 2-10 2-9 memory map.................................................................................................................. ....... 2-14 3-1 MPC8555E signal reference by functional block................................................................ 3-3 3-2 MPC8555E alphabetical si gnal reference ............................................................................ 3-8 3-3 MPC8555E reset configur ation signals.............................................................................. 3-14 3-4 output signal states duri ng system reset........................................................................... 3-15 4-1 signal summ ary .............................................................................................................. ........ 4-1 4-2 system control signals?detaile d signal descriptions ......................................................... 4-2 4-3 clock signals?detailed si gnal descriptions ........................................................................ 4-3 4-4 local configuration cont rol register map ............................................................................ 4-4 4-5 ccsrbar bit se ttings ........................................................................................................ .. 4-5 4-6 altcbar bit settings........................................................................................................ ... 4-6 4-7 altcar bit se ttings ......................................................................................................... .... 4-6 4-8 bptr bit se ttings ........................................................................................................... ........ 4-8 4-9 ccb clock pl l ratio ......................................................................................................... .4-12 4-10 e500 core clock pll ratios ................................................................................................ 4 -12 4-11 boot rom lo cation.......................................................................................................... .... 4-13 4-12 host/agent conf iguration................................................................................................... .. 4-14 4-13 cpu boot conf iguration..................................................................................................... .. 4-14 4-14 boot sequencer c onfiguration .............................................................................................. 4 -15 4-15 tsec width conf iguration ................................................................................................... 4-15 4-16 tsec1 protocol c onfiguration ............................................................................................. 4- 16 4-17 tsec2 protocol c onfiguration ............................................................................................. 4- 16 4-18 pci1 clock select .......................................................................................................... ....... 4-16 4-19 pci2 clock select .......................................................................................................... ....... 4-17 4-20 pci-32 confi guration....................................................................................................... ..... 4-17 4-21 pci1 i/o im pedance......................................................................................................... ..... 4-17 4-22 pci2 i/o im pedance......................................................................................................... ..... 4-18 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 lxxxviii freescale semiconductor tables table number title page number 4-23 pci1 arbiter c onfiguratio n ................................................................................................. .4-18 4-24 pci2 arbiter c onfiguratio n ................................................................................................. .4-18 4-25 pci debug confi guration .................................................................................................... .4-18 4-26 memory debug config uration.............................................................................................. 4-1 9 4-27 ddr debug confi guration ................................................................................................... 4 -19 4-28 pci1 output hold configuratio n .......................................................................................... 4-2 0 4-29 pci2 output hold configuratio n .......................................................................................... 4-2 0 4-30 local bus output hold configuration.................................................................................. 4-20 4-31 general-purpose por configuratio n.................................................................................... 4-21 5-1 device revision level cr oss-reference ................................................................................ 5-4 5-2 performance monitor instructions ........................................................................................ 5-10 5-3 cache locking in structions .................................................................................................. 5-10 5-4 scalar and vector embedded floa ting-point instructions .................................................... 5-11 5-5 btb locking instructions.................................................................................................... .5-11 5-6 interrupt re gisters......................................................................................................... ........ 5-19 5-7 interrupt vector registers and exception conditions........................................................... 5-20 5-8 differences between the e500 core and th e powerquicc iii core implementation ........ 5-29 6-1 base and embedded category special-purpos e registers (by spr abbreviation)................ 6-4 6-2 additional sprs (by spr abbreviation) ................................................................................ 6-7 6-3 xer field desc ription....................................................................................................... ..... 6-8 6-4 bi operand settings for cr fields ......................................................................................... 6- 9 6-5 cr0 bit desc riptions ........................................................................................................ .... 6-10 6-6 msr field desc riptions...................................................................................................... .. 6-11 6-7 pvr field desc riptions ...................................................................................................... .. 6-14 6-8 svr field desc riptions ...................................................................................................... .. 6-14 6-9 tcr field desc riptions ...................................................................................................... .. 6-15 6-10 tsr field desc riptions ..................................................................................................... .... 6-16 6-11 ivor assi gnments ........................................................................................................... .... 6-18 6-12 esr field desc riptions ..................................................................................................... .... 6-19 6-13 mcsr field de scriptions .................................................................................................... .6-21 6-14 spr assignm ents ............................................................................................................ ..... 6-22 6-15 bbear field de scriptions ................................................................................................... 6-23 6-16 bbtar field de scriptions ................................................................................................... 6-23 6-17 bucsr field de scriptions ................................................................................................... 6-24 6-18 hid0 field descriptions .................................................................................................... ... 6-25 6-19 hid1 field descriptions .................................................................................................... ... 6-26 6-20 l1csr0 field de scriptions .................................................................................................. 6-28 6-21 l1csr1 field de scriptions .................................................................................................. 6-29 6-22 l1cfg0 field de scriptions .................................................................................................. 6-30 6-23 l1cfg1 field de scriptions .................................................................................................. 6-31 6-24 mmucsr0 field desc riptions............................................................................................. 6-32 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor lxxxix tables table number title page number 6-25 mmucfg field desc riptions .............................................................................................. 6-33 6-26 tlb0cfg field de scriptions ............................................................................................... 6- 33 6-27 tlb1cfg field de scriptions ............................................................................................... 6- 34 6-28 mas0 field descriptions?mmu read/w rite and replacement control .......................... 6-35 6-29 mas1 field descriptions ?descriptor context and conf iguration control........................ 6-35 6-30 mas2 field descriptions?epn and page attr ibutes ......................................................... 6-36 6-31 mas3 field descriptions?rpn and access control ........................................................... 6-37 6-32 mas4 field descriptions?hardware re placement assist c onfiguration.......................... 6-38 6-33 mas6?tlb search cont ext register 0.............................................................................. 6-38 6-34 dbcr0 field de scriptions ................................................................................................... 6-39 6-35 dbcr1 field de scriptions ................................................................................................... 6-40 6-36 dbcr2 field de scriptions ................................................................................................... 6-41 6-37 dbsr field de scriptions .................................................................................................... .. 6-43 6-38 spefscr field desc riptions................................................................................................ 6 -44 6-39 acc field desc riptions..................................................................................................... ... 6-46 6-40 supervisor-level pmrs (pmr[5] = 1) ................................................................................. 6-47 6-41 user-level pmrs (pmr[5] = 0) (read on ly)...................................................................... 6-47 6-42 pmgc0 field de scriptions ................................................................................................... 6-48 6-43 pmlca0?pmlca3 field descriptions ................................................................................. 6-49 6-44 pmlcb0?pmlcb3 field descriptions ................................................................................ 6-50 6-45 pmc0?pmc3 field de scriptions ......................................................................................... 6-50 7-1 l2/sram memory-mappe d registers................................................................................... 7-6 7-2 l2ctl field de scriptions .................................................................................................... .. 7-8 7-3 l2cewar n field descript ions............................................................................................ 7-10 7-4 l2cewcr n field descript ions............................................................................................ 7-11 7-5 l2srbar n field descripti ons............................................................................................. 7-12 7-6 l2errinjhi field de scriptions .......................................................................................... 7-13 7-7 l2errinjlo field de scriptions ......................................................................................... 7-14 7-8 l2errinjctl field de scriptions....................................................................................... 7-14 7-9 l2captdatahi field descriptions ................................................................................... 7-15 7-10 l2captdatalo field descriptions .................................................................................. 7-15 7-11 l2captecc field de scriptions . ......................................................................................... 7-16 7-12 l2errdet field desc riptions ............................................................................................ 7-16 7-13 l2errdis field de scriptions .............................................................................................. 7- 17 7-14 l2errinten field descriptions ........................................................................................ 7-18 7-15 l2errattr field de scriptions . ......................................................................................... 7-18 7-16 l2erraddr field descriptions......................................................................................... 7-19 7-17 l2errctl field desc riptions ............................................................................................ 7-20 7-18 fastest read timing? hit in l2 .. ......................................................................................... 7-2 1 7-19 plru bit update algorithm ................................................................................................ 7- 27 7-20 plru-based victim sele ction mechanism .......................................................................... 7-28 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 xc freescale semiconductor tables table number title page number 7-21 l2 cache states............................................................................................................ ......... 7-28 7-22 state transitions due to core -initiated transa ctions ........................................................... 7-29 7-23 state transitions due to syst em-initiated transa ctions ....................................................... 7-32 8-1 ecm memory map .............................................................................................................. ... 8-2 8-2 eebacr field desc riptions .................................................................................................. 8 -3 8-3 eebpcr field de scriptions ................................................................................................... 8-4 8-4 eedr field desc riptions ..................................................................................................... ... 8-5 8-5 eeer field desc riptions ..................................................................................................... ... 8-5 8-6 eeatr field de scriptions.................................................................................................... .. 8-6 8-7 eeadr field de scriptions .................................................................................................... .8-7 9-1 ddr memory interface signal summary .............................................................................. 9-3 9-2 memory address signal mappings......................................................................................... 9-4 9-3 memory interface signals?deta iled signal descri ptions ..................................................... 9-5 9-4 clock signals?detailed si gnal descriptions ........................................................................ 9-8 9-5 ddr memory controller memory map ................................................................................. 9-8 9-6 cs n _bnds field descri ptions............................................................................................. 9-10 9-7 cs n _config field desc riptions ........................................................................................ 9-10 9-8 timing_cfg_1 field descriptions .................................................................................... 9-11 9-9 timing_cfg_2 register fi eld descripti ons...................................................................... 9-13 9-10 ddr_sdram_cfg field descriptions.............................................................................. 9-14 9-11 ddr_sdram_mode field descriptions.......................................................................... 9-15 9-12 ddr_sdram_interval fiel d descriptions .................................................................. 9-16 9-13 ddr_sdram_clk_cntl fiel d descriptions ................................................................. 9-16 9-14 data_err_inject_hi fi eld descriptions....................................................................... 9-17 9-15 data_err_inject_lo fi eld descriptions ..................................................................... 9-18 9-16 ecc_err_inject fiel d descriptions ............................................................................... 9-18 9-17 capture_data_hi fiel d descriptions............................................................................ 9-19 9-18 capture_data_lo fiel d descripti ons........................................................................... 9-19 9-19 capture_ecc field descriptions .................................................................................... 9-20 9-20 err_detect field de scriptions ....................................................................................... 9-20 9-21 err_disable field descriptions...................................................................................... 9-21 9-22 err_int_en field descriptions ........................................................................................ 9-22 9-23 capture_attributes fi eld descriptions .................................................................... 9-23 9-24 capture_address field descriptions .......................................................................... 9-24 9-25 err_sbe field de scriptions ............................................................................................... 9- 24 9-26 byte lane to data relationshi p ............................................................................................ 9 -29 9-27 supported ddr sdram device configurati ons ................................................................ 9-30 9-28 ddr sdram address multiplexing ................................................................................... 9-31 9-29 sdram command table ..................................................................................................... 9-3 2 9-30 ddr sdram interface ti ming intervals ............................................................................ 9-33 9-31 ddr sdram power-saving modes refresh configur ation............................................... 9-41 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor xci tables table number title page number 9-32 memory controller?dat a beat orderi ng ............................................................................ 9-43 9-33 ddr sdram ecc syndr ome encoding ............................................................................ 9-44 9-34 ddr sdram ecc syndrome enc oding (check bits) ....................................................... 9-45 9-35 memory controll er errors ................................................................................................... .9-46 9-36 memory interface conf iguration register initia lization parameters.................................... 9-47 10-1 processor interrupts gene rated outside the core?types and sources ............................... 10-3 10-2 e500 core-generated interrupts that cause a wa ke-up...................................................... 10-4 10-3 internal interrupt assignments............................................................................................. . 10-6 10-4 pic interfac e signals ...................................................................................................... ...... 10-7 10-5 interrupt signals?detailed signal descriptions .................................................................. 10-7 10-6 pic register a ddress map................................................................................................... . 10-9 10-7 frr field desc riptions..................................................................................................... .. 10-15 10-8 gcr field desc riptions ..................................................................................................... . 10-16 10-9 vir field desc riptions ..................................................................................................... .. 10-16 10-10 pir field desc riptions .................................................................................................... .... 10-17 10-11 ipivpr n field descrip tions................................................................................................ 10-18 10-12 svr field desc riptions .................................................................................................... .. 10-18 10-13 tfrr field de scriptions ................................................................................................... . 10-19 10-14 gtccr n field descrip tions ............................................................................................... 10-20 10-15 gtbcr n field descrip tions ............................................................................................... 10-20 10-16 gtvpr n field descript ions ............................................................................................... 10-21 10-17 gtdr n field descript ions.................................................................................................. 10-22 10-18 parameters for hourly interrupt timer cascade example.................................................. 10-22 10-19 tcr field desc riptions .................................................................................................... .. 10-23 10-20 irqsr0 field de scriptions ................................................................................................ 1 0-25 10-21 irqsr1 field de scriptions ................................................................................................ 1 0-25 10-22 cisr0 field de scriptions .................................................................................................. . 10-26 10-23 cisr1 field de scriptions .................................................................................................. . 10-26 10-24 pm n mr0 field descript ions .............................................................................................. 10-27 10-25 pm n mr1 field descript ions .............................................................................................. 10-28 10-26 msgr n field descript ions ................................................................................................. 10-28 10-27 mer field desc riptions.................................................................................................... .. 10-29 10-28 msr field desc riptions.................................................................................................... .. 10-30 10-29 eivpr n field descript ions................................................................................................. 10-31 10-30 eidr n field descript ions ................................................................................................... 10-32 10-31 iivpr n field descript ions.................................................................................................. 10-33 10-32 iidr n field descript ions .................................................................................................... 10-34 10-33 mivpr n field descrip tions................................................................................................ 10-35 10-34 midr n field descript ions.................................................................................................. 10-36 10-35 per-cpu registers?private a ccess address offs ets ........................................................ 10-36 10-36 ipidr n field descript ions.................................................................................................. 10-38 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 xcii freescale semiconductor tables table number title page number 10-37 ctpr field de scriptions ................................................................................................... . 10-39 10-38 whoami field desc riptions ...... ....................................................................................... 10-3 9 10-39 iack field de scriptions ................................................................................................... . 10-40 10-40 eoi field desc riptions.................................................................................................... .... 10-40 11-1 i 2 c interface signal de scriptions ......................................................................................... 11-3 11-2 i 2 c interface signal?detailed signal descriptions............................................................. 11-4 11-3 i 2 c memory map .................................................................................................................. 1 1-5 11-4 i2cadr field de scriptions.................................................................................................. 11-6 11-5 i2cfdr field de scriptions .................................................................................................. 11-7 11-6 i2ccr field de scriptions ................................................................................................... .. 11-8 11-7 i2csr field de scriptions ................................................................................................... .. 11-9 11-8 i2cdr field de scriptions................................................................................................... 11-10 11-9 i2cdfsrr field desc riptions.............................................................................................11- 11 12-1 duart signal overview ..................................................................................................... 1 2-3 12-2 duart signals?detailed si gnal descriptions .................................................................. 12-3 12-3 duart register summary .................................................................................................. 12- 5 12-4 urbr field desc riptions .................................................................................................... . 12-6 12-5 uthr field desc riptions .................................................................................................... . 12-7 12-6 udmb field desc riptions .................................................................................................... 12-7 12-7 udlb field desc riptions .................................................................................................... . 12-8 12-8 baud rate examples ......................................................................................................... .... 12-8 12-9 uier field desc riptions .................................................................................................... ... 12-9 12-10 uiir field de scriptions ................................................................................................... ... 12-10 12-11 uiir iid bits summary ..................................................................................................... . 12-10 12-12 ufcr field de scriptions ................................................................................................... . 12-11 12-13 ulcr field de scriptions ................................................................................................... . 12-13 12-14 parity selection using ulcr[pen ], ulcr[sp], and ulcr[eps] .................................. 12-13 12-15 umcr field desc riptions .................................................................................................. 1 2-14 12-16 ulsr field de scriptions ................................................................................................... . 12-15 12-17 umsr field de scriptions ................................................................................................... 12-16 12-18 uscr field de scriptions ................................................................................................... . 12-17 12-19 uafr field desc riptions................................................................................................... . 12-17 12-20 udsr field desc riptions................................................................................................... . 12-18 12-21 udsr[txrdy] set conditions ......................................................................................... 12-19 12-22 udsr[txrdy] cleared conditions.................................................................................. 12-19 12-23 udsr[rxrdy] set conditions......................................................................................... 12-19 12-24 udsr[rxrdy] cl eared .................................................................................................... 12- 19 13-1 signal properties? summary................................................................................................ 13 -4 13-2 local bus controller detail ed signal descri ptions .............................................................. 13-5 13-3 local bus controller memory map...................................................................................... 13-9 13-4 br n field descript ions ....................................................................................................... 13-11 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor xciii tables table number title page number 13-5 memory bank sizes in relati on to address mask ............................................................ 13-12 13-6 or n ?gpcm field descri ptions ....................................................................................... 13-13 13-7 or n ?upm field descri ptions .......................................................................................... 13-15 13-8 or n ?sdram field desc riptions .................................................................................... 13-16 13-9 mar field desc riptions ..................................................................................................... 13-17 13-10 m x mr field descript ions................................................................................................... 13-18 13-11 mrtpr field desc riptions ................................................................................................. 1 3-21 13-12 mdr field desc riptions .................................................................................................... . 13-21 13-13 lsdmr field desc riptions ................................................................................................ 13 -22 13-14 lurt field de scriptions ................................................................................................... . 13-24 13-15 lsrt field de scriptions................................................................................................... .. 13-24 13-16 ltesr field de scriptions .................................................................................................. 13-25 13-17 ltedr field de scriptions.................................................................................................. 13-26 13-18 lteir field de scriptions .................................................................................................. . 13-27 13-19 lteatr field de scriptions ................................................................................................ 1 3-28 13-20 ltear field de scriptions.................................................................................................. 13-29 13-21 lbcr field de scriptions ................................................................................................... . 13-30 13-22 lcrr field de scriptions ................................................................................................... . 13-31 13-23 gpcm write control signal timing for lcrr[clkdiv] = 4 or 8.................................. 13-38 13-24 gpcm read control signal timing for lcrr[clkdiv] = 4 or 8................................... 13-39 13-25 gpcm write control signal ti ming for lcrr[clkdiv] = 2 ......................................... 13-40 13-26 gpcm read control signal ti ming for lcrr[clkdiv] = 2.......................................... 13-41 13-27 boot bank field values after reset ................................................................................... 13-48 13-28 sdram interface co mmands ............................................................................................ 13-50 13-29 upm routines star t addresses ........................................................................................... 13- 61 13-30 ram word field de scriptions ........................................................................................... 13-6 7 13-31 m x mr loop field us e ....................................................................................................... 13-71 13-32 upm address mult iplexing ................................................................................................ 13 -72 13-33 data bus requirements for read cycle............................................................................. 13-86 13-34 typical sdram devices............. ....................................................................................... 1 3-88 13-35 lad n signal connections to 128-mbyte sdra m ............................................................ 13-90 13-36 logical address bu s partitioning ....................................................................................... 13- 91 13-37 sdram device address port during address phase........................................................ 13-91 13-38 sdram device address port du ring read/write command..................................... 13-91 13-39 register settings fo r 128-mbyte sdrams ........................................................................ 13-92 13-40 logical address partitioni ng .............................................................................................. 13-92 13-41 sdram device address port during address phase........................................................ 13-93 13-42 sdram device address port du ring read/write command..................................... 13-93 13-43 register settings fo r 512-mbyte sdrams ........................................................................ 13-93 13-44 sdram capaci tance ......................................................................................................... . 13-95 13-45 sdram ac charac teristics ............................................................................................... 13- 96 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 xciv freescale semiconductor tables table number title page number 13-46 local bus to msc8101 hdi16 connecti ons.................................................................... 13-101 13-47 upm synchronizati on cycles ........................................................................................... 13-10 9 13-48 ehpi signals .............................................................................................................. ...... 13-115 14-1 tsec signals?detailed si gnal descriptions .................................................................... 14-10 14-2 module memory map summary......................................................................................... 14-13 14-3 module memory map ......................................................................................................... 1 4-14 14-4 ievent field desc riptions................................................................................................ 14 -20 14-5 imask field desc riptions ................................................................................................. 14 -23 14-6 edis field descriptions .................................................................................................... . 14-24 14-7 ecntrl field desc riptions............................................................................................... 14- 25 14-8 minflr field desc riptions ............................................................................................... 14- 26 14-9 ptv field desc riptions ..................................................................................................... .. 14-27 14-10 dmactrl field desc riptions........................................................................................... 14-27 14-11 tbipa field de scriptions .................................................................................................. . 14-29 14-12 fifo_pause_ctrl fiel d descriptions ........................................................................... 14-30 14-13 fifo_tx_thr field descriptions .................................................................................... 14-31 14-14 fifo_tx_starve fiel d descriptio ns ............................................................................. 14-31 14-15 fifo_tx_starve_shutoff field descript ions.......................................................... 14-32 14-16 tctrl field de scriptions .................................................................................................. 14-32 14-17 tstat field de scriptions.................................................................................................. . 14-33 14-18 tbdlen field de scriptions .............................................................................................. 14- 34 14-19 txic field de scriptions ................................................................................................... .. 14-34 14-20 ctbptr field de scriptions ............................................................................................... 14 -35 14-21 tbptr field de scriptions .................................................................................................. 14-36 14-22 tbase field de scriptions .................................................................................................. 14-36 14-23 ostbd field desc riptions ................................................................................................. 1 4-37 14-24 ostbdp field de scriptions ............................................................................................... 14 -39 14-25 rctrl field desc riptions ................................................................................................. 1 4-39 14-26 rstat field de scriptions .................................................................................................. 14-40 14-27 rbdlen field desc riptions .............................................................................................. 14- 41 14-28 rxic field de scriptions................................................................................................... .. 14-41 14-29 crbptr field desc riptions ............................................................................................... 14 -42 14-30 mrblr field desc riptions ................................................................................................ 14 -43 14-31 rbptr field de scriptions.................................................................................................. 14-43 14-32 rbase field desc riptions ................................................................................................. 1 4-44 14-33 maccfg1 field desc riptions .... ....................................................................................... 14-47 14-34 maccfg2 field desc riptions .... ....................................................................................... 14-48 14-35 ipgifg field de scriptions ................................................................................................. 14-50 14-36 hafdup field desc riptions .............................................................................................. 14- 51 14-37 maxfrm field desc riptions ............................................................................................ 14-52 14-38 miimcfg field de scriptions............................................................................................. 14- 52 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor xcv tables table number title page number 14-39 miimcom field desc riptions .... ....................................................................................... 14-53 14-40 miimadd field desc riptions............................................................................................ 14-5 4 14-41 miimcon field desc riptions ............................................................................................ 14-5 4 14-42 miimstat field de scriptions .... ....................................................................................... 14-5 5 14-43 miimind field de scriptions ............................................................................................. 14- 55 14-44 ifstat field de scriptions ................................................................................................. 14-56 14-45 macstnaddr1 field descriptions ................................................................................ 14-57 14-46 macstnaddr2 field descriptions ................................................................................ 14-57 14-47 tr64 field desc riptions ................................................................................................... .. 14-58 14-48 tr127 field desc riptions .................................................................................................. . 14-59 14-49 tr255 field desc riptions .................................................................................................. . 14-59 14-50 tr511 field de scriptions .................................................................................................. . 14-60 14-51 tr1k field de scriptions ................................................................................................... . 14-60 14-52 trmax field desc riptions................................................................................................ 14 -61 14-53 trmgv field desc riptions................................................................................................ 14 -61 14-54 rbyt field desc riptions................................................................................................... . 14-62 14-55 rpkt field de scriptions ................................................................................................... . 14-62 14-56 rfcs field de scriptions ................................................................................................... . 14-63 14-57 rmca field desc riptions .................................................................................................. 1 4-63 14-58 rbca field desc riptions ................................................................................................... 14-64 14-59 rxcf field de scriptions ................................................................................................... . 14-64 14-60 rxpf field de scriptions ................................................................................................... . 14-65 14-61 rxuo field de scriptions ................................................................................................... 14-65 14-62 raln field de scriptions ................................................................................................... 14-66 14-63 rflr field de scriptions ................................................................................................... . 14-66 14-64 rcde field desc riptions................................................................................................... . 14-67 14-65 rcse field desc riptions ................................................................................................... . 14-67 14-66 rund field de scriptions ................................................................................................... 14-68 14-67 rovr field de scriptions ................................................................................................... 14-68 14-68 rfrg field de scriptions ................................................................................................... . 14-69 14-69 rjbr field de scriptions................................................................................................... .. 14-69 14-70 rdrp field de scriptions ................................................................................................... . 14-70 14-71 tbyt field de scriptions ................................................................................................... . 14-70 14-72 tpkt field de scriptions ................................................................................................... . 14-71 14-73 tmca field de scriptions................................................................................................... 14-71 14-74 tbca field de scriptions ................................................................................................... . 14-72 14-75 txpf field de scriptions ................................................................................................... . 14-72 14-76 tdfr field de scriptions ................................................................................................... . 14-73 14-77 tedf field desc riptions ................................................................................................... . 14-73 14-78 tscl field de scriptions ................................................................................................... . 14-74 14-79 tmcl field de scriptions ................................................................................................... 14-74 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 xcvi freescale semiconductor tables table number title page number 14-80 tlcl field desc riptions ................................................................................................... . 14-75 14-81 txcl field de scriptions ................................................................................................... . 14-75 14-82 tncl field de scriptions ................................................................................................... . 14-76 14-83 tdrp field de scriptions ................................................................................................... . 14-76 14-84 tjbr field desc riptions ................................................................................................... .. 14-77 14-85 tfcs field de scriptions................................................................................................... .. 14-77 14-86 txcf field de scriptions ................................................................................................... . 14-77 14-87 tovr field de scriptions ................................................................................................... 14-78 14-88 tund field de scriptions ................................................................................................... 14-78 14-89 tfrg field de scriptions ................................................................................................... . 14-79 14-90 car1 field de scriptions ................................................................................................... . 14-79 14-91 car2 field de scriptions ................................................................................................... . 14-81 14-92 cam1 field de scriptions ................................................................................................... 14-82 14-93 cam2 field de scriptions ................................................................................................... 14-83 14-94 iaddr n field descript ions................................................................................................ 14-85 14-95 gaddr n field descript ions .............................................................................................. 14-85 14-96 attr field de scriptions ................................................................................................... . 14-86 14-97 attreli field de scriptions .............................................................................................. 14 -87 14-98 tbi mii regist er set...................................................................................................... ..... 14-88 14-99 cr field desc riptions ..................................................................................................... .... 14-88 14-100 sr descri ptions.......................................................................................................... ......... 14-90 14-101 ana field desc riptions................................................................................................... ... 14-91 14-102 pause priority resolution................................................................................................ . 14-92 14-103 anlpbpa field de scriptions ............................................................................................ 14- 92 14-104 anex field desc riptions .................................................................................................. . 14-94 14-105 annpt field de scriptions ................................................................................................. 14-95 14-106 anlpanp field de scriptions ............................................................................................ 14- 96 14-107 exst field de scriptions .................................................................................................. .. 14-97 14-108 jd field desc riptions.................................................................................................... ...... 14-98 14-109 tbicon field de scriptions ............................................................................................... 1 4-99 14-110 gmii, mii, and tbi si gnal multiplexing ......................................................................... 14-104 14-111 rgmii and rtbi signa l multiplexing ............................................................................. 14-105 14-112 shared signals........................................................................................................... ........ 14-107 14-113 steps of minimum regist er initializat ion ......................................................................... 14-107 14-114 flow control fram e structure .......................................................................................... 14- 115 14-115 non-error transmit interrupts .......................................................................................... 14 -116 14-116 non-error receive interrupts............................................................................................ 1 4-117 14-117 interrupt coalescing timi ng threshold ranges ............................................................... 14-118 14-118 transmission errors ...................................................................................................... .... 14-119 14-119 reception errors ......................................................................................................... ...... 14-119 14-120 transmit data buffer descriptor (txbd) field de scriptions .......................................... 14-122 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor xcvii tables table number title page number 14-121 receive buffer descriptor field descript ions .................................................................. 14-124 14-122 mii interface mode signa l configuration ........................................................................ 14-126 14-123 shared mii signals....................................................................................................... ..... 14-127 14-124 mii mode register init ialization steps............................................................................. 14-127 14-125 gmii interface mode si gnal configuration ..................................................................... 14-129 14-126 shared gmii signals...................................................................................................... ... 14-130 14-127 gmii mode register in itialization steps.......................................................................... 14-131 14-128 tbi interface mode signa l configuratio n ........................................................................ 14-133 14-129 shared tbi signals ....................................................................................................... .... 14-134 14-130 tbi mode register ini tialization step s............................................................................. 14-134 14-131 rgmii interface mode signal configuration................................................................... 14-137 14-132 shared rgmi i signals ..................................................................................................... . 14-138 14-133 rgmii mode register in itialization st eps ....................................................................... 14-138 14-134 rtbi interlace mode si gnal configurat ion...................................................................... 14-140 14-135 shared rtbi signals ...................................................................................................... ... 14-142 14-136 rtbi mode register in itialization st eps .......................................................................... 14-142 15-1 relationship of mode s and features ..................................................................................... 15-3 15-2 dma mode bit settings ...................................................................................................... . 15-3 15-3 dma signals?detailed si gnal descripti ons....................................................................... 15-5 15-4 dma register summary ............. ......................................................................................... 1 5-7 15-5 mr n field descrip tions ........................................................................................................ 15-9 15-6 sr n field descript ions ....................................................................................................... 15-12 15-7 clndar n field descript ions............................................................................................ 15-14 15-8 satr n field descript ions .................................................................................................. 15-15 15-9 sar n field descript ions .................................................................................................... 15-15 15-10 datr n field descript ions.................................................................................................. 15-16 15-11 dar n field descrip tions.................................................... ................................................ 15-17 15-12 bcr n field descrip tions .................................................... ................................................ 15-17 15-13 nlndar n field descript ions............................................................................................ 15-18 15-14 clsdar n field descript ions ............................................................................................ 15-19 15-15 nlsdar n field descript ions ............................................................................................ 15-19 15-16 ssr n field descript ions ..................................................................................................... 15-20 15-17 dsr n field descript ions .................................................................................................... 15-20 15-18 dgsr field desc riptions................................................................................................... . 15-21 15-19 channel state table....................................................................................................... ...... 15-29 15-20 list dma descriptor summary... ....................................................................................... 15-31 15-21 link dma descript or summary ........................................................................................ 15-31 15-22 MPC8555E dma paths...................................................................................................... 15 -36 16-1 por parameters for pci controller...................................................................................... 16-4 16-2 pci1 and pci2 interface signals?d etailed signal descriptions ........................................ 16-8 16-3 pci memory-mapped re gister map................................................................................... 16-14 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 xcviii freescale semiconductor tables table number title page number 16-4 pci cfg_addr field descriptions.................................................................................. 16-17 16-5 pci cfg_data field descriptions................................................................................... 16-18 16-6 pci int_ack field descriptions ...................................................................................... 16-19 16-7 potar n field descriptions ............................................................................................... 16-20 16-8 potear n field descripti ons............................................................................................. 16-21 16-9 powbar n field descript ions ........................................................................................... 16-21 16-10 powar n field descript ions .............................................................................................. 16-23 16-11 pitar n field descripti ons ................................................................................................. 16-25 16-12 piwbar field de scriptions............................................................................................... 16 -26 16-13 piwbear field desc riptions ............................................................................................ 16-2 6 16-14 piwar n field descript ions................................................................................................ 16-27 16-15 err_dr field de scriptions ............................................................................................... 16 -29 16-16 err_cap_dr field descriptions ..................................................................................... 16-30 16-17 err_en field de scriptions ............................................................................................... 16 -31 16-18 err_attrib field descriptions ...................................................................................... 16-32 16-19 err_addr field desc riptions .. ....................................................................................... 16-33 16-20 err_ext_addr field descriptions ............................................................................... 16-33 16-21 err_dl field de scriptions ............................................................................................... 16 -34 16-22 err_dh field desc riptions............................................................................................... 16 -34 16-23 gas_timr field desc riptions .......................................................................................... 16-35 16-24 pci vendor id register field descript ions ........................................................................ 16-36 16-25 pci device id register field descriptions ........................................................................ 16-37 16-26 pci bus command register field descriptions................................................................. 16-37 16-27 pci bus status register field descript ions........................................................................ 16-39 16-28 pci revision id register field descrip tions ..................................................................... 16-40 16-29 pci bus programming interface re gister field descriptions ............................................ 16-40 16-30 pci subclass code register field descript ions ................................................................. 16-41 16-31 pci bus base class code regi ster field descri ptions....................................................... 16-41 16-32 pci bus cache line size regist er field descri ptions ....................................................... 16-42 16-33 pci bus latency timer regist er field descri ptions .......................................................... 16-42 16-34 pcsrbar field desc riptions ..... ....................................................................................... 16-4 3 16-35 32-bit memory base address re gister field descriptions ................................................ 16-43 16-36 64-bit low memory base address register field de scriptions........................................ 16-44 16-37 bit setting for 64-bit high memo ry base address register.............................................. 16-45 16-38 pci subsystem vendor id regist er field descri ptions...................................................... 16-45 16-39 pci subsystem id register field descript ions .................................................................. 16-45 16-40 pci bus capabilities pointer re gister field desc riptions.................................................. 16-46 16-41 pci bus interrupt line regist er field descriptions ........................................................... 16-46 16-42 pci bus interrupt pin regist er field descri ptions ............................................................. 16-47 16-43 pci bus minimum grant regist er field descriptions ....................................................... 16-47 16-44 pci bus maximum latency regist er field descriptions ................................................... 16-47 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor xcix tables table number title page number 16-45 pci bus function register field descriptions ................................................................... 16-48 16-46 pci bus arbiter configuration re gister field descriptions .............................................. 16-49 16-47 pci bus co mmands .......................................................................................................... .. 16-53 16-48 supported combinations of pci n _ad[1:0]........................................................................ 16-55 16-49 pci configuration space header summary ....................................................................... 16-66 16-50 pci type 0 configurat ion?device number to ad n translation...................................... 16-69 16-51 special-cycle mess age encodings ..................................................................................... 16-72 16-52 pci mode erro r actions .................................................................................................... . 16-74 16-53 affected configuration regi ster bits for por ................................................................... 16-75 16-54 power-on reset values for aff ected configurati on bits ................................................... 16-76 16-55 extended 64-bit pci1 si gnal connections ......................................................................... 16-77 17-1 example data packet descriptor .......................................................................................... 17- 4 17-2 sec base addr ess map ............... ....................................................................................... 1 7-10 17-3 sec addres s map ............................................................................................................ ... 17-10 17-4 header dword bit definitions ............................................................................................ 17- 16 17-5 eu_sel1 and eu_sel2 values ........................................................................................ 17-17 17-6 descriptor types ........................................................................................................... ...... 17-17 17-7 pointer dword fiel d definitions ......................................................................................... 17- 19 17-8 link table field definitions ............................................................................................... 17-20 17-9 descriptor pointer dword usage ........................................................................................ 17-23 17-10 pkeumr mode field descriptions................................................................................. 17-25 17-11 pkeurcr field desc riptions..... ....................................................................................... 17-2 8 17-12 pkeusr field de scriptions ............................................................................................... 17 -29 17-13 pkeuisr field de scriptions .............................................................................................. 17 -30 17-14 pkeuicr field de scriptions ............................................................................................. 17- 31 17-15 deumr field desc riptions................................................................................................ 17 -33 17-16 deuksr field de scriptions .............................................................................................. 17- 35 17-17 deurcr field de scriptions .............................................................................................. 17- 36 17-18 deusr field desc riptions ................................................................................................. 1 7-37 17-19 deuisr field de scriptions................................................................................................ 1 7-38 17-20 deuicr field de scriptions ............................................................................................... 17 -40 17-21 afeumr field de scriptions .............................................................................................. 17- 43 17-22 afeurcr field desc riptions..... ....................................................................................... 17-4 6 17-23 afeusr field de scriptions ............................................................................................... 17 -46 17-24 afeuisr field de scriptions .............................................................................................. 17 -47 17-25 afeuicr field de scriptions ............................................................................................. 17- 49 17-26 mdeumr field desc riptions ............................................................................................ 17-52 17-27 mdeumr?hmac generated by single descriptor ....................................................... 17-53 17-28 mdeumr?hmac generated for a message across a chain of descriptors................. 17-53 17-29 mdeurcr field desc riptions .......................................................................................... 17-55 17-30 mdeusr field de scriptions .............................................................................................. 17- 55 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 c freescale semiconductor tables table number title page number 17-31 mdeuisr field desc riptions ............................................................................................ 17-5 6 17-32 mdeuicr field desc riptions..... ....................................................................................... 17-5 7 17-33 rngmr field definitions.................................................................................................. 1 7-62 17-34 rngrcr field de scriptions .............................................................................................. 17- 63 17-35 rngsr field desc riptions ................................................................................................. 1 7-64 17-36 rngisr field de scriptions ................................................................................................ 1 7-65 17-37 rngicr field de scriptions ............................................................................................... 17 -66 17-38 aesumr field de scriptions .............................................................................................. 17- 67 17-39 aes cipher modes .......................................................................................................... ... 17-68 17-40 aesurcr field desc riptions..... ....................................................................................... 17-7 1 17-41 aesusr field de scriptions ............................................................................................... 17 -71 17-42 aesuisr field de scriptions .............................................................................................. 17 -72 17-43 aesuicr field de scriptions ............................................................................................. 17- 74 17-44 counter modulus........................................................................................................... ...... 17-77 17-45 cccr field desc riptions................................................................................................... . 17-81 17-46 ccpsr field de scriptions.................................................................................................. 17-83 17-47 g_state field values ...................................................................................................... . 17-85 17-48 s_state fiel d values...................................................................................................... .. 17-86 17-49 chn_state fiel d values.................................................................................................. 17 -86 17-50 ccpsr error field definitions........................................................................................... 17 -88 17-51 channel pointer status regist er ptr_dw field values .................................................... 17-89 17-52 cdpr field de scriptions ................................................................................................... . 17-89 17-53 fetch fifo field descriptions............................................................................................ 1 7-90 17-54 channel assignmen t value ................................................................................................. 1 7-93 17-55 interrupt mask, status, and clear register field descriptions........................................... 17-97 17-56 mcr field desc riptions .................................................................................................... . 17-98 18-1 external signal summary .................................................................................................... . 18-2 18-2 detailed signal de scriptions............................................................................................... .. 18-2 18-3 global utilities block re gister summar y ............................................................................ 18-3 18-4 porpllsr field desc riptions ... ......................................................................................... 18-5 18-5 porbmsr field desc riptions ............................................................................................. 18-6 18-6 porimpscr field desc riptions. ......................................................................................... 18-7 18-7 pordevsr field desc riptions .. ......................................................................................... 18-8 18-8 pordbgmsr field de scriptions........................................................................................ 18-9 18-9 gpporcr field desc riptions ..... ....................................................................................... 18-10 18-10 gpiocr field de scriptions ................................................................................................ 1 8-10 18-11 gpoutdr field desc riptions .... ....................................................................................... 18-12 18-12 gpindr field de scriptions ............................................................................................... 18 -13 18-13 pmuxcr field desc riptions ............................................................................................. 18-1 4 18-14 devdisr field de scriptions ............................................................................................. 18- 15 18-15 powmgtcsr field de scriptions ..................................................................................... 18-16 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor ci tables table number title page number 18-16 mcpsumr field desc riptions ... ....................................................................................... 18-18 18-17 pvr field desc riptions .................................................................................................... .. 18-18 18-18 svr field desc riptions .................................................................................................... .. 18-19 18-19 clkocr field de scriptions .............................................................................................. 18- 19 18-20 lbdllcr field desc riptions ..... ....................................................................................... 18-2 1 18-21 MPC8555E power management m odes?basic descriptions........................................... 18-22 18-22 power management entry protocol and initiating functional units .................................. 18-25 19-1 control register me mory map ............................................................................................. 19- 3 19-2 pmgc0 field de scriptions ................................................................................................... 19-5 19-3 pmlca0 field desc riptions ................................................................................................ 19 -6 19-4 pmlca1?pmlca8 field descriptions............................................................................... 19-6 19-5 pmlcb0 field desc riptions................................................................................................. 1 9-7 19-6 pmlcb1?pmlcb8 field descriptions ............................................................................... 19-8 19-7 pmc0 field desc riptions.................................................................................................... 19-10 19-8 pmc1?pmc8 field de scriptions ....................................................................................... 19-10 19-9 burst definition........................................................................................................... ........ 19-13 19-10 performance moni tor events .............................................................................................. 19 -15 19-11 pmgc0 and pmlca n settings... ....................................................................................... 19-25 19-12 register settings for counting examples ........................................................................... 19-26 20-1 por configuration setti ngs and debug modes ................................................................... 20-3 20-2 debug, watchpoint, and test signal summary..................................................................... 20-5 20-3 debug signals?detailed si gnal descriptions ..................................................................... 20-7 20-4 watchpoint and trigger signals?d etailed signal desc riptions .......................................... 20-8 20-5 jtag test and other signals?det ailed signal descriptions .............................................. 20-8 20-6 debug and watchpoint moni tor memory map................................................................... 20-10 20-7 wmcr0 field desc riptions................................................................................................ 20- 11 20-8 wmcr1 field desc riptions................................................................................................ 20- 12 20-9 wmar field desc riptions ................................................................................................. 20- 13 20-10 wmamr field desc riptions....... ....................................................................................... 20-1 3 20-11 wmtmr field desc riptions ....... ....................................................................................... 20-1 4 20-12 transaction types by interface........................................................................................... 2 0-14 20-13 wmsr field desc riptions .................................................................................................. 2 0-15 20-14 tbcr0 field de scriptions .................................................................................................. 20-16 20-15 tbcr1 field de scriptions .................................................................................................. 20-17 20-16 tbar field de scriptions ................................................................................................... . 20-18 20-17 tbamr field desc riptions ................................................................................................ 20 -18 20-18 tbtmr field desc riptions ................................................................................................ 20 -19 20-19 tbsr field de scriptions ................................................................................................... . 20-19 20-20 tbacr field desc riptions ................................................................................................. 2 0-20 20-21 tbadhr field de scriptions.............................................................................................. 20- 21 20-22 tbadr field desc riptions................................................................................................. 2 0-21 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 cii freescale semiconductor tables table number title page number 20-23 pcidr field de scriptions .................................................................................................. 20-22 20-24 ccidr field de scriptions .................................................................................................. 20-23 20-25 tosr field de scriptions ................................................................................................... . 20-24 20-26 source and target id values............................................................................................... 20-24 20-27 cmd trace buffer entry field de scriptions (tbcr1[ifsel] = 000) .............................. 20-28 20-28 ddr trace buffer entry field desc riptions (tbcr1[ifsel] = 001)............................... 20-29 20-29 pci trace buffer entry field de scriptions (tbcr1[ifsel] = 010) ................................. 20-29 21-1 MPC8555E internal me mory map ....................................................................................... 21-4 21-2 cear field desc riptions.................................................................................................... 21-19 21-3 ceer field desc riptions .................................................................................................... 21-19 21-4 cemr field desc riptions ................................................................................................... 2 1-20 21-5 peripheral prio ritization .................................................................................................. .... 21-21 21-6 risc controller confi guration register fiel d descriptions .............................................. 21-22 21-7 rtscr field desc riptions.................................................................................................. 2 1-23 21-8 risc microcode revi sion number .................................................................................... 21-24 21-9 cp command register fi eld descripti ons ......................................................................... 21-25 21-10 cp command op codes ....................................................................................................... 2 1-26 21-11 command desc riptions...................................................................................................... . 21-27 21-12 buffer descriptor format.................................................................................................. .. 21-31 21-13 parameter ram ............................................................................................................. ..... 21-31 21-14 risc timer table pa rameter ram .................................................................................... 21-33 21-15 tm_cmd field desc riptions ............................................................................................. 21-3 4 22-1 interrupt source pr iority levels........................................................................................... . 22-3 22-2 encoding the interr upt vector .............................................................................................. . 22-6 22-3 sicr field desc riptions .................................................................................................... ... 22-9 22-4 scprr_h field desc riptions ............................................................................................. 22-1 0 22-5 scprr_l field desc riptions ............................................................................................. 22-1 1 22-6 siexr field de scriptions................................................................................................... 22-16 23-1 si2 ram en try .............................................................................................................. ....... 23-9 23-2 si2 ram entry de scriptions .............................................................................................. 23- 11 23-3 si2gmr field desc riptions................................................................................................ 23 -14 23-4 si2mr field desc riptions .................................................................................................. 2 3-15 23-5 si2rsr field desc riptions ................................................................................................. 2 3-20 23-6 si2cmdr field desc riptions ............................................................................................. 23-2 1 23-7 si2str field desc riptions ................................................................................................. 2 3-21 23-8 idl signal de scriptions .................................................................................................... .. 23-23 23-9 si2 ram entries for an idl interface ............................................................................... 23-25 23-10 gci signals ............................................................................................................... .......... 23-27 23-11 si2 ram entries for a gci in terface (scit m ode) .......................................................... 23-29 24-1 clock source options ....................................................................................................... .... 24-5 24-2 cmxuar field desc riptions............................................................................................... 24- 6 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor ciii tables table number title page number 24-3 cmxsi2cr field desc riptions ... ......................................................................................... 24-8 24-4 cmxfcr field desc riptions................................................................................................ 24 -9 24-5 cmxscr field desc riptions.............................................................................................. 24-1 1 24-6 cmxsmr field desc riptions............................................................................................. 24-13 25-1 sccr field desc riptions .................................................................................................... .. 25-2 25-2 brgc n field descript ions ................................................................................................... 25-3 25-3 brg external clock source options.................................................................................... 25-4 25-4 typical baud rates for async hronous communicat ion....................................................... 25-6 26-1 tgcr1 field de scriptions ................................................................................................... . 26-4 26-2 tgcr2 field de scriptions ................................................................................................... . 26-5 26-3 tmr1?tmr4 field de scriptions ......................................................................................... 26-6 26-4 ter field desc riptions..................................................................................................... .... 26-8 27-1 smevr and lmevr fiel d descriptions............................................................................. 27-3 27-2 smctr/lmctr field descriptions.................................................................................... 27-3 28-1 gsmr_h field desc riptions ................................................................................................ 28 -3 28-2 gsmr_l field desc riptions ................................................................................................ 28 -5 28-3 todr field desc riptions .................................................................................................... . 28-9 28-4 scc parameter ram map fo r all protocols...................................................................... 28-12 28-5 parameter ram?scc ba se addresses............................................................................. 28-14 28-6 rfcr x /tfcr x field descriptions ..................................................................................... 28-14 28-7 scc x event, mask, and stat us registers ........................................................................... 28-15 28-8 preamble requi rements ...................................................................................................... 28-21 28-9 dpll codi ngs ............................................................................................................... ..... 28-23 29-1 uart-specific scc paramete r ram memory map ........................................................... 29-3 29-2 transmit co mmands .......................................................................................................... ... 29-5 29-3 receive comm ands........................................................................................................... .... 29-6 29-4 control character table, rccm, and rccr descriptions.................................................. 29-8 29-5 toseq field de scriptions ................................................................................................... 29-9 29-6 dsr fields de scriptions .................................................................................................... . 29-11 29-7 transmission errors ........................................................................................................ .... 29-11 29-8 reception er rors ........................................................................................................... ...... 29-12 29-9 psmr uart field de scriptions ........................................................................................ 29-13 29-10 scc uart rxbd status and cont rol field descri ptions ................................................. 29-16 29-11 scc uart txbd status and cont rol field descri ptions ................................................. 29-17 29-12 scce/sccm field descripti ons for uart mode ............................................................ 29-20 29-13 uart sccs field de scriptions.. ....................................................................................... 29-21 29-14 uart control characters for s-records exam ple ............................................................ 29-21 30-1 hdlc-specific scc paramete r ram memory map .......................................................... 30-3 30-2 transmit co mmands .......................................................................................................... ... 30-5 30-3 receive comm ands ........................................................................................................... ... 30-5 30-4 transmit er rors ............................................................................................................ ........ 30-6 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 civ freescale semiconductor tables table number title page number 30-5 receive errors............................................................................................................. .......... 30-6 30-6 psmr hdlc field de scriptions.......................................................................................... 30-7 30-7 scc hdlc rxbd status and cont rol field descri ptions................................................... 30-9 30-8 scc hdlc txbd status and cont rol field descri ptions ................................................. 30-11 30-9 scce/sccm field de scriptions . ....................................................................................... 30-12 30-10 hdlc sccs field de scriptions.. ....................................................................................... 30-14 31-1 scc bisync parameter ram memory map ..................................................................... 31-3 31-2 transmit co mmands .......................................................................................................... ... 31-4 31-3 receive comm ands........................................................................................................... .... 31-5 31-4 control character table and r ccm field descriptions ...................................................... 31-6 31-5 bsync field de scriptions ................................................................................................... 31-7 31-6 bdle field desc riptions .................................................................................................... .. 31-8 31-7 receiver sync pattern le ngths of the dsr........................................................................ 31-8 31-8 transmit er rors ............................................................................................................ ......... 31-9 31-9 receive errors............................................................................................................. .......... 31-9 31-10 psmr field desc riptions................................................................................................... . 31-10 31-11 scc bisync rxbd status and control field descriptions ............................................. 31-11 31-12 scc bisync txbd status and control field descriptions ............................................. 31-13 31-13 scce/sccm field de scriptions . ....................................................................................... 31-15 31-14 sccs field de scriptions ................................................................................................... . 31-15 31-15 control char acters ........................................................................................................ ...... 31-16 32-1 receiver sync pattern le ngths of the dsr........................................................................ 32-3 32-2 scc transparent paramete r ram memory map................................................................. 32-6 32-3 transmit co mmands .......................................................................................................... ... 32-6 32-4 receive comm ands........................................................................................................... .... 32-7 32-5 transmit er rors ............................................................................................................ ......... 32-7 32-6 receive errors............................................................................................................. .......... 32-8 32-7 scc transparent rxbd status a nd control field descriptions........................................... 32-9 32-8 scc transparent txbd status a nd control field descriptions ......................................... 32-10 32-9 scce/sccm field de scriptions . ....................................................................................... 32-11 32-10 sccs field de scriptions ................................................................................................... . 32-12 34-1 global multi-channe l parameters ........................................................................................ 34-7 34-2 time-slot assignment table entry fields for receive section ........................................ 34-10 34-3 time-slot assignment table entry fields for transmit section ...................................... 34-11 34-4 channel-specific hdl c parameters .................................................................................. 34-15 34-5 chamr field descrip tions (hdlc) ................................................................................. 34-17 34-6 tstate field descript ions (hdlc).................................................................................. 34-18 34-7 rstate field descrip tions (hdlc) ................................................................................. 34-19 34-8 channel-specific transp arent parameters .......................................................................... 34-20 34-9 chamr bit settings (tra nsparent mode) ......................................................................... 34-21 34-10 tstate field descriptions (transparent mode) ............................................................... 34-22 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor cv tables table number title page number 34-11 rstate field descriptions (transparent m ode) ............................................................... 34-27 34-12 scc event register fi eld descriptions .............................................................................. 34-31 34-13 interrupt table entry fi eld descriptions............................................................................. 34-32 34-14 rxbd field de scriptions ................................................................................................... . 34-35 34-15 transmit buffer descriptor (t xbd) field descri ptions ..................................................... 34-38 35-1 usb pins f unctions ......................................................................................................... ..... 35-3 35-2 usb toke ns ................................................................................................................. ......... 35-6 35-3 usb toke ns ................................................................................................................. ....... 35-10 35-4 usb parameter ram memory map .................................................................................. 35-12 35-5 endpoint paramete r block .................................................................................................. 3 5-13 35-6 frame_n field desc riptions..... ....................................................................................... 35-15 35-7 frame_n field desc riptions..... ....................................................................................... 35-15 35-8 rfcr and tfcr fields ...................................................................................................... 3 5-16 35-9 usmod fi elds ............................................................................................................... .... 35-17 35-10 usadr fi elds .............................................................................................................. ...... 35-18 35-11 usep n field descript ions .................................................................................................. 35-18 35-12 uscom fi elds.............................................................................................................. ...... 35-20 35-13 usber fi elds .............................................................................................................. ....... 35-20 35-14 usbs fields............................................................................................................... ......... 35-21 35-15 ussft fields.............................................................................................................. ........ 35-22 35-16 usb rxbd fields........................................................................................................... .... 35-24 35-17 usb function txbd fields ................................................................................................ 35 -26 35-18 usb host txbd fields...................................................................................................... . 35-28 35-19 usb host trbd fields ...................................................................................................... . 35-30 35-20 usb controller tran smission erro rs .................................................................................. 35-33 35-21 usb controller re ception errors ....................................................................................... 35-3 3 36-1 smcmr1, smcmr2 field descriptions............................................................................. 36-3 36-2 smc uart and transparent pa rameter ram memory map ............................................. 36-6 36-3 rfcr, tfcr field de scriptions . ......................................................................................... 36-8 36-4 transmit co mmands .......................................................................................................... . 36-12 36-5 receive comm ands........................................................................................................... .. 36-12 36-6 smc uart errors............................................................................................................ .. 36-13 36-7 smc uart rxbd fiel d descriptions ............................................................................... 36-14 36-8 smc uart txbd fiel d descriptio ns ............................................................................... 36-17 36-9 smce/smcm field de scriptions ...................................................................................... 36-18 36-10 smc transparent tran smit commands.............................................................................. 36-25 36-11 smc transparent rece ive commands ............................................................................... 36-25 36-12 smc transparent er ror conditions .................................................................................... 36-25 36-13 smc transparent rxbd fi eld descriptions....................................................................... 36-26 36-14 smc transparent txbd fi eld descripti ons....................................................................... 36-27 36-15 smce/smcm field de scriptions ...................................................................................... 36-28 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 cvi freescale semiconductor tables table number title page number 36-16 smc gci parameter ra m memory map .......................................................................... 36-30 36-17 smc gci co mmands ......................................................................................................... 3 6-32 36-18 smc monitor channel rxbd field descript ions .............................................................. 36-32 36-19 smc monitor channel txbd field descriptions .............................................................. 36-33 36-20 smc c/i channel rxbd fi eld descriptions ...................................................................... 36-33 36-21 smc c/i channel txbd fi eld descripti ons ...................................................................... 36-34 36-22 smce/smcm field de scriptions ...................................................................................... 36-34 37-1 gfmr register field descriptions....................................................................................... 37-4 37-2 gfemr x field descript ions................................................................................................. 37-7 37-3 ftodr field de scriptions ................................................................................................... 37-8 37-4 fcc parameter ram common to al l protocols except atm .......................................... 37-11 37-5 fcr x field descript ions ..................................................................................................... 37-13 38-1 fcc hdlc-specific paramete r ram memory map .......................................................... 38-3 38-2 transmit co mmands .......................................................................................................... ... 38-5 38-3 receive comm ands........................................................................................................... .... 38-6 38-4 hdlc transmissi on errors .................................................................................................. 3 8-6 38-5 hdlc reception errors ...................................................................................................... . 38-7 38-6 fpsmr field desc riptions .................................................................................................. 3 8-8 38-7 rxbd field desc riptions .................................................................................................... 38-11 38-8 hdlc txbd field de scriptions . ....................................................................................... 38-13 38-9 fcce/fccm field de scriptions . ....................................................................................... 38-14 38-10 fccs register fiel d descriptions ...................................................................................... 38-1 6 40-1 flow control frame structure .............................................................................................. 4 0-7 40-2 ethernet-specific pa rameter ram ....................................................................................... 40-9 40-3 transmit co mmands .......................................................................................................... . 40-12 40-4 receive co mmands.......................................................................................................... .. 40-13 40-5 rmon statistics a nd counters .... ....................................................................................... 40-1 4 40-6 transmission errors ........................................................................................................ .... 40-19 40-7 reception er rors ........................................................................................................... ...... 40-19 40-8 gfemr x field descript ions............................................................................................... 40-20 40-9 fpsmr ethernet field descriptions................................................................................... 40-21 40-10 fcce/fccm field de scriptions . ....................................................................................... 40-23 40-11 rxbd field de scriptions ................................................................................................... . 40-25 40-12 ethernet txbd fiel d definitions ........................................................................................ 40- 28 41-1 atm service types.......................................................................................................... ..... 41-8 41-2 external cam input and output field descript ions .......................................................... 41-14 41-3 field descriptions for address compression ..................................................................... 41-15 41-4 vcoffset calculation examples for contiguous vclts ............................................... 41-16 41-5 vp-level table entry address calculation exam ple......................................................... 41-17 41-6 vc-level table entry address calculation exam ple ........................................................ 41-17 41-7 fields and their positions in rm cells .............................................................................. 41-26 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor cvii tables table number title page number 41-8 pre-assigned header valu es at the uni ............................................................................. 41-27 41-9 pre-assigned header valu es at the nni ............................................................................. 41-28 41-10 performance monitori ng cell fields................................................................................... 41-30 41-11 atm parameter ra m map................................................................................................. 41-3 5 41-12 vci filtering enable fi eld descriptio ns ............................................................................ 41-38 41-13 gmode field desc riptions................................................................................................ 41 -38 41-14 receive and transmit conn ection table sizes ................................................................... 41-39 41-15 rct field desc riptions .................................................................................................... .. 41-42 41-16 rct settings (aal5 prot ocol-specific) ............................................................................ 41-43 41-17 abr protocol-specific rct field descript ions ................................................................ 41-44 41-18 aal1 protocol-specific rct field descript ions .............................................................. 41-45 41-19 aal0-specific rct fiel d descriptions............................................................................. 41-47 41-20 tct field desc riptions.................................................................................................... ... 41-48 41-21 aal5-specific tct fiel d descriptio ns ............................................................................. 41-51 41-22 aal1 protocol-specific tct field descriptions .............................................................. 41-52 41-23 aal0-specific tct fiel d descriptio ns ............................................................................. 41-53 41-24 vbr-specific tcte fiel d descriptions............................................................................. 41-54 41-25 ubr+ protocol-specific tc te field descript ions............................................................ 41-55 41-26 abr-specific tcte fiel d descriptions............................................................................. 41-56 41-27 oam?performance monitoring ta ble field descriptions ............................................... 41-59 41-28 apc paramete r table....................................................................................................... ... 41-60 41-29 apc priority ta ble entry .................................................................................................. .. 41-61 41-30 control slot fiel d descripti ons........................................................................................... 41-62 41-31 free buffer pool entry field descriptions.......................................................................... 41-66 41-32 free buffer pool parameter table....................................................................................... 41- 66 41-33 receive and trans mit buffers............................................................................................. 4 1-67 41-34 aal5 rxbd field de scriptions.. ....................................................................................... 41-68 41-35 aal1 rxbd field de scriptions.. ....................................................................................... 41-69 41-36 aal0 rxbd field de scriptions.. ....................................................................................... 41-70 41-37 aal5 txbd field de scriptions ......................................................................................... 41-72 41-38 aal1 txbd field de scriptions ......................................................................................... 41-73 41-39 aal0 txbd field de scriptions ......................................................................................... 41-74 41-40 uni statistics table ...................................................................................................... ...... 41-76 41-41 interrupt queue entry fi eld descriptions ........................................................................... 41-78 41-42 interrupt queue parameter table ........................................................................................ 41- 79 41-43 utopia master mode si gnal descripti ons ....................................................................... 41-80 41-44 utopia slave mode signals ............................................................................................. 41-8 1 41-45 utopia loopback modes ................................................................................................. 41-8 3 41-46 gfemr x field descript ions............................................................................................... 41-83 41-47 fcc atm mode regi ster (fpsmr) .................................................................................. 41-84 41-48 fcce/fccm field de scriptions . ....................................................................................... 41-87 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 cviii freescale semiconductor tables table number title page number 41-49 ftirr x field descript ions ................................................................................................. 41-88 41-50 comm_info field de scriptions ...................................................................................... 41-89 41-51 firper x field descriptions (tirem = 1)......................................................................... 41-91 41-52 firer x field descriptions (tirem = 1)........................................................................... 41-92 41-53 irsr x _hi field descriptions (tirem = 1) ....................................................................... 41-92 41-54 firsr x _lo field descriptions (tirem = 1).................................................................... 41-93 41-55 ftirr x field descript ions ................................................................................................. 41-94 42-1 aal2 protocol-specific tr ansmit connection table (tct ) field descriptions ............... 42-10 42-2 cps txqd field desc riptions ............................................................................................ 42-1 3 42-3 cps txbd field desc riptions ............................................................................................ 42-1 5 42-4 sssar txqd field de scriptions....................................................................................... 42-17 42-5 sssar txbd field de scriptions ....................................................................................... 42-18 42-6 aal2 protocol-specific rct field descript ions .............................................................. 42-24 42-7 cps rxqd field desc riptions............................................................................................ 42-2 7 42-8 cps rxbd field desc riptions ............................................................................................ 42-2 8 42-9 cps switch rxqd fiel d descriptions................................................................................ 42-29 42-10 switch rxbd field descriptions ........................................................................................ 42-3 0 42-11 sssar rxqd field de scriptions....................................................................................... 42-31 42-12 sssar rxbd field de scriptions....................................................................................... 42-33 42-13 aal2 paramete r ram ....................................................................................................... 4 2-34 42-14 aal2 interrupt queue entry cid 0 field descriptions.................................................. 42-38 42-15 aal2 interrupt queue entry cid = 0 field descri ptions.................................................. 42-39 43-1 spmode field desc riptions ................................................................................................ 43 -6 43-2 example conve ntions ........................................................................................................ ... 43-8 43-3 spie/spim field de scriptions .............................................................................................. 4 3-9 43-4 spcom field desc riptions................................................................................................. 43 -10 43-5 spi parameter ram memory map .................................................................................... 43-10 43-6 rfcr/tfcr field desc riptions .. ....................................................................................... 43-12 43-7 spi commands............................................................................................................... ..... 43-12 43-8 spi rxbd status and contro l field descriptions............................................................... 43-14 43-9 spi txbd status and contro l field descriptions............................................................... 43-15 44-1 i2mod field de scriptions................................................................................................... . 44-6 44-2 i2add field desc riptions ................................................................................................... . 44-7 44-3 i2brg field de scriptions................................................................................................... .. 44-7 44-4 i2cer/i2cmr field descriptions........................................................................................ 44-8 44-5 i2com field de scriptions................................................................................................... . 44-9 44-6 i 2 c parameter ram memory map....................................................................................... 44-9 44-7 rfcr, tfcr field de scriptions . ....................................................................................... 44-11 44-8 i 2 c transmit/receive commands....................................................................................... 44-11 44-9 i 2 c rxbd status and c ontrol bits...................................................................................... 44-13 44-10 i 2 c txbd status and c ontrol bits ...................................................................................... 44-14 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor cix tables table number title page number 45-1 podra field de scriptions................................................................................................... 45-2 45-2 podrb field desc riptions ................................................................................................... 45-3 45-3 podrc field desc riptions ................................................................................................... 45-3 45-4 podrd field de scriptions................................................................................................... 45-4 45-5 pdira field de scriptions ................................................................................................... . 45-7 45-6 pdirb field de scriptions ................................................................................................... . 45-8 45-7 pdirc field de scriptions ................................................................................................... . 45-9 45-8 pdird field de scriptions ................................................................................................... . 45-9 45-9 ppara field desc riptions.................................................................................................. 4 5-10 45-10 pparb field de scriptions .................................................................................................. 45-11 45-11 pparc field de scriptions .................................................................................................. 45-12 45-12 ppard field de scriptions.................................................................................................. 45-12 45-13 psor x field descript ions .................................................................................................. 45-13 45-14 psorb field de scriptions.................................................................................................. 45-14 45-15 psorc field de scriptions.................................................................................................. 45-15 45-16 psord field desc riptions ................................................................................................. 4 5-15 45-17 port a dedicated pin assi gnment (ppara = 1) ................................................................ 45-18 45-18 port b dedicated pin assi gnment (pparb = 1) ................................................................ 45-21 45-19 port c dedicated pin assi gnment (pparc = 1) ................................................................ 45-22 45-20 port d dedicated pin assi gnment (ppard = 1) ................................................................ 45-24 a-1 mpc8541e internal memory map ........................................................................................ a-9 a-2 port a dedicated pin assi gnment (ppara = 1) ................................................................. a-15 a-3 port b dedicated pin assi gnment (pparb = 1) ................................................................. a-17 a-4 port c dedicated pin assi gnment (pparc = 1) ................................................................. a-18 a-5 port d dedicated pin assi gnment (ppard = 1) ................................................................. a-19 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 cx freescale semiconductor tables table number title page number 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor cxi about this book this reference manual defines the functionality of the MPC8555E and mpc8541e. it is written from the perspective of the MPC8555E, which is the superset device. for specifics on how to use this manual for the mpc8541e, see appendix a, ?mpc8541e.? the MPC8555E powerquicc? iii is a next-genera tion powerquicc? ii integrated communications processor. the MPC8555E provides integration of proce ssing power for networki ng and communications peripherals, resulting in higher device performa nce. the MPC8555E contains a powerpc? processor core built on power architecture? technology. the e 500 processor core is a low-power implementation of the family of reduced instru ction set computing (risc) embedde d processors that implement the embedded category features of the power architecture technology. this book is intended as a companion to the powerpc? e500 core family reference manual. audience it is assumed that the reader understands operating systems, microprocessor sy stem design, and the basic principles of risc processing. organization following is a summary and a brief description of the major parts of this reference manual: part i, ?overview,? describes the many features of the mpc855 5e integrated communication processor at an overview level. the following chapters are included: ? chapter 1, ?overview,? provides a high-level description of features and functionality of the MPC8555E integrated communicati on processor. it describes th e MPC8555E, its interfaces, and its programming model. the functional operation of the mpc 8555e with emphasis on peripheral functions is also described. ? chapter 2, ?memory map,? describes the memory map of the MPC8555E. an overview of the local address map is followed by a description of how local access windows are used to define the local address map. the inbound and outbound address translation mech anisms used to map to and from external memory spaces are described next. finally, the conf iguration, control, and status registers are described, including a complete list ing of all memory-mapped registers with cross references to the sections de tailing descriptions of each. ? chapter 3, ?signal descriptions,? provides a listing of all the exte rnal signals, cross-references for signals that serve multiple functi ons, output signal states at reset, and reset configuration signals (and the modes they define). ? chapter 4, ?reset, clocking, and initialization,? describes the hard and soft resets, the power-on reset (por) sequence, power-on reset configur ation, clocking, and initialization of the MPC8555E. 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 cxii freescale semiconductor part ii, ?e500 core comp lex and l2 cache,? describes the many f eatures of the mpc 8555e core processor at an overview level and the interaction between th e core complex and the l2 cache. the following chapters are included: ? chapter 5, ?core complex overview,? provides an overview of the e500 core processor and the l1 caches and mmu that, together with the core, comprise the core complex. ? chapter 6, ?core register summary,? provides a listing of the e500 registers in reference form. ? chapter 7, ?l2 look-aside cache/sram,? describes the l2 cache of the MPC8555E. note that the l2 cache can also be addresse d directly as memory-mapped sram. part iii, ?memory, security, and i/o interfaces,? defines the memory, security and i/o interfaces of the MPC8555E and how these blocks interact with one another and with other blocks on the device. the following chapters are included: ? chapter 8, ?e500 coherency module,? defines the e500 coherency module and how it facilitates communication between the e500 core complex, the l2 cache, and the other blocks that comprise the coherent memory domain of the MPC8555E. the ecm provides a mechanism for i/o-initiated transactions to snoop the core complex bus (ccb) of the e500 core in orde r to maintain cohere ncy across cacheable local memory. it also provides a flexible, easily expandabl e switch-type structure for e500- and i/o-initiated transactions to be routed (dispatched) to target modules on the MPC8555E. ? chapter 9, ?ddr memory controller,? describes the ddr sdram memory controller of the MPC8555E. this fully programmabl e controller supports most dd r memories available today, including both buffered and unbuffere d devices. the built-in error checking and correction (ecc) ensures very low bit-error rates for reli able high-frequency ope ration. dynamic power management and auto-precharge modes simplify memory system design. a large set of special features like dll software override, crawl mode , and ecc error injection support rapid system debug. ? chapter 10, ?programmable interrupt controller,? describes the em bedded programmable interrupt controller (pic) of th e MPC8555E. the pic is an openpic-compliant interrupt controller that provides interrupt ma nagement and is responsible for re ceiving hardware-generated interrupts from different sources (both inte rnal and external), prioritizing them and delivering them to the cpu for servicing. ? chapter 11, ?i 2 c interface,? describes the inter-ic (iic or i 2 c) bus controller of the MPC8555E. this synchronous, serial, bidirect ional, multiple-master bus al lows two-wire connection of devices, such as microcontroller s, eeproms, real-time clock devi ces, a/d converters and lcds. the MPC8555E powers up in boot seque ncer mode which allows the i 2 c controller to initialize configuration registers. ? chapter 12, ?duart,? describes the (dual) universal asynchronous receiver/transmitters (uarts) which feature a pc16552d-compatible pr ogramming model. thes e independent uarts are provided specifically to support system debugging. ? chapter 13, ?local bus controller,? describes the MPC8555E local bus controller. the main component of the local bus controller (lbc) is its memory controller which provides a seamless interface to many types of memory devices and pe ripherals. the memory c ontroller is responsible for controlling eight memory banks shared by a high performance sdram machine, a 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor cxiii general-purpose chip-select machine (gpcm), a nd up to three user-programmable machines (upms). as such, it supports a minimal glue l ogic interface to synchr onous dram (sdram), sram, eprom, flash eprom, burstable ram, re gular dram devices, extended data output dram devices, and other peripherals. ? chapter 14, ?three-speed ethernet controllers,? describes the 2 three-speed ethernet controllers on the MPC8555E. these controllers provide 10/100/1g b ethernet support with a complete set of media-independent interface opti ons including gmii, rgmii, tbi, and rtbi. each controller provides very high throughput using a captive dm a channel and direct connection to the MPC8555E memory coherency module. ? chapter 15, ?dma controller,? describes the four-cha nnel general-purpose dm a controller of the MPC8555E. the dma controller transf ers blocks of data independent of the e500 core or external hosts. data movement occurs among the local a ddress space. the dma controller has four high-speed channels. both the e500 core and exte rnal masters can initiate a dma transfer. all channels are capable of complex data m ovement and advanced transaction chaining. ? chapter 16, ?pci bus interface,? describes the MPC8555E pci controller. ? chapter 17, ?security engine (sec) 2.0,? describes the MPC8555E security controller. part iv, ?global functions and debug,? defines other global blocks of the MPC8555E. the following chapters are included: ? chapter 18, ?global utilities,? defines the global utilities of the MPC8555E. these include power management, i/o device enabling, power- on-reset (por) confi guration monitoring, general-purpose i/o signal use, a nd multiplexing for the interrupt and local bus chip select signals ? chapter 19, ?performance monitor,? describes the performance m onitor of the MPC8555E. note that the MPC8555E performance m onitor is similar to but separa te from the performance monitor implemented on the e500 core. ? chapter 20, ?debug features and watchpoint facility,? describes the debug features and watchpoint monitor of the MPC8555E. part v, ?cpm features,? defines the MPC8555E cpm blocks. th e following chapters are included: ? chapter 21, ?communications processor module overview,? provides a high-level summary of the MPC8555E features and memory map. ? chapter 22, ?cpm interrupt controller,? describes the MPC8555E cpm interrupt controller. ? chapter 23, ?serial interface with time-slot assigner,? describes the MPC8555E serial interface and tsa. ? chapter 24, ?cpm multiplexing,? describes how the cpm multip lexing logic (cmx) connects the physical layer (utopia, mii, mode m lines, tdm lines, and proprietary serial lines) to the fccs and sccs. ? chapter 25, ?baud-rate generators (brgs),? describes the eight indepe ndent, identical baud-rate generators (brgs) that can be used with the fccs and sccs. ? chapter 26, ?cpm timers,? describes the four identical 16-bi t general-purpose cpm timers that can alternately be used as two 32-bit timers. ? chapter 27, ?sdma channels,? describes the two phys ical serial dma (sdm a) channels of the MPC8555E. 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 cxiv freescale semiconductor ? chapter 28, ?serial communications controllers (sccs),? describes the four serial communications controllers (sccs) which can be confi gured independently to implement different protocols for bridging functions, routers, and gate ways, and to interface w ith a wide variety of standard wans, lans, and proprietary networks. ? chapter 29, ?scc uart mode,? describes how the general scc m ode register (gsmr) is used to configure an scc channel to function in uart mode, which prov ides standard serial i/o using asynchronous character-based (start-stop) protocols with rs-232c-type lines. ? chapter 30, ?scc hdlc mode,? describes how hdlc mode is selected for an scc. in hdlc mode, an scc becomes an hdlc c ontroller, and consists of separate transmit and receive sections whose operations are async hronous with the core and can eith er be synchronous or asynchronous with respect to other sccs. ? chapter 31, ?scc bisync mode,? describes how transparent bisy nc mode allows full binary data to be sent with a ny possible character pattern. ? chapter 32, ?scc transparent mode,? describes how an scc in tran sparent mode functions as a high-speed serial-to-parallel a nd parallel-to-se rial converter. ? chapter 33, ?scc appletalk mode,? describes how the MPC8555E provides localtalk protocol support. the appletalk contro ller provides required frame synchronization, bit sequence, preamble, and postamble onto standard hdlc frames. ? chapter 34, ?quicc multi-channel controller (qmc),? describes the qm c protocol, which emulates up to 64 logical channels within one scc using the same time-division-multiplexed (tdm) physical interface. ? chapter 35, ?universal serial bus controller,? describes the MPC8555E usb controller, including basic operation, the pa rameter ram, and registers. ? chapter 36, ?serial manageme nt controllers (smcs),? describes two serial management controllers, full-duplex ports that can be co nfigured independently to support one of three protocols?uart, transparent, or general-circuit interface (gci). ? chapter 37, ?fast communications controllers (fccs),? describes how the fccs can be configured independently to implement differen t protocols. together, they can be used to implement bridging functions, rout ers, and gateways, and also interface with a wide variety of standard wans, lans, and proprietary networks. ? chapter 38, ?fcc hdlc controller,? describes the MPC8555E fcc hdlc controller. ? chapter 39, ?fcc transparent controller,? describes how the fcc transparent controller functions as a high-speed serial-to-parallel and para llel-to-serial converter. ? chapter 40, ?cpm fast ethernet controller,? describes the fast ethernet controller in the cpm. ? chapter 41, ?atm controller,? describes the atm controller that provides the atm and aal layers of the atm protocol usi ng the universal test and operations physical layer (phy) interface for atm (utopia level ii) for both master and slave modes. ? chapter 42, ?atm aal2,? describes the aal2 microcode package. ? chapter 43, ?serial peripheral interface (spi),? describes the MPC8555E cpm serial peripheral interface (spi). ? chapter 44, ?i 2 c controller,? describes the cpm i 2 c controller. 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor cxv ? chapter 45, ?parallel i/o ports,? describes the four general-purpose i/o ports of the cpm. ? appendix a, ?mpc8541e,? describes the features of the mpc8541e, how it differs from the MPC8555E, and provides additional ma terial and specifics for using this reference manual for the mpc8541e. ? appendix b, ?revision history,? lists the major difference s between revisions of the MPC8555E powerquicc? iii integrated processor reference manual . ? this reference manual also includes a glossary and an index. suggested reading this section lists additional reading that provides bac kground for the information in this manual as well as general information about the architecture. general information the following documentation, published by morgan-kau fmann publishers, 340 pine street, sixth floor, san francisco, ca, provides useful information a bout the power architecture technology and computer architecture in general: ? the powerpc architecture: a specification for a new family of risc processors , second edition, by international business machines, inc. ? computer architecture: a quantitative approach , third edition, by john l. hennessy and david a. patterson ? computer organization and design: the hardware/software interface , second edition, by david a. patterson and john l. hennessy related documentation freescale documentation is availabl e from the sources listed on the back cover of this manual; the document order numbers are included in parentheses for ease in ordering: ? eref: a reference for freescale book e and the e500 core ?this book provides a higher-level view of the programming model as it is defined by the freescale embedded category implementation standards a nd the e500 microprocessor. ? reference manuals (formerly called user?s manuals)?these books provide details about individual implementations . ? addenda/errata to reference or us er?s manuals?because some processors have follow-on parts an addendum is provided that descri bes the additional features and functionality changes. these addenda are intended for use with the co rresponding reference or user?s manuals. ? hardware specifications?hardwar e specifications provide speci fic data regarding bus timing, signal behavior, and ac, dc, and th ermal characteristics, as well as other design considerations. ? application notes?these short documents address specific design issues us eful to programmers and engineers working with freescale processors. additional literature is published as new processors become av ailable. for a current list of documentation, refer to http://www.freescale.com. 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 cxvi freescale semiconductor conventions this document uses the foll owing notational conventions: cleared/set when a bit takes the valu e zero, it is said to be clea red; when it ta kes a value of one, it is said to be set. mnemonics instruction mnemonics are shown in lowercase bold italics italics indicate variable command parameters, for example, bcctr x book titles in text are set in italics internal signals are set in lo wercase italics, for example, core_int 0x0 prefix to denote hexadecimal number 0b0 prefix to denote binary number r a, r b instruction syntax used to identify a source gpr r d instruction syntax used to identify a destination gpr reg[field] abbreviations for registers are shown in uppercase text. specific bits, fields, or ranges appear in brackets. for example, ms r[le] refers to the little-endian mode enable bit in the machine state register. x in some contexts, such as signal enc odings, an unitalicized x indicates a don?t care. x an italicized x indicates an alphanumeric variable n an italicized n indicates a numeric variable ? not logical operator & and logical operator | or logical operator || concatenation, for example tcr[wp]||tcr[wpext] indicates a reserved bit field in an e500 register. although these bits can be written to as ones or zeros, they are always read as zeros. indicates a reserved bit field in a me mory-mapped register. although these bits can be written to as ones or zeros, they are always read as zeros. indicates a read-only bit field in a memory-mapped register. indicates a write-only bit fi eld in a memory-mapped regi ster. although these bits can be written to as ones or zeros, they are always read as zeros. ? r0 w rfieldname w r w fieldname 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor cxvii signal conventions overbar an overbar indicates that a signal is active-low. lowercase_italics lowercase italics is used to indicate internal signals. lowercase_plaintext lowercase plain text is used to indicate signals that are used for configuration. for more information, see section 3.2, ?configuration si gnals sampled at reset.? acronyms and abbreviations table i contains acronyms and abbrevia tions used in this document. table i. acronyms and abbreviated terms term meaning adb allowable disconnect boundary atm asynchronous transfer mode atmu address translation and mapping unit bd buffer descriptor bist built-in self test bri basic rate interface btb branch target buffer buid bus unit id cam content-addressable memory ccb core complex bus ccsr configuration control and status register cept confrence des administrations europenes des post es et tlcommunications (european conference of postal and telecommunications administrations) col collision cpm communication processor module crc cyclic redundancy check crs carrier sense ddr double data rate dma direct memory access dpll digital phase-locked loop dram dynamic random access memory duart dual universal asynchronous receiver/transmitter ea effective address ecc error checking and correction ecm e500 coherency module 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 cxviii freescale semiconductor eest enhanced ethernet serial transceiver ehpi enhanced host port interface eprom erasable programmable read-only memory fcs frame-check sequence gci general circuit interface gmii gigabit media independent interface gpcm general-purpose chip-select machine gpio general-purpose i/o gpr general-purpose register gui graphical user interface hdlc high-level data link control i 2 c inter-integrated circuit idl inter-chip digital link ieee institute of electrical and electronics engineers ipg interpacket gap irda infrared data association isdn integrated services digital network itlb instruction translation lookaside buffer iu integer unit jtag joint test action group lae local access error law local access window lbc local bus controller lifo last-in-first-out lru least recently used lsb least-significant byte lsb least-significant bit lsu load/store unit mac multiply accumulate, media access control mdi medium-dependent interface mesi modified/exclusive/shared/invalid?cache coherency protocol mii media independent interface mmu memory management unit table i. acronyms and abbreviated terms (continued) term meaning 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor cxix msb most-significant byte msb most-significant bit nmsi nonmultiplexed serial interface no-op no operation ocean on-chip network osi open systems in terconnection pci peripheral component interconnect pcmcia personal computer memory card international association pcs physical coding sublayer pic programmable interrupt controller pma physical medium attachment pmd physical medium dependent por power-on reset pri primary rate interface rgmii reduced gigabit media independent interface risc reduced instruction set computing rtos real-time operating system rwitm read with intent to modify rwm read modify write rx receive rxbd receive buffer descriptor scc serial communication controller scp serial control port sdlc synchronous data link control sdma serial dma sfd start frame delimiter si serial interface siu system interface unit smc serial management controller sna systems network architecture spi serial peripheral interface spr special-purpose register sram static random access memory table i. acronyms and abbreviated terms (continued) term meaning 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 cxx freescale semiconductor tap test access port tbi ten-bit interface tdm time-division multiplexed tlb translation lookaside buffer tsa time-slot assigner tsec three-speed ethernet controller tx transmit txbd transmit buffer descriptor uart universal asynchronous receiver/transmitter upm user-programmable machine usb universal serial bus utp unshielded twisted pair va virtual address zbt zero bus turnaround table i. acronyms and abbreviated terms (continued) term meaning 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor i-1 part i overview this part describes the many features of the MPC8555E integrated processor at an overview level. the following chapters are included: ? chapter 1, ?overview? ? chapter 2, ?memory map? ? chapter 3, ?signal descriptions? ? chapter 4, ?reset, clocking, and initialization? chapter 1, ?overview,? provides a high-level description of fe atures and functionality of the MPC8555E integrated processor. it descri bes the MPC8555E, its in terfaces, and programming model. the functional operation of the MPC8555E with emphasis on peripheral functions is also described. chapter 2, ?memory map,? describes the MPC8555E memory map. an overview of the local address map is followed by a description of how local access wi ndows are used to define the local address map. the inbound and outbound address tran slation mechanisms used to map to and from ex ternal memory spaces are described next. finally, the conf iguration, control, and status re gisters are described, including a complete listing of all memory mapped registers with cr oss references to the secti ons detailing descriptions of each. chapter 3, ?signal descriptions,? provides a listing of all the external signals, cro ss-references for signals that serve multiple functions, output signal states at reset, and reset configuration signals (and the modes they define). chapter 4, ?reset, clocking, and initialization,? describes the hard and so ft resets, power-on reset sequence, power-on reset (por) configuration, clocking, and initialization of the MPC8555E. 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 i-2 freescale semiconductor 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 1-1 chapter 1 overview freescale semiconductor's MPC8555E powerquicc? iii integrated communications processor includes a wide range of advanced freescale technologies, modular co res, and peripherals. leveraging freescale's system-on-chip (soc) powerquicc iii platfo rm architecture, the MPC8555E combines the powerful e500 core and communicati ons peripheral technology to balanc e processor perfor mance with i/o system throughput. the proc essor is designed to offer clock speeds scaling from 533 mhz to 1 ghz. this chapter provides a high-level description of featur es and functionality of the MPC8555E and mpc8541e integrated communications processors. it is written from the perspective of the MPC8555E, which is the superset device. for specifics on how to use th is manual for the mpc8541e, see appendix a, ?mpc8541e.? 1.1 introduction freescale's MPC8555E device inte grates two processing blocks: a high-performance e500 core that implements the power architecture? definition of the embedded category instruction set architecture and a risc-based communications proce ssor module (cpm) that supports a wide range of communications peripherals. this innovativ e architecture is designed to reduce power consumption and offer a more balanced approach to processing than traditional processor architectures. th e cpm offloads low-level peripheral communications tasks, enabling the embe dded e500 core to manage high-level processing tasks. the MPC8555E device's high level of integr ation helps simplify boa rd design and enhances system-level bandwidth and performa nce. in addition to the e500 core and cpm, the MPC8555E features an integrated security engine, a double data rate sdram (ddr sd ram) memory controller, dual gigabit ethernet controllers, a four-channel dma controller , dual asynchronous receiver /transmitters (duart), and a 64-bit pci controller that can also serve as two 32-bit pci ports. dual on-chip pci support provides a cost-effective alternative to separate , discrete pci bridges a nd chipsets for i/o-intens ive applications that require multiple pci interfaces. in addition to these features, the MPC8555E provides a local bus controller and i 2 c support. the MPC8555E processor features a security engine that supports des, 3des, md-5, sha-1, aes, and arc-4 encryption algorithms, as we ll as offering a public key acceler ator and on-chip random number generator. this embedded s ecurity core is derived from freescale' s security coprocessor product line and offers the same direct-memory access (dma) and parallel processing capabilit ies, as well as the ability to perform single-pass encryption and au thentication as required by widely us ed security prot ocols, such as ipsec and ieee 802.11i? standard. integrated securi ty makes the MPC8555E an optimal communications processor solution for applications th at require security feat ures in concert with high performance and low system-level cost. 4 datasheet u .com
overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 1-2 freescale semiconductor 1.2 MPC8555E overview the following section provides a high-le vel overview of the MPC8555E features. figure 1-1 shows the major functional units within the MPC8555E. figure 1-1. MPC8555E block diagram 1.2.1 key features the following lists an overview of the MPC8555E feature set: ? embedded e500 core ? high-performance, 32-bit core that impl ements the embedded category of the power architecture technology ? dual-issue superscalar, 7-stage pipeline design ? 32-kbyte l1 instruction cache and 32-kbyt e l1 data cache with parity protection ? lockable l1 caches?entire cache or on a per-line basis ? separate locking for instructions and data ? single-precision floa ting-point operations ? memory management unit especially designed for embedded applications ? enhanced hardware and software debug support i 2 c controller local bus controller 64/32b pci controller 0/32b pci controller dma controller 10/100/1000 mac 10/100/1000 mac mii, gmii, tbi, rtbi, rgmiis serial dma rom i-memory dpram risc engine parallel i/o baud rate generators timers fcc fcc scc/usb smc spi i 2 c time-slot assigner serial interfaces mphy miis/rmiis tdms i/os cpm ddr sdram controller cpm controller interrupt 256-kbyte l2 cache/ sram e500 core 32-kbyte l1 i cache core complex e500 coherency module ocean irqs sdram ddr gpio 32b programmable interrupt controller utopia bus duart scc smc scc security engine 32-kbyte l1 d cache 4 datasheet u .com
overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 1-3 ? dynamic power management ? performance monitor facility ? the security engine is optimized to handle all the algorithm s associated with ipsec, ssl/tls, srtp, 802.11i standard, iscsi, and ike proces sing. the security engine contains four crypto-channels, a controller, and a set of crypto execution units (eus). the execution units are: ? public key execution unit (pkeu) supporting the following: ? rsa and diffie-hellman ? programmable field size up to 2048 bits ? elliptic curve cryptography ? f2m and f(p) modes ? programmable field size up to 511 bits ? data encryption standa rd execution unit (deu) ? des, 3des ? two key (k1, k2) or three key (k1, k2, k3) ? ecb and cbc modes for both des and 3des ? advanced encryption standard unit (aesu) ? implements the rinjdael symmetric key cipher ? key lengths of 128, 192, and 256 bits, two key ? ecb, cbc, ccm, and counter modes ? arc four execution unit (afeu) ? implements a stream cipher comp atible with the rc4 algorithm ? 40- to 128-bit programmable key ? message digest execution unit (mdeu) ? sha with 160- or 256-bit message digest ? md5 with 128-bit message digest ? hmac with either algorithm ? random number generator (rng) ? four crypto-channels, each supporting multi-command descriptor chains ? static and/or dynamic assignmen t of crypto-execution units through an integrated controller ? buffer size of 256 bytes for each execution unit, with flow control for large data sizes ? high-performance risc cp m operating at up to 333 mhz ? cpm software compatibility with previous powe rquicc families ? one instruction per clock ? executes code from intern al rom or instruction ram ? 32-bit risc architecture ? tuned for communication environments: instru ction set supports crc computation and bit manipulation ? internal timer 4 datasheet u .com
overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 1-4 freescale semiconductor ? interfaces with the embedded e500 core pr ocessor through a 32-kbyte dual-port ram and virtual dma channels for e ach peripheral controller ? handles serial protocols and virtual dma ? two full-duplex fast communica tions controllers (fccs) that support the following protocols: ? atm protocol through two utopia level ii interfaces ? ieee 802.3? standard/fast ethernet ? hdlc ? totally transparent operation ? three full-duplex serial communi cations controllers (sccs) support the following protocols: ? high level/synchronous data link control (hdlc/sdlc) ? localtalk (hdlc-based local area network protocol) ? universal asynchronous receiver transmitter (uart) ? synchronous uart (1x clock mode) ? binary synchronous communication (bisync) ? totally transparent operation ? qmc support, providing 64 channels per scc using only 1 physical tdm interface ? universal serial bus (usb) cont roller that is full-/low-spee d compliant (multiplexed on an scc) ? usb host mode ? supports usb slave mode ? serial peripheral interface (spi ) support for master or slave ?i 2 c bus controller ? two serial management c ontrollers (smcs) supporting: ? uart ? transparent ? general-circuit interfaces (gci) ? time-slot assigner supports multiplexing of data from any of the sccs and fccs onto eight time-division multiplexed (tdm) interfaces. th e time-slot assigner supports the following tdm formats: ? t1/cept lines ?t3/e3 ? pulse code modulation (pcm) highway interface ? isdn primary rate ? freescale interchi p digital link (idl) ? general circuit interface (gci) ? user-defined interfaces ? eight independent baud rate generators (brgs) ? four general-purpose 16-bit ti mers or two 32-bit timers 4 datasheet u .com
overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 1-5 ? general-purpose parallel ports?16 parallel i/o lines with interrupt capability ? supports inverse muxing of atm cells (ima) ? 256 kbytes of on-chip memory ? can act as a 256- kbyte level-2 cache ? can act as a 256-kbyte or two 128- kbyte memory-mapped sram arrays ? can be partitioned into 128-k byte l2 cache plus 128-kbyte sram ? full ecc support on 64-bit boundary in both cache and sram modes ? sram operation supports reloca tion and is byte-accessible ? cache mode supports instructi on caching, data caching, or both ? external masters can force data to be allo cated into the cache through programmed memory ranges or special transaction types (stashing) ? eight way set-associativ e cache organization (1024 se ts of 32-byte cache lines) ? supports locking the entire cache or selected lines ? individual line locks set and cleared through instructions or by externally mastered transactions ? global locking and flash cl earing done through writes to l2 configuration registers ? instruction and data locks ca n be flash cleared separately ? read and write buffering for internal bus accesses ? address translation and mapping unit (atmu) ? eight local access windows define mappi ng within local 32-bit address space ? inbound and outbound atmus map to larger external address spaces ? three inbound windows plus a c onfiguration window on pci ? four outbound windows plus default translation for pci ? ddr memory controller ? programmable timing supporti ng first generation ddr sdram ? 64-bit data interface, up to 333-mhz data rate ? four banks of memory supported, each up to 1 gbyte ? dram chip configurations from 64 mb its to 1 gbit with x8/x16 data ports ? full ecc support ? page mode support (up to 16 simultaneous open pages) ? contiguous or discontiguous memory mapping ? sleep mode support for self refresh ddr sdram ? supports auto refreshing ? on-the-fly power manage ment using cke signal ? registered dimm support ? fast memory access through jtag port ? 2.5-v sstl2 compatible i/o 4 datasheet u .com
overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 1-6 freescale semiconductor ? programmable interrupt controller (pic) ? programming model is compliant with the openpic architecture ? supports 16 programmable interrupt a nd processor task priority levels ? supports 12 discrete external interrupts ? supports 4 message interrupts with 32-bit messages ? supports connection of an external interrupt controller such as the 8259 programmable interrupt controller ? four global high resolution timers/count ers that can generate interrupts ? supports additional internal interrupt sources ? supports fully nested interrupt delivery ? interrupts can be routed to exte rnal pin for external processing ? interrupts can be routed to the e500 core ?s standard or critical interrupt inputs ? interrupt summary registers allow fa st identification of interrupt source ?two i 2 c controllers (one is c ontained within the cpm, the other is a stand-alone controller which is not part of the cpm) ? two-wire interface ? multiple master support ? master or slave i 2 c mode support ? on-chip digital filtering rejects spikes on the bus ? boot sequencer ? optionally loads configuration data from se rial rom at reset thro ugh the stand-alone i 2 c interface ? can be used to initialize conf iguration registers and/or memory ? supports extended i 2 c addressing mode ? data integrity checked with preamble signature and crc ? duart ? two 4-wire interfaces (rxd, txd, rts, cts) ? programming model compat ible with the origin al 16450 uart and the pc16550d ? local bus controller (lbc) ? multiplexed 32-bit address and data operating at up to 166 mhz ? eight chip selects support eight external slaves ? up to eight-beat burst transfers ? the 32-, 16-, and 8-bit port sizes are cont rolled by an on-chip memory controller ? three protocol engines availabl e on a per chip select basis: ? general-purpose chip select machine (gpcm) ? three user-programmable machines (upms) ? dedicated single-data-rate sdram controller 4 datasheet u .com
overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 1-7 ? parity support ? default boot rom chip select with conf igurable bus width (8-, 16-, or 32-bit) ? two three-speed (10/100/1000) ethernet controllers (tsecs) ? dual ieee 802.3, 802.3u?, 802.3x?, 802.3z?, 802.3ac? standard compliant controllers ? support for different ethe rnet physical interfaces: ? 10/100/1000 mbps ieee 802.3 standard gmii ? 10/100 mbps ieee 802.3 standard mii ? 10 mbps ieee 802.3 standard mii ? 1000 mbps ieee 802.3z standard tbi ? 10/100/1000 mbps rgmii/rtbi ? full- and half-duplex support ? buffer descriptors are backwards comp atible with mpc8260 and mpc860t 10/100 programming models ? 9.6-kbyte jumbo frame support ? rmon statistics support ? 2-kbyte internal transmit and receive fifos ? mii management interface for control and status ? programmable crc ge neration and checking ? ocean switch fabric ? three-port crossbar packet switch ? reorders packets from a source based on priorities ? reorders packets to bypass blocked packets ? implements starvation avoidance algorithms ? supports packets with pa yloads of up to 256 bytes ? integrated dma controller ? four-channel controller ? all channels accessible by bot h local and remote masters ? extended dma functions (advanced chaining and striding capability) ? support for scatter and gather transfers ? misaligned transfer capability ? interrupt on completed segm ent, link, list, and error ? supports transfers to or from any local memory or i/o port ? selectable hardware-enfor ced coherency (snoop/no-snoop) ? ability to start and flow control each dma channel from external 3-pin interface ? ability to launch dma from single write transaction ?pci controllers ? pci 2.2 compatible 4 datasheet u .com
overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 1-8 freescale semiconductor ? one 64-bit or two 32-bit pci ports supported at 16 to 66 mhz ? host and agent mode support, 64- bit pci port can be host or agen t, if two 32-bit ports, only one can be an agent ? 64-bit dual address cycle (dac) support ? supports pci-to-memory and memory-to-pci streaming ? memory prefetching of pci read accesses ? supports posting of processor-to -pci and pci-to -memory writes ? pci 3.3-v compatible ? selectable hardware-enforced coherency ? selectable clock source (sys clk or independent pci_clk) ? power management ? fully static 1.2-v cmos de sign with 3.3- and 2.5-v i/o ? supports power save mode s: doze, nap, and sleep ? employs dynamic power management ? system performance monitor ? supports eight 32-bit counters that count the occurrence of selected events ? ability to count up to 512 counter-specific events ? supports 64 reference events that can be counted on any of the 8 counters ? supports duration and quant ity threshold counting ? burstiness feature that permits counting of burst events with a programmable time between bursts ? triggering and chaining capability ? ability to generate an interrupt on overflow ? system access port ? uses jtag interface and a tap controller to access entire system memory map ? supports 32-bit accesses to configuration registers ? supports cache-line burst accesses to main memory ? supports large block (4-kbyte) uploads and downloads ? supports continuous bit stre aming of entire block for fast upload and download ? ieee 1149.1? compliant, jtag boundary scan ? 783-pin fc-pbga package 4 datasheet u .com
overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 1-9 1.3 MPC8555E architecture overview the following sections describe the major functional units of the MPC8555E. 1.3.1 e500 core overview the MPC8555E uses the e500 microprocessor core co mplex. both the e500 core and the cpm have internal plls that allow independent optimization of their operating frequencies. the core and cpm frequencies are derived from either the primary pci clock input or an external oscillator. for more information regarding the e500 core refer to the following documents: ? eref: a reference for freescale semiconductor book e and the e500 core ? powerpc? e500 core family reference manual ? powerpc? e500 application binary interface user's guide the following is a brief list of some of th e key features of the e500 core complex: ? 32-bit architecture ? implements additional instructions , registers, and interrupts (formerly referred to as apus). the signal processing engine (spe) provides an extens ive instruction set for 64-bit vector integer, single-precision floating-point, a nd fractional operations. the sp fp provides scalar (32-bit) single-precision floating- point instructions. note the spe and spfp functionality will be implemented in all powerquicc iii devices. however, these instructions will not be supported in devices subsequent to powerquicc iii. freescale strongly recommends that use of these instructions be conf ined to libraries and device drivers. customer software that uses spe or spfp instructions at the assembly level or that uses spe intrinsics will re quire rewriting for upward compatibility with next-generati on powerquicc devices. freescale offers a libcfs l_e500 library that uses spe and spfp instructions. freescale will also provide future libraries to support next generation powerquicc devices. ? l1 cache structure ? 32?kbyte, 32-byte line, eight way set-associative instruction cache ? 32?kbyte, 32-byte line, eight wa y set-associative data cache ? 1.5-cycle cache array access, 3-cycle load-to-use latency ? pseudo-lru replacement algorithm ? copy-back data cache ? dual-dispatch superscalar ? precise exception handling ? seven-stage pipeline control ? instruction unit 4 datasheet u .com
overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 1-10 freescale semiconductor ? twelve-entry instruction queue ? full hardware detection of interlocks ? dispatch up to two instructions per cycle ? dispatch serialization control ? register dependency resolution and renaming ? branch unit (bu) ? dynamic branch prediction ? two-entry branch in struction queue (biq) ? executes all branch and cr logical instruction ? completion unit ? as many as 14 instructions al lowed in 14-entry completion queue ? in-order retirement of up to two instructions per cycle ? completion and refetch serialization control ? synchronization for all instruction flow ch anges?interrupts and mispredicted branches ? two simple execution units that perform: ? single-cycle add and subtract ? single-cycle shift and rotate ? single-cycle logical operations ? multiple-cycle execution unit (mu) ? four-cycle latency for multiplication (incl uding floating-point multiply instructions). ? variable-latency divide: 4, 11, 19, and 35 cycles fo r all divide instructions. note that the mu allows divide instructions to bypass the second two mu pipeline stages, freeing those stages for other mu instructions to execute in parallel. ? four-cycle floating-point multiply ? four-cycle floating-point add and subtract ? single-precision floa ting-point operations ? load/store unit (lsu) ? three-cycle load latency ? fully pipelined ? four-entry load queue allows up to four load misses before stalling ? can continue servicing load hits when load queue is full ? six-entry store queue allows full pipelining of stores ? cache coherency ? bus support for hardware-enf orced coherency (bus snooping) ? core complex bus (ccb) ? high-speed, on-chip local bus with data tagging ? 32-bit address bus ? 60x-like address protocol with a ddress pipelining and retry/copyback 4 datasheet u .com
overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 1-11 ? two general-purpose read data, one write data bus ? 128-bit data plus parity/tags (each data bus) ? supports out-of-order reads, in-order writes ? little to no data bus arbitration logic require d for native systems ? easily adaptable to 60x-like environments ? supports one-level pipelining of addr esses with address-retry responses ? extended exception handling ? supports embedded cate gory interrupt model ? interrupt vector prefix register (ivpr) ? vector offset regist ers (ivors) 0?15 and 32?35 ? exception syndrome register (esr) ? preempting critical interrupt , including critical interrupt status registers (csrr0 and csrr1) and an rfci instruction ? a separate set of resources for machine-check interrupts ? spe unavailable exception ? floating-point data exception ? floating-point round exception ? performance monitor ? memory management unit (mmu) ? data l1 mmu ? four-entry, fully-associative tlb array for variable-sized pages ? 64-entry, four way set-associative tlb for 4-kbyte pages ? instruction l1 mmu ? four-entry, fully-associative tlb array for variable-sized pages ? 64-entry, four way set-associative tlb for 4-kbyte pages ? unified l2 mmu ? 16-entry, fully-associative tlb array for variable-sized pages ? 256-entry, two way set-associative tlb for 4-kbyte pages ? software reload for tlbs ? virtual memory support for as much as 4 gbytes (2 32 ) of virtual memory ? real memory support for as much as 4 gbytes (2 32 ) of physical memory ? support for big-endian and true little-endian memory on a per-page basis ? power management ? low power design ? 1.2-v design ? dynamic power management on the core mini mizes power consumption of functional unit, such as execution units, caches, and mmus, when they are idle. ? power-saving modes: standby and shutdown 4 datasheet u .com
overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 1-12 freescale semiconductor ? internal clock multipliers of 2x, 2.5x, and 3x from bus clock ? testability ? lssd scan design ? jtag interface ? esp support ? reliability and serviceability ? internal code parity ? parity checking on e500 local bus 1.3.2 integrated security engine (sec) a block diagram of the integrated security engine?s internal architecture is shown in figure 1-2 . the bus interface module is designed to transf er 64-bit words between the internal bus and any regi ster inside the sec. an operation begins with a write of a pointer to a crypto-channel fetch register which points to a data packet descriptor. the channel re quests the descriptor and decodes the operation to be performed. the channel then requests the controller to assign crypto execution units and fetch the keys, ivs, and data needed to perform the given operation. the controller satisfies the requests by assigning execution units to the channel and by making requests to the master inte rface. as data is processe d, it is written to the individual execution unit?s output buffer and then b ack to system memory through the bus interface module. the sec functionality is compatible with code written for the freescale mpc185 encryption device. figure 1-2. integrated security engine functional blocks crypto- channel master/slave interface control pkeu deu fifo fifo fifo rng fifo fifo aesu fifo fifo fifo fifo afeu crypto- channel crypto- channel crypto- channel mdeu 4 datasheet u .com
overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 1-13 1.3.3 communications processor module (cpm) the cpm contains features that al low the MPC8555E to excel in a vari ety of applications targeted for networking and telecommunication markets. the MPC8555E cpm is a superset of the mpc8260 powerquicc ii, with enhanced communications processor (cp) performance. the cpm also has additional hardware and micr ocode routines that support high bit rate protocols like atm (up to 155 mbps full-duplex) and fast ethernet (100 mbps full-duplex). the MPC8555E cp m features are very similar to those of the powerquicc ii devices, such as th e mpc8272. existing powerquicc ii code should port easily to the MPC8555E. figure 1-3 shows the major functional units within the MPC8555E cpm. figure 1-3. MPC8555E communications pr ocessor module (cpm) block diagram baud rate generators system bus 2 fccs scc1 scc4 2 smcs i 2 c 4 timers parallel i/o ports bus interface sdma dual-port ram communications rom internal bus peripheral bus time-slot assigner (tsa) cpm interrupt controller local bus cpm int processor spi serial interface (si) scc3/ usb 4 datasheet u .com
overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 1-14 freescale semiconductor the following list summarizes the major features of the cpm: ? the communications processor (cp) is an embedded 32-bit risc c ontroller residing on a separate bus (cpm local bus). with this separate bus, th e cp does not affect the performance of the e500 core. the cp handles the lower-la yer tasks and dma cont rol activities, leaving the e500 core free to handle higher-layer activities. the cp has an instruction set optimized for communications but that can also be used for general-purpose applicat ions, relieving the system core of small, often repeated tasks. ? two serial dmas (sdmas), one associated with the local bus and one as sociated with the e500 coherency module (ecm), handli ng transfers simultaneously. ? two full-duplex, serial fast communications controllers (fccs) supporting atm (155 mbps) protocol through two utopia leve l ii interfaces. or the fccs may be configured to support ieee 802.3 fast ethernet, or hdlc up to e3 rate s (45 mbps). each fcc can be configured to transmit fully transparent and re ceive hdlc data or vice-versa. ? three full-duplex serial communi cations controllers (sccs) supporting, hi gh-level synchronous data link control (hdlc), local talk, uart, s ynchronous uart, bisync, or transparent. they also support quicc multichannel control (qmc), which can run 64 channels per scc using only one physical tdm inte rface. scc3 can be confi gured as a usb controller which is full/low speed compliant. ? one full-duplex serial peripheral interface (s pi) providing a synchronou s, character-oriented channel that supports a four-wire interface for communication with other microprocessors, peripheral devices such as eep roms, real-time clocks, a/d c onverters, and isdn devices. ? one i 2 c bus controller providing communication with other i 2 c capable devices, see section 1.3.8, ?i 2 c controllers.? there are actually two i 2 c controllers on the MPC8555E , this one in the cpm and a separate standalone i 2 c controller. ? two full-duplex serial manage ment controllers (smcs) that can be configured as uart, transparent, or general- circuit interfaces (gci). ? time-slot assigner (tsa) that supports multiplexing of data fr om any of the fccs, sccs, or smcs. 1.3.4 on-chip memory unit the MPC8555E contains an internal 256-kbyte memory array that can be configured as memory-mapped sram or as a look-aside l2 cache. the array can also be divided into two 128-kbyte arrays, one of which may be used as cache and the other as sram. the memory controller for this array connects to the core comple x bus (ccb) and communicates through 128-bit read and write buses to the e 500 core and the MPC8555E system logic. the on-chip memory unit contains: ? 256-kbytes of on-chip memory ? l2 cache partitioning is configurable ? can act as a 256-kbyte l2 cache ? 256-kbyte array organized as 1024 eigh t way sets of 32-byte cache lines 4 datasheet u .com
overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 1-15 ? array can be partitioned into 128-kbyte l2 cache and 128-kbyte memory mapped sram ? can act as two 128-kbyte me mory-mapped sram arrays or a 256-kbyte sram region ? sram operation is byte-accessible ? data ecc on 64-bit boundaries (single-er ror correction, double-error detection) ? tag parity (1 bit covering all tag bits) ? cache mode supports instructi on caching, data caching, or both ? external masters can force data to be allo cated into the cache through programmed memory ranges or special transaction types ? separate locking for instructions and data so that locks can be set and cleared separately ? supports locking the entire cache or selected lines ? individual line locks are set and cleared thr ough core-initiated instructions, by external reads or writes, or by accesse s to programmed memory ranges ? flash clearing done th rough writes to l2 configuration registers ? locks for the entire cache may be set and cleared by accesses to memory-mapped control registers 1.3.4.1 on-chip memory as memory-mapped sram when the on-chip memory is configured as an sram , the 256 kbytes of memory can be configured to reside at any aligned location in the memory map. it is byte-accessible and fully ecc protected using read-modify-write transactions for sub-cacheline transactions. i/o device s can access the sram by marking transactions global so that they ar e directed to the core complex bus (ccb). 1.3.4.2 on-chip memory as l2 cache the MPC8555E on-chip memory arrays include a 256-kbyte data array, an address tag array, and a status array. the data array is organized as 1024 se ts of 8 cache lines. each cache line size is 32 bytes. the replacement policy within each eight way set is governed by a ps eudo-lru algorithm. the data is protected with ecc and the tag array is protected by parity. the l2 cache tags are non-blocking fo r efficient load/store and snooping operations. the l2 cache can be accessed internally while a load miss is pending (all owing hits under misses). subsequent to a load miss updating the memory, loads or stores can o ccur to that line on the very next cycle. the l2 status array maintains status bits for each line that are used to determine the status of the line. different combinations of these bits result in different l2 states. note that because the cache is always write-through, there is no modified state. the status bits include: ?v?valid ? il?instruction locked ? dl?data locked all accesses to the l2 memory are fully pipelined so back-to-back loads and stor es can have single-cycle throughput. 4 datasheet u .com
overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 1-16 freescale semiconductor the cache can be configured to allocate instructions-onl y, data-only, or both. it can also be configured to allocate global i/o writes that correspond to a pr ogrammable address window or that use a special transaction type (stashing). in th is way, dma engines or i/o device s can force data into the cache. line locks can be set in a variety of ways. the architecture defines instru ctions that explicitly set and clear locks in the l2. these instructions are supported by the core complex and the l2 controller. in addition, the l2 controller can be configured to lock all lines that fall into either of two specified address ranges when the line is allocated. finally, the entire cache ca n be locked by writing to a configuration register in the l2 cache controller. the status array tracks line locks as either instruction locks or data lock s for each line, and the status array supports flash clearing of al l instruction locks or data locks separa tely by writes to configuration registers in the l2 controller. 1.3.5 e500 coherency module (ecm) the e500 coherency module (ecm) provi des a mechanism for i/o-initiate d transactions to snoop the bus between the e500 core and the integrated l2 cache in order to maintain coherency across local cacheable memory. it also provides a fl exible switch-type structure for core and i/o-initiated transact ions to be routed or dispatched to target modules on the device. 1.3.6 ddr sdram controller the MPC8555E supports ddr-i sdra m that operates at up to 166 mhz (333-mhz data rate). the memory interface controls main memory accesses a nd provides for a maximum of 3.5 gbytes of main memory. the memory controller can be configured to support the various memory sizes through software initialization of on-chip configuration registers. the MPC8555E supports a variety of sdram configurations. sdram ba nks can be built using dimms or directly-attached memory devices . fifteen multiplexed address signals provide for device densities of 64 mbits, 128 mbits, 256 mbits, 512 mbit s, and 1 gbit. four chip select signals support up to four banks of memory. the MPC8555E supports ba nk sizes from 64 mbytes to 1 gbyt e. nine column address strobes (mdm[0:8]) are used to provide byt e selection for memory bank writes. the MPC8555E can be configured to retain the currently active sdram pa ge for pipelined burst accesses. page mode support of up to 16 simultaneously open pages can dramatically re duce access latencies for page hits. depending on the memory system design and timin g parameters, using page mode can save 3 to 4 clock cycles from subsequent burst accesses that hit in an active page. the MPC8555E supports error checking and correction (ecc) for system memory. using ecc, the MPC8555E detects and corrects all singl e-bit errors and detects all double-bi t errors and all errors within a nibble. the MPC8555E can invoke a level of system power management by as serting the mcke sdram signal on-the-fly to put the memory into a low-power sleep mode. 4 datasheet u .com
overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 1-17 1.3.7 programmable interrupt controller (pic) the programmable interrupt controller (pic) implements the necessa ry functions to provide a flexible solution for a general purpose interrupt control. the interrupt controller unit implements the logic and programming structures of the openpi c architecture. the MPC8555E inte rrupt controller unit supports its processor core and provides for 12 ex ternal interrupts (with fully nested interrupt delivery), 4 message interrupts, internal-logic driven interrupts, and 4 global high resolution timers. up to 16 programmable interrupt priority levels are supported. the interrupt controller unit can be bypassed to allow use of an external interrupt controller. inter-processor interrupt (ipi) co mmunication is supported through the ex ternal interrupt and core reset signals of different processor cores on the same device. the four ipis ar e only used for self-interrupt in a single-core device such as the MPC8555E. 1.3.8 i 2 c controllers there are two inter-ic (iic or i 2 c) controllers on the MPC8555E that are full/low speed compliant. one is contained within the cpm a nd multiplexed on an scc. the second one is a stand-alone i 2 c controller. both of the i 2 c controllers provide an i 2 c, two-wire, bi-directional seri al bus that provides a simple, efficient method of data exchange between de vices. the synchronous, multi -master bus of the i 2 c controllers allow the MPC8555E to exchange data with other i 2 c devices such as microcontrollers, eeproms, real-time clock de vices, a/d converters, and lcds. the two-wire bus (ser ial data sda and serial clock scl) minimi zes the interconnections am ong devices, and provides a pplication expansion and system development. the i 2 c controller is a true multiple -master bus which includes collisio n detection and arbitration that prevents data corruption if two or more masters attempt to control the bus simultaneously. this feature allows for complex applications with multiprocessor control. the i 2 c controller c onsists of a transmitter/receiver unit, a clocki ng unit, and a control unit. the i 2 c unit supports genera l broadcast mode, and has on-chip filtering that rejects spikes on the bus. 1.3.9 boot sequencer the MPC8555E provides a boot sequencer that uses the stand alone i 2 c controller interface to access an external serial rom and loads the da ta into the MPC8555E configuration registers. the boot sequencer is enabled by a configuration pin that is sampled at th e negation of the MPC8555E hardware reset signal. if enabled, the boot sequencer holds the MPC8555E processor core in reset until the boot sequence is complete. if the boot sequencer is not enabled, the processor core exits reset and fetches boot code in default configurations. 1.3.10 dual universal asynchronous receiver/transmitter (duart) the MPC8555E includes a duart intended for us e in maintenance, bringing-up, and debugging of systems. the MPC8555E provi des a standard four-wire handshake (txd, rxd, rts , cts ) for each port. the duart is a slave interface. an in terrupt is provided to the interrupt controller or optionally steered externally to allow device handshake s. interrupts are generated for tran smit, receive, line status, and modem status. 4 datasheet u .com
overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 1-18 freescale semiconductor the MPC8555E duart supports a full-duplex opera tion. it is compatible with the pc16450 and pc16550 programming models. also, 16- byte fifos are supported for both the transmitter and the receiver. software programmable baud generators divide the system clock to gene rate a 16x clock. serial interface data formats (data length, parity , 1/1.5/2 stop bit, baud rate) are also software selectable. 1.3.11 local bus controller (lbc) the MPC8555E local bus cont roller (lbc) allows connections with a wide vari ety of external memories, dsps, and asics. three separate st ate machines share the same exte rnal pins and can be programmed separately to access different type s of devices. the genera l purpose chip select machine (gpcm) controls accesses to asynchronous devices using a simple ha ndshake protocol. the us er programmable machine (upm) can be programmed to interface to synchronous devices or custom asic interfaces. the sdram controller provides access to standard sdram. each chip select can be configured so that the associated chip interface can be controlled by the gpcm, upm, or sdram controller. all may exist in the same system. the gpcm provides a flexible asynchronous interf ace to sram, eprom, feprom, rom, and other devices such as asynchronous dsp host interfaces and cams. minimal glue logi c is required. handshake signals can be configured to transition on fracti ons of the system clock. the gpcm does not support bursting. the upm allows an extremely flexible interface in which the programmer confi gures each of a set of general purpose protocol signals by writing the transi tion pattern into a memory array. the upm supports synchronous and bursting inte rfaces. it also supports multiplexed addressing so that a simple dram interface can be implemented. the upm is entirely fl exible in order to provide a very high degree of customization with respect to both asynchronous and burst-synchr onous interfaces, which permits glueless or almost glueless connection to burst sram, custom asic, and synchronous dsp interfaces. the lbc provides a synchronous dram (sdram) mach ine that provides the control functions and signals for glueless connection to jedec-complian t sdram devices. an internal dll (delay-locked loop) for bus clock generation ensures improved da ta setup margins for board designs. the sdram machine can optimize burst transfers and exploits interleaving to maxi mize data transfer bandwidth and minimize access latency. programma ble row and column address multiplexing allows a variety of sdram configurations and sizes to be supported without hardware changes. 1.3.12 three-speed ethernet controllers (10/100/1gb) the MPC8555E has two on-chip thre e-speed ethernet controllers (t secs). the tsecs incorporate a media access control sublayer (mac) that suppor ts 10- and 100-mbps, a nd 1gbps ethernet/802.3 networks with mii, gmii, rgmii, rtbi, and tb i physical interfaces. the tsecs include 2-kbyte receive and transmit fi fos, and dma functions. the buffer descriptors are based on the mp c8260 and mpc860t 10/ 100 programming models. 4 datasheet u .com
overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 1-19 the MPC8555E tsecs support programmable crc ge neration and checking, rmon statistics, and jumbo frames of up to 9.6 kbytes. frame headers and buf fer descriptors can be forced into the l2 cache to speed classification or other frame processing. 1.3.13 integrated dma the MPC8555E dma engine is capable of transferring blocks of data from any legal address range to any other legal address range. therefore, it can perform a dma transfer between any of its i/o or memory ports or even between two device s or locations on the same port. the four-channel dma controller allows chai ning (both extended and direct) through local memory-mapped chain descriptors. scattering, gathering, and misali gned transfers are supported. in addition, advanced capabilities such as stride transfers and comple x transaction chaining are supported. dma transfers can be initiated by a single write to a configuration register. there is also support for external control of tr ansfers using dma_dreq , dma_dack , and dma_ddone handshake signals. local attributes such as sno op and l2-write stashing can be specified by dma descriptors. interrupts are provided on a completed segment, link, list, chain, or on an error condition. coherency is selectable and hardware enforced (snoop/no snoop). 1.3.14 pci controller the MPC8555E 32-/64-bit pci contro ller is compatible with the pci local bus specification, revision 2.2 . the interface can function as a host or agen t bridge interface. the pci interface supports 64-bit addressing and 32- or 64-bit data buses, providi ng either two independent 32-bit interfaces or one 64-bit interface. as a master, the MPC8555E supports read and writ e operations to the pci memory space, the pci i/o space, and the pci configuration space. also, th e MPC8555E can generate pci special-cycle and interrupt-acknowledge commands. as a target, the MPC8555E supports read a nd write operations to system memory as well as configuration accesses. an internal arbiter can be used to support up to five extern al masters. a round robi n arbitration algorithm with two priority levels is used. 1.3.15 power management in addition to low-voltage operation and dynamic power management in its execution units, the MPC8555E supports four power cons umption modes: full-on, doze, na p, and sleep. the three low-power modes: doze, nap, and sleep, can be entered under software control in th e e500 core or by external masters accessing a configuration register. doze mode suspends execution of instructions in the e5 00 core. the core is left in a standby mode in which cache snooping and time base interrupts are still enabled. device logic external to the processor core is fully functional in this mode. 4 datasheet u .com
overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 1-20 freescale semiconductor nap mode shuts down clocks to all the e500 functional units except the time base, which can be disabled separately. no snooping is performed in nap mode, but the device logic ex ternal to the processor core is fully functional. sleep mode shuts down not only the e500 core, but also all of the MPC8555E i/o interfaces as well. only the interrupt controller and power management logic remain enabled so that the device can be awakened. 1.3.16 clocking the MPC8555E takes in the sy sclk signal as an input to the device pll, and multiplies it by an integer from 1 to 16 to generate the internal platform clock. this platform clock is the same frequency as the ddr dram data rate (266 or 333 mhz). the core complex bus (ccb) and l2 cache also run at this frequency. the e500 core uses the platform clock as an input to its pll, which multiplies it again by 2, 2.5, 3, or 3.5 to generate the core clock. six differential clock pairs are generated for ddr drams. dlls are used in the local bus memory controller (lbc) to generate two clock outputs. the pci interface can be clocked by sysclk or optionally by an i ndependent pci_clk. there is no frequency or phase relationship re quired between sysclk and pci_clk. 1.3.17 address map the MPC8555E supports a flexible phys ical address map. conceptually, the address map consists of local space and external address space. th e local address map is 4 gbytes. the MPC8555E can be made part of a larger system address space thr ough the mapping of translation windows. this functionality is included in the address translation an d mapping units (atmus). both inbound and outbound tran slation windows are provided. the atmus allows the MPC8555E to be pa rt of larger address maps such as the pci 64-bit address environment. 1.3.18 ocean switch fabric in order to reduce the strain on the core interconnects with the addition of new fu nctional blocks in this generation of the powerquicc fami ly, an on-chip non-blocking crossbar switch fabric called ocean (on-chip network) has been integr ated to decrease contention, decreas e latency, and increase bandwidth. this revolutionary non-blocking crossbar fabric al lows for full-duplex port connections at 128 gbps concurrent throughput, and i ndependent per-port transacti on queuing and flow control. 1.4 data processing overview protocol data units (pdus) can navigate through the various MPC8555E i/o ports in three ways. in the first, data is processed by the MPC8555E cpm (as it is received and transmitted through the utopias, miis, and tdms associat ed with the cpm) and the local bus. in the second method, data is received by any of the available i/o ports, is sent through the on-ch ip switch fabric, and is finally transmitted on the target i/o port without the use of the ecm. lastly, da ta can be routed from any i/o port to any other i/o port through the ecm. 4 datasheet u .com
overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 1-21 1.4.1 processing between the cpm and local bus in this case, the MPC8555E stores data in buffers that reside in sdram on the local bus. these buffers are each referenced by a buffer descriptor (bd), whic h may reside in one of tw o tables (rx-receive and tx-transmit) typically placed in dp ram. the following is a general overview of how incoming data is processed by the cpm (refer to figure 1-4 ). 1. when rx data arrives on the i/o port, it is decode d; the pdu is delineated from the incoming data stream. 2. next, data is converted from its serial form into a parallel form and then loaded into the rx fifo. 3. when the rx fifo is filled to a set threshol d, the respective communication channel signals the cpm for service. 4. the cpm accesses the next available rxbd in th e rxbd table (pointed to by a register in the channel?s parameter ram table). the bd defines the main memory location where the data is to be placed, as well as th e length of this buffer. data is then moved from the rx fifo to a temporary storage location by the cpm. 5. data is finally moved from this temporar y storage location to main memory through dma transactions. the status and control bits of the bd are updated, and the bd is closed. 6. a cpu interrupt is instantiated to notify th e core that a new packet has been received. because fifos are typically smaller than the incoming pdu, steps 1?3 may be repeated several times to store the entire packet. there may also be times when the incoming pd u is larger than the buffer length defined in the rxbd. in such cases, steps 4?5 may be repeated and seve ral bds may be opened and closed to store the entire pdu. when the transmit portion of the communication channel is enabled, the cpm starts with the first bd in the txbd table (pointed to by a register in the ch annel?s parameter ram table) , polling the ready r bit of the bd to verify that the bu ffer is ready for transmission. 7. when the bd is marked ready, the data is moved from the main memory buffer to a temporary storage location through dma transactions. 8. the cpm moves data from the tempor ary memory location to the tx fifo. 9. data is taken from the tx fifo in its parallel form and serialized. 10. when the tx fifo is emptied to a set thres hold, the communication chan nel signals the cpm for more data in order to maintain throughput. 11. the serialized data is lastly encoded and transmitted on the i/o port. again, because the buffer pointed to by the tx bd is typically larger than the tx fifo, the communication channel may make several iter ations of steps 7?10 to load and transmit the entire pdu. 4 datasheet u .com
overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 1-22 freescale semiconductor figure 1-4. data processing within the cpm 1.4.2 processing across the on-chip fabric when processing across the on-chip fabric, the atmus at each fabric port are us ed to determine the flow of data across the MPC8555E . the atmus at each fabric port are responsible for generating a fabric port destination id as well as a new local device addr ess. the port id and local address are based on the programmed destination of the tran saction. the following is a ge neral overview of how the atmus process transactions over th e on-chip fabric (refer to figure 1-5 ). 1. when a transaction on one of the fabric ports begins, the atmu on the or igination port translates the programmed destination addr ess into both a destination fabr ic port id and a local device address. 2. the data is then processed across the on-chip fa bric from the origination port to the destination port. 3. if the destination port connects off-chip (for exampl e, to a pci device), the local device address is translated by the destination port atmu to an outbound address with respect to the destination port?s memory map, and the data is processed accordingly. figure 1-5. processing transactions across the on-chip fabric cpm decoder shifter rx fifo te m p s t o r a g e buffer memory te m p s t o r a g e tx fifo shifter encoder 1 2 3 4 5 cpu 6 7 8 10 9 11 1 2 3 at m u at m u 4 datasheet u .com
overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 1-23 1.4.3 data processing with the e500 coherency module processing through the ecm is simila r to processing between the cpm and local bus or across the on-chip fabric (in the sense of how data is received and transmitted) with the exception that the transaction passes through the ecm. the purpose of the ecm is to provi de a means for any i/o tr ansaction to maintain coherency with the cacheable ddr sdram and the local bus memory (e xcept in the case where the cpm is directly accessing the local bus). however, simply because the ecm is used doe s not make transactions across it coherent. the e500 and l2 cache are snooped to maintain coherency only if the transaction across the ecm is designated as global (g bl bit set). otherwise, the trans action passes through the ecm using the ecm as a simple conduit to get to its destination. in essence, only global transactions across the ecm are coherent transactions; all others (between the cpm and the local bus, and across the on-chip fabric) are non-coherent. while transactions between the cpm and local bus are considered non-cohere nt because the cpm typically interfaces directly to the local bus (where its buffers are stored), cpm transactions can be made coherent. atm transactions on a per- connection and direction basis can be set as coherent by setting the necessary bits in the receive and transmit connection tabl es. coherency of mcc transactions per logical channel is determined by bits set in tstate. fc c and scc transactions per physical channel and direction can be progr ammed as coherent by asser ting the appropriate bits in the fcc and scc functional code registers, respectively. 1.5 compatibility issues this section describes some software and hardware compatibility issues. 1.5.1 software the MPC8555E cpm features are similar to those in the previous generation mpc8260. the code ports easily from previous devices to the MPC8555E, except for new protocols. during the defi nition of this device, an effort was made to main tain compatibility wherever possible. note that the MPC8555E initialization code requi res changes from the mpc8260 initialization code (freescale will provide the reference code). 1.5.2 MPC8555E hardware as the MPC8555E family migrates to smaller geometri es, the core voltage will re duce from 1.2 v to lower voltages. a programmable voltage re gulator is recommended for future compatibility. see the MPC8555E hardware specifications for th e electrical requirements and th e ac and dc characteristics. 4 datasheet u .com
overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 1-24 freescale semiconductor 1.5.3 communications protocol table table 1-1 summarizes available protocol s for each communications port. 1.5.4 MPC8555E configurations the MPC8555E offers flexibility in configuring th e device for specific appl ications. the functions mentioned in the above sections are all available in the device, but not all of them can be used at the same time. this does not imply that the device is not fully activated in any given implementation. the cpm architecture has the advantage of using common ha rdware resources for many different protocols and applications. two factor s limit the functionality in any gi ven system: pinout and performance. 1.5.5 pin configurations to maximize the efficiency of devi ce pins, some pins have multiple functions. in some cases choosing a function may preclude the use of another function. 1.5.6 communications performance the cpm is designed to handle an aggregate of 1 gbps on the communications channels running at 333 mhz. performance depends on a number of factors: ? channel rate versus cpm clock frequency for adequate polling of communications channels for service ? channel rate and protocol versus cpm cl ock frequency for cp protocol handling ? channel rate and protocol versus bus bandwidth ? channel rate and protocol versus system core clock for adequate protocol handling table 1-1. MPC8555E protocols protocol port tsec fcc scc smc atm (utopia) atm (serial) 1000baset 100baset ? 10baset ? hdlc ? hdlc_bus transparent ?? uart ? multichannel (qmc) usb 4 datasheet u .com
overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 1-25 the second item above is addr essed in this section?the cp?s ability to handle high bit-rate protocols. slow bit-rate protocols do not signi ficantly affect those numbers. table 1-2 shows the peak cpm performance of various protocols under the assumption that only one of those protocols is running at a give n time. the atm numbers shown also as sume that the local bus is used exclusively by the cpm and enough bandwidth on the ddr memory system is available for the cpm (implying that other resources like the pci contro llers, tsecs, dma controller, and cpu do not all operate at their maximum performance). the fre quency specified is the minimum cpm frequency necessary to run the mentioned prot ocols concurrently in full-duplex. these performance esti mates assume the cpm is ope rating at 333 mhz, and that data is stored in sdram on the local bus operating at 166 mhz. 1.6 reference manual revision history a list of the major differences between revisions of the MPC8555E powerquicc? iii integrated processor family reference manual is provided in appendix b, ?revision history.? table 1-2. peak cpm performance by protocol protocol frame size 1024 bytes 128 bytes 64 bytes ethernet fcc: 100base t 2 100base t full duplex = 400 mbps at m fcc: aal5 no bus limitation 1000 mbps aggregated 900 mbps aggregated connection tables on local bus fcc: aal0 no bus limitation 1000 mbps aggregated connection tables on local bus fcc: aal2 cps 33?242 mbps depending on pdu size 4 datasheet u .com
overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 1-26 freescale semiconductor 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 2-1 chapter 2 memory map this chapter describes the MPC8555E memory map. an overview of the local address map is followed by a description of how local access windows are used to define the local address map. the inbound and outbound address translation mechanisms used to map to and from external memo ry spaces are described next. finally, the configuration, contro l, and status registers are describe d, including a complete listing of all memory-mapped registers with cr oss references to the sections detailing descriptions of each. 2.1 local memory map overview and example the MPC8555E provides an extremely flexible local memory map. the local memory map refers to the 32-bit address space seen by the processor as it acces ses memory and i/o space. dma engines also see this same local memory map. all memory acce ssed by the MPC8555E ddr sdram and local bus memory controllers exists in this memory map, as do all memory-mapped configuration, control, and status registers. the local memory map is defined by a set of eight local access windows. each of these windows map a region of memory to a particular target interfac e, such as the ddr sdram controller or the pci controller. note that the local acc ess windows do not perform any addre ss translation. the size of each window can be configured from 4 kbytes to 2 gbytes. the target interface is specified using the codes shown in table 2-1 . . table 2-1. target interface codes target interface target code pci 1 0000 pci 2 0001 local bus 0100 ddr sdram 1111 4 datasheet u .com
memory map MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 2-2 freescale semiconductor figure 2-1 shows an example memory map. figure 2-1. local memory map example table 2-2 shows one corresponding set of local access window settings. in this example, it is not necessa ry to use a loca l access window to specify the location of the boot rom because it is in the default location at the highest 8 mbytes of memory (see section 4.4.3.3, ?boot rom location? ). neither is it required to define a local acces s window to describe the range of memory used for memory-mapped registers because this is a fi xed 1-mbyte space pointed to by ccsrbar. see section 4.3.1.1.2, ?configuration, cont rol, and status base address register (ccsrbar).? however, note that the e500 core only provides one default tlb entry to access boot code and it al lows for accesses table 2-2. local access windows example window base address size target interface 0 0x0000_0000 2 gbytes 0b1111 (ddr sdram) 1 0x8000_0000 1 mbyte 0b0100 (local bus) 2 0xa000_0000 256 mbytes 0b0000 (pci 1) 3 0xb000_0000 256 mbytes 0b0001 (pci 2) 4 0xc000_0000 256 mbytes 0b0100 (local bus) 5?7 unused example local 0 0xffff_ffff 0xa000_000 memory map memory i/o 0xa000_0000 0xb000_0000 pci 1 0xc000_0000 pci 2 ccsr boot rom 0x8000_000 local bus sram ddr sdram local bus flash configuration registers local bus dsp 4 datasheet u .com
memory map MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 2-3 within the highest 4 kbytes of memo ry. in order to access th e full 8 mbytes of de fault boot space (and the 1 mbyte of ccsr space), additional tlb entries must be set up within the e500 core for mapping these regions. 2.2 address translation and mapping four distinct types of tr anslation and mapping operations are perfo rmed on transactions in the MPC8555E. these are as follows: ? mapping a local address to a target interface ? assigning attributes to transactions ? translating local 32-bi t addresses to external address spaces ? translating external addresses to the local 32-bit address space the local access windows perform target mapping for transactions within the local address space. no address translation is perfor med by the local access windows. outbound atmu windows perform th e mapping from the local 32-bit address space to the external address spaces of the pci contro llers, which may be much larger than the local space. outbound atmu windows also map attributes such as transaction type or priority level. inbound atmu windows perform the addr ess translation from the extern al address space to the local address space, attach attributes and transaction types to the transaction, and also map the transaction to its target interface. note that in mapping the transac tion to the target interface, an inbound atmu window performs a similar function as the local access windows. the target mappings created by an inbound atmu must be consistent with t hose of the local access windows. th at is, if an inbound atmu maps a transaction to a given local address and a given target , a local access window must also map that same local address to the same target. all of the configuration registers that define tr anslation and mapping functi ons use the concept of translation or mapping windows, and al l follow the same register format. table 2-3 summarizes the general format of these window definitions. windows must be a power-of-two size. to perform a translation or mapping func tion, the address of the transaction is compared with the base address regist er of each window. the number of bits used in the comparison is dictated by each wi ndow?s size attribute. when an address hits a window, if address translation is being performed, the new translated a ddress is created by concatenating the window offset to the translation address. again, the windows size attribute dictat es how many bits are translated. table 2-3. format of atmu window definitions register function translation address high-order address bits defining lo cation of the window in the target address space base address high-order address bits defining location of the window in the initial address space window size/attributes window enable, window size, target interface, and transaction attributes 4 datasheet u .com
memory map MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 2-4 freescale semiconductor 2.2.1 sram windows the on-chip memory array of the MPC8555E can be configured as a memory -mapped sram of 128 or 256 kbytes. configuration registers in the l2 cache c ontroller set the base addresses and sizes for these windows. when enabled, these windows supersede all ot her mappings of these addr esses for processor and global (snoopable) i/o trans actions. therefore, sram windows must never overlap configuration space as defined by ccsrbar. it is possible to have sram windows overlap local acce ss windows, but this is discouraged because processor a nd snoopable i/o transactions would map to the sram while non-snooped i/o transactions would be mapped by the local access windows. only if all accesses to the sram address range are snoopable can results be consistent if the sram window overlaps a local access window. see section 7.3.1.4, ?l2 memory-mapped sram base address registers 0?1 (l2srbarn),? for information about configuring sram windows. 2.2.2 window into configuration space ccsrbar defines a window used to access all memo ry-mapped configuration, control, and status registers. no address translation is done, so there are no associated translati on address registers. the window is always enabled with a fixed size of 1 mbyt e; no other attributes are attached, so there is no associated size/attribute register. this window always takes precedence over all local access windows. see section 4.3.1.1.2, ?configuration, cont rol, and status base address register (ccsrbar),? and section 2.3, ?configuration, contro l, and status register map.? 2.2.3 local access windows as demonstrated in the address map overview in section 2.1, ?local memory map overview and example,? local access windows associate a ra nge of the local 32-bit address sp ace with a particular target interface. this allows the internal interconnections of the MPC8555E to route a transaction from its source to the proper target. no a ddress translation is perfor med. the base address defi nes the high order address bits that give the location of the window in the local address space. the window attributes enable the window, define its size, and specify the target interface. with the exception of configurat ion space (mapped by ccsrbar), on- chip sram regions (mapped by l2srbar registers), and default boot rom, all addresses used by the system must be mapped by a local access window. this includes addr esses that are mapped by inbound at mu windows; target mappings of inbound atmu windows and local access windows must be consistent. the local access window registers exist as part of the local access block in the ge neral utilities registers. see section 2.3.4, ?general ut ilities registers.? a detailed description of the local access window registers is given in the following sections. note that the minimum si ze of a window is 4 kbytes, so the low order 12 bits of the base address cannot be specified. 4 datasheet u .com
memory map MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 2-5 2.2.3.1 local access register memory map table 2-4 shows the memory map for the local access registers. 2.2.3.2 local access window n base address registers (lawbar0?lawbar7) figure 2-2 shows the bit fields of the lawbar n registers. figure 2-2. local access window n base address registers (lawbar0?lawbar7) table 2-4. local access register memory map local memory offset (hex) register access reset section/page 0x0_0c08 lawbar0?local access window 0 base address register r/w 0x0000_0000 2.2.3.2/2-5 0x0_0c10 lawsr0?local access window 0 attribute register r/w 0x0000_0000 2.2.3.3/2-6 0x0_0c28 lawbar1?local access window 1 base address register r/w 0x0000_0000 2.2.3.2/2-5 0x0_0c30 lawar1?local access window 1 attribute register r/w 0x0000_0000 2.2.3.3/2-6 0x0_0c48 lawbar2?local access window 2 base address register r/w 0x0000_0000 2.2.3.2/2-5 0x0_0c50 lawar2?local access window 2 attribute register r/w 0x0000_0000 2.2.3.3/2-6 0x0_0c68 lawbar3?local access window 3 base address register r/w 0x0000_0000 2.2.3.2/2-5 0x0_0c70 lawar3?local access window 3 attribute register r/w 0x0000_0000 2.2.3.3/2-6 0x0_0c88 lawbar4?local access window 4 base address register r/w 0x0000_0000 2.2.3.2/2-5 0x0_0c90 lawar4?local access window 4 attribute register r/w 0x0000_0000 2.2.3.3/2-6 0x0_0ca8 lawbar5?local access window 5 base address register r/w 0x0000_0000 2.2.3.2/2-5 0x0_0cb0 lawar5?local access window 5 attribute register r/w 0x0000_0000 2.2.3.3/2-6 0x0_0cc8 lawbar6?local access window 6 base address register r/w 0x0000_0000 2.2.3.2/2-5 0x0_0cd0 lawar6?local access window 6 attribute register r/w 0x0000_0000 2.2.3.3/2-6 0x0_0ce8 lawbar7?local access window 7 base address register r/w 0x0000_0000 2.2.3.2/2-5 0x0_0cf0 lawar7?local access window 7 attribute register r/w 0x0000_0000 2.2.3.3/2-6 01112 31 r000000000000 base_addr w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0xc08, 0xc28, 0xc48, 0xc68, 0xc88, 0xca8, 0xcc8, 0xce8 4 datasheet u .com
memory map MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 2-6 freescale semiconductor table 2-5 describes lawbar n bit settings. 2.2.3.3 local access window n attributes registers (lawar0?lawar7) figure 2-3 shows the bit fields of the lawar n registers. figure 2-3. local access window n attributes registers (lawar0?lawar7) table 2-6 describes lawar n bit settings. table 2-5. lawbar n bit settings bits name description 0?11 ? write reserved, read = 0 12?31 base_addr identifies the 20 most-s ignificant address bits of the base of local access window n . the specified base address should be aligned to the window size, as defined by lawar n [size]. 0 1 7 8 11 12 25 26 31 r e n 0000000 trgt_if 00000000000000 size w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0xc10, 0xc30, 0xc50, 0x c70, 0xc90, 0xcb0, 0xcd0, 0xcf0 table 2-6. lawar n bit settings bits name description 0 en 0 the local access window n (and all other lawar n and lawbar n fields) are disabled. 1 the local access window n is enabled and other lawar n and lawbar n fields combine to identify an address range for this window. 1?7 ? write reserved, read = 0 8?11 trgt_if identifies the target interface id when a transacti on hits in the address range defined by this window. note that configuration registers and sram regions are mapped by the windows defined by ccsrbar and l2srbar. these mappings supersede local access window mappings, so configuration registers and sram do not appear as a target for local access windows. 0000 pci 1 0001 pci 2 0010?0011 reserved 0100 local bus memory controller 0101?1110 reserved 1111 ddr sdram 12?25 ? write reserved, read = 0 26?31 size identifies the size of the window fr om the starting address. window size is 2 (size+1) bytes. 000000?001010 reserved 001011 4 kbytes 001100 8 kbytes 001101 16 kbytes .. . . . . . 2 (size+1) bytes 011110 2 gbytes 011111?111111 reserved 4 datasheet u .com
memory map MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 2-7 2.2.3.4 precedence of local access windows if two local access windows overlap, the lower numbere d window takes precedence. for instance, if two windows are setup as shown in table 2-7 , local access window 1 governs the mapping of the 1-mbyte region from 0x7ff0_0000 to 0x7fff_fff, even though the window described in local access window 2 also encompasses that memory region. 2.2.3.5 configuring local access windows once a local access window is enabled, it should not be modified while a ny device in the system may be using the window. neither s hould a new window be used until the ef fect of the write to the window is visible to all blocks that use the window. this can be guaranteed by completing a read of the last local access window configuration register before enabling any other device s to use the window. for instance, if local access windows 0?3 are being configured in orde r during the initialization process, the last write (to lawar3) should be followed by a read of lawa r3 before any devices try to use any of these windows. if the configuration is being done by the lo cal e500 processor, the read of lawar3 should be followed by an isync instruction. 2.2.3.6 distinguishing local access windows from other mapping functions it is important to distinguish between the mappi ng function performed by the local access windows and the additional mapping functions that happen at the target interface. the local access windows define how a transaction is routed through the MPC8555E internal interconnects from the tr ansactions source to its target. after the transaction has arrived at its target interface, that interface controller may perform additional mapping. for instance, the ddr sdram controller has chip sel ect registers that map a memory request to a particular external devi ce. similarly, the local bus controller has base registers that perform a similar function. the pcis have in terface has outbound address translat ion and mapping units that map the local address into an external address space. these other mapping functions are configured by programming the conf iguration, control, and status registers of the individual interfaces. note that th ere is no need to have a one-to-one correspondence between local access windows and chip select regions or outbound atmu windows. a single local access window can be further decoded to any number of chip selects or to any number of outbound atmu windows at the target interface. 2.2.3.7 illegal interaction between local access wind ows and ddr sdram chip selects if a local access window maps an a ddress to an interface ot her than the ddr sdram controller, then there should not be a valid chip select configured for the same address in the ddr sdram controller. because table 2-7. overlapping local access windows window base address size target interface 1 0x7ff0_0000 1 mbyte 0b0100 (local bus controller ?lbc) 2 0x0000_0000 2 gbytes 0b1111 (ddr sdram) 4 datasheet u .com
memory map MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 2-8 freescale semiconductor ddr sdram chip select boundaries are defined by a begi nning and ending address, it is easy to define them so that they do not overlap with loca l access windows that ma p to other interfaces. 2.2.4 outbound address translation and mapping windows outbound address translation and mappi ng refers to the translation of addresses from the local 32-bit address space to the external addr ess space and attributes of a particular i/o in terface. on the MPC8555E, both the pci blocks have outbound address translation and mapping units (atmus). the pci controllers have four outbound atmu windows plus a defa ult window. the pci outbound atmu registers include an extended translati on address register so that up to 64 bits of external address space can be supported. see section 16.3.1.2, ?pci atmu outbound registers,? for a detailed description of the pci outbound atmu windows. 2.2.5 inbound address transl ation and mapping windows inbound address translation and mapping refers to the tran slation of an address fr om the external address space of an i/o interface to the local address space understood by the internal interfaces of the MPC8555E. it also refers to the mapping of tran sactions to a particular target interface and the a ssignment of transaction attributes. both the pci controllers have inbou nd address translation an d mapping units (atmus). 2.2.5.1 pci inbound atmu the pci controller has three general inbound atmu windows plus a dedicated window for memory mapped configuration acces ses (pcsrbar). these windows have a one-to-one correspondence with the base address registers in the pci programming model. updating one automatically updates the other. there is no default inbound window; if a pci address doe s not match one of the inbound atmu windows, the MPC8555E does not respond with an assertion of pci n _devsel . see section 16.3.1.2, ?pci atmu outbound registers,? for a detailed description of the pci inbound atmu windows. 2.2.5.2 illegal interaction between inbound atmus and lo cal access windows since both local access window s and inbound atmus map transactions to a target interface, it is essential that they not contradict one another. for instance , it is a programming error to have an inbound atmu map a transaction to the ddr sdram memory contro ller (target interface 0b1111) if the resulting translated local address is mapped to pci1 (t arget interface 0b0000) by a local access window. such a programming error may result in unpredictable system deadlocks. 2.3 configuration, control, and status register map all of the memory mapped configuration, control, a nd status registers in the MPC8555E are contained within a 1-mbyte address region. to allow for flexibilit y, the configuration, control, and status block is relocatable in the local address space. the local addres s map location of this regi ster block is controlled by the configuration, control, and status registers base addr ess register (ccsrbar), see section 4.3.1.1.2, ?configuration, control, and status base address register (ccsrbar).? the default value for ccsrbar is 4 gbytes?9 mbytes, or 0xff70_0000. 4 datasheet u .com
memory map MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 2-9 note the configuration, control, and stat us window must not overlap a local access window that maps to the ddr controller. otherwise, undefined behavior occurs. an example of a top-level memory ma p with the default loca tion of the configurati on, control, and status registers is shown in figure 2-4 . figure 2-4. top-level register map example 2.3.1 accessing ccsr memory from the e500 core when the local e500 processor is used to configur e ccsr space, the ccsr memory space should typically be marked as cache- inhibited and guarded. in addition, many configurat ion registers affect accesses to other me mory regions; therefore, writes to these registers must be guara nteed to have taken effect before accesses are made to the associated memory regions. to guarantee that the results of any sequence of writes to configuration register s are in effect, the final configuration register write should be chased by a read of the same register, and that should be followed example local 0 4g ccsrbar (4g-9m) 4g-8m shaded area indicates locations not allowed for ccsrbar. reserved only if local boot rom memory map memory i/o 0x0 0000 device specific pic 0xe 0000 0xf ffff ccsr register memory block 0x4 0000 0x8 0000 general utilities utilities 0xc 0000 cpm reserved ccsr 4 datasheet u .com
memory map MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 2-10 freescale semiconductor by a sync instruction. then accesses can safely be made to memory regions aff ected by the configuration register write. 2.3.2 accessing ccsr memory from external masters in addition to being accessible by the e500 processor, the configuration, control, and status registers are accessible from external interfaces. this allows ex ternal masters on the i/o ports to configure the MPC8555E. external masters do not need to know the location of the ccsr memory in the local address map. rather, they access this region of the local memory map through a window defined by a regi ster in the interface?s programming model that is accessible to the exte rnal master from its external memory map. the pci base address for accessing the local ccsr me mory is selectable through the pci configuration and status register base address register (pcsrbar ), at offset 0x10, described in section 16.3.2.11, ?pci base address registers.? an external pci master sets this re gister by running a pci configuration cycle to the MPC8555E. subsequent memory accesses by a pci master to the pci address range indicated by pcsrbar are translated to the local address i ndicated by the current setting of ccsrbar. 2.3.3 organization of ccsr memory the configuration, control, and st atus registers of the MPC8555E are grouped according to functional units. most functional blocks are allocated a 4-kbyte a ddress space for registers. registers that fall into this category are referred to as general utilities re gisters. these registers o ccupy the first 256 kbytes of ccsr memory. registers that control functions that are not particular to a functiona l unit but to the device as a whole occupy the highest 256 kbytes of ccsr memory. thes e are referred to as device-specific registers. some functional units, such as a nd the openpic-based inte rrupt controller and the cpm have larger address spaces as defined by their programming models. the re gisters for these blocks are given their own large regions of ccsr memory. table 2-8. local memory configuration, control, and status register summary offset from ccsrbar register grouping 0x0_0000?0x3_ffff general utilities 0x4_0000?0x7_ffff programmable in terrupt controller (pic) 0x8_0000?0xb_ffff cpm 0xc_0000?0xd_ffff reserved 0xe_0000?0xf_ffff devic e-specific utilities 4 datasheet u .com
memory map MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 2-11 2.3.4 general utilities registers figure 2-5 provides an overview of the general utilities registers. figure 2-5. general utilities registers mapping to c onfiguration, control, and status memory block figure 2-5 also shows the organization of registers inside the 4-kbyte re gister space allocated to an individual functional block. the first 3 kbytes are available for general registers. the next 512 bytes are dedicated to address translation and mapping registers, if appl icable to that particul ar functional unit (for example, pci). if a unit has error management register s, they are typically placed starting at offset 0xe00 0x0 0000 0x0 1000 0x0 3000 general utilities registers memory block 0x0 4000 0x0 0000 device specific pic 0xe 0000 0xf ffff ccsr register memory block 0x4 0000 0x8 0000 general 0x0 2000 utilities 0x0 7000 0xn n000 0xn nfff general utility block 0xn nf00 debug 0xn ne00 error mgmt general registers utilities 0x3 ffff l2 cache 0xn nc00 at m u tsec 1 tsec 2 0x0 5000 0xc 0000 cpm 0x0 6000 ecm i2c memory local bus ocean local access 0x0 8000 0x2 0000 0x2 1000 0x2 4000 0x2 5000 0x2 6000 dma pci1 . . . duart 0x0 9000 pci2 0x3 0000 security 4 datasheet u .com
memory map MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 2-12 freescale semiconductor from the beginning of the bl ock?s 4-kbyte space, and any debug register s are typically pla ced in the final 256 bytes of the unit?s register space starting at offset 0xf00. general utilities registers ar e accessed as 32-bit quantities except for the duart and i 2 c registers, which are accessed as bytes. note refer to detailed register descripti ons for each functional unit for exact locations, sizes, and access requirements. some blocks may have exceptions to the above guidelines. 2.3.5 interrupt controller and ccsr the programmable interrupt contro ller (pic) registers are at offset 0x4_0000 from ccsrbar, see figure 2-6 . its programming model follows the openpic arch itecture. the interrupt controller registers should only be accessed with 32-bit accesses. figure 2-6. pic mapping to configuratio n, control, and status memory block 0x4 0000 processor global cfg timers external irqs 0x4 1100 0x5 1020 0x7 ffff pic registers 0x6 0000 0x5 0000 internal irqs 0x4 1000 0x4 1200 0x0 0000 device specific pic 0xe 0000 0xf ffff ccsr register memory block 0x4 0000 0x8 0000 general utilities utilities 0xc 0000 cpm 4 datasheet u .com
memory map MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 2-13 2.3.6 communications processor module and ccsr the communication processor module (c pm) uses 256 kbytes of configur ation memory. in addition to a 64-kbyte region for configuration re gisters, two separate 16-kbyte pa rameter ram regions are defined as well as a 32-kbyte instruction ram region. figure 2-7. cpm mapping to configuration, control, and status memory block 2.3.7 device-specific utilities the device-specific registers cons ist of power management, perfor mance monitors, and device-wide debug utilities (refer to figure 2-8 ). these registers are acc essible with 32-bit acces ses only. transactions of other than 32-bit are considered a programming error and operation is undefined. reserved bits in the following regi ster descriptions are not guaranteed to have pred ictable values. software must preserve the values of reserved bits when writ ing to a register. also, when reading from a register, software should not rely on the value of any reserved bit remaining consistent. 0x8 0000 0x8 8000 0xa 0000 0xa 8000 0x9 0000 0x8 4000 0x8 c000 0x0 0000 device specific pic 0xe 0000 0xf ffff ccsr register memory block 0x4 0000 0x8 0000 general utilities utilities 0xc 0000 cpm cpm configuration pram pram iram config regs 4 datasheet u .com
memory map MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 2-14 freescale semiconductor figure 2-8. device-specific register mapping to configuration, control, and status memory block 2.4 complete ccsr map table 2-9 lists the MPC8555E memory-mapped registers. table 2-9. memory map offset register acce ss reset section/page local-access registers?configuration, control, and status registers 0x0_0000 ccsrbar?configuration, control, and status registers base address register r/w 0x000f_f700 4.3.1.1.2/4-5 0x0_0008 altcbar?alternate configuration base address register r/w 0x0000_0000 4.3.1.2.1/4-6 0x0_0010 altcar?alternate configuration attribute register r/w 0x0000_0000 4.3.1.2.2/4-6 0x0_0020 bptr?boot page translation register r/w 0x0000_0000 4.3.1.3.1/4-7 local-access registers?local-access window base and size registers 0x0_0c08 lawbar0?local access window 0 base address register r/w 0x0000_0000 2.2.3.2/2-5 0x0_0c10 lawsr0?local access window 0 attribute register r/w 0x0000_0000 2.2.3.3/2-6 0x0_0c28 lawbar1?local access window 1 base address register r/w 0x0000_0000 2.2.3.2/2-5 0x0_0c30 lawar1?local access window 1 attribute register r/w 0x0000_0000 2.2.3.3/2-6 global utilities 0xe 1000 device specific 0xe 0000 0xe 2000 registers 0xf fffc perf. monitor device specific utilities 0xf ffff 0xe 0000 0xc 0000 0x8 0000 0x4 0000 0x0 0000 cpm pic general utilities watchpoint/debug 4 datasheet u .com
memory map MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 2-15 0x0_0c48 lawbar2?local access window 2 base address register r/w 0x0000_0000 2.2.3.2/2-5 0x0_0c50 lawar2?local access window 2 attribute register r/w 0x0000_0000 2.2.3.3/2-6 0x0_0c68 lawbar3?local access window 3 base address register r/w 0x0000_0000 2.2.3.2/2-5 0x0_0c70 lawar3?local access window 3 attribute register r/w 0x0000_0000 2.2.3.3/2-6 0x0_0c88 lawbar4?local access window 4 base address register r/w 0x0000_0000 2.2.3.2/2-5 0x0_0c90 lawar4?local access window 4 attribute register r/w 0x0000_0000 2.2.3.3/2-6 0x0_0ca8 lawbar5?local access window 5 base address register r/w 0x0000_0000 2.2.3.2/2-5 0x0_0cb0 lawar5?local access window 5 attribute register r/w 0x0000_0000 2.2.3.3/2-6 0x0_0cc8 lawbar6?local access window 6 base address register r/w 0x0000_0000 2.2.3.2/2-5 0x0_0cd0 lawar6?local access window 6 attribute register r/w 0x0000_0000 2.2.3.3/2-6 0x0_0ce8 lawbar7?local access window 7 base address register r/w 0x0000_0000 2.2.3.2/2-5 0x0_0cf0 lawar7?local access window 7 attribute register r/w 0x0000_0000 2.2.3.3/2-6 registers 0x0_1000 eebacr?ecm ccb address configuration register r/w 0x0000_0003 8.2.1.1/8-3 0x0_1010 eebpcr?ecm ccb port configuration register r/w 0x0*00_0000 8.2.1.2/8-4 0x0_1e00 eedr?ecm error detect register special 0x0000_0000 8.2.1.3/8-4 0x0_1e08 eeer?ecm error enable register r/w 0x0000_0000 8.2.1.4/8-5 0x0_1e0c eeatr?ecm error attributes capture register r 0x0000_0000 8.2.1.5/8-6 0x0_1e10 eeadr?ecm error address capture register r 0x0000_0000 8.2.1.6/8-7 ddr memory controller memory map 0x0_2000 cs0_bnds?chip select 0 memory bounds r/w 0x0000_0000 9.4.1.1/9-9 0x0_2008 cs1_bnds?chip select 1 memory bounds 0x0_2010 cs2_bnds?chip select 2 memory bounds 0x0_2018 cs3_bnds?chip select 3 memory bounds 0x0_2080 cs0_config?chip select 0 configuration r/w 0x0000_0000 9.4.1.2/9-10 0x0_2084 cs1_config?chip select 1 configuration 0x0_2088 cs2_config?chip select 2 configuration 0x0_208c cs3_config?chip select 3 configuration 0x0_2108 timing_cfg_1?ddr sdram timing configuration 1 r/w 0x0000_0000 9.4.1.3/9-11 0x0_210c timing_cfg_2?ddr sdram timing configuration 2 r/w 0x0000_0000 9.4.1.4/9-12 0x0_2110 ddr_sdram_cfg?ddr sdram cont rol configuration r/w 0x0200_0000 9.4.1.5/9-13 0x0_2118 ddr_sdram_mode?ddr sdram mode configuration r/w 0x0000_0000 9.4.1.6/9-14 table 2-9. memory map (continued) offset register acce ss reset section/page 4 datasheet u .com
memory map MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 2-16 freescale semiconductor 0x0_2124 ddr_sdram_interval?ddr sdram interval configuration r/w 0x0000_0000 9.4.1.7/9-15 0x0_2130 ddr_sdram_clk_cntl?ddr sdram clock control r/w 0x0000_0000 9.4.1.8/9-16 0x0_2e00 data_err_inject_hi?memo ry data path error injection mask high r/w 0x0000_0000 9.4.1.9/9-17 0x0_2e04 data_err_inject_lo?mem ory data path error injection mask low r/w 0x0000_0000 9.4.1.10/9-17 0x0_2e08 ecc_err_inject?memory data path error injection mask ecc r/w 0x0000_0000 9.4.1.11/9-18 0x0_2e20 capture_data_hi?memory data pat h read capture high r/w 0x0000_0000 9.4.1.12/9-19 0x0_2e24 capture_data_lo?memory data pat h read capture low r/w 0x0000_0000 9.4.1.13/9-19 0x0_2e28 capture_ecc?memory data pa th read capture ecc r/w 0x0000_0000 9.4.1.14/9-20 0x0_2e40 err_detect?memory error detect special 0x0000_0000 9.4.1.15/9-20 0x0_2e44 err_disable?memory error disable r/w 0x0000_0000 9.4.1.16/9-21 0x0_2e48 err_int_en?memory error interrupt enable r/w 0x0000_0000 9.4.1.17/9-22 0x0_2e4c capture_attributes?memory e rror attributes capture r/w 0x0000_0000 9.4.1.18/9-22 0x0_2e50 capture_address?memory error address capture r/w 0x0000_0000 9.4.1.19/9-23 0x0_2e58 err_sbe?single-bit ecc memory error management r/w 0x0000_0000 9.4.1.20/9-24 i 2 c 0x0_3000 i2cadr?i 2 c address register r/w 0x00 11.3.1.1/11-5 0x0_3004 i2cfdr?i 2 c frequency divider register r/w 0x00 11.3.1.2/11-6 0x0_3008 i2ccr?i 2 c control register r/w 0x00 11.3.1.3/11-7 0x0_300c i2csr?i 2 c status register r/w 0x81 11.3.1.4/11-9 0x0_3010 i2cdr?i 2 c data register r/w 0x00 11.3.1.5/11-10 0x0_3014 i2cdfsrr?i 2 c digital filter sampling rate register r/w 0x10 11.3.1.6/11-11 duart registers 0x0_4500 urbr?ulcr[dlab] = 0 uart0 receiver buffer register r 0x00 12.3.1.1/12-6 0x0_4500 uthr?ulcr[dlab] = 0 uart0 transmitter holding register w 0x00 12.3.1.2/12-6 0x0_4500 udlb?ulcr[dlab] = 1 uart0 divisor least significant byte register r/w 0x00 12.3.1.3/12-7 0x0_4501 uier?ulcr[dlab] = 0 uart0 interrupt enable register r/w 0x00 12.3.1.4/12-9 0x0_4501 udmb?ulcr[dlab] = 1 uart0 divisor most significant byte register r/w 0x00 12.3.1.3/12-7 0x0_4502 uiir?ulcr[dlab] = 0 uart0 interrupt id register r 0x01 12.3.1.5/12-9 0x0_4502 ufcr?ulcr[dlab] = 0 uart0 fifo control register w 0x00 12.3.1.6/12-11 table 2-9. memory map (continued) offset register acce ss reset section/page 4 datasheet u .com
memory map MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 2-17 0x0_4502 uafr?ulcr[dlab] = 1 uart0 alternate function register r/w 0x00 12.3.1.12/12-17 0x0_4503 ulcr?ulcr[dlab] = x uart0 line control register r/w 0x00 12.3.1.7/12-12 0x0_4504 umcr?ulcr[dlab] = x uart0 modem control register r/w 0x00 12.3.1.8/12-14 0x0_4505 ulsr?ulcr[dlab] = x uart 0 line status register r 0x60 12.3.1.9/12-14 0x0_4506 umsr?ulcr[dlab] = x uart0 modem status register r 0x00 12.3.1.10/12-16 0x0_4507 uscr?ulcr[dlab] = x uart0 scratch register r/w 0x00 12.3.1.11/12-17 0x0_4510 udsr?ulcr[dlab] = x uart0 dma status register r 0x01 12.3.1.13/12-18 0x0_4600 urbr?ulcr[dlab] = 0 uart1 receiver buffer register r 0x00 12.3.1.1/12-6 0x0_4600 uthr?ulcr[dlab] = 0 uart1 transmitter holding register w 0x00 12.3.1.2/12-6 0x0_4600 udlb?ulcr[dlab] = 1 uart1 divisor least significant byte register r/w 0x00 12.3.1.3/12-7 0x0_4601 uier?ulcr[dlab] = 0 uart1 interrupt enable register r/w 0x00 12.3.1.4/12-9 0x0_4601 udmb_ulcr[dlab] = 1 uart1 divisor most significant byte register r/w 0x00 12.3.1.3/12-7 0x0_4602 uiir?ulcr[dlab] = 0 uart1 interrupt id register r 0x01 12.3.1.5/12-9 0x0_4602 ufcr?ulcr[dlab] = 0 uart1 fifo control register w 0x00 12.3.1.6/12-11 0x0_4602 uafr?ulcr[dlab] = 1 uart1 alternate function register r/w 0x00 12.3.1.12/12-17 0x0_4603 ulcr?ulcr[dlab] = x uart1 line control register r/w 0x00 12.3.1.7/12-12 0x0_4604 umcr?ulcr[dlab] = x uart1 modem control register r/w 0x00 12.3.1.8/12-14 0x0_4605 ulsr?ulcr[dlab] = x uart 1 line status register r 0x60 12.3.1.9/12-14 0x0_4606 umsr?ulcr[dlab] = x uart1 modem status register r 0x00 12.3.1.10/12-16 0x0_4607 uscr?ulcr[dlab] = x uart1 scratch register r/w 0x00 12.3.1.11/12-17 0x0_4610 udsr?ulcr[dlab] = x uart1 dma status register r 0x01 12.3.1.13/12-18 local bus controller registers 0x0_5000 br0?base register 0 r/w 0x0000_rr01 1 13.3.1.1/13-10 0x0_5008 br1?base register 1 0x0000_0000 0x0_5010 br2?base register 2 0x0_5018 br3?base register 3 0x0_5020 br4?base register 4 0x0_5028 br5?base register 5 0x0_5030 br6?base register 6 0x0_5038 br7?base register 7 table 2-9. memory map (continued) offset register acce ss reset section/page 4 datasheet u .com
memory map MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 2-18 freescale semiconductor 0x0_5004 or0?options register 0 r/w 0x0000_0ff7 13.3.1.2/13-12 0x0_500c or1?options register 1 0x0000_0000 0x0_5014 or2?options register 2 0x0_501c or3?options register 3 0x0_5024 or4?options register 4 0x0_502c or5?options register 5 0x0_5034 or6?options register 6 0x0_503c or7?options register 7 0x0_5068 mar?upm address register r/w 0x0000_0000 13.3.1.3/13-17 0x0_5070 mamr?upma mode register r/w 0x0000_0000 13.3.1.4/13-18 0x0_5074 mbmr?upmb mode register r/w 0x0000_0000 13.3.1.4/13-18 0x0_5078 mcmr?upmc mode register r/w 0x0000_0000 13.3.1.4/13-18 0x0_5084 mrtpr?memory refresh timer prescaler register r/w 0x0000_0000 13.3.1.5/13-20 0x0_5088 mdr?upm data register r/w 0x0000_0000 13.3.1.6/13-21 0x0_5094 lsdmr?sdram mode register r/w 0x0000_0000 13.3.1.7/13-21 0x0_50a0 lurt?upm refresh timer r/w 0x0000_0000 13.3.1.8/13-23 0x0_50a4 lsrt?sdram refresh timer r/w 0x0000_0000 13.3.1.9/13-24 0x0_50b0 ltesr?transfer error status register read/ bit-reset 0x0000_0000 13.3.1.10/13-25 0x0_50b4 ltedr?transfer error disable register r/w 0x0000_0000 13.3.1.11/13-26 0x0_50b8 lteir?transfer error interrupt register r/w 0x0000_0000 13.3.1.12/13-27 0x0_50bc lteatr?transfer error attributes register r/w 0x0000_0000 13.3.1.13/13-28 0x0_50c0 ltear?transfer error address register r/w 0x0000_0000 13.3.1.14/13-29 0x0_50d0 lbcr?configuration register r/w 0x0000_0000 13.3.1.15/13-29 0x0_50d4 lcrr?clock ratio register r/w 0x8000_0008 13.3.1.16/13-31 pci registers pci1 configuration access registers 0x0_8000 cfg_addr?pci1 configur ation address r/w 0x0000_0000 16.3.1.1.1/16-17 0x0_8004 cfg_data?pci1 configuration data r/w 0x0000_0000 16.3.1.1.1/16-17 0x0_8008 int_ack?pci1 interrupt acknowledge r 0x0000_0000 16.3.1.1.3/16-19 0x0_800c? 0x0_8bfc reserved ? ? ? table 2-9. memory map (continued) offset register acce ss reset section/page 4 datasheet u .com
memory map MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 2-19 pci1 atmu registers?outbound and inbound 0x0_8c00?0x0_8c3c?outbound window 0 (default) 0x0_8c00 potar0?pci1 outbound window 0 (default) translation address register r/w 0x0000_0000 16.3.1.2.1/16-20 0x0_8c04 potear0?pci1 outbound window 0 (default) translation extended address register r/w 0x0000_0000 16.3.1.2.2/16-20 0x0_8c08 reserved ? ? 0x0_8c0c reserved ? ? 0x0_8c10 powar0?pci1 outbound window 0 (default) attributes register r/w 0x8004_401f 16.3.1.2.4/16-22 0x0_8c14? 0x0_8c1c reserved ? ? 0x0_8c20?0x0_8c3c?outbound window 1 0x0_8c20 potar1?pci1 outbound window 1 translation address register r/w 0x0000_0000 16.3.1.2.1/16-20 0x0_8c24 potear1?pci1 outbound window 1 translation extended address register r/w 0x0000_0000 16.3.1.2.2/16-20 0x0_8c28 powbar1?pci1 outbound window 1 base address register r/w 0x0000_0000 16.3.1.2.3/16-21 0x0_8c2c reserved ? ? 0x0_8c30 powar1?pci1 outbound window 1 attributes register r/w 0x0000_0000 16.3.1.2.4/16-22 0x0_8c34? 0x0_8c3c reserved ? ? 0x0_8c40?0x0_8c5c?outbound window 2 0x0_8c40 potar2?pci1 outbound window 2 translation address register r/w 0x0000_0000 16.3.1.2.1/16-20 0x0_8c44 potear2?pci1 outbound window 2 translation extended address register r/w 0x0000_0000 16.3.1.2.2/16-20 0x0_8c48 powbar2?pci1 outbound window 2 base address register r/w 0x0000_0000 16.3.1.2.3/16-21 0x0_8c4c reserved ? ? 0x0_8c50 powar2?pci1 outbound window 2 attributes register r/w 0x0000_0000 16.3.1.2.4/16-22 0x0_8c54? 0x0_8c5c reserved ? ? 0x0_8c60?0x0_8c7c?outbound window 3 0x0_8c60 potar3?pci1 outbound window 3 translation address register r/w 0x0000_0000 16.3.1.2.1/16-20 0x0_8c64 potear3?pci1 outbound window 3 translation extended address register r/w 0x0000_0000 16.3.1.2.2/16-20 table 2-9. memory map (continued) offset register acce ss reset section/page 4 datasheet u .com
memory map MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 2-20 freescale semiconductor 0x0_8c68 powbar3?pci1 outbound window 3 base address register r/w 0x0000_0000 16.3.1.2.3/16-21 0x0_8c6c reserved ? ? 0x0_8c70 powar3?pci1 outbound window 3 attributes register r/w 0x0000_0000 16.3.1.2.4/16-22 0x0_8c74? 0x0_8c7c reserved ? ? 0x0_8c80?0x0_8c9c?outbound window 4 0x0_8c80 potar4?pci1 outbound window 4 translation address register r/w 0x0000_0000 16.3.1.2.1/16-20 0x0_8c84 potear4?pci1 outbound window 4 translation extended address register r/w 0x0000_0000 16.3.1.2.2/16-20 0x0_8c88 powbar4?pci1 outbound window 4 base address register r/w 0x0000_0000 16.3.1.2.3/16-21 0x0_8c8c reserved ? ? 0x0_8c90 powar4?pci1 outbound window 4 attributes register r/w 0x0000_0000 16.3.1.2.4/16-22 0x0_8c94? 0x0_8d9c reserved ? ? 0x0_8da0?0x0_8dbc?inb ound window 3 0x0_8da0 pitar3?pci1 inbound window 3 translation address register r/w 0x0000_0000 16.3.1.3.1/16-24 0x0_8da4 reserved ? ? 0x0_8da8 piwbar3?pci1 inbound window 3 base address register r/w 0x0000_0000 16.3.1.3.2/16-25 0x0_8dac piwbear3?pci1 inbound window 3 base extended address register r/w 0x0000_0000 16.3.1.3.3/16-26 0x0_8db0 piwar3?pci1 inbound window 3 attributes register r/w 0x0000_0000 16.3.1.3.4/16-26 0x0_8db4? 0x0_8dbc reserved ? ? 0x0_8dc0?0x0_8ddc?inb ound window 2 0x0_8dc0 pitar2?pci1 inbound window 2 translation address register r/w 0x0000_0000 16.3.1.3.1/16-24 0x0_8dc4 reserved ? ? 0x0_8dc8 piwbar2?pci1 inbound window 2 base address register r/w 0x0000_0000 16.3.1.3.2/16-25 0x0_8dcc piwbear2?pci1 inbound window 2 base extended address register r/w 0x0000_0000 16.3.1.3.3/16-26 0x0_8dd0 piwar2?pci1 inbound window 2 attributes register r/w 0x0000_0000 16.3.1.3.4/16-26 0x0_8dd4? 0x0_8ddc reserved ? ? 0x0_8de0?0x0_8dfc?inbound window 1 0x0_8de0 pitar1?pci1 inbound window 1 translation address register r/w 0x0000_0000 16.3.1.3.1/16-24 0x0_8de4 reserved ? ? table 2-9. memory map (continued) offset register acce ss reset section/page 4 datasheet u .com
memory map MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 2-21 0x0_8de8 piwbar1?pci1 inbound window 1 base address register r/w 0x0000_0000 16.3.1.3.2/16-25 0x0_8dec reserved ? ? 0x0_8df0 piwar1?pci1 inbound window 1 attributes register r/w 0x0000_0000 16.3.1.3.4/16-26 0x0_8df4? 0x0_8dfc reserved ? ? pci1 error management registers 0x0_8e00 err_dr?pci1 error detect register special 0x0000_0000 16.3.1.4.1/16-29 0x0_8e04 err_cap_dr?pci1 error capture disabled register r/w 0x0000_0000 16.3.1.4.2/16-30 0x0_8e08 err_en?pci1 error enable register r/w 0x0000_0000 16.3.1.4.3/16-31 0x0_8e0c err_attrib?pci1 error attrib utes capture register r/w 0x0000_0000 16.3.1.4.4/16-32 0x0_8e10 err_addr?pci1 error address capture register r/w 0x0000_0000 16.3.1.4.5/16-33 0x0_8e14 err_ext_addr?pci1 error extended address capture register r/w 0x0000_0000 16.3.1.4.6/16-33 0x0_8e18 err_dl?pci1 error data lo w capture register r/w 0x0000_0000 16.3.1.4.7/16-33 0x0_8e1c err_dh?pci1 error data high capture register r/w 0x0000_0000 16.3.1.4.8/16-34 0x0_8e20 gas_timr?pci1 gasket timer register r/w 0x0000_0000 16.3.1.4.9/16-35 0x0_8e24? 0x0_8efc reserved ? ? 0x0_8f00? 0x0_8ffc reserved for debug ? ? 0x0_9000? 0x0_9ffc pci2 registers note: the pci2 interface has the same memory-mapped regi sters that are described for pci1 from 0x0_8000 to 0x0_8fff except the offsets are from 0x0_9000 to 0x0_9fff l2/sram memory-mapped configuration registers 0x2_0000 l2ctl?l2 control register r/w 0x2000_0000 7.3.1.1/7-7 0x2_0010 l2cewar0?l2 cache external write address register 0 r/w 0x0000_0000 7.3.1.2/7-10 0x2_0018 l2cewcr0?l2 cache external write control register 0 r/w 0x0000_0000 7.3.1.3/7-10 0x2_0020 l2cewar1?l2 cache external write address register 1 r/w 0x0000_0000 7.3.1.2/7-10 0x2_0028 l2cewcr1?l2 cache external write control register 1 r/w 0x0000_0000 7.3.1.3/7-10 0x2_0030 l2cewar2?l2 cache external write address register 2 r/w 0x0000_0000 7.3.1.2/7-10 0x2_0038 l2cewcr2?l2 cache external write control register 2 r/w 0x0000_0000 7.3.1.3/7-10 0x2_0040 l2cewar3?l2 cache external write address register 3 r/w 0x0000_0000 7.3.1.2/7-10 0x2_0048 l2cewcr3?l2 cache external write control register 3 r/w 0x0000_0000 7.3.1.3/7-10 0x2_0100 l2srbar0?l2 memory-mapped sram base address register 0 r/w 0x0000_0000 7.3.1.4/7-11 table 2-9. memory map (continued) offset register acce ss reset section/page 4 datasheet u .com
memory map MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 2-22 freescale semiconductor 0x2_0108 l2srbar1?l2 memory-mapped sram base address register 1 r/w 0x0000_0000 7.3.1.4/7-11 0x2_0e00 l2errinjhi?l2 error injection mask high register r/w 0x0000_0000 7.3.1.5.1/7-12 0x2_0e04 l2errinjlo?l2 error injection mask low register r/w 0x0000_0000 7.3.1.5.1/7-12 0x2_0e08 l2errinjctl?l2 error injection tag/ecc control register r/w 0x0000_0000 7.3.1.5.1/7-12 0x2_0e20 l2captdatahi?l2 error data high capture register r 0x0000_0000 7.3.1.5.2/7-14 0x2_0e24 l2captdatalo?l2 error data low capture register r 0x0000_0000 7.3.1.5.2/7-14 0x2_0e28 l2captecc?l2 error syndrome register r 0x0000_0000 7.3.1.5.2/7-14 0x2_0e40 l2errdet?l2 error detect register special 0x0000_0000 7.3.1.5.2/7-14 0x2_0e44 l2errdis?l2 error disable register r/w 0x0000_0000 7.3.1.5.2/7-14 0x2_0e48 l2errinten?l2 error interrupt enable register r/w 0x0000_0000 7.3.1.5.2/7-14 0x2_0e4c l2errattr?l2 error attributes capture register r/w 0x0000_0000 7.3.1.5.2/7-14 0x2_0e50 l2erraddr?l2 error addre ss capture register r 0x0000_0000 7.3.1.5.2/7-14 0x2_0e58 l2errctl?l2 error control register r/w 0x0000_0000 7.3.1.5.2/7-14 dma registers 0x2_1100 mr n ?dma 0 mode register r/w 0x0000_0000 15.3.2.1/15-9 0x2_1104 sr n ?dma 0 status register special 0x0000_0000 15.3.2.2/15-11 0x2_1108 reserved ? ? ? 0x2_110c clndar n ?dma 0 current link descriptor address register r/w 0x0000_0000 15.3.2.3/15-12 0x2_1110 satr n ?dma 0 source attributes register r/w 0x0000_0000 15.3.2.4/15-14 0x2_1114 sar n ?dma 0 source address register r/w 0x0000_0000 15.3.2.5/15-15 0x2_1118 datr n ?dma 0 destination attributes register r/w 0x0000_0000 15.3.2.6/15-16 0x2_111c dar n ?dma 0 destination address register r/w 0x0000_0000 15.3.2.7/15-16 0x2_1120 bcr n ?dma 0 byte count register r/w 0x0000_0000 15.3.2.8/15-17 0x2_1124 reserved ? ? ? 0x2_1128 nlndar n ?dma 0 next link descriptor address register r/w 0x0000_0000 15.3.2.9/15-17 0x2_1130 reserved ? ? ? 0x2_1134 clsdar n ?dma 0 current list alternate base descriptor address register r/w 0x0000_0000 15.3.2.10/15-18 0x2_1138 reserved ? ? ? 0x2_113c nlsdar n ?dma 0 next list descriptor address register r/w 0x0000_0000 15.3.2.11/15-19 0x2_1140 ssr n ?dma 0 source stride register r/w 0x0000_0000 15.3.2.12/15-19 0x2_1144 dsr n ?dma 0 destination stride register r/w 0x0000_0000 15.3.2.13/15-20 table 2-9. memory map (continued) offset register acce ss reset section/page 4 datasheet u .com
memory map MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 2-23 0x2_1180 mr n ?dma 1 mode register r/w 0x0000_0000 15.3.2.1/15-9 0x2_1184 sr n ?dma 1 status register special 0x0000_0000 15.3.2.2/15-11 0x2_1188 reserved ? ? ? 0x2_118c clndar n ?dma 1 current link descriptor address register r/w 0x0000_0000 15.3.2.3/15-12 0x2_1190 satr n ?dma 1 source attributes register r/w 0x0000_0000 15.3.2.4/15-14 0x2_1194 sar n ?dma 1 source address register r/w 0x0000_0000 15.3.2.5/15-15 0x2_1198 datr n ?dma 1 destination attributes register r/w 0x0000_0000 15.3.2.6/15-16 0x2_119c dar n ?dma 1 destination address register r/w 0x0000_0000 15.3.2.7/15-16 0x2_11a0 bcr n ?dma 1 byte count register r/w 0x0000_0000 15.3.2.8/15-17 0x2_11a4 reserved ? ? ? 0x2_11a8 nlndar n ?dma 1 next link descriptor address register r/w 0x0000_0000 15.3.2.9/15-17 0x2_11b0 reserved ? ? ? 0x2_11b4 clsdar n ?dma 1 current list alternate base descriptor address register r/w 0x0000_0000 15.3.2.10/15-18 0x2_11b8 reserved ? ? ? 0x2_11bc nlsdar n ?dma 1 next list descriptor address register r/w 0x0000_0000 15.3.2.11/15-19 0x2_11c0 ssr n ?dma 1 source stride register r/w 0x0000_0000 15.3.2.12/15-19 0x2_11c4 dsr n ?dma 1 destination stride register r/w 0x0000_0000 15.3.2.13/15-20 0x2_1200 mr n ?dma 2 mode register r/w 0x0000_0000 15.3.2.1/15-9 0x2_1204 sr n ?dma 2 status register special 0x0000_0000 15.3.2.2/15-11 0x2_1208 reserved ? ? ? 0x2_120c clndar n ?dma 2 current link descriptor address register r/w 0x0000_0000 15.3.2.3/15-12 0x2_1210 satr n ?dma 2 source attributes register r/w 0x0000_0000 15.3.2.4/15-14 0x2_1214 sar n ?dma 2 source address register r/w 0x0000_0000 15.3.2.5/15-15 0x2_1218 datr n ?dma 2 destination attributes register r/w 0x0000_0000 15.3.2.6/15-16 0x2_121c dar n ?dma 2 destination address register r/w 0x0000_0000 15.3.2.7/15-16 0x2_1220 bcr n ?dma 2 byte count register r/w 0x0000_0000 15.3.2.8/15-17 0x2_1224 reserved ? ? ? 0x2_1228 nlndar n ?dma 2 next link descriptor address register r/w 0x0000_0000 15.3.2.9/15-17 0x2_1230 reserved ? ? ? 0x2_1234 clsdar n ?dma 2 current list alternate base descriptor address register r/w 0x0000_0000 15.3.2.10/15-18 0x2_1238 reserved ? ? ? table 2-9. memory map (continued) offset register acce ss reset section/page 4 datasheet u .com
memory map MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 2-24 freescale semiconductor 0x2_123c nlsdar n ?dma 2 next list descriptor address register r/w 0x0000_0000 15.3.2.11/15-19 0x2_1240 ssr n ?dma 2 source stride register r/w 0x0000_0000 15.3.2.12/15-19 0x2_1244 dsr n ?dma 2 destination stride register r/w 0x0000_0000 15.3.2.13/15-20 0x2_1280 mr n ?dma 3 mode register r/w 0x0000_0000 15.3.2.1/15-9 0x2_1284 sr n ?dma 3 status register special 0x0000_0000 15.3.2.2/15-11 0x2_1288 reserved ? ? ? 0x2_128c clndar n ?dma 3 current link descriptor address register r/w 0x0000_0000 15.3.2.3/15-12 0x2_1290 satr n ?dma 3 source attributes register r/w 0x0000_0000 15.3.2.4/15-14 0x2_1294 sar n ?dma 3 source address register r/w 0x0000_0000 15.3.2.5/15-15 0x2_1298 datr n ?dma 3 destination attributes register r/w 0x0000_0000 15.3.2.6/15-16 0x2_129c dar n ?dma 3 destination address register r/w 0x0000_0000 15.3.2.7/15-16 0x2_12a0 bcr n ?dma 3 byte count register r/w 0x0000_0000 15.3.2.8/15-17 0x2_12a4 reserved ? ? ? 0x2_12a8 nlndar n ?dma 3 next link descriptor address register r/w 0x0000_0000 15.3.2.9/15-17 0x2_12b0 reserved ? ? ? 0x2_12b4 clsdar n ?dma 3 current list alternate base descriptor address register r/w 0x0000_0000 15.3.2.10/15-18 0x2_12b8 reserved ? ? ? 0x2_12bc nlsdar n ?dma 3 next list descriptor address register r/w 0x0000_0000 15.3.2.11/15-19 0x2_12c0 ssr n ?dma 3 source stride register r/w 0x0000_0000 15.3.2.12/15-19 0x2_12c4 dsr n ?dma 3 destination stride register r/w 0x0000_0000 15.3.2.13/15-20 0x2_1300 dgsr?dma general status register read 0x0000_0000 15.3.2.14/15-21 tsec1 general control and status registers 0x2_4000? 0x2_400c reserved r 0x0000_0000 ? 0x2_4010 ievent?interrupt event register r/w 0x0000_0000 14.5.3.1.1/14-19 0x2_4014 imask?interrupt mask register r/w 0x0000_0000 14.5.3.1.2/14-22 0x2_4018 edis?error disabled register r/w 0x0000_0000 14.5.3.1.3/14-24 0x2_401c reserved r 0x0000_0000 ? 0x2_4020 ecntrl?ethernet cont rol register r/w 0x0000_0000 14.5.3.1.4/14-25 0x2_4024 minflr?minimum frame length register r/w 0x0000_0040 14.5.3.1.5/14-26 0x2_4028 ptv?pause time value register r/w 0x0000_0000 14.5.3.1.6/14-26 0x2_402c dmactrl?dma control register r/w 0x0000_0000 14.5.3.1.7/14-27 table 2-9. memory map (continued) offset register acce ss reset section/page 4 datasheet u .com
memory map MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 2-25 0x2_4030 tbipa?tbi phy address register r/w 0x0000_0000 14.5.3.1.8/14-28 0x2_4034? 0x2_4088 reserved r 0x0000_0000 ? tsec1 fifo control and status registers 0x2_404c fifo_pause_ctrl?fifo paus e control register r/w 0x0000_0000 14.5.3.2.1/14-30 0x2_4050? 0x2_4088 reserved r 0x0000_0000 ? 0x2_408c fifo_tx_thr?fifo transmit threshold register r/w 0x0000_0100 14.5.3.2.2/14-30 0x2_4090? 0x2_4094 reserved r 0x0000_0000 ? 0x2_4098 fifo_tx_starve?fifo transmit starve register r/w 0x0000_0080 14.5.3.2.3/14-31 0x2_409c fifo_tx_starve_shut off?fifo transmit starve shutoff register r/w 0x0000_0100 14.5.3.2.4/14-31 0x2_40a0? 0x2_40fc reserved r 0x0000_0000 ? tsec1 transmit control and status registers 0x2_4100 tctrl?transmit control register r/w 0x0000_0000 14.5.3.3.1/14-32 0x2_4104 tstat?transmit status register r/w 0x0000_0000 14.5.3.3.2/14-33 0x2_4108 reserved r 0x0000_0000 ? 0x2_410c tbdlen?txbd data length register r 0x0000_0000 14.5.3.3.3/14-34 0x2_4110 txic?transmit interrupt coalescing configuration register r/w 0x0000_0000 14.5.3.3.4/14-34 0x2_4114? 0x2_4120 reserved r 0x0000_0000 ? 0x2_4124 ctbptr?current txbd pointer register r 0x0000_0000 14.5.3.3.5/14-35 0x2_4128? 0x2_4180 reserved r 0x0000_0000 ? 0x2_4184 tbptr?txbd pointer register r/w 0x0000_0000 14.5.3.3.6/14-35 0x2_4188? 0x2_4200 reserved r 0x0000_0000 ? 0x2_4204 tbase?txbd base address register r/w 0x0000_0000 14.5.3.3.7/14-36 0x2_4208? 0x2_42ac reserved r 0x0000_0000 ? 0x2_42b0 ostbd?out-of-sequence txbd register r/w 0x0800_0000 14.5.3.3.8/14-36 0x2_42b4 ostbdp?out-of-sequence tx data buffer pointer register r/w 0x0000_0000 14.5.3.3.9/14-38 0x2_42b8? 0x2_42fc reserved r 0x0000_0000 ? table 2-9. memory map (continued) offset register acce ss reset section/page 4 datasheet u .com
memory map MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 2-26 freescale semiconductor tsec1 receive control and status registers 0x2_4300 rctrl?receive control register r/w 0x0000_0000 14.5.3.4.1/14-39 0x2_4304 rstat?receive status register r/w 0x0000_0000 14.5.3.4.2/14-40 0x2_4308 reserved r 0x0000_0000 ? 0x2_430c rbdlen?rxbd data length register r 0x0000_0000 14.5.3.4.3/14-40 0x2_4310 rxic?receive interrupt coalescing configuration register r/w 0x0000_0000 14.5.3.4.4/14-41 0x2_4314? 0x2_4320 reserved r 0x0000_0000 ? 0x2_4324 crbptr?current rxbd pointer register r 0x0000_0000 14.5.3.4.5/14-42 0x2_4328? 0x2_433c reserved r 0x0000_0000 ? 0x2_4340 mrblr?maximum receive buffer length register r/w 0x0000_0000 14.5.3.4.6/14-42 0x2_4344? 0x2_4380 reserved r 0x0000_0000 ? 0x2_4384 rbptr?rxbd pointer register r/w 0x0000_0000 14.5.3.4.7/14-43 0x2_4388? 0x2_4400 reserved r 0x0000_0000 ? 0x2_4404 rbase?rxbd base address register r/w 0x0000_0000 14.5.3.4.8/14-44 0x2_4408? 0x2_44fc reserved r 0x0000_0000 ? tsec1 mac registers 0x2_4500 maccfg1?mac configurat ion register #1 r/w 0x0000_0000 14.5.3.6.1/14-47 0x2_4504 maccfg2?mac configurat ion register #2 r/w 0x0000_7000 14.5.3.6.2/14-48 0x2_4508 ipgifg?inter-packet gap/inte r-frame gap register r/w 0x4060_5060 14.5.3.6.3/14-49 0x2_450c hafdup?half-duplex register r/w 0x00a1_f037 14.5.3.6.4/14-50 0x2_4510 maxfrm?maximum frame length register r/w 0x0000_0600 14.5.3.6.5/14-51 0x2_4514? 0x2_451c reserved r 0x0000_0000 ? 0x2_4520 miimcfg?mii manag ement configuration register r/w 0x0000_0000 14.5.3.6.6/14-52 0x2_4524 miimcom?mii management command register r/w 0x0000_0000 14.5.3.6.7/14-53 0x2_4528 miimadd?mii management address register r/w 0x0000_0000 14.5.3.6.8/14-53 0x2_452c miimcon?mii management control register w 0x0000_0000 14.5.3.6.9/14-54 0x2_4530 miimstat?mii management status register r 0x0000_0000 14.5.3.6.10/14-55 0x2_4534 miimind?mii management indicator register r 0x0000_0000 14.5.3.6.11/14-55 0x2_4538 reserved r 0x0000_0000 ? table 2-9. memory map (continued) offset register acce ss reset section/page 4 datasheet u .com
memory map MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 2-27 0x2_453c ifstat?interface status register r 0x0000_0000 14.5.3.6.12/14-56 0x2_4540 macstnaddr1?station address register, part 1 r/w 0x0000_0000 14.5.3.6.13/14-56 0x2_4544 macstnaddr2?station address register, part 2 r/w 0x0000_0000 14.5.3.6.14/14-57 0x2_4548? 0x2_467c reserved r 0x0000_0000 ? tsec1 rmon mib registers tsec1 transmit and receive counters 0x2_4680 tr64?transmit and receive 64-byte frame counter register r/w 0x0000_0000 14.5.3.7.1/14-58 0x2_4684 tr127?transmit and receive 65- to 127-byte frame counter register r/w 0x0000_0000 14.5.3.7.2/14-58 0x2_4688 tr255?transmit and receive 128- to 255-byte frame counter register r/w 0x0000_0000 14.5.3.7.3/14-59 0x2_468c tr511?transmit and receive 256- to 511-byte frame counter register r/w 0x0000_0000 14.5.3.7.4/14-59 0x2_4690 tr1k?transmit and receive 512- to 1023-byte frame counter register r/w 0x0000_0000 14.5.3.7.5/14-60 0x2_4694 trmax?transmit and receive 1024- to 1518-byte frame counter register r/w 0x0000_0000 14.5.3.7.6/14-60 0x2_4698 trmgv?transmit and receive 1519- to 1522-byte good vlan frame count register r/w 0x0000_0000 14.5.3.7.7/14-61 tsec1 receive counters 0x2_469c rbyt?receive byte counter register r/w 0x0000_0000 14.5.3.7.8/14-61 0x2_46a0 rpkt?receive packet counter register r/w 0x0000_0000 14.5.3.7.9/14-62 0x2_46a4 rfcs?receive fcs error counter register r/w 0x0000_0000 14.5.3.7.10/14-62 0x2_46a8 rmca?receive multicast packet counter register r/w 0x0000_0000 14.5.3.7.11/14-63 0x2_46ac rbca?receive broadcast packet counter register r/w 0x0000_0000 14.5.3.7.12/14-63 0x2_46b0 rxcf?receive control frame packet counter register r/w 0x0000_0000 14.5.3.7.13/14-64 0x2_46b4 rxpf?receive pause frame packet counter register r/w 0x0000_0000 14.5.3.7.14/14-64 0x2_46b8 rxuo?receive unknown op code counter register r/w 0x0000_0000 14.5.3.7.15/14-65 0x2_46bc raln?receive alignment error counter register r/w 0x0000_0000 14.5.3.7.16/14-65 0x2_46c0 rflr?receive frame length error counter register r/w 0x0000_0000 14.5.3.7.17/14-66 0x2_46c4 rcde?receive code error counter register r/w 0x0000_0000 14.5.3.7.18/14-66 0x2_46c8 rcse?receive carrier sense error counter register r/w 0x0000_0000 14.5.3.7.19/14-67 0x2_46cc rund?receive undersize packet counter register r/w 0x0000_0000 14.5.3.7.20/14-67 0x2_46d0 rovr?receive oversize packet counter register r/w 0x0000_0000 14.5.3.7.21/14-68 table 2-9. memory map (continued) offset register acce ss reset section/page 4 datasheet u .com
memory map MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 2-28 freescale semiconductor 0x2_46d4 rfrg?receive fragments counter register r/w 0x0000_0000 14.5.3.7.22/14-68 0x2_46d8 rjbr?receive jabber counter register r/w 0x0000_0000 14.5.3.7.23/14-69 0x2_46dc rdrp?receive drop register r/w 0x0000_0000 14.5.3.7.24/14-69 tsec1 transmit counters 0x2_46e0 tbyt?transmit byte counter register r/w 0x0000_0000 14.5.3.7.25/14-70 0x2_46e4 tpkt?transmit packet counter register r/w 0x0000_0000 14.5.3.7.26/14-70 0x2_46e8 tmca?transmit multicast packet counter register r/w 0x0000_0000 14.5.3.7.27/14-71 0x2_46ec tbca?transmit broadcast pa cket counter register r/w 0x0000_0000 14.5.3.7.28/14-71 0x2_46f0 txpf?transmit pause control frame counter register r/w 0x0000_0000 14.5.3.7.29/14-72 0x2_46f4 tdfr?transmit deferral packet counter register r/w 0x0000_0000 14.5.3.7.30/14-72 0x2_46f8 tedf?transmit excessive deferral packet counter register r/w 0x0000_0000 14.5.3.7.31/14-73 0x2_46fc tscl?transmit single collision packet counter register r/w 0x0000_0000 14.5.3.7.32/14-73 0x2_4700 tmcl?transmit multiple collision packet counter register r/w 0x0000_0000 14.5.3.7.33/14-74 0x2_4704 tlcl?transmit late collision packet counter register r/w 0x0000_0000 14.5.3.7.34/14-74 0x2_4708 txcl?transmit excessive collision packet counter register r/w 0x0000_0000 14.5.3.7.35/14-75 0x2_470c tncl?transmit total collision counter register r/w 0x0000_0000 14.5.3.7.36/14-75 0x2_4710 reserved r 0x0000_0000 ? 0x2_4714 tdrp?transmit drop frame counter register r/w 0x0000_0000 14.5.3.7.37/14-76 0x2_4718 tjbr?transmit jabber fram e counter register r/w 0x0000_0000 14.5.3.7.38/14-76 0x2_471c tfcs?transmit fcs error counter register r/w 0x0000_0000 14.5.3.7.39/14-77 0x2_4720 txcf?transmit control fr ame counter register r/w 0x0000_0000 14.5.3.7.40/14-77 0x2_4724 tovr?transmit oversize frame counter register r/w 0x0000_0000 14.5.3.7.41/14-78 0x2_4728 tund?transmit undersize frame counter register r/w 0x0000_0000 14.5.3.7.42/14-78 0x2_472c tfrg?transmit fragments fr ame counter register r/w 0x0000_0000 14.5.3.7.43/14-79 tsec1 general registers 0x2_4730 car1?carry register one register r/w 0x0000_0000 14.5.3.7.44/14-79 0x2_4734 car2?carry register two register r/w 0x0000_0000 14.5.3.7.45/14-80 0x2_4738 cam1?carry register o ne mask register r/w 0xfe01_ffff 14.5.3.7.46/14-82 0x2_473c cam2?carry register two mask register r/w 0x000f_ffff 14.5.3.7.47/14-83 0x2_4740? 0x2_47fc reserved r 0x0000_0000 ? table 2-9. memory map (continued) offset register acce ss reset section/page 4 datasheet u .com
memory map MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 2-29 tsec1 hash function registers 0x2_4800 iaddr0?individual address register 0 r/w 0x0000_0000 14.5.3.8.1/14-84 0x2_4804 iaddr1?individual address register 1 r/w 0x0000_0000 0x2_4808 iaddr2?individual address register 2 r/w 0x0000_0000 0x2_480c iaddr3?individual address register 3 r/w 0x0000_0000 0x2_4810 iaddr4?individual address register 4 r/w 0x0000_0000 0x2_4814 iaddr5?individual address register 5 r/w 0x0000_0000 0x2_4818 iaddr6?individual address register 6 r/w 0x0000_0000 0x2_481c iaddr7?individual address register 7 r/w 0x0000_0000 0x2_4820? 0x2_487c reserved r 0x0000_0000 ? 0x2_4880 gaddr0?group address register 0 r/w 0x0000_0000 14.5.3.8.2/14-85 0x2_4884 gaddr1?group address register 1 r/w 0x0000_0000 0x2_4888 gaddr2?group address register 2 r/w 0x0000_0000 0x2_488c gaddr3?group address register 3 r/w 0x0000_0000 0x2_4890 gaddr4?group address register 4 r/w 0x0000_0000 0x2_4894 gaddr5?group address register 5 r/w 0x0000_0000 0x2_4898 gaddr6?group address register 6 r/w 0x0000_0000 0x2_489c gaddr7?group address register 7 r/w 0x0000_0000 0x2_48a0? 0x2_4bf4 reserved r 0x0000_0000 ? tsec1 attribute registers 0x2_4bf8 attr?attribute register r/w 0x0000_0000 14.5.3.9.1/14-85 0x2_4bfc attreli?attribute el & ei register r/w 0x0000_0000 14.5.3.9.2/14-87 tsec1 future ex pansion space 0x2_4c00? 0x2_4fff reserved r 0x0000_0000 ? tsec2 registers 0x2_5000? 0x2_5fff tsec2 registers note: tsec2 has the same memory-mapped registers that are described for tsec1 from 0x 2_4000 to 0x2_4fff except that the offsets are from 0x 2_5000 to 0x2_5fff. security engine register address map controller registers 0x3_1008 imr?interrupt mask register r/w 0x0000_0000 _0000_0000 17.6.2.1/17-93 table 2-9. memory map (continued) offset register acce ss reset section/page 4 datasheet u .com
memory map MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 2-30 freescale semiconductor 0x3_1010 isr?interrupt stat us register r 0x0000_0000 _0000_0000 17.6.2.2/17-94 0x3_1018 icr?interrupt clear register w 0x0000_0000 _0000_0000 17.6.2.3/17-95 0x3_1020 id?identification register r 0x0000_0000 _0000_0040 17.6.2.4/17-97 0x3_1028 euasr?eu assignment st atus register r 0xf0f0_f0f0 _00ff_f0f0 17.6.2/17-92 0x3_1030 mcr?master contro l register r/w 0x0000_0000 _0000_0000 17.6.2.5/17-98 channel 1 0x3_1108 cccr1?crypto-channel 1 configuration register r/w 0x0000_0000 _0000_0000 17.5.1.1/17-81 0x3_1110 ccpsr1?crypto-channel 1 pointer status register r 0x0000_0000 _0000_0007 17.5.1.2/17-83 0x3_1140 cdpr1?crypto-channel 1 current descriptor pointer register r 0x0000_0000 _0000_0000 17.5.1.3/17-89 0x3_1148 ff1?crypto-channel 1 fetch fifo address register w 0x0000_0000 _0000_0000 17.5.1.4/17-90 0x3_1180? 0x3_11bf dbn?crypto-channel 1descriptor buffers[0?7] r 0x0000_0000 _0000_0000 17.5.1.5/17-90 channel 2 0x3_1208 cccr2?crypto-channel 2 configuration register r/w 0x0000_0000 _0000_0000 17.5.1.1/17-81 0x3_1210 ccpsr2?crypto-channel 2 pointer status register r 0x0000_0000 _0000_0007 17.5.1.2/17-83 0x3_1240 cdpr2?crypto-channel 2 current descriptor pointer register r 0x0000_0000 _0000_0000 17.5.1.3/17-89 0x3_1248 ff2?crypto-channel 2 fetch fifo address register w 0x0000_0000 _0000_0000 17.5.1.4/17-90 0x3_1280? 0x3_12bf dbn?crypto-channel 2 descriptor buffers[0?7] r 0x0000_0000 _0000_0000 17.5.1.5/17-90 channel 3 0x3_1308 cccr3?crypto-channel 3 configuration register r/w 0x0000_0000 _0000_0000 17.5.1.1/17-81 0x3_1310 ccpsr3?crypto-channel 3 pointer status register r 0x0000_0000 _0000_0007 17.5.1.2/17-83 0x3_1340 cdpr3?crypto-channel 3 current descriptor pointer register r 0x0000_0000 _0000_0000 17.5.1.3/17-89 table 2-9. memory map (continued) offset register acce ss reset section/page 4 datasheet u .com
memory map MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 2-31 0x3_1348 ff3?crypto-channel 3 fetch fifo address register w 0x0000_0000 _0000_0000 17.5.1.4/17-90 0x3_1380? 0x3_13bf dbn?crypto-channel 3 descriptor buffers[0?7] r 0x0000_0000 _0000_0000 17.5.1.5/17-90 channel 4 0x3_1408 cccr4?crypto-channel 4 configuration register r/w 0x0000_0000 _0000_0000 17.5.1.1/17-81 0x3_1410 ccpsr4?crypto-channel 4 pointer status register r 0x0000_0000 _0000_0007 17.5.1.2/17-83 0x3_1440 cdpr4?crypto-channel 4 current descriptor pointer register r 0x0000_0000 _0000_0000 17.5.1.3/17-89 0x3_1448 ff4?crypto-channel 4 fetch fifo address register w 0x0000_0000 _0000_0000 17.5.1.4/17-90 0x3_1480? 0x3_14bf dbn?crypto-channel 4 descriptor buffers[0?7] r 0x0000_0000 _0000_0000 17.5.1.5/17-90 data encryption standard execution unit (deu) 0x3_2000 deumr?deu mode register r/w 0x0000_0000 _0000_0000 17.4.2.1/17-33 0x3_2008 deuksr?deu key size register r/w 0x0000_0000 _0000_0000 17.4.2.2/17-34 0x3_2010 deudsr?deu data size register r/w 0x0000_0000 _0000_0000 17.4.2.3/17-35 0x3_2018 deurcr?deu reset control register r/w 0x0000_0000 _0000_0000 17.4.2.4/17-36 0x3_2028 deusr?deu status register r 0x0000_0000 _0000_0000 17.4.2.5/17-37 0x3_2030 deuisr?deu interrupt status register r 0x0000_0000 _0000_0000 17.4.2.6/17-38 0x3_2038 deuicr?deu interrupt control register r/w 0x0000_0000 _0000_3000 17.4.2.7/17-39 0x3_2050 deueug?deu eu-go register w 0x0000_0000 _0000_0000 17.4.2.8/17-41 0x3_2100 deuiv?deu initialization vector register r/w 0x0000_0000 _0000_0000 17.4.2.9/17-41 0x3_2400 deuk1?deu key 1 register w ? 17.4.2.10/17-41 0x3_2408 deuk2?deu key 2 register w ? 17.4.2.10/17-41 0x3_2410 deuk3?deu key 3 register w ? 17.4.2.10/17-41 0x3_2800? 0x3_2fff deu fifo r/w 0x0000_0000 _0000_0000 17.4.2.11/17-42 table 2-9. memory map (continued) offset register acce ss reset section/page 4 datasheet u .com
memory map MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 2-32 freescale semiconductor advanced encryption standa rd execution unit (aesu) 0x3_4000 aesumr?aesu mode register r/w 0x0000_0000 _0000_0000 17.4.6.1/17-67 0x3_4008 aesuksr?aesu key size register r/w 0x0000_0000 _0000_0000 17.4.6.2/17-69 0x3_4010 aesudsr?aesu data size register r/w 0x0000_0000 _0000_0000 17.4.6.3/17-70 0x3_4018 aesurcr?aesu reset control register r/w 0x0000_0000 _0000_0000 17.4.6.4/17-70 0x3_4028 aesusr?aesu status register r 0x0000_0000 _0000_0000 17.4.6.5/17-71 0x3_4030 aesuisr?aesu interrupt status register r 0x0000_0000 _0000_0000 17.4.6.6/17-72 0x3_4038 aesuicr?aesu interrupt control register r/w 0x0000_0000 _0000_1000 17.4.6.7/17-73 0x3_4050 aesuemr?aesu end of message register w 0x0000_0000 _0000_0000 17.4.6.8/17-75 0x3_4100 aesu context memory registers r/w 0x0000_0000 _0000_0000 17.4.6.9/17-75 0x3_4400? 0x3_4408 aesu key memory r/w 0x0000_0000 _0000_0000 17.4.6.9.5/17-79 0x3_4800? 0x3_4fff aesu fifo r/w 0x0000_0000 _0000_0000 17.4.6.9.6/17-80 message digest execution unit (mdeu) 0x3_6000 mdeumr?mdeu mode register r/w 0x0000_0000 _0000_0000 17.4.4.1/17-51 0x3_6008 mdeuksr?mdeu key size register r/w 0x0000_0000 _0000_0000 17.4.4.3/17-53 0x3_6010 mdeudsr?mdeu data size register r/w 0x0000_0000 _0000_0000 17.4.4.4/17-54 0x3_6018 mdeurcr?mdeu reset control register r/w 0x0000_0000 _0000_0000 17.4.4.5/17-54 0x3_6028 mdeusr?mdeu status register r 0x0000_0000 _0000_0000 17.4.4.6/17-55 0x3_6030 mdeuisr?mdeu interrupt status register r 0x0000_0000 _0000_0000 17.4.4.7/17-56 0x3_6038 mdeuicr?mdeu interrupt control register r/w 0x0000_0000 _0000_1000 17.4.4.8/17-57 0x3_6050 mdeueug?mdeu eu-go register w 0x0000_0000 _0000_0000 17.4.4.9/17-58 table 2-9. memory map (continued) offset register acce ss reset section/page 4 datasheet u .com
memory map MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 2-33 0x3_6100? 0x3_6120 mdeu context memory registers r/w 0x0000_0000 _0000_0000 17.4.4.10/17-59 0x3_6400? 0x3_647f mdeu key memory w 0x0000_0000 _0000_0000 17.4.4.11/17-60 0x3_6800? 0x3_6fff mdeu fifo w 0x0000_0000 _0000_0000 17.4.4.12/17-60 arc four execution unit (afeu) 0x3_8000 afeumr?afeu mode register r/w 0x0000_0000 _0000_0000 17.4.3.1/17-42 0x3_8008 afeuksr?afeu key size register r/w 0x0000_0000 _0000_0000 17.4.3.3/17-43 0x3_8010 afeudsr?afeu data size register r/w 0x0000_0000 _0000_0000 17.4.3.4/17-44 0x3_8018 afeurcr?afeu reset control register r/w 0x0000_0000 _0000_0000 17.4.3.5/17-45 0x3_8028 afeusr?afeu status register r 0x0000_0000 _0000_0000 17.4.3.6/17-46 0x3_8030 afeuisr?afeu interrupt status register r 0x0000_0000 _0000_0000 17.4.3.7/17-47 0x3_8038 afeuicr?afeu interrupt control register r/w 0x0000_0000 _0000_1000 17.4.3.8/17-48 0x3_8050 afeuemr?afeu end of message register w 0x0000_0000 _0000_0000 17.4.3.9/17-50 0x3_8100? 0x3_81ff afeu context memory registers r/w 0x0000_0000 _0000_0000 17.4.3.10.1/17-50 0x3_8200 afeu context memory pointers r/w 0x0000_0000 _0000_0000 17.4.3.10.2/17-51 0x3_8400 afeuk0?afeu key register 0 w ? 17.4.3.11/17-51 0x3_8408 afeuk1?afeu key register 1 w ? 17.4.3.11/17-51 0x3_8800? 0x3_8fff afeu fifo r/w 0x0000_0000 _0000_0000 17.4.3.11.1/17-51 random number generator (rng) 0x3_a000 rngmr?rng mode register r/w 0x0000_0000 _0000_0000 17.4.5.1/17-61 0x3_a010 rngdsr?rng data size register r/w 0x0000_0000 _0000_0000 17.4.5.2/17-62 0x3_a018 rngrcr?rng reset control register r/w 0x0000_0000 _0000_0000 17.4.5.3/17-63 0x3_a028 rngsr?rng stat us register r 0x0000_0000 _0000_0000 17.4.5.4/17-63 table 2-9. memory map (continued) offset register acce ss reset section/page 4 datasheet u .com
memory map MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 2-34 freescale semiconductor 0x3_a030 rngisr?rng interrupt status register r 0x0000_0000 _0000_0000 17.4.5.5/17-64 0x3_a038 rngicr?rng interrupt control register r/w 0x0000_0000 _0000_1000 17.4.5.6/17-65 0x3_a050 rngeug?rng eu-go register w 0x0000_0000 _0000_0000 17.4.5.7/17-66 0x3_a800? 0x3_afff rng fifo r 0x0000_0000 _0000_0000 17.4.5.8/17-66 public key execution unit (pkeu) 0x3_c000 pkeumr?pkeu mode register r/w 0x0000_0000 _0000_0000 17.4.1.1/17-25 0x3_c008 pkeuksr?pkeu key size register r/w 0x0000_0000 _0000_0000 17.4.1.2/17-26 0x3_c010 pkeudsr?pkeu data size register r/w 0x0000_0000 _0000_0000 17.4.1.3/17-26 0x3_c018 pkeurcr?pkeu reset control register r/w 0x0000_0000 _0000_0000 17.4.1.5/17-28 0x3_c028 pkeusr?pkeu status register r 0x0000_0000 _0000_0000 17.4.1.6/17-29 0x3_c030 pkeuisr?pkeu interrupt status register r 0x0000_0000 _0000_0000 17.4.1.7/17-30 0x3_c038 pkeuicr?pkeu interrupt control register r/w 0x0000_0000 _0000_1000 17.4.1.8/17-31 0x3_c040 pkeuabs?pkeu ab size register r/w 0x0000_0000 _0000_0000 17.4.1.3/17-26 0x3_c050 pkeueug?pkeu eu-go w 0x0000_0000 _0000_0000 17.4.1.9/17-32 table 2-9. memory map (continued) offset register acce ss reset section/page 4 datasheet u .com
memory map MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 2-35 0x3_c200? 0x3_c23f pkeu parameter memory a0 r/w 0x0000_0000 _0000_0000 17.4.1.10/17-32 0x3_c240? 0x3_c27f pkeu parameter memory a1 r/w 0x0000_0000 _0000_0000 0x3_c280? 0x3_c2bf pkeu parameter memory a2 r/w 0x0000_0000 _0000_0000 0x3_c2c0? 0x3_c2ff pkeu parameter memory a3 r/w 0x0000_0000 _0000_0000 0x3_c300? 0x3_c33f pkeu parameter memory b0 r/w 0x0000_0000 _0000_0000 0x3_c340? 0x3_c37f pkeu parameter memory b1 r/w 0x0000_0000 _0000_0000 0x3_c380? 0x3_c3bf pkeu parameter memory b2 r/w 0x0000_0000 _0000_0000 0x3_c3c0? 0x3_c3ff pkeu parameter memory b3 r/w 0x0000_0000 _0000_0000 0x3_c400? 0x3_c4ff pkeu parameter memory e w 0x0000_0000 _0000_0000 0x3_c800? 0x3_c8ff pkeu parameter memory n r/w 0x0000_0000 _0000_0000 pic register address map?global registers 0x4_0000? 0x4_0030 reserved ? ? ? 0x4_0040 ipidr0?interprocessor interrupt 0 (ipi 0) dispatch register w 0x0000_0000 10.3.7.1/10-37 0x4_0050 ipidr1?ipi 1 dispatch register 0x4_0060 ipidr2?ipi 2 dispatch register 0x4_0070 ipidr3?ipi 3 dispatch register 0x4_0080 ctpr?current task priority register r/w 0x0000_000f 10.3.7.2/10-38 0x4_0090 whoami?who am i register r 0x0000_0000 10.3.7.3/10-39 0x4_00a0 iack?interrupt acknowledge register r 0x0000_0000 10.3.7.4/10-39 0x4_00b0 eoi?end of interrupt register w 0x0000_0000 10.3.7.5/10-40 0x4_00c0? 0x4_0ff0 reserved ? ? ? 0x4_1000 frr?feature report ing register r 0x0037_0002 10.3.1.1/10-15 0x4_1010 reserved ? ? ? 0x4_1020 gcr?global configuration register r/w 0x0000_0000 10.3.1.2/10-15 0x4_1030 reserved ? ? ? table 2-9. memory map (continued) offset register acce ss reset section/page 4 datasheet u .com
memory map MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 2-36 freescale semiconductor 0x4_1040? 0x4_1070 vendor reserved ? ? ? 0x4_1080 vir?vendor identificat ion register r 0x0000_0000 10.3.1.3/10-16 0x4_1090 pir?processor initialization register r/w 0x0000_0000 10.3.1.4/10-16 0x4_10a0 ipivpr0?ipi 0 vector/priority register r/w 0x8000_0000 10.3.1.5/10-17 0x4_10b0 ipivpr1?ipi 1 vector/priority register 0x4_10c0 ipivpr2?ipi 2 vector/priority register 0x4_10d0 ipivpr3?ipi 3 vector/priority register 0x4_10e0 svr?spurious vector register r/w 0x0000_ffff 10.3.1.6/10-18 0x4_10f0 tfrr?timer frequency reporting register r/w 0x0000_0000 10.3.2.1/10-19 0x4_1100 gtccr0?global timer 0 current count register r 0x0000_0000 10.3.2.2/10-19 0x4_1110 gtbcr0?global timer 0 base count register r/w 0x8000_0000 10.3.2.3/10-20 0x4_1120 gtvpr0?global timer 0 vector/priority register r/w 0x8000_0000 10.3.2.4/10-20 0x4_1130 gtdr0?global timer 0 destination register r/w 0x0000_0001 10.3.2.5/10-21 0x4_1140 gtccr1?global timer 1 current count register r 0x0000_0000 10.3.2.2/10-19 0x4_1150 gtbcr1?global timer 1 base count register r/w 0x8000_0000 10.3.2.3/10-20 0x4_1160 gtvpr1?global timer 1 vector/priority register r/w 0x8000_0000 10.3.2.4/10-20 0x4_1170 gtdr1?global timer 1 destination register r/w 0x0000_0001 10.3.2.5/10-21 0x4_1180 gtccr2?global timer 2 current count register r 0x0000_0000 10.3.2.2/10-19 0x4_1190 gtbcr2?global timer 2 base count register r/w 0x8000_0000 10.3.2.3/10-20 0x4_11a0 gtvpr2?global timer 2 vector/priority register r/w 0x8000_0000 10.3.2.4/10-20 0x4_11b0 gtdr2?global timer 2 destination register r/w 0x0000_0001 10.3.2.5/10-21 0x4_11c0 gtccr3?global timer 3 current count register r 0x0000_0000 10.3.2.2/10-19 0x4_11d0 gtbcr3?global timer 3 base count register r/w 0x8000_0000 10.3.2.3/10-20 0x4_11e0 gtvpr3?global timer 3 vector/priority register r/w 0x8000_0000 10.3.2.4/10-20 0x4_11f0 gtdr3?global timer 3 destination register r/w 0x0000_0001 10.3.2.5/10-21 0x4_1200? 0x4_12f0 reserved ? ? ? 0x4_1300 tcr?timer control register r/w 0x0000_0000 10.3.2.6/10-22 0x4_1310 irqsr0?irq_out summary register 0 r 0x0000_0000 10.3.3.1/10-24 0x4_1320 irqsr1?irq_out summary register 1 r 0x0000_0000 10.3.3.2/10-25 0x4_1330 cisr0?critical interrupt summary register 0 r 0x0000_0000 10.3.3.3/10-26 0x4_1340 cisr1?critical interrupt summary register 1 r 0x0000_0000 10.3.3.4/10-26 table 2-9. memory map (continued) offset register acce ss reset section/page 4 datasheet u .com
memory map MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 2-37 0x4_1350 pm0mr0?performance monitor 0 mask register 0 r/w 0x00ff_ffff 10.3.4.1/10-27 0x4_1360 pm0mr1?performance monitor 0 mask register 1 r/w 0xffff_ffff 10.3.4.2/10-28 0x4_1370 pm1mr0?performance monitor 1 mask register 0 r/w 0x00ff_ffff 10.3.4.1/10-27 0x4_1380 pm1mr1?performance monitor 1 mask register 1 r/w 0xffff_ffff 10.3.4.2/10-28 0x4_1390 pm2mr0?performance monitor 2 mask register 0 r/w 0x00ff_ffff 10.3.4.1/10-27 0x4_13a0 pm2mr1?performance monitor 2 mask register 1 r/w 0xffff_ffff 10.3.4.2/10-28 0x4_13b0 pm3mr0?performance monito r 3 mask register 0 r/w 0x00ff_ffff 10.3.4.1/10-27 0x4_13c0 pm3mr1?performance monitor 3 mask register 1 r/w 0xffff_ffff 10.3.4.2/10-28 0x4_13d0? 0x4_13f0 reserved ? ? ? 0x4_1400 msgr0?message register 0 r/w 0x0000_0000 10.3.5.1/10-28 0x4_1410 msgr1?message register 1 0x4_1420 msgr2?message register 2 0x4_1430 msgr3?message register 3 0x4_1440? 0x4_14f0 reserved ? ? ? 0x4_1500 mer?message enable register r/w 0x0000_0000 10.3.5.2/10-29 0x4_1510 msr?message status register r/w 0x0000_0000 10.3.5.3/10-29 0x4_1520? 0x4_fff0 reserved ? ? ? pic register address map?interrupt source configuration registers 0x5_0000 eivpr0?external interrupt 0 (irq0) vector/priority register r/w 0x8000_0000 10.3.6.1/10-30 0x5_0010 eidr0?external interrupt 0 (irq0) destination register r/w 0x0000_0001 10.3.6.2/10-31 0x5_0020 eivpr1?external interrupt 1 (irq1) vector/priority register r/w 0x8000_0000 10.3.6.1/10-30 0x5_0030 eidr1?external interrupt 1 (irq1) destination register r/w 0x0000_0001 10.3.6.2/10-31 0x5_0040 eivpr2?external interrupt 2 (irq2) vector/priority register r/w 0x8000_0000 10.3.6.1/10-30 0x5_0050 eidr2?external interrupt 2 (irq2) destination register r/w 0x0000_0001 10.3.6.2/10-31 0x5_0060 eivpr3?external interrupt 3 (irq3) vector/priority register r/w 0x8000_0000 10.3.6.1/10-30 0x5_0070 eidr3?external interrupt 3 (irq3) destination register r/w 0x0000_0001 10.3.6.2/10-31 0x5_0080 eivpr4?external interrupt 4 (irq4) vector/priority register r/w 0x8000_0000 10.3.6.1/10-30 0x5_0090 eidr4?external interrupt 4 (irq4) destination register r/w 0x0000_0001 10.3.6.2/10-31 0x5_00a0 eivpr5?external interrupt 5 (irq5) vector/priority register r/w 0x8000_0000 10.3.6.1/10-30 0x5_00b0 eidr5?external interrupt 5 (irq 5) destination register r/w 0x0000_0001 10.3.6.2/10-31 0x5_00c0 eivpr6?external interrupt 6 (irq6) vector/priority register r/w 0x8000_0000 10.3.6.1/10-30 table 2-9. memory map (continued) offset register acce ss reset section/page 4 datasheet u .com
memory map MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 2-38 freescale semiconductor 0x5_00d0 eidr6?external interrupt 6 (irq6) destination register r/w 0x0000_0001 10.3.6.2/10-31 0x5_00e0 eivpr7?external interrupt 7 (irq 7) vector/priority register r/w 0x8000_0000 10.3.6.1/10-30 0x5_00f0 eidr7?external interrupt 7 (irq 7) destination register r/w 0x0000_0001 10.3.6.2/10-31 0x5_0100 eivpr8?external interrupt 8 (irq8) vector/priority register r/w 0x8000_0000 10.3.6.1/10-30 0x5_0110 eidr8?external interrupt 8 (irq8) destination register r/w 0x0000_0001 10.3.6.2/10-31 0x5_0120 eivpr9?external interrupt 9 (irq9) vector/priority register r/w 0x8000_0000 10.3.6.1/10-30 0x5_0130 eidr9?external interrupt 9 (irq9) destination register r/w 0x0000_0001 10.3.6.2/10-31 0x5_0140 eivpr10?external interrup t 10 (irq10) vector/priority register r/w 0x8000_0000 10.3.6.1/10-30 0x5_0150 eidr10?external interrupt 10 (irq10) destination register r/w 0x0000_0001 10.3.6.2/10-31 0x5_0160 eivpr11?external interrup t 11 (irq11) vector/priority register r/w 0x8000_0000 10.3.6.1/10-30 0x5_0170 eidr11?external interrupt 11 (irq11) destination register r/w 0x0000_0001 10.3.6.2/10-31 0x5_0180? 0x5_01f0 reserved ? ? ? 0x5_0200 iivpr0?internal interrupt 0 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_0210 iidr0?internal interrupt 0 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_0220 iivpr1?internal interrupt 1 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_0230 iidr1?internal interrupt 1 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_0240 iivpr2?internal interrupt 2 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_0250 iidr2?internal interrupt 2 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_0260 iivpr3?internal interrupt 3 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_0270 iidr3?internal interrupt 3 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_0280 iivpr4?internal interrupt 4 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_0290 iidr4?internal interrupt 4 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_02a0 iivpr5?internal interrupt 5 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_02b0 iidr5?internal interrupt 5 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_02c0 iivpr6?internal interrupt 6 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_02d0 iidr6?internal interrupt 6 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_02e0 iivpr7?internal interrupt 7 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_02f0 iidr7?internal interrupt 7 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_0300 iivpr8?internal interrupt 8 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_0310 iidr8?internal interrupt 8 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_0320 iivpr9?internal interrupt 9 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 table 2-9. memory map (continued) offset register acce ss reset section/page 4 datasheet u .com
memory map MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 2-39 0x5_0330 iidr9?internal interrupt 9 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_0340 iivpr10?internal interrupt 10 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_0350 iidr10?internal interrupt 10 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_0360 iivpr11?internal interrupt 11 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_0370 iidr11?internal interrupt 11 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_0380 iivpr12?internal interrupt 12 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_0390 iidr12?internal interrupt 12 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_03a0 iivpr13?internal interrupt 13 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_03b0 iidr13?internal interrupt 13 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_03c0 iivpr14?internal interrupt 14 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_03d0 iidr14?internal interrupt 14 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_03e0 iivpr15?internal interrupt 15 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_03f0 iidr15?internal interrupt 15 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_0400 iivpr16?internal interrupt 16 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_0410 iidr16?internal interrupt 16 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_0420 iivpr17?internal interrupt 17 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_0430 iidr17?internal interrupt 17 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_0440 iivpr18?internal interrupt 18 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_0450 iidr18?internal interrupt 18 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_0460 iivpr19?internal interrupt 19 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_0470 iidr19?internal interrupt 19 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_0480 iivpr20?internal interrupt 20 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_0490 iidr20?internal interrupt 20 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_04a0 iivpr21?internal interrupt 21 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_04b0 iidr21?internal interrupt 21 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_04c0 iivpr22?internal interrupt 22 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_04d0 iidr22?internal interrupt 22 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_04e0 iivpr23?internal interrupt 23 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_04f0 iidr23?internal interrupt 23 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_0500 iivpr24?internal interrupt 24 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_0510 iidr24?internal interrupt 24 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_0520 iivpr25?internal interrupt 25 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_0530 iidr25?internal interrupt 25 destination register r/w 0x0000_0001 10.3.6.4/10-33 table 2-9. memory map (continued) offset register acce ss reset section/page 4 datasheet u .com
memory map MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 2-40 freescale semiconductor 0x5_0540 iivpr26?internal interrupt 26 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_0550 iidr126?internal interrupt 26 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_0560 iivpr27?internal interrupt 27 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_0570 iidr27?internal interrupt 27 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_0580 iivpr28?internal interrupt 28 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_0590 iidr28?internal interrupt 28 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_05a0 iivpr29?internal interrupt 29 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_05b0 iidr29?internal interrupt 29 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_05c0 iivpr30?internal interrupt 30 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_05d0 iidr30?internal interrupt 30 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_05e0 iivpr31?internal interrupt 31 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_05f0 iidr31?internal interrupt 31 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_0600? 0x5_15f0 reserved ? ? ? 0x5_1600 mivpr0?messaging interrupt 0 (msg 0) vector/priority register r/w 0x8000_0000 10.3.6.5/10-34 0x5_1610 midr0?messaging interrupt 0 (msg 0) destination register r/w 0x0000_0001 10.3.6.6/10-35 0x5_1620 mivpr1?messaging interrupt 1 (msg 1) vector/priority register r/w 0x8000_0000 10.3.6.5/10-34 0x5_1630 midr1?messaging interrupt 1 (msg 1) destination register r/w 0x0000_0001 10.3.6.6/10-35 0x5_1640 mivpr2?messaging interrupt 2 (msg 2) vector/priority register r/w 0x8000_0000 10.3.6.5/10-34 0x5_1650 midr2?messaging interrupt 2 (msg 2) destination register r/w 0x0000_0001 10.3.6.6/10-35 0x5_1660 mivpr3?messaging interrupt 3 (msg 3) vector/priority register r/w 0x8000_0000 10.3.6.5/10-34 0x5_1670 midr3?messaging interrupt 3 (msg 3) destination register r/w 0x0000_0001 10.3.6.6/10-35 0x5_1680? 0x5_fff0 reserved ? ? ? pic register address map?per-cpu registers 0x6_0000? 0x6_0030 reserved ? ? ? 0x6_0040 ipidr0?p0 ipi 0 dispatch register w all zeros 10.3.7.1/10-37 0x6_0050 ipidr1?p0 ipi 1 dispatch register 0x6_0060 ipidr2?p0 ipi 2 dispatch register 0x6_0070 ipidr3?p0 ipi 3 dispatch register table 2-9. memory map (continued) offset register acce ss reset section/page 4 datasheet u .com
memory map MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 2-41 0x6_0080 ctpr0?p0 current task pr iority register r/w 0x0000_000f 10.3.7.2/10-38 0x6_0090 whoami0?p0 who am i register r all zeros 10.3.7.3/10-39 0x6_00a0 iack0?p0 interrupt acknowledge register r all zeros 10.3.7.4/10-39 0x6_00b0 eoi0?p0 end of interrupt register w all zeros 10.3.7.5/10-40 cpm dual-port ram 0x8_0000? 0x8_1fff dpram1?dual-port ram r/w ? 21.4/21-28 0x8_2000? 0x8_7fff reserved ? ? ? 0x8_8000? 0x8_9fff dpram2?dual-port ram r/w ? 21.4/21-28 0x8_a000? 0x8_ffff reserved ? ? ? e500 core interface 0x9_0000 cear?cpm error address register r 0x0000_0000 21.2.3.1.1/21-18 0x9_0004 ceer?cpm error event register r/w 0x0000 21.2.3.1.2/21-19 0x9_0006 cemr?cpm error mask register r/w 0x0000 21.2.3.1.3/21-20 sdma 0x9_0050 smaer?system bus address error register r 0x0000_0000 27.1.1/27-2 0x9_0054 reserved ? ? ? 0x9_0058 smevr?system bus event register r/w 0x0000_0000 27.1.2/27-2 0x9_005c smctr?system bus c ontrol register r/w 0x3800_0000 27.1.3/27-3 0x9_0060 lmaer?local bus address error register r 0x0000_0000 27.1.1/27-2 0x9_0064 reserved ? ? ? 0x9_0068 lmevr?local bus event register r/w 0x0000_0000 27.1.2/27-2 0x9_006c lmctr?local bus control register r/w 0x3800_0000 27.1.3/27-3 interrupt controller 0x9_0c00 sicr?cpm interrupt config uration register r/w 0x0000_0000 22.5.1/22-9 0x9_0c02 reserved ? ? ? 0x9_0c04 sivec?cpm interrupt vector register r/w 0x0000_0000 22.5.1.5/22-14 0x9_0c08 sipnr_h?cpm interrupt pending register (high) r/w 0x0000_0000 22.5.1.3/22-11 0x9_0c0c sipnr_l?cpm interrupt pending register (low) r/w 0x0000_0000 22.5.1.3/22-11 0x9_0c10 reserved ? ? ? 0x9_0c14 scprr_h?cpm interrupt priority register (high) r/w 0x0530_9770 22.5.1.2/22-10 table 2-9. memory map (continued) offset register acce ss reset section/page 4 datasheet u .com
memory map MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 2-42 freescale semiconductor 0x9_0c18 scprr_l?cpm interrupt priority register (low) r/w 0x0530_9770 22.5.1.2/22-10 0x9_0c1c simr_h?cpm interrupt mask register (high) r/w 0x0000_0000 22.5.1.4/22-12 0x9_0c20 simr_l?cpm interrupt mask register (low) r/w 0x0000_0000 22.5.1.4/22-12 0x9_0c24 siexr?cpm external interrupt control register r/w 0x0000_0000 22.5.1.6/22-15 0x9_0c28? 0x9_0c7f reserved ? ? ? clock 0x9_0c80 sccr?system clock control register r/w 0x0000_0000 25.1/25-2 input/output port 0x9_0d00 pdira?port a data direction register r/w 0x0000_0000 45.2.2.2/45-5 0x9_0d04 ppara?port a pin assignment register r/w 0x0000_0000 45.2.4/45-10 0x9_0d08 psora?port a special options register r/w 0x0000_0000 45.2.5/45-13 0x9_0d0c podra?port a open drain register r/w 0x0000_0000 45.2.1/45-1 0x9_0d10 pdata?port a data register r/w 0x0000_0000 45.2.2/45-4 0x9_0d14? 0x9_0d1f reserved ? ? ? 0x9_0d20 pdirb?port b data direction register r/w 0x0000_0000 45.2.2.2/45-5 0x9_0d24 pparb?port b pin assignment register r/w 0x0000_0000 45.2.4/45-10 0x9_0d28 psorb?port b special options register r/w 0x0000_0000 45.2.5/45-13 0x9_0d2c podrb?port b open drain register r/w 0x0000_0000 45.2.1/45-1 0x9_0d30 pdatb?port b data register r/w 0x0000_0000 45.2.2/45-4 0x9_0d34? 0x9_0d3f reserved ? ? ? 0x9_0d40 pdirc?port c data direction register r/w 0x0000_0000 45.2.2.2/45-5 0x9_0d44 pparc?port c pin assignment register r/w 0x0000_0000 45.2.4/45-10 0x9_0d48 psorc?port c special options register r/w 0x0000_0000 45.2.5/45-13 0x9_0d4c podrc?port c open drain register r/w 0x0000_0000 45.2.1/45-1 0x9_0d50 pdatc?port c data register r/w 0x0000_0000 45.2.2/45-4 0x9_0d54? 0x9_0d5f reserved ? ? ? 0x9_0d60 pdird?port d data direction register r/w 0x0000_0000 45.2.2.2/45-5 0x9_0d64 ppard?port d pin assignment register r/w 0x0000_0000 45.2.4/45-10 0x9_0d68 psord?port d special options register r/w 0x0000_0000 45.2.5/45-13 0x9_0d6c podrd?port d open drain register r/w 0x0000_0000 45.2.1/45-1 table 2-9. memory map (continued) offset register acce ss reset section/page 4 datasheet u .com
memory map MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 2-43 0x9_0d70 pdatd?port d data register r/w 0x0000_0000 45.2.2/45-4 cpm timers 0x9_0d80 tgcr1?timer 1 and timer 2 global configuration register r/w 0x00 26.2.2/26-3 0x9_0d81 reserved ? ? ? 0x9_0d84 tgcr2?timer 3 and timer 4 global configuration register r/w 0x00 26.2.2/26-3 0x9_0d85? 0x9_0d8f reserved ? ? ? 0x9_0d90 tmr1?timer 1 mode register r/w 0x0000 26.2.3/26-5 0x9_0d92 tmr2?timer 2 mode register r/w 0x0000 26.2.3/26-5 0x9_0d94 trr1?timer 1 reference register r/w 0x0000 26.2.4/26-7 0x9_0d96 trr2?timer 2 reference register r/w 0x0000 26.2.4/26-7 0x9_0d98 tcr1?timer 1 capt ure register r/w 0x0000 26.2.5/26-7 0x9_0d9a tcr2?timer 2 ca pture register r/w 0x0000 26.2.5/26-7 0x9_0d9c tcn1?timer 1 counter r/w 0x0000 26.2.6/26-7 0x9_0d9e tcn2?timer 2 counter r/w 0x0000 26.2.6/26-7 0x9_0da0 tmr3?timer 3 mode register r/w 0x0000 26.2.3/26-5 0x9_0da2 tmr4?timer 4 mode register r/w 0x0000 26.2.3/26-5 0x9_0da4 trr3?timer 3 reference register r/w 0x0000 26.2.4/26-7 0x9_0da6 trr4?timer 4 reference register r/w 0x0000 26.2.4/26-7 0x9_0da8 tcr3?timer 3 ca pture register r/w 0x0000 26.2.5/26-7 0x9_0daa tcr4?timer 4 ca pture register r/w 0x0000 26.2.5/26-7 0x9_0dac tcn3?timer 3 counter r/w 0x0000 26.2.6/26-7 0x9_0dae tcn4?timer 4 counter r/w 0x0000 26.2.6/26-7 0x9_0db0 ter1?timer 1 event register r/w 0x0000 26.2.7/26-8 0x9_0db2 ter2?timer 2 event register r/w 0x0000 26.2.7/26-8 0x9_0db4 ter3?timer 3 event register r/w 0x0000 26.2.7/26-8 0x9_0db6 ter4?timer 4 event register r/w 0x0000 26.2.7/26-8 0x9_0db8? 0x9_12ff reserved ? ? ? fcc1 0x9_1300 gfmr1?fcc1 general mode register r/w 0x0000_0000 37.2/37-3 table 2-9. memory map (continued) offset register acce ss reset section/page 4 datasheet u .com
memory map MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 2-44 freescale semiconductor 0x9_1304 fpsmr1?fcc1 protocol-specific mode register r/w 0x0000_0000 (atm) 41.13.3/41-84 (ethernet) 40.18.2/40-20 (hdlc) 38.6/38-8 0x9_1308 ftodr1?fcc1 transmit on demand register r/w 0x0000 37.6/37-8 0x9_130a reserved ? ? ? 0x9_130c fdsr1?fcc1 data synchronization register r/w 0x7e7e 37.5/37-7 0x9_130e reserved ? ? ? 0x9_1310 fcce1?fcc1 event re gister r/w 0x0000_0000 (atm) 41.13.4/41-86 (ethernet) 40.18.3/40-22 (hdlc) 38.9/38-14 0x9_1312 reserved ? ? ? 0x9_1314 fccm1?fcc1 mask register r/w 0x0000_0000 (atm) 41.13.4/41-86 (ethernet) 40.18.3/40-22 (hdlc) 38.9/38-14 0x9_1316 reserved ? ? ? 0x9_1318 fccs1?fcc1 status register r 0x00 38.10/38-16 (hdlc) 0x9_1319 reserved ? ? ? 0x9_131c ftirr1_phy0?fcc1 transmit internal rate registers for phy0 r/w 0x00 41.13.5/41-87 (atm) 0x9_131d ftirr1_phy1?fcc1 transmit internal rate registers for phy1 r/w 0x00 41.13.5/41-87 (atm) 0x9_131e ftirr1_phy2?fcc1 transmit internal rate registers for phy2 r/w 0x00 41.13.5/41-87 (atm) 0x9_131f ftirr1_phy3?fcc1 transmit internal rate registers for phy3 r/w 0x00 41.13.5/41-87 (atm) fcc2 0x9_1320 gfmr2?fcc2 general mode register r/w 0x0000_0000 37.2/37-3 0x9_1324 fpsmr2?fcc2 protocol-specific mode register r/w 0x0000_0000 (atm) 41.13.3/41-84 (ethernet) 40.18.2/40-20 (hdlc) 38.6/38-8 table 2-9. memory map (continued) offset register acce ss reset section/page 4 datasheet u .com
memory map MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 2-45 0x9_1328 ftodr2?fcc2 transmit on-demand register r/w 0x0000 37.6/37-8 0x9_132a reserved ? ? ? 0x9_132c fdsr2?fcc2 data synchronization register r/w 0x7e7e 37.5/37-7 0x9_132e reserved ? ? ? 0x9_1330 fcce2?fcc2 event re gister r/w 0x0000_0000 (atm) 41.13.4/41-86 (ethernet) 40.18.3/40-22 (hdlc) 38.9/38-14 0x9_1332 reserved ? ? ? 0x9_1334 fccm2?fcc2 mask register r/w 0x0000_0000 (atm) 41.13.4/41-86 (ethernet) 40.18.3/40-22 (hdlc) 38.9/38-14 0x9_1336 reserved ? ? ? 0x9_1338 fccs2?fcc2 status register r 0x00 38.10/38-16 (hdlc) 0x9_1339? 0x9_137f reserved ? 0x00 ? 0x9_133c ftirr2_phy0?fcc2 transmit internal rate registers for phy0 r/w 0x00 41.13.5/41-87 (atm) 0x9_133d ftirr2_phy1?fcc2 transmit internal rate registers for phy1 r/w 0x00 41.13.5/41-87 (atm) 0x9_133e ftirr2_phy2?fcc2 transmit internal rate registers for phy2 r/w 0x00 41.13.5/41-87 (atm) 0x9_133f ftirr2_phy3?fcc2 transmit internal rate registers for phy3 r/w 0x00 41.13.5/41-87 (atm) 0x9_1340? 0x9_137f reserved ? ? ? fcc1 (continued) 0x9_1380 firper1?fcc1 internal rate port enable register r/w 0x0000_0000 41.15.3/41-90 0x9_1384 firer1?fcc1 internal rate event register r/w 0x0000_0000 41.15.4/41-91 0x9_1388 firsr1_hi?fcc1 internal rate selection register: hi r/w 0x0000_0000 41.15.5/41-92 0x9_138c firsr1_lo? fcc1 internal rate selection register: lo r/w 0x0000_0000 41.15.5/41-92 0x9_1390 gfemr1?general fcc1 expansion mode register r/w 0x00 37.3/37-7 0x9_1391? 0x9_139f reserved ? ? ? table 2-9. memory map (continued) offset register acce ss reset section/page 4 datasheet u .com
memory map MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 2-46 freescale semiconductor fcc2 (continued) 0x9_13a0 firper2?fcc2 internal rate port enable register r/w 0x0000_0000 41.15.3/41-90 0x9_13a4 firer2?fcc2 internal ra te event register r/w 0x0000_0000 41.15.4/41-91 0x9_13a8 firsr2_hi?fcc2 internal rate selection register: hi r/w 0x0000_0000 41.15.5/41-92 0x9_13ac firsr2_lo?fcc2 internal rate selection register: lo r/w 0x0000_0000 41.15.5/41-92 0x9_13b0 gfemr2?general fcc2 expansion mode register r/w 0x00 37.3/37-7 0x9_13b1? 0x9_15ef reserved ? ? ? brgs 5?8 0x9_15f0 brgc5?brg5 configurat ion register r/w 0x0000_0000 25.2/25-3 0x9_15f4 brgc6?brg6 configurat ion register r/w 0x0000_0000 25.2/25-3 0x9_15f8 brgc7?brg7 configurat ion register r/w 0x0000_0000 25.2/25-3 0x9_15fc brgc8?brg8 configuration register r/w 0x0000_0000 25.2/25-3 0x9_1600? 0x9_185f reserved ? ? ? i 2 c 0x9_1860 i2mod?i 2 c mode register r/w 0x00 44.4.1/44-6 0x9_1861 reserved ? ? ? 0x9_1864 i2add?i 2 c address register r/w 0x00 44.4.2/44-7 0x9_1865 reserved ? ? ? 0x9_1868 ii2brg?i 2 c brg register r/w 0x00 44.4.3/44-7 0x9_1869 reserved ? ? ? 0x9_186c i2com?i 2 c command register r/w 0x00 44.4.5/44-8 0x9_186d reserved ? ? ? 0x9_1870 i2cer?i 2 c event register r/w 0x00 44.4.4/44-7 0x9_1871 reserved ? ? ? 0x9_1874 i2cmr?i 2 c mask register r/w 0x00 44.4.4/44-7 0x9_1875? 0x9_19bf reserved ? ? ? communications processor 0x9_19c0 cpcr?communications processor command register r/w 0x0000_0000 21.3.1/21-24 0x9_19c4 rccr?cp configuration register r/w 0x0000_0000 21.2.6/21-22 0x9_19c8? 0x9_19d5 reserved ? ? ? table 2-9. memory map (continued) offset register acce ss reset section/page 4 datasheet u .com
memory map MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 2-47 0x9_19d6 rter?cp timers event register r/w 0x0000 21.5.4/21-35 0x9_19da rtmr?cp timers mask register r/w 0x0000 21.5.4/21-35 0x9_19dc rtscr?cp time-stamp timer control register r/w 0x0000 21.2.7/21-23 0x9_19de reserved ? ? ? 0x9_19e0 rtsr?cp time-stamp register r/w 0x0000_0000 21.2.8/21-24 brgs 1?4 0x9_19f0 brgc1?brg1 configurat ion register r/w 0x0000_0000 25.2/25-3 0x9_19f4 brgc2?brg2 configurat ion register r/w 0x0000_0000 25.2/25-3 0x9_19f8 brgc3?brg3 configurat ion register r/w 0x0000_0000 25.2/25-3 0x9_19fc brgc4?brg4 configuration register r/w 0x0000_0000 25.2/25-3 scc1 0x9_1a00 gsmr_l1?scc1 general mode register r/w 0x0000_0000 28.2/28-3 0x9_1a04 gsmr_h1?scc1 general mode register r/w 0x0000_0000 28.2/28-3 0x9_1a08 psmr1?scc1 protocol-spec ific mode register r/w 0x0000 28.2/28-3 29.16/29-12 (uart) 30.8/30-7 (hdlc) 31.11/31-9 (bisync) 32.9/32-8 (transparent) 0x9_1a0a reserved ? ? ? 0x9_1a0c todr1?scc1 transmit-on-demand register r/w 0x0000 28.2.3/28-9 0x9_1a0e dsr1?scc1 data synchronization register r/w 0x7e7e 28.2.2/28-8 0x9_1a10 scce1?scc1 event register r/w 29.19/29-18 (uart) 30.11/30-12 (hdlc) 31.14/31-14 (bisync) 32.12/32-11 (transparent) 0x9_1a14 sccm1?scc1 mask register r/w 0x0000 0x9_1a16 reserved ? ? ? 0x9_1a17 sccs1?scc1 stat us register r/w 0x00 29.20/29-20 (uart) 30.12/30-13 (hdlc) 31.15/31-15 (bisync) 32.13/32-12 (transparent) 0x9_1a18? 0x9_1a3f reserved ? ? ? table 2-9. memory map (continued) offset register acce ss reset section/page 4 datasheet u .com
memory map MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 2-48 freescale semiconductor scc3 0x9_1a40 gsmr_l3?scc3 general mode register r/w 0x0000_0000 28.2/28-3 0x9_1a44 gsmr_h3?scc3 general mode register r/w 0x0000_0000 0x9_1a48 psmr3?scc3 protocol-spec ific mode register r/w 0x0000 28.2.1/28-8 29.16/29-12 (uart) 30.8/30-7 (hdlc) 31.11/31-9 (bisync) 32.9/32-8 (transparent) 0x9_1a4a reserved ? ? ? 0x9_1a4c todr3?scc3 transmit on demand register r/w 0x0000 28.2.2/28-8 0x9_1a4e dsr3?scc3 data synchronization register r/w 0x7e7e 28.2.2/28-8 0x9_1a50 scce3?scc3 event register r/w 29.19/29-18 (uart) 30.11/30-12 (hdlc) 31.14/31-14 (bisync) 32.12/32-11 (transparent) 0x9_1a54 sccm3?scc3 mask register r/w 0x0000 0x9_1a56 reserved ? ? ? 0x9_1a57 sccs3?scc3 stat us register r/w 0x00 29.20/29-20 (uart) 30.12/30-13 (hdlc) 31.15/31-15 (bisync) 32.13/32-12 (transparent) 0x9_1a58? 0x9_1a5f reserved ? ? ? scc4 0x9_1a60 gsmr_l4?scc4 general mode register r/w 0x0000_0000 28.2/28-3 0x9_1a64 gsmr_h4?scc4 general mode register r/w 0x0000_0000 28.2/28-3 0x9_1a68 psmr4?scc4 protocol-spec ific mode register r/w 0x0000 28.2.1/28-8 29.16/29-12 (uart) 30.8/30-7 (hdlc) 31.11/31-9 (bisync) 32.9/32-8 (transparent) 0x9_1a6a reserved ? ? ? 0x9_1a6c todr4?scc4 transmit on-demand register r/w 0x0000 28.2.3/28-9 0x9_1a6e dsr4?scc4 data synchronization register r/w 0x7e7e 28.2.2/28-8 table 2-9. memory map (continued) offset register acce ss reset section/page 4 datasheet u .com
memory map MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 2-49 0x9_1a70 scce4?scc4 event register r/w 29.19/29-18 (uart) 30.11/30-12 (hdlc) 31.14/31-14 (bisync) 32.12/32-11 (transparent) 0x9_1a74 sccm4?scc4 mask register r/w 0x0000 0x9_1a76 reserved ? ? ? 0x9_1a77 sccs4?scc4 st atus register ? ? 29.20/29-20 (uart) 30.12/30-13 (hdlc) 31.15/31-15 (bisync) 32.13/32-12 (transparent) 0x9_1a78? 0x9_1a7f reserved ? ? ? smc1 0x9_1a82 smcmr1?smc1 mode register r/w 0x0000 36.2.1/36-2 0x9_1a84 reserved ? 16 bits ? 0x9_1a86 smce1?smc1 event register r/w 0x00 36.3.11/36-18 0x9_1a87 reserved ? 24 bits ? 0x9_1a8a smcm1?smc1 mask register r/w 0x00 36.3.11/36-18 0x9_1a8b? 0x9_1a91 reserved ? 7 bytes ? smc2 0x9_1a92 smcmr2?smc2 mode register r/w 0x0000 36.2.1/36-2 0x9_1a94 reserved ? 16 bits ? 0x9_1a96 smce2?smc2 event register r/w 0x00 36.3.11/36-18 0x9_1a97 reserved ? 24 bits ? 0x9_1a9a smcm2?smc2 mask register r/w 0x00 36.3.11/36-18 0x9_1a9b? 0x9_1a9f reserved ? 5 bytes ? spi 0x9_1aa0 spmode?spi mode register r/w 0x0000 43.4.1/43-6 0x9_1aa2 reserved ? ? ? 0x9_1aa6 spie?spi even t register r/w 0x00 43.4.2/43-9 0x9_1aa7 reserved ? ? ? 0x9_1aaa spim?spi mask register r/w 0x00 43.4.2/43-9 0x9_1aab reserved ? ? ? table 2-9. memory map (continued) offset register acce ss reset section/page 4 datasheet u .com
memory map MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 2-50 freescale semiconductor 0x9_1aad spcom?spi command register w 0x00 43.4.3/43-10 0x9_1aa7? 0x9_1b00 reserved ? ? ? cpm mux 0x9_1b02 cmxsi2cr?cpm mux si2 cl ock route register r/w 0x00 24.4.2/24-8 0x9_1b03 reserved ? ? ? 0x9_1b04 cmxfcr?cpm mux fcc cloc k route register r/w 0x0000_0000 24.4.3/24-8 0x9_1b08 cmxscr?cpm mux scc clock route register r/w 0x0000_0000 24.4.4/24-10 0x9_1b0c cmxsmr?cpm mux smc clock route register r/w 0x00 24.4.5/24-13 0x9_1b0e cmxuar?cpm mux utopia address register r/w 0x0000 24.4.1/24-5 0x9_1b10? 0x9_1b3f reserved ? ? ? si1 registers si2 registers 0x9_1b40 si2amr?si2 tdma2 mode register r/w 0x0000 23.6.2/23-14 0x9_1b42 si2bmr?si2 tdmb2 mode register r/w 0x0000 23.6.2/23-14 0x9_1b44 si2cmr?si2 tdmc2 mode register r/w 0x0000 23.6.2/23-14 0x9_1b46 reserved r/w 16 bits 23.6.2/23-14 0x9_1b48 si2gmr?si2 global mode register r/w 0x00 23.6.1/23-14 0x9_1b49 reserved ? ? ? 0x9_1b4a si2cmdr?si2 comm and register r/w 0x00 23.6.4/23-20 0x9_1b4b reserved ? ? ? 0x9_1b4c si2str?si2 status register r/w 0x00 23.6.5/23-21 0x9_1b4d reserved ? ? ? 0x9_1b4e si2rsr?si2 ram shadow address register r/w 0x0000 23.6.3/23-20 0x9_1b50? 0x9_1b5f reserved ? ? ? usb 0x9_1b60 usmod?usb mode register r/w 0x00 35.5.7.1/35-17 0x9_1b61 usadr?usb address register r/w 0x00 35.5.7.2/35-18 0x9_1b62 uscom?usb command register r/w 0x00 35.5.7.4/35-19 0x9_1b64 usep1?usb end point 1 register r/w 0x0000 35.5.7.3/35-18 0x9_1b66 usep2?usb end point 2 register r/w 0x0000 35.5.7.3/35-18 0x9_1b68 usep3?usb end point 3 register r/w 0x0000 35.5.7.3/35-18 table 2-9. memory map (continued) offset register acce ss reset section/page 4 datasheet u .com
memory map MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 2-51 0x9_1b6a usep4?usb end point 4 register r/w 0x0000 35.5.7.3/35-18 0x9_1b6c? 0x9_1b6f reserved ? 32 bits ? 0x9_1b70 usber?usb event register r/w 0x0000 35.5.7.5/35-20 0x9_1b72 reserved ? 16 bits ? 0x9_1b74 usbmr?usb mask register r/w 0x0000 35.5.7.6/35-21 0x9_1b77 usbs?usb status register r/w 0x00 35.5.7.7/35-21 0x9_1b79? 0x9_1fff reserved ? 1174 bytes ? si2 ram 0x9_2800? 0x9_29ff si2txram?si 2 transmit routing ram ? ? 23.5.3/23-9 0x9_2a00? 0x9_2bff reserved ? ? ? 0x9_2c00? 0x9_2dff si2rxram?si 2 receive routing ram ? ? 23.5.3/23-9 0x9_2e00? 0x9_3fff reserved ? ? ? instruction ram 0xa_0000? 0xa_0fff dual-port ram (instruction ram only) ? ? 21.4/21-28 global utilities registers power-on reset configuration values 0xe_0000 porpllsr?por pll ratio status register r 0x00 nn _ n 1 nn 18.4.1.1/18-4 0xe_0004 porbmsr?por boot mode status register r 0x nnnn _0000 18.4.1.2/18-5 0xe_0008 porimpscr?por i/o im pedance status and control register r/w 0x000 n _007f 18.4.1.3/18-6 0xe_000c pordevsr?por i/o device status register r see ref. 18.4.1.4/18-7 0xe_0010 pordbgmsr?por debug mode status register r see ref. 18.4.1.5/18-8 0xe_0020 gpporcr?general-purpose por configuration register r see ref. 18.4.1.6/18-9 signal multiplexing and gpio controls 0xe_0030 gpiocr?gpio control register r/w 0x0000_0000 18.4.1.7/18-10 0xe_0040 gpoutdr?general-purpose out put data register r/w 0x0000_0000 18.4.1.8/18-11 0xe_0050 gpindr?general-purpose input data register r 0x nnnn _0000 18.4.1.9/18-12 0xe_0060 pmuxcr?alternate function sig nal multiplex control r/w 0x0000_0000 18.4.1.9/18-12 table 2-9. memory map (continued) offset register acce ss reset section/page 4 datasheet u .com
memory map MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 2-52 freescale semiconductor device disables 0xe_0070 devdisr?device disable control r/w 0x0000_0000 18.4.1.11/18-14 power management registers 0xe_0080 powmgtcsr?power man agement status and control register r/w 0x0000_0000 18.4.1.12/18-16 interrupt reporting 0xe_0090 mcpsumr?machine check summary register read/cle ar 0x0000_0000 18.4.1.13/18-17 version registers 0xe_00a0 pvr?processor version register r e500 processor version 18.4.1.14/18-18 0xe_00a4 svr?system version register r MPC8555E/ mpc8541e system version 18.4.1.15/18-19 debug control 0xe_0e00 clkocr?clock out select register r/w 0x0000_0000 18.4.1.16/18-19 0xe_0e20 lbdllcr?lbc dll control register r/w 0x0000_0000 18.4.1.17/18-20 performance monitor control registers 0xe_1000 pmgc0?performance monitor global control register r/w 0x0000_0000 19.3.2.1/19-5 0xe_1010 pmlca0?performance monitor local control register a0 r/w 0x0000_0000 19.3.2.2/19-5 0xe_1014 pmlcb0?performance monitor local control register b0 r/w 0x0000_0000 19.3.2.2/19-5 0xe_1018 pmc0 (upper)?performance monitor counter 0 upper r/w 0x0000_0000 19.3.3.1/19-9 0xe_101c pmc0 (lower)?performance monitor counter 0 lower r/w 0x0000_0000 19.3.3.1/19-9 0xe_1020 pmlca1?performance monitor local control register a1 r/w 0x0000_0000 19.3.2.2/19-5 0xe_1024 pmlcb1?performance monitor local control register b1 r/w 0x0000_0000 19.3.2.2/19-5 0xe_1028 pmc1?performance monitor counter 1 r/w 0x0000_0000 19.3.3.1/19-9 0xe_1030 pmlca2?performance monitor local control register a2 r/w 0x0000_0000 19.3.2.2/19-5 0xe_1034 pmlcb2?performance monitor local control register b2 r/w 0x0000_0000 19.3.2.2/19-5 0xe_1038 pmc2?performance monitor counter 2 r/w 0x0000_0000 19.3.3.1/19-9 0xe_1040 pmlca3?performance monitor local control register a3 r/w 0x0000_0000 19.3.2.2/19-5 0xe_1044 pmlcb3?performance monitor local control register b3 r/w 0x0000_0000 19.3.2.2/19-5 0xe_1048 pmc3?performance monitor counter 3 r/w 0x0000_0000 19.3.3.1/19-9 0xe_1050 pmlca4?performance monitor local control register a4 r/w 0x0000_0000 19.3.2.2/19-5 0xe_1054 pmlcb4?performance monitor local control register b4 r/w 0x0000_0000 19.3.2.2/19-5 0xe_1058 pmc4?performance monitor counter 4 r/w 0x0000_0000 19.3.3.1/19-9 table 2-9. memory map (continued) offset register acce ss reset section/page 4 datasheet u .com
memory map MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 2-53 0xe_1060 pmlca5?performance monitor local control register a5 r/w 0x0000_0000 19.3.2.2/19-5 0xe_1064 pmlcb5?performance monitor local control register b5 r/w 0x0000_0000 19.3.2.2/19-5 0xe_1068 pmc5?performance monitor counter 5 r/w 0x0000_0000 19.3.3.1/19-9 0xe_1070 pmlca6?performance monitor local control register a6 r/w 0x0000_0000 19.3.3.1/19-9 0xe_1074 pmlcb6?performance monitor local control register b6 r/w 0x0000_0000 19.3.2.2/19-5 0xe_1078 pmc6?performance monitor counter 6 r/w 0x0000_0000 19.3.3.1/19-9 0xe_1080 pmlca7?performance monitor local control register a7 r/w 0x0000_0000 19.3.2.2/19-5 0xe_1084 pmlcb7?performance monitor local control register b7 r/w 0x0000_0000 19.3.2.2/19-5 0xe_1088 pmc7?performance monitor counter 7 r/w 0x0000_0000 19.3.3.1/19-9 0xe_1090 pmlca8?performance monitor local control register a8 r/w 0x0000_0000 19.3.2.2/19-5 0xe_1094 pmlcb8?performance monitor local control register b8 r/w 0x0000_0000 19.3.2.2/19-5 0xe_1098 pmc8?performance monitor counter 8 r/w 0x0000_0000 19.3.3.1/19-9 debug and watchpoint monitor registers watchpoint monitor registers 0xe_2000 wmcr0?watchpoint monitor control register 0 r/w 0x0000_0000 20.3.1.1/20-10 0xe_2004 wmcr1?watchpoint monitor control register 1 r/w 0x0000_0000 20.3.1.1/20-10 0xe_200c wmar?watchpoint monitor address register r/w 0x0000_0000 20.3.1.2/20-12 0xe_2014 wmamr?watchpoint monitor address mask register r/w 0x0000_0000 20.3.1.3/20-13 0xe_2018 wmtmr?watchpoint monitor transaction mask register r/w 0x0000_0000 20.3.1.4/20-13 0xe_201c wmsr?watchpoint monitor status register r/w 0x0000_0000 20.3.1.5/20-15 trace buffer registers 0xe_2040 tbcr0?trace buffer control register r/w 0x0000_0000 20.3.2.1/20-15 0xe_2044 tbcr1?trace buffer control register r/w 0x0000_0000 20.3.2.1/20-15 0xe_204c tbar?trace buffer address register r/w 0x0000_0000 20.3.2.2/20-18 0xe_2054 tbamr?trace buffer address mask register r/w 0x0000_0000 20.3.2.3/20-18 0xe_2058 tbtmr?trace buffer transaction mask register r/w 0x0000_0000 20.3.2.4/20-18 0xe_205c tbsr?trace buffer status register r/w 0x0000_0000 20.3.2.5/20-19 0xe_2060 tbacr?trace buffer access control register r/w 0x0000_0000 20.3.2.6/20-20 0xe_2064 tbadhr?trace buffer access data high register r/w 0x0000_0000 20.3.2.7/20-21 0xe_2068 tbadr?trace buffer access data register r/w 0x0000_0000 20.3.2.8/20-21 context id registers 0xe_20a0 pcidr?programmed context id register r/w 0x0000_0000 20.3.3.1/20-22 0xe_20a4 ccidr?current context id register r/w 0x0000_0000 20.3.3.2/20-22 table 2-9. memory map (continued) offset register acce ss reset section/page 4 datasheet u .com
memory map MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 2-54 freescale semiconductor other registers 0xe_20b0 tosr?trigger output source register r/w 0x0000_0000 20.3.4.1/20-23 1 port size for br0 is configured from external pins during reset, hence ?rr? is either 0x08, 0x10, or 0x18. table 2-9. memory map (continued) offset register acce ss reset section/page 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 3-1 chapter 3 signal descriptions this chapter describes the MPC8555E external signa ls. it is organized into the following sections: ? overview of signals and cross re ferences for signals that serve multiple functions, including two lists: one ordered by functiona l block and one alphabetical. ? list of reset configuration signals ? list of output signal states at reset note a bar over a signal name indicates that the signal is active low, such as irq_out (interrupt out). active-low signa ls are referred to as asserted (active) when they are low and negate d when they are high. signals that are not active low, such as ir q (interrupt input), are refe rred to as asserted when they are high and negated when they are low. internal signals throughout this documen t are shown as lower case and in italics. for example, sys_logic_clk is an internal signal. these are referenced only as necessary for unders tanding of the extern al functionality of the device. 3.1 signals overview the MPC8555E signals are grouped as follows: ? ddr memory interface signals ? pci interface signals ? ethernet management interface signals ? tsec1 interface signals ? tsec2 interface signals ? local bus interface signals ? dma interface signals ? pic interface signals ? duart interface signals ?i 2 c interface signals ? cpm interface signals ? system control, power ma nagement, and debug signals ? test, jtag, and configuration signals ? clock signals 4 datasheet u .com
signal descriptions MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 3-2 freescale semiconductor figure 3-1 illustrates the external signals of the mp c8555e, showing how the signals are grouped. refer to the MPC8555E powerquicc? iii integrated processor hardware specifications for a pinout diagram showing pin numbers and a listing of all th e electrical and mechan ical specifications. note that individual chapters of this document provide details for each signal, describing each signal?s behavior when asserted and negated and when the signal is an input or an output. figure 3-1. MPC8555E signal groupings MPC8555E 1 mdq[0:63] mecc[0:7] mdm[0:7] mdqs[0:7] mdm[8] mdqs[8] mba[0:1] ma[0:14] 64 8 8 1 8 1 2 15 mwe mras mcas mcs [0:3] 1 1 1 4 mcke[0:1] 2 pci1_req 0 , pci2_req 0 pci1_req [4:1], pci2_req [4:1] pci1_gnt 0 , pci2_gnt 0 pci1_gnt [4:1], pci2_gnt [4:1] ec_mdc ec_mdio 2 8 2 8 1 1 tsec1_tx_en tsec1_tx_er tsec1_tx_clk 8 1 1 1 tsec1_gtx_clk tsec1_crs 1 1 tsec1_col tsec1_rxd[7:0] 1 8 tsec1_rx_dv tsec1_rx_er 1 1 tsec1_rx_clk 1 32 4 1 4 4 4 4 1 local bus interface 1 1 1 1 1 1 1 1 9 3 1 1 1 power management 1 1 5 1 1 1 1 1 1 67 signals 1 signal pci1_ad[63:0] 64 pci1_c/be [7:0] pci1_par, pci1_par64 pci1_frame , pci2_frame pci1_trdy , pci2_trdy 8 2 2 2 pci1_irdy , pci2_irdy pci1_stop , pci2_stop 2 2 pci1_devsel , pci2_devsel pci1_idsel, pci2_idsel 2 2 pci1_req64 pci1_ack64 1 1 pci1_perr , pci2_perr pci1_serr , pci2_serr 2 2 te s t 7 signals jtag 5 signals 1 1 1 8 1 1 1 1 1 1 8 1 1 1 lwe [0:3]/lbs [0:3] lbctl lale lgpl0/lsda10 lgpl1/lsdwe lgpl2/loe /lsdras lgpl3/lsdcas lgpl4/lgta /lupwait/lpbse lgpl5 lad[0:31] ldp[0:3] la27 la[28:31] lcs [0:3] lcs [4:7] asleep lssd_mode l1_tstclk l2_tstclk mcp ude irq[0:8] irq[9:11] irq_out iic_sda iic_scl tck tdi tdo tms trst trig_in trig_out msrcid[0:4] mdval tsec1_txd[7:0] ec_gtx_clk125 1 1 pic interface 15 signals debug 8 signals pci interface 112 signals dma_dreq [0:1],dma_dreq [2:3] dma_dack [0:1],dma_dack [2:3] dma_ddone [0:1],dma_ddone [2:3] 4 4 4 i 2 c interface 2 signals ethernet interface 3 signals tsec1 ethernet interface 25 signals dma interface 12 signals tsec2 ethernet interface 25 signals tsec2_tx_en tsec2_tx_er tsec2_tx_clk tsec2_gtx_clk tsec2_crs tsec2_col tsec2_rxd[7:0] tsec2_rx_dv tsec2_rx_er tsec2_rx_clk tsec2_txd[7:0] memory interface 128 signals mck[0:5], mck [0:5] 12 1 lcke 3 lclk[0:2] 2 lsync_in, lsync_out 24 14 28 16 pa[8:31] pb[18:31] pc[0:1] [4:29] pd[7] [14:25] [29:31] cpm 82 signals clock 2 1 5 signals pci1_clk, pci2_clk rtc 1 test_sel0 (MPC8555E)/test_sel0(mpc8541e) 1 clk_out 1 1 1 1 1 hreset hreset_req sreset ckstp_in ckstp_out system control 6 signals 1 ready 2 therm[0:1] 2 2 2 uart_sin[0:1] uart_sout[0:1] uart_cts [0:1] uart_rts [0:1] 2 dual uart interface 8 signals 1 sysclk 1 test_sel1 4 datasheet u .com
signal descriptions MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 3-3 the following tables provide summaries of signal functions. table 3-1 provides a summary of the signals grouped by function, and table 3-4 provides a summary of the signals grouped alphabetically. these tables detail the signal name, interface, al ternate functions, number of signals, and whether the signal is an input, output, or bidirectional. the direct ion of the multiplexed signals appl ies for the primary signal function listed in the left-most column of the table for that row (and does not apply for the state of the reset configuration signals). finally, the table provides a pointer to the table wh ere the signal function is described. table 3-1. MPC8555E signal reference by functional block name description functional block alternate function(s) no. of signals i/o table/page mdq[0:63] ddr data ddr memory ? 64 i/o 9-3/9-5 mecc[0:7] ddr error correcting code ddr memory ? 8 i/o 9-3/9-5 mdm[0:7] ddr data mask ddr memory ? 8 o 9-3/9-5 mdm8 ddr ecc data mask ddr memory ? 1 o 9-3/9-5 mdqs[0:7] ddr data strobe ddr memory ? 8 i/o 9-3/9-5 mdqs8 ddr ecc data strobe ddr memory ? 1 i/o 9-3/9-5 mba[0:1] ddr bank select ddr memory ? 2 o 9-3/9-5 ma[0:14] ddr address ddr memory ? 15 o 9-3/9-5 mwe ddr write enable ddr memory ? 1 o 9-3/9-5 mras ddr row address strobe ddr memory ? 1 o 9-3/9-5 mcas ddr column address strobe ddr memory ? 1 o 9-3/9-5 mcs [0:3] ddr chip select (2/dimm) ddr memory ? 4 o 9-3/9-5 mcke[0:1] ddr clock enable ddr memory ? 2 o 9-4/9-8 mck[0:5], mck [0:5] ddr differential clocks (3 pairs/dimm) ddr memory ? 12 o 9-4/9-8 pci1_ad[63:0] pci address/data pci ? 64 i/o 16-2/16-8 pci1_c/be [7:0] pci command/byte enable pci ? 8 i/o 16-2/16-8 pci1_par pci parity pci ? 1 i/o 16-2/16-8 pci1_par64/ pci2_par pci parity 64 pci ? 1 i/o 16-2/16-8 pci1_frame pci frame pci ? 1 i/o 16-2/16-8 pci1_trdy , pci2_trdy pci target ready pci ? 2 i/o 16-2/16-8 pci1_irdy , pci2_irdy pci initiator ready pci ? 2 i/o 16-2/16-8 pci1_stop , pci2_stop pci stop pci ? 2 i/o 16-2/16-8 pci1_devsel pci device select pci ? 1 i/o 16-2/16-8 4 datasheet u .com
signal descriptions MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 3-4 freescale semiconductor pci1_idsel, pci2_idsel pci initial device select pci ? 2 i 16-2/16-8 pci1_req64/ pci2_frame pci request 64/ pci2 frame pci cfg_pci1_impd 1 i/o 16-2/16-8 pci1_ack64/ pci2_devsel pci acknowledge 64/ pci2 device select pci ? 1 i/o 16-2/16-8 pci1_perr , pci2_perr pci parity error pci ? 2 i/o 16-2/16-8 pci1_serr , pci2_serr pci system error pci ? 2 i/o 16-2/16-8 pci1 _req [4:0], pci2_req [4:0] pci request 4?0 pci ? 10 i 16-2/16-8 pci1_gnt0 pci1 grant 0 pci ? 1 i/o 16-2/16-8 pci1 _gnt1 pci1 grant 1 pci cfg_pci1_impd 1 o 16-2/16-8 pci1 _gnt2 pci1 grant 2 pci cfg_pci1_arb 1 o 16-2/16-8 pci1 _gnt3 pci1 grant 3 pci cfg_pci1_debug 1 o 16-2/16-8 pci1 _gnt4 pci1 grant 4 pci cfg_pci1_hold_en 1 o 16-2/16-8 pci2_gnt0 pci2 grant 0 pci ? 1 i/o 16-2/16-8 pci2_gnt1 pci grant 1 pci cfg_pc2_impd 1 o 16-2/16-8 pci2_gnt2 pci grant 2 pci cfg_pci2_arb 1 o 16-2/16-8 pci2_gnt3 pci grant 3 pci ? 1 o 16-2/16-8 pci2_gnt4 pci grant 4 pci cfg_pci2_hold_en 1 o 16-2/16-8 ec_gtx_clk125 gigabit reference clock gigabit clock ? 1 i 14-3/14-14 ec_mdc ethernet management data clock ethernet management cfg_tsec_reduce 1 o 14-3/14-14 ec_mdio ethernet management data in/out ethernet management ?1i/o 14-3/14-14 tsec1_txd[7:0] tsec1 transmit data 7?0 tsec1 ? 8 o 14-3/14-14 tsec1_tx_en tsec1 tran smit enable tsec1 ? 1 o 14-3/14-14 tsec1_tx_er tsec1 tran smit error tsec1 ? 1 o 14-3/14-14 tsec1_tx_clk tsec1 transmit clock in tsec1 ? 1 i 14-3/14-14 tsec1_gtx_clk tsec1 tran smit clock out tsec1 ? 1o 14-3/14-14 tsec1_crs tsec1 carrier sense tsec1 ? 1 i 14-3/14-14 tsec1_col tsec1 collision detect tsec1 ? 1 i 14-3/14-14 tsec1_rxd[7:0] tsec1 receive data 7?0 tsec1 ? 8 i 14-3/14-14 table 3-1. MPC8555E signal reference by functional block (continued) name description functional block alternate function(s) no. of signals i/o table/page 4 datasheet u .com
signal descriptions MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 3-5 tsec1_rx_dv tsec1 receive data valid tsec1 ? 1 i 14-3/14-14 tsec1_rx_er tsec1 receiver error tsec1 ? 1 i 14-3/14-14 tsec1_rx_clk tsec1 receive clock tsec1 ? 1 i 14-3/14-14 tsec2_txd[7:4] tsec2 transmit data 7?4 tsec2 ? 4 o 14-3/14-14 tsec2_txd3 tsec2 transmit data 3 tsec2 cfg_tsec1 1 o 14-3/14-14 tsec2_txd2 tsec2 transmit data 2 tsec2 cfg_tsec2 1 o 14-3/14-14 tsec2_txd1 tsec2 transmit data 1 tsec2 cfg_pci1_clk 1 o 14-3/14-14 tsec2_txd0 tsec2 transmit data 0 tsec2 cfg_pci2_clk 1 o 14-3/14-14 tsec2_tx_en tsec2 tran smit enable tsec2 ? 1 o 14-3/14-14 tsec2_tx_er tsec2 tran smit error tsec2 ? 1 o 14-3/14-14 tsec2_tx_clk tsec2 transmit clock in tsec2 ? 1 i 14-3/14-14 tsec2_gtx_clk tsec2 tran smit clock out tsec2 ? 1 o 14-3/14-14 tsec2_crs tsec2 carrier sense tsec2 ? 1 i 14-3/14-14 tsec2_col tsec2 collision detect tsec2 ? 1 i 14-3/14-14 tsec2_rxd[7:0] tsec2 receive data tsec2 ? 8 i 14-3/14-14 tsec2_rx_dv tsec2 receive data valid tsec2 ? 1 i 14-3/14-14 tsec2_rx_er tsec2 receiver error tsec2 ? 1 i 14-3/14-14 tsec2_rx_clk tsec2 receive clock tsec2 ? 1 i 14-3/14-14 lad[0:31] lbc address/data lbc cfg_gpinput[0:31] 32 i/o 13-1/13-4 ldp[0:3] lbc data parity lbc ? 4 i/o 13-1/13-4 la27 lbc burst address lbc cfg_cpu_boot 1 o 13-1/13-4 la[28:31] lbc port address lbc cfg_sys_pll[0:3] 4 o 13-1/13-4 lcs [0:4] lbc chip select 0?4 lbc ? 5 o 13-1/13-4 lcs5 lbc chip select 5 lbc dma_dreq2 1o 13-1/13-4 lcs6 lbc chip select 6 lbc dma_dack2 1o 13-1/13-4 lcs7 lbc chip select 7 lbc dma_ddone2 1o 13-1/13-4 lwe0 / lsddqm0/lbs0 lbc write enable/byte lane data mask/byte select 0 lbc cfg_lb_hold_en0 1 o 13-1/13-4 lwe1 / lsddqm1/lbs1 lbc write enable/byte lane data mask/byte select 1 lbc cfg_lb_hold_en1 1 o 13-1/13-4 lwe2 / lsddqm2/lbs2 lbc write enable/byte lane data mask/byte select 2 lbc cfg_host_agt 1 o 13-1/13-4 lwe3 / lsddqm3/lbs3 lbc write enable/byte lane data mask/byte select 3 lbc cfg_rom_loc2 1 o 13-1/13-4 table 3-1. MPC8555E signal reference by functional block (continued) name description functional block alternate function(s) no. of signals i/o table/page 4 datasheet u .com
signal descriptions MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 3-6 freescale semiconductor lbctl lbc data buffer control lbc ? 1 o 13-1/13-4 lale lbc address latch enable lbc cfg_core_pll0 1 o 13-1/13-4 lgpl0/lsda10 lbc upm general purpose line 0/sdram address bit 10 lbc cfg_rom_loc0 1 o 13-1/13-4 lgpl1/lsdwe lbc gp line 1/sdram write enable lbc cfg_rom_loc1 1 o 13-1/13-4 lgpl2/loe / lsdras lbc gp line 2/output enable/sdram ras lbc cfg_core_pll1 1 o 13-1/13-4 lgpl3/lsdcas lbc gp line 3/sdram cas lbc cfg_boot_seq0 1 o 13-1/13-4 lgpl4/lgta / lupwait/lpbse lbc gp line 4/gpcm terminate access/upm wait/parity byte select lbc ? 1 i/o 13-1/13-4 lgpl5 lbc gp line 5 address lbc cfg_boot_seq1 1 o 13-1/13-4 lcke lbc clock enable lbc ? 1 o 13-1/13-4 lclk[0:2] lbc clock lbc ? 3 o 13-1/13-4 lsync_in, lsync_out lbc dll synchroni zation lbc ? 2 i/o 13-1/13-4 dma_dreq [0:1] dma request 0?1 dma ? 2 i 15-3/15-5 dma_dreq2 dma request 2 dma lcs 5 1i 15-3/15-5 dma_dreq3 dma request 3 dma irq9 1 i 15-3/15-5 dma_dack [0:1] dma acknowledge 0?1 dma ? 2 o 15-3/15-5 dma_dack2 dma acknowledge 2 dma lcs 6 1o 15-3/15-5 dma_dack3 dma acknowledge 3 dma irq10 1 o 15-3/15-5 dma_ddone [0:1] dma done 0?1 dma ? 2 o 15-3/15-5 dma_ddone2 dma done 2 dma lcs 7 1o 15-3/15-5 dma_ddone3 dma done 3 dma irq11 1 o 15-3/15-5 mcp machine check processor pic ? 1 i 10-5/10-7 ude unconditional debug event pic ? 1 i 10-5/10-7 irq[0:8] external interrupt 0?8 pic ? 9 i 10-5/10-7 irq9 external interrupt 9 pic dma_dreq3 1i 10-5/10-7 irq10 external interrupt 10 pic dma_dack3 1i 10-5/10-7 irq11 external interrupt 11 pic dma_ddone3 1i 10-5/10-7 irq_out interrupt output pic ? 1 o 10-5/10-7 uart_sin[0:1] duart serial data in dual uart ? 2 i 12-2/12-3 table 3-1. MPC8555E signal reference by functional block (continued) name description functional block alternate function(s) no. of signals i/o table/page 4 datasheet u .com
signal descriptions MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 3-7 uart_sout[0:1] duart serial data out dual uart ? 2 o 12-2/12-3 uart_cts [0:1] duart clear to send dual uart ? 2 i 12-2/12-3 uart_rts [0:1] duart ready to send dual uart ? 2 o 12-2/12-3 iic_sda i 2 c serial data i 2 c?1i/o 11-2/11-4 iic_scl i 2 c serial clock i 2 c?1i/o 11-2/11-4 hreset hard reset system control ? 1 i 4-2/4-2 hreset_req hard reset request system control ? 1 o 4-2/4-2 sreset soft reset system control ? 1 i 4-2/4-2 ckstp_in checkstop in system control ? 1 i 18-2/18-2 ckstp_out checkstop out system control ? 1 o 18-2/18-2 ready device ready system control trig_out 1 o 4-2/4-2 trig_in watchpoint trigger in debug ? 1 i 20-2/20-5 trig_out watchpoint trigger out debug ready 1 o 20-2/20-5 msrcid[0:1] memory debug source port id 0?1 debug cfg_mem_debug cfg_ddr_debug 2o 9-6/9-10 msrcid[2:4] memory debug source port id2?4 debug ? 3 o 20-2/20-5 mdval memory debug data valid debug ? 1 o 20-2/20-5 asleep asleep power mgmt ? 1 o 18-2/18-2 sysclk system clock/pci clock clock ? 1 i 4-3/4-3 pci1_clk, pci2_clk asynchronous pci clock clock ? 2 i 4-3/4-3 rtc real time clock clock ? 1 i 4-3/4-3 clk_out clock out clock ? 1 o 18-2/18-2 lssd_mode lssd mode test ? 1 i 20-2/20-5 l1_tstclk l1 test clock test ? 1 i 20-2/20-5 l2_tstclk l2 test clock test ? 1 i 20-2/20-5 test_sel0 (MPC8555E) test_sel0 (mpc8541e) test select 0 test ? 1 i 20-2/20-5 test_sel1 test select 1 test ? 1 i 20-2/20-5 therm[0:1] thermal resistor access test ? 2 i 20-2/20-5 tck test clock jtag ? 1 i 20-2/20-5 table 3-1. MPC8555E signal reference by functional block (continued) name description functional block alternate function(s) no. of signals i/o table/page 4 datasheet u .com
signal descriptions MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 3-8 freescale semiconductor tdi test data in jtag ? 1 i 20-2/20-5 tdo test data out jtag ? 1 o 20-2/20-5 tms test mode select jtag ? 1 i 20-2/20-5 trst test reset jtag ? 1 i 20-2/20-5 pa[8:31] port a cpm ? 24 i/o 45-17/45-18 pb[18:31] port b cpm ? 14 i/o 45-18/45-21 pc[0:1] [4:29] port c cpm ? 28 i/o 45-19/45-22 pd[7] [14:25] [29:31] port d cpm ? 16 i/o 45-20/45-24 table 3-2. MPC8555E alphabetical signal reference name description functional block alternate function(s) no. of signals i/o table/page asleep asleep power mgmt ? 1 o 18-2/18-2 ckstp_in checkstop in system control ? 1 i 18-2/18-2 ckstp_out checkstop out system control ? 1 o 18-2/18-2 clk_out clock out clock ? 1 o 18-2/18-2 dma_dack2 dma acknowledge 2 dma lcs 6 1o 15-3/15-5 dma_dack3 dma acknowledge 3 dma irq10 1 o 15-3/15-5 dma_dack [0:1] dma acknowledge 0?1 dma ? 2 o 15-3/15-5 dma_ddone2 dma done 2 dma lcs 7 1o 15-3/15-5 dma_ddone3 dma done 3 dma irq11 1 o 15-3/15-5 dma_ddone [0:1] dma done 0?1 dma ? 2 o 15-3/15-5 dma_dreq2 dma request 2 dma lcs 5 1i 15-3/15-5 dma_dreq3 dma request 3 dma irq9 1 i 15-3/15-5 dma_dreq [0:1] dma request 0?1 dma ? 2 i 15-3/15-5 ec_gtx_clk125 gigabit reference clock gigabit clock ? 1 i 14-3/14-14 ec_mdc ethernet management data clock ethernet management cfg_tsec_reduce 1 o 14-3/14-14 ec_mdio ethernet management data in/out ethernet management ?1i/o 14-3/14-14 hreset hard reset system control ? 1 i 4-2/4-2 hreset_req hard reset request system control ? 1 o 4-2/4-2 iic_scl i 2 c serial clock i 2 c?1i/o 11-2/11-4 table 3-1. MPC8555E signal reference by functional block (continued) name description functional block alternate function(s) no. of signals i/o table/page 4 datasheet u .com
signal descriptions MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 3-9 iic_sda i 2 c serial data i 2 c?1i/o 11-2/11-4 irq[0:8] external interrupt 0?8 pic ? 9 i 10-5/10-7 irq10 external interrupt 10 pic dma_dack3 1i 10-5/10-7 irq11 external interrupt 11 pic dma_ddone3 1i 10-5/10-7 irq9 external interrupt 9 pic dma_dreq3 1i 10-5/10-7 irq_out interrupt output pic ? 1 o 10-5/10-7 l1_tstclk l1 test clock test ? 1 i 20-2/20-5 l2_tstclk l2 test clock test ? 1 i 20-2/20-5 la27 lbc burst address lbc cfg_cpu_boot 1 o 13-1/13-4 lad[0:31] lbc address/data lbc cfg_gpinput[0:31] 32 i/o 13-1/13-4 lale lbc address latch enable lbc cfg_core_pll0 1 o 13-1/13-4 la[28:31] lbc port address lbc cfg_sys_pll0 cfg_sys_pll1 cfg_sys_pll2 cfg_sys_pll3 4o 13-1/13-4 lbctl lbc data buffer control lbc ? 1 o 13-1/13-4 lcke lbc clock enable lbc ? 1 o 13-1/13-4 lclk[0:2] lbc clock lbc ? 3 o 13-1/13-4 lcs5 lbc chip select 5 lbc dma_dreq2 1o 13-1/13-4 lcs6 lbc chip select 6 lbc dma_dack2 1o 13-1/13-4 lcs7 lbc chip select 7 lbc dma_ddone2 1o 13-1/13-4 lcs [0:4] lbc chip select 0?4 lbc ? 5 o 13-1/13-4 ldp[0:3] lbc data parity lbc ? 4 i/o 13-1/13-4 lgpl0/lsda10 lbc upm general purpose line 0/sdram address bit 10 lbc cfg_rom_loc0 1 o 13-1/13-4 lgpl1/lsdwe lbc gp line 1/sdram write enable lbc cfg_rom_loc1 1 o 13-1/13-4 lgpl2/loe / lsdras lbc gp line 2/output enable/sdram ras lbc cfg_core_pll1 1 o 13-1/13-4 lgpl3/lsdcas lbc gp line 3/sdram cas lbc cfg_boot_seq0 1 o 13-1/13-4 lgpl4/lgta / lupwait/lpbse lbc gp line 4/gpcm terminate access/upm wait/parity byte select lbc ? 1 i/o 13-1/13-4 lgpl5 lbc gp line 5 address lbc cfg_boot_seq1 1 o 13-1/13-4 lssd_mode lssd mode test ? 1 i 20-2/20-5 table 3-2. MPC8555E alphabetical signal reference (continued) name description functional block alternate function(s) no. of signals i/o table/page 4 datasheet u .com
signal descriptions MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 3-10 freescale semiconductor lsync_in, lsync_out lbc dll synchroni zation lbc ? 2 i/o 13-1/13-4 lwe0 / lsddqm0/lbs0 lbc write enable/byte lane data mask/byte select 0 lbc cfg_lb_hold_en0 1 o 13-1/13-4 lwe1 / lsddqm1/lbs1 lbc write enable/byte lane data mask/byte select 1 lbc cfg_lb_hold_en1 1 o 13-1/13-4 lwe2 / lsddqm2/lbs2 lbc write enable/byte lane data mask/byte select 2 lbc cfg_host_agt 1 o 13-1/13-4 lwe3 / lsddqm3/lbs3 lbc write enable/byte lane data mask/byte select 3 lbc cfg_rom_loc2 1 o 13-1/13-4 ma[0:14] ddr address ddr memory ? 15 o 9-3/9-5 mba[0:1] ddr bank select ddr memory ? 2 o 9-3/9-5 mcas ddr column address strobe ddr memory ? 1 o 9-3/9-5 mcke[0:1] ddr clock enable ddr memory ? 2 o 9-4/9-8 mck[0:5], mck [0:5] ddr differential clocks (3 pairs/dimm) ddr memory ? 12 o 9-4/9-8 mcp machine check processor pic ? 1 i 10-5/10-7 mcs [0:3] ddr chip select (2/dimm) ddr memory ? 4 o 9-3/9-5 mdm8 ddr ecc data mask ddr memory ? 1 o 9-3/9-5 mdm[0:7] ddr data mask ddr memory ? 8 o 9-3/9-5 mdqs8 ddr ecc data strobe ddr memory ? 1 i/o 9-3/9-5 mdqs[0:7] ddr data strobe ddr memory ? 8 i/o 9-3/9-5 mdq[0:63] ddr data ddr memory ? 64 i/o 9-3/9-5 mdval memory debug data valid debug ? 1 o 20-2/20-5 mecc[0:7] ddr error correcting code ddr memory ? 8 i/o 9-3/9-5 mras ddr row address strobe ddr memory ? 1 o 9-3/9-5 msrcid[0:1] memory debug source port id 0?1 debug cfg_mem_debug cfg_ddr_debug 2o 9-6/9-10 msrcid[2:4] memory debug source port id 2?4 debug ? 3 o 20-2/20-5 mwe ddr write enable ddr memory ? 1 o 9-3/9-5 pa[8:31] port a cpm ? 24 i/o 45-17/45-18 pb[18:31] port b cpm ? 14 i/o 45-18/45-21 pci1_ack64 / pci2_devsel pci acknowledge 64/ pci2 device select pci ? 1 i/o 16-2/16-8 pci1_ad[63:0] pci address/data pci ? 64 i/o 16-2/16-8 table 3-2. MPC8555E alphabetical signal reference (continued) name description functional block alternate function(s) no. of signals i/o table/page 4 datasheet u .com
signal descriptions MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 3-11 pci1_c/be [7:0] pci command/byte enable pci ? 8 i/o 16-2/16-8 pci1_clk, pci2_clk asynchronous pci clock clock ? 2 i 4-3/4-3 pci1_devsel pci device select pci ? 1 i/o 16-2/16-8 pci1_frame pci1 frame pci ? 1 i/o 16-2/16-8 pci1_gnt0 pci1 grant 0 pci ? 1 i/o 16-2/16-8 pci1_ gnt1 pci1 grant 1 pci cfg_pci1_impd 1 o 16-2/16-8 pci1_ gnt2 pci1 grant 2 pci cfg_pci1_arb 1 o 16-2/16-8 pci1_ gnt3 pci1 grant 3 pci cfg_pci1_debug 1 o 16-2/16-8 pci1_ gnt4 pci1 grant 4 pci cfg_pci1_hold_en 1 o 16-2/16-8 pci2_gnt0 pci2 grant 0 pci ? 1 i/o 16-2/16-8 pci2_ gnt1 pci2 grant 1 pci cfg_pci2_impd 1 o 16-2/16-8 pci2_ gnt2 pci2 grant 2 pci cfg_pci2_arb 1 o 16-2/16-8 pci2_ gnt3 pci2 grant 3 pci ? 1 o 16-2/16-8 pci2_ gnt4 pci2 grant 4 pci cfg_pci2_hold_en 1 o 16-2/16-8 pci1_idsel, pci2_idsel pci initial device select pci ? 2 i 16-2/16-8 pci1_irdy , pci2_irdy pci initiator ready pci ? 2 i/o 16-2/16-8 pci1_par pci1 parity pci ? 1 i/o 16-2/16-8 pci1_par64/ pci2_par pci1 parity 64/pci2 parity pci ? 1 i/o 16-2/16-8 pci1_perr , pci2_perr pci parity error pci ? 2 i/o 16-2/16-8 pci1_req64 / pci2_frame pci request 64/pci frame pci cfg_pci1_impd 1 i/o 16-2/16-8 pci1 _req [4:0], pci2_req [4:0] pci request 4?0 pci ? 10 i 16-2/16-8 pci1_serr , pci2_serr pci system error pci ? 2 i/o 16-2/16-8 pci1_stop , pci2_stop pci stop pci ? 2 i/o 16-2/16-8 pci1_trdy , pci2_trdy pci target ready pci ? 2 i/o 16-2/16-8 pc[0:1] [4:29] port c cpm ? 28 i/o 45-19/45-22 table 3-2. MPC8555E alphabetical signal reference (continued) name description functional block alternate function(s) no. of signals i/o table/page 4 datasheet u .com
signal descriptions MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 3-12 freescale semiconductor pd[7] [14:25] [29:31] port d cpm ? 16 i/o 45-20/45-24 ready device ready system control trig_out 1 o 4-2/4-2 rtc real time clock clock ? 1 i 4-3/4-3 sreset soft reset system control ? 1 i 4-2/4-2 sysclk system clock/pci clock clock ? 1 i 4-3/4-3 tck test clock jtag ? 1 i 20-2/20-5 tdi test data in jtag ? 1 i 20-2/20-5 tdo test data out jtag ? 1 o 20-2/20-5 test_sel0 (MPC8555E) test_sel0 (mpc8541e) test select 0 test ? 1 i 20-2/20-5 test_sel1 test select 1 test ? 1 i 20-2/20-5 therm[0:1] thermal resistor access test ? 2 i 20-2/20-5 tms test mode select jtag ? 1 i 20-2/20-5 trig_in watchpoint trigger in debug ? 1 i 20-2/20-5 trig_out watchpoint trigger out debug ready 1 o 20-2/20-5 trst test reset jtag ? 1 i 20-2/20-5 tsec1_col tsec1 collision detect tsec1 ? 1 i 14-3/14-14 tsec1_crs tsec1 carrier sense tsec1 ? 1 i 14-3/14-14 tsec1_gtx_clk tsec1 tran smit clock out tsec1 ? 1 o 14-3/14-14 tsec1_rxd[7:0] tsec1 receive data tsec1 ? 8 i 14-3/14-14 tsec1_rx_clk tsec1 receive clock tsec1 ? 1 i 14-3/14-14 tsec1_rx_dv tsec1 receive data valid tsec1 ? 1 i 14-3/14-14 tsec1_rx_er tsec1 receiver error tsec1 ? 1 i 14-3/14-14 tsec1_txd[7:0] tsec1 transmit data 7?0 tsec1 ? 8 o 14-3/14-14 tsec1_tx_clk tsec1 transmit clock in tsec1 ? 1 i 14-3/14-14 tsec1_tx_en tsec1 tran smit enable tsec1 ? 1 o 14-3/14-14 tsec1_tx_er tsec1 tran smit error tsec1 ? 1 o 14-3/14-14 tsec2_col tsec2 collision detect tsec2 ? 1 i 14-3/14-14 tsec2_crs tsec2 carrier sense tsec2 ? 1 i 14-3/14-14 tsec2_gtx_clk tsec2 tran smit clock out tsec2 ? 1 o 14-3/14-14 table 3-2. MPC8555E alphabetical signal reference (continued) name description functional block alternate function(s) no. of signals i/o table/page 4 datasheet u .com
signal descriptions MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 3-13 3.2 configuration signals sampled at reset the signals that serve alternate functions as configuration input signals during system reset are summarized in table 3-3 . the detailed interpretation of their voltage levels dur ing reset is described in chapter 4, ?reset, clocking, and initialization.? note that throughout this document, the reset configuration signals are described as being sampled at the negation of hreset . however, there is a setup a nd hold time for these signals relative to the rising edge of hreset , as described in the MPC8555E powerquicc? iii integrated processor hardware specifications . note that the pll configuration signals ha ve different setup and hold time requirements than the other reset configuration signals. the reset configuration signals are multiplexed with other functional si gnals. the values on these signals during reset are interpreted to be logic one or zero, regardless of wh ether the functional signal name is defined as active low. most of the reset configuration signals have intern al pull-up resistors so that if the signals are not driven, the default va lue is high (a one), as shown in the table. some signals do not have pull-up resistors and must be driven high or low duri ng the reset period. for deta ils about all the signals that require external pull-up resistors, see the MPC8555E powerquicc? iii integrated processor hardware specifications . tsec2_rxd[7:0] tsec2 receive data tsec2 ? 8 i 14-3/14-14 tsec2_rx_clk tsec2 receive clock tsec2 ? 1 i 14-3/14-14 tsec2_rx_dv tsec2 receive data valid tsec2 ? 1 i 14-3/14-14 tsec2_rx_er tsec2 receiver error tsec2 ? 1 i 14-3/14-14 tsec2_txd0 tsec2 transmit data 0 tsec2 cfg_pci2_clk 1 o 14-3/14-14 tsec2_txd1 tsec2 transmit data 1 tsec2 cfg_pci1_clk 1 o 14-3/14-14 tsec2_txd2 tsec2 transmit data 2 tsec2 cfg_tsec2 1 o 14-3/14-14 tsec2_txd3 tsec2 transmit data 3 tsec2 cfg_tsec1 1 o 14-3/14-14 tsec2_txd[7:4] tsec2 transmit data 7?4 tsec2 ? 4 o 14-3/14-14 tsec2_tx_clk tsec2 transmit clock in tsec2 ? 1 i 14-3/14-14 tsec2_tx_en tsec2 tran smit enable tsec2 ? 1 o 14-3/14-14 tsec2_tx_er tsec2 tran smit error tsec2 ? 1 o 14-3/14-14 uart_cts [0:1] duart clear to send dual uart ? 2 i 12-2/12-3 uart_rts [0:1] duart ready to send dual uart ? 2 o 12-2/12-3 uart_sin[0:1] duart serial data in dual uart ? 2 i 12-2/12-3 uart_sout[0:1] duart serial data out dual uart ? 2 o 12-2/12-3 ude unconditional debug event pic ? 1 i 10-5/10-7 table 3-2. MPC8555E alphabetical signal reference (continued) name description functional block alternate function(s) no. of signals i/o table/page 4 datasheet u .com
signal descriptions MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 3-14 freescale semiconductor note that the multiplexing of va rious signals on the MPC8555E is controlled by the pmuxcr register described in chapter 18, ?global utilities.? also, the multiplexing of the cpm signals occurs through the cpm programming model. see chapter 45, ?parallel i/o ports,? for details on cpm signal multiplexing. table 3-3. MPC8555E reset configuration signals functional interface functional signal name reset configuration name default pci pci1_gnt 4 cfg_pci1_hold_en 1 pci1_gnt 3 cfg_pci1_debug 1 pci1_gnt 2 cfg_pci1_arb 1 pci1_gnt 1 cfg_pci1_impd 1 pci2 pci1_req64 / pci2_frame cfg_pci1_width 1 pci2_gnt 4 cfg_pci2_hold_en 1 pci2_gnt 2 cfg_pci2_arb 1 pci2_gnt 1 cfg_pci2_impd 1 ethernet management ec_mdc cfg_tsec_reduce 1 tsec2 tsec2_txd3 cfg_tsec1 1 tsec2_txd2 cfg_tsec2 1 tsec2_txd1 cfg_pci1_clk 1 tsec2_txd0 cfg_pci2_clk 1 lbc la27 cfg_cpu_boot 1 la[28:31] cfg_sys_pll[0:3] must be driven lwe0 /lbs0 cfg_lb_hold_en0 1 lwe1 /lbs1 cfg_lb_hold_en1 1 lwe2 /lbs2 cfg_host_agt 1 lwe3 /lbs3 cfg_rom_loc2 1 lale cfg_core_pll0 must be driven lgpl0/lsda10 cfg_rom_loc0 1 lgpl1/lsdwe cfg_rom_loc1 1 lgpl2/loe /lsdras cfg_core_pll1 must be driven lgpl3/lsdcas cfg_boot_seq0 1 lgpl5 cfg_boot_seq1 1 lad[0:31] cfg_gpinput[0:31] i ndeterminate if not driven (no default) debug msrcid0 cfg_mem_debug 1 msrcid1 cfg_ddr_debug 1 4 datasheet u .com
signal descriptions MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 3-15 3.3 output signal states during reset when a system reset is recognized (hreset is asserted), the MPC8555E a borts all current internal and external transactions and releas es all bidirectional i/o signals to a high-impedance state. see chapter 4, ?reset, clocking, and initialization,? for a complete description of the reset functionality. during reset, the MPC8555E ignores most input signals (except for the reset configuration signals) and drives most of the output-only signals to an inactive state. table 3-4 shows the states of the output-only signals (that is, the signals that are not multiplexed with other inputs, or are not us ed as reset configuration signals during system reset). table 3-4. output signal states during system reset interface signal state during reset ddr memory mdm[0:8] high-z ddr memory mba[0:1] high-z ddr memory ma[0:14] high-z ddr memory mwe high-z ddr memory mras high-z ddr memory mcas high-z ddr memory mcs [0:3] high-z ddr memory mcke[0:1] driven low ddr memory mck[0:5], mck [0:5] high-z tsec1 tsec1_txd[3:0] input?reset config (test only) tsec1 tsec1_tx_en driven low tsec1 tsec1_tx_er high-z tsec1 tsec1_gtx_clk high-z tsec2 tsec2_txd[1:0] input?reset config tsec2 tsec2_tx_en driven low tsec2 tsec2_tx_er high-z tsec2 tsec2_gtx_clk high-z lbc lclk[0:2] high-z lbc lcs [0:5] high-z lbc dma_dack2 /lcs6 dma_ddone2 /lcs7 high-z lbc lbctl input?reset config (test only) dma dma_dack [0:1] high-z dma dma_dack2 /lcs6 dma_ddone2 /lcs7 high-z dma dma_ddone0 high-z 4 datasheet u .com
signal descriptions MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 3-16 freescale semiconductor dma dma_ddone1 driven (test only) pic irq8 driven (test only) pic irq_out high-z dual uart uart_sout[0:1] high-z dual uart uart_rts [0:1] high-z system control hreset_req high-z system control ckstp_out high-z debug trig_out/ready input?reset config (test only) debug msrcid[2:4] high-z debug mdval high-z power mgmt asleep input?reset config (test only) clock clk_out high-z table 3-4. output signal states during system reset (continued) interface signal state during reset 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 4-1 chapter 4 reset, clocking, and initialization this chapter describes the reset, clocking, and some overall initialization of the MPC8555E, including a definition of the reset configurations signals and the options they sel ect. additionally, the configuration, control, and status registers are de scribed. note that chapters in this book describe specif ic initialization aspects for individual blocks. 4.1 overview the reset, clocking, and control signals provide many options for the operation of the MPC8555E. additionally, many modes are selected with reset configuration signals dur ing the assertion of a hard reset (assertion of hreset ). 4.2 external signal description table 4-1 summarizes the external signals described in this chapter. table 4-2 and table 4-3 have detailed signal descriptions, but table 4-1 contains references to additional s ections that contain more information. the following sections describe the reset and clock signals in detail. 4.2.1 system control signals table 4-2 describes some of the system control signals of the MPC8555E. section 4.4.3, ?power-on reset configuration,? describes the signals that also function as reset configuration signals. note that the ckstp_in and ckstp_out signals are described in chapter 18, ?global utilities.? table 4-1. signal summary signal i/o description references (section/page) hreset i hard reset input. causes a power-on reset (por) sequence 4.4.1.2/4-8 hreset_req o hard reset request output. an internal block requests that hreset be asserted ? sreset i soft reset input. causes mcp assertion to the core and a soft reset to the cpm 4.4.1.1/4-8 ready o the MPC8555E has completed the reset operation and is not in a power-down (nap, doze or sleep) or debug state. 4.4.2/4-9 sysclk i primary clock input to the MPC8555E 4.4.4.1/4-21 pci1_clk i pci clock input for pci1 in asynchronous mode 4.4.4/4-21 pci2_clk i pci clock input for pci2 in asynchronous mode 4.4.4/4-21 rtc i real time clock input 4.4.4.3/4-22 4 datasheet u .com
reset, clocking, and initialization MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 4-2 freescale semiconductor 4.2.2 clock signals table 4-3 describes the over all clock signals of the MPC8555E. note that some clock signals are specific to blocks within the MPC8555E, and although some of their functionality is described in section 4.4.4, ?clocking,? they are defined in detail in their respective chapters. note that there is also a clk_out signal in th e MPC8555E; the signal driven on the clk_out pin is selectable and described in section 18.4.1.16, ?clock out c ontrol register (clkocr).? table 4-2. system control signals?detailed signal descriptions signal i/o description hreset i hard reset. causes the MPC8555E to abort all current internal and external transactions and set all registers to their default values. hreset may be asserted completely asynchronously with respect to all other signals. state meaning asserted/negated?see chapter 3, ?signal descriptions,? and section 4.4.3, ?power-on reset configuration,? for more information on the interpretation of the other MPC8555E signals during reset. timing assertion/negation?the MPC8555E powerquicc? iii integrated processor hardware specifications gives specific timing information for this signal and the reset configuration signals. hreset_req o hard reset request. indicates to the board (sys tem in which the MPC8555E is embedded) that a condition requiring the assertion of hreset has been detected. state meaning asserted?a watchdog timer or a boot sequencer failure (see section 11.4.5, ?boot sequencer mode,? ) has triggered a request for hard reset. negated?indicates no reset request. timing assertion/negation?may occur anytime, synchrono us to the core comp lex bus clock. once asserted, hreset_req does not ne gate until hreset is asserted. sreset i soft reset. causes a machine check interrupt to the e500 core and a soft reset to the cpm. note that if the e500 core is not c onfigured to process mach ine check interrupts, the assertion of sreset causes a core checkstop. sreset need not be asserted during a hard reset. state meaning asserted?asserting sreset causes a machine check interrupt (edge sensitive) to the e500 core and a soft reset to th e cpm (level sensitive). sreset has no effect while hreset is asserted. however, the por sequence is paused if sreset is asserted during por. timing assertion?may occur at any time, asynchronous to any clock. negation?must be asserted for at least two ccb_clk cycles. ready o ready. multiplexed with trig_out. see chapter 20, ?debug features and watchpoint facility,? for more information on tosr and trig_out. state meaning asserted?indicates that the MPC8555E has co mpleted the reset operation and is not in a power-down state (nap, doze or sleep) when tosr[sel] equals 0b000. see section 4.4.2, ?power-on reset sequence,? for more information. timing assertion/negation?initial assertion of ready after reset is synchronous with sysclk. subsequent assertion/negation due to power down modes occurs asynchronously. 4 datasheet u .com
reset, clocking, and initialization MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 4-3 4.3 memory map/register definition there are no unique registers in th e reset and clocking blocks of th e MPC8555E. however, this section describes the configuration, control, and status registers of the overall MPC8555E device; it also contains a brief description of the boot sequencer. 4.3.1 local configuration control table 4-4 shows the memory map for the configuration, c ontrol, and status regi sters. undefined 4-byte address spaces within offset 0x000?0xfff are reserved. table 4-3. clock signals?detailed signal descriptions signal i/o description sysclk i system clock/pci clock (sysclk/pci_clk). sysclk is the primary clock input to the MPC8555E. it is the clock source for the e500 core and for all devices and interfaces that operate synchronously with the core. multiplied up with a phased-lock loop (pll) to cr eate the core complex bus (ccb) clock (also called the platform clock) which is used by virtually all of the synchronous system logic, include the l2 cache, the ddr sdram and local bus memory controllers, and other internal blocks such as the dma and interrupt controllers. the ccb clock, in turn, feeds the pll in the e500 core and the dll that creates the local bus memory clocks. when the pci interface is used in synchronous mode, sysclk also functions as the pci_clk signal. note that this is true whether the MPC8555E is in age nt or host mode. the MPC8555E does not provide a separate pci_clk output in host mode. timing assertion/negation?see the MPC8555E powerquicc? iii integrated processor hardware specifications for specific timing information for this signal. pci1_clk i pci1 clock can be selected as the asynchronous pci clock reference for the pci1 interface of the MPC8555E. in asynchronous mode, there is no re quired relationship betw een pci1_clk and sysclk. the pci1 interface logic can be clocked based on this input and internal logic synchronizes the pci interface logic with the platform logic. timing assertion/negation?see the MPC8555E powerquicc? iii integrated processor hardware specifications for specific timing information for this signal. pci2_clk i pci2 clock can be selected as the asynchronous pci clock reference for the pci2 interface of the MPC8555E. in asynchronous mode, there is no re quired relationship betw een pci2_clk and sysclk. the pci2 interface logic can be clocked based on this input and internal logic synchronizes the pci interface logic with the platform logic. timing assertion/negation?see the MPC8555E powerquicc? iii integrated processor hardware specifications for specific timing information for this signal. rtc i real time clock. may be used (optionally) to clock the time base of the e500 core. the rtc timing specifications are given in the MPC8555E powerquicc? iii integrated processor hardware specifications , but the maximum input frequency should not exceed 1/4th the ccb frequency. see section 4.4.4.3, ?real time clock.? this signal can also be used (optionally) to clock the global timers in the programmable interrupt controller (pic). timing assertion/negation?see the MPC8555E powerquicc? iii integrated processor hardware specifications for specific timing information for this signal. 4 datasheet u .com
reset, clocking, and initialization MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 4-4 freescale semiconductor 4.3.1.1 accessing configuration, control, and status registers the configuration, control, and stat us registers are memory mapped. the set of configuration, control, and status registers occupies a 1-m byte region of memory. their locati on is programmable using the ccsr base address register (ccsrbar). the default base address for the c onfiguration, control, and status registers is 0xff70_0000 (ccsrbar = 0x000f_f700). ccsrbar itself is part of the local access block of ccsr memory, which begins at offset 0x0 from ccsrbar. becaus e ccsrbar is at offset 0x0 from the beginning of the local access regi sters, ccsrbar always points to itself. the contents of ccsrbar are broadcast internally in the MPC8555E to all functiona l units that need to be able to identify or create configuration transactions. 4.3.1.1.1 updating ccsrbar updates to ccsrbar that relocate the entire 1-mbyte region of c onfiguration, control, and status registers, requires special treatment . the effect of the update must be guaranteed to be visible by the mapping logic before an access to the new location is seen. to make sure this happens, these guidelines should be followed: ? ccsrbar should be updated during initial confi guration of the device when only one host or controller has access to the device. ? if the boot sequencer is being used to initialize, it is re commended that the boot sequencer set ccsrbar to its desi red final location. ? if an external host on pci is c onfiguring the device, it should se t ccsrbar to the desired final location before the e500 core is released to boot. ? if the e500 core is initializing the device, it should set ccsrbar to the desired final location before enabling other i/o de vices to access the device. ? when the e500 core is writing to ccsrba r, it should use the following sequence: ? read the current value of ccsrbar using a load word instruction followed by an isync . this forces all accesses to configuration space to complete. ? write the new value to ccsrbar. ? perform a load of an address that does not access configuration spac e or the on-chip sram, but has an address mapping already in effect (for example, boot rom). fo llow this load with an isync . ? read the contents of ccsrbar from its new location, followed by another isync instruction. table 4-4. local configuration control register map local memory offset (hex) register access reset section/page 0x0_0000 ccsrbar?configuration, cont rol, and status registers base address register r/w 0x000f_f700 4.3.1.1.2/4-5 0x0_0008 altcbar?alternate configuration base address register r/w 0x0000_0000 4.3.1.2.1/4-6 0x0_0010 altcar?alternate configuratio n attribute register r/w 0x0000_0000 4.3.1.2.2/4-6 0x0_0020 bptr?boot page translation register r/w 0x0000_0000 4.3.1.3.1/4-7 4 datasheet u .com
reset, clocking, and initialization MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 4-5 4.3.1.1.2 configuration, control, and status base ad dress register (ccsrbar) figure 4-1 shows the fields of ccsrbar. figure 4-1. configuration, control, and status register base address register (ccsrbar) table 4-5 defines the bit fields of ccsrbar. 4.3.1.2 accessing alternate configuration space an alternate configuration space can be accessed by configuring the altcbar and altcar registers. these are intended to be used with the boot sequencer to allow the boot sequencer to access an alternate 1-mbyte region of configur ation space. by loading the proper boot sequencer command in the serial rom the base address in the altcbar can be combined wi th the 20 bits of address offset supplied from the serial rom to generate a 32-bit a ddress that is mapped to the targ et specified in altcar. thus, by configuring these registers, the boot sequencer has access to the enti re memory map, one 1-mbyte block at a time. see section 11.4.5, ?boot sequencer mode,? for more information. note the enable bit in the altcar register should be cleared either by the boot sequencer or by the boot code that ex ecutes after the boot sequencer has completed its configuration operati ons. this prevents problems with incorrect mappings if subs equent configuration of the local access windows uses a different target mapping for the address specified in altcbar. 01112232431 r000000000000 base_addr 00000000 w reset 0000_0000_0000_1111_1111_0111_0000_0000 offset 0x000 table 4-5. ccsrbar bit settings bits name description 0?11 ? write reserved, read = 0 12?23 base_addr identifies the12 most signif icant address bits of the window used for configuration accesses. the base address is aligned on a 1-mbyte boundary. 24?31 ? write reserved, read = 0 4 datasheet u .com
reset, clocking, and initialization MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 4-6 freescale semiconductor 4.3.1.2.1 alternate configuration base address register (altcbar) figure 4-2 shows the fields of altcbar. figure 4-2. alternate configuration base address register (altcbar) table 4-6 defines the bit fields of altcbar. 4.3.1.2.2 alternate configurati on attribute register (altcar) figure 4-3 shows the fields of altcar. figure 4-3. alternate configuratio n attribute register (altcar) table 4-7 defines altcar fields. 01112232431 r000000000000 base_addr 00000000 w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x008 table 4-6. altcbar bit settings bits name description 0?11 ? write reserved, read = 0 12?23 base_addr identifies the12 most signif icant address bits of an alternate window used for configuration accesses 24?31 ? write reserved, read = 0 0 1 7 8 11 12 31 r e n 0000000 trgt_id 00000000000000000000 w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x010 table 4-7. altcar bit settings bits name description 0 en enable for a second configuration window. like ccsrbar, it has a fixed size of 1 mbyte. 0 second configuration window is disabled 1 second configuration window is enabled 1?7 ? write reserved, read = 0 4 datasheet u .com
reset, clocking, and initialization MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 4-7 4.3.1.3 boot page translation when the e500 core comes out of reset, its mmu has one 4-kbyte pa ge defined at 0xffff_f nnn . the first instruction executed by the e500 core is always a ddress 0xffff_fffc, which must be a branch to an address within the 4-kbyte boot page. for systems in which the boot code resides at a different address, the MPC8555E provides boot page tran slation capability. boot page tran slation is controlled by the boot page translation register (bptr). the boot sequencer can enable boot page translation, or the boot page can be translated by an external host when the MPC8555E is configured to be in boot holdoff mode. if translation is pe rformed to a page outside of the default boot rom address range define d in the MPC8555E (8 mbytes at 0xff80_0000 to 0xffff_ffff as defined in section 4.4.3.3, ?boot rom location? ), the external host or boot sequencer must also set up a local access window to define the r outing of the boot code fetc h to the target interface that contains the boot code because the bptr defines only the address tran slation, not the target interface. see section 2.1, ?local memory map overview and example,? and section 11.4.5, ?boot sequencer mode,? for more information. 4.3.1.3.1 boot page transl ation register (bptr) figure 4-4 shows the fields of bptr. figure 4-4. boot page translation register (bptr) 8?11 trgt_ id identifies the device id to target when a transaction hi ts in the 1-mbyte address range defined by the second configuration window. 0000 pci interface 1 0001 pci interface 2 0010 reserved 0011 reserved 0100 local bus controller 0101?0111 reserved 1000 configuration, control, and status registers 1001?1110 reserved 1111 local memory ?ddr sdram and on-chip sram 12?31 ? write reserved, read = 0 01 1112 31 r en 00000000000 boot_page w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x020 table 4-7. altcar bit settings (continued) bits name description 4 datasheet u .com
reset, clocking, and initialization MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 4-8 freescale semiconductor table 4-8 describes bptr bit settings. 4.3.2 boot sequencer the boot sequencer is a dma engine that accesses a serial rom on the i 2 c interface and writes data to ccsr memory or the memory space pointed to by th e alternate configuration base address register (altcbar). see section 4.3.1.2, ?accessing altern ate configuration space.? the boot sequencer is enabled by reset c onfiguration pins as described in section 4.4.3.6, ?boot seque ncer configuration.? if the boot sequencer is enabled, the e500 core is held in reset until th e boot sequencer has completed its operation. for more details, see section 11.4.5, ?boot sequencer mode.? 4.4 functional description this section describes the various ways to reset the MPC8555E device, the po r configurations, and the clocking on the MPC8555E. 4.4.1 reset operations the MPC8555E has reset input signals for hard and soft reset operation. 4.4.1.1 soft reset assertion of the sreset signal causes the cpm to go through its soft reset sequence. in addition, assertion of sreset causes a machine check interrupt to the e 500 core. when this occurs, the soft reset flag is recorded in the machine check summary regist er (mcpsumr) in the global utilities block so that software can identify the machine ch eck as a soft reset condition. see the powerpc? e500 core family reference manual for more information on the machine check interrupt, and section 18.4.1.13, ?machine check summary register (mcpsumr),? for more information on the setti ng of the soft reset flag. note that if sreset is asserted before th e e500 core is co nfigured to handl e a machine check interrupt, a core checkstop condition occurs, which causes ckstp_out to assert. 4.4.1.2 hard reset the MPC8555E can be completely re set by the assertio n of the hreset input. the assertion of this signal by external logic is the equivalent of a por and causes the sequence of events described in section 4.4.2, ?power-on reset sequence.? table 4-8. bptr bit settings bits name description 0 en boot page translation enable 0 boot page is not translated 1 boot page is translated as defined in the bptr[boot_page] parameter 1?11 ? write reserved, read = 0 12?31 boot_page translation for boot page. if enabled, the high order 20 bits of accesses to 0xffff_f nnn are replaced with this value. 4 datasheet u .com
reset, clocking, and initialization MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 4-9 refer to the MPC8555E powerquicc? iii integrated processor hardware specifications for the timing requirements for hreset assertion and negation. the MPC8555E hard reset reques t output signal (hreset_req ) indicates to external logic that a hard reset is being requested by hardware. hardware causes this signal to assert for a boot sequencer failure (see section 11.4.5, ?boot sequencer mode,? and section 11.4.5.2, ?eeprom data format,? ) or when the e500 watchdog timer is configured to cause a reset request when it expires. 4.4.2 power-on reset sequence the por sequence for the MPC8555E is as follows: 1. power is applied to meet the specifications in the MPC8555E powerquicc? iii integrated processor hardware specifications . 2. system asserts hreset and trst causing all registers to be initialized to their default states and most i/o drivers to be three-stated (some cloc k, clock enabled, and system control signals are active). 3. system applies a stable sysclk signal and stable pll configurat ion inputs, and the device pll begins locking to sysclk. 4. system negates hreset after its required hold time and afte r por configuration inputs have been valid for at least 4 sysclk cycles. note if the jtag signals ar e not used, then trst may be tied active; however, it is recommended that trst not remain asserted after the negation of hreset . trst may be connected directly to hreset . there is no need to assert the sreset signal when hreset is asserted. if sreset is asserted on negation of hreset , the por sequence will be paused after the e500 core pll is locked and before the e500 reset is negated. the por sequence will be resumed when s reset is negated. 5. MPC8555E enables i/o drivers. 6. the MPC8555E pci interface can assert devsel in response to configuration cycles. 7. the cpm reset signals (cpm_por_reset, cpm_hres et, and cpm_sreset) are asserted, and the e500 and cpm pll configuration inputs are applied, allowing the e500 a nd cpm plls to begin locking to the device clock (the ccb clock). 8. the ccb clock is cycled for approximately 50 s to lock the e500 pll and the cpm pll. 9. the internal hard reset to the e500 core is negate d and soft resets are nega ted to the dll and other remaining i/o blocks. the dll begins to lock. 10. when dll locking is completed, the boot sequencer is released, causing it to load configuration data from serial roms, if enabled, as described in section 4.4.3.6, ?boot sequencer configuration.? 4 datasheet u .com
reset, clocking, and initialization MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 4-10 freescale semiconductor 11. when the boot sequencer complete s, the pci interface is released to accept external requests, and the boot vector fetch by the e500 core is allowed to proceed unless processo r booting is further held off by por configuration inputs as described in section 4.4.3.5, ?cpu boot configuration.? the MPC8555E is now in its ready state. 12. the asleep signal negates synchronized to a ri sing edge of sysclk, indi cating the ready state. the ready state is also indicated by the asse rtion of ready/trig_out if tosr[sel] = 000. in this case, ready is asserted with the same rising edge of sysclk, to indica te that the device has reached its ready state. see section 20.3.4.1, ?trigger out source register (tosr),? for more information on this register. asserting ready allows external system monitors to know basi c device status. for example, exactly when it emerges from rese t, or if the device is in a lo w-power mode. for more information on the debug functions of trig_out, see section 20.3.4, ?trigger out function.? for more information about power management states, see section 18.4.1, ?register descriptions.? figure 4-5 shows a timing diagram of the por sequence. figure 4-5. power-on reset sequence sysclk hreset treset sreset (high impedance) hreset_req por configs pll configs ready 1 asleep (high impedance) (high impedance) 1 multiplexed with trig_out. 4 datasheet u .com
reset, clocking, and initialization MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 4-11 4.4.3 power-on reset configuration various device functions are initialized by sampli ng certain signals during the assertion of hreset . the values of all these signals are sa mpled into registers while hreset is asserted. these inputs are to be pulled high or low by external resistors. during hreset , all other signal driver s connected to these signals must be in the high-impedance state. all por configuration signals have in ternal pull-up resistors so that if the desired setting is high, there is no need for a pull-up resistor on the board. this section describes the functions and modes configured by por configuration si gnals. note that many reset configuration settings are accessible to soft ware through the following read-only memory-mapped registers described in chapter 18, ?global utilities? : ? por pll status register (porpllsr) ? por boot mode status register (porbmsr) ? por i/o impedance status a nd control register (porimpscr) ? por device status register (pordevsr) ? por debug mode status register (pordbgmsr) ? general-purpose por configuration regist er (gpporcr)?reports th e value on lad[0:31] during por (can be used to ex ternal system configuration) note in the following tables, the binary value 0b0 represents a signal pulled down to gnd and a value of 0b1 repr esents a signal pulled up to v dd , regardless of the sense of the functional signal name on the signal. 4.4.3.1 system pll ratio the system pll inputs, shown in table 4-9 , establish the clock ratio between the pci_clk/sysclk input and the platform clock used by the MPC8555E. the platform clock, also called the ccb clock, drives the l2 cache, the ddr sdram data rate, and the e500 core complex bus (ccb). there is no default value for this pll ratio; these signals must be pulled to the desired valu es. note that the values latched on these signals during por are accessible in the porpllsr (por pll status register), as described in section 18.4.1.1, ?por pll status register (porpllsr).? 4 datasheet u .com
reset, clocking, and initialization MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 4-12 freescale semiconductor 4.4.3.2 e500 core pll ratio table 4-10 describes the e500 core clock pll inputs that program the core pll and establish the ratio between the e500 core clock and the e500 core comple x bus (ccb) clock. there is no default value for this pll ratio; these signals must be pulled to the desired values. note that the values latched on these signals during por are accessible through the memory-mapped porpllsr, as described in section 18.4.1.1, ?por pll status register (porpllsr),? and also in the e500 core hid1 register, as described in section 6.10.2, ?hardware implementati on-dependent register 1 (hid1).? 4.4.3.3 boot rom location the first instruction executed by the e500 core is always address 0xffff_fffc, which must be a branch to an address within the 4-kbyt e boot page. the MPC8555E defines th e default boot rom address range table 4-9. ccb clock pll ratio functional signals reset configuration name value (binary) ccb clock : sysclk ratio la[28:31] no default cfg_sys_pll[0:3] 0000 16 : 1 0001 reserved 0010 2 : 1 0011 3 : 1 0100 4 : 1 0101 5 : 1 0110 6 : 1 0111 reserved 1000 8 : 1 1001 9 : 1 1010 10 : 1 1011 reserved 1100 12 : 1 1101 reserved 1110 reserved 1111 reserved table 4-10. e500 core clock pll ratios functional signals reset configuration name value (binary) e500 core: ccb clock ratio lale, lgpl2 no default cfg_core_pll[0:1] 00 2 : 1 01 5 : 2 (2.5:1) 10 3 : 1 11 7 : 2 (3.5:1) 4 datasheet u .com
reset, clocking, and initialization MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 4-13 to be 8 mbytes at address 0xff80_0000 to 0xffff_ffff . however, which on-chip peripheral handles these boot rom accesses can be selected at power up. the boot rom location inputs, shown in table 4-11 , establish the location of boot rom. accesses to the boot vector and the default boot rom region of the local address map ar e directed to the interface specified by these inputs. note that the values latched on these signals during por are accessible through the memory-mapped porbmsr (por boot mode stat us register) described in section 18.4.1.2, ?por boot mode status register (porbmsr).? see section 2.1, ?local memory map overview and example,? for an example memory map that relies on the default boot ro m values. also, see section 4.3.1.3.1, ?boot page tran slation register (bptr),? for information on translation of the boot page. if en abled, this translation only affects cpu accesses to 0xffff_f nnn . 4.4.3.4 host/agent configuration the host/agent reset confi guration inputs, shown in table 4-12 , configure the MPC8555E to act as a host or as an agent of a master on another interface. in host mode, the MPC8555E is immediately enabled to master transactions to the pci interfaces. if the mp c8555e is an agent on the pci1 interface, then the MPC8555E is disabled from mastering transactions on that interface until the external host enables it to do so. the external host does this by setting the control registers of th e MPC8555E interfaces appropriately. see detail s in the pci programming models described in chapter 16, ?pci bus interface.? note that the values latched on these signals during por are accessible through the memory-mapped porbmsr (por boot mode stat us register) described in section 18.4.1.2, ?por boot mode status register (porbmsr).? table 4-11. boot rom location functional signals reset configuration name value (binary) meaning lgpl0, lgpl1, lwe [3] default (111) cfg_rom_loc[0:2] 000 pci 1 001 ddr sdram 010 pci 2 011 reserved 100 reserved 101 local bus gpcm?8-bit rom 110 local bus gpcm?16-bit rom 111 local bus gpcm?32-bit rom (default) 4 datasheet u .com
reset, clocking, and initialization MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 4-14 freescale semiconductor note the MPC8555E is always a host on pc i2. if the MPC8555E is an agent on pci1, and the cpu is not in ho ldoff mode (as described in section 4.4.3.5, ?cpu boot configuration? ), the boot rom should not be located on pci1 where the external host exists, becau se the MPC8555E is not initially enabled to master reads onto that interface. 4.4.3.5 cpu boot configuration the cpu boot configuration input, shown in table 4-13 , specifies the boot configuration mode. if la27 is sampled low at reset, the e500 core is prevente d from fetching boot code until configuration by an external master is complete. the external master frees the cpu to boot by setting eebpcr[cpu_en] in the ecm ccb port configurati on register (eebpcr). see section 8.2.1.2, ?ecm ccb port configuration register (eebpcr),? for more information. note that the values latched on these signals during por are accessible through the memory-mapped porbmsr (por boot mode stat us register) described in section 18.4.1.2, ?por boot mode status register (porbmsr).? 4.4.3.6 boot sequencer configuration the boot sequencer configuration options, shown in table 4-14 , allow the boot sequencer to load configuration data from the serial rom located on the i 2 c port before the host tries to configure the MPC8555E. these options also specify normal or extended i 2 c addressing modes. see section 11.4.5, ?boot sequencer mode,? for more information on the boot sequencer. note that the values latched on these signals during por are accessible through the memory-mapped porbmsr (por boot mode stat us register) described in section 18.4.1.2, ?por boot mode status register (porbmsr).? table 4-12. host/agent configuration functional signals reset configuration name value (binary) meaning lwe [2] default (1) cfg_host_agt 0 MPC8555E acts as an agent on pci1 1 MPC8555E acts as a host on pci1 table 4-13. cpu boot configuration functional signal reset configuration name value (binary) meaning la27 default (1) cfg_cpu_boot 0 cpu boot hold-off mode. the e500 core is prevented from booting until configured by an external master. 1 the e500 core is allowed to boot without waiting for configuration by an external master (default). 4 datasheet u .com
reset, clocking, and initialization MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 4-15 note when the boot sequencer is enabled, the pr ocessor core will be held in reset and thus prevented from fetching boot code until the boot sequencer has completed its task, regardless of the state of the cpu boot configuration signal described in section 4.4.3.5, ?cpu boot configuration.? 4.4.3.7 tsec width the tsec width input, shown in table 4-15 , selects standard versus re duced width for both of the three-speed ethernet controller interfaces. note th at the value latched on this signal during por is accessible through the memory-mapped pordevsr (p or device status re gister) described in section 18.4.1.4, ?por device stat us register (pordevsr).? note while the width of both in terfaces is controlled by this single configuration input, the protocol (tbi or gmii) used by each is separate ly controlled with other configuration inputs described in section 4.4.3.8, ?tsec1 protocol,? and section 4.4.3.9, ?tsec2 protocol.? 4.4.3.8 tsec1 protocol the tsec1 protocol input, shown in table 4-16 , selects the protocol (gmi i or tbi) used by the tsec1 controller. note that the value latched on this si gnal during por is accessibl e through the memory-mapped table 4-14. boot sequencer configuration functional signals reset configuration name value (binary) meaning lgpl3, lgpl5 default (11) cfg_boot_seq[0:1] 00 reserved 01 normal i 2 c addressing mode is used. boot sequencer is enabled and loads configuration information from a rom on the i 2 c interface. a valid rom must be present. 10 extended i 2 c addressing mode is used. boot sequencer is enabled and loads configuration information from a rom on the i 2 c interface. a valid rom must be present. 11 boot sequencer is disabled. no i 2 c rom is accessed (default). table 4-15. tsec width configuration functional signal reset configuration name value (binary) meaning ec_mdc default (1) cfg_tsec_reduce 0 ethernet interfaces operate in reduced mode, either rtbi or rgmii, using only four transmit data signals and four receive data signals. 1 ethernet interfaces operate in their standard tbi or gmii modes using eight transmit data signals and eight receive data signals (default). 4 datasheet u .com
reset, clocking, and initialization MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 4-16 freescale semiconductor pordevsr (por device status register) described in section 18.4.1.4, ?por device status register (pordevsr).? 4.4.3.9 tsec2 protocol the tsec2 protocol input, shown in table 4-17 , selects the protocol (gmi i or tbi) used by the tsec2 controller. note that the value latched on this si gnal during por is accessibl e through the memory-mapped pordevsr (por device status register) described in section 18.4.1.4, ?por device status register (pordevsr).? 4.4.3.10 pci clock selection the pci clock source inputs, shown in table 4-18 and table 4-19 specify the clock mode (synchronous or asynchronous) for the pci1 a nd pci2 inte rfaces. see section 4.4.4.1, ?system cl ock and pci clocks,? for more information. note that the value latched on this signal during por is accessible through the memory-mapped pordevsr (por devi ce status register) described in section 18.4.1.1, ?por pll status register (porpllsr).? table 4-16. tsec1 protocol configuration functional signal reset configuration name value (binary) meaning tsec2_txd3 default (1) cfg_tsec1 0 the tsec1 controller operates using the gmii protocol (or rgmii if configured in reduced mode as described in section 4.4.3.7, ?tsec width.? ) 1 the tsec1 controller operates using the tbi protocol (or rtbi if configured in reduced mode as described in section 4.4.3.7, ?tsec width,? ) (default). table 4-17. tsec2 protocol configuration functional signal reset configuration name value (binary) meaning tsec2_txd2 default (1) cfg_tsec2 0 the tsec2 controller operates using the gmii protocol (or rgmii if configured in reduced mode as described in section 4.4.3.7, ?tsec width.? ) 1 the tsec2 controller operates using the tbi protocol (or rtbi if configured in reduced mode as described in section 4.4.3.7, ?tsec width,? ) (default). table 4-18. pci1 clock select functional signals reset configuration name value (binary) meaning tsec2_txd1 default (1) cfg_pci1_clk 0 asynchronous mode. pci1_clk is used as the clock for the pci1 interface 1 synchronous mode. sysclk is used as the clock for the pci1 interface (default) 4 datasheet u .com
reset, clocking, and initialization MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 4-17 4.4.3.11 pci width configuration the pci width configuration input, shown in table 4-20 , configures the pci1 interface to 32- or 64-bit operation. note that the value latched on this si gnal during por is accessi ble through the pordevsr described in section 18.4.1.4, ?por device stat us register (pordevsr).? note also that the pci1_req64_b signal used for this configuration input is physically the same pin as pci2_frame_b, but if the second pci port is to be used, then there is no need to configure the width si nce the default 32-bit interface must be used. 4.4.3.12 pci i/o impedance the pci i/o impedanc e inputs, shown in table 4-21 and table 4-22 , select the impeda nce of the pci i/o drivers. note that the values latched on these si gnals during por are accessi ble through porimpscr, described in section 18.4.1.3, ?por i/o impedance status and control register (porimpscr).? note that if a 64-bit pci interfac e is configured, the user is responsible to ensure that both the upper and lower 32 bits possess the same i/ o impedance configuration. table 4-19. pci2 clock select functional signals reset configuration name value (binary) meaning tsec2_txd0 default (1) cfg_pci2_clk 0 asynchronous mode. pci2_clk is used as the clock for the pci2 interface 1 synchronous mode. sysclk is used as the clock for the pci2 interface (default) table 4-20. pci-32 configuration functional signal reset configuration name value (binary) meaning pci2_frame cfg_pci1_width 0 the pci interface operates as a 64-bit interface. default (1) 1 the pci interface operates as two 32-bit interfaces (default). table 4-21. pci1 i/o impedance functional signal reset configuration name value (binary) meaning pci1_gnt 1 cfg_pci1_impd 0 25- i/o drivers are used on the pci1 interface (applies to the lower 32 bits if 64-bit pci is used) default (1) 1 42- i/o drivers are used on the pci1 interface (applies to the lower 32 bits if 64-bit pci is used) (default) 4 datasheet u .com
reset, clocking, and initialization MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 4-18 freescale semiconductor 4.4.3.13 pci arbiter configuration the pci arbiter configuration inputs, shown in table 4-23 and table 4-24 , enable the on-chip pci arbiters. note that the value latched on th ese signals during por is accessible through th e pordevsr described in section 18.4.1.4, ?por device status register (pordevsr).? 4.4.3.14 pci debug configuration the pci debug configuration input, shown in table 4-25 , enables pci debug mode for the pci1 interface only. in this mode, source id in formation is driven onto the highest order address bits pci1_ad[62:58] during the bus command phase. note that this debug function is only av ailable on pci1 and only when it is being used as a 64-bit pci interface. the value latched on this signal duri ng por is accessible through the pordbgmsr described in section 18.4.1.5, ?por debug mode stat us register (pordbgmsr).? table 4-22. pci2 i/o impedance functional signal reset configuration name value (binary) meaning pci2_gnt 1 cfg_pci2_impd 0 25- i/o drivers are used on the pci2 interface (applies to the upper 32 bits if 64-bit pci is used) default (1) 1 42- i/o drivers are used on the pci2 interface (default) table 4-23. pci1 arbiter configuration functional signal reset configuration name value (binary) meaning pci1_gnt 2 cfg_pci1_arbiter 0 the on-chip pci arbiter is disabled for the pci1 interface. external arbitration is required. default (1) 1 the on-chip pci arbiter is enabled for the pci1 interface (default). table 4-24. pci2 arbiter configuration functional signal reset configuration name value (binary) meaning pci2_gnt 2 cfg_pci2_arbiter 0 the on-chip pci arbiter is disabled for the pci2 interface. external arbitration is required. default (1) 1 the on-chip pci arbiter is enabled for the pci2 interface (default). table 4-25. pci debug configuration functional signal reset configuration name value (binary) meaning pci1_gnt 3 default (1) cfg_pci_debug 0 pci debug is enabled. source id information is driven onto the highest order address bits, pci1_ad[62:58 ], during the bus command phase. 1 pci operates in normal mode (default). 4 datasheet u .com
reset, clocking, and initialization MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 4-19 4.4.3.15 memory debug configuration the memory debug configur ation input, shown in table 4-26 , selects which debug outputs (ddr or lbc memory controller) are driven onto the msrcid and mdval debug signals. note that the value latched on this signal during por is acc essible through the memory-mappe d pordbgmsr (por debug mode register) described in section 18.4.1.5, ?por debug mode stat us register (pordbgmsr).? 4.4.3.16 ddr debug configuration the ddr debug configuration input, shown in table 4-27 , enables a ddr memory controller debug mode in which the ddr sdram source id field and data valid strobe are driven onto the ecc pins. ecc checking and generation are disabled in this case. ecc signals driven from the sdrams must be electrically disconnected from the ecc i/o pins of the MPC8555E in this mode. note that the value latched on this signal during po r is accessible through the memory-mapped pordbgmsr (por debug mode register) described in section 18.4.1.5, ?por debug mode stat us register (pordbgmsr).? 4.4.3.17 pci output hold configuration the pci output hold configuration i nputs configure the output hold times for the pci output drivers. the default value will meet the hold ti mes required by the specification. hold times are adjusted for heavily loaded buses by removing the buffer delays. refer to the MPC8555E powerquicc? iii integrated processor hardware specifications for specific timing information. table 4-28 shows the hold time configuration for the pci1 interface, and table 4-29 shows the hold time configuration for the pci2 interface. note that if a 64-bit pci interface is configured, the user is responsible to ensure that both the upper and lower 32-bits possess the same output hold configuration. table 4-26. memory debug configuration functional signal reset configuration name value (binary) meaning msrcid0 default (1) cfg_mem_debug 0 debug information from the lo cal bus controller (lbc) is driven on the msrcid and mdval signals. 1 debug information from the ddr s dram controller is driven on the msrcid and mdval signals (default). table 4-27. ddr debug configuration functional signal reset configuration name value (binary) meaning msrcid1 default (1) cfg_ddr_debug 0 debug information is driven on the ecc pins instead of normal ecc i/o. ecc signals from memory devices must be disconnected. 1 debug information is not driven on ecc pins. ecc pins function in their normal mode (default). 4 datasheet u .com
reset, clocking, and initialization MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 4-20 freescale semiconductor 4.4.3.18 local bus output hold configuration the lbc output hold configuration inputs, shown in table 4-30 , configure the output hold times for the local bus interface output drivers. hold times are adjusted by adding buffe r delays to the intrinsic delay of the output driver. the default values were selected for historical purposes . it is expected that designs done with the MPC8555E can use zero a dded buffer delays. refer to the MPC8555E powerquicc? iii integrated processor hardware specifications for specific timing information. 4.4.3.19 general-purpose por configuration the lbc address/data bus inputs, shown in table 4-31 , configure the value of the general-purpose por configuration register defined in section 18.4.1.6, ?general-purpose po r configuration register (gpporcr).? this register is intended to facilitate por configuration of user systems. a value placed on lad[0:31] during por is captured a nd stored (read only) in the gppo rcr. software can then use this value to inform the operating system about initial system configuration. typical interpretations include circuit board type, board id number, or a list of available peripherals. table 4-28. pci1 output hold configuration functional signals reset configuration name value (binary) meaning pci1_gnt4 default (1) cfg_pci1_hold_en 1 tw o added buffer delays?re quired to meet 2-ns hol d time requirement. (applies to the lower 32 bits if 64-bit pci is used.) 0 zero added buffer delays?for heavily loaded systems. (applies to the lower 32 bits if 64-bit pci is used.) table 4-29. pci2 output hold configuration functional signals reset configuration name value (binary) meaning pci2_gnt4 default (1) cfg_pci2_hold_en 1 tw o added buffer delays?re quired to meet 2-ns hol d time requirement. (applies to upper 32 bits if 64-bit pci is used.) 0 zero added buffer delays?for heavily loaded systems. (applies to upper 32 bits if 64-bit pci is used.) table 4-30. local bus output hold configuration functional signals reset configuration name value (binary) meaning lwe [0:1] default (11) cfg_lb_hold[0:1] 11 one added buffer delay (default) (zero added buffer delays for lale) 10 two added buffer delays (default + 1) (one added buffer delay for lale) 01 three added buffer delays (default + 2) (one added buffer delay for lale) 00 zero added buffer delays (zero added buffer delays for lale) 4 datasheet u .com
reset, clocking, and initialization MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 4-21 4.4.4 clocking the following paragraphs describe th e clocking within the MPC8555E device. 4.4.4.1 system clock and pci clocks the MPC8555E takes uses the sysclk input as the clock source for the e500 core and all of the devices and interfaces that opera te synchronously with the core. as shown in figure 4-6 , the sysclk input (frequency) is multiplied up using a phase lock loop (pll) to create the core complex bus (ccb) clock (also called the platform clock). the ccb clock is us ed by virtually all of the synchronous system logic, including the l2 cache, and other inte rnal blocks such as the dma and interrupt controller. the ccb clock also feeds the pll in the e500 core and the dll that creates clocks for the local bus memory controller. the pci interfaces may be run such that the sysclk is the pci clock. this is the default configuration and is called synchronous mode. howe ver each pci interface can be confi gured to use a separate pci clock input that may be completely unrel ated to the sysclk input; this is called asynchronous mode. note that the divide-by-two ccb clock divider and the divide-by- n ccb clock divider, shown in figure 4-6 , are located in the ddr and loca l bus blocks, respectively. table 4-31. general-purpose por configuration functional signals reset configuration name value (binary) meaning lad[0:31] no default cfg_gpporcr xx general-purpose por config uration vector to be placed in gpporcr 4 datasheet u .com
reset, clocking, and initialization MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 4-22 freescale semiconductor figure 4-6. MPC8555E clock subsystem block diagram 4.4.4.2 ethernet clocks the ethernet blocks operate asynchronously with respect to the rest of the device . these blocks use receive and transmit clocks supplied by their respect ive phy chips, plus a 125-mhz clock input (ec_gtx_clk125) for gigabit protocols. data transf ers are synchronized to the ccb clock internally. 4.4.4.3 real time clock as shown in figure 4-7 , the real time clock (rtc) input can optionally be used to clock the e500 core timer facilities. rtc can also be used (optionally) by the MPC8555E program mable interrupt co ntroller (pic) core pll platform pll dll lsync_in lsync_out lclk0 lclk1 core_clk e500 core ccb_clk to rest of the device sysclk ccb_clk cfg_sys_pll[0:3] cfg_core_pll[0:1] 2 4 lbc pci1 pll pci2 pll pci 2 pci 1 pci1_clk cfg_pci1_clk cfg_pci2_clk pci2_clk 2 n dram mck[0:5] mck [0:5] 6 6 ddr controller clock control 4 datasheet u .com
reset, clocking, and initialization MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 4-23 global timer facili ties. the rtc is separate from the e500 core clock and is intended to support relatively low frequency timing applications. the rt c frequency range is specified in the MPC8555E powerquicc? iii integrated processor hardware specifications , but the maximum value should not exceed 1/4th of the ccb frequency. before being distributed to the core time base, rtc is sampled and synchronized with the ccb clock. the clock source for the core time base is specified by two fields in hid0: time base enable (tben), and select time base clock (sel_tbclk) . if the time base is enabled, (h id0[tben] is set), the clock source is determined as follows: ? hid0[sel_tbclk] = 0, the time ba se is updated every 8 ccb clocks ? hid0[sel_tbclk] = 1, the time base is updated on the rising edge of rtc the default source of the time base is the ccb clock divided by eight. for more details, see the powerpc? e500 core family reference manual. section 10.3.2.6, ?timer control register (tcr),? provides additional inform ation on the use of the rtc signal to clock the global timers in the pic unit. figure 4-7. rtc and core timer facilities clocking options rtc (sampled and synchronized) hid0 tben sel_tbclk core time base (incrementer) decrementer event 63 decar 32 auto-reload 63 32 63 32 (decrementer) watchdog timer events based on one of the 64 tb bits selected by concatenating tcr[wpext] with the eis-defined tcr[wp] (wpext||wp). fixed-interval timer events based on one of the 64 tb bits selected by concatenating tcr[fpext] with the eis-defined tcr[fp] (fpext||fp). dec tbu tbl core timer e500 core 8 ccb clock ? ? ? ? ? ? note: the logic circuits shown depict functional relationships only; they do not represent physical implementation details. (0 ? 1 detect) facilities clock 4 datasheet u .com
reset, clocking, and initialization MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 4-24 freescale semiconductor 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor ii-1 part ii e500 core complex and l2 cache this part describes the many features of the mpc 8555e core processor at an overview level and the interaction between the core complex and the l2 cache. the following chapters are included: ? chapter 5, ?core complex overview,? provides an overview of the e500 core processor and the l1 caches and mmu that, together with the core, comprise the core complex. ? chapter 6, ?core register summary,? provides a listing of the e500 registers in reference form. ? chapter 7, ?l2 look-aside cache/sram,? describes the l2 cache of the MPC8555E. note that the l2 cache can also be addresse d directly as memory-mapped sram. the e500 processor core is a low-po wer implementation of the family of reduced instruc tion set computing (risc) embedded processors that implement the em bedded category features of the power architecture technology. this part provides additiona l information about the architecture as it relates spec ifically to the e500 core complex and specific detail s on how its registers are accessed. the e500 core complex interacts with the l2 cache through the core complex bus (ccb). 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 ii-2 freescale semiconductor 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 5-1 chapter 5 core complex overview this chapter provides an overview of the e500 mi croprocessor core as it is implemented on the MPC8555E. this chapter includes the following: ? an overview of architecture features as implemented in this core a nd a summary of the core feature set ? a summary of the instruction pipeline and flow ? an overview of the programming model ? an overview of interrupts and exception handling ? a description of the memo ry management architecture ? high-level details of the e500 co re memory and coherency model ? a brief description of the core complex bus (ccb) ? a summary of the power architecture embedded category compatibility a nd migration from the original version of the powerpc ar chitecture as it is de fined by apple, ibm, a nd motorola (referred to as the aim version of the powerpc architecture) specific details about the e500 are provided in the powerpc? e500 core family reference manual (freescale document id no. e500cor erm). the e500 core provi des features that the integrated device may not implement or may implem ent in a more specific way. 5.1 overview the e500 processor core is a low-po wer implementation of the family of reduced instruc tion set computing (risc) embedded processors that implement the em bedded category features of the power architecture technology. the e500 is a 32-bit implementation us ing the lower words in the 64-bit general-purpose registers (gprs). figure 5-1 is a block diagram of the processor core comp lex that shows how the functional units operate independently and in parallel. note that this conc eptual diagram does not attempt to show how these features are physic ally implemented. 4 datasheet u .com
core complex overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 5-2 freescale semiconductor figure 5-1. e500 core complex block diagram reservation station reservation station reservation station additional features ? time base counter/decrementer ? clock multiplier ? jtag/cop interface ? power management ? performance monitor fetch stages branch prediction unit btb 512-entry ctr lr instruction unit instruction queue (12 instructions) program order is maintained by passing instructions reservation branch unit gpr file completion queue (14-entry) load/store unit 32-/ 64-bit l2 mmus 256-entry tlb array 16-entry condition cr field 128-bit general issue queue (giq) branch issue queue (biq) (tlb0) tlb array (tlb1) register unified l1 data mmu 64-entry d-l1tlb4k 4-entry d-l1vsp two instruction dispatch (1 biq, 2 giq) core interface unit l1 instruction mmu 64-entry i-l1tlb4k 4-entry i-l1vsp 32-kbyte i cache station reservation station simple unit 1 (32-/64-bit) simple unit 2 (32-bit) multiple unit (64-/32-bit) (64-/32-bit) memory unit (4 instructions) ta g s ta g s 32-kbyte d cache maximum mas registers two instructions retire per cycle from the iq to the cq at dispatch. load data line fill buffer data write buffer instruction line rename buffers (14) fill buffer rename buffers (14) gpr completion bus operand bus crf bus two instruction issue to giq per clock one instruction issue to biq per clock l1 store queue miss queue core complex bus each execution unit can accept one instruction per cycle. 4 datasheet u .com
core complex overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 5-3 the power architecture technology defines categories that extend the architecture that can perform computational or syst em management functions. one of these on the e500 is the signal processing engine (spe), which includes a suite of vect or instructions that us e the upper and lower halves of the gprs as a single two-element operand. so me extensions are defined by freescale?s embedded category implementation standards (eis). 5.1.1 upward compatibility the e500 provides 32-bit effective addr esses and integer data types of 8, 16, and 32 b its, as defined by the architecture. it also provides two-element, 64- bit data types for the spe and embedded vector floating-point instructions, which in clude instructions that operate on operands comprised of two 32-bit elements. the embedded single-precisi on scalar floating-point in structions use 32-bit singl e-precision instructions. note the spe (which includes embedded floating-point functionality) is implemented in all power quicc iii devices. howeve r, these instructions will not be supported in devices subs equent to powerquicc iii. freescale semiconductor strongly recommends that use of these instructions be confined to libraries and device drivers. customer software that uses spe or embedded floating-poin t instructions at the assembly level or that uses spe intrinsics will require rewriti ng for upward compatibility with next-generation powerquicc devices. freescale semiconductor offers a li bcfsl_e500 library that uses spe instructions. freescale will also provide libraries to support next-generation powerquicc devices. 5.1.2 core complex summary the core complex is a superscalar processor that can issue two instructions and complete two instructions per clock cycle. instructions complete in order, but can execute out of or der. execution results are available to subsequent instructions through the rename buffe rs, but those results are recorded into architected registers in program order, maintain ing a precise exception mode l. all arithmetic inst ructions that execute in the core operate on data in the gprs. alt hough the gprs are 64 bits wide, only spe, dpfp (e500v2 only), and embedded vector floating-point instructions operate on the upper word of the gprs; the upper 32 bits are not affected by other 32-bit instructions. the processor core integrates two simple instructi on units (su1, su2), a multip le-cycle instruction unit (mu), a branch unit (bu), and a load/store unit (lsu). the lsu and su2 support 64- and 32-bit instructions. the ability to execute five instructions in parallel a nd the use of simple instructions with short execution times yield high efficiency and throughput . most integer instructions execute in 1 clock cycle. a series of independent vector floating- point add instructions can be issued and completed with a throughput of one instruction per cycle. 4 datasheet u .com
core complex overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 5-4 freescale semiconductor the core complex includes independent on-chip, 32- kbyte, eight-way set-associative, physically addressed caches for instructions and data. it also incl udes on-chip first-level in struction and data memory management units (mmus) and an on-chip second-le vel unified mmu. ? the first-level mmus contain two four-entry, fu lly-associative instructi on and data translation lookaside buffer (tlb) arrays that provide s upport for demand-paged virtual memory address translation and variable-sized pages. they al so contain two 64-entry, 4-way set-associative instruction and data tlb arrays that support 4-kbyte pages. these arrays are maintained entirely by the hardware with a true leas t-recently-used (lru) algorithm. the second-level mmu cont ains a 16-entry, fully-associative unified (instruction and data) tlb array that provides support for vari able-sized pages. it also cont ains a unified tlb for 4-kbyte page size support the core complex allows cache-line-bas ed user-mode locks on the contents in either th e instruction or data cache. this provides embedded applic ations with the capability for lo cking interrupt routines or other important (time-sensitive) in struction sequences into the instruction cache. it also allows data to be locked into the data cache, which supports deterministic execution time. the core complex supports a high-sp eed on-chip internal bus with data tagging called the core complex bus (ccb). the ccb has two general- purpose read data buses, one write da ta bus, data parity bits, data tag bits, an address bus, and address attribute bits. the processor core complex supports out-of-order reads, in-order writes, and one level of pi pelining for addresses w ith address-retry responses . it can also support single-beat and burst data transfers for memo ry accesses and memory-mapped i/o operations. 5.2 e500 processor and system version numbers table 5-1 lists the revision codes in the processor version register (pvr) and the sy stem version register (svr). these registers can be accessed as sprs through the e500 core (see section 6.5.3, ?processor version register (pvr),? and section 6.5.4, ?system version register (svr)? ) or as memory-mapped registers defined by the integrated device (see ? section 18.4.1.14, ?processor version register (pvr),? and section 18.4.1.15, ?system version register (svr)? ). table 5-1. device revision level cross-reference MPC8555E/ mpc8541e revision core revision processor version register (pvr) system version register (svr) 1.1 2.0 0x8020_0020 0x8079-0011 (MPC8555E) 0x8071-0011 (mpc8555) 0x807a-0011 (mpc8541e) 0x8072-0011 (mpc8541) 4 datasheet u .com
core complex overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 5-5 5.3 features key features of the e500 ar e summarized as follows: ? 32-bit architecture ? additional categories (formerl y referred to as apus) branch target buffer (btb) locki ng is specific to the e500. btb lo cking gives the us er the ability to lock, unlock, and invalidate btb entr ies; further informat ion is provided in table 5-5. the eis (see eref: a reference for freescale book e and the e500 core ) defines the following: ? integer select. this instructio n is now part of th e power architecture te chnology base category. ? performance monitor. the performance monitor facility provides the ability to monitor and count predefined events such as processor clocks, misses in the instruction cache or data cache, types of instructions decoded, or mispredicted branches. the count of such events can be used to trigger the performance monitor excepti on. additional performanc e monitor registers (pmrs) similar to sprs are used to configure and track performance m onitor operations. these registers are accessed with the move to pmr and move from pmr instructions ( mtpmr and mfpmr ). see section 5.12, ?performance monitoring.? ? cache locking. allows instructions and data to be locked into their respective caches on a cache block basis. locking is performe d by a set of touch and lock set instructions. this functionality can be enabled for user mode by setting msr[ ucle]. the feature also provides resources for detecting and handling overlocking conditions. ? machine check. the machine check interrupt is treated as a separa te level of inte rrupt. it uses its own save and restore registers (mcsrr0 and mcsrr1) and return from machine check interrupt ( rfmci ) instruction. see section 5.8, ?interrupts and exception handling.? ? single-precision embe dded scalar and vector floating- point instructions, listed in table 5-4 . ? signal processing engine (spe). note that the spe is not a sepa rate unit; spe computational and logical instructions are executed in the simp le and multiple-cycle units used by all other computational and logical instru ctions, and 64-bit load s and stores are executed in the common lsu. figure 5-1 shows how execution logic for su1, the mu, and the lsu is replicated to support operations on the upper halves of the gprs. the e500 register set is modified as follows: ? gprs are widened to 64 bits to support 64-bit load, store, and merge operations. note that the upper 32 bits are affected only by 64-bit instructions. ? a 64-bit accumulator (acc) has been added. ? the signal processing and embe dded floating-point status and control register (spefscr) provides interrupt control and status for spe and embedded floating-point instructions. these registers are shown in figure 5-6 . spe instructions are grouped as follows: ? single-cycle integer add and s ubtract with the same latencie s for spe operations as for the 32-bit equivalent ? single-cycle logical operations ? single-cycle shift and rotates ? four-cycle integer pipelined multiplies 4 datasheet u .com
core complex overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 5-6 freescale semiconductor ? 4-, 11-, 19-, and 35-cycle integer divides ?if r a or r b is zero, a floating-point divide takes 4 cycles; all other ca ses take 29 cycles. ? four-cycle simd pipelined multiply-accumulate (mac) ? 64-bit accumulator for no-stall mac operations ? 64-bit loads and stores ? 64-bit merge instructions ? cache structure?separate 32-kbyte, 32-byte line, 8-way set-associative level 1 instruction and data caches ? 1.5-cycle cache array access, 3-cycle load-to-use latency ? pseudo-lru (plru) re placement algorithm ? copy-back data cache that can function as a write-through cache on a page-by-page basis ? supports all embedded categor y memory coherency modes ? supports eis-defined cache-locki ng instructions, as listed in table 5-3 ? dual-issue superscalar control ? two-instructions-per-clock peak issue rate ? precise exception handling ? decode unit ? 12-entry instruction queue (iq) ? full hardware detection of interlocks ? decodes as many as two instructions per cycle ? decode serialization control ? register dependency resolution and renaming ? branch prediction unit (bpu) ? dynamic branch prediction using a 512-entry, 4-way set-associative branch target buffer (btb) supported by the e500 bt b instructions listed in table 5-5 . ? branch prediction is handled in the fetch stages. ? completion unit ? as many as 14 instructions allowe d in 14-entry completion queue (cq) ? in-order retirement of as many as two instructions per cycle ? completion and refetch serialization control ? synchronization for all instruction flow cha nges?interrupts, mispredicted branches, and context-synchronizing instructions ? issue queues ? two-entry branch instruction issue queue (biq) ? four-entry general instru ction issue queue (giq) ? branch unit?the branch unit (bu) is an execution uni t and is distinct from the bpu. it executes (resolves) all branch and cr logical instructions. 4 datasheet u .com
core complex overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 5-7 ? two simple units (su1 and su2) ? add and subtract ? shift and rotate ? logical operations ? support for 64-bit spe instructions in su1 ? multiple-cycle unit (mu)?the mu is shown in figure 5-2 . figure 5-2. four-stage mu pipeline, showing divide bypass the mu has the following features: ? four-cycle latency for all multiplication, in cluding spe integer and fractional multiply instructions and embedded sc alar and vector floating-poi nt multiply instructions ? variable-latency divide: 4, 1 1, 19, and 35 cycles for all inte ger divide inst ructions. if r a or r b is zero, floating-point divide inst ructions take 4 cycles; all othe rs take 29. note that although most divide instructions take more than 4 cy cles to execute, the mu allows subsequent multiply instructions to exec ute through all four mu stages in parallel with the divide. ? 4-cycle floating-point add and subtract ? the load/store unit (lsu) is shown in figure 5-3 . upper lower mu-3 mu-1 mu-2 divide bypass path postdivide divide reservation station from giq0 or giq1 mu-4 4 datasheet u .com
core complex overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 5-8 freescale semiconductor figure 5-3. three-stage load/store unit the lsu has the following features: ? three-cycle load latency ? fully pipelined ? load miss queue allows up to four load misses before stalling. ? load hits can continue to be serviced when the load miss queue is full. ? the seven-entry l1 store queue al lows full pipelining of stores. ? the three-entry data line fill buffer is used fo r loads and cacheable stores. stores are allocated here so loads can access data from the store immediately. ? the data write buffer contains three entries: one dedicated for snoop pushes, one dedicated for castouts, and one that can be us ed for snoop pushes or cast outs. ? cache coherency ? supports four-state cache cohe rency: modified-exclusive, ex clusive, shared, and invalid (mesi). note, however that shared state ma y not be accessible in some implementations. ? bus support for hardware-enf orced coherency (bus snooping) ? core complex bus (ccb)?internal bus ? high-speed, on-chip local bus with data tagging ? 32-bit address bus ? address protocol with addre ss pipelining and retry/copyback derived from bus used by previous generations of processo rs (referred to as the 60x bus) ? two general-purpose read data buses and one write data bus ? extended exception handling ? supports embedded cate gory interrupt model ? less than 10-cycle interrupt latency reservation station load/store unit (64-/32-bit) load data line fill buffer data write buffer l1 store queue miss queue to core interface unit to data cache to gpr operand bus to completion queue to g p r s three-stage pipeline queues and buffers 4 datasheet u .com
core complex overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 5-9 ? interrupt vector prefix register (ivpr) ? interrupt vector offset registers (ivors) 0?15 and 32?35 ? exception syndrome register (esr) ? preempting critical interrupt , including critical interrupt status registers (csrr0 and csrr1) and an rfci instruction ? a separate set of resources for machine-check interrupts ? spe unavailable exception ? floating-point data exception ? floating-point round exception ? performance monitor ? memory management unit (mmu) ? 32-bit effective address translat ed to 32-bit real a ddress (using a 41-bit in terim virtual address) ? tlb entries for variable- (4-kbyte?256-m byte) and fixed-size (4-kbyte) pages ? data l1 mmu ? 4-entry, fully-associative tlb array for variable-sized pages ? 64-entry, 4-way set-associative tlb for 4-kbyte pages ? instruction l1 mmu ? 4-entry, fully-associative tlb array for variable-sized pages ? 64-entry, 4-way set-associative tlb for 4-kbyte pages ? unified l2 mmu ? 16-entry, fully-associative tlb array for variable-sized pages ? 256-entry, 2-way set-associativ e unified (for instruction and data accesses) l2 tlb array (tlb0) supports onl y 4-kbyte pages ? software reload for tlbs ? virtual memory support for as much as 4 gbytes (2 32 ) of effective address space ? real memory support for as much as 4 gbytes (2 32 ) of physical memory ? support for big-endian and true little-endian memory on a per-page basis ? power management ? low-power design ? power-saving modes: core-halted and core-stopped ? internal clock multipliers ranging from 1 to 8 times the bus cloc k, including integer and half-mode multipliers.the MPC8555E s upports multipliers of 2, 2.5, 3, and 3.5. ? dynamic power management of ex ecution units, caches, and mmus ? nap, doze, and sleep bits in hid0 can be used to assert nap , doze , and sleep output signals to initiate power-saving modes at the integrated device level. 4 datasheet u .com
core complex overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 5-10 freescale semiconductor ? testability ? lssd scan design ? jtag interface ? esp support ? reliability and serviceability ? parity checking on caches ? parity checking on e500 local bus 5.4 instruction set the e500 implements the following instructions: ? the embedded category instruction set for 32-bit im plementations. this is composed primarily of the user-level instructions defi ned by the power architecture user instruction set architecture (uisa). the e500 does not include floating-point inst ructions that require floating-point registers (fprs), load string, or st ore string instructions. ? the e500 supports the following instructions: ? integer select. now part of the base category. consists of the integer select instruction ( isel ), which functions as an if - then-else statement that selects between two source registers by comparison to a cr bit. this instruction elimin ates conditional branches , decreases latency, and reduces the code footprint. ? performance monitor. table 5-2 lists performance m onitor instructions. ? cache locking. consists of th e instructions described in table 5-3 . ? machine check. defines the return from machine check interrupt instruction ( rfmci ). ? spe vector instructions. vector instructions are defined that vi ew the 64-bit gprs as composed of a vector of two 32-bi t elements (some instructions also re ad or write 16-bit elements). some scalar instructions produ ce a 64-bit scalar result. table 5-2. performance monitor instructions name mnemonic syntax move from performance monitor register mfpmr r d,pmrn move to performance monitor register mtpmr pmrn, r s table 5-3. cache locking instructions name mnemonic syntax data cache block lock clear dcblc ct, r a, r b data cache block touch and lock set dcbtls ct, r a, r b data cache block touch for store and lock set dcbtstls ct, r a, r b instruction cache block lock clear icblc ct, r a, r b instruction cache block touch and lock set icbtls ct, r a, r b 4 datasheet u .com
core complex overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 5-11 ? the embedded floating-point categories provide s calar and vector floati ng-point instructions. scalar single-precision floating- point instructions use only the lower 32 bits of the gprs; double-precision operands (e500v2 only) use all 64 bits. table 5-4 lists embedded floating-point instructions. ? btb locking instructions. the core complex provides a 512-entry btb fo r efficient processing of branch instructions. the btb is a branch target address cach e, organized as 128 rows with 4-way set associativity, that holds the address and target instruction of the 512 most-recently taken branches. table 5-5 lists btb instructions. table 5-4. scalar and vector embedded floating-point instructions instruction mnemonic syntax scalar vector convert floating-point from signed fraction efscfsf evfscfsf r d ,r b convert floating-point from signed integer efscfsi evfscfsi r d ,r b convert floating-point from unsigned fraction efscfuf evfscfuf r d ,r b convert floating-point from unsigned integer efscfui evfscfui r d ,r b convert floating-point to signed fraction efsctsf evfsctsf r d ,r b convert floating-point to signed integer efsctsi evfsctsi r d ,r b convert floating-point to signed integer with round toward zero efsctsiz evfsctsiz r d ,r b convert floating-point to unsigned fraction efsctuf evfsctuf r d ,r b convert floating-point to unsigned integer efsctui evfsctui r d ,r b convert floating-point to unsigned integer with round toward zero efsctuiz evfsctuiz r d ,r b floating-point absolute value efsabs evfsabs r d ,r a floating-point add efsadd evfsadd r d ,r a ,r b floating-point compare equal efscmpeq evfscmpeq cr d ,r a ,r b floating-point compare greater than efscmpgt evfscmpgt cr d ,r a ,r b floating-point compare less than efscmplt evfscmplt cr d ,r a ,r b floating-point divide efsdiv evfsdiv r d ,r a ,r b floating-point multiply efsmul evfsmul r d ,r a ,r b floating-point negate efsneg evfsneg r d ,r a floating-point negative absolute value efsnabs evfsnabs r d ,r a floating-point subtract efssub evfssub r d ,r a ,r b floating-point test equal efststeq evfststeq cr d ,r a ,r b floating-point test greater than efststgt evfststgt cr d ,r a ,r b floating-point test less than efststlt evfststlt cr d ,r a ,r b table 5-5. btb locking instructions name mnemonic syntax branch buffer load entry and lock set bblels ? branch buffer entry lock reset bbelr ? 4 datasheet u .com
core complex overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 5-12 freescale semiconductor 5.5 instruction flow the e500 core is a pipelined, supersca lar processor with parall el execution units that allow instructions to execute out of order but record their results in order. pipelining breaks instructi on processing into discrete stages, so multiple instructions in an instruction sequence can occ upy the successive stages: as an instruction completes one stage, it passes to the next, leaving the previous stage available to a subsequent instruction. so, even though it may take multiple cycles for an instruction to pass through all of the pipeline stages, once a pipeline is full , instruction throughput is much shorter than the latency. a superscalar processor is one that issues multiple independent instructions in to separate execution units, allowing parallel execution. the e500 core has five ex ecution units, one each for branch (bu), load/store (lsu), and multiple-cycle operations (mu), and two for simple arithmet ic operations (su1 and su2). the mu and su1 arithmetic execution units also execute 64-bit spe vector instructions, using both the lower and upper halves of the 64-bit gprs. the parallel execution units allow mu ltiple instructions to execute in parallel and out of order. for example, a low-latency addition instruct ion that is issued to an su after an integer divide is issued to the mu should finish executing before th e higher latency divide instruction. the add instruction can make its results available to a subs equent instruction, but it cannot update the architected gpr specif ied as its target operand ahead of the multiple -cycle divide instruction. 5.5.1 initial instruction fetch the e500 core begins execution at fixed virtua l address 0xffff_fffc. the mmu has a default page translation which maps this to the identical physical address. so, the instru ction at physical address 0xffff_fffc must be a branch to another address within the 4-kbyte boot page. 5.5.2 branch detection and prediction to improve branch performance, the e500 provides implementation-specific dynamic branch prediction using the btb to resolve branch inst ructions and improve the accuracy of branch predictions. each of the 512 entries in the 4-way set associative address cache of branch target addresses includes a 2-bit saturating branch history counter, whose value is incremented or decremented depending on whether the branch was taken. these bits can take on four values indicating strongly taken, we akly taken, weakly not taken, and strongly not taken. the btb is used not only to predict branches, but to detect branches during the fetch stage, offering an efficient way to access instruction streams for branches predicted as taken. in the e500, all branch instructions are assigned positions in the comple tion queue at dispatch. speculative instructions in branch target st reams are allowed to execute and proceed through the completion queue, although they can complete only after the branch pred iction is resolved as correct and after the branch instruction itself completes. if a branch resolves as correct, instructions in the target stream are marked nons peculative and are allowed to complete. if the branch history bits in the bt b indicated weakly taken or weakly not taken, the prediction is upgraded to strongl y taken or strongly not taken. if a branch resolves as incorrect, in structions in the target stream are flushed from the exec ution pipeline, the branch history bits are updated in th e btb entry, and nonspeculative fetc hing begins from the correct path. 4 datasheet u .com
core complex overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 5-13 5.5.3 e500 execution pipeline the seven stages of the e500 execution pipeline?f etch1, fetch2/predecode, decode/dispatch, issue, execute, complete, and write bac k?are highlighted in grey in figure 5-4 . figure 5-4. instruction pipeline flow the common pipeline stages are as follows: ? instruction fetch?includes the clock cycles necessa ry to request an instruction and the time the memory system takes to respond to the request. instru ctions retrieved are latc hed into the instruction queue (iq) for subsequent cons ideration by the dispatcher. instruction fetch timing depends on ma ny variables, such as whether an instruction is in the on-chip instruction cache or an l2 cache (if implemented). those factors incr ease when it is necessary to fetch instructions from system memory and include the proce ssor-to-bus clock ratio, the amount of bus traffic, and whether any cache coherency operations are required. because there are so many variables, unless othe rwise specified, the instruction timing examples in this chapter assume optimal performance and s how the portion of the fetch stage in which the decode stage su1 maximum four-instruction bu bu su2 fetch per clock cycle fetch stage 1 fetch stage 2 completion stage write-back stage general issue queue (giq) execute stage maximum two-instruction completion per clock cycle mu stage 1 at dispatch, instructions are deallocated from the iq and assigned sequential positions in the cq. instruction cache maximum two-instruction per cycle dispatch to the issue queues. biq can accept one per cycle; giq can accept at most two. issue stage divide bypass postdivide divide execute finish indicates stages branch issue queue (biq) stage 2 lsu stage 1 stage 3 stage 3 stage 4 stage 2 4 datasheet u .com
core complex overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 5-14 freescale semiconductor instruction is in the instruction queue. the fe tch1 and fetch2 stages ar e primarily involved in retrieving instructions. ? the decode/dispatch stage fully decodes each instru ction; most instructions are dispatched to the issue queues (however, isync , rfi , sc , nop s, and some other instructi ons do not go to issue queues). ? the two issue queues, biq and giq, can accept as many as one and two inst ructions, respectively, in a cycle. the behavior of instruction dispatch is covere d in significant detail in the e500 software optimization guide . the following simplifica tion covers most cases: ? instructions dispatch only from the two lowest iq entries?iq0 and iq1. ? a total of two instructions can be disp atched to the issue queues per clock cycle. ? space must be available in the cq for an in struction to decode and dispatch (this includes instructions that are assigned a space in the cq but not in an issue queue). dispatch is treated as an event at the end of the decode stage. the issue st age reads source operands from rename registers and regist er files and determines when instructions are latched into the execution unit reservation stations. note that the e500 has 14 rename registers, one for each completion queue entry, so instru ctions cannot stall because of a shortage of rename registers. the general behavior of the two issu e queues is described as follows: ? the giq accepts as many as tw o instructions from the dispat ch unit per cycl e. su1, su2, mu, and all lsu instructions (incl uding 64-bit loads and stores) are dispatched to the giq, shown in figure 5-5 . figure 5-5. gpr issue queue (giq) instructions can be issued out -of-order from the bottom two giq entries (giq1?giq0). giq0 can issue to su1, mu, and lsu. giq1 can issue to su2, mu, and lsu. note that su2 executes a subset of the instructions that can be executed in su1. the ability to identify and dispatch instructions to su2 incr eases the availability of su1 to execute more computational-intensive instructions. an instruction in giq1 destined for su2 or th e lsu need not wait for an mu instruction in giq0 that is stalled behind a long-latency divide. ? the execute stage accepts instructions from it s issue queue when the appropriate reservation stations are not busy. in this stage, the operands assigned to th e execution stage fr om the issue stage are latched. the execution unit executes the instruction (perhaps over multiple cycles), writes results on its result bus, and notifies the cq when the inst ruction finishes. the execution unit reports any exceptions to the completion stage. instructi on-generated exceptions are not taken until the excepting instruction is next to retire. giq1 giq3 giq0 giq2 to su2, mu, or lsu from iq0/iq1 to su1, mu, or lsu 4 datasheet u .com
core complex overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 5-15 most integer instructions have a 1-cycle latency, so results of these instructions are available 1 clock cycle after an instruction enters the ex ecution unit. the mu and lsu are pipelined, as shown in figure 5-4 . branches resolve in execute stage. if a branch is mispredicted, it takes 5 cycles for the next instruction to reach the execute stage. ? the complete and write-back stages maintain th e correct architectural ma chine state and commit results to the architecture-define d registers in the proper order. if completion logic detects an instruction containing an exceptio n status or a mispredi cted branch, all follow ing instructions are cancelled, their execution results in rename regi sters are discarded, and the correct instruction stream is fetched. the complete stage ends when the instruction is retired. two instructions can be retired per clock cycle. if no dependencies exist, as many as tw o instructions are retired in program order. the write-back stage occurs in the cloc k cycle after the instruction is retired. the e500 core also provides new instructions that perform single-instruction, multiple-data (simd) operations. these signal processing instructions consist of parallel operations on both the upper and lower 32 bits of two 64-bit gpr values and produce two 32-bit results written to a 64-bit gpr. as shown in figure 5-4 , the lsu, mu, and su1 replicate logic to support 64-bit operations. although a vector instruction generates separate , discrete results in the upper and lower halves of the target gpr, latency and throughput for vector in structions are the same as thos e for their scalar equivalents. 5.6 programming model the following section describe s the e500 core registers. figure 5-6 shows the e500 register set. 4 datasheet u .com
core complex overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 5-16 freescale semiconductor figure 5-6. e500 core programming model user-level registers general-purpose registers instruction-accessible registers user general spr (read/write) 0 31 32 63 0 31 32 63 32 63 user spr general 0 (upper) gpr0 1 (lower) 1 the 64-bit gpr registers are accessed by the spe as separate 32-bit registers by spe instructions. only spe vector instructions can access the upper word. general- purpose registers cr condition register spr 256 usprg0 2 2 usprg0 is a separate physical register from sprg0. gpr1 spr 9 ctr count register general sprs (read-only) gpr2 spr 8 lr link register spr 259 sprg3 spr general registers 3?7 gpr31 spr 260 sprg4 spr 1 xer integer exception register ? ? ? performance monitor pmrs (read-only) spr 512 spefscr 3 spe fp status/control register spr 263 sprg7 pmr 384 upmgc0 3 3 these registers are defined by the eis. global control register acc 3 accumulator time-base registers (read-only) pmr 0?3 upmcs 3 counter registers 0?3 miscellaneous registers spr 268 tbl time base lower/upper pmr 128?131 upmlcas 3 local control registers a0?a3 spr 269 tbu spr 513 bbear 4 4 these registers are e500-specific. branch buffer entry address register pmr 256?259 upmlcbs 3 local control registers b0?b3 l1 cache (read-only) spr 514 bbtar 4 branch buffer target address register l1 cache configuration registers 0?1 spr 515 l1cfg0 3 spr 516 l1cfg1 3 supervisor-level registers interrupt registers configuration registers 32 63 32 63 32 63 spr 63 ivpr interrupt vector prefix spr 400 ivor0 interrupt vector offset registers 0?15 msr machine state spr 401 ivor1 spr 26 srr0 save/restore registers 0/1 spr 1023 svr system version ? ? ? spr 27 srr1 spr 415 ivor15 spr 286 pir processor id spr 58 csrr0 critical srr 0/1 processor version spr 528 ivor32 3 interrupt vector offset registers 32?35 spr 287 pvr spr 59 csrr1 spr 529 ivor33 3 spr 570 mcsrr0 3 machine check srr 0/1 spr 530 ivor34 3 timer/decrementer registers spr 571 mcsrr1 3 spr 531 ivor35 3 spr 22 dec decrementer exception syndrome register spr 62 esr mmu control and status (read/write) decrementer auto-reload spr 54 decar mmu control and status register 0 spr 572 mcsr 3 machine check syndrome register spr 1012 mmucsr0 3 spr 284 tbl time base lower/upper spr 573 mcar 3 machine check address register spr 624 mas0 3 mmu assist registers 0?4 and 6 spr 285 tbu spr 625 mas1 3 spr 61 dear data exception address register spr 340 tcr timer control spr 626 mas2 3 spr 627 mas3 3 spr 336 tsr timer status debug registers spr 628 mas4 3 miscellaneous registers spr 308 dbcr0 debug control registers 0?2 spr 630 mas6 3 spr 309 dbcr1 spr 1008 hid0 3 hardware implementation dependent 0?1 spr 48 pid0 process id registers 0?2 spr 310 dbcr2 spr 1009 hid1 3 spr 633 pid1 3 spr 304 dbsr debug status register spr 634 pid2 3 spr 1013 bucsr 4 branch control and status register spr 312 iac1 instruction address compare registers 1 and 2 mmu control and status (read only) spr 272?279 sprg0?7 general sprs 0?7 spr 313 iac2 spr 1015 mmucfg 3 mmu configuration performance monitor registers data address compare registers 1 and 2 spr 316 dac1 spr 688 tlb0cfg 3 tlb configuration 0/1 pmr 400 pmgc0 3 global control register spr 317 dac2 spr 689 tlb1cfg 3 pmr 16?19 pmc0?3 3 counter registers 0?3 l1 cache (read/write) pmr 144?147 pmlca0?3 3 local control a0?a3 spr 1010 l1csr0 3 l1 cache control/status 0/1 pmr 272?275 pmlcb0?3 3 local control b0?b3 spr 1011 l1csr1 3 4 datasheet u .com
core complex overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 5-17 5.7 on-chip cache implementation the core complex contains separate 32-kbyte, eight-way set-associative, level 1 (l1) inst ruction and data caches to give rapid access to instructions and data. the data cache supports four-state mesi memory coherency protocol. the core complex broadcasts all cache management functions based on the setting of the address broadcast enable bit, hid1[abe], allowing management of other caches in the system. on the MPC8555E the abe bit must be set to ensure that cache and tlb management inst ructions operate properly on the l2 cache. the caches implement a pseudo-least-recen tly-used (plru) replacement algorithm. parity generation and checking may be enabled for both caches, and each cache can be independently invalidated through l1csr1 and l1 csr0. additionally, instructions are provided to perform cache locking and unlocking on both data and instruction cach es on a cache-block granularity. these are listed in section 5.10.3, ?cache control instructions.? individual instruction cache bl ocks and data cache blocks can be invalidated using the icbi and dcbi instructions, respectively. the entire data cache can be invalidated by setting l1csr0[cfi]; the entire instruction cache can be invali dated by setting l1csr1[icfi]. 5.8 interrupts and exception handling the e500 core supports an extended exception handli ng model, with nested in terrupt capability and extensive interrupt vector programma bility. the following sections defi ne the exception model, including an overview of exception handling as implemented on the e500 core, a brief descript ion of the exception classes, and an overview of the re gisters involved in the processes. 5.8.1 exception handling in general, interrupt processing begins with an exception that occurs due to external conditions, errors, or program execution problems. when the exception occurs, the processor checks to verify interrupt processing is enabled for that partic ular exception. if enabled, the interrupt causes the state of the processor to be saved in the appropriate registers and prepar es to begin execution of the handler located at the associated vector address fo r that particular exception. once the handler is executing, the implementation may n eed to check one or more bits in the exception syndrome register (esr) or the spefscr, depending on th e exception, to verify the specific cause of the exception and take appropriate action. the core complex provides the interrupts described in section 5.8.5, ?interrupt registers.? 4 datasheet u .com
core complex overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 5-18 freescale semiconductor 5.8.2 interrupt classes all interrupts may be categorized as as ynchronous/synchronous and critical/noncritical. ? asynchronous interrupts (such as machine check, crit ical input, and external interrupts) are caused by events that are independent of instruction execution. for asynchronous interrupts, the address reported in a save/restore register is the address of the instruction that would have executed next had the asynchronous interrupt not occurred. ? synchronous interrupts are those that are caused di rectly by the execution or attempted execution of instructions. synchronous inputs may be either precise or impr ecise, which are described as follows: ? synchronous precise interrupts are those that precisely indicate th e address of the instruction causing the exception that gene rated the interrupt or, in so me cases, the address of the immediately following instruction. the interrupt ty pe and status bits i ndicate which instruction is addressed in the appropriate save/restore register. ? synchronous imprecise interrupts are those that may indicate the address of the instruction causing the exception that generated the interrupt or some instruction after the instruction causing the interrupt. if the in terrupt was caused by either the context synchronizing mechanism or the execution synchronizing mechanism, the addr ess in the appropriate save/restore register is the address of the interrupt fo rcing instruction. if the interrupt was not caused by either of those mechanisms, the address in the save/restore re gister is the last inst ruction to start execution and may not have completed. no in struction following the instruction in the save/restore register has executed. 5.8.3 interrupt types the e500 core processes all interrupt s as either machine check, critical , or noncritical types. separate control and status register sets ar e provided for each interrupt type. the core handles interrupts from these three types in the following priority order: 1. machine check interrupt (highest priority)?the e5 00 defines a separate set of resources for the machine check interrupt. they use the ma chine check save and restore registers (mcsrr0/mcsrr1) to save state when they are taken, and they use the rfmci instruction to restore state. these interrupts can be masked by the machine check enable bit, msr[me]. 2. noncritical interrupts?first-level interrupts that allow the processor to change program flow to handle conditions generated by exte rnal signals, errors, or unusual conditions arisi ng from program execution or from programmable timer-related events. these inte rrupts are largely identical to those previously defined by the oea portion of the architecture. they use save and restore registers (srr0/srr1) to save state when they ar e taken and they use the rfi instruction to restore state. asynchronous noncritical interrupts can be ma sked by the external interrupt enable bit, msr[ee]. 3. critical interrupts?critical in terrupts can be taken dur ing a noncritical interru pt or during regular program flow. they use the criti cal save and restore registers (c srr0/csrr1) to save state when they are taken and they use the rfci instruction to restore state. these interrupts can be masked by 4 datasheet u .com
core complex overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 5-19 the critical enable bit, msr[ce]. the embedde d category defines the critical input, watchdog timer, and machine check interrupts as critical in terrupts, but the e500 implements a third set of resources for the machine check interrupt, as described in table 5-6 . all interrupts except machine check are ordered within the two categories of noncritical and critical, such that only one interrupt of each cate gory is reported, and when it is proc essed (taken), no program state is lost. because save/restore re gister pairs are serially reusable, program state may be lost when an unordered interrupt is taken. 5.8.4 upper bound on interrupt latencies core complex interrupt latency is defined as the number of core clocks between the sampling of the interrupt signal as asserted and the in itiation of the ivor fetc h (that is, the fetch of the first instruction in the handler). core complex interrupt latency is dete rminate unless a guarded load or a cache-inhibited stwcx. is being executed, in which case the latency is i ndeterminate. the minimum la tency is 3 core clocks and the maximum is 8, not including the 2 bus clock cy cles required to synchronize the interrupt signal from the pad. when an interrupt is taken, all instructions in the iq are thrown away unless th e oldest instruction is a load/store instruction. that is, if an asynchronous interr upt is being serviced and the oldest instruction is not a load/store instruction, the core complex goes straight from sampling the interrupt to ensuring a recoverable state and issuing an exception. if a load/s tore instruction is oldest, the core complex waits 4 clocks before ensuring a recoverable state. during this time, any instruction finished by the lsu is deallocated. 5.8.5 interrupt registers the registers associated with interrupt and exception handling are described in table 5-6 . table 5-6. interrupt registers register description noncritical interrupt registers srr0 save/restore register 0?holds the address of the instru ction causing the exception or the address of the instruction that will execute after the rfi instruction. srr1 save/restore register 1?holds machine state on n oncritical interrupts and restores machine state after an rfi instruction is executed. critical interrupt registers csrr0 critical save/restore register 0?on critical interrup ts, holds either the address of the instruction causing the exception or the address of the inst ruction that will execute after the rfci instruction. csrr1 critical save/restore register 1?holds machine state on critical interrupts and restores machine state after an rfci instruction is executed. machine check interrupt registers mcsrr0 machine check save/restore regist er 0?used to store the address of the instruction that will execute after an rfmci instruction is executed. mcsrr1 machine check save/restore register 1?holds machin e state on machine check interrupts and restores machine state (if recoverable) after an rfmci instruction is executed. 4 datasheet u .com
core complex overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 5-20 freescale semiconductor each interrupt has an associated in terrupt vector address, obtained by concatenating the ivpr value with the address index in the associat ed ivor (that is, ivpr[32?47] || ivor n [48?59] || 0b0000). the resulting address is that of the instruction to be executed wh en that interrupt occurs. ivpr and ivor values are indeterminate on reset, and must be in itialized by the syst em software using mtspr . table 5-7 lists ivor registers implemented on the e500 and the associated interrupts. mcar machine check address register?holds the address of t he data or instruction that caused the machine check interrupt. mcar contents are not meaningful if a signal triggered the machine check interrupt. syndrome registers mcsr machine check syndrome register?holds machine state information on machine check interrupts and restores machine state after an rfmci instruction is executed. esr exception syndrome register?provides a syndrome to differ entiate between the different kinds of exceptions that generate the same interrupt type. upon generation of a s pecific exception type, the associated bit is set and all other bits are cleared. spe interrupt registers spefscr signal processing and embedded floatin g-point status and control register?p rovides interrupt control and status as well as various condition bits associated with the operations performed by the spe. other interrupt registers dear data exception address register?holds the address that was referenced by a load, store, or cache management instruction that caused an alignment, dat a tlb miss, or data storage interrupt. ivpr ivors together, ivpr[32?47] || ivor n [48?59] || 0b0000 define the address of an interrupt-processing routine. see ta bl e 5 - 7 and the eref for more information. table 5-7. interrupt vector registers and exception conditions register interrupt embedded category?defined ivors ivor0 critical input ivor1 machine check interrupt offset ivor2 data storage interrupt offset ivor3 instruction storage interrupt offset ivor4 external input interrupt offset ivor5 alignment interrupt offset ivor6 program interrupt offset ivor7 floating-point unavailable interrupt offset ivor8 system call interrupt offset ivor9 auxiliary processor unavailable interrupt offset ivor10 decrementer interrupt offset ivor11 fixed-interval timer interrupt offset ivor12 watchdog timer interrupt offset ivor13 data tlb error interrupt offset ivor14 instruction tlb error interrupt offset ivor15 debug interrupt offset table 5-6. interrupt registers (continued) register description 4 datasheet u .com
core complex overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 5-21 5.9 memory management the e500 core complex supports demand-paged virtua l memory as well other memory management schemes that depend on precise contro l of effective-to-physical address translation and flexible memory protection as defined by the archite cture. the mapping mechanism consists of software-managed tlbs that support variable-sized pages with per-page pr operties and permissions. th e following properties can be configured for each tlb: ? user-mode page execute access ? user-mode page read access ? user-mode page write access ? supervisor-mode page execute access ? supervisor-mode page read access ? supervisor-mode page write access ? write-through required (w) ? caching inhibited (i) ? memory coherency required (m) (ignored on the MPC8555E) ? guarded (g) ? endianness (e) ? user-definable (u0?u3), a 4-bit implementation-specific field the core complex employs a two-level memory manage ment unit (mmu) architecture. there are separate instruction and data level-1 (l1) mmus backed up by a unified level-2 (l2) mmu. e500-specific ivors ivor32 spe unavailable interrupt offset ivor33 spe floating-point data exception inte rrupt offset ivor34 spe floating-point round exception interrupt offset ivor35 performance monitor table 5-7. interrupt vector registers and exception conditions (continued) register interrupt 4 datasheet u .com
core complex overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 5-22 freescale semiconductor this two-level structure is shown in figure 5-7 . figure 5-7. mmu structure level-1 mmus have the following features: ? four-entry, fully associative tlb arra y that supports all nine page sizes ? 64-entry, 4-way set-associative tlb 4-k byte array that supports 4-kbyte pages only ? hardware partially managed by l2 mmu ? supports snooping of tlbs by both internal and external tlbivax instructions the level-2 mmu has th e following features: ? a 16-entry, fully associative l2 tlb array (tlb 1) that supports all nine variable page sizes ? tlb array (tlb0) that supports only 4-kbyte pages, as follows: ? 256-entry, 2-way set-associative tlb array ? hardware assist for tlb miss exceptions ? software managed by tlbre , tlbwe , tlbsx , tlbsync , tlbivax , and mtspr instructions ? supports snooping of tlb by both internal and external tlbivax instructions 5.9.1 address translation the core complex fetch and load/store units generate 32-bit effective ad dresses. the mmu translates these addresses to real addresses (which are used for memory bus accesses) using an interim 41-bit virtual address. l2 mmus 256-entry tlb array 16-entry (tlb0) tlb array (tlb1) unified l1 data mmu 64-entry d-l1tlb4k 4-entry d-l1vsp l1 instruction mmu 64-entry i-l1tlb4k 4-entry i-l1vsp 32-kbyte i-cache memory unit tags tags 32-kbyte d-cache mas registers to instruction unit instruction line fill buffer to load/store unit core interface data line fill buffer 4 datasheet u .com
core complex overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 5-23 figure 5-8 shows the translation flow. figure 5-8. effective-to-real address translation flow the appropriate l1 mmu (instruction or data) is checked for a matching address translation. the instruction l1 mmu and data l1 mmu operate independently and can be acc essed in parallel, so that hits for instruction accesses and data accesses can occur in the same clock. if an l1 mmu misses, the request for translation is forwarded to th e unified (instruction and data) l2 mmu. if found, the contents of the tlb entry are concatenated with the byte address to obtain the physical address of the requested access. on misses, the l1 tlb entries are replaced from their l2 tlb counter parts using a true lru algorithm. 5.9.2 mmu assist registers (mas0?mas4 and mas6) mmu assist registers are used to hold values either read from or to be written to the tlbs and information required to identify the tlb to be accessed. mas3 implements the real page number (rpn), the user attribute bits (u0?u3), and permission bits (ux, sx, uw, sw, ur, sr ) that specify user and supervisor read, write, and execute permissions. the e500 does not implement mas5. mas registers are affected by the following instructi ons (see the eref for more detailed information): ? mas registers are accessed with the mtspr and mfspr instructions. effective page number byte address real page number byte address 32-bit effective address (ea) 32-bit real address 4?20 bits* 12?28 bits* 4?20 bits* 12?28 bits* l2 mmu (unified) three 41-bit virtual addresses (vas) 8 bits msr ??? is ds ??? instruction access data access as pid0 pid1 pid2 l1 mmus instruction l1 mmu data l1 mmu 2 tlbs 2 tlbs * number of bits depends on page size (4 kbytes?256 mbytes). 16-entry fully-assoc. vsp array (tlb1) 256-entry 2-way set-assoc. array (tlb0) 4 datasheet u .com
core complex overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 5-24 freescale semiconductor ? the tlb read entry instruction ( tlbre ) causes the contents of a single tlb entry from the l2 mmu to be placed in defined locations in mas0?mas3 (and optionally mas7 on the e500v2). the tlb entry to be extracted is determined by information written to mas0 and mas2 before the tlbre instruction is executed. ? the tlb write entry instruction ( tlbwe ) causes the information stored in certain locations of mas0?mas3 (and mas7 on the e500v2) to be written to the tlb specified in mas0. ? the tlb search i ndexed instruction ( tlbsx ) updates mas registers conditionally, based on success or failure of a lookup in the l2 mmu. the lookup is specified by the instruction encoding and specific search fields in mas 6. the values placed in the mas registers may differ, depending on a successful or unsuccessful search. for tlb miss and certain mmu-related dsi/isi exceptions, mas4 provides default values for updating mas0?mas2. 5.9.3 process id registers (pid0?pid2) the e500 core complex also implements three process id (pid) registers that hold the values used to construct the three virtual addresse s for each access. these process id s provide an extended page sharing capability. which of these three virt ual addresses is used is controlled by the tid field of a matching tlb entry, and when tid = 0x00 (identifying a page as globally shared), the pid values are ignored. a hit to multiple tlb entries in the l1 mmu (even if they are in separate arrays) or a hit to multiple entries in the l2 mmu is considered to be a programming error. 5.9.4 tlb coherency the core complex provides the ability to invalidate a tlb entry, as defined by the architecture. the tlbivax instruction invalidates a matching local tlb entry. exec ution of this instruction is also broadcast on the core complex bus (ccb) if hid1[abe] is set. the co re complex also snoops tlb invalidate transactions on the ccb from other bus masters. on the MPC8555E the abe bit must be set to ensure that cache and tlb management inst ructions operate properly on the l2 cache. 5.10 memory coherency the core complex supports four-state memory cohe rency. memory coherency is hardware-supported on the system bus through bus snooping and the retry/ copyback bus protocol, and through broadcasting of cache management instructions. tr anslation coherency is also ha rdware-supported through broadcasting and bus snooping of tlb invalidate transactions. the four-state me si protocol supports efficient large-scale real-time data sharing between multiple caching bus masters. 5.10.1 atomic update memory references the e500 core supports atomic update memory referenc es for both aligned word forms of data using the load and reserve and store conditional instruction pair, lwarx and stwcx . typically, a load and reserve 4 datasheet u .com
core complex overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 5-25 instruction establishes a reservation and is paired with a store conditiona l instruction to achieve the atomic operation. however, there are restri ctions and requirements for this functionality. the processor revokes reservations during a context switc h, so the programmer must reacquire the reservation after a context switch occurs. 5.10.2 memory access ordering the core complex supports weakly ordered references to memory. thus the e500 manages the order and synchronization of instructions to ensure proper execution when memo ry is shared between multiple processes or programs. the cache and data memory control attributes, along with msync and mbar , provide the required access control. 5.10.3 cache control instructions the core complex supports instructions for performing a full range of cache control functions, including cache locking by line. the core complex supports broadcasting and snooping of these cache control instructions on the ccb. the e500 core also s upports the following e500- specific cache locking instructions: ? data cache block lock clear ( dcblc ) ? data cache block touch and lock set ( dcbtls ) ? data cache block touch for store and lock set ( dcbtstls ) ? instruction cache block lock clear ( icblc ) ? instruction cache block touch and lock set ( icbtls ) 5.10.4 programmable page characteristics cache and memory attributes are programmable on a per-page basis. in addition to the write-through, caching-inhibited, memory coherency enforced, and guarded characteristics defined by the wimg bits, the endianness bit, e, allows selection of big- or little-endian byte orde ring on a per-page basis. in addition to the wimge bits, th e mmu model defines user-definab le page attribute bits u0?u3. 5.11 core complex bus (ccb) the core complex defines a versatile local bus interface that allows a wide range of system performance and system-complexity trade-offs. the interface defines the following buses: ? an address-out bus for ma stering bus transactions ? an address-in bus for snooping internal resources ? three tagged data buses two of the data buses are general-purpose data-in buses fo r reads, and the third is a data-out bus for writes. the two data-in buses feature support for out-of-orde r read transactions from two different sources simultaneously, and all three data buses may be operated concurrently. the address-in bus supports snooping for external management of the l1 caches and tlbs by other bus mast ers. the core complex 4 datasheet u .com
core complex overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 5-26 freescale semiconductor broadcasts and snoops the cache and tlb management instructions accor dingly. it is envisioned that a wide range of system implementations can be constructed from the defined interface. 5.12 performance monitoring the e500 core provides a performance monitoring capabi lity that allows counting of events such as processor clocks, instruction cache misses, data c ache misses, mispredicted branches, and others. the count of these events may be configured to trigge r a performance monitor exception following the e500 interrupt model. this interrupt is assi gned to vector offset register ivor35. the register set associated with th e performance monitoring f unction consists of count er registers, a global control register, and local control registers. these re gisters are read/write from supervisor mode, and each register is reflected to a corresponding read-onl y register for user mode. two instructions, mtpmr and mfpmr , are provided for moving data to and from thes e registers. an overvie w of the performance monitoring registers is provide d in the following sections. 5.12.1 global control register the pmgc0 register provides global control of the performance monito ring facility from supervisor mode. from this register all counters may be froze n, unfrozen, or configured to freeze on an enabled condition or event. additionally, the performance monitori ng facility may be disabled or enabled from this register. the contents of pmgc0 ar e reflected to upmgc0, which may be read from user mode using the mfpmr instruction. 5.12.2 performance monitor counter registers there are four counter registers (pcm0?pcm3) provided in the perf ormance monitoring facility. these 32-bit registers hold the current count for software-selectable events a nd can be programmed to generate an exception on overflow. these regi sters may be written or read fr om supervisor mode using the mtpmr and mfpmr instructions. the contents of these register s are reflected to upcm0?upcm3, which can be read from user mode with mfpmr . performance monitor exceptions occur only if all of the following conditions are met: ? a counter is in the overflow state. ? the counter's overflow signaling is enabled. ? overflow exception generation is enabled in pmgc0. ? msr[ee] is set. 5.12.3 local control registers for each of the counter regi sters, there are two corr esponding local control regist ers. these two registers specify which of the 128 available even ts is to be counted, what specific action is to be taken on overflow, and various options for free zing a counter value under given modes or conditions. ? pmlca0?pmlca3 provide fields that allow freezing of the corr esponding counter in user mode, supervisor mode, or under software control. a dditionally, the overflow c ondition may be enabled 4 datasheet u .com
core complex overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 5-27 or disabled from this regi ster. the contents of these registers are reflected to upmlca0?upmlca3, which can be read from user mode with mfpmr . ? pmlcb0?pmlcb3 provide count scaling for each c ounter register using configurable threshold and multiplier values. the threshold is a 6-bit va lue and the multiplier is a 3-bit encoded value, allowing eight multiplier values in the range of 1 to 128. any counter may be configured to increment only when an event occurs more than [threshold multiplier] times. the contents of these registers are reflected to upmlcb0?upmlcb3, which can be read from user mode with mfpmr . 5.13 legacy support of power architecture technology this section provides an overview of the architectural differences a nd compatibilities of the e500 core compared with the aim power architecture technology. the two levels of the e500 programming environment are as follows: ? user level?this defines the base user-level instruction set, user -level registers, data types, memory conventions, and the memory and programming models seen by application programmers. ? supervisor level?this defines supervisor-level resources t ypically required by an operating system, the memory management model, supervis or level registers, a nd the exception model. like all devices that impl ement the power architecture technology, in general, the e500 core supports the user-level architecture. the followi ng sections are intended to highlight the main differences. for specific implementation details refer to the relevant chapter. 5.13.1 instruction set compatibility the following sections generally describe the user and supervis or instruction sets. 5.13.1.1 user instruction set the e500 core executes legacy user-mode binaries and object f iles except for the following: ? the e500 supports vector and scalar single-pr ecision floating-point operati ons as part of the spe. the e500v2 supports scalar double-pre cision floating-point instructi ons. these instructions have different encoding than the aim definition of th e architecture. additiona lly, the e500 core uses gprs for floating-point operations, rather than the fprs defined by the uisa. most porting of floating-point operations can be handled by recompiling. ? string instructions are not implem ented on the e500; therefore, trap emulation must be provided to ensure backward compatibility. 5.13.1.2 supervisor instruction set the supervisor mode instruction set defined by the powerpc architecture is compatible wi th the e500 with the following exceptions: ? the mmu architecture is different, so some tlb manipulation instructions have different semantics. 4 datasheet u .com
core complex overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 5-28 freescale semiconductor ? instructions that support the bats and segment registers ar e not implemented. 5.13.2 memory subsystem the architecture provides separate instruction and data memory res ources. the e500 provides additional cache control features, including cache locking. 5.13.3 exception handling exception handling is generally the same as that de fined in the aim version of the architecture for the e500, with the following differences: ? the critical interrupt provides an extra level of interrupt nesting. the cr itical interrupt includes external critical and wa tchdog timer time-out inputs. ? the machine check exception uses the return from machine check interrupt instruction, rfmci , and two machine check save/restore registers, mcsrr0 and mcsrr1. ? ivpr and ivors set interrupt vectors individually, but they can be set to the address offsets defined in the oea to provide compatibility. ? the embedded category does not defi ne a reset vector; execution begins at a fixed virtual address, 0xffff_fffc. ? timer services are generally compatible, although the embedded category defines a new decrementer auto reload feature, the fixed-interv al timer critical interr upt, and the watchdog timer interrupt, which are implemented in the e500 core. an overview of the interrupt and exception handlin g capabilities of the e500 core can be found in section 5.8, ?interrupts and exception handling.? 5.13.4 memory management the embedded category defines resour ces for fixed 4-kbyte pages and mult iple, variable page sizes that can be configured in a single im plementation. tlb management is pr ovided with new instructions and sprs. 5.13.5 reset embedded category?compliant cores do not share a common reset v ector with the aim version of the architecture. instead, at reset fetching begins at address 0xffff_fffc. in addition, the freescale mmu category defines specific aspects of the mmu page translation and pr otection mechanisms. unlike the aim version of the core, as soon as instruction fetchi ng begins, the e500 core is in virtual mode with a hardware-initialized tlb entry. mmu operations are described in the eref. 4 datasheet u .com
core complex overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 5-29 5.13.6 little-endian mode unlike the aim version of the architecture, where lit tle-endian mode is controll ed on a system basis, the embedded category allows control of byte ordering on a memory page basi s. in addition, the little-endian byte ordering used is true little endian. 5.14 powerquicc iii implementation details table 5-8 summarizes e500 core functi onality that is not implemen ted by powerquicc iii devices. table 5-8. differences between the e500 core and the powerquicc iii core implementation feature powerquicc iii implementation cache protocol the l2 cache does not support mesi cache protocol. multiprocessor functionality because powerquicc iii is designed for a uniprocessor environment, the following e500 functionality is not implemented: ? the memory coherence bit, m, which is cont rolled through mas2[m] and mas4[md] has no effect. ? hid1[abe] has meaning only in that it must be set to ensure that cache and tlb management instructions operate properly with respect to the l2 cache. ? dynamic snooping does not occur in power-stopped state (see the note below in the entry for dynamic bus snooping). nexus support nexus is not supported. the nexus processo r id register (npidr) and the nexus bus enable bit (hid1[nexen]) are not supported. r1 and r2 data bus parity r1 and r2 data bus parity are disabled on powerquicc iii devices. hid1[r1dpe,r2dpe] are reserved. dynamic bus snooping the powerquicc iii devices do not perform dynamic bu s snooping as described here. that is, when the e500 core is in core-stopped state (which is the state of the core when the powerquicc iii device is in either the nap or sleep state), the core is not awakened to perfo rm snoops on global transactions. therefore, before entering nap or sleep modes, l1 caches should be fl ushed if coherency is required during these power-down modes. for more information, see section 18.5.1.9, ?snooping in power-down modes.? supported tcr[wrc] powerquicc iii devices define values for 01, 10, and 11, as follows: 00 no watchdog timer reset can occur. 01 force processor checkstop on se cond timeout of watchdog timer 10 assert processor reset output ( core_hreset_req ) on second timeout of watchdog timer 11 reserved spe and floating-point categories the spe and the vector and scalar floating-point instru ctions will not be implement ed in the next generation of powerquicc devices. freescale semiconductor stro ngly recommends that use of these instructions be confined to libraries and device drivers. customer softwa re that uses these instruct ions at the assembly level or that uses spe or floating-point intrinsics will requir e rewriting for upward compatibility with next generation powerquicc devices. freescale semiconductor offers a libcfsl_e500 library th at uses spe instructions. freescale semiconductor will also provide future libraries to support next generation powerquicc devices. hid0 implementation sel_tbclk bit. selects time base clock. if this bit is set and the time base is enabled, the time base is based on the tbclk input, which on the powerquicc iii devices is rtc. 4 datasheet u .com
core complex overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 5-30 freescale semiconductor hid1 implementation pll_mode. set to 01 pll_cfg. powerquicc iii devices support the following: 0001_00 ratio of 2:1 0001_01 ratio of 5:2 (2.5:1) 0001_10 ratio of 3:1 0001_11 ratio of 7:2 (3.5:1) nexen, r1dpe, r2dpe, mpxtt, mshars, sshar, ats, and mid are not implemented on powerquicc iii devices, abe must be set to ensure that cache and tlb management instructions operate properly on the l2 cache. please refer to the description of hid1[rfxe] in section 6.10.2, ?hardware implementation-dependent register 1 (hid1).? if rfxe is 0, conditions that cause the assertion of core_fault_in cannot directly cause the e500 to generate a machine check; however, powerquicc iii devices must be configured to detect and enable such conditions. the following describes how error bits should be configured: ? ecm mapping errors: eeer [laee] must be set. see section 8.2.1.4, ?ecm error enable register (eeer).? ? l2 multiple-bit ecc errors: l2errdis[mbeccdis] must be cleared to ensure that error can be detected. l2errinten[mbeccinten] must be set. see section 7.3.1.5, ?l2 error registers.? ? ddr multiple-bit ecc errors. err_disable[mbed] and err_int_en[mbee] must be zero and ddr_sdram_cfg[ecc_en] must be one to ensure that an interrupt is generated. see section 9.4.1, ?register descriptions.? ? pci. the appropriate parity detect and master-abort bits in err_dr must be cleared and the corresponding enable bits in err_en must be set to ensure that an interrupt is generated. local bus controller parity errors. ltedr[pard] must be cleared and lteir[pari] must be set to ensure that an parity errors can generate an interrupt. see section 13.3.1.11, ?transfer error check disable register (ltedr),? and section 13.3.1.12, ?transfer error in terrupt enable register (lteir).? pir value the pir value is all zeros on powerquicc iii devices. pvr value the pvr reset value is 0x80 nn _ nnnn. see ta b l e 5 - 1 for specific values. pvr[version] = 0x80 nn pvr[revision] = 0x nnnn svr value the svr reset value is 0x80 nn _ nnnn. see ta b l e 5 - 1 for specific values. alternate time base the alternate time base defines a time base counter si milar to the time base defined in architecture. it is intended to be used for measuring time in implementation defined intervals. it differs from the defined time base in that it is not writable and always counts up, wrapping when the 64-bit count overflows. it defines two sprs, atbl (spr 526) and atbl (spr 527). table 5-8. differences between the e500 core and the powerquicc iii core implementation (continued) feature powerquicc iii implementation 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 6-1 chapter 6 core register summary this chapter describes the e500 register model and in dicates whether each register is defined by the power architecture technology, by the freescale embedded ca tegory implementation standards (eis), or by the implementation. for the programmer, drawing this distinction indicate s the degree to which code is portable among freescale processors. this chapter provides reference materi al?figures for each register and co mplete descriptions of register fields, including how the registers are accessed, reset values, and whether they can be accessed by user- and supervisor-level software. de tailed discussions of how these re gisters are used are provided in eref: a reference for freescale book e and the e500 core and the powerpc? e500 core family reference manual . note that all registers described here are implemented in the hardware as part of the e500 core. 6.1 overview as shown in figure 6-1 , most of the registers implemented are defined by the architecture, and most of those were defined by the aim definition of the ar chitecture and have change d very little. additional registers and fields within registers are defined by the eis and by the implementation. the power architecture technology defines some register fields in a very general way, leaving some details as implementation specific. in some cases, this more specific f unctionality is defined by the eis; in others it is left up to the processor. this chapter identifies the level at whic h each features is defined. 6.1.1 register set table 6-1 shows the e500 register set, grouped by wh ether they can be accessed by user- or supervisor-level software. unless otherwise indicated, thes e registers are defined by the base or embedded category. 4 datasheet u .com
core register summary MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 6-2 freescale semiconductor figure 6-1. core register model user-level registers general-purpose registers instruction-accessible registers user general spr (read/write) 0 31 32 63 0 31 32 63 32 63 user spr general 0 1 1 usprg0 is a separate physical register from sprg0. (upper) gpr0 2 (lower) 2 the 64-bit gpr registers are accessed by the spe as separate 32-bit registers by spe instructions. only spe vector instructions can access the upper word. general- purpose registers cr condition register spr 256 usprg0 gpr1 spr 9 ctr count register general sprs (read only) gpr2 ? ? ? spr 8 lr link register spr 259 sprg3 spr general registers 3?7 gpr31 spr 260 sprg4 spr 1 xer integer exception register ? ? ? performance monitor registers (read-only pmrs) spr 512 spefscr 3 3 these registers are defined by additional categories. spe fp status/control register spr 263 sprg7 acc 3 accumulator time-base registers (read only) global control register pmr 384 upmgc0 3 miscellaneous registers spr 268 tbl time base lower/upper pmr 0?3 upmcs 3 counter registers 0?3 spr 269 tbu spr 513 bbear 3 branch buffer entry address register pmr 128?131 upmlcas 3 local control registers a0?a3 l1 cache (read only) spr 514 bbtar 3 branch buffer target address register l1 cache configuration registers 0?1 pmr 256?259 upmlcbs 3 local control registers b0?b3 spr 515 l1cfg0 3 spr 516 l1cfg1 3 supervisor-level registers interrupt registers configuration registers 32 63 32 63 32 63 spr 63 ivpr interrupt vector prefix spr 400 ivor0 interrupt vector offset registers 0?15 msr machine state spr 401 ivor1 spr 26 srr0 save/restore registers 0/1 spr 1023 svr system version ? ? ? spr 27 srr1 spr 415 ivor15 spr 286 pir processor id spr 58 csrr0 critical srr 0/1 processor version spr 528 ivor32 3 interrupt vector offset registers 32?35 spr 287 pvr spr 59 csrr1 spr 529 ivor33 3 timer/decrementer registers spr 570 mcsrr0 3 machine check srr 0/1 spr 530 ivor34 3 spr 571 mcsrr1 3 spr 531 ivor35 3 spr 22 dec decrementer exception syndrome register spr 62 esr mmu control and status (read/write) decrementer auto-reload spr 54 decar mmu control and status register 0 spr 572 mcsr 3 machine check syndrome register spr 1012 mmucsr0 3 spr 284 tbl time base lower/upper spr 573 mcar machine check address register spr 624 mas0 3 mmu assist registers 0?4 and 6 spr 285 tbu spr 625 mas1 3 spr 61 dear data exception address register spr 340 tcr timer control spr 626 mas2 3 spr 627 mas3 3 spr 336 tsr timer status debug registers spr 628 mas4 3 miscellaneous registers spr 308 dbcr0 debug control registers 0?2 spr 630 mas6 3 spr 309 dbcr1 spr 1008 hid0 3 hardware implementation dependent 0?1 spr 48 pid0 process id registers 0?2 spr 310 dbcr2 spr 1009 hid1 3 spr 633 pid1 3 spr 304 dbsr debug status register spr 634 pid2 3 spr 1013 bucsr 4 4 these registers are e500-specific. branch control and status register spr 312 iac1 instruction address compare registers 1 and 2 mmu control and status (read only) spr 272?279 sprg0?7 general sprs 0?7 spr 313 iac2 spr 1015 mmucfg 3 mmu configuration performance monitor registers data address compare registers 1 and 2 spr 316 dac1 spr 688 tlb0cfg 3 tlb configuration 0/1 pmr 400 pmgc0 3 global control spr 317 dac2 spr 689 tlb1cfg 3 pmr 16?19 pmc0?3 3 counter registers 0?3 l1 cache (read/write) pmr 144?147 pmlca0?3 3 local control a0?a3 spr 1010 l1csr0 3 l1 cache control/status 0/1 pmr 272?275 pmlcb0?3 3 local control b0?b3 spr 1011 l1csr1 3 4 datasheet u .com
core register summary MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 6-3 6.2 register model for 32-bit implementations embedded 32-bit processors impl ement the following types of software-accessible registers: ? architecture-defined registers that are accessed as part of instru ction execution. these include the following: ? registers used for computation. these include the following: ? general-purpose registers (g prs)?the 32 gprs hold sour ce and destination operands for load, store, arithmetic, and computational in structions, and to read and write to other registers. the e500 implements thes e as 64-bit registers for use with 64-bit load, store, and merge instructions, as described in section 6.3.1, ?general-pur pose registers (gprs).? ? integer exception register (xer)?bits in this register are set base d on the operation of an instruction considered as a whol e, not on intermediate results. (for example, the subtract from carrying instruction ( subfc ), the result of which is specified as the sum of three values, sets bits in the xer based on the entire operation, not on an intermediate sum.) these registers are described in section 6.3, ?registers for computational operations.? ? condition register (cr)?used to record conditions such as overflows and carries that occur as a result of executi ng arithmetic instructions (includi ng those implemented by the spe). the cr is described in section 6.4, ?registers fo r branch operations.? ? machine state register (msr)?us ed by the operating system to configure parameters such as user/supervisor mode, address space, and enabli ng of asynchronous interrupt s. this register is described in section 6.5.1, ?machine state register (msr),? grouped with pr ocessor control sprs. ? special-purpose registers (sprs) are accessed explicitly using mtspr and mfspr instructions. these registers are listed in table 6-1 in section 6.2.1, ?special-pur pose registers (sprs).? ? freescale eis? and e500-defined sprs that are accessed explicitly using mtspr and mfspr are listed in table 6-2 in section 6.2.1, ?special-pur pose registers (sprs).? ? freescale eis?defined performan ce monitor registers (pmrs). these registers are similar to sprs, but are accessed with freescale eis?defined m ove to and move from pmr instructions ( mtpmr and mfpmr ). in this chapter, sprs are grouped by function as follows: ? section 6.4, ?registers for branch operations,? describes the count register (ctr) and the link register (lr). ? section 6.5, ?processor control registers? ? section 6.6, ?timer registers? ? section 6.7, ?interrupt registers? ? section 6.8, ?software-use sprs (sprg0?sprg7 and usprg0),? describes sprs defined for software use. ? section 6.9, ?branch target buffer (btb) registers,? describes e500-specific registers defined to support the e500 tabs. ? section 6.10, ?hardware implemen tation-dependent registers,? describes hid0 and hid1. ? section 6.11, ?l1 cache co nfiguration registers? 4 datasheet u .com
core register summary MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 6-4 freescale semiconductor ? section 6.12, ?mmu registers? ? section 6.13, ?debug registers? ? section 6.14, ?signal processing and embedded fl oating-point status and control register (spefscr)? the e500 core implements 64-bit gprs, the upper 32 bits of which are used only with 64-bit load, store, and merge instructions. 6.2.1 special-purpose registers (sprs) table 6-1 summarizes sprs. the spr numbe rs are used in the instructi on mnemonics. bit 5 in an spr number indicates whether an spr is accessible fr om user- or supervisor -level software. an mtspr or mfspr instruction that specifies an unsupported spr number is considered an invalid instruction. in table 6-1 and in the register figures and field descri ptions, the following access definitions apply: ? reserved fields are always ignored for the purposes of determining access type. ? r/w, r, and w (read/write, read only, and write only) indicate that all the non-reserved fields in a register have the same access type. ? w1c indicates that all of the non-reserved fields in a register are cleared by writing ones to them. ? mixed indicates a combination of access types. ? special is used when no other cate gory applies. in this case the re gister figure and field description table should be read carefully. note writing to the following registers re quires synchronization, as described in the ?synchronization requirements? s ection in the ?register model? chapter of the powerpc? e500 core family reference manual . ? btb locking registers?bbear, bbtar, and bucsr ?dbcr n ?hid n ?l1csr n ? mmu registers?mas n, mmucsr0, pid n ? spefscr table 6-1. base and embedded category special-purpose registers (by spr abbreviation) spr abbreviation name defined spr number access supervisor only section/ page decimal binary csrr0 critical save/restore register 0 58 00001 11010 read/write yes 6.7.1.1/6-17 csrr1 critical save/restore register 1 59 00001 11011 read/write yes 6.7.1.2/6-17 ctr count register 9 00000 01001 read/write no 6.4.3/6-11 4 datasheet u .com
core register summary MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 6-5 dac1 data address compare 1 316 01001 11100 read/write yes 6.13.4/6-44 dac2 data address compare 2 317 01001 11101 dbcr0 debug control register 0 1 308 01001 10100 read/write yes 6.13.1/6-39 dbcr1 debug control register 1 1 309 01001 10101 read/write yes dbcr2 debug control register 2 1 310 01001 10110 read/write yes dbsr debug status register 304 01001 10000 w1c 2 ye s 6.13.2/6-42 dear data exception address register 61 00001 11101 read/write yes 6.7.1.5/6-18 dec decrementer 22 00000 10110 read/write yes 6.6.4/6-16 decar decrementer auto-reload 54 00001 10110 write only esr exception syndrome register 62 00001 11110 read/write yes 6.7.1.8/6-19 iac1 instruction address compare 1 312 01001 11000 read/write yes 6.13.3/6-44 iac2 instruction address compare 2 313 01001 11001 ivor0 critical input 400 01100 10000 read/write yes 6.7.1.7/6-18 ivor1 machine check interrupt offset 401 01100 10001 ivor2 data storage interrupt offset 402 01100 10010 ivor3 instruction storage interrupt offset 403 01100 10011 ivor4 external input interrupt offset 404 01100 10100 ivor5 alignment interrupt offset 405 01100 10101 ivor6 program interrupt offset 406 01100 10110 ivor8 system call interrupt offset 408 01100 11000 ivor10 decrementer interrupt offset 410 01100 11010 ivor11 fixed-interval timer interrupt offset 411 01100 11011 ivor12 watchdog timer interrupt offset 412 01100 11100 ivor13 data tlb error interrupt offset 413 01100 11101 ivor14 instruction tlb error interrupt offset 414 01100 11110 ivor15 debug interrupt offset 415 01100 11111 ivpr interrupt vector 63 00001 11111 read/write yes 6.7.1.6/6-18 lr link register 8 00000 01000 read/write no 6.4.2/6-11 pid process id register 3 48 00001 10000 read/write yes 6.12.1/6-32 pir processor id register 286 01000 11110 read only yes 6.5.2/6-13 pvr processor version register 287 01000 11111 read only yes 6.5.3/6-13 table 6-1. base and embedded category special-purpose registers (by spr abbreviation) (continued) spr abbreviation name defined spr number access supervisor only section/ page decimal binary 4 datasheet u .com
core register summary MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 6-6 freescale semiconductor sprg0 spr general 0 272 01000 10000 read/write yes 6.8/6-22 sprg1 spr general 1 273 01000 10001 read/write yes sprg2 spr general 2 274 01000 10010 read/write yes sprg3 spr general 3 259 01000 00011 read only no 4 275 01000 10011 read/write yes sprg4 spr general 4 260 01000 00100 read only no 276 01000 10100 read/write yes sprg5 spr general 5 261 01000 00101 read only no 6.8/6-22 277 01000 10101 read/write yes sprg6 spr general 6 262 01000 00110 read only no 278 01000 10110 read/write yes sprg7 spr general 7 263 01000 00111 read only no 279 01000 10111 read/write yes srr0 save/restore register 0 26 00000 11010 read/write yes 6.7.1.1/6-17 srr1 save/restore register 1 27 00000 11011 read/write yes 6.7.1.2/6-17 tbl time base lower 268 01000 01100 read only no 6.6.3/6-16 284 01000 11100 write only yes tbu time base upper 269 01000 01101 read only no 285 01000 11101 write only yes tcr timer control register 340 01010 10100 read/write yes 6.6.1/6-14 tsr timer status regi ster 336 01010 10000 w1c 5 ye s 6.6.2/6-15 usprg0 user spr general 0 6 256 01000 00000 read/write no 6.8/6-22 xer integer exception register 1 00000 00001 read/write no 6.3.2/6-8 1 accesses to this register requires synch ronization, as described in the ?synch ronization requirements? section of the ?register model? chapter of the powerpc? e500 core family reference manual 2 the dbsr is read using mfspr . it cannot be directly written to. instead, dbsr bits corresponding to 1 bits in the gpr can be cleared using mtspr . 3 implementations may support more than one pid. for implement ations with multiple pids, t he pid defined by the embedded category is pid0. 4 user-mode read access to sprg3 is implementation dependent. 5 the tsr is read using mfspr . it cannot be directly written to. instead, tsr bi ts corresponding to 1 bits in the gpr can be cleared using mtspr . 6 usprg0 is a separate physical register from sprg0. table 6-1. base and embedded category special-purpose registers (by spr abbreviation) (continued) spr abbreviation name defined spr number access supervisor only section/ page decimal binary 4 datasheet u .com
core register summary MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 6-7 table 6-2 describes the implementation-sp ecific sprs and sprs defined by categories other than the base and embedded categories. compilers should recognize the mnemonic names given in table 6-2 when parsing instructions. table 6-2. additional sprs (by spr abbreviation) spr abbreviation name spr number access supervisor only section/ page bbear branch buffer entry address register 1 513 read/write no 6.9.1/6-23 bbtar branch buffer target address register 1 514 read/write no 6.9.2/6-23 bucsr branch unit control and status register 1 1013 read/write yes 6.9.3/6-24 hid0 hardware implementation dependent reg 0 1 1008 read/write yes 6.10.1/6-25 hid1 hardware implementation dependent reg 1 1 1009 read/write yes 6.10.2/6-26 ivor32 spe unavailable interrupt offset 528 read/write yes 6.7.1.7/6-18 ivor33 floating-point data exception interrupt offset 529 read/write yes ivor34 floating-point round exceptio n interrupt offset 530 read/write yes ivor35 performance monitor 531 read/write yes l1cfg0 l1 cache configuration register 0 515 read only no 6.11.3/6-30 l1cfg1 l1 cache configuration register 1 516 read only no 6.11.4/6-31 l1csr0 l1 cache control and status register 0 1 1010 read/write yes 6.11.1/6-28 l1csr1 l1 cache control and status register 1 1 1011 read/write yes 6.11.2/6-29 mas0 mmu assist register 0 1 624 read/write yes 6.12.5.1/6-34 mas1 mmu assist register 1 1 625 read/write yes 6.12.5.2/6-35 mas2 mmu assist register 2 1 626 read/write yes 6.12.5.3/6-36 mas3 mmu assist register 3 1 627 read/write yes 6.12.5.4/6-37 mas4 mmu assist register 4 1 628 read/write yes 6.12.5.5/6-37 mas6 mmu assist register 6 1 630 read/write yes 6.12.5.6/6-38 mcar machine check address register 573 read only yes 6.7.2.3/6-21 mcsr machine check syndrome register 572 read/write yes 6.7.2.4/6-21 mcsrr0 machine check save/restore register 0 570 read/write yes 6.7.2.1/6-20 mcsrr1 machine check save/restore register 1 571 read/write yes 6.7.2.2/6-20 mmucfg mmu configuration register 1015 read only yes 6.12.3/6-32 mmucsr0 mmu control and status register 0 1 1012 read/write yes 6.12.2/6-32 pid0 process id register 0 1 48 read/write yes 6.12.1/6-32 pid1 process id register 1 1 633 read/write yes pid2 process id register 2 1 634 read/write yes spefscr signal processing and embedded floating-point status and control register 1 512 read/write no 6.14/6-44 4 datasheet u .com
core register summary MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 6-8 freescale semiconductor 6.3 registers for computational operations the following sections describe genera l-purpose and integer exception registers. note register fields designat ed as write-one-t o-clear are cleared only by writing ones to them. writing zeros to them has no effect. 6.3.1 general-purpose registers (gprs) gpr0?gpr31 support integer operations. the instruction formats provide 5-bit fields for specifying the gprs to be used in the execution of the instruct ion. each gpr is a 64-bit register, although only 64-bit load, store, and merge instructions use gpr bits 0?31. 6.3.2 integer exception register (xer) svr system version register 1023 read only yes 6.5.4/6-14 tlb0cfg tlb configuration register 0 688 read only yes 6.12.4/6-33 tlb1cfg tlb configuration register 1 689 read only yes 6.12.4.2/6-34 1 accesses to this register requires synch ronization, as described in the ?synch ronization requirements? section of the ?register model? chapter of the powerpc? e500 core family reference manual . spr 1 access: user read/write 32 33 34 35 56 57 63 r so ov ca ? number of bytes w reset all zeros figure 6-2. integer exception register (xer) table 6-3. xer field description bits name description 32 so summary overflow. set when an instruction (except mtspr ) sets the overflow bit. once set, so remains set until it is cleared by mtspr[xer] or mcrxr . so is not altered by compare inst ructions or by other instructions (except mtspr[xer] and mcrxr ) that cannot overflow. executing mtspr[xer] , supplying the values 0 for so and 1 for ov, causes so to be cleared and ov to be set. 33 ov overflow. x-form add, subtract fr om, and negate instructions having oe = 1 set ov if the carry out of bit 32 is not equal to the carry out of bit 33, and clear ov otherwise to indicate a signed overflow. x-form multiply low word and divide word instructions having oe = 1 set ov if the result cannot be represented in 32 bits ( mullwo , divwo , and divwuo ) and clear ov otherwise. ov is not altered by compare instructions or by other instructions (except mtspr[xer] and mcrxr ) that cannot overflow. table 6-2. additional sprs (by spr abbreviation) (continued) spr abbreviation name spr number access supervisor only section/ page 4 datasheet u .com
core register summary MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 6-9 6.4 registers for branch operations this section describes registers th at support branch and cr operations. 6.4.1 condition register (cr) 34 ca carry. add carrying, subtract from carrying, add ex tended, and subtract from extended instructions set ca if there is a carry out of bit 32 and clear it otherwis e. ca can be used to indicate unsigned overflow for add and subtract operations that set ca. shift right algebraic word instructions set ca if any 1 bits are shifted out of a negative operand and clear ca otherwise. com pare instructions and instructions that cannot carry (except shift right algebraic word, mtspr[xer] , and mcrxr ) do not affect ca. 35?56 ? reserved, should be cleared. 57?63 no. of bytes supports emulation of load and store string instructions . specifies the number of bytes to be transferred by a load string indexed or store string indexed instruction. access: user read/write 32 35 36 39 40 43 44 47 48 51 52 55 56 59 60 63 r cr0 cr1 cr2 cr3 cr4 cr5 cr6 cr7 w reset all zeros figure 6-3. condition register (cr) table 6-4. bi operand settings for cr fields cr n bits cr bits bi description cr0[0] 32 00000 negative (lt)?set when the result is negative. for spe vector compare and vector test instructions: set if the high-order element of r a is equal to the high-order element of r b; cleared otherwise. cr0[1] 33 00001 positive (gt)?set when the result is positive (and not zero). for spe vector compare and vector test instructions: set if the low-order element of r a is equal to the low-order element of r b; cleared otherwise. cr0[2] 34 00010 zero (eq)?set when the result is zero. for spe vector com pare and vector test instructions: set to the or of the result of the compare of the high and low elements. cr0[3] 35 00011 summary overflow (so). copy of xer[so] at the instruction?s completion. for spe vector compare and vector test instructions: set to the and of the result of the compare of the high and low elements. cr1[0] 36 00100 negative (lt) for spe vector compare and vector test instructions: set if the high-order element of r a is equal to the high-order element of r b; cleared otherwise. cr1[1] 37 00101 positive (gt) for spe vector compare and vector test instructions: set if the low-order element of r a is equal to the low-order element of r b; cleared otherwise. table 6-3. xer field description (continued) bits name description 4 datasheet u .com
core register summary MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 6-10 freescale semiconductor the bits of cr0 are inte rpreted as described in table 6-5 . cr1[2] 38 00110 zero (eq) for spe vector compare and vector test instructions: set to the or of the result of the compare of the high and low elements. cr1[3] 39 00111 summary overflow (so) for spe vector compare and vector test instructions: set to the and of the result of the compare of the high and low elements. cr n [0] 40 44 48 52 56 60 01000 01100 10000 10100 11000 11100 less than (lt) for integer compare instructions: r a < simm or rb (signed comparison) or r a < uimm or r b (unsigned comparison). for spe vector compare and vector test instructions: set if the high-order element of r a is equal to the high-order element of r b; cleared otherwise. cr n [1] 41 45 49 53 57 61 01001 01101 10001 10101 11001 11101 greater than (gt) for integer compare instructions: r a > simm or r b (signed comparison) or r a > uimm or r b (unsigned comparison). for spe vector compare and vector test instructions: set if the low-order element of r a is equal to the low-order element of r b; cleared otherwise. cr n [2] 42 46 50 54 58 62 01010 01110 10010 10110 11010 11110 equal (eq) for integer compare instructions: r a = simm, uimm, or r b. for spe vector compare and vector test instructions: set to the or of the result of the compare of the high and low elements. cr n [3] 43 47 51 55 59 63 01011 01111 10011 10111 11011 11111 summary overflow (so) for integer compare instructions, this is a copy of xer[so] at the completion of the instruction. for spe vector compare and vector test instructions: set to the and of the result of the compare of the high and low elements. table 6-5. cr0 bit descriptions cr bit name description 32 negative (lt) bit 32 of the result is equal to 1. 33 positive (gt) bit 32 of the result is equal to 0 and at least one bit from 33?63 of the result is non-zero. 34 zero (eq) bits 32?63 of the result are equal to 0. 35 summary overflow (so) this is a copy of the final state of xer[so] at the co mpletion of the instruction. table 6-4. bi operand settings for cr fields (continued) cr n bits cr bits bi description 4 datasheet u .com
core register summary MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 6-11 6.4.2 link register (lr) 6.4.3 count register (ctr) 6.5 processor control registers this section addresses machine state, proc essor id, and processo r version registers. 6.5.1 machine state register (msr) spr 8 access: user read/write 32 63 r link address w reset all zeros figure 6-4. link register (lr) spr 9 access: user read/write 32 63 r count value w reset all zeros figure 6-5. count register (ctr) access: supervisor read/write 32 36 37 38 39 44 45 46 47 48 49 50 51 52 53 54 55 57 58 59 60 61 62 63 r ? ucle spe ? we ce ? ee pr ? me ?uble de ? is ds ?pmm ? w reset all zeros figure 6-6. machine state register (msr) table 6-6. msr field descriptions bits name description 32?36 ? reserved, should be cleared. 1 37 ucle user-mode cache lock enable. used to restrict user-mode cache-line locking by the operating system 0 any cache lock instruction executed in user-mode ta kes a cache-locking dsi exception and sets either esr[dlk] or esr[ilk]. this allows the operating system to manage and track the lo cking/unlocking of cache lines by user-mode tasks. 1 cache-locking instructions can be executed in user-mo de and they do not take a dsi for cache-locking (they may still take a dsi for access violations though). 4 datasheet u .com
core register summary MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 6-12 freescale semiconductor 38 spe spe enable. (e500-specific). 0 if software attempts to execute an instruction that accesses the upper word of a gpr, the spe unavailable exception is taken. the exception is also taken if software attempts to execute scalar floating-point instructions. 1 software can execute the following instructions: these instructions include the spe instructions and both vector and scalar single-precision floating-point instructions. 39?44 ? reserved, should be cleared. 1 45 we wait state enable. allows the core complex to sign al a request for power management , according to the states of hid0[doze], hid0[nap], and hid0[sleep]. 0 the processor is not in wait state and continues proc essing. no power management request is signaled to external logic. 1 the processor enters wait state by ceasing to execut e instructions and entering low-power mode. details of how wait state is entered and exited and how the processor behaves in the wait state are implementation-dependent. on the e500 , msr[we] gates the doze, nap, and sleep outputs from the core complex; as a result, these outputs negate to the ex ternal power management logic on entry to the interrupt and then return to their previous state on return from th e interrupt. we is cleared on entry to any interrupt and restored to its previous state upon return. 46 ce critical enable 0 critical input and watchdog timer interrupts are disabled. 1 critical input and watchdog timer interrupts are enabled. 47 ? reserved, should be cleared. 1 48 ee external enable 0 external input, decrementer, fixed-interval timer, and performance monitor interrupts are disabled. 1 external input, decrementer, fixed-interval timer, and performance monitor interrupts are enabled. 49 pr user mode (problem state) 0 the processor is in supervisor mode, can execute any inst ruction, and can access any resource (for example, gprs, sprs, and the msr). 1 the processor is in user mode, cannot execute any pr ivileged instruction, and cannot access any privileged resource. pr also affects memory access control 50 ? reserved, should be cleared. 1 51 me machine check enable 0 machine check interrupts are disabled. 1 machine check interrupts are enabled. 52 ? reserved, should be cleared. 1 53 uble in the e500, it is the user btb lock enable bit. 0 user-mode execution of the btb lock instructions is disabled; privileged instruction exception taken instead. 1 user-mode execution of the btb lock instructions for user mode is enabled. 54 de debug interrupt enable. see the description of the dbsr[ude] in section 6.13.2, ?deb ug status register (dbsr).? 0 debug interrupts are disabled. 1 debug interrupts are enabled if dbcr0[idm] = 1. 55?57 ? reserved, should be cleared. 1 table 6-6. msr field descriptions (continued) bits name description 4 datasheet u .com
core register summary MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 6-13 6.5.2 processor id register (pir) 6.5.3 processor version register (pvr) 58 is instruction address space 0 the processor directs all instruction fetches to add ress space 0 (ts = 0 in the relevant tlb entry). 1 the processor directs all instruction fetches to add ress space 1 (ts = 1 in the relevant tlb entry). 59 ds data address space 0 the processor directs data memory accesses to address space 0 (ts = 0 in the relevant tlb entry). 1 the processor directs data memory accesses to address space 1 (ts = 1 in the relevant tlb entry). 60 ? reserved, should be cleared. 1 61 pmm performance monitor mark bit. system software can set pmm when a marked process is running to enable statistics to be gathered only during execution of the ma rked process. msr[pr] and msr[pmm] together define a state that the processor (supervisor or user) and the process (marked or unmarked) may be in at any time. if this state matches an individual st ate specified in the pmlcax, the st ate for which monitoring is enabled, counting is enabled. 62?63 ? preserved for oea-defined ri and le, respectively 1 an msr bit that is reserved may be altered by a return from interrupt instruction. spr 286 access: supervisor read only 32 63 r processor id w reset all zeros figure 6-7. processor id register (pir) spr 287 access: supervisor read only 32 47 48 63 r version revision w reset soc-dependent value. see section 5.2, ?e500 processor and system version numbers.? figure 6-8. processor version register (pvr) table 6-6. msr field descriptions (continued) bits name description 4 datasheet u .com
core register summary MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 6-14 freescale semiconductor 6.5.4 system version register (svr) 6.6 timer registers 6.6.1 timer control register (tcr) table 6-7. pvr field descriptions bits name description 32?47 version a 16-bit number that identif ies the version of the processor. different version numbers indicate major differences between processors, such as which optional facilities and instructi ons are supported. (see section 5.2, ?e500 processor and system version numbers ,? for specific values.) 48?63 revision a 16-bit number that dist inguishes between implementat ions of the version. different revision numbers indicate minor differences between processors having the same version number, such as clock rate and engineering change level. (see section 5.2, ?e500 processor and system version numbers ,? for specific values.) spr 1023 access: supervisor read only 32 63 r system version w reset soc-dependent value. see section 5.2, ?e500 processor and system version numbers.? figure 6-9. system version register (svr) table 6-8. svr field descriptions bits name description 32?63 system version a 16-bit number th at identifies the soc version. see section 5.2, ?e500 processor and system version numbers ,? for specific values. spr 340 access: supervisor read/write 32 33 34 35 36 37 38 39 40 41 42 43 46 47 50 51 63 r wp wrc wie die fp fie are ? wpext fpext ? w reset all zeros figure 6-10. timer control register (tcr) 4 datasheet u .com
core register summary MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 6-15 6.6.2 timer status register (tsr) table 6-9. tcr field descriptions bits name description 32?33 wp watchdog timer period. when concatenated with wpext, specifies one of 64-bit locations of the time base used to signal a watchdog timer exception on a transition from 0 to 1. wpext[0?3] || wp[0?1] = 0b00_0000 selects tbu[32] (the msb of the tb) wpext[0?3] || wp[0?1] = 0b11_1111 select s tbl[63] (the lsb of the tb) 34?35 wrc watchdog timer reset control. this value is wr itten into tsr[wrs] when a watchdog event occurs. wrc may be set by software but cannot be cleared by software, except by a software-induced reset. once written to a non-zero value, wrc may no longer be altered by software. 00 no watchdog timer reset will occur. 01 if msr[me] = 0, the second timeout is ignored. if msr[me] = 1, a machine check condition occurs on a second timeout of the watchdog timer, and if hid0[emcp] = 1, the machine check interrupt is generated. 10 assert processor reset output ( core_hreset_req ) on second timeout of watchdog timer 11 reserved 36 wie watchdog timer interrupt enable 0 watchdog timer interrupts disabled 1 watchdog timer interrupts enabled 37 die decrementer interrupt enable 0 decrementer interrupts disabled 1 decrementer interrupts enabled 38?39 fp fixed interval timer period. when concatenated with fpext, fp specifies one of 64 bit locations of the time base used to signal a fixed-interval timer exception on a transition from 0 to 1. fpext[0?3] || fp[0?1] = 0b00_0000 select s tbu[32] (the msb of the tb) fpext[0?3] || fp[0?1] = 0b11_1111 select s tbl[63] (the lsb of the tb) 40 fie fixed interval interrupt enable 0 fixed interval interrupts disabled 1 fixed interval interrupts enabled 41 are auto-reload enable. controls whether the decar va lue is reloaded into the dec when the dec value reaches 0000_0001. see eref: a reference for freescale book e and the e500 core . 0 auto-reload disabled 1 auto-reload enabled 42 ? reserved, should be cleared. 43?46 wpext watchdog timer period extension (see the description for wp) 47?50 fpext fixed-interval timer period extension (see the description for fp) 51?63 ? reserved, should be cleared. spr 336 access: supervisor w1c 1 32 33 34 35 36 37 38 63 r enw wis wrs dis fis ? w w1c w1c w1c w1c w1c reset all zeros 1 set by hardware. read with mfspr and cleared with mtspr by writing ones to any tsr bit positions to be cleared and zeros in all other bit positions. figure 6-11. timer status register (tsr) 4 datasheet u .com
core register summary MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 6-16 freescale semiconductor 6.6.3 time base registers 6.6.4 decrementer register table 6-10. tsr field descriptions bits name description 32 enw enable next watchdog time. fu nctions as write-one-to-clear. 0 action on next watchdog timer time-out is to set tsr[enw] 1 action on next watchdog timer time-out is governed by tsr[wis] when a watchdog timer time-out occurs while wi s = 0 and the next watchdog time-out is enabled (enw = 1), a watchdog timer exception is generated and logged by setting wis. this is referred to as a watchdog timer first time out. a watchdog timer interrupt occurs if enabled by tcr[wie] and msr[ce]. to avoid another watchdog timer inte rrupt once msr[ce] is reenabled, (assuming tcr[wie] is not cleared instead), the interrupt handler must reset tsr[wis]. 33 wis watchdog timer interrupt status. functions as write-one-to-clear. 0 a watchdog timer event has not occurred. 1 a watchdog timer event occurred. when ms r[ce] = 1 and tcr[wie] = 1, a watchdog timer interrupt is taken. see the description of enw for more information about how wis is used. 34?35 wrs watchdog timer reset status. functions as writ e-one-to-clear. defined at reset (value = 00). set to tcr[wrc] when a reset is caused by the watchdog timer. 36 dis decrementer interrupt status. functions as write-one-to-clear. 0 a decrementer event has not occurred. 1 a decrementer event occurred. when msr[ee] = tcr[die] = 1, a decrementer interrupt is taken. 37 fis fixed-interval timer interrupt status. functions as write-one-to-clear. 0 a fixed-interval timer event has not occurred. 1 a fixed-interval timer event occurred. when msr[ee] = 1 and tcr[fie] = 1, a fixed-interval timer interrupt is taken. 38?63 ? reserved, should be cleared. spr tbu: 269 read/285 write tbl: 268 read/284 write access: user read/supervisor write 32 63 32 63 r tbu tbl w reset all zeros figure 6-12. time base upper/lower registers (tbu/tbl) spr 22 access: supervisor read/write 32 63 r decrementer value w reset all zeros figure 6-13. decrementer register (dec) 4 datasheet u .com
core register summary MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 6-17 6.6.5 decrementer auto-rel oad register (decar) 6.7 interrupt registers 6.7.1 interrupt registers defined by the embedded and base categories 6.7.1.1 save/restore register 0 (srr0) 6.7.1.2 save/restore register 1 (srr1) 6.7.1.3 critical save/restore register 0 (csrr0) spr 54 access: supervisor write only 32 63 r w decrementer auto-reload value reset all zeros figure 6-14. decrementer auto-reload register (decar) spr 26 access: supervisor read/write 32 63 r next instruction address w reset all zeros figure 6-15. save/restore register 0 (srr0) spr 27 access: supervisor read/write 32 63 r msr state information w reset all zeros figure 6-16. save/restore register 1 (srr1) spr 58 access: supervisor read/write 32 63 r next instruction address w reset all zeros figure 6-17. critical save/restore register 0 (csrr0) 4 datasheet u .com
core register summary MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 6-18 freescale semiconductor 6.7.1.4 critical save/restore register 1 (csrr1) 6.7.1.5 data exception address register (dear) 6.7.1.6 interrupt vector prefix register (ivpr) 6.7.1.7 interrupt vector offset registers (ivor n ) spr 59 access: supervisor read/write 32 63 r msr state information w reset all zeros figure 6-18. critical save/restore register 1 (csrr1) spr 61 access: supervisor read/write 32 63 r exception address w reset all zeros figure 6-19. data exception address register (dear) spr 63 access: supervisor read/write 32 47 48 63 r interrupt vector prefix ? w reset all zeros figure 6-20. interrupt vector prefix register (ivpr) spr (see ta b l e 6 - 1 1 .) access: supervisor read/write 32 47 48 59 60 63 r ? interrupt vector offset ? w reset all zeros figure 6-21. interrupt vector offset registers (ivor n ) table 6-11. ivor assignments ivor number spr interrupt type ivor0 400 critical input ivor1 401 machine check ivor2 402 data storage ivor3 403 instruction storage ivor4 404 external input 4 datasheet u .com
core register summary MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 6-19 6.7.1.8 exception syndrome register (esr) ivor5 405 alignment ivor6 406 program ivor8 408 system call ivor10 410 decrementer ivor11 411 fixed-interval timer interrupt ivor12 412 watchdog timer interrupt ivor13 413 data tlb error ivor14 414 instruction tlb error ivor15 415 debug ivor16?ivor31 ? reserved for future architectural use ivor32 528 spe unavailable ivor33 529 floating-point data exception ivor34 530 floating-point round exception ivor35 531 performance monitor ivor36?ivor63 ? allocated for implementation-dependent use spr 62 access: supervisor read/write 32 35 36 37 38 39 40 41 42 43 44 45 46 47 55 56 57 63 r ? pil ppr ptr ? st ? dlk ilk ? bo ? spe ? w reset all zeros figure 6-22. exception syndrome register (esr) table 6-12. esr field descriptions bits name syndrome interrupt types 32?35 ? reserved, should be cleared. ? 36 pil illegal instruction exception program 37 ppr privileged instruction exception program 38 ptr trap exception program 39 ? reserved and permanently cleared because the e500 does not implement this fpu. setting it has no effect. ? 40 st store operation alignment, data storage, data tlb error table 6-11. ivor assignments (continued) ivor number spr interrupt type 4 datasheet u .com
core register summary MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 6-20 freescale semiconductor 6.7.2 additional interrupt registers 6.7.2.1 machine check save/restore register 0 (mcsrr0) 6.7.2.2 machine check save/restore register 1 (mcsrr1) 41 ? reserved, should be cleared. ? 42 dlk cache locking. settings are implementation-dependent. 0default 1 on the e500, dlk is set when a dsi occurs because dcbtls , dcbtstls , or dcblc is executed in user mode while msr[ucle] = 0. data storage 43 ilk set when a dsi occurs because icbtl or icblc is executed in user mode (msr[pr] = 1) and msr[ucle] = 0 data storage 44?45 ? reserved, should be cleared. 46 bo byte-ordering exception data storage, instruction storage 47?55 ? reserved, should be cleared. ? 56 spe spe exception bit (e500-specific) 0default 1 any exception caused by an spe or spfp instruction spe unavailable 57?63 ? reserved, should be cleared. ? spr 570 access: supervisor read/write 32 63 r next instruction address w reset all zeros figure 6-23. machine check save/restore register 0 (mcsrr0) spr 571 access: supervisor read/write 32 63 r msr state information w reset all zeros figure 6-24. machine check save/restore register 1 (mcsrr1) table 6-12. esr field descriptions (continued) bits name syndrome interrupt types 4 datasheet u .com
core register summary MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 6-21 6.7.2.3 machine check address register (mcar) 6.7.2.4 machine check syndrome register (mcsr) spr 573 access: supervisor read only 32 63 r machine check address w reset all zeros figure 6-25. machine chec k address register (mcar) spr 572 access: supervisor read/write 32 33 34 35 36 39 r mcp icperr dcp_perr dcperr ? w reset all zeros 40 47 r ? w reset all zeros 48 55 r ? w reset all zeros 56 57 58 59 60 61 62 63 r bus_iaerr bus_raerr bus_waerr bus_iberr b us_rberr bus_wberr bus_iperr bus_rperr w reset all zeros figure 6-26. machine check syndrome register (mcsr) table 6-13. mcsr field descriptions bits name description 32 mcp machine check input pin 33 icperr instruction cache parity error 34 dcp_perr data cache push parity error 35 dcperr data cache parity error 36?55 ? reserved, should be cleared. 56 bus_iaerr bus instruction address error 57 bus_raerr bus read address error 58 bus_waerr bus write address error 4 datasheet u .com
core register summary MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 6-22 freescale semiconductor 6.8 software-use sprs (s prg0?sprg7 and usprg0) 59 bus_iberr bus instruction data bus error 60 bus_rberr bus read data bus error 61 bus_wberr bus write bus error 62 bus_iperr bus instruction parity error 63 bus_rperr bus read parity error spr see ta bl e 6 - 1 4 . access: see ta b l e 6 - 1 4 . 32 63 r software-determined information w reset all zeros figure 6-27. software-use sprs (sprg0?sprg7 and usprg0) table 6-14. spr assignments name spr access level sprg0 272 read/write supervisor sprg1 273 read/write supervisor sprg2 274 read/write supervisor sprg3 259 read only user/supervisor 275 read/write supervisor sprg4 260 read only user/supervisor 276 read/write supervisor sprg5 261 read only user/supervisor 277 read/write supervisor sprg6 262 read only user/supervisor 278 read/write supervisor sprg7 263 read only user/supervisor 279 read/write supervisor usprg0 256 read/write user/supervisor table 6-13. mcsr field descriptions (continued) bits name description 4 datasheet u .com
core register summary MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 6-23 6.9 branch target buffer (btb) registers 6.9.1 branch buffer entry address register (bbear) 6.9.2 branch buffer target address register (bbtar) spr 513 access: user read/write 32 61 62 63 r branch buffer entry address iab[0?1] w reset all zeros figure 6-28. branch buffer entry address register (bbear) table 6-15. bbear field descriptions bits name description 32?61 branch buffer entry address branch buffer entry effective address bits 0?29 62?63 iab[0?1] instruction after branch (with bbtar[62]). 3-bit pointer that points to the instruction in the cache line after the branch. see th e description in the bblels instruction in the eref. if the branch is the last instruction in the cache block, iab = 000, to indicate the next sequential instruction, which resides in the zeroth position of the next cache block. spr 514 access: user read/write 32 61 62 63 r branch buffer target address iab2 bdirpr w reset all zeros figure 6-29. branch buffer target address register (bbtar) table 6-16. bbtar field descriptions bits name description 32?61 branch buffer target address branch buffer target effective address bits 0?29 62 iab2 instruction after branch bit 2 ( with bbear[62?63]). iab is a 3-bit pointer that poin ts to the instruction in the cache line after the branch. see the description for bblels in the eref. if the branch is the last instruction in the cache block, iab = 000, to indicate the next sequential instruction, which resides in the zeroth position of the next cache block. 63 bdirpr branch direction prediction. the user c an pick the direction of the predicted branch. 0 the locked address is always predicted as not taken. 1 the locked address is always predicted as taken. 4 datasheet u .com
core register summary MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 6-24 freescale semiconductor 6.9.3 branch unit control and status register (bucsr) spr 1013 access: supervisor read/write 32 53 54 55 56 57 58 62 63 r ? bbfi bblo bbul bblfc ? bpen w reset all zeros figure 6-30. branch unit control and status register (bucsr) table 6-17. bucsr field descriptions bits name description 32?53 ? reserved, should be cleared. 54 bbfi branch buffer flash invalidate. clearing and then sett ing bbfi flash clears the valid bit of all entries in the branch buffer; clearing occurs independently from the valu e of the enable bit (bpen). bbfi is always read as 0. 55 bblo branch buffer lock overflow status 0 indicates a lock overflow condition was not encountered in the branch buffer 1 indicates a lock overflow condition was encountered in the branch buffer this sticky bit is set by hardware and is cleared by writing 0 to this bit location. 56 bbul branch buffer unable to lock 0 indicates a lock overflow condition in the branch buffer 1 indicates a lock set instruction failed in the branch buffer, for example, if the btb is disabled. this sticky bit is set by hardware and is cleared by writing 0 to this bit location. 57 bblfc branch buffer lock bits flash clear. clearing and then setting bblfc flash clears the lock bit of all entries in the branch buffer; clearing occurs independently from t he value of the enable bit (bpen). bblfc is always read as 0. 58?62 ? reserved, should be cleared. 63 bpen branch prediction enable 0 branch prediction disabled 1 branch prediction enabled (enables btb to predict branches) 4 datasheet u .com
core register summary MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 6-25 6.10 hardware implementation-dependent registers 6.10.1 hardware implementation-d ependent register 0 (hid0) spr 1008 access: supervisor read/write 32 33 39 40 41 42 43 47 r emcp ? doze nap sleep ? w reset all zeros 48 49 50 51 62 63 r ? tben sel_tbclk ? nopti w reset all zeros figure 6-31. hardware implementation-dependent register 0 (hid0) table 6-18. hid0 field descriptions bits name description 32 emcp enable machine check pin, mcp . used to mask out further machine check exceptions caused by assertion of mcp . 0mcp is disabled. 1mcp is enabled. if mse[me] = 0, asserting mcp causes checkstop. if msr[me] = 1, asserting mcp causes a machine check exception. 33?39 ? reserved, should be cleared. 40 doze doze power management mode. if msr[we ] is set, this bit controls doze mode. 0 core not in doze mode 1 core in doze mode 41 nap nap power management mode. if msr[we] is set, this bit controls nap mode. 0 core not in nap mode 1 core in nap mode 42 sleep configure for sleep power management mode. controls sleep mode if msr[we] is set. 0 core not in sleep mode 1 core in sleep mode 43?48 ? reserved, should be cleared. 49 tben time base enable 0 time base disabled (no counting) 1 time base enabled ? if hid0[tben] = 1 and hid0[sel_tbclk] = 0, the time base is updated every 8 bus clocks ? if hid0[tben] = 1 and hid0[sel_tbclk] = 1, th e time base is updated on the rising edge of core_tbclk (sampled at bus rate). the maximum supported frequency can be found in the electrical specifications, but this value is approximately 25% of the bus clock frequency. 50 sel_tbclk select time base clock. if the time base is enabled, this field functions as follows: 0 time base is based on the processor clock 1 time base is based on the tbclk (rtc) input 4 datasheet u .com
core register summary MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 6-26 freescale semiconductor 6.10.2 hardware implementation-d ependent register 1 (hid1) 51?62 ? reserved, should be cleared. 63 nopti no-op the data and instruct ion cache touch instructions. 0 dcbt , dcbtst , and icbt are enabled. on the e500, if ct = 0, icbt is always a no-op, regardless of the value of nopti. if ct = 1, icbt does a touch load to an l2 cache, if one is present. 1 dcbt , dcbtst , and icbt are treated as no-ops; dcblc and dcbtls are not. spr 1009 access: supervisor read/write 32 33 34 39 40 45 46 47 r pll_mode pll_cfg ? rfxe ? w reset all zeros 48 49 50 51 52 63 r ? astme abe ? w reset all zeros figure 6-32. hardware implementation-dependent register 1 (hid1) table 6-19. hid1 field descriptions bits name description 32?33 pll_mode read-only for integrated devices. 01 fixed value for MPC8555E 34?39 pll_cfg reflected directly from configuration input pi ns (read-only). pll_cfg[0?4] corresponds to the integer divide ratio and pll_cfg5 is the half-mode bit. the following values are supported: 0001_00 ratio of 2:1 0001_01 ratio of 5:2 (2.5:1) 0001_10 ratio of 3:1 0001_11 ratio of 7:2 (3.5:1) note that this value is also re flected to porpllsr[e500_ratio]. see section 18.4.1.1, ?por pll status register (porpllsr).? 40?45 ? reserved, should be cleared. table 6-18. hid0 field de scriptions (continued) bits name description 4 datasheet u .com
core register summary MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 6-27 46 rfxe read fault exception enable. enables the core to internally generate a machine check interrupt when core_fault_in is asserted. depending on the value of msr[me], this results in either a machine check interrupt or a checkstop. 0 assertion of core_fault_in cannot cause a machine check. the e500 does not stall when faulty instructions or data are received, as described in the following note. note: the e500 does not stall when faulty instructions or data are received. instead, it continues processing with faulty instructions or data. the only re liable way to prevent such behavior is to set rfxe, which causes a machine check before the faulty instruct ions or data are used. to avoid the use of faulty instructions or data and to have good error determination, software must set rfxe and program the pic to interrupt the processor when errors occur. as a re sult, software must deal with multiple interrupts for the same fundamental problem. 1 assertion of core_fault_in causes a machine check if msr[me] = 1 or a checkstop if msr[me] = 0. the core_fault_in signal is asserted to the core when logic outside of the core has a problem delivering good data to the core. for example, the front-side l2 cache asserts core_fault_in when an ecc error occurs and ecc is enabled. as a second ex ample, it is asserted when there is a master abort on a pci transaction. see ?proper reporting of bus faults? in the core complex bus chapter of the powerpc? e500 core family reference manual . the rfxe bit provides flexibility in error recovery. typically, devices outside the core have some way other than the assertion of core_fault_in to signal the core that an error occurred. usually, this is done by channeling interrupt requests through a programmable interrupt controller (pic) to the core. in these cases, the assertion of core_fault_in is used only to prevent the core from using bad data before receiving an interrupt from the pic (for example, an external or critical input interrupt). possible combinations of rfxe and pic configuration are as follows: ? rfxe = 0 and the pic is configured to interrupt the processor. in this configuration, the assertion of core_fault_in does not trigger a machine check interrupt. however, there is a possibility that the core might use faulty data or instructions. the pic inte rrupts the core so that error recovery can begin. this configuration allows the core to query the pi c and the rest of the system for more information about the cause of the interrupt, and generally provides the best error recovery capabilities. ? rfxe = 1 and the pic is not configured to interrupt the processor. this configuration provides quick error detection without the overhead of configuring the pic. when the pic is not configured, setting rfxe avoids stalling the core when core_fault_in is asserted. determination of the root cause of the problem may be somewhat more difficult than it would be if the pic were enabled. ? rfxe = 1 and the pic is configured to interrupt t he processor. in this configuration, the core may receive two interrupts for the same fundamental e rror. the two interrupts may occur in any order, which may complicate error handling. therefore, this is usually not an interesting configuration for a single-core device. this may, however, be an interesting configuration for multi-core devices in which the pic may steer interrupts to a processor other than the one that attempted to fetch the faulty data. ? rfxe = 0 and the pic is not configured to inte rrupt the processor. this is not a recommended configuration. the processor may stall indefinitely due to an unreported error. 47?49 ? reserved, should be cleared. 50 astme address bus streaming mode enable. this bit, al ong with the ecm st ream control bits in the eebacr, enables address bus streaming on the ccb. see section 8.2.1.1, ?ecm ccb address configuration register (eebacr).? 0 address bus streaming mode disabled 1 address bus streaming mode enabled table 6-19. hid1 field de scriptions (continued) bits name description 4 datasheet u .com
core register summary MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 6-28 freescale semiconductor 6.11 l1 cache configuration registers 6.11.1 l1 cache control and st atus register 0 (l1csr0) 51 abe address broadcast enable. the e500 broadcasts cache management instructions ( dcbst , dcblc (ct = 1), icblc (ct = 1), dcbf , dcbi , mbar , msync , tlbsync , icbi ) based on abe. abe must be set to allow management of external l2 caches. 0 address broadcasting disabled 1 address broadcasting enabled 52?63 ? reserved, should be cleared. spr 1010 access: supervisor read/write line locking bits 32 46 47 48 49 51 52 53 54 55 56 61 62 63 r ? cpe cpi ? cslc cul clo clfr ? cfi ce w reset all zeros figure 6-33. l1 cache control and status register 0 (l1csr0) table 6-20. l1csr0 field descriptions bits name description 32?46 ? reserved, should be cleared. 47 cpe (data) cache parity enable 0 parity checking of the cache disabled 1 parity checking of the cache enabled 48 cpi (data) parity error injection enable 0 parity error injection disabled 1 parity error injection enabled. cache parity must also be enabled (cpe = 1) when this bit is set. 49?51 ? reserved, should be cleared. 52 cslc (data) cache snoop lock clear. sticky bit set by hardware if a dcbi snoop (either internally or externally generated) invalidated a locked cache line. note that the lock bit for that line is cleared whenever the line is invalidated. this bit can be cleared only by software. 0 the cache has not encountered a dcbi snoop that invalidated a locked line. 1 the cache has encountered a dcbi snoop that invalidated a locked line. 53 cul (data) cache unable to lock. sticky bit set by hardware and cleared by writing 0 to this bit location. 0 indicates a lock set instructio n was effective in the cache 1 indicates a lock set instruction was not effective in the cache 54 clo (data) cache lock overflow. sticky bit set by hardware and cleared by writing 0 to this bit location. 0 indicates a lock overflow condition was not encountered in the cache 1 indicates a lock overflow condition was encountered in the cache table 6-19. hid1 field de scriptions (continued) bits name description 4 datasheet u .com
core register summary MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 6-29 6.11.2 l1 cache control and st atus register 1 (l1csr1) 55 clfr (data) cache lock bits flash reset. writing a 1 dur ing a flash clear operation causes an undefined operation. writing a 0 during a flash clear operation is ignored. clearing occurs regardless of the enable (ce) value. 0 default. 1 hardware initiates a cache lock bits flash clear operation. this bit is cleared when the operation is complete. 56?61 ? reserved, should be cleared. 62 cfi (data) cache flash invalidate. 0 no cache invalidate. writing a 0 to cfi during an invalidation operation is ignored. 1 cache invalidation operation. a cache invalidation operation is initiated by hardware. once complete, this bit is cleared. writing a 1 during an invalida tion operation causes an undefined operation. invalidation occurs regardless of the enable (ce) value. 63 ce (data) cache enable 0 the cache is neither accessed or updated. 1 enables cache operation spr 1011 access: supervisor read/write line locking bits 32 46 47 48 49 51 52 53 54 55 56 61 62 63 r ? icpe icpi ? icslc icul iclo iclfr ? icfi ice w reset all zeros figure 6-34. l1 cache control and status register 1 (l1csr1) table 6-21. l1csr1 field descriptions bits name description 32?46 ? reserved, should be cleared. 47 icpe instruction cache parity enable 0 parity checking of the instruction cache disabled 1 parity checking of the instruction cache enabled 48 icpi instruction parity error injection enable 0 parity error injection disabled 1 parity error injection enabled. note that instruction cache parity must also be enabled (icpe = 1) when this bit is set. 49?51 ? reserved, should be cleared. 52 icslc instruction cache snoop lock clear. sticky bit set by hardware if an icbi snoop (either internally or externally generated) invalidated a locked line in the instruction cach e. note that the lock bit for that line is cleared whenever the line is invalidated. this bit can only be cleared by software. 0 the instruction cache has not encountered an icbi snoop that invalidated a locked line. 1 the instruction cache has encountered an icbi snoop that invalidated a locked line. table 6-20. l1csr0 field descriptions (continued) bits name description 4 datasheet u .com
core register summary MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 6-30 freescale semiconductor 6.11.3 l1 cache configuration register 0 (l1cfg0) 53 icul instruction cache unable to lock. sticky bit set by hardware and cleared by writing 0 to this bit location. 0 indicates a lock set instruction was effective in the instruction cache 1 indicates a lock set instruction was no t effective in the instruction cache 54 iclo instruction cache lock overflow. sticky bit set by hardware and cleared by writing 0 to this bit location. 0 indicates a lock overflow condition was not encountered in the instruction cache 1 indicates a lock overflow condition was encountered in the instruction cache 55 iclfr instruction cache lock bits flas h reset. writing 0 and then 1 flash clears the lock bit of all entries in the instruction cache; clearing occurs independently from th e value of the enable bit (ice). iclfr is always read as 0. 56?61 ? reserved, should be cleared. 62 icfi instruction cache flash invalidate. written to 0 and then 1 to flash clear the valid bit of all entries in the instruction cache; operates independently from the value of the enable bit (ice). icfi is always read as 0. 63 ice instruction cache enable 0 the instruction cache is neither accessed or updated. 1 enables instruction cache operation spr 515 access: user read only 32 33 34 38 39 40 41 42 43 44 45 49 50 51 52 53 55 56 63 r carch ? cbsize crepl cla cpa ? cnway ? csize w reset0 0 00000 0 0 0 1 1 1 0000011100000100000 figure 6-35. l1 cache configuration register 0 (l1cfg0) table 6-22. l1cfg0 field descriptions bits name description 32?33 carch cache architecture 00 harvard 01 unified 34?38 ? reserved, should be cleared. 39?40 cbsize cache line size 032 bytes 164 bytes 41?42 crepl cache replacement policy 0 true lru 1 pseudo lru 43 cla cache locking available 0 unavailable 1 available table 6-21. l1csr1 field descriptions (continued) bits name description 4 datasheet u .com
core register summary MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 6-31 6.11.4 l1 cache configuration register 1 (l1cfg1) 44 cpa cache parity available 0 unavailable 1 available 45?49 ? reserved, should be cleared. 50?52 cnway cache number of ways 111 indicates 8 ways 53?55 ? reserved, should be cleared. 56?63 csize cache size 0x20 indicates 32 kbytes spr 516 access: user read only 32 38 39 40 41 42 43 44 45 52 53 63 r ? icbsize icrepl icla icpa icnway icsize w reset0000000 0 0 0 1 1 1 0000011100000100000 figure 6-36. l1 cache configuration register 1 (l1cfg1) table 6-23. l1cfg1 field descriptions bits name description 32?38 ? reserved, should be cleared. 39?40 icbsiz instruction cache block size 00 indicates block size of 32 bytes 41?42 icrepl instruction cache replacement policy 01 indicates pseudo-lru policy 43 icla instruction cache locking available 1 indicates available 44 icpa instruction cache parity available 1 indicates available 45?52 icnway instruction cache number of ways 111 indicates 8 ways 53?63 icsize instruction cache size 0x20 indicates 32 kbytes table 6-22. l1cfg0 field descriptions (continued) bits name description 4 datasheet u .com
core register summary MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 6-32 freescale semiconductor 6.12 mmu registers 6.12.1 process id registers (pid0?pid2) 6.12.2 mmu control and stat us register 0 (mmucsr0) 6.12.3 mmu configuration register (mmucfg) spr spr spr 48 (pid0) 633 (pid1) 634 (pid2) access: supervisor read/write 32 55 56 63 r ? process id w reset all zeros figure 6-37. process id registers (pid0?pid2) spr 1012 access: supervisor read/write 32 60 61 62 63 r ? l2tlb0_fi l2tlb1_fi ? w reset all zeros figure 6-38. mmu control and status register 0 (mmucsr0) table 6-24. mmucsr0 field descriptions bits name description 32?60 ? reserved, should be cleared. 61 l2tlb0_fi tlb0 flash invalidate (write to 1 to invalidate) 62 l2tlb1_fi tlb1 flash invalidate (write 1 to invalidate) 0 no flash invalidate. writing a 0 to this bit during an invalidation operation is ignored. 1 tlb1 invalidation operation. hardware initiates a tl b1 invalidation operation. when this operation is complete, this bit is cleared. writing a 1 dur ing an invalidation operation causes an undefined operation. 63 ? reserved, should be cleared. spr 1015 access: supervisor read only 32 48 49 52 53 57 58 59 60 61 62 63 r? npids pidsize ? ntlbs mavn w reset0000000000000000000110011100 0 1 0 0 figure 6-39. mmu configuration register (mmucfg) 4 datasheet u .com
core register summary MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 6-33 6.12.4 tlb configuration registers (tlb n cfg) 6.12.4.1 tlb0 configuratio n register 0 (tlb0cfg) table 6-25. mmucfg field descriptions bits name description 32?48 ? reserved, should be cleared. 49?52 npids number of pid registers, a 4-bit field that indica tes the number of pid register s provided by the processor. the e500 implements three pids. 53?57 pidsize pid register size. the 5-bit value of pidsize is one less than the number of bits in each of the pid registers implemented by the processor. the processo r implements only the least significant pidsize+1 bits in the pid registers. 00111 indicates 8-bit registers. this is the value presented by the e500. 58?59 ? reserved, should be cleared. 60?61 ntlbs number of tlbs. the value of ntlbs is one less than the number of software -accessible tlb structures that are implemented by the processor. ntlbs is se t to one less than the number of tlb structures so that its value matches the ma ximum value of mas0[tlbsel]. 00 1 tlb 01 2 tlbs. this is the value presented by the e500. 10 3 tlbs 11 4 tlbs 62?63 mavn mmu architecture version number. indicates th e version number of the architecture of the mmu implemented by the processor. 0b00 indicates version 1.0. spr 688 access: supervisor read only 32 39 40 43 44 47 48 49 50 51 52 63 r assoc minsize maxsize iprot avail ? nentry w reset00000010 00010001 0 0 000 00100000000 figure 6-40. tlb configuration register 0 (tlb0cfg) table 6-26. tlb0cfg field descriptions bits name description 32?39 assoc associativity of tlb0 0x02 indicates associativit y is 2-way set associative 40?43 minsize minimum page size of tlb0 0x1 indicates smallest page size is 4k 44?47 maxsize maximum page size of tlb0 0x1 indicates maximum page size is 4k 48 iprot invalidate protect capability of tlb0 0 indicates invalidate protection capability not supported 49 avail page size availability of tlb0 0 no variable-sized pages available (minsize = maxsize) 4 datasheet u .com
core register summary MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 6-34 freescale semiconductor 6.12.4.2 tlb1 configuratio n register 1 (tlb1cfg) 6.12.5 mmu assist registers 6.12.5.1 mas register 0 (mas0) 50?51 ? reserved, should be cleared. 52?63 nentry number of entries in tlb0 0x100 lb0 contains 256 entries spr 689 access: supervisor read only 32 39 40 43 44 47 48 49 50 51 52 63 r assoc minsize maxsize iprot avail ? nentry w reset0001000000011001 1 1 00000000010000 figure 6-41. tlb configuration register 1 (tlb1cfg) table 6-27. tlb1cfg field descriptions bits name description 32?39 assoc associativity of tlb1 0x10 indicates associativity is 16 40?43 minsize minimum page size of tlb1 0x1 indicates smallest page size is 4k 44?47 maxsize maximum page size of tlb1 0x9 indicates maximum page size is 256 mbyte 48 iprot invalidate protect capability of tlb1 1 indicates that tlb1 supports invalidate protection capability 49 avail page size availability of tlb1 1 indicates all page si zes between minsize and maxsize supported 50?51 ? reserved, should be cleared. 52?63 nentry number of entries in tlb1 0x010: tlb1 contains 16 entries spr 624 access: supervisor read/write 32 34 35 36 43 44 47 48 62 63 r ? tlbsel ? esel ? nv w reset all zeros figure 6-42. mas register 0 (mas0) table 6-26. tlb0cfg field descriptions (continued) bits name description 4 datasheet u .com
core register summary MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 6-35 6.12.5.2 mas register 1 (mas1) table 6-28. mas0 field descriptions?mmu read/write and replacement control bits name descriptions 32?34 ? reserved, should be cleared. 35 tlbsel selects tlb for access 0tlb0 1tlb1 36?43 ? reserved, should be cleared. 44?47 esel entry select. number of entry in selected array to be used for tlbwe . this field is also updated on tlb error exceptions (misses), and tlbsx hit and miss cases. only certain bits are valid, depending on the array selected in tlbsel. other bits should be 0. for the e500, esel serves as the way select for the corresponding tlb as follows: when tlbsel = 00 (tlb0 selected), only bit 47 is used (and bits 44?46 should be cleared). this bit selects between way 0 and way 1 of tlb0. ea bits 45?51 from mas2[epn] are used to index into the tlb to further select the entry for the operation. when tlbsel = 01 (tlb1 selected), all four bits are used to select one of 16 entries in the array. 48?62 ? reserved, should be cleared. 63 nv next victim. next victim bit value to be written to tlb0[nv] on execution of tlbwe . this field is also updated on tlb error exceptions (misses), tlbsx hit and miss cases and on execution of tlbre . this field is updated based on the calculated next victim bit for tlb0 (based on the round-robin replacement algorithm.) note that this field is not defined for operations t hat specify tlb1 (when tlbsel = 01). spr 625 access: supervisor read/write 32 33 34 39 40 47 48 50 51 52 55 56 63 r v iprot ? tid ?tstsize ? w reset all zeros figure 6-43. mas register 1 (mas1) table 6-29. mas1 field descriptions?descr iptor context and configuration control bits name descriptions 32 v tlb valid bit 0 this tlb entry is invalid. 1 this tlb entry is valid. 33 iprot invalidate protect. set to protect this tlb en try from invalidate operati ons due the execution of tlbiva [ x ] (tlb1 only). note that not all tlb arrays are necessarily prot ected from invalidation with iprot. arrays that support invalidate protection are denoted as su ch in the tlb configuration registers. 0 entry is not protected from invalidation 1 entry is protected from invalidation. 34?39 ? reserved, should be cleared. 40?47 tid translation identity. an 8-bit field that defines th e process id for this tlb entry. tid is compared with the current process ids of the three virtual address to be translated. a tid value of 0 defines an entry as global and matches with all process ids. 4 datasheet u .com
core register summary MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 6-36 freescale semiconductor 6.12.5.3 mas register 2 (mas2) 48?50 ? reserved, should be cleared. 51 ts translation space. this bit is compared with the is or ds fields of the msr (dep ending on the type of access) to determine if this tlb entry may be used for translation. 52?55 tsize translation size. defines the tlb entry page size. for arrays that contain fixed-size tlb entries, tsize is ignored. for variable page size arrays, the page size is 4 tsize kbytes. the e500 supports the following sizes: 0001 4 kbytes 0010 16 kbytes 0011 64 kbytes 0100 256 kbytes 0101 1 mbyte 0110 4 mbytes 0111 16 mbytes 1000 64 mbytes 1001 256 mbytes 56?63 ? reserved, should be cleared. spr 626 access: supervisor read/write 32 51 52 56 57 58 59 60 61 62 63 r epn ?x0x1wimge w reset all zeros figure 6-44. mas register 2 (mas2) table 6-30. mas2 field descriptions?epn and page attributes bits name description 32?51 epn effective page number. depending on page size, on ly the bits associated with a page boundary are valid. bits that represent offsets within a page are ignored and should be cleared. 52?56 ? reserved for implementation-specific use 57 x0 implementation-dependent page attribute 58 x1 implementation-dependent page attribute 59 w write-through 0 this page is considered write-back with respect to the caches in the system. 1 all stores performed to this page are written through the caches to main memory. 60 i caching-inhibited 0 accesses to this page are considered cacheable. 1 the page is considered caching-inhibited. all loads and stores to the page bypass the caches and are performed directly to main memory. 61 m memory coherency required 0 memory coherency is not required. 1 memory coherency is required. this allows loads and stores to this page to be coherent with loads and stores from other processo rs (and devices) in the system, assuming all such devices are participating in the coherency protocol. table 6-29. mas1 field descriptions?descripto r context and configuration control (continued) bits name descriptions 4 datasheet u .com
core register summary MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 6-37 6.12.5.4 mas register 3 (mas3) 6.12.5.5 mas register 4 (mas4) 62 g guarded 0 accesses to this page are not guarded and can be performed before it is known if they are required by the sequential execution model. 1 all loads and stores to this page that miss in the l1 cache are performed without speculation (that is, they are known to be required). speculative loads can be pe rformed if they hit in the l1 cache. in addition, accesses to caching-inhibited pages are performed us ing only the memory elem ent that is explicitly specified. 63 e endianness. determines endianness for the corresponding page. little-endian operation is true little endian, which differs from the modified little-endian byte-ordering model optionally available in previous devices that implement the original powerpc architecture. see the powerpc? e500 core family reference manual for more information. 0 the page is accessed in big-endian byte order. 1 the page is accessed in true little-endian byte order. spr 627 access: supervisor read/write 32 51 52 53 54 57 58 59 60 61 62 63 r rpn ? u0?u3 ux sx uw sw ur sr w reset all zeros figure 6-45. mas register 3 (mas3) table 6-31. mas3 field descript ions?rpn and access control bits name description 32?51 rpn real page number. depending on page size, only the bits associated with a page boundary are valid. bits that represent offsets within a page are ignored and should be cleared. 52?53 ? reserved, should be cleared. 54?57 u0?u3 user attribute bits. associated with a tlb entry and can be used by system software. for example, they can hold information useful to a page-scanning algorithm or mark more abstract page attributes. 58?63 permis permission bits (ux, sx, uw, sw, ur, sr). user and supervisor read, write, and execute permission bits. spr 628 access: supervisor read/write 32 34 35 36 45 46 47 48 50 51 52 55 56 57 58 59 60 61 62 63 r ? tlbseld ? tidseld ? tsized ? x0d x1d wd id md gd ed w reset all zeros figure 6-46. mas register 4 (mas4) table 6-30. mas2 field descriptions?epn and page attributes (continued) bits name description 4 datasheet u .com
core register summary MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 6-38 freescale semiconductor 6.12.5.6 mas register 6 (mas6) table 6-32. mas4 field descriptions?hardware replacement assist configuration bits name description 32?34 ? reserved, should be cleared. 35 tlbseld tlbsel default value. the default value to be loaded in mas0[tlbsel] on a tlb miss exception. 0tlb0 1tlb1 36?45 ? reserved, should be cleared. 46?47 tidseld tid default selection value. a 2-bit field that sp ecifies which of the current pid registers should be used to load the mas1[tid] fiel d on a tlb miss exception. the e500 implementation defines this field as follows: 00 pid0 01 pid1 10 pid2 11 tidz (0x00) (all zeros) 48?51 ? reserved, should be cleared. 52?55 tsized default tsize value. specifies the default value to be loaded into mas1[tsize] on a tlb miss exception. 56 ? reserved, should be cleared. 57 x0d default x0 value. specifies the default value to be loaded into mas2[x0] on a tlb miss exception. 58 x1d default x1 value. specifies the default value to be loaded into mas2[x1] on a tlb miss exception. 59 wd default w value. specifies the default value to be loaded into mas2[w] on a tlb miss exception. 60 id default i value. specifies the default value to be loaded into mas2[i] on a tlb miss exception. 61 md default m value. specifies the default value to be loaded into mas2[m] on a tlb miss exception. 62 gd default g value. specifies the default value to be loaded into mas2[g] on a tlb miss exception. 63 ed default e value. specifies the default value to be loaded into mas2[e] on a tlb miss exception. spr 630 access: supervisor read/write 32 39 40 47 48 62 63 r ? spid0 ? sas w reset all zeros figure 6-47. mas register 6 (mas6) table 6-33. mas6?tlb search context register 0 bits name comments, or function when set 32?39 ? reserved, should be cleared. 40?47 spid0 specifies the pid value (recent value of pi d0) used when searching the tlb during execution of tlbsx . 48?62 ? reserved, should be cleared. 63 sas address space (as) value for searches. specifies the value of as used when searching the tlb (during execution of tlbsx ). 4 datasheet u .com
core register summary MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 6-39 6.13 debug registers 6.13.1 debug control registers (dbcr0?dbcr2) 6.13.1.1 debug control register 0 (dbcr0) spr 308 access: supervisor read/write 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 62 63 r ? idm rst icmp brt irpt trap iac1 iac2 ? dac1 dac2 ret ? ft w reset all zeros figure 6-48. debug control register 0 (dbcr0) table 6-34. dbcr0 field descriptions bits name description 32 ? reserved, should be cleared. 33 idm internal debug mode 0 debug interrupts are disabled. no debug interrupts are taken and debug events are not logged. 1 if msr[de] = 1, the occurrence of a debug event or t he recording of an earlier debug event in the dbsr when msr[de] = 0 or dbcr0[idm] = 0 causes a debug interrupt. programming note: software must clear debug event status in the dbsr in the debug interrupt handler when a debug interrupt is taken before re-enabling interrupts through msr[de]. otherwise, redundant debug interrupts are taken for the same debug event. 34?35 rst reset. the e500 implements these bits as follows: 0 x default (no action) 1 x causes a hard reset if msr[de] and dbcr0[idm] are set. always cleared on subsequent cycle. this causes a hard reset to the core only. 36 icmp instruction completion debug event enable 0 icmp debug events are disabled 1 icmp debug events are enabled note: instruction completion does not cause an icmp debug event if msr[de] = 0. 37 brt branch taken debug event enable 0 brt debug events are disabled 1 brt debug events are enabled note: taken branches do not caus e a brt debug event if msr[de] = 0. 38 irpt interrupt taken debug event enable. this bit affects only noncritical interrupts. 0 irpt debug events are disabled 1 irpt debug events are enabled 39 trap trap debug event enable 0 trap debug events cannot occur 1 trap debug events can occur 40 iac1 instruction address compare 1 debug event enable 0 iac1 debug events cannot occur 1 iac1 debug events can occur 4 datasheet u .com
core register summary MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 6-40 freescale semiconductor 6.13.1.2 debug control register 1 (dbcr1) 41 iac2 instruction address compare 2 debug event enable 0 iac2 debug events cannot occur 1 iac2 debug events can occur 42?43 ? reserved, should be cleared. 44?45 dac1 data address compare 1 debug event enable 00 dac1 debug events cannot occur 01 dac1 debug events can occur only if a store-type data storage access 10 dac1 debug events can occur only if a load-type data storage access 11 dac1 debug events can occur on any data storage access 46?47 dac2 data address compare 2 debug event enable 00 dac2 debug events cannot occur 01 dac2 debug events can occur only if a store-type data storage access 10 dac2 debug events can occur only if a load-type data storage access 11 dac2 debug events can occur on any data storage access 48 ret return debug event enable 0 ret debug events cannot occur 1 ret debug events can occur note: an rfci does not cause an ret debug event if msr[de] = 0 at the time that rfci executes. 49?62 ? reserved, should be cleared. 63 ft freeze timers on debug event 0 enable clocking of timers 1 disable clocking of timers if any dbsr bit is set (except mrr) spr 309 access: supervisor read/write 32 33 34 35 36 37 38 39 40 41 42 63 r iac1us iac1er iac2us iac2er iac12m ? w reset all zeros figure 6-49. debug control register 1 (dbcr1) table 6-35. dbcr1 field descriptions bits name description 32?33 iac1us instruction address compare 1 user/supervisor mode 00 iac1 debug events can occur 01 reserved 10 iac1 debug events can occur only if msr[pr] = 0 11 iac1 debug events can occur only if msr[pr] = 1 34?35 iac1er instruction address compare 1 effective/real mode 00 iac1 debug events are based on effective addresses 01 reserved on the e500 10 iac1 debug events are based on effective addresses and can occur only if msr[is] = 0 11 iac1 debug events are based on effective addresses and can occur only if msr[is] = 1 table 6-34. dbcr0 field descriptions (continued) bits name description 4 datasheet u .com
core register summary MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 6-41 6.13.1.3 debug control register 2 (dbcr2) 36?37 iac2us instruction address compare 2 user/supervisor mode 00 iac2 debug events can occur 01 reserved 10 iac2 debug events can occur only if msr[pr] = 0 11 iac2 debug events can occur only if msr[pr] = 1 38?39 iac2er instruction address compare 2 effective/real mode 00 iac2 debug events are based on effective addresses 01 reserved on the e500 10 iac2 debug events are based on effective addresses and can occur only if msr[is] = 0 11 iac2 debug events are based on effective addresses and can occur only if msr[is] = 1 40?41 iac12m instruction address compare 1/2 mode 00 exact address compare. iac1 debug events can occur only if the address of the instruction fetch is equal to the value specified in iac1. iac2 debug even ts can occur only if the address of the instruction fetch is equal to the value specified in iac2. 01 address bit match. iac1 and iac2 debug events can o ccur only if the address of the instruction fetch, anded with the contents of iac2 are equal to the co ntents of iac1, plus anded with the contents of iac2. if iac1us iac2us or iac1er iac2er, results are boundedly undefined. 10 inclusive address range compare. iac1 and iac2 debug events occur only if the address of the instruction fetch is greater than or equal to the value specified in iac1 and less than the value specified in iac2. if iac1us iac2us or iac1er iac2er, results are boundedly undefined. 11 exclusive address range compare. iac1 and iac2 debug events occur only if the address of the instruction fetch is less than the value specified in ia c1 or is greater than or equal to the value specified in iac2. if iac1us iac2us or iac1er iac2er, results are boundedly undefined. 42?63 ? reserved, should be cleared. spr 310 access: supervisor read/write 32 33 34 35 36 37 38 39 40 41 42 63 r dac1us dac1er dac2us dac2er dac12m ? w reset all zeros figure 6-50. debug control register 2 (dbcr2) table 6-36. dbcr2 field descriptions bits name description 32?33 dac1us data address compare 1 user/supervisor mode 00 dac1 debug events can occur 01 reserved 10 dac1 debug events can occur only if msr[pr] = 0. 11 dac1 debug events can occur only if msr[pr] = 1. table 6-35. dbcr1 field descriptions (continued) bits name description 4 datasheet u .com
core register summary MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 6-42 freescale semiconductor 6.13.2 debug status register (dbsr) 34?35 dac1er data address compar e 1 effective/real mode 00 dac1 debug events are based on effective addresses. 01 reserved on the e500 10 dac1 debug events are based on effectiv e addresses and can occur only if msr[ds] = 0. 11 dac1 debug events are based on effectiv e addresses and can occur only if msr[ds] = 1. 36?37 dac2us data address compare 2 user/supervisor mode 00 dac2 debug events can occur. 01 reserved 10 dac2 debug events can occur only if msr[pr] = 0. 11 dac2 debug events can occur only if msr[pr] = 1. 38?39 dac2er data address compar e 2 effective/real mode 00 dac2 debug events are based on effective addresses. 01 reserved on the e500 10 dac2 debug events are based on effectiv e addresses and can occur only if msr[ds] = 0. 11 dac2 debug events are based on effectiv e addresses and can occur only if msr[ds] = 1. 40?41 dac12m data address compare 1/2 mode 00 exact address compare. dac1 debug events can o ccur only if the address of the data storage access is equal to the value specified in dac1. dac2 debug events can occur only if the address of the data storage access is equal to the value specified in dac2. 01 address bit match. dac1 and dac2 debug events ca n occur only if the address of the data storage access, anded with the contents of dac2 are equa l to the contents of da c1, also anded with the contents of dac2. if dac1us dac2us or dac1er dac2er, results are boundedly undefined. 10 inclusive address range compare. dac1 and dac2 debug events can occur only if the address of the data storage access is greater than or equal to th e value specified in dac1 and less than the value specified in dac2. if dac1us dac2us or dac1er dac2er, results are boundedly undefined. 11 exclusive address range compare. dac1 and dac2 debug events can occur only if the address of the data storage access is less than the value specified in dac1 or is greater than or equal to the value specified in dac2. if dac1us dac2us or dac1er dac2er, results are boundedly undefined. 42?63 ? reserved, should be cleared. spr: 304 access: supervisor w1c 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 r ide ude mrr icmp brt irpt trap iac1 iac2 ? dac1r dac1w dac2r dac2w w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset00undefined00000000 0 0 0 0 48 49 63 r ret ? ww1c reset all zeros figure 6-51. debug status register (dbsr) table 6-36. dbcr2 field descriptions (continued) bits name description 4 datasheet u .com
core register summary MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 6-43 table 6-37. dbsr field descriptions bits name description 32 ide imprecise debug event. set if msr[de] = 0 and a debug event causes its respective dbsr bit to be set. functions as write-one-to-clear. 33 ude unconditional debug event. set if an unconditional debug event occurred. functions as write-one-to-clear. if ude (level sensitive, active low) is asserted, dbsr[ude] is affected as follows: msr[de] dbcr0[idm] action x 0 no action. 0 1 ude is set. 1 1 ude is set and a debug interrupt is taken. 34?35 mrr most recent reset. functions as write-one-to -clear. undefined at power-on. the e500 implements hreset as follows: 0x no hard reset occurred since this bit was last cleared by software. 1x the previous reset was a hard reset. 36 icmp instruction complete debug event. set if an instruction completion debug event occurred and dbcr0[icmp] = 1. functions as write-one-to-clear. 37 brt branch taken debug event. set if a branch taken debug event occurred (dbcr0[brt] = 1). functions as write-one-to-clear. 38 irpt interrupt taken debug event. set if an interrupt taken debug event occurred (dbcr0[irpt] = 1). functions as write-one-to-clear. 39 trap trap instruction debug event. set if a trap instruction debug event occurred (dbcr0[trap] = 1). functions as write-one-to-clear. 40 iac1 instruction address compare 1 debug event. set if an iac1 debug event occurred (dbcr0[iac1] = 1). functions as write-one-to-clear. 41 iac2 instruction address compare 2 debug event. set if an iac2 debug event occurred (dbcr0[iac2] = 1). functions as write-one-to-clear. 42?43 ? reserved, should be cleared 44 dac1r data address compare 1 read debug event. set if a read-type dac1 debug event occurred (dbcr0[dac1] = 10 or 11). functions as write-one-to-clear. 45 dac1w data address compare 1 write debug event. set if a write-type dac1 debug event occurred (dbcr0[dac1] = 01 or 11). functions as write-one-to-clear. 46 dac2r data address compare 2 read debug event. set if a read-type dac2 debug event occurred (dbcr0[dac2] = 10 or 11). functions as write-one-to-clear. 47 dac2w data address compare 2 write debug event. set if a write-type dac2 debug event occurred (dbcr0[dac2] = 01 or 11). functions as write-one-to-clear. 48 ret return debug event. set if a return debug event occurred (dbcr0[ret] = 1). functions as write-one-to-clear. 49?63 ? reserved, should be cleared. 4 datasheet u .com
core register summary MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 6-44 freescale semiconductor 6.13.3 instruction address compare registers (iac1?iac2) 6.13.4 data address compare registers (dac1?dac2) 6.14 signal processing and embedded floating-point status and control register (spefscr) spr 312 (iac1); spr 313 (iac2) access: supervisor read/write 32 61 62 63 r instruction address ? w reset all zeros figure 6-52. instruction address compare registers (iac1?iac2) spr 316 (dac1); spr 317 (dac2) access: supervisor read/write 32 63 r data address w reset all zeros figure 6-53. data address compare registers (dac1?dac2) spr: 512 access: user mixed 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 r sovh ovh fgh fxh finvh fdbzh funfh fovfh ? finxs finvs fdbzs funfs fovfs mode w reset all zeros 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 r sov ov fg fx finv fdbz funf fovf ? finxe finve fdbze funfe fovfe frmc w reset all zeros figure 6-54. signal processing and embedded floating-point status and control register (spefscr) table 6-38. spefscr field descriptions bits name function 32 sovh summary integer overflow high. set whenever an instruction (except mtspr ) sets ovh. sovh remains set until it is cleared by an mtspr[spefscr] . 33 ovh integer overflow high. an overfl ow occurred in the upper half of the register while exec uting a spe integer instruction high-word error bits status bits enable bits 4 datasheet u .com
core register summary MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 6-45 34 fgh embedded floating-point guard bit high. floating-point guard bit from the upper half. the value is undefined if the processor takes a floating-point exception due to input error, floating-point overflow, or floating-point underflow. 35 fxh embedded floating-point sticky bit high. floating bi t from the upper half. the value is undefined if the processor takes a floating-point exception due to inpu t error, floating-point overflow, or floating-point underflow. 36 finvh embedded floating-point invalid operation error high. se t when an input value on the high side is a nan, inf, or denorm. also set on a divide if both the dividend and divisor are zero. 37 fdbzh embedded floating-point divide by zero error high. set if the dividend is non-zero and the divisor is zero. 38 funfh embedded floating-point underflow error high 39 fovfh embedded floating-point overflow error high 40?41 ? reserved, should be cleared. 42 finxs embedded floating-point inexact st icky. finxs = finxs | fgh | fxh | fg | fx 43 finvs embedded floating-point invalid operation sticky. location for software to use when implementing true ieee floating point. 44 fdbzs embedded floating-point divide by zero sticky. fdbzs = fdbzs | fdbzh | fdbz 45 funfs embedded floating-point underflo w sticky. storage location for software to use when implementing true ieee floati ng point. 46 fovfs embedded floatin g-point overflow sticky. storage location fo r software to use when implementing true ieee floating point. 47 mode embedded floating-point mode (read only on e500) 48 sov integer summary overflow. set whenever an spe instruction (except mtspr ) sets ov. sov remains set until it is cleared by mtspr[spefscr] . 49 ov integer overflow. an overflow occurred in the lower half of the regist er while a spe integer instruction is being executed. 50 fg embedded floating-point guard bit. floating-point guard bi t from the lower half. the value is undefined if the processor takes a floating-point exception due to inpu t error, floating-point overflow, or floating-point underflow. 51 fx embedded floating-point sticky bit. floating bit from th e lower half. the value is undefined if the processor takes a floating-point exception due to input error, floating-point overflow, or floating-point underflow. 52 finv embedded floating-point invalid operation error. set when an input value on the high side is a nan, inf, or denorm. also set on a divide if both the dividend and divisor are zero. 53 fdbz embedded floating-point divide by zero error. set of the dividend is non-zero and the divisor is zero. 54 funf embedded floating-point underflow error 55 fovf embedded floating-point overflow error 56 ? reserved, should be cleared. 57 finxe embedded floating-point inexact enable table 6-38. spefscr field descriptions (continued) bits name function 4 datasheet u .com
core register summary MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 6-46 freescale semiconductor 6.14.1 accumulator (acc) 58 finve embedded floating-point invalid operation/input error exception enable 0 exception disabled 1 exception enabled if the exception is enabled, a floating -point data exception is taken if finv or finvh is set by a floating-point instruction. 59 fdbze embedded floating-point divide-by-zero exception enable 0 exception disabled 1 exception enabled if the exception is enabled, a floating-point data exception is taken if fdbz or fdbzh is set by a floating-point instruction. 60 funfe embedded floating-poin t underflow exception enable 0 exception disabled 1 exception enabled if the exception is enabled, a floating-point data exception is taken if funf or funfh is set by a floating-point instruction. 61 fovfe embedded floating-point overflow exception enable 0 exception disabled 1 exception enabled if the exception is enabled, a floating-point data exception is taken if fovf or fovfh is set by a floating-point instruction. 62?63 frmc embedded floating-point rounding mode control 00 round to nearest 01 round toward zero 10 round toward +infinity 11 round toward ?infinity access: user read/write 0313263 r upper word lower word w reset all zeros figure 6-55. accumulator (acc) table 6-39. acc field descriptions bits name function 0?31 upper word holds the upper-word accumulate value for spe multiply with accumulate instructions 32?63 lower word holds the lower-word accumulate value for spe multiply with accumulate instructions table 6-38. spefscr field descriptions (continued) bits name function 4 datasheet u .com
core register summary MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 6-47 6.15 performance monitor registers (pmrs) table 6-40. supervisor-level pmrs (pmr[5] = 1) abbreviation register name pmr number pmr[0?4] pmr[5?9] section/page pmc0 performance monitor counter 0 16 00000 10000 6.15.4/6-50 pmc1 performance monitor counter 1 17 00000 10001 pmc2 performance monitor counter 2 18 00000 10010 pmc3 performance monitor counter 3 19 00000 10011 pmgc0 performance monitor global control register 0 400 01100 10000 6.15.1/6-48 pmlca0 performance monitor local control a0 144 00100 10000 6.15.2/6-48 pmlca1 performance monitor local control a1 145 00100 10001 pmlca2 performance monitor local control a2 146 00100 10010 pmlca3 performance monitor local control a3 147 00100 10011 pmlcb0 performance monitor local control b0 272 01000 10000 6.15.3/6-49 pmlcb1 performance monitor local control b1 273 01000 10001 pmlcb2 performance monitor local control b2 274 01000 10010 pmlcb3 performance monitor local control b3 275 01000 10011 table 6-41. user-level pmrs (pmr[5] = 0) (read only) abbreviation register name pmr number pmr[0?4] pmr[5?9] section/page upmc0 user performance monitor counter 0 0 00000 00000 6.15.4/6-50 upmc1 user performance monitor counter 1 1 00000 00001 upmc2 user performance monitor counter 2 2 00000 00010 upmc3 user performance monitor counter 3 3 00000 00011 upmlca0 user performance monitor local control a0 128 00100 00000 6.15.3/6-49 upmlca1 user performance monitor local control a1 129 00100 00001 upmlca2 user performance monitor local control a2 130 00100 00010 upmlca3 user performance monitor local control a3 131 00100 00011 upmlcb0 user performance monitor local control b0 256 01000 00000 6.15.3/6-49 upmlcb1 user performance monitor local control b1 257 01000 00001 upmlcb2 user performance monitor local control b2 258 01000 00010 upmlcb3 user performance monitor local control b3 259 01000 00011 upmgc0 user performance monitor global control register 0 384 01100 00000 6.15.2/6-48 4 datasheet u .com
core register summary MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 6-48 freescale semiconductor 6.15.1 global control regi ster 0 (pmgc0, upmgc0) 6.15.2 local control a registers (pmlca0?pmlca3, u pmlca0?upmlca3) pmgc0 (pmr400) upmgc0 (pmr384) access: pmgc0: supervisor- read/write upmgc0: supervisor/user read only 32 33 34 35 63 r fac pmie fcece ? w reset all zeros figure 6-56. performance monitor global control register 0 (pmgc0), user performance monitor global control register 0 (upmgc0) table 6-42. pmgc0 field descriptions bits name description 32 fac freeze all counters. when fac is set by hardware or software, pmlcx[fc] maintains its current value until it is changed by software. 0 the pmcs are incremented (if permitted by other pm control bits). 1 the pmcs are not incremented. 33 pmie performance monitor interrupt enable 0 performance monitor interrupts are disabled. 1 performance monitor interrupts are enabled and occur when an enabled condition or event occurs. 34 fcece freeze counters on enabled condition or event 0 the pmcs can be incremented (if permitted by other pm control bits). 1 the pmcs can be incremented (if permitted by other pm control bits) only until an enabled condition or event occurs. when an enabled condition or event occurs, pmgc0[fac] is set. it is up to software to clear fac. 35?63 ? reserved, should be cleared. pmlca0 (pmr144) pmlca1 (pmr145) pmlca2 (pmr146) pmlca3 (pmr147) upmlca0 (pmr128) upmlca1 (pmr129) upmlca2 (pmr130) upmlca3 (pmr131) access: pmlca0?pmlca3: supervisor read/write upmlca0?upmlca3: supervisor/user read only 32 33 34 35 36 37 38 40 41 47 48 63 r fc fcs fcu fcm1 fcm0 ce ? event ? w reset all zeros figure 6-57. local control a registers (pmlca0?pmlca3), user local control a registers (upmlca0?upmlca3) 4 datasheet u .com
core register summary MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 6-49 6.15.3 local control b registers (pmlcb0?pmlcb3, upmlcb0?upmlcb3) table 6-43. pmlca0?pmlca3 field descriptions bits name description 32 fc freeze counter 0 the pmc is incremented (if permitted by other pm control bits). 1 the pmc is not incremented. 33 fcs freeze counter in supervisor state 0 the pmc is incremented (if permitted by other pm control bits). 1 the pmc is not incremented if msr[pr] = 0. 34 fcu freeze counter in user state 0 the pmc is incremented (if permitted by other pm control bits). 1 the pmc is not incremented if msr[pr] = 1. 35 fcm1 freeze counter while mark = 1 0 the pmc is incremented (if permitted by other pm control bits). 1 the pmc is not incremented if msr[pmm] = 1. 36 fcm0 freeze counter while mark = 0 0 the pmc is incremented (if permitted by other pm control bits). 1 the pmc is not incremented if msr[pmm] = 0. 37 ce condition enable 0pmc x overflow conditions cannot occur (pmc x cannot cause interrupts, cannot freeze counters) 1 overflow conditions occur when the most-significant bit of pmc x is equal to 1. it is recommended that ce be cleared when counter pmc x is selected for chaining. 38?40 ? reserved, should be cleared. 41?47 event event selector. up to 128 events selectable. these events are described in the powerpc? e500 core family reference manual. 48?63 ? reserved, should be cleared. pmlcb0 (pmr272) pmlcb1 (pmr273) pmlcb2 (pmr274) pmlcb3 (pmr275) upmlcb0 (pmr256) upmlcb1 (pmr257) upmlcb2 (pmr258) upmlcb3 (pmr259) access: pmlcb0?pmlcb3: supervisor read/write upmlcb0?upmlcb3: supervisor/user read only 32 52 53 55 56 57 58 63 r ? threshmul ? threshold w reset all zeros figure 6-58. local control b registers (pmlcb0?pmlcb3)/user local control b registers (upmlcb0?upmlcb3) 4 datasheet u .com
core register summary MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 6-50 freescale semiconductor 6.15.4 performance monitor counter registers (pmc0?pmc3, upmc0?upmc3) table 6-44. pmlcb0?pmlcb3 field descriptions bits name description 32?52 ? reserved, should be cleared. 53?55 threshmul threshold multiple 000 threshold field is multiplied by 1 (pmlcb n [threshold] 1) 001 threshold field is multiplied by 2 (pmlcb n [threshold] 2) 010 threshold field is multiplied by 4 (pmlcb n [threshold] 4) 011 threshold field is multiplied by 8 (pmlcb n [threshold] 8) 100 threshold field is multiplied by 16 (pmlcb n [threshold] 16) 101 threshold field is multiplied by 32 (pmlcb n [threshold] 32) 110 threshold field is multiplied by 64 (pmlcb n [threshold] 64) 111 threshold field is multiplied by 128 (pmlcb n [threshold] 128) 56?57 ? reserved, should be cleared. 58?63 threshold threshold. only events that exceed th e threshold value are counted. such events are implementation-dependent as are the dimension (for example duration in cycles) and granularity with which the value is interpreted. by varying the value, software can obtain a profile of the event characteristics subject to thresholding. for example, if pmc1 is configured to count cache misses that last longer than the threshold value, software can obtain the distribution of cache miss durations for a given program by monitoring the program repeatedly using a different threshold each time. pmc0 (pmr16) pmc1 (pmr17) pmc2 (pmr18) pmc3 (pmr19) upmc0 (pmr0) upmc1 (pmr1) upmc2 (pmr2) upmc3 (pmr3) access: pmc0?pmc3: supervisor read/write upmc0?upmc3: supervisor/user read only 32 33 63 r ov counter value w reset all zeros figure 6-59. performance monitor counter regi sters (pmc0?pmc3)/user performance monitor counter registers (upmc0?upmc3) table 6-45. pmc0?pmc3 field descriptions bits name description 32 ov overflow. when this bit is set, it indi cates this counter reaches its maximum value. 33?63 counter value indicates the number of occurrences of the specified event 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 7-1 chapter 7 l2 look-aside cache/sram this chapter describes the organization of the on- chip l2/sram, cache coherency rules, cache line replacement algorithm, cache contro l instructions, and vari ous cache operations. it also describes the interaction between the l2/sram and the e500 core complex. 7.1 l2 cache overview the integrated 256-kbyte l2 cache is organized as 1024 8 way sets of 32-byte cache lines based on 32-bit physical addresses, as shown in figure 7-1 . figure 7-1. l2 cache/sram configuration the sram can be configured with memory-mapped registers as externally accessible memory-mapped sram in addition to or instead of cache. the l2 cache can operate in the following modes, described in section 7.2, ?cache organization? : ? full cache mode (256-kbyte cache) ? full memory-mapped sram m ode (256-kbyte sram mapped as a single 256-kbyte block or two 128-kbyte blocks) ? half sram and half cache mode (128-kbyt e cache and 128-kbyte memory-mapped sram) e500 core 32-kbyte l1 instruction cache 32-kbyte l1 data cache core complex bus e500 core complex 256-kbyte l2 cache/sram coherency module 64 128 128 two 128-kbyte banks (8 way) independently programmable as l2 cache or sram wr rd2 rd1 dout wr in rd in 4 datasheet u .com
l2 look-aside cache/sram MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 7-2 freescale semiconductor 7.1.1 l2 cache and sram features two 128-kbyte arrays can be designa ted independently as externally -accessible memory-mapped sram or cache. the l2 cache has the following characteristics: ? write-through, fro nt-side cache ? front-side design provides easi er cache access for i/o masters such as ethernet and cpm ? write-through design is more efficient on the processor bus for front-side caches ? valid, locked, and stale states (no modified state) ? two input data buses (64 and 128 bits) and one output data bus (128 bits wide) ? all accesses are fully pipelined and non-blocking (allows hits under misses) ? 256-kbyte array organized as 1024 8 way sets of 32-byte cache lines ? eight-way set-associativity (high level of asso ciativity yields good perfor mance even with many locked lines) ? tag arrays contain 17 tag bits and 1 tag parity bit per line to support 256-kbyte cache (1024 sets), or 18 tag bits to support 128-kbyte cache (512 sets). ? configurable to allocate proces sor instructions, data, or both ? allows external writes (stashing) to allocate and optionally lock a line using one of the two following methods: ? attributes attached to the tr ansactions by initiator or atmu ? i/o devices can force memory writes to be allocated using programmed memory ranges ? pseudo-lru (7-bit replacement algorithm) ? data ecc on 64-bit boundaries (single-er ror correction, double-error detection) ? tag parity for 256-kbyte mode (1 ta g bit per line covering cache tags) ? cache locking methods ? individual line locks are set and cleared by using e500 cache locking instructions? data cache block touch and lock set ( dcbtls ), data cache block touch for store and lock set ( dcbtstls ), and instruction cache block touch and lock set ( icbtls ). ? a lock attribute can be attached to write operations. ? individual line locks are set and cleared through core-initiated instructions, by external reads or writes, or by accesses to pr ogrammed memory ranges defined in l2 cache external write address registers (l2cewar n ). ? the entire cache can be locked by setti ng a configuration register appropriately. ? lock clearing methods ? individual locks cleared by cache locking instru ctions (instruction cache block lock clear ( icblc ) and data cache block lock clear ( dcblc )) or by snooped flush unless entire cache is locked. ? flash clearing of all instruction and/or data lo cks is done by writes to configuration registers. ? an unlock attribute attached to a read instruction. ? error injection modes for testing 4 datasheet u .com
l2 look-aside cache/sram MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 7-3 sram features include the following: ? i/o devices access sram regions by mark ing transactions as snoopable (global) ? regions can reside at any ali gned location in the memory map ? for accesses of less than a cach e-line, byte-accessible ecc is pr otected using read-modify-write transactions. 7.2 cache organization when the entire 256-kbyte array is used as a cache, it has two banks each containing 512 sets of eight cache blocks (8 wa ys), as shown in figure 7-2 . each block consists of 32 bytes of data and an address tag. figure 7-2. cache organization 512 sets block 5 block 6 block 7 way 4 address tag 4 address tag 5 address tag 6 address tag 7 way 1 way 2 way 3 way 0 address tag 0 address tag 1 address tag 2 address tag 3 words [0?7] words [0?7] words [0?7] words [0?7] words [0?7] words [0?7] words [0?7] words [0?7] 8 words/block 512 sets way 5 way 6 way 7 way 4 address tag 4 address tag 5 address tag 6 address tag 7 way 1 way 2 way 3 way 0 address tag 0 address tag 1 address tag 2 address tag 3 words [0?7] words [0?7] words [0?7] words [0?7] words [0?7] words [0?7] words [0?7] words [0?7] bank 1 bank 0 8 words/block 4 datasheet u .com
l2 look-aside cache/sram MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 7-4 freescale semiconductor the tag size depends on whether both 128-kbyt e arrays are configured as cache. figure 7-3 shows how physical address bits are used to access the l2 in full cache m ode (256-kbyte cache). figure 7-3. 256-kbyte l2 cache address configuration?full cache mode physical address bits 1 7?26 identify the bank and set of the tag a nd data. physical address bits 0?16 are compared against the tags of all 8 ways. a match of a valid tag selects a 32-byte bloc k of data within the set. physical address bits 27?31 identi fy the byte or bytes of data within the block. if the l2 is programmed as one block of 256-kbyte sram, physical address bits 14?16 are used as the way select, without a tag lookup. in half sram, half c ache mode (128-kbyte cache), there is no bank select, as shown in figure 7-4 , so the tag is 18 bits (with no parity bit) for cache accesses. the cache resides in bank 1, and the sram in bank 0. for sram accesses, physical address bits 15?17 are used as the way select. if the l2 is programmed as two blocks of 128-kbyte sram, bank 0 is block 0 (defined by l2srbar0, see table 7-5 ) and bank 1 is block 1. 26 17 16 0 set index (9 bits) 18 bank select tag (17 bits) 31 27 26 17 byte select set index (9 bits) 18 bank select (5 bits) (within a cache line) tag lookup data read/write 4 datasheet u .com
l2 look-aside cache/sram MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 7-5 as shown in figure 7-4 , the tag is 18 bits (with no parity bit) for cache accesses. for sram accesses, physical address bits 15?17 are used as the way select. figure 7-4. 128-kbyte l2 cache address configuration?half sram, half cache mode the e500 core connects to the l2 cac he and the system interface through the high-speed core complex bus (ccb). the e500 core and the l2 cache connect to th e rest of the integrated device through the e500 coherency module (ecm). figure 7-5 shows the data connections of the e500 core and l2/sram. the e500 core can simultaneously read 128 bits of data from the l2/sram, read 64 bits of data from the system interface, and write 128 bits of data to the l2/sram and/or system interface. the l2/sram can be accessed by the e500 core or the system interfac e through the ecm. the l2 cache does not initiate transactions. figure 7-5 shows the data bus connections of the e500 core and l2/sram. . figure 7-5. data bus connection of ccb 31 27 26 byte select set index (9 bits) 18 (within a cache line) (5 bits) 26 18 17 0 tag (18 bits) way select (sram access only) (3 bits) tag lookup data read/write 15 17 set index (9 bits) e500 core l2/sram wr rd2 dout wr in rd1 rd in 64 e500 coherency module 128 128 (ecm) 4 datasheet u .com
l2 look-aside cache/sram MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 7-6 freescale semiconductor figure 7-6 shows address connections of the e500 core and l2/sram. figure 7-6. address bus connection of ccb in sram mode, if a non?cache-line read or write transaction is not prec eded by a cache-line write, an ecc error occurs; such a non?cache-line write tr ansaction cannot be allocated in the l2. 7.3 memory map/register definition table 7-1 shows the memory map for the l2/sram regist ers. undefined 4-byte address spaces within offset 0x000?0xfff are reserved. table 7-1. l2/sram memory-mapped registers offset register access reset section/page 0x2_0000 l2ctl?l2 control register r/w 0x2000_0000 7.3.1.1/7-7 0x2_0010 l2cewar0?l2 cache external write address register 0 r/w 0x0000_0000 7.3.1.2/7-10 0x2_0018 l2cewcr0?l2 cache external write control register 0 r/w 0x0000_0000 7.3.1.3/7-10 0x2_0020 l2cewar1?l2 cache external write address register 1 r/w 0x0000_0000 7.3.1.2/7-10 0x2_0028 l2cewcr1?l2 cache external write control register 1 r/w 0x0000_0000 7.3.1.3/7-10 0x2_0030 l2cewar2?l2 cache external write address register 2 r/w 0x0000_0000 7.3.1.2/7-10 0x2_0038 l2cewcr2?l2 cache external write control register 2 r/w 0x0000_0000 7.3.1.3/7-10 0x2_0040 l2cewar3?l2 cache external write address register 3 r/w 0x0000_0000 7.3.1.2/7-10 0x2_0048 l2cewcr3?l2 cache external write control register 3 r/w 0x0000_0000 7.3.1.3/7-10 0x2_0100 l2srbar0?l2 memory-mapped sram base address register 0 r/w 0x0000_0000 7.3.1.4/7-11 0x2_0108 l2srbar1?l2 memory-mapped sram base address register 1 r/w 0x0000_0000 7.3.1.4/7-11 0x2_0e00 l2errinjhi?l2 error injection mask high register r/w 0x0000_0000 7.3.1.5.1/7-12 0x2_0e04 l2errinjlo?l2 error injection mask low register r/w 0x0000_0000 7.3.1.5.1/7-12 0x2_0e08 l2errinjctl?l2 error injection t ag/ecc control register r/w 0x0000_0000 7.3.1.5.1/7-12 0x2_0e20 l2captdatahi?l2 error data hi gh capture register r 0x0000_0000 7.3.1.5.2/7-14 0x2_0e24 l2captdatalo?l2 error data low capture register r 0x0000_0000 7.3.1.5.2/7-14 0x2_0e28 l2captecc?l2 error syndrome register r 0x0000_0000 7.3.1.5.2/7-14 0x2_0e40 l2errdet?l2 error detect register special 0x0000_0000 7.3.1.5.2/7-14 mstr e500 core l2/sram snoop addr_in e500 coherency module (ecm) 4 datasheet u .com
l2 look-aside cache/sram MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 7-7 7.3.1 l2/sram register descriptions the following sections descri be registers that control a nd configure the l2/sram array. 7.3.1.1 l2 control register (l2ctl) the l2 control register (l2ctl), shown in figure 7-7 , controls configuration and operation of the l2/sram array. the sequence for m odifying l2ctl is as follows: 1. mbar 2. isync 3. stw (wimg = 01xx) ccsrbar+0x2_0000 4. lwz (wimg = 01xx) ccsrbar+0x2_0000 5. mbar 0x2_0e44 l2errdis?l2 error disable register r/w 0x0000_0000 7.3.1.5.2/7-14 0x2_0e48 l2errinten?l2 error interrupt enable register r/w 0x0000_0000 7.3.1.5.2/7-14 0x2_0e4c l2errattr?l2 error attributes capture register r/w 0x0000_0000 7.3.1.5.2/7-14 0x2_0e50 l2erraddr?l2 error address capture register r 0x0000_0000 7.3.1.5.2/7-14 0x2_0e58 l2errctl?l2 error control register r/w 0x0000_0000 7.3.1.5.2/7-14 012 3456 891011 1213 15 r l2e l2i l2siz l2blksz 000 l2do l2io 0 l2intdis l2sram w reset 0010_0000_0000_0000 16 17 18 19 20 21 22 23 24 31 r0 0 l2lo l2slc 0 l2lfr l2lfrid 0000 0 000 w reset 0000_0000_0000_0000 offset 0x2_0000 figure 7-7. l2 control register (l2ctl) table 7-1. l2/sram memory-mapped registers (continued) offset register access reset section/page 4 datasheet u .com
l2 look-aside cache/sram MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 7-8 freescale semiconductor table 7-2 describes l2ctl fields. table 7-2. l2ctl field descriptions bits name description 0 l2e l2 enable. used to enable the l2 array (cache or memory-mapped sram). 0 the l2 sram (cache and memory-mapped sram) is disabled and is not accessed for reads, snoops, or writes. setting the l2 flash invalidate bit (l2i) is allowed. 1 the l2 sram (cache or memory-mapped sram) is enabled. note that l2i can be set regardless of the value of l2e. 1 l2i l2 flash invalidate 0 the l2 status and lru bits are not being cleared. 1 setting l2i invalidates the l2 cache globally by clearing the all the l2 status bits, as well as the lru algorithm. memory-mapped sram is unaffected. data in memory-mapped sram regions is unaffe cted by the flash invalidate. the hardware automatically clears l2i when the invalidate is complete. 2?3 l2siz l2 sram size (read only). indicates the total av ailable size of l2 sram (to be configured as cache or memory-mapped sram). 00 reserved 01 reserved 10 256 kbyte 11 reserved 4?5 l2blksz l2 cache/memory-mapped sram block size. determines the l2 cache/memory-mapped sram block size. to change these bits, the l2 must be disabled (l2ctl[l2e] = 0). l2blksz must be l2siz when l2e = 1. see the description of l2ctl[l2sram] for info rmation on configuring the total sram as cache or memory-mapped sram. 00 reserved 01 128 kbyte 10 256 kbyte 11 reserved 6?8 ? reserved 9 l2do l2 data-only. reserved in full memory-mapped sram mode. l2do may be changed while the l2 is enabled or disabled. 0 the l2 cache allocates en tries for instruction fetches that miss in the l2. 1 the l2 cache allocates entries for processor data loads that miss in the l2 and for processor l1 castouts but does not allocate entrie s for instruction fetches that mi ss in the l2. instruction accesses that hit in the l2, data accesses, and accesses fr om the system (including i/o stash writes) are unaffected. note that if l2do and l2io are both set, no new lines are allocated into the l2 cache for any processor transactions, and processor writes and castouts that hit existing data in the cache invalidate those lines rather than updating them. 10 l2io l2 instruction-only. reserved in full memory-mapped sram mode. causes the l2 cache to allocate lines for instruction cache transactions only. l2io may be changed while the l2 is enabled or disabled. 0 the l2 cache entries are allocated for data loads that miss in the l2 and for processor l1 castouts. 1 the l2 cache allocates entries for instruction fetch misses, but does not allocate entries for processor data transactions. data accesses that hit in t he l2, instruction accesses, and accesses from the system (including i/o stash writes) are unaffected. note that if l2do and l2io are both set, no new lines are allocated into the l2 cache for any processor transactions, and processor writes and castouts that hit existing data in the cache invalidate those lines rather than updating them. 11 ? reserved 4 datasheet u .com
l2 look-aside cache/sram MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 7-9 12 l2intdis cache read intervention disable. reserved for full memory-mapped sram mode. used to disable cache read intervention. may be changed while the l2 is enabled or disabled. 0 cache intervention is enabled. the ecm ensures that if a data read from another device hits in the l2 cache, it is serviced from the l2 cache. 1 cache intervention is disabled 13?15 l2sram l2 block assignment. determines the l2 cache/memory-mapped sram block assignment. l2siz = l2blksiz (1 block): 000 block 0 = cache 001 block 0 = sram0 010?111 reserved l2siz = l2blksiz 2 (2 blocks): block 0 block 1 000 unused cache 001 sram0 unused 010 sram0 cache 011 sram0 sram1 1xx reserved to change these bits, the l2 must be disabled (l2ctl[l2e] = 0). 16?17 ? reserved 18 l2lo l2 cache lock overflow. reserved in full memory -mapped sram mode. this sticky bit is set if an overlock condition is detected in the l2 cache. a lock overflow is triggered either by executing instruction or data cache block touch and lock set instructions or by performing l2 cache external writes with lock set. if all ways are locked and an attempt to stash is made, the stash is not allocated. 0 the l2 cache did not encounter a lock overflow. l2lo is cleared only by software. 1 the l2 cache encountered a lock overflow condition. 19 l2slc l2 snoop lock clear. this sticky bit is set if a snoop invalidated a locked data cache line. note that the lock bit for that line is cleared whenever the line is invalidated. l2slc is reserved in full memory-mapped sram mode. 0 a snoop did not invalidate a locked l2 cache line. l2slc is cleared only by software. 1 the l2 cache encountered a snoop that invalidated a locked line. 20 ? reserved 21 l2lfr l2 cache lock bits flash reset. the l2 cache mu st be enabled (l2ctl[l2e] = 1) for reset to occur. this field is reserved in full memory-mapped sram mode. 0 the l2 cache lock bits are not cleared or the clear operation completed. 1 a reset operation is issued that clears each l2 cache line?s lock bits. depending on the l2lfrid value, data or instruction locks, or both can be re set. cache access is blocked during this time. after l2lfr is set, the l2 cache unit automatically clears l2lfr when the reset operation is complete (if l2ctl[l2e] is set). 22?23 l2lfrid l2 cache lock bits flash reset select instructio n or data. indicates whether dat a or instruction lock bits or both are reset. 00 not used 01 reset data locks if l2lfr = 1 10 reset instruction locks if l2lfr = 1 11 reset both data and instruction locks if l2lfr = 1 24?31 ? reserved table 7-2. l2ctl field descriptions (continued) bits name description 4 datasheet u .com
l2 look-aside cache/sram MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 7-10 freescale semiconductor 7.3.1.2 l2 cache external write address registers 0?3 (l2cewar n ) the MPC8555E supports allocat ing and locking of l2 cache lines from external agents, such as pci. this functionality is called stashing. the l2 cache external write addre ss registers 0?3 (l2cewar n ) are paired with the l2 cache external writ e control registers 0?3 (l2cewcr n ) to control the cache external write functionality. each re gister pair (for example, l2cewar0 and l2cewcr0) specif ies a programmed memory range that can be locked wi th a snoop write transaction. the a ddress register must be naturally aligned to the window size in the co rresponding control register. l2cewar n registers contain identical fields, as shown in figure 7-8 . table 7-3 describes l2cewar n fields. 7.3.1.3 l2 cache external write control registers 0?3 (l2cewcr n ) the l2cewar n registers are paired with the l2 cache extern al write control registers 0?3 (l2cewcr n ), shown in figure 7-9 , to control cache external write functionality. 0 23 24 31 r addr 00000000 w reset all zeros offset 0x2_0010, 0x2_0020, 0x2_0030, 0x2_0040 figure 7-8. l2 cache external write address registers (l2cewar n ) table 7-3. l2cewar n field descriptions bits name description 0?23 addr l2 cache external write base address 24?31 ? reserved 012 78 31 r elock 000000 sizmask w reset all zeros offset 0x2_0018, 0x2_0028, 0x2_0038, 0x2_0048 figure 7-9. l2 cache external write control registers (l2cewcr0?l2cewcr3) 4 datasheet u .com
l2 look-aside cache/sram MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 7-11 the l2cewcr n registers contain identical fi elds, which are described in table 7-4 . 7.3.1.4 l2 memory-mapped sram base address registers 0?1 (l2srbar n ) the l2 memory-mapped sram ba se address registers (l2srbar n ), shown in figure 7-10 , control the memory-mapped sram mode functi onality. specified addresses must be aligned to the value in l2ctl[l2blksz]. if l2ctl[l2sram] specifies one memory-mapped sram block, its base address must be written to l2srbar0; if it specifies two memory-ma pped sram blocks, l2srbar0 and l2srbar1 are used. table 7-4. l2cewcr n field descriptions bits name description 0 e external write enable. an external write matching the address window defined by l2cewar n /l2cewcr n is allocated or updated in the l2 cache. 0 external writes for the l2cewar n /l2cewcr n pair are disabled. 1 external writes are enabled for the l2cewar n /l2cewcr n pair. 1 lock lock lines in the targeted cache. an exte rnal write matching the address window defined by l2cewar n /l2cewcr n is locked in the l2 cache when it is allocated or updated. 0 the locked bit is not set when a line is allocated unle ss explicitly specified by transaction attributes. 1 cache lines are allocated as locked. a hit to a valid, unlocked lines sets the lock. 2?7 ? reserved 8?31 sizmask mask size. defines the size of the naturally aligned address region for cache external writes. the address region must be aligned to a boundary that is a multiple of the mask size. any value not listed below is illegal and produces boundedly undefined results. 1111 1111 1111 1111 1111 1111 256 bytes 1111 1111 1111 1111 1111 1110 512 bytes 1111 1111 1111 1111 1111 1100 1 kbyte 1111 1111 1111 1111 1111 1000 2 kbytes 1111 1111 1111 1111 1111 0000 4 kbytes 1111 1111 1111 1111 1110 0000 8 kbytes 1111 1111 1111 1111 1100 0000 16 kbytes 1111 1111 1111 1111 1000 0000 32 kbytes 1111 1111 1111 1111 0000 0000 64 kbytes 1111 1111 1111 1110 0000 0000 128 kbytes 1111 1111 1111 1100 0000 0000 256 kbytes 1111 1111 1111 1000 0000 0000 512 kbytes 1111 1111 1111 0000 0000 0000 1 mbyte 1111 1111 1110 0000 0000 0000 2 mbytes 1111 1111 1100 0000 0000 0000 4 mbytes 1111 1111 1000 0000 0000 0000 8 mbytes 1111 1111 0000 0000 0000 0000 16 mbytes 1111 1110 0000 0000 0000 0000 32 mbytes 1111 1100 0000 0000 0000 0000 64 mbytes 1111 1000 0000 0000 0000 0000 128 mbytes 1111 0000 0000 0000 0000 0000 256 mbytes 1110 0000 0000 0000 0000 0000 512 mbytes 1100 0000 0000 0000 0000 0000 1 gbyte 1000 0000 0000 0000 0000 0000 2 gbytes 0000 0000 0000 0000 0000 0000 4 gbytes 0 17 18 31 r addr 0000000000000 w reset all zeros offset 0x2_0100, 0x2_0108 figure 7-10. l2 memory-mapped sram base address registers (l2srbar n ) 4 datasheet u .com
l2 look-aside cache/sram MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 7-12 freescale semiconductor l2srbar bits are described in table 7-5 . when enabled, the windows defined in l2srbar n supersede all other mappings of these addresses for processor and global (snoopable) i/ o transactions. therefore, sr am windows must never overlap configuration space as defined by ccsrbar (see section 4.3.1.1.2, ?configurati on, control, and status base address register (ccsrbar)? ). overlapping sram and local access windows is discouraged because processor and snoopable i/o transactions would map to the sram while non-snooped i/o transactions would be mapped by th e local access windows. only if al l accesses to the sram address range are snoopable can results be consistent if sram and local access windows overlap. furthermore, l2srbarn should not overlap a ddr dr am space for which a valid chip select is define d. this could result in spurious ecc errors if ec c and speculative reads are enabled. see section 2.2.3.7, ?illegal interaction between local access windo ws and ddr sdram chip selects.? 7.3.1.5 l2 error registers l2 error detection, reporting, and injec tion allow flexible handling of ecc a nd parity errors in the l2 data and tag arrays. when the device dete cts an l2 error, the appropriate bit in the error detect register (l2errdet) is set. error de tection is disabled by sett ing the corresponding bit in the error disable register (l2errdis). the address and attributes of the first detected error are also save d in the error capture registers (l2erraddr, l2errattr, l2captdatahi, l2ca ptdatalo, and l2captacc). subsequent errors set error bits in the error detection registers, but information is saved only for the first one. error reporting (by generating an interrupt ) is enabled by setting the corres ponding bit in the error interrupt enable register (l2errinten). note th at the error detect bit is set regardless of th e state of the interrupt enable bit. when an error is detected, if error dete ction is enabled the l2 cache/sram always asserts an internal error signal with read data to prevent the l1 caches and archit ectural registers from being loaded with corrupt data. if error detection is disabled, the detected error bit is not set and no internal signal is asserted. the l2 error detect register (l2errd et) is implemented as a bit-reset type register. reading from this register occurs normally; however, write operations can clear but not set bits. a bit is cleared whenever the register is written, and th e data in the corresponding bit location is a 1. for example, to clear bit 6 and not affect any other bits in th e register, the value 0x0200_0000 is written to the register. note that in sram mode, if a non?cache-line read or write transaction is not preceded by a cache-line write, an ecc error occurs; such a non?cache-line write transaction cannot be allocated in the l2. 7.3.1.5.1 error in jection registers the l2 cache includes support for inject ing errors into the l2 data, data ecc, or tag. this may be used to test error recovery software by dete rministically creating error scenarios. table 7-5. l2srbar n field descriptions bits name description 0?17 addr l2 memory-mapped sram base address 18?31 ? reserved 4 datasheet u .com
l2 look-aside cache/sram MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 7-13 the preferred method for error inject ion is to set all data pages to cache-inhibited (mmu tlb entry i = 1) except a scratch page, set l2ctl[l2do ] to prevent allocation of instru ction accesses, and invalidate the l2 by setting l2ctl[l2i] = 1. the following code sequenc e triggers an error, then detects it (a is an address in the scratch page): dcbz a | allocates the line in the l1 in the modified state dcbtls_l2 a | forces the line from the l1 and allocates the line in the l2 lwz a data or tag errors are injected into the line, acc ording to the error injection settings in l2errinjhi, l2errinjlo, and l2errinjc tl, at allocation. the final load detect s and reports the error (if enabled) and allows software to examine the of fending data, address, and attributes. note that error injection enable bits in l2errinjc tl must be cleared by software and the l2 must be invalidated (by setting l2ctl[l2i]) before resuming l2 normal operation. figure 7-11 shows the l2 error injection mask high re gister (l2errinjhi). table 7-6 describes l2errinjhi[eimaskhi]. figure 7-12 shows the l2 error inje ction mask low register (l2errinjlo) fields. 0 31 r eimaskhi w reset all zeros offset 0x2_0e00 figure 7-11. l2 error injection mask high register (l2errinjhi) table 7-6. l2errinjhi field descriptions bits name description 0?31 eimaskhi error injection mask/high word . a set bit corresponding to a data path bit causes th at bit on th e data path to be inverted on cache/sram writes if l2errinjctl[derrien] = 1. 0 31 r eimasklo w reset all zeros offset 0x2_0e04 figure 7-12. l2 error injection mask low register (l2errinjlo) 4 datasheet u .com
l2 look-aside cache/sram MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 7-14 freescale semiconductor table 7-7 describes l2errinjlo[eimasklo]. figure 7-13 shows the l2 error in jection mask control re gister (l2errinjctl). table 7-8 describes l2errinjctl fields. 7.3.1.5.2 error control and capture registers the error control and capture registers control de tection and reporting of tag parity, ecc and l2 configuration errors. l2 configurati on errors are illegal combinations of l2 size and block size and are table 7-7. l2errinjlo field descriptions bits name description 0?31 eimasklo error injection mask/low word. a set bit corresponding to a data path bit causes that bit on the data path to be inverted on sram writes if l2errinjctl[derrien] = 1. 0 141516 2122 2324 31 r00000000000000 0 terrien 000000 eccmb derrien eccerrim w reset all zeros offset 0x2_0e08 figure 7-13. l2 error injection mask control register (l2errinjctl) table 7-8. l2errinjctl field descriptions bits name description 0?14 ? reserved 15 terrien l2 tag array error injection enable 0 no tag errors are injected. 1 all subsequent entries written to the l2 tag array have the parity bit inverted. 16?21 ? reserved 22 eccmb ecc mirror byte enable 0 ecc byte mirroring is disabled 1 the most significant data path byte is mirrored onto the ecc byte if derrien = 1. 23 derrien l2 data array error injection enable 0 no data errors are injected. 1 subsequent entries written to the l2 data array have data or ecc bits inverted as specified in the data and ecc error injection masks and/or data path byte mirrored onto ecc as specified by ecc mirror byte enable. note: if both ecc mirror byte and data error injection are enabled, ecc mask error injection is performed on the mirrored ecc. 24?31 eccerrim error injection mask for the ecc bits. a set bit corre sponding to an ecc bit causes that bit to be inverted on sram writes if derrien = 1. 4 datasheet u .com
l2 look-aside cache/sram MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 7-15 detected when the l2 is enabled (l2ctl[l2e] = 1). figure 7-14 shows the l2 error capture data high register (l2captdatahi). table 7-9 describes l2captdat ahi[l2data] fields. figure 7-15 shows the l2 error capture data low register (l2captdatalo). table 7-10 describes l2captdatalo[l2data] fields. figure 7-16 shows the l2 error syndr ome register (l2captecc). 0 31 r l2data w reset all zeros offset 0x2_0e20 figure 7-14. l2 error capture data high register (l2captdatahi) table 7-9. l2captdatahi field descriptions bits name description 0?31 l2data l2 data high word 0 31 r l2data w reset all zeros offset 0x2_0e24 figure 7-15. l2 error capture data low register (l2captdatalo) table 7-10. l2captdatalo field descriptions bits name description 0?31 l2data l2 data low word 078 232431 r eccsynd 0000000000000000 ec cchksum w reset all zeros offset 0x2_0e28 figure 7-16. l2 error syndrome register (l2captecc) 4 datasheet u .com
l2 look-aside cache/sram MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 7-16 freescale semiconductor table 7-11 describes l2captecc fields. figure 7-17 shows the l2 error detect register (l2errdet). table 7-12 describes l2errdet fields. table 7-11. l2captecc field descriptions bits name description 0?7 eccsynd the calculated ecc syndrome of the failing double word 8?23 ? reserved 24?31 eccchksum the data path ecc of the failing double word 0 1 26 27 28 29 30 31 r mull2err 0000000000000000000000000 0 tparerr mbeccerr sbeccerr 0 l2cfgdis w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x2_0e40 figure 7-17. l2 error detect register (l2errdet) table 7-12. l2errdet field descriptions bits name description 0 mull2err multiple l2 errors (bit reset, write 1 to clear) 0 multiple l2 errors of the same type were not detected. 1 multiple l2 errors of the same type were detected. 1?26 ? reserved 27 tparerr tag parity error (bit reset, write 1 to clear) 0 tag parity error was not detected 1 tag parity error was detected note that if an l2 cache tag parity error occurs on an attempt to write a new line, the l2 cache must be flash invalidated. l2 functionality is not guaranteed if flash invalidation is not performed after a tag parity error. 28 mbeccerr multiple-bit ecc error (bit reset, write 1 to clear) 0 multiple-bit ecc errors were not detected. 1 multiple-bit ecc errors were detected. 29 sbeccerr single-bit ecc error (bit reset, write 1 to clear) 0 single-bit ecc error was not detected 1 single-bit ecc error was detected 30 ? reserved 31 l2cfgerr l2 configuration error (bit reset, write 1 to clear). reports inconsistencies between the l2siz, l2blksz, and l2sram settings of the l2 control register (l2ctl). 0 l2 configuration errors were not detected 1 l2 illegal configuration error detected 4 datasheet u .com
l2 look-aside cache/sram MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 7-17 figure 7-18 shows the l2 error disa ble register (l2errdis). table 7-13 describes l2errdis fields. figure 7-19 shows the l2 error interrupt enable regi ster (l2errinten). when an enabled error condition exists, the l2 signals an inte rrupt to the core through the internal int signal. 0262728293031 r00000000000000000000000000 0 tpardis mbeccdis sbeccdis 0 l2cfgdis w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x2_0e44 figure 7-18. l2 error disable register (l2errdis) table 7-13. l2errdis field descriptions bits name description 0?26 ? reserved 27 tpardis tag parity error disable 0 tag parity error detection enabled 1 tag parity error detection disabled 28 mbeccdis multiple-bit ecc error disable. note that uncorrectable read errors may cause the assertion of core_fault_in , which causes the core to generate a machine check interrupt, unless it is disabled (by clearing hid1[rfxe]). if rfxe is zero and this error occurs, mbeccdis must be cleared and l2errinten[mbeccinten] must be set to ensur e that an interrupt is generated. for more information, see section 6.10.2, ?hardware implementa tion-dependent register 1 (hid1).? 0 multiple-bit ecc error detection enabled 1 multiple-bit ecc error detection disabled 29 sbeccdis single-bit ecc error disable 0 single-bit ecc error detection enabled 1 single-bit ecc error detection disabled 30 ? reserved 31 l2cfgdis l2 configuration error disable 0 l2 configuration error detection enabled 1 l2 configuration error detection disabled 0262728293031 r00000000000000000000000000 0 tparinten mbeccinten sbeccinten 0 l2cfginten w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x2_0e48 figure 7-19. l2 error interrupt enable register (l2errinten) 4 datasheet u .com
l2 look-aside cache/sram MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 7-18 freescale semiconductor table 7-14 describes l2er rinten fields. figure 7-20 shows the l2 error attributes capture register (l2errattr). table 7-15 describes l2errattr fields. table 7-14. l2errinten field descriptions bits name description 0?26 ? reserved 27 tparinten tag parity error reporting enable 0 tag parity error reporting disabled 1 tag parity error reporting enabled 28 mbeccinten multiple-bit ecc error reporting enable. note that uncorrectable read errors may cause the assertion of core_fault_in , which causes the core to generate a machine check interrupt, unless it is disabled (by clearing hid1[rfxe]). if rfxe is zero and this error occurs, l2errdis[mbeccdis] must be cleared and mbeccinten must be set to ensure that an interrupt is generated. for more information, see section 6.10.2, ?hardware implementa tion-dependent register 1 (hid1).? 0 multiple-bit ecc error reporting disabled 1 multiple-bit ecc error reporting enabled 29 sbeccinten single-bit ecc error reporting enable 0 single-bit ecc error reporting disabled 1 single-bit ecc error reporting enabled 30 ? reserved 31 l2cfginten l2 configuration error reporting enable 0 l2 configuration error reporting disabled 1 l2 configuration error reporting enabled 012 345 7 8 91011 15161718 1920 30 31 r00 dwnum 0 transsiz burst 00 transsrc 00 transtype 0 000000000 0 valinfo w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x2_0e4c figure 7-20. l2 error attributes capture register (l2errattr) table 7-15. l2errattr field descriptions bits name description 0?1 ? reserved 2?3 dwnum double-word number of the detected error (data ecc errors only) 4?reserved 5?7 transsiz transaction size for detected error single-beat burst 000 8 bytes reserved 001 1 byte 16 bytes 010 2 bytes 32 bytes 011 3 bytes reserved single-beat burst 100 4 bytes reserved 101 5 bytes reserved 110 6 bytes reserved 111 7 bytes reserved 4 datasheet u .com
l2 look-aside cache/sram MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 7-19 figure 7-21 shows the l2 error address capture register (l2erraddr). table 7-16 describes l2erraddr[l2addr] fields. 8 burst burst transaction for detected error 0 single-beat ( 64 bits) transaction 1 burst transaction 9?10 ? reserved 11?15 transsrc transaction source for detected error 00000 external (system logic) 10000 processor (instruction) 10001 processor (data) 16?17 ? reserved 18?19 transtype transaction type for detected error 00 snoop (tag/status read) 01 write 10 read 11 read-modify-write 20?30 ? reserved 31 valinfo l2 capture registers valid 0 l2 capture registers contain no valid inform ation or no enabled errors were detected. 1 l2 capture registers contain info rmation of the first detected error which has reporting enabled. software must clear this bit to unfreeze error capture so error detection hardware can overwrite the capture address/data/attributes for a newly detected error. 0 31 r l2addr w reset all zeros offset 0x2_0e50 figure 7-21. l2 error addres s capture register (l2erraddr) table 7-16. l2erraddr field descriptions bits name description 0?31 l2addr l2 address corresponding to detected error table 7-15. l2errattr field descriptions (continued) bits name description 4 datasheet u .com
l2 look-aside cache/sram MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 7-20 freescale semiconductor figure 7-22 shows the l2 error control register (l2errctl). table 7-17 describes l2errctl fields. 7.4 external writes to the l2 cache (cache stashing) data from an i/o master can be allocated into the l2 cache while simultaneously being written to memory. external writes can be perf ormed from any i/o master: ? ethernet ?cpm ?pci ?dma new cache lines are allocated for full cache line wr ites, unless the line is already valid or locked. sub?cache-line write data is stashed only if the line is valid in the cache. a read -modify-write process is used to merge the stashed data with the valid line data. the l2 cache external write address registers 0?3 (l2cewar n ) are paired with th e l2 cache external write control regi sters 0?3 (l2cewcr n ) to control the cache stashing functi onality. each regi ster pair (for example, l2cewar0 and l2cewcr0) specifies a progr ammed memory range that can be locked with a snoop write transaction. the addres s register must be naturally aligned to the window size in the corresponding control register. for more information, see section 7.3.1.2, ?l2 cache external write address registers 0?3 (l2cewarn),? and section 7.3.1.3, ?l2 cache external write control registers 0?3 (l2cewcrn).? note that stashing can occur regardless of whether the l1 cache is enabled. 0 7 8 1516 2324 31 r00000000 l2cthresh 00000000 l2ccount w reset all zeros offset 0x2_0e58 figure 7-22. l2 error control register (l2errctl) table 7-17. l2errctl field descriptions bits name description 0?7 ? reserved 8?15 l2cthresh l2 cache threshold. threshold value for the numb er of ecc single-bit errors that are detected before reporting an error condition 16?23 ? reserved 24?31 l2ccount l2 count. counts ecc single-bit errors detect ed. if l2ccount equals the ecc single-bit error trigger threshold, an error is reported if single-bit error reporting is enabled 4 datasheet u .com
l2 look-aside cache/sram MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 7-21 note that stashing can also occur even if the cache- inhibited bit in the mmu is set for the page. when the core looks for (and does not find) the stashed data in the l1 cache, a transaction is gene rated in which the l2 cache responds by updating the l1 cache with the requested data. for information on how to initiate cac he stashing, see the respective chapters for the i/o masters, listed above, that support stashing. 7.5 l2 cache timing table 7-18 shows the timing of back-to-back loads that miss in the l1 data cache and hit in the l2 cache, assuming the core is running at 2 1/ 2 times the l2 cache frequency. the l2 returns the 1 28 bits containing the requested data (critical quad word) first. this data is forwarded to the result register before the full cache line reloads the l1. . table 7-18. fastest read timing?hit in l2 core clocks 1234567891011121314151617181920212223242526 e500 core load 1 to d-cache d-cache miss to c i u ciu q to c i u lsu dlfb lsu reads command lsu reads out data result bus e500 core load 2 to d-cache d-cache miss to ciu ciu q to c i u lsu dlfb lsu reads command lsu reads out data result bus ccb clocks<1234567891011> ccb address bus load 1 bg ts aack hit data- coming ccb address bus load 2 bg ts aack hit data- coming ccb data bus load 1 data data ccb data bus load 2 data data 4 datasheet u .com
l2 look-aside cache/sram MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 7-22 freescale semiconductor 7.6 l2 cache and sram coherency this section explains the rules of cache and memory-mapped sram coherency. the term ?snoop transaction? refers to tran sactions initiated by the devi ce system logic or by i/o traffic, as opposed to e500 core-initiated transactions. 7.6.1 l2 cache coherency rules l2 cache coherency rules are as follows: ? the l2 is non-inclusive of the l1?valid l1 lines may be valid or invalid in the l2. ? the l2 cache holds no modified data. there are four states?invali d, exclusive, exclusive locked, and stale. ? the l2 allocates entries for da ta cast-out or pushed (non-global, non-write-th rough write with kill) from the l1 caches. ? lines for e500 core-initi ated burst read transactions are allocated as exclusive in the l2. ? the l2 supports i/o devices read ing data from valid lines in th e l2 cache (data intervention) if l2ctl[l2intdis] = 0. an optional unl ock attribute causes i/o reads to clear a lock when the read is performed. ? the l2 cache does not respond to ca che-inhibited read transactions. ? e500 core-initiated, cache-inhibited store transact ions invalidate the line when they hit on a valid l2 line. if the line is locked, it goes to th e stale state. for other write transactions the cache-inhibited bit is ignored. ? non-burst cacheable write transact ions from the e500 core (generated by write-through cacheable stores) update a valid l2 cache line through a read-modify-write operation. ? e500 core cast out transac tions that hit on a st ale line in the l2 cache cause a data update of the line and a change to the valid locked state for that line. ? an e500 core-initiated, cacheable, non-write-through st ore that misses in l1 and hits on a line in the l2 invalidates that line in th e l2. if the line is marked exclus ive locked, the l2 marks the line as stale. ? transactions that hit a stale l2 cache line that would cause an allocate if they miss cause a data update of the line (when data arrives from memory) and a change to the line?s valid locked state. data is not supplied by the l2 c ache for the read in this case. ? the following transactions kill th e data and the respective locks when they hit a valid l2 line: ? dcbf ? dcbi ? the l2 cache supports mixed cache ex ternal writes and core-initiated writes to the same addresses if the core-initiated writes are marked c oherency-required, caching a llowed, not write-through (wimg = 001x) and the external writes are ma rked coherency-required, caching-allowed. ? the l2 cache supports writes to the l2 cache fr om peripheral devices or from i/o controllers through snoop write transactions with addresses that hit in a programmed memory range. full-cache-line (32-byte) write transa ctions update the data for a valid line in the l2, and if the line 4 datasheet u .com
l2 look-aside cache/sram MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 7-23 is not valid in the l2, a line is allocated. sub-cache-line write transactions upda te the data only for valid l2 cache lines through read-modify-write operations. ? the l2 cache supports burst writes that lock an l2 cache line from peripheral devi ces or from i/o controllers through write transacti ons with addresses that hit in a programmed memory range that has the lock attribute set. ? the l2 cache supports burst writes that allocat e and/or lock an l2 cache line from peripheral devices or i/o controllers thr ough a write allocate tr ansaction. see the syst em logic programming model (for example, that of the dma controller) for details on how to set the transaction type for cache external writes to the l2. 7.6.2 memory-mapped sram coherency rules memory-mapped sram coherency rules are as follows: ? external (non?core-initiated) accesses to memory-mapped sram must be marked coherency-required. external accesses marked coherency-not-required to memory-mapped sram may cause an address unavailable error. ? accesses to memory-mapped sram are cacheable only in the correspo nding e500 l1 caches. external accesses must be marked cache-inhibite d or be performed with non-caching transactions. 7.7 l2 cache locking the device caches can be locked and cleared using the following methods: ? cache locking methods ? individual line locks are set and cleared by using instru ctions defined by the architecture, which is part of the freescale embedded category impl ementation standards (eis). these instructions include data cache bloc k touch and lock set ( dcbtls ), data cache block touch for store and lock set ( dcbtstls ), and instruction cache block touch and lock set ( icbtls ). for detailed information about these instructions, see the powerpc? e500 core family reference manual. ? a lock attribute can be attached to write operations. ? individual line locks are set and cleared through core-initiated instructions, by external reads or writes, or by accesses to pr ogrammed memory ranges defined in l2 cache external write address registers (l2cewar n ). ? the entire cache can be locked by sett ing configuration regi sters appropriately. ? methods for clearing locks ? individual locks are cleared by cache locking inst ructions (instruction cache block lock clear ( icblc ) and data cache block lock clear ( dcblc )) or by snooped flush unless the entire cache is locked. ? flash clearing of all instruction and/or data locks can be done by wr ites to configuration registers. ? an unlock attribute can be att ached to i/o read operations. 4 datasheet u .com
l2 look-aside cache/sram MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 7-24 freescale semiconductor 7.7.1 locking the entire l2 cache the entire l2 cache can be locked by setting l2ctl[l2do] = 1 and l2ctl[l2io] = 1. this has the effect of preventing any further allo cation of new lines in the cache by core requests. if there are lines in the cache that are not valid, they cannot be used by core requests until the cache is unlocked. while the cache is locked, read requests are serviced as no rmal, and snooping continues as normal to maintain coherency. lines invalidated to sa tisfy coherency requireme nts cannot be realloca ted by core requests while the cache remains locked. the l2 cache ca n be unlocked by clearing l2ctl[l2io] and/or l2ctl[l2do]. note that l2ctl[l2do] and l2ctl[ l2io] have no effect on cache external write allocations or memory-mapped sram. note that this form of cache locking does not use the lock bits of the cache and cannot be cleared by resetting the cache or lock bits. 7.7.2 locking programmed memory ranges a programmed memory range can be locked with a snoop write transact ion that matches a cache external write address range (s pecified by l2cewar n and l2cewcr n ). there is no clearing of locks through the programmed address ranges. locks can be clea red using clear lock instructions, flushes, or read-and-clear-lock snoop (rwnitc with clea r lock attribute), or flash clear locks. 7.7.3 locking selected lines individual lines are locked when the l2 receiv es one of the following burst transactions: ? icbtls (ct = 1)?instruction cache block t ouch and lock set instruction ? dcbtls (ct = 1)?data cache block touch and lock set instruction ? dcbtstls (ct = 1)?data cache block touch for store and lock set instruction ? snoop burst write?if the a ddress hits on a programmed cache exte rnal write space with the lock attribute set, or if the write a llocate transaction type is used ? snoop non-burst write?if the address hits on a pr ogrammed cache external write space with the lock attribute set note that the core complex broadcasts these instructions to the l2 if the ct field in the instruction specifies the l2 cache (ct = 1). when the l2 c ache is specified, data is not placed in the l 1, only the l2. if the l1 cache is specified (ct = 0), the l2 does not lock the line, and the data is placed in the l1 (and locked). when the touch lock set l2 instruction ( dcbtls or dcbtstls ) hits are modified in the l1 cache, the modified data is allocated into the l2 cache (and written back to main memory) and a data lock is set. the l1 line state transitions to invalid. note that if the l2 receives a request to allocate and lo ck a line, but all lines in the selected way are locked, the requested l2 line is not allocated and the l2 cache lock overflow bit (l2ctl[l2lo]) is set. lines invalidated to satisfy cohere ncy requirements cannot be reallocated while the cache remains locked. 4 datasheet u .com
l2 look-aside cache/sram MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 7-25 7.7.4 clearing locks on selected lines individual locks in the l2 ar e cleared by a lock clear ( icblc or dcblc, ct = 1) instruction. this directs the l2 cache to clear a lock on that line if it hits in the l2 cache. both data and instruction locks are cleared by the icblc and dcblc instructions. note that the lock on a line is cl eared if the line is invalidated by a snooped flush transaction, and the line in the cache is available for allocati on of a new line of instru ction or data unless the entire cache is locked. note there is a scenario in which a lock cl ear operation appears to fail to clear a lock in the l2 cache. this occurs only when the attempt to set the lock results in a bus error (for example, pci returns an error condition). assume the following scenario: 1. the e500 attempts to set a lock in the l2 cache (by executing a dcbtls or icbtls instruction with ct = 1). the line is not already present in the cache, so it must be read from exte rnal memory. this read encounters an error which, depending on the chip conf iguration, will be reported to the core (probably as an interrupt). 2. at (or near) the same time, a cache ex ternal write to the same cache line is being mastered by the ecm. 3. very soon after the cache external write, a transaction to clear the lock occurs. this can be caused by the processor executing a dcblc or icblc instruction with ct = 1, or by the ecm mastering a lock clear transaction. if this scenario occurs within a tight timing window, the cache line may unexpectedly remain locked at the end of the sequence. the interrupt handler may want to clear the erroneously remaining lock in this case. 7.7.5 flash clearing of instruction and data locks locks for instructions and data are recorded separately in the l2 cache, and they can be flash cleared separately by writing the appropriate value to th e l2 cache control register (l2ctl[l2lfr] and l2ctl[l2lfrid]). flash invalida ting of the l2 (setting l2ctl[l2i]) clears all locks on both instructions and data. note that flash clearing is the only way to clear data locks without clearing instruction locks, or to clear instruction locks without clear ing data locks. all instructions and s noop transactions that clear locks clear both data and instruction locks. 4 datasheet u .com
l2 look-aside cache/sram MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 7-26 freescale semiconductor 7.7.6 locks with stale data if data is locked in the l2 and either the e 500 core performs a cacheab le copyback store or a dcbtst misses in the l1, the l2 invalidates the line; however, the l2 clear s the valid bit for the data, the lock remains, and the line cannot be victimized. if the e500 core casts out modified da ta or pushes it in response to a non-flush snoop, the l2 updates the data and sets the valid bit again, main taining the lock and keeping the data in the cache hierarchy. 7.8 plru l2 replacement policy line replacement is determined using a pseudo least -recently-used (plru) algorit hm. there is a valid bit (v0?v7) for each line. to determine the replacement victim (the line to be cast out), there are seven plru bits (p0?p6) for each set. plru bits are updated every time a new line is allocat ed or replaced and every time a line is modified or invalida ted. there are two sets of lock bits , one for instructions (i0?i7) and one for data (d0?d7) for every line. the lock bits act as a mask over the plru bits to determine victim selection. the plru bi ts are updated regardless of line locking. figure 7-23 shows the binary decision tree used to generate the victim line. the eight ways of the l2 cache are labeled w0?w7; the seven plru bits are labeled p0?p6. figure 7-23. l2 cache line replacement algorithm p0 = 0? p1 = 0? p2 = 0? p3 = 0? p5 = 0? p4 = 0? p6 = 0? allocate w0 allocate w1 allocate w2 allocate w3 allocate w4 allocate w5 allocate w6 allocate w7 ye s ye s ye s ye s ye s ye s no no no no no no ye s n o p0 p1 p2 p3 p4 p6 0 0 x 0 p5 x x x 0 1 x x 0 x x 0 1 x x 1 x x 0 0 x 1 x x x 1 x 0 x x 0 x 1 x 0 x x 1 x 1 x 1 x x x 0 1 x 1 x x x 1 4 datasheet u .com
l2 look-aside cache/sram MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 7-27 7.8.1 plru bit update considerations plru bits are updated when a way is modified, either by a write, an i nvalidate, or an allocation of a new line. plru bit updates depend on which cach e way was last accessed, as summarized in table 7-19 . when an l2 line is invalidated, the plru bits are updated, marking the corresponding way as least-recently-used. this causes the invalidate d way to be selected as the next victim. 7.8.2 allocation of lines l2 cache lines are locked through the status array lock bits. there are two lock bits for each way of each set (1024 sets by eight ways). these bits are set or cleared through special l2 controller commands. lock bits are used at allocate time to steer the plru algorithm away from select ing locked victims. in the following discussion, the eight lock bits for a particular set are called l0?l7. where lock way i: li = di | ii, i=0...7 (di = data lock, ii = instruction lock) an effective value of each plru bit is calculated as follows: p0_eff = f(p0,l0,l1,l2,l3,l4,l5,l6,l7) = (l0 & l1 & l2 & l3) | (p0 & ~(l4 & l5 & l6 & l7)) p1_eff = f(p1,l0,l1,l2,l3) = (l0 & l1) | (p1 & ~(l2 & l3)) p2_eff = f(p2,l4,l5,l6,l7) = (l4 & l5) | (p2 & ~(l6 & l7)) p3_eff = f(p3,l0,l1) = l0 | (p3 & ~l1) p4_eff = f(p4,l2,l3) = l2 | (p4 & ~l3) p5_eff = f(p5,l4,l5) = l4 | (p5 & ~l5) p6_eff = f(p6,l6,l7) = l6 | (p6 & ~l7) table 7-19. plru bit update algorithm last way accessed plru bits p0 p1 p2 p3 p4 p5 p6 0 1 1?1??? 1 1 1?0??? 210??1?? 310??0?? 40?1??1? 50?1??0? 6 0 ? 0 ??? 1 7 0 ? 0 ??? 0 4 datasheet u .com
l2 look-aside cache/sram MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 7-28 freescale semiconductor these effective plru bits are used to select a victim, as indicated in table 7-20 . 7.9 l2 cache operation this section describes the be havior of the l1 and l2 cache in response to various operations and in various configurations. 7.9.1 l2 cache states the l2 status array uses f our bits for each line to dete rmine the status of the li ne. different combinations of these bits result in different l2 states. the status bits are as follows: ?valid (v) ? instruction locked (il) ? data locked (dl) ?stale (t) table 7-21 shows l2 cache states. note that these conventions are also used in table 7-22 . table 7-20. plru-based victim selection mechanism way selected plru state (binary) reduced logic equation w0 00x0xxx ~p0 & ~p1 & ~p3 w1 00x1xxx ~p0 & ~p1 & p3 w2 01xx0xx ~p0 & p1 & ~p4 w3 01xx1xx ~p0 & p1 & p4 w4 1x0xx0x p0 & ~p2 & ~p5 w5 1x0xx1x p0 & ~p2 & p5 w6 1x1xxx0 p0 & p2 & ~p6 w7 1x1xxx1 p0 & p2 & p6 table 7-21. l2 cache states v t il dl l2 states 0 x x x invalid (i) 1000exclusive (e) 1001exclusive data locked (edl) 1010exclusive instruction locked (eil) 1011exclusive instruction and data locked (el) 1100stale (data invalid, locks invalid) (t) 1101stale (data invalid, dlock valid) (tdl) 1110stale (data invalid, ilock valid) (til) 1111stale (data invalid, locks valid) (tl) 4 datasheet u .com
l2 look-aside cache/sram MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 7-29 7.9.2 flash invalidation of the l2 cache the l2 cache may be completely invalidated by setti ng the l2i bit of the l2 control register (l2ctl). note that no data is lost in this process because the l2 cache is a write-through cache and contains no modified data. flash invalidation of the cache is necessary when the cach e is initially enabled and may be necessary to recover from some error conditions such as a tag parity error. the invalidation process requires several cycles to co mplete. the l2i bit remains set during this procedure and is then cleared automatically when the procedure is complete. the l2 cache controller issues retries for all transactions on the e500 core complex bus (ccb) while the flash i nvalidation process is in progress. note that the contents of memo ry-mapped sram regions of the da ta array are unaffected by a flash invalidation of the l2 c ache regions of the array. 7.9.3 l2 state transitions table 7-22 lists state transitions for all e5 00 core-initiated transactions th at change the l2 cache state. core-initiated transactions caused when the core executes msync , mbar , tlbivax , or tlbsync do not change the l2 cache state. the table does not list initial l1 stat es for transactions that hit in the l1 (il1 or dl1) and are not sent to the l2. in the table, the heading ?l2 hit? indi cates that the l2 provides (on a read) or captures (on a write) data for an existing line. some entries list tw o final l1 states. l2 t ouch instructions never al locate into il1 or dl1. note that if the l2 sram is disabl ed, the l2 initial and final states are always i and the l2 never hits. similarly, if the l2 sram is in full memory-ma pped sram mode, the l2 initial and final states are always i and the l2 never hits for addresses not in the memory-mapped sram address range. the l2 always hits for addresses in the enab led memory-mapped sram address ranges. table 7-22. state transitions due to core-initiated transactions source of transaction initial states l2 hit final states comments l1 l2 l1 l2 cacheable instruction fetch icbtls_l1 il1 i i/t no i/v same l2ctl[l2do] = 1. l2 touch instructions not allocated in l1 i no i/v e l2ctl[l2do] = 0 icbt_l2 dl1 i,e e/el yes i/v same t no i/v el l2ctl[l2do] = 0. restore locked line in l2 with valid data from bus icbtls_l2 dl1 i,e i/t no i same l2ctl[l2do] = 1 e yes i i l2ctl[l2do] = 1 el yes i t l2ctl[l2do] = 1 i no i el l2ctl[l2do] = 0 e yes i el l2ctl[l2do] = 0 el yes i same l2ctl[l2do] = 0 t no i el l2ctl[l2do] = 0. restore locked line in l2 with valid data from bus 4 datasheet u .com
l2 look-aside cache/sram MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 7-30 freescale semiconductor cache-inhibited instruction fetch n/a n/a no n/a n/a no l1/l2 effect cacheable load (4-state) cacheable lwarx (4-state) dcbt_l1 (4-state) dcbtls_l1 (4-state) dl1 i i/t no e same l2ctl[l2io] = 1 e yes e i l2ctl[l2io] = 1 el yes e t l2ctl[l2io] = 1 i no e e l2ctl[l2io] = 0 e/el yes e same l2ctl[l2io] = 0 t no el el l2ctl[l2io] = 0. restore locked line in l2 with valid data from bus cache-inhibited load n/a n/a no n/a n/a no l1/l2 effect cache-inhibited lwarx n/a n/a no n/a n/a no l2 effect writeback store dl1 i i/t no m same l2 allocates when a line is cast out of l1. eyesm i el yes m t writeback stwcx. dl1 i i/t no m same eyesm i el yes m t cacheable load (3-state) cacheable lwarx (3-state) dcbt_l1 (3-state) dcbtls_l1 (3-state) dl1 i i no e/i i l2ctl[l2io] = 1 t no e/i t l2ctl[l2io] = 1 e yes e/i i l2ctl[l2io] = 1 el yes e/i t l2ctl[l2io] = 1 i no e/i e l2ctl[l2io] = 0 dcbt_l2 dcbtst_l2 dl1 i,e e/el yes e/i same l2ctl[l2io] = 0 t no e/i el l2ctl[l2io] = 0. restore locked line with valid data from bus dcbtst_l1 dcbtstls_l1 dl1 i i/t no e same eyese i el yes e t dcbtls_l2 dcbtstls_l2 dl1 i,e i no i i l2ctl[l2io] = 1 t no i t l2ctl[l2io] = 1 e yes i i l2ctl[l2io] = 1 el yes i t l2ctl[l2io] = 1 i no i el l2ctl[l2io] = 0 e/el yes i el l2ctl[l2io] = 0 t no i el l2ctl[l2io] = 0. restore locked line with valid data from bus write-through store dl1 i,e,m i/t no same i e/el yes same same read-modify-write table 7-22. state transitions due to core-initiated transactions (continued) source of transaction initial states l2 hit final states comments l1 l2 l1 l2 4 datasheet u .com
l2 look-aside cache/sram MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 7-31 table 7-23 lists l2 cache state transitions for all system-initiated (non-core ) transactions that change the l2. the transaction types and attri butes listed follow mpx bus nomencl ature, with the addition of write allocate (burst write wi th l2 cache allocation). table 7-23 accounts for changes caused by l1 snoop pushes triggered by snoops, listed in table 7-22 . cache-inhibited store n/a i/e no n/a i invalidate line el/t no n/a t invalidate data, keep lock cache-inhibited stwcx. n/a i/e no n/a i invalidate line el/t no n/a t invalidate data, keep lock dcblc_l2 icblc_l2 dl1 i,e,m i/e no same same el no same e tnosamei victim castout dcbt_l2 icbt_l2 dcbtst_l2 dl1 m i/t no i same l2ctl[l2io] = 1. if software sharing cache lines between instructions and data wishes to capture instruction lines in l2 with l2ctl[l2io] = 1, it must perform dcbst to flush the line out of the dl1 before fetching it into l2. i no i e l2ctl[l2io] = 0 e/el no i i/t l2ctl[l2io] = 1 yes i same l2ctl[l2io] = 0 t yes i el l2ctl[l2io = 0 dcbtls_l2 icbtls_l2 dcbtstls_l2 dl1 m i no i el an icbtls_l2 that hits modified in l1 cannot be distinguished from dcbtls_l2 and sets the l2 dlock bit. if software shares cache lines between instructions and data and wishes to set ilocks in l2, it must perform dcbst to flush the line out of the dl1 before locking it in l2. e/el/t yes i el snoop push dl1 m i/e no i/e i el/t no i/e t invalidat e data, keep lock dcbf dcbst dl1 m i/e/el no i i dcbz dcba dl1 i i/e no m i el no m t dcbi dl1 i,e,m i/ e/el/t no i i dcbf dcbst dl1 i,e i/ e/el/t no i i icbi il1 i,v i/ e/el/t no i i table 7-22. state transitions due to core-initiated transactions (continued) source of transaction initial states l2 hit final states comments l1 l2 l1 l2 4 datasheet u .com
l2 look-aside cache/sram MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 7-32 freescale semiconductor table 7-23. state transitions due to system-initiated transactions transaction type wt ci gbl initial l2 state final l2 state comments clean ikill x x 0 i/e/el/t same flush x x 0 i/e/el/t i write allocate 0 1 0 i/e/el/t el allocate and lock regardless of cache external write (cew) window 1 1 0 i/e e allocate regardless of cew window el/t el x 0 0 i/e i no allocate if cache-inhibited el/t t invalidate data, keep lock wwk 32-byte wwf 32-byte wwf atomic x 1 0 i/e/el/t i miss in cache external write windows i e/el hit in cache external write window. set lock if cew lock attribute set el same ee/el tel x 0 0 i/e i invalidate line el/t t invalidate data, keep lock < 32-byte wwf < 32-byte wwf atomic x 1 0 i/e i miss in cache external write windows el/t t miss in cache external write windows i/t same hit in cew window but need burst data el same hit in cache external write window e e/el hit in cache external write window. set lock if cew lock attribute set x 0 0 i/e i invalidate line el/t t invalidate data, keep lock read read atomic 110 i/t same ee el el x 0 0 n/a n/a no l1/l2 effect rwnitc 1 1 0 i/l/t same ee el el 0 1 0 i same read-and-clear-lock el e ti x 0 0 n/a n/a no l1/l2 effect 4 datasheet u .com
l2 look-aside cache/sram MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 7-33 7.10 initialization/application information this section describes some required steps for initializing the l2 sram both in l2 cache mode, and in memory-mapped sram mode. also, it includ es some guidelines for error management. 7.10.1 initialization this section describes l1 cache and memory-mapped sram initialization. 7.10.1.1 l2 cache initialization after power-on reset, the valid bits in the l2 cache status array are in random states. therefore, it is necessary to perform a flash invalida te operation before using the array as an l2 cache. this is done by writing a 1 to the l2i bit of the l2 control register (l2ctl). this can be done before or simultaneously with the write that enables the l2 ca che. that is, the l2e and l2i bits of l2ctl can be set simultaneously. the l2i bit clears automatically, so no further writes are necessary. 7.10.1.2 memory-mapped sram initialization after power-on reset, the contents of the data and e cc arrays and are random, so all sram data must be initialized before it is read. if the cache is initializ ed by the core or any other de vice that uses sub-cacheline transactions, ecc error checking s hould be disabled during the initiali zation process to avoid false ecc errors generated during the read-modi fy-write process used for sub-cach eline writes to the sram array. this is done by setting the multi- and single-bit ecc er ror disable bits of the l2 error disable register (l2errdis[mbeccdis, sbeccdis]). see section 7.3.1.5.2, ?error contro l and capture registers.? if the array is initialized by a dma e ngine using cache-line wr ites, then ecc checking can remain enabled during the initial ization process. 7.10.2 managing errors this section describes recommended ha ndling for ecc and tag parity errors. 7.10.2.1 ecc errors an individual soft error that caus es a single- or multi-bit ecc error can be cleared from the l2 array simply by executing a dcbf instruction for the address captured in the l2erraddr register. this will invalidate the line in the l2 cache. when the load th at caused the ecc error is performed again, the data will be re-allocated into the l2 with ecc bits set properly again. kill rwitm rwitm atomic rclaim x 1 0 i/e i el/t t invalidate data, keep lock x 0 0 i/e/el/t same table 7-23. state transitions due to system-initiated transactions (continued) transaction type wt ci gbl initial l2 state final l2 state comments 4 datasheet u .com
l2 look-aside cache/sram MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 7-34 freescale semiconductor if the threshold for single bit errors set in the l2 errctl register is exceeded, then the l2 cache should be flash invalidated to clea r out all single-bit errors. note that no data is lost by executing dcbf instructions or flash invalidate operations because the l2 cache is write-through and contains no modified data. 7.10.2.2 tag parity errors a tag parity error must be fixed by flash inva lidating the l2 cache. no te that executing a dcbf instruction for the address that caused the error to be reported is not sufficient because a tag parity error is seen as an l2 miss and does not cause invalidation of the bad ta g. proper l2 operation cannot be guaranteed if an l2 tag parity error is not repaired by a flash invalidation of the entire array. 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor iii-1 part iii memory, security, and i/o interfaces this part defines the memory, security, and i/o in terfaces of the MPC8555E a nd it describes how these blocks interact with one another a nd with other blocks on the device. the following chapters are included: ? chapter 8, ?e500 coherency module,? defines the e500 coherency module and how it facilitates communication between the e500 core complex, the l2 cache and the other blocks that comprise the coherent memory domain of the MPC8555E. the ecm provides a mechanism for i/o-initiated transactions to snoop the core complex bus (ccb) of the e500 core in orde r to maintain cohere ncy across cacheable local memory. it also provides a flexible, easily expandabl e switch-type structure for e500- and i/o-initiated transactions to be routed (dispatched) to target modules on the MPC8555E. ? chapter 9, ?ddr memory controller,? describes the ddr sdram memory controller of the MPC8555E. this fully programmabl e controller supports most dd r memories available today, including both buffered and unbuffere d devices. the built-in error checking and correction (ecc) ensures very low bit error rates for reliable high-frequency operation. d ynamic power management and auto-precharge modes simplify memory system design. a large set of special features like dll software override, crawl mode, and ecc error injection support rapid system debug. ? chapter 10, ?programmable interrupt controller,? describes the em bedded programmable interrupt controller (pic) of th e MPC8555E. this controller is an openpic-compliant interrupt controller that provides interrupt management, and is responsible for receiving hardware-generated interrupts from different sources (both internal and external), prioritizing them, and delivering them to the cpu for servicing. ? chapter 11, ?i 2 c interface,? describes the inter-ic (iic or i 2 c) bus controller of the MPC8555E. this synchronous, serial, bidirect ional, multi-master bus allows two-wire connection of devices such as microcontrollers, eep roms, real-time clock devices, a/d converters, and lcds. the MPC8555E powers up in boot sequen cer mode which allows the i 2 c controller to initialize configuration registers. ? chapter 12, ?duart,? describes the (dual) universal asynchronous receiver/transmitters (uarts) which feature a pc16552d-compatible pr ogramming model. thes e independent uarts are provided specifically to support system debugging. ? chapter 13, ?local bus controller,? describes the local bus controller of the MPC8555E. the main component of the local bus controller (lbc) is its memory controller which provides a seamless interface to many types of memory devices and pe ripherals. the memory c ontroller is responsible for controlling eight memory banks shared by a high performance sdram machine, a general-purpose chip-select machine (gpcm), a nd up to three user-programmable machines (upms). as such, it supports a minimal glue l ogic interface to synchr onous dram (sdram), 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 iii-2 freescale semiconductor sram, eprom, flash eprom, burstable ram, regular dram devices, extended data output dram devices, and other peripherals. ? chapter 14, ?three-speed ethernet controllers,? describes the two three-speed ethernet controllers on the MPC8555E. these controller s provide 10/100/1gb ethernet support with a complete set of media-independe nt interface options including gmii, rgmii, tbi, and rtbi. each controller provides very high throughput using a captive dma channel and direct connection to the MPC8555E memory coherency module. ? chapter 15, ?dma controller,? describes the four-cha nnel general-purpose dm a controller of the MPC8555E. the dma controller transf ers blocks of data, independent of the e500 core or external hosts. the dma controller has four high-speed channels. both the e500 core and external masters can initiate a dma transfer. all channels are ca pable of complex data movement and advanced transaction chaining. ? chapter 16, ?pci bus interface,? describes the pci cont roller of the MPC8555E. ? chapter 17, ?security engine (sec) 2.0,? describes the security controller of the MPC8555E. 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 8-1 chapter 8 e500 coherency module 8.1 introduction the e500 coherency module (ecm) prov ides a flexible, easily expandabl e switching struct ure for routing e500- and i/o-initiated transactions to target modules on the device. figure 8-1 shows a high-level block diagram of the ecm. figure 8-1. e500 coherency module block diagram 8.1.1 overview the ecm routes transactions initia ted by the e500 core to the appropria te target interface on the device. in a manner analogous to a bridging router in a local area network, the ecm forwards i/o-initiated transactions that are tagged with th e global attribute onto the core comp lex bus (ccb). this allows on-chip data bus arbiter ccb arbiter i/o arbiter dispatch bus global data bus port data buses core complex bus (to/from e500) port data internal global data bus config reg?s configuration bus global data mux global (to ocean, request transaction queue ccb interface (from ocean, ddr, lbc?) ddr, lbc?) bus (internal) ? ? ? ? (to ocean, ddr, lbc,?) buses ocean tsec1 & 2 security cpm 4 datasheet u .com
e500 coherency module MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 8-2 freescale semiconductor caches to snoop these transactions as if they were locally initiated and to take actions to maintain coherency across cacheable memory. 8.1.2 features the ecm includes these distinctive features: ? support for e500 core and an l2/sram on the ccb, including a ccb arbiter. it sources a 64-bit data bus for returning read data from the ecm to the e500 core and rout ing write data from the ecm to the l2/sram. it sinks a 128-bit data bus for receiving data from the l2/sram and a 128-bit write data bus from the e500 core. ? four connection points for i/o- initiating (mastering into the de vice) interfaces. one of those connection points services ocean initiators, one services security, one services tsec1 & 2, and one services the cpm and other i/o initiators. the ecm supports five connection points for i/o targets. the ddr memory controll er, local bus, ocean targets, pr ogrammable interrupt controller (pic), and configuration regist er access block all have a targ et port connection to the ecm. ? split transaction support?separate address and data tenures allow for pipe lining of transactions and out-of-order data tenures be tween initiators and targets. ? proper ordering of i/o- initiated transactions. ? speculative read bus for low-latency di spatch of reads to the ddr controller. ? low-latency path for returning read data from ddr to the e500. ? error registers trap transactions with invalid addresses. errors can be programmed to generate interrupts to the e500 core, as desc ribed in the following sections: ? section 8.2.1.3, ?ecm error detect register (eedr)? ? section 8.2.1.4, ?ecm error enable register (eeer)? ? section 8.2.1.5, ?ecm error attribut es capture register (eeatr)? ? section 8.2.1.6, ?ecm error addre ss capture register (eeadr)? ? errors from reading i/o devices (for example, a master-aborted read transaction on the pci interface) terminate with data sent to the master with a corrupt attr ibute. if the master is the e500 core, the ecm asserts core_fault_in to the core, which causes the co re to generate a machine check interrupt, unless it is disabled (b y clearing hid1[rfxe]). if rfxe is zero and one of these errors occurs, appropriate interrupts must be enabled to ensure that an inte rrupt is generated. see section 6.10.2, ?hardware implementati on-dependent register 1 (hid1).? 8.2 memory map/register definition table 8-1 shows the ecm?s memory map. undefined 4- byte address spaces within offset 0x000?0xfff are reserved. table 8-1. ecm memory map local memory offset register access reset section/page 0x0_1000 eebacr?ecm ccb address configuration register r/w 0x0000_0003 8.2.1.1/8-3 0x0_1010 eebpcr?ecm ccb port configuration register r/w 0x0*00_0000 8.2.1.2/8-4 4 datasheet u .com
e500 coherency module MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 8-3 8.2.1 register descriptions this section consists of detailed descri ptions of those registers summarized in table 8-1 . note that these registers are shown in big-endian format. 8.2.1.1 ecm ccb address conf iguration register (eebacr) the ecm ccb address configur ation register, shown in figure 8-2 , controls arbitrat ion and streaming policies for the ccb. figure 8-2. ecm ccb address conf iguration register (eebacr) table 8-2 describes the eebacr fields. 0x0_1e00 eedr?ecm error detect register special 0x0000_0000 8.2.1.3/8-4 0x0_1e08 eeer?ecm error enable register r/w 0x0000_0000 8.2.1.4/8-5 0x0_1e0c eeatr?ecm error attributes capture register r 0x0000_0000 8.2.1.5/8-6 0x0_1e10 eeadr?ecm error address capture register r 0x0000_0000 8.2.1.6/8-7 02728293031 r a_strm_dis core_strm_dis a_strm_cnt w reset 0000_0000_0000_0000_0000_0000_0000_0011 offset 0x0_1000 table 8-2. eebacr field descriptions bits name description 0?27 ? reserved 28 a_strm_dis controls whether the ec m allows any streaming to occur. 0 streaming is enabled. 1 streaming is disabled. 29 core_strm_dis with a_strm_dis, controls whether the e500 core can stream commands onto the ccb. a_strm_dis and core_strm_dis must both be cleared for the e500 core to be enabled to stream address tenures that it masters. 0 stream address tenures initiated by the e5 00 core, provided a_strm_dis is cleared. 1 streaming of address tenures initiated by the e500 core not allowed. 30?31 a_strm_cnt stream count. specifies the maximum number of transactions that any master can stream (issue sequentially without preemption) on the ccb following an initial transaction. 00 reserved 01 one transaction can be streamed with the initial transaction. 10 two transactions can be streamed with the initial transaction. 11 three transactions can be streamed with the initial transaction (default). table 8-1. ecm memory map (continued) local memory offset register access reset section/page 4 datasheet u .com
e500 coherency module MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 8-4 freescale semiconductor 8.2.1.2 ecm ccb port confi guration register (eebpcr) the ecm ccb port configuration re gister (eebpcr) is shown in figure 8-3 . figure 8-3. ecm ccb port configuration register (eebpcr) table 8-3 describes eebpcr fields. 8.2.1.3 ecm error detect register (eedr) the ecm error detect regist er (eedr) is shown in figure 8-4 . figure 8-4. ecm error detect register (eedr) 0 678 29 30 31 r cpu_en cpu_pri w reset 0000_000*_0000_0000_0000_0000_0000_0000 offset 0x0_1010 table 8-3. eebpcr field descriptions bits name description 0?6 ? reserved 7 cpu_en cpu port enable. controls boot holdoff mode when the device is an agent of an external host. specifies whether the e500 core (cpu) port is enabled to run transactions on the ccb. the cpu boot configuration power-on reset pin (cfg_cpu_boot) determines the initial value of this bit. if the pin is sampled as a logic 1 at the negation of reset, the cpu is enabled to boot at the end of the po r sequence. otherwise, the cpu cannot fetch its boot vector until an external host sets the cpu_en bit. 0 boot holdoff mode. cpu arbitration is disabl ed on the ccb and no bus grants are issued. 1 cpu is enabled and receives bus grants in response to bus requests for the boot vector. after this bit is set, it should not be cleared by software. it is not intended to dynamically enable and disable cpu operation. it is only intended to end boot holdoff mode. see section 4.4.3.5, ?cpu boot configuration,? for more information. 8?29 ? reserved 30?31 cpu_pri specifies the priority level of the e500 core (cpu) port. this priority level is used to determine whether a particular port?s bus request can cause the ccb arbite r to terminate another port?s streaming of address tenures. 00 lowest priority level 01 second-lowest priority level 10 highest priority level 11 reserved 01 30 31 r mult_err lae w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x0_1e00 4 datasheet u .com
e500 coherency module MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 8-5 table 8-4 describes eedr fields. 8.2.1.4 ecm error enable register (eeer) the ecm error enable register (eeer) shown in figure 8-5 enables the reporting of error conditions to the e500 core through the internal int interrupt signal. figure 8-5. ecm error en able register (eeer) table 8-5 describes eeer fields. table 8-4. eedr field descriptions bits name description 0 mult_err multiple error. indicates the occurrence of mu ltiple errors of the same type. write 1 to clear. 0 multiple errors of the same type were not detected. 1 multiple errors of the same type were detected. 1?30 ? reserved 31 lae local access error. write 1 to clear. two cases can generate laes: ? transaction does not map to any target. in this case the ecm inject s read responses (with the corrupt attribute set) and write data is dropped. note that a read that attempts to access an unmapped target causes the assertion of core_fault_in , which causes the core to generate a machine check interrupt, unless it is disabled (by cleari ng hid1[rfxe]). if rfxe is zero and this error occurs, eeer[laee] must be set to ensure that an interrupt is generated. for more information, see section 6.10.2, ?hardware implementation-dependent register 1 (hid1).? ? source and target ids indicate that an ocn port in itiated a transaction that targets an ocn port. this loopback behavior can result from programming errors where inbound atmu window targets are inconsistent with targets configured in the local access windows for a given address range. for this type of lae, the dispatch (to ocn target in this case) is not screen ed off; the lae error is reported, but the transaction is still sent to its ocn target. 0 local access error has not occurred. 1 local access error occurred. 0 30 31 r laee w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x0_1e08 table 8-5. eeer field descriptions bits name description 0?30 ? reserved 31 laee local access error enable. note that a read that a ttempts to access an unmapped target causes the assertion of core_fault_in , which causes the core to generate a machine check interrupt, unless it is disabled (by clearing hid1[rfxe]). if rfxe is zero and this error occurs, laee must be set to ensure that an interrupt is generated. for more information, see section 6.10.2, ?hardware implem entation-dependent register 1 (hid1).? 0 disable reporting local access errors as interrupts. 1 enable reporting local access errors as interrupts. 4 datasheet u .com
e500 coherency module MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 8-6 freescale semiconductor 8.2.1.5 ecm error attributes capture register (eeatr) the ecm error attributes capture register (eeatr) is shown in figure 8-6 . figure 8-6. ecm error attributes capture register (eeatr) table 8-6 describes eeatr fields. 0 2 3 7 8 1011 151617 2021 30 31 r byte_cnt src_id 0 ttype val w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x0_1e0c table 8-6. eeatr field descriptions bits name description 0?2 ? reserved 3?7 byte_cnt byte count. specifies the transaction byte count. 00000 32 bytes 00001 1 byte 00010 2 bytes 00100 4 bytes 01000 8 bytes 10000 16 bytes 8?10 ? reserved 11?15 src_id source id. specifies the sour ce device mastering the transaction. 00000 pci1 interface 00001 pci2 interface 00010?00110 reserved 00111 security 01000?01001 reserved 01010 boot sequencer 01011?01111 reserved 10000 processor (instruction) 10001 processor (data) 10010 reserved 10011 reserved 10100 cpm 10101 dma 10110 reserved 10111 sap 11000 tsec1 11001 tsec2 11010?11111 reserved 16 ? reserved 17?20 ttype transaction type. defined as follows: 0000 write 0001 reserved 0010 write with allocate 0011 write with allocate with lock 0100 address only transaction 0101?0111 reserved 1000 read 1001 read with unlock 101x reserved 1100 read with clear atomic 1101 read with set atomic 1110 read with decrement atomic 1111 read with increment atomic 4 datasheet u .com
e500 coherency module MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 8-7 8.2.1.6 ecm error address capture register (eeadr) the ecm error address capture re gister (eeadr) is shown in figure 8-7 . figure 8-7. ecm error address capture register (eeadr) table 8-7 describes eeadr fields. 8.3 functional description the following is a very genera l discussion of ecm operation. 8.3.1 i/o arbiter figure 8-1 shows the i/o arbiter block that manages i/o- initiated address tenure requests arriving on the request buses. four request buses compete for access to the ecm, which can onl y process one request at a time. the ecm uses two fa ctors to select the winning request bus: the pr imary factor is request priority and the secondary factor is longest waiting/least recently gr anted status. by defau lt all requesters use the lowest priority (priority 0) for requests except for the cpm, which always requests at th e highest priority (priority 3). the tsec controllers dynamically raise a nd lower their priority le vels based on fifo depth. a starvation avoidance algorithm prev ents high-priority reque sts from indefinitely starving low-priority requesters. the transaction from the winning request bus competes w ith e500 core requests for the ccb and entry into the transaction queue. 21?30 ? reserved 31 val register data valid. 0 ecm error attribute capture register does not contain valid information. 1 ecm error attribute capture register contains valid information. 0 31 r addr w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x0_1e10 table 8-7. eeadr field descriptions bits name description 0?31 addr address. specifies the 32-bit address of the transaction. qualified by eeatr[val]. table 8-6. eeatr field descriptions (continued) bits name description 4 datasheet u .com
e500 coherency module MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 8-8 freescale semiconductor 8.3.2 ccb arbiter figure 8-1 shows the ccb arbiter block coordinating the entry of new transactions into the ecm?s transaction queue. it handles arbitr ation for requests to use the ccb from the e500 core and the winning request bus and consequently controls when these new transactions can ente r the transaction queue. because the ccb operates most effici ently when it streams commands fr om one initiator, the ccb arbiter alternates grants between streams of transactions from the processor and from the winner of the i/o arbiter. the length of a stream (num ber of back-to-back transactions) is limited by the a_strm_cnt field in the eebacr register. however, the arbiter also uses the pr iority of the requests to limit streaming. if the priority of a new request is higher than that of a stream in progress, then the higher-priority transaction will interrupt the other stream. the priority of e500 tr ansactions is set by the cpu_pri field in eebpcr register. 8.3.3 transaction queue the ecm?s transaction queue performs three ba sic functions: target mapping and dispatching, enforcement of ordering, and enforcem ent of coherency. the address of each transaction is compared against each local access window, and th e transaction is then routed to the appropriate target interface associated with the local access wi ndow that the address hits within. even though the ccb and ecm allow the pipelining of transactio ns, the address tenures of all transacti ons issued from masters other than the e500 core (all i/o masters) are strict ly ordered and are dispatch ed to their target interfaces in the same order they are submitted. for those trans actions accessing address space marked as snoopable, or space that may be cached by the e500 core, the ecm enforces cohere ncy, snooping those transactions on the ccb, and taking castouts from the e500 core as is necessary. 8.3.4 global data multiplexer figure 8-1 shows how the global data multiplexer takes da ta bus connections and multiplexes them onto one 128-bit global data bus. th e global data mux allows initiators of write transactions to route data to their targets and read targets to return data to the initiators. 8.3.5 ccb interface figure 8-1 shows the ccb interface for both ccb address and data tenures. this interface formats ccb address tenures for the ecm transa ction queue. it also contains th e queueing and buffering needed to manage outstanding ccb data tenures. the buffers receive e500 core-initi ated write and i/ o-initiated read data (that hit in the l2/sram m odule) from the e500 write (128-bit wide) and read (128-bit wide) data buses and route them through the global data mux to th e global data bus. the buffers also receive e500 core-initiated read a nd i/o-initiated write data (t hat hit in the l2/sram module) from the global data bus and forward them onto the ccb data bus (64 bits). 4 datasheet u .com
e500 coherency module MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 8-9 8.4 initialization/application information if the e500 core is used to init ialize the MPC8555E, the cpu boot conf iguration power-on reset pin should be pulled high to initially set eebpcr[cpu_en]. see chapter 4, ?reset, clocking, and initialization,? for more information on power-up reset initialization. if any device other than the e500 core, such as th e boot sequencer or pci, is used to initialize the MPC8555E, the cpu boot configurati on power-on reset pin should be pulled low to initially clear eebpcr[cpu_en]. this prevents the e500 core from accessing any configurat ion registers or local memory space during initialization. however, in any such system, one step near th e end of the initialization routine must set eebpcr[cpu_en] to re-enable th e e500 core. note that for basic functionality, eebpcr[cpu_en] is the only field that must be written (provided a devi ce other than the e500 core is used to initialize the device) in the ecm. eebpcr[cpu_pri] specifies the priori ty level associated with all e500 core?initiated transactions. this value allows users running ti me-critical applications to adjust the average response latency of transactions initiated by the core compared to thos e initiated by i/o masters. this prio rity level affects whether the e500 core requests can interrupt the streaming of addres s tenures initiated by (the ecm on behalf of) i/o masters. only transactions with a priority greater th an the current ccb transacti on can interrupt streaming. the higher the core?s priority, the lower the average la tency needed for it to obtain bus grants from the ecm, because it can interrupt lower-priority streami ng. the default value of zero gives all core-initiated transactions the lowest priority, which prevents the co re from interrupting i/o ma ster transaction streams. eebacr[a_strm_cnt] allows users to balance response latency w ith throughput and should prove useful in tuning systems with mult iple time-critical tasks. the defa ult value of 0b11 causes the ecm to attempt to stream as many as four transactions initiated from the same ccb master. increasing this value increases the maximum number of tran sactions that may be streamed t ogether from any one ccb master. raising this value can increase throughput for high-priority transact ions, but may incr ease latency for lower-priority transactions from a nother ccb master. note that the e 500 core must also have streaming enabled (through hid1[astme]) for the ccb to stream. 4 datasheet u .com
e500 coherency module MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 8-10 freescale semiconductor 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 9-1 chapter 9 ddr memory controller 9.1 introduction the fully programmable ddr sdra m controller supports most first-generation jedec standard 8 or 16 ddr memories available, including buffered and unbuffered dimms. however, mixing unbuffered and registered dimms in the same system is not supporte d. built-in error checki ng and correction (ecc) ensures very low bit-error rates for reliable hi gh-frequency operation. dynami c power management and auto-precharge modes simplify memory system design. note in this chapter, the word ?bank? refers to a physical bank specified by a chip select; ?logical bank? refe rs to one of the four sub-banks in each sdram chip. a sub-bank is specified by the two least significant bits (lsbs) of a bank address. figure 9-1 is a high-level block di agram of the ddr memory controller with its associated interfaces. section 9.5, ?functional description,? contains detailed figures of the controller. 4 datasheet u .com
ddr memory controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 9-2 freescale semiconductor figure 9-1. ddr memory controller simplified block diagram 9.2 features the ddr memory controller includes these distinctive features: ? support for ddr sdram ? 64-/72-bit sdram data bus ? programmable settings for meet ing all sdram timing parameters ? the following sdram configurations are supported ? as many as four physical banks (chip se lects), each bank indepe ndently addressable ? 64-mbit to 1-gbit devices with 8/ 16 data ports (no direct 4 support) ? unbuffered and registered dimms ? support for data mask signals and read-modify-w rite for sub-double word writes. note that read-modify-write sequence is only necessary when ecc is enabled. ? support for double-bit error detecti on and single-bit error correcti on ecc (8-bit check word across 64-bit data) ? two-entry input request queue address from ddr sdram data from data from ddr sdram data signals rmw ecc request from row physical bank, fifo sdram address open row address en en data qualifiers clocks to error ma[0:14] mba[0:1] mcs [0:3] mcas mras mwe mdm[0:8] mcke[0:1] mdqs[0:8] mdq[0:63] mecc[0:7] mck[0:5] decode control open logical bank, row ta b l e control dram input staging queue memory array memory control master master sdram master management mck [0:5] ecm ecc delay chain error signals sdram control clock control 4 datasheet u .com
ddr memory controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 9-3 ? open page management (dedicat ed entry for each logical bank) ? memory controller clock freque ncy of two times the sdram cloc k with support for sleep power management ? support for error injection 9.2.1 modes of operation the ddr memory controller supports the following modes: ? dynamic power management mode . the ddr memory controller can reduce power consumption by negating the sdram cke signal when no tr ansactions are pending to the sdram. ? auto-precharge mode. clearing ddr_sdra m_interval[bstopre] causes the memory controller to issue an auto precharge command with every read or write tr ansaction. auto precharge mode can be enabled for separa te chip selects by setting cs n _config[ap_ n _en]. 9.3 external signal descriptions this section provides descriptions of the ddr memory controller?s external signals. it describes each signal?s behavior when the signal is asserted or nega ted and when the signal is an input or an output. note a bar over a signal name indicates that the signal is active low, such as as (address strobe). active-low signals are referred to as asserted (active) when they are low and negated when they are high. signals that ar e not active low, such as nmi (nonmaskable interrupt), are referred to as asserted when they are high and negated when they are low. 9.3.1 signals overview memory controller signals are grouped as follows: ? memory interface signals ? clock signals ? debug signals table 9-1 shows how ddr memory controller external signals are grouped. the MPC8555E powerquicc? iii integrated processor hardware specifications has a pinout diag ram showing pin numbers. it also lists all electric al and mechanical specifications. table 9-1. ddr memory interface signal summary name function/description reset pins i/o mdq[0:63] data bus all zeros 64 i/o mdqs[0:8] data strobes all zeros 9 i/o mecc[0:7] error checking a nd correcting all zeros 8 i/o mcas column address strobe high-z 1 o 4 datasheet u .com
ddr memory controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 9-4 freescale semiconductor table 9-2 shows the memory address signal mappings. 9.3.2 detailed signal descriptions the following sections desc ribe the ddr sdram controll er input and output signal s, the meaning of their different states, and relative timing information for assertion and negation. ma[0:14] address bus high-z 15 o mba[0:1] logical bank address high-z 2 o mcs [0:3] chip select high-z 4 o mwe write enable high-z 1 o mras row address strobe high-z 1 o mdm[0:8] data mask high-z 9 o mck[0:5] dram clock outputs high-z 6 o mck [0:5] dram clock outputs (complement) high-z 6 o mcke[0:1] dram clock enable driven low 2 o mdval memory debug data valid zero 1 o msrcid[0:4] memory debug source id all zeros 5 o table 9-2. memory address signal mappings signal name (outputs) jedec ddr dimm signals (inputs) signal name (outputs) jedec ddr dimm signals (inputs) sdram 168-pin dimm sdram 168-pin dimm msb ma14 ? ma5 a5 ma13 a13 ma4 a4 ma12 a12 ma3 a3 ma11 a11 ma2 a2 ma10 a10(ap) ma1 a1 ma9 a9 ma0 a0 ma8 a8 mba1 ba1 ma7 a7 lsb mba0 ba0 ma6 a6 table 9-1. ddr memory interface signal summary (continued) name function/description reset pins i/o 4 datasheet u .com
ddr memory controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 9-5 9.3.2.1 memory interface signals table 9-3 describes the ddr controller memory interface signals. table 9-3. memory interface signals?detailed signal descriptions signal(s) i/o description mdq[0:63] i/o data bus. both input and out put signals on the ddr memory controller. o as outputs for the bidirectional data bus, these signals operate as described below. state meaning asserted/negated?represent the value of data being driven by the ddr memory controller. timing assertion/negation?driven coincident with corresponding data strobes (mdqs) signal. high impedance?no read or write command is in progress; data is not being driven by the memory controller or the dram. i as inputs for the bidirectional data bus, these signals operate as described below. state meaning asserted/negated?represents the state of data being driven by the external ddr sdrams. timing assertion/negation?the ddr dimm drives data during a read transaction. high impedance?no read or write command in progress; data is not being driven by the memory controller or the dram. mdqs[0:8] i/o data strobes. inputs with read data and as outputs with write data. o as outputs, the data strobes are driven by the ddr memo ry controller during a write transaction. the memory controller always drives these signals low unless a read has been issued and incoming data strobes are expected. this keeps the data strobes from floatin g high when there are no transactions on the dram interface. state meaning asserted/negated?driven high when positive capture data is transmitted/received and driven low when negative capture data is transmitted/rece ived. centered in the data ?eye? for writes; coincident with the data eye for reads. treated as a clock. data is valid when signals toggle. see ta bl e 9 - 2 6 for byte lane assignments. timing assertion/negation?if a write command is registered at clock edge n , data strobes at the dram assert centered in the data ?eye? on clock edge n + 1. see the jedec ddr sdram specification for more information. i as inputs, the data strobes are driven by the exte rnal ddr sdrams during a read transaction. the data strobes are used by the memory controller to synchronize data latching. state meaning asserted/negated?driven high when positive capture data is transmitted/received and driven low when negative capture data is transmitted/rece ived. centered in the data ?eye? for writes; coincident with the data eye for reads. treated as a clock. data is valid when signals toggle. see ta bl e 9 - 2 6 for byte lane assignments. timing assertion/negation?if a read command is registered at clock edge n , and the latency is programmed in timing_cfg_1[caslat] to be m clocks, data strobes at the dram assert coincident with the data on clock edge n+m . see the jedec ddr sdram specification for more information. 4 datasheet u .com
ddr memory controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 9-6 freescale semiconductor mecc[0:7] i/o error checking and correcting codes. input and outpu t signals for the ddr controller?s bidirectional ecc bus. mecc[0:5] function in both normal and debug modes. o as normal mode outputs the ecc signals represent the st ate of ecc driven by the ddr controller on writes. as debug mode outputs mecc[0:5] provide s ource id and data-valid information. see section 20.4.3.2, ?debug information on ecc pins,? for more details. state meaning asserted/negated?represents the state of ecc being driven by the ddr controller on writes. timing assertion/negation?same timing as mdq high impedance?same timing as mdq i as inputs, the ecc signals represent the state of ecc driven by the sdram devices on reads. state meaning asserted/negated?represents th e state of ecc being driven by the ddr sdrams on reads. timing assertion/negation?same timing as mdq high impedance?same timing as mdq ma[0:14] o address bus. memory controller outputs for the addr ess to the dram. ma[0:14] carry 15 of the address bits for the ddr memory interface corresponding to the ro w and column address bits. ma[0] is the lsb of the address output from the memory controller. state meaning asserted/negated?represents the address driv en by the ddr memory controller. contains different portions of the address depending on the memory size and the dram command being issued by the memory controller. see ta b l e 9 - 2 8 for a complete description of the mapping of these signals. timing assertion/negation?the address is always driven when the memory controller is active. it is valid when a transaction is driven to dram (when mcs n is negated). high impedance?when the memory controller is idle. mba[0:1] o logical bank address. outputs that drive the logical (or internal) b ank address pins of the sdram. each sdram supports four addressable logical sub-banks. bit zero of the memory controller?s output bank address must be connected to bit zero of the sdram?s input bank address. mba[0] is asserted during the mode register set command to specify the extended mode register. state meaning asserted/negated?selects the ddr sdram logical (or internal) bank to be activated during the row address phase and selects the sdram inte rnal bank for the read or write operation during the column address phase of the memory access. ta b l e 9 - 2 8 describes the mapping of these signals in all cases. timing assertion/negation?same timing as ma n high-impedance?same timing as ma n mcas o column address strobe. active-low sdram address multiplexing signal. mcas is asserted for read or write transactions and for mode register set, refresh, and precharge commands. state meaning asserted?indicates that a valid sdram column addr ess is on the address bus for read and write transactions. see ta bl e 9 - 2 9 for more information on the states required on mcas for various other sdram commands. negated?the column address is not guaranteed to be valid. timing assertion/negation?assertion and negation timing is directed by the values described in section 9.4.1.3, ?ddr sdram timing configuration 1 (timing_cfg_1).? high impedance?mcas is always driven unless the memory controller is idle. table 9-3. memory interface signals?de tailed signal descriptions (continued) signal(s) i/o description 4 datasheet u .com
ddr memory controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 9-7 mras o row address strobe. active-low sdram address multiplexing signal. asserted for activate commands. in addition; used for mode register set commands and refresh commands. state meaning asserted?indicates that a valid sdram row addre ss is on the address bus for read and write transactions. see ta bl e 9 - 2 9 for more information on the states required on mras for various other sdram commands. negated?the row address is not guaranteed to be valid. timing assertion/negation?timing is directed by the values described in section 9.4.1.3, ?ddr sdram timing configuration 1 (timing_cfg_1).? high impedance?mras is always driven unless the memory controller is idle. mcs [0:3] o chip select. four chip selects supported by the memory controller. state meaning asserted?selects a physical sdram bank to perform a memory operation as described in section 9.4.1.1, ?chip select memory bounds (csn_bnds),? and section 9.4.1.2, ?chip select configuration (csn_config).? the ddr controller asserts one of the mcs [0:3] signals to begin a memory cycle. negated?indicates no sdram acti on during the current cycle timing assertion/negation?asserted to signal any new tr ansaction to the sdram. the transaction must adhere to the timing constraints set in timing_cfg_1. high impedance?always driven unless the memory controller is disabled mwe o write enable. asserted when a write transaction is issued to the sdram. this is also used for mode registers set commands and precharge commands. state meaning asserted?indicates a memory write operation. see ta b l e 9 - 2 9 for more information on the states required on mwe for various other sdram commands. negated?indicates a memory read operation timing assertion/negation?similar timing as mras and mcas . used for write commands. high impedance?mwe is always driven unless the memory controller is idle. mdm[0:8] o ddr sdram data output mask. masks unwanted bytes of data transferred during a burst write. they are needed to support sub-burst-size transactions (such as single-byte writes) on sdram where all i/o occurs in multi-byte bursts. mdm0 corresponds to the most significant byte (msb); mdm7 corresponds to the lsb. mdm8 corresponds to the ecc byte. ta bl e 9 - 2 6 shows byte lane encodings. state meaning asserted?prevents writing to ddr sdram. asse rted when data is written to dram if the corresponding byte(s) should be masked for the write. note that the mdm n signals are active-high for the ddr controller. mdm n is part of the ddr command encoding. negated?allows the corresponding byte to be read from or written to the sdram timing assertion/negation?same timing as mdqx as outputs high impedance?always driven unless the memory controller is disabled table 9-3. memory interface signals?de tailed signal descriptions (continued) signal(s) i/o description 4 datasheet u .com
ddr memory controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 9-8 freescale semiconductor 9.3.2.2 clock interface signals table 9-4 contains the detailed descriptions of the clock signals of the ddr controller. 9.3.2.3 debug signals the debug signals msrcid[0:4] and mdval have no function in normal ddr controller operation. a detailed description of th ese signals can be found in section 20.4.3, ?ddr sdram interface debug.? 9.4 memory map/register definition table 9-5 shows the register memory map for the ddr memory controller. u ndefined 4-byte address spaces within offset 0x000?0xfff are reserved. table 9-4. clock signals?detailed signal descriptions signal(s) i/o description mck[0:5], mck [0:5] o dram clock outputs and their complements. see section 9.5.4.1, ?clock distribution.? state meaning asserted/negated?the jedec ddr sdram spec ifications require true and complement clocks. a clock edge is seen by the sdram when the true and complement cross. timing assertion/negation? source synchronous configuration as defin ed by the ddr_sdram_clk_cntl register determines timing relationship. mcke[0:1] o clock enable. two identical output signals (each he reafter referred to simply as mcke) used as the clock enable to one or more sdrams. mcke can be negated to stop clocking the ddr sdram. while this results in system power savings, the user is cautioned to disable sdra m clocking only wh en there are no transactions on the interface. state meaning asserted?clocking to the sdram is enabled. negated?clocking to the sdram is disabled and the sdram should ignore signal transitions on mck or mck . mck/mck are don?t cares while mcke is negated. timing assertion/negation?similar timing to ma n high impedance?always driven table 9-5. ddr memory controller memory map offset register access reset section/page 0x0_2000 cs0_bnds?chip select 0 memory bounds r/w 0x0000_0000 9.4.1.1/9-9 0x0_2008 cs1_bnds?chip select 1 memory bounds 0x0_2010 cs2_bnds?chip select 2 memory bounds 0x0_2018 cs3_bnds?chip select 3 memory bounds 0x0_2080 cs0_config?chip select 0 configuration r/w 0x0000_0000 9.4.1.2/9-10 0x0_2084 cs1_config?chip select 1 configuration 0x0_2088 cs2_config?chip select 2 configuration 0x0_208c cs3_config?chip select 3 configuration 0x0_2108 timing_cfg_1?ddr sdram timing configuration 1 r/w 0x0000_0000 9.4.1.3/9-11 4 datasheet u .com
ddr memory controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 9-9 9.4.1 register descriptions this section describes the ddr memory controller registers. shading indi cates reserved fi elds that should not be written. 9.4.1.1 chip select memory bounds (cs n _bnds) the chip select bounds registers (cs n _bnds) shown in figure 9-2 define the starting and ending address of the memory space that corresponds to the individual chip selects. note that the size specified in cs n _bnds should equal the size of physical dram. also, note that ea n must be greater than or equal to sa n . if the high-order 8 bits of an a ddress are greater than or equal to sa n , and they are less than or equal to ea n , then chip select n will be used. 0x0_210c timing_cfg_2?ddr sdram timing configuration 2 r/w 0x0000_0000 9.4.1.4/9-12 0x0_2110 ddr_sdram_cfg?ddr sdram cont rol configuration r/w 0x0200_0000 9.4.1.5/9-13 0x0_2118 ddr_sdram_mode?ddr sdram mode configuration r/w 0x0000_0000 9.4.1.6/9-14 0x0_2124 ddr_sdram_interval?ddr sdram interval configuration r/w 0x0000_0000 9.4.1.7/9-15 0x0_2130 ddr_sdram_clk_cntl?ddr sdram clock control r/w 0x0000_0000 9.4.1.8/9-16 0x0_2e00 data_err_inject_hi?memory data pat h error injection mask high r/w 0x0000_0000 9.4.1.9/9-17 0x0_2e04 data_err_inject_lo?memory data pat h error injection mask low r/w 0x0000_0000 9.4.1.10/9-17 0x0_2e08 ecc_err_inject?memory data path error injection mask ecc r/w 0x0000_0000 9.4.1.11/9-18 0x0_2e20 capture_data_hi?memory data pat h read capture high r/w 0x0000_0000 9.4.1.12/9-19 0x0_2e24 capture_data_lo?memory data pat h read capture low r/w 0x0000_0000 9.4.1.13/9-19 0x0_2e28 capture_ecc?memory data pa th read capture ecc r/w 0x0000_0000 9.4.1.14/9-20 0x0_2e40 err_detect?memory error detect special 0x0000_0000 9.4.1.15/9-20 0x0_2e44 err_disable?memory error disable r/w 0x0000_0000 9.4.1.16/9-21 0x0_2e48 err_int_en?memory error interrupt enable r/w 0x0000_0000 9.4.1.17/9-22 0x0_2e4c capture_attributes?memory e rror attributes capture r/w 0x0000_0000 9.4.1.18/9-22 0x0_2e50 capture_address?memory error address capture r/w 0x0000_0000 9.4.1.19/9-23 0x0_2e58 err_sbe?single-bit ecc memory error management r/w 0x0000_0000 9.4.1.20/9-24 0 78 1516232431 r00000000 sa n 00000000 ea n w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x0_2000, 0x0_2008, 0x0_2010, 0x0_2018 figure 9-2. chip select bounds registers (cs n _bnds) table 9-5. ddr memory controller memory map (continued) offset register access reset section/page 4 datasheet u .com
ddr memory controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 9-10 freescale semiconductor table 9-6 describes the cs n _bnds register fields. 9.4.1.2 chip select configuration (cs n _config) the chip select configuration (cs n _config) registers shown in figure 9-3 enable the ddr chip selects and set the number of row and column bits used for each chip select. these registers should be loaded with the correct number of row and column bits for each sdram. because cs n _config[row_bits_cs_ n ,col_bits_cs_ n ] establish address mul tiplexing, the user should take great care to set these values correctly. table 9-7 describes the cs n _config register fields. table 9-6. cs n_ bnds field descriptions bits name description 0?7 ? reserved 8?15 sa n starting address for chip select (bank) n. this value is compared against the 8 msbs of the address. 16?23 ? reserved 24?31 ea n ending address for chip select (bank) n. this value is compared against the 8 msbs of the address. 0 1 7 8 9 2021 2324 2829 31 r cs_ n _ en 0000000 ap_n_en 00000000000 0 row_bits_cs_ n 00000 col_bits_cs_ n w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x0_2080, 0x0_2084, 0x0_2088, 0x0_208c figure 9-3. chip select configuration register (cs n _config) table 9-7. cs n _config field descriptions bits name description 0cs_ n _en chip select n enable 0 chip select n is not active. 1 chip select n is active and assumes the state set in csn_bnds. 1?7 ? reserved 8 ap_n_en chip select n auto precharge enable 0 chip select n is auto precharged only if global auto precharge mode is enabled (ddr_sdram_interval[bstopre] = 0). 1 chip select n always issues an auto precharge for read and write transactions. 9?20 ? reserved 21?23 row_bits_cs_ n number of row bits for sdram on chip select n 000 12 row bits 001 13 row bits 010 14 row bits 011?111 reserved 4 datasheet u .com
ddr memory controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 9-11 9.4.1.3 ddr sdram timing configuration 1 (timing_cfg_1) ddr sdram timing configurat ion register 1, shown in figure 9-4 , sets the number of clock cycles between various sdram control commands. table 9-8 describes timing_cfg_1 fields. 24?28 ? reserved 29?31 col_bits_cs_ n number of column bits for sdram on chip select n 000 8 column bits 001 9 column bits 010 10 column bits 011 11 column bits 011?111 reserved 0 1 3 4 7 8 9 11 1213 1516 192021 2324 25 27 28 29 31 r0 pretoact acttopre 0 acttorw 0 caslat refrec 0 wrrec 0 acttoact 0 wrtord w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x0_2108 figure 9-4. ddr sdram timing confi guration register 1 (timing_cfg_1) table 9-8. timing_cfg_1 field descriptions bits name description 0 ? reserved, should be cleared. 1?3 pretoact precharge-to-activate interval (t rp ). determines the number of clock cycles from a precharge command until an activate or refresh command is allowed. 000 reserved 001 1 clock 010 2 clocks 011 3 clocks 100 4 clocks 101 5 clocks 110 6 clocks 111 7 clocks 4?7 acttopre activate to precharge interval (t ras ). determines the number of cloc k cycles from an activate command until a precharge command is allowed. 0000 reserved 0001 1 clock 0010 2 clocks 0010 2 clocks ? 1111 15 clocks 8 ? reserved, should be cleared. 9?11 acttorw activate to read/write interval for sdram (t rcd ). controls the number of clock cycles from an activate command until a read or write command is allowed. 000 reserved 001 1 clock 010 2 clocks 011 3 clocks 100 4 clocks 101 5 clocks 110 6 clocks 111 7 clocks 12 ? reserved, should be cleared. table 9-7. cs n _config field descriptions (continued) bits name description 4 datasheet u .com
ddr memory controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 9-12 freescale semiconductor 9.4.1.4 ddr sdram timing configuration 2 (timing_cfg_2) ddr sdram timing configuration 2, shown in figure 9-5 , sets the clock delay to data for writes. figure 9-5. ddr sdram timing confi guration register 2 (timing_cfg_2) 13?15 caslat mcas latency from read command. number of clock cycles between registrati on of a read command by the sdram and the availability of the first output data. if a read command is registered at clock edge n and the latency is m clocks, data is available nominally coincident with clock edge n + m . this value must be programmed at initialization as described in section 9.4.1.6, ?ddr sdram mode configuration (ddr_sdram_mode).? ) 000 reserved 001 1 clock 010 1 . 5 clocks 011 2 clocks 100 2 . 5 clocks 101 3 clocks 110 3 . 5 clocks 111 4 clocks 16?19 refrec refresh recovery time (t rfc ). controls the number of clock cycl es from a refresh command until an activate command is allowed. refresh recovery time is equal to eight plus the refrec value. 0000 24 clocks 0001 9 clocks 0010 10 clocks 0011 11 clocks ? 1111 23 clocks 20 ? reserved, should be cleared. 21?23 wrrec last data to precharge minimum interval (t wr ). determines the number of clock cycles from the last data associated with a write command until a precharge command is allowed. 000 0 clock 001 1 clock 010 2 clocks 011 3 clocks 100 4 clocks 101 5 clocks 110 6 clocks 111 7 clocks 24 ? reserved, should be cleared. 25?27 acttoact activate-to-activate interval (t rrd ). number of clock cycles from an activate command until another activate command is allowed for a different logical bank in the same physical bank (chip select). 000 reserved 001 1 clock 010 2 clocks 011 3 clocks 100 4 clocks 101?111 reserved 28 ? reserved, should be cleared. 29?31 wrtord last write data pair to read command issue interval (t wtr ). number of clock cycles between the last write data pair and the subsequent read command to the same physical bank. 000 reserved 001 1 clock 010 2 clocks 011 3 clocks 100 4 clocks 101 5 clocks 110 6 clocks 111 7 clocks 0 34 78 111213 1819 2122 31 r0000 cpo 0000 acsm 000000 wr_data_delay 0000000000 w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x0_210c table 9-8. timing_cfg_1 field descriptions (continued) bits name description 4 datasheet u .com
ddr memory controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 9-13 table 9-9 describes the timing_cfg_2 fields. 9.4.1.5 ddr sdram control c onfiguration (ddr_sdram_cfg) the ddr sdram control confi guration register, shown in figure 9-6 , enables the interface logic and specifies certain operating features such as self refreshing, error checking and correcting, registered dimms, and dynamic power management. figure 9-6. ddr sdram control conf iguration register (ddr_sdram_cfg) table 9-9. timing_cfg_2 register field descriptions bits name description 0?3 ? reserved 4?7 cpo mcas -to-preamble override. defines the number of dram cycles between when a read is issued and when the corresponding dqs preamble is valid for the memory controller. 0000 default. mcas to preamble is defined as caslat + 1 0001 0010 + 1/2 0011 + 1 0100 + 3/2 0101 + 2 0110 + 5/2 0111 + 3 1000 + 7/2 1001 + 4 1010 + 9/2 1011 + 5 1100?1111 reserved 8?11 ? reserved 12 acsm address and control shift mode 0 the dram address and control buses are output in the default mode. 1 the dram address and control buses are delayed by 1/2 dram cycle before being driven onto the pins. 13?18 ? reserved 19?21 wr_data_delay write command to write data strobe timing adjustment. controls the am ount of delay applied to the data and data strobes for writes. 000 0 clock delay 001 2/8 clock delay (recommended) 010 4/8 clock delay 011 6/8 clock delay 100 1 clock delay 101?111 reserved 22?31 ? reserved 0 1 2 3 4 5 6 7 8 9 10 11 13 14 15 r mem_en sren ecc_en rd_en 0 0 sdram_type 0 0 dyn_pwr 000 ncap 0 w reset 0000_0010_0000_0000 16 17 31 2t_en 0 0 0 000 000 0 00000 0000_0000_0000_0000 offset 0x0_2110 caslat caslat caslat caslat caslat caslat caslat caslat caslat caslat caslat 4 datasheet u .com
ddr memory controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 9-14 freescale semiconductor table 9-10 describes the ddr_sdram_cfg fields. 9.4.1.6 ddr sdram mode conf iguration (ddr_sdram_mode) the ddr sdram mode configur ation register, shown in figure 9-7 , sets the values loaded into the ddr?s mode registers. table 9-10. ddr_sdram_cfg field descriptions bits name description 0 mem_en ddr sdram interface logic enable 0 sdram interface logic is disabled 1 sdram interface logic is enabled. must not be set until all other memory configuration parameters have been appropriately configured by initialization code. 1 sren self refresh enable (during sleep) 0 sdram self refresh is disabled during sleep or soft-stop. whenever self-refresh is disabled, the system is responsible for preserving the inte grity of sdram during sleep or soft-stop. 1 sdram self refresh is enabled during sleep or soft-stop 2 ecc_en ecc enable. note that uncorrectable read errors may cause the assertion of core_fault_in , which causes the core to generate a machine check interrupt unless it is disabled (by clearing hid1[rfxe]). if rfxe is zero and this error occurs, err_disable[mbed ] must be zero and err_int_en[mbee] and ecc_en must be one to ensure an interrupt is generated. see section 6.10.2, ?hardware implementat ion-dependent register 1 (hid1).? 0 no ecc errors are reported. no ecc interrupts are generated. 1 ecc is enabled. 3 rd_en registered dimm enab le. specifies the type of dimm used in the system. 0 indicates unbuffered dimms. 1 indicates registered dimms. 4?5 ? reserved 6?7 sdram_type type of sdram device to be used 00?01 reserved 10 ddr sdram 11 reserved 8?9 ? reserved 10 dyn_pwr dynamic power management mode 0 dynamic power management mode is disabled. 1 dynamic power management mode is enabled. if there is no ongoing memory activity, the sdram cke signal is negated. 11?13 ? reserved 14 ncap non-concurrent auto precharge 0 sdrams in system support concurrent auto precharge. 1 sdrams in system do not support concurrent auto precharge. 15 ? reserved 16 2t_en 2t timing enable 0 1t timing is used. the sdram command/address are held for only 1 cycle on the sdram bus. 1 2t timing is enabled. the sdram command/address are held for 2 full cycles on the sdram bus for every sdram transaction. however, the chip select is only held for the second cycle. 17?31 ? reserved 4 datasheet u .com
ddr memory controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 9-15 figure 9-7. ddr sdram mode confi guration register (ddr_sdram_mode) table 9-11 describes the ddr_sdram_mode fields. 9.4.1.7 ddr sdram interval conf iguration (ddr_sdram_interval) the ddr sdram interval confi guration register, shown in figure 9-8 , sets the number of dram clock cycles between bank refres hes issued to the ddr sd rams. in addition, the numbe r of dram cycles that a page is maintained after it is accessed is provided here. 0151631 r esdmode sdmode w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x0_2118 table 9-11. ddr_sdram_mode field descriptions bits name description 0?15 esdmode [0:15] extended sdram mode. specifies the initial value loaded into the ddr sdram extended mode register. the range and meaning of legal values is specified by the ddr sdram manufacturer. the value of esdmode[1:15] is driven onto ma[14:0] during th e extended mode register set operation of the initialization sequence. the lsb of esdmode (esdmode[15]) is driven onto ma[0] and esdmode[1] is driven onto ma[14]. 16?31 sdmode [0:15] sdram mode. specifies the initial value loaded into the ddr sdram mode register. the range of legal values of legal values is specified by the ddr sdram manufacturer. the value of sdmode[1:15] is driv en onto ma[14:0] during the mode register set operation of the initialization sequence. the lsb of sdmode (sdmod e[15]) is driven onto ma[0] and sdmode[1] is driven onto ma[14]. because the memory controller forces sdmode[3?8] to certain values depending upon the state of the initialization sequence (for resett ing the sdram?s dll) the corresponding bits of this field is ignored by the memory controller. 0 1 2 15 16 17 18 31 r0 0 refint 00 bstopre w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x0_2124 figure 9-8. ddr sdram interval configur ation register (ddr_sdram_interval) 4 datasheet u .com
ddr memory controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 9-16 freescale semiconductor table 9-12 describes the ddr_sdram_interval fields. 9.4.1.8 ddr sdram clock c ontrol (ddr_sdram_clk_cntl) the ddr sdram clock control conf iguration register, shown in figure 9-9 , provides a source synchronous option, along with a 1/4 cycle clock adjustment. note the ddr_sdram_clk_cntl[ss_en] defa ult value out of reset is 0 and this must be set to a 1 for proper operation. figure 9-9. ddr sdram clock control register (ddr_sdram_clk_cntl) table 9-13 describes the ddr_sdram_clk_cntl fields. table 9-12. ddr_sdram_interval field descriptions bits name description 0?1 ? reserved 2?15 refint refresh interv al. represents the number of memory bus clock cycles betw een refresh cycles. one row is refreshed in each ddr sdram physical bank during each refresh cycle. the va lue for refint depends on the specific sdrams used and the interface clock frequency. note that refint must be set to a non-zero va lue in order for the ddr to enter sleep mode. see section 18.5.1.5.3, ?sleep mode,? for additional details. 16?17 ? reserved 18?31 bstopre precharge interval. sets the duration (in memory bus clocks) that a page is retained after a ddr sdram access. if bstopre is zero, the ddr memory cont roller uses auto precharge read and write commands rather than operating in page mode. this is called global auto precharge mode. 0 1 45 78 31 r ss_en 0000 clk_adjst 00000000000000000000000 0 w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x0_2130 table 9-13. ddr_sdram_clk_cntl field descriptions bits name description 0 ss_en source synchronous enable. this bitfield must be set during initialization. see section 9.6.1, ?ddr sdram initialization sequence,? for details. 0reserved 1 the address and command are sent to the ddr sdrams source synchronously. 1?4 ? reserved 4 datasheet u .com
ddr memory controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 9-17 9.4.1.9 memory data path error inject ion mask high (data_err_inject_hi) the memory data path error injecti on mask high register is shown in figure 9-10 . figure 9-10. memory data path error injection mask high register (data_err_inject_hi) table 9-14 describes the data_err_inject_hi fields. 9.4.1.10 memory data path error in jection mask low (data_err_inject_lo) the memory data path error injection mask low register is shown in figure 9-11 . figure 9-11. memory data path error injection mask low register (data_err_inject_lo) table 9-15 describes the data_err_inject_lo fields. 5?7 clk_adjst clock adjust 000 applied clock (mck/mck_b) is launched aligned with address/command 001 applied clock (mck/mck_b) is launched 1/4 of one sdram cl ock cycle after address/command 010 applied clock (mck/mck_b) is launched 1/2 of one sdram cl ock cycle after address/command 011 applied clock (mck/mck_b) is launched 3/4 of one sdram cl ock cycle after address/command 100 applied clock (mck/mck_b) is launched 1 sdra m clock cycle after address/command. note that this setting causes the applied clock and address/co mmand to be aligned just as a setting of 000 101?111 reserved 8?31 ? reserved 0 31 r eimh w reset 0000_0000_0000_0000 offset 0x0_2e00 table 9-14. data_err_inject_hi field descriptions bits name description 0?31 eimh error injection mask high data path. used to test e cc by forcing errors on the high word of the data path. setting a bit causes the corresponding data path bit to be inverted on memory bus writes. 0 31 r eiml w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x0_2e04 table 9-13. ddr_sdram_clk_cntl field descriptions (continued) bits name description 4 datasheet u .com
ddr memory controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 9-18 freescale semiconductor 9.4.1.11 memory data path error injection mask ecc (ecc_err_inject) the memory data path error injection mask ecc register, shown in figure 9-12 , sets the ecc mask, enables errors to be written to ecc memory, and allo ws the ecc byte to mirror the most significant data byte. figure 9-12. memory data path error inje ction mask ecc regist er (ecc_err_inject) table 9-16 describes the ecc_err_inject fields. table 9-15. data_err_inject_lo field descriptions bits name description 0?31 eiml error injection mask low data path. used to test ecc by forcing errors on the low wo rd of the data path. setting a bit causes the corresponding data path bit to be inverted on memory bus writes. 0 21 22 23 24 31 r0000000000000000000000 emb eien eeim w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x0_2e08 table 9-16. ecc_err_inject field descriptions bits name description 0?21 ? reserved 22 emb ecc mirror byte 0 mirror byte functionality disabled 1 mirror the most significant dat a path byte onto the ecc byte. 23 eien error injection enable 0 error injection disabled 1 error injection enabled. this applies to the data mask bits, the ecc mask bits, and the ecc mirror bit. 24?31 eeim ecc error injection mask. setting a mask bit causes the corresponding ecc bit to be inverted on memory bus writes. 4 datasheet u .com
ddr memory controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 9-19 9.4.1.12 memory data path read capture high (capture_data_hi) the memory data path read capture high register, shown in figure 9-13 , stores the high word of the read data path during error capture. figure 9-13. memory data path read ca pture high register (capture_data_hi) table 9-17 describes the capture_data_hi fields. 9.4.1.13 memory data path read capture low (capture_data_lo) the memory data path read cap ture low register, shown in figure 9-14 , stores the low word of the read data path during error capture. figure 9-14. memory data path read ca pture low register (capture_data_lo) table 9-18 describes the capture_data_lo fields. 0 31 r echd w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x0_2e20 table 9-17. capture_data_hi field descriptions bits name description 0?31 echd error capture high data path. captures the high word of the data path when errors are detected. 0 31 r ecld w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x0_2e24 table 9-18. capture_data_lo field descriptions bits name description 0?31 ecld error capture low data path. captures the lo w word of the data path when errors are detected. 4 datasheet u .com
ddr memory controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 9-20 freescale semiconductor 9.4.1.14 memory data path read capture ecc (capture_ecc) the memory data path read ca pture ecc register, shown in figure 9-15 , stores the ecc s yndrome bits that were on the data bus when an error was detected. figure 9-15. memory data path read capture ecc register (capture_ecc) table 9-19 describes the capture_ecc fields. 9.4.1.15 memory error detect (err_detect) the memory error detect register, shown in figure 9-16 , stores the detection bits for multiple memory errors, single- and multiple-b it ecc errors, and memory select errors. it is a read/write register. a bit can be cleared by writing a high value to the bit. system software can determine the type of memory error by examining the contents of this register. if an er ror is disabled with er r_disable, the corresponding error is never detected or captured in err_detect. table 9-20 describes the err_detect fields. 0 23 24 31 r000000000000000000000000 ece w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x0_2e28 table 9-19. capture_ecc field descriptions bits name description 0?23 ? reserved 24?31 ece error capture ecc. captures the ecc bits on the data path whenever errors are detected. 01 27 28 29 30 31 r mme 000000000000000000000000000 mbe sbe 0 mse w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x0_2e40 figure 9-16. memory error detect register (err_detect) table 9-20. err_detect field descriptions bits name description 0 mme multiple memory errors. this bit is cleared by software writing a 1. 0 multiple memory errors of the same type were not detected. 1 multiple memory errors of the same type were detected. 1?27 ? reserved 4 datasheet u .com
ddr memory controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 9-21 9.4.1.16 memory error disable (err_disable) the memory error disable register, shown in figure 9-17 , allows selective di sabling of the ddr controller?s error detection circuitry. disabled errors are not detected or reported. figure 9-17. memory error disable register (err_disable) table 9-21 describes the err_disable fields. 28 mbe multiple-bit error. this bit is cleared by software writing a 1. 0 a multiple-bit error has not been detected. 1 a multiple-bit error has been detected. 29 sbe single-bit ecc error. this bit is cleared by software writing a 1. 0 the number of single-bit ecc erro rs detected has not crossed th e threshold set in err_sbe[sbet]. 1 the number of single-bit ecc errors detected crossed the threshold set in err_sbe[sbet]. 30 ? reserved 31 mse memory select error. this bit is cleared by software writing a 1. 0 a memory select error has not been detected. 1 a memory select error has been detected. 0 27 28 29 30 31 r0000000000000000000000000000 mbed sbed 0 msed w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x0_2e44 table 9-21. err_disable field descriptions bits name description 0?27 ? reserved 28 mbed multiple-bit ecc error disable 0 multiple-bit ecc errors are detec ted if ddr_sdram_cfg[ecc_en] is set. they are reported if err_int_en[mbee] is set. note that uncorre ctable read errors ca use the assertion of core_fault_in , which causes the core to generate a machine check interrupt, unless it is disabled (by clearing hid1[rfxe]). if rfxe is zero and this error occu rs, mbed must be zero and err_int_en[mbee] and ecc_en must be one to ensure that an interrupt is generated. 1 multiple-bit ecc errors ar e not detected or reported. 29 sbed single-bit ecc error disable 0 single-bit ecc errors are enabled. 1 single-bit ecc errors are disabled. 30 ? reserved 31 msed memory select error disable 0 memory select errors are enabled. 1 memory select errors are disabled. table 9-20. err_detect field descriptions (continued) bits name description 4 datasheet u .com
ddr memory controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 9-22 freescale semiconductor 9.4.1.17 memory error interrupt enable (err_int_en) the memory error interrupt enable register, shown in figure 9-18 , enables ecc interrupts or memory select error interrupts. when an enable d interrupt condition occurs, the internal int signal is asserted to the programmable interrupt controller (pic). figure 9-18. memory error interrupt enable register (err_int_en) table 9-22 describes the err_int_en fields. 9.4.1.18 memory error attributes capture (capture_attributes) the memory error attributes capture register, shown in figure 9-19 , sets attributes for errors including type, size, source, and others. figure 9-19. memory error attributes capture register (capture_attributes) 0 27 28 29 30 31 r0000000000000000000000000000 mbee sbee 0 msee w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x0_2e48 table 9-22. err_int_en field descriptions bits name description 0?27 ? reserved 28 mbee multiple-bit ecc error interrupt enable. note that uncorrectable read errors may cause the assertion of core_fault_in , which causes the core to generate a machine check interrupt, unless it is disabled (by clearing hid1[rfxe]). if rfxe is zero and this error occu rs, err_disable[mbed] must be zero and mbee and ddr_sdram_cfg[ecc_en] must be set to ensure that an interrupt is generated. for more information, see section 6.10.2, ?hardware implementat ion-dependent register 1 (hid1).? 0 multiple-bit ecc errors cannot generate interrupts. 1 multiple-bit ecc errors generate interrupts. 29 sbee single-bit ecc error interrupt enable 0 single-bit ecc errors cannot generate interrupts. 1 single-bit ecc errors generate interrupts. 30 ? reserved 31 msee memory select error interrupt enable 0 memory select errors do not cause interrupts. 1 memory select errors generate interrupts. 0 1 3 4 5 7 8 10 11 15 16 17 18 19 20 30 31 r0 bnum 0 tsiz 000 tsrc 00 ttyp 00000000000 vld w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x0_2e4c 4 datasheet u .com
ddr memory controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 9-23 table 9-23 describes the capture_attributes fields. 9.4.1.19 memory error address capture (capture_address) the memory error address capture register, shown in figure 9-20 , holds the 32 lsbs of a transaction when a ddr ecc error is detected. figure 9-20. memory error address capture register (capture_address) table 9-23. capture_attributes field descriptions bits name description 0 ? reserved 1?3 bnum data beat number. captures th e data beat number for t he detected error. relevant only for ecc errors. 4 ? reserved 5?7 tsiz transaction size for the error. captures the transaction size in double words. 8?10 ? reserved 11?15 tsrc transaction source for the error 00000 pci 00001?00011 reserved 00100 local bus 00101?00111 reserved 01000 configuration space 01001 reserved 01010 boot sequencer 01011 reserved 01100 reserved 01101?01111 reserved 10000 processor (instruction) 10001 processor (data) 10010?10011 reserved 10100 cpm 10101 dma 10110 reserved 10111 sap 11000 tsec1 11001 tsec2 11010 reserved 11011?11111reserved 16?17 ? reserved 18?19 ttyp transaction type for the error 00 reserved 01 write 10 read 11 read-modify-write 20?30 ? reserved 31 vld valid. set as soon as valid information is captured in the error capture registers. 0 31 r caddr w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x0_2e50 4 datasheet u .com
ddr memory controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 9-24 freescale semiconductor table 9-24 describes the capture_address fields. 9.4.1.20 single-bit ecc memory error management (err_sbe) the single-bit ecc memory error management register, shown in figure 9-21 , stores the threshold value for reporting single-bit errors and the number of single-bit erro rs counted since the last error report. when the counter field reaches the threshold, it wraps back to the reset value (0 ). if necessary, software must clear the counter after it has managed the error. figure 9-21. single-bit ecc memory error management register (err_sbe) table 9-25 describes the err_sbe fields. 9.5 functional description the ddr sdram controller controls processor and i/ o interactions with syst em memory. it provides support for jedec-compliant ddr sdra ms (first generation dua l data rate). the me mory system allows a wide range of memory devices to be mapped to any arbitrary chip select. however, registered dimms cannot be mixed with unbuffered dimms. figure 9-22 is a high-level block diagram of the ddr memory controller. requests are received from the internal mastering device and the address is decoded to generate the physical bank, logical bank, row, and column addresses. the transaction is then loaded into the input staging queue with the decoded information. the lower two entries of the input queue are compared with values in the row open table to determine if the address maps to an open page. if the address from eith er entry does not map to an open table 9-24. capture_address field descriptions bits name description 0?31 caddr captured address. captures the 32 lsbs of the transaction address when an error is detected. 0 7 8 1516 2324 31 r00000000 sbet 00000000 sbec w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x0_2e58 table 9-25. err_sbe field descriptions bits name description 0?7 ? reserved 8?15 sbet single-bit error threshold. esta blishes the number of single-bit errors that must be detected before an error condition is reported. 16?23 ? reserved 24?31 sbec single-bit error counter. indicates the number of si ngle-bit errors detected and corrected since the last error report. if single-bit error reporting is enabled, an error is reported and an interrupt is generated when this value equals sbet. sbec is automati cally cleared when the th reshold value is reached. 4 datasheet u .com
ddr memory controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 9-25 page, an activate command is issued for the entry that did not hit an open page, with the lo west entry having priority over the next lowest. commands are alwa ys issued from the lowest input queue entry. figure 9-22. ddr memory controller block diagram the ddr sdram interface supports as many as four physical banks of 64/72 bit-wide memory. a bank size up to 1 gbyte is supported, providing up to a maxi mum of 4 gbytes of ddr main memory. however, 4 gbytes would span the entire 32- bit address space, and some space must be reserved for boot rom, configuration registers, and othe r important addressable locations. programmable parameters allow fo r a variety of memory organiza tions and timings. optional error checking and correcting (ecc) prot ection is provided for the ddr sdram data bus. using ecc, the ddr memory controller detects and corrects all single-bit errors with in the 64-bit data bus, detects all double-bit errors within the 64-bit data bus, and detects all errors within a nibble. the contro ller allows as many as 16 pages to be open simultaneously. the am ount of time (in clock cycles) the pages remain open is programmable with ddr_sdram_interval[bstopre]. read and write accesses to the ddr sdram are burst oriented ; accesses start at a selected location and continue for a programmed number of higher locations (2, 4, or 8) in a programmed sequence (sequential address decode request from master input staging queue physical bank, logical bank, row row open address control ddr sdram memory array: ma[0:14] mbaa[0:1] debug signals: msrcid[0:4] mdval ddr sdram memory control: mcs [0:3] mcas mras mwe mdm[0:8] mcke[0:1] data strobes: mdqs[0:8] data signals: mdq[0:63] mecc[0:7] address from master sdram control row open ta b l e delay chain neg dq ecc error signals dq dq ecc rmw ecm to e r r o r management data from sdram data from master en en clocks: mck [0:5] mck[0:5] dram fifo pos fifo clock control 4 datasheet u .com
ddr memory controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 9-26 freescale semiconductor or interleaved). accesses to closed pages start with the registration of an active command followed by a read or write. (accessing open pages does not require an active command.) the address bits registered coincident with the activate command sp ecifies the logical bank a nd row to be accessed. the address coincident with the read or write command spec ify the logical bank a nd starting column for the burst access. the data interface is source synchr onous, meaning whatever sources the data also provides a clocking signal to synchronize data reception. these bidirect ional data strobes (mdqs[0:8]) are inputs to the controller during reads, and outputs during writes . the ddr sdram specification requires the data strobe signals to be centered within the data tenure during writes and to be offset by the controller to the center of the data tenure during reads. this is implemented in the controller with delay chains for the data strobe signals during reads and a delay chain on the data multiplexer select during writes. when ecc is enabled, one clock cycle is added to the read path to check ecc and correct single-bit errors. ecc generation does not add a cycle to the write path. figure 9-23 shows an example ddr sdram confi guration with four physical banks. figure 9-23. typical dual data ra te sdram intern al organization logical bank 0 logical bank 1 logical bank 2 logical bank 3 mux, mask, read data latch data-out registers data-in registers data bus addr command: dqm ba1,ba0 cke, mck, mck mcs , mras , mcas , mwe control sdram 4 datasheet u .com
ddr memory controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 9-27 figure 9-24 shows some typical signal connections. figure 9-24. typical ddr sdram interface signals figure 9-25 shows an example ddr sdram configuration with four physi cal banks each comprised of nine 8m 8 ddr modules for a total of 256 mbytes of syst em memory. one of the nine modules is used for the memory?s ecc checking function. certain address and control lines may require buffering. analysis of the MPC8555E device?s ac timing spec ifications, desired memo ry operating frequency, capacitive loads, and board routing loads, can a ssist the system designer in deciding signal buffering requirements. the MPC8555E ddr memory controller drives 15 address pins, but in this example the ddr sdram devices use only 12 bits. a[12:0] write enable dq[7:0] dqs 64m 1 byte ck command bus 512 mbit ba[1:0] data data 8 addr mras mcas mwe mcs dm cke mck mck 13 2 ?sub? bank addr strobe 4 datasheet u .com
ddr memory controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 9-28 freescale semiconductor figure 9-25. example 2 56-mbyte ddr sdram configuration with ecc cas cs ras cke clk dm a[0-11] 2mx8 sdram dq[0-7] ba[0-1] cas cs ras cke clk dm a[0-11] 2mx8 sdram dq[0-7] ba[0-1] cas cs ras cke clk dm a[0-11] 2mx8 sdram dq[0-7] ba[0-1] cas cs ras cke clk dm a[0-11] 2mx8 sdram dq[0-7] ba[0-1] cas cs ras cke clk dm a(11-0) 2mx8 sdram dq(7-0) ba(1-0) cas cs ras cke clk dm a(11-0) 2mx8 sdram dq(7-0) ba(1-0) cas cs ras cke clk dm a[0-11] 2mx8 sdram dq[0-7] ba[0-1] cas cs ras we cke ck dm a[11:0] 8m 8 sdram dq[7:0] ba[1:0] 0 mdq[0:7] mdq[8:15] mdq[16:23] mdq[24:31] mdq[32:39] mdq[40:47] mdq[48:55] mdq[56:63] 1 2 3 4 5 6 7 0 mdq[0:7] 1 2 3 4 5 6 7 cas cs ras cke ck dm a[11:0] 8m 8 sdram dq[7:0] ba[1:0] 8 ecc[0:7] mras mcas mwe mcke mck[0:5] mcs [0:3] mba[0:1] ma[0:14] mdq[0:63] mecc[0:7] mdm[0:8] mcs0 mcs1 bank 1 8m 72 (64 mbytes) to all sdram devices in common memory data bus and strobes bank 0 8m 72 (64 mbytes) cas cs ras cke clk dm a[0-11] 2mx8 sdram dq[0-7] ba[0-1] cas cs ras cke clk dm a[0-11] 2mx8 sdram dq[0-7] ba[0-1] cas cs ras cke clk dm a[0-11] 2mx8 sdram dq[0-7] ba[0-1] cas cs ras cke clk dm a[0-11] 2mx8 sdram dq[0-7] ba[0-1] cas cs ras cke clk dm a(11-0) 2mx8 sdram dq(7-0) ba(1-0) cas cs ras cke clk dm a(11-0) 2mx8 sdram dq(7-0) ba(1-0) cas cs ras cke clk dm a[0-11] 2mx8 sdram dq[0-7] ba[0-1] cas cs ras cke ck dm a[11:0] 8m 8 sdram dq[7:0] ba[1:0] mdq[8:15] mdq[16:23] mdq[24:31] mdq[32:39] mdq[40:47] mdq[48:55] mdq[56:31] banks 2?3 mdqs[0] mdqs mdqs[7] mdqs[8] mdqs mdqs[0] mdqs mdqs[7] mdqs[0:8] 4. mck[0:5] may be apportioned among all memory devices. complementary bus is not shown. 3. buffering may be needed if large memory arrays are used. 2. each of the mcs [0:3] signals correspond with a separate physical bank of memory. 1. all signals are connected in common (in parallel) except for mcs [0:3],mck[0:5], mdm[0:8], and the data bus signals. ddr controller cas cs ras cke ck dm a[11:0] 8m 8 sdram dq[7:0] ba[1:0] 8 ecc[0:7] mdqs[8] mdqs mck [0:5] we we we 4 datasheet u .com
ddr memory controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 9-29 section 9.5.13, ?error management,? explains how the ddr memory controller handles errors. 9.5.1 ddr sdram interface operation the ddr memory controller supports many differ ent ddr sdram configur ations. sdrams with different sizes can be used in the same system. fourteen multiplexed address signals a nd two logical bank select signals support device de nsities from 64 mbits to 1 gb it. four chip select (cs ) signals support up to 2 dimms of memory. the ddr sdram physical banks can be built from standard memory modules or directly-attached memory devices. the data path to individual physical banks is 64 bits wide, 72 bits with ecc. the MPC8555E ddr memory controller supports physical bank si zes from 32 mbytes to 1 gbyte. the physical banks can be constructed using 8, or 16 memory device s. the memory technologies supported are 64, 128, 256, and 512 mbits, a nd 1 gbit. nine data qualifier (dqm) signals provide byte selection for memory accesses. note an 8-bit ddr sdram device has a dqm signal and 8 data signals (dq[0:7]). a 16-bit ddr sdram devi ce has 2 dqm signals associated with specific halves of the 16 da ta signals (dq[0:7] and dq[8:15]). when ecc is enabled, all memory accesses are performe d on double-word boundaries (that is, all dqm signals are set simultaneously). however, when ec c is disabled, the memory system uses the dqm signals for byte lane selection. table 9-26 shows the ddr memory controller?s relati onships between data byte lane 0?7, mdm[0:7], mdqs[0:7], and mdq[0:63]. 9.5.1.1 supported ddr sdram organizations although the ddr memory controller multiplexes row and column addr ess bits onto 14 memory address signals and 2 logical bank select signals, individual physic al banks may be implemented with memory devices requiring fe wer than 28 address bits. e ach physical bank may be individually configured to provide from 12 to 14 row address bits, plus 2 logical bank-select bits and from 8?11 colu mn address bits. table 9-27 describes ddr sdram device configurations supported by the ddr memory controller. table 9-26. byte lane to data relationship data byte lane data bus mask data bus strobe data bus 64-bit mode 0 (msb) mdm[0] mdqs[0] mdq[0:7] 1 mdm[1] mdqs[1] mdq[8:15] 2 mdm[2] mdqs[2] mdq[16:23] 3 mdm[3] mdqs[3] mdq[24:31] 4 mdm[4] mdqs[4] mdq[32:39] 5 mdm[5] mdqs[5] mdq[40:47] 6 mdm[6] mdqs[6] mdq[48:55] 7 (lsb) mdm[7] mdqs[7] mdq[56:63] 4 datasheet u .com
ddr memory controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 9-30 freescale semiconductor note ddr sdram is limited to 27 total address bits. if a transaction request is issued to the ddr memory controller and th e address does not lie within any of the programmed address ranges for an enabled chip se lect, a memory select erro r is flagged. errors are described in detail in section 9.5.13, ?error management.? by using a memory-polling algorithm at power-on reset or by querying th e jedec serial presence detect capability of memory modules, sy stem firmware uses the memory- boundary registers to configure the ddr memory controller to map the size of each bank in memory. the memory controller uses its bank map to assert the appropriate mcs n signal for memory accesses accordi ng to the provided bank starting and ending addresses. the memory banks are not required to be mappe d to a contiguous address space. 9.5.2 ddr sdram address multiplexing table 9-28 shows the address bit encodings for each ddr sdram configuration. the address presented at the memory controller signals ma[14:0] use ma[14] as the msb a nd ma[0] as the lsb. also, ma[10] is used as the auto precharge bi t for reads and writes, so the colu mn address can never use ma[10]. table 9-27. supported ddr sdram device configurations sdram device device configuration row column bits 64-bit bank si ze four banks of memory 64 mbits 8 mbits 812 9 64 mbytes 256 mbytes 64 mbits 4 mbits 16 12 8 32 mbytes 128 mbytes 128 mbits 16 mbits 8 12 10 128 mbytes 512 mbytes 128 mbits 8 mbits 16 12 9 64 mbytes 256 mbytes 256 mbits 32 mbits 8 13 10 256 mbytes 1 gbyte 256 mbits 16 mbits 16 13 9 128 mbytes 512 mbytes 512 mbits 64 mbits 8 13 11 512 mbytes 2 gbytes 512 mbits 32 mbits 16 13 10 256 mbytes 1 gbyte 1 gbit 128 mbits 8 14 11 1 gbyte 4 gbytes 1 gbit 64 mbits 16 14 10 512 mbytes 2 gbytes 4 datasheet u .com
ddr memory controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 9-31 9.5.3 jedec standard ddr sdram interface commands all read or write accesses to dd r sdram are performed by the ddr memory controller using jedec standard ddr sdram interface commands. the sd ram device samples comm and and address inputs on rising edges of the memory clock; data is sampled using both the ri sing and falling edges of dqs. data read from the ddr sdram is al so sampled on both edges of dqs. table 9-28. ddr sdram address multiplexing row x col msb address from core master lsb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29?31 14 11 mras 131211109876543210 mba 10 mcas 119876543210 14 10 mras 131211109876543210 mba 10 mcas 9876543210 13 11 mras 1211109876543210 mba 10 mcas 119876543210 13 10 mras 1211109876543210 mba 10 mcas 9876543210 13 9 mras 1211109876543210 mba 10 mcas 876543210 12 10 mras 11109876543210 mba 10 mcas 9876543210 12 9 mras 11109876543210 mba 10 mcas 876543210 12 8 mras 11109876543210 mba 10 mcas 76543210 4 datasheet u .com
ddr memory controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 9-32 freescale semiconductor the following ddr sdram interf ace commands (summarized in table 9-29 ) are provided by the ddr controller. all actions for these commands are desc ribed from the perspectiv e of the sdram device. ? row activate?latches row address a nd initiates memory read of that row. row data is latched in sdram sense amplifiers and must be restored by a precharge command before another row activate occurs. ? precharge?restores data from the sense amplifiers to the appropriate row. also initializes the sense amplifiers in preparation for reading another row in the memory array, (performing another activate command). precharge must occur after read or write, if the row address changes on the next open page mode access. ? read?latches column address and transfers data from the selected sense amplifier to the output buffer as determined by the column address. duri ng each succeeding clock e dge, additional data is driven without additional read commands. the am ount of data transferred is determined by the burst size which defaults to 4. ? write?latches column address and transfers data from the data pins to the selected sense amplifier as determined by the column address. du ring each succeeding cloc k edge, additional data is transferred to the sense amplifiers from the data pins without additi onal write commands. the amount of data transferre d is determined by the burst size, whic h is set to four by the ddr memory controller. ? refresh (similar to mcas before mras )?causes a row to be read in all logical banks (jedec sdram) as determined by the refresh, row addres s counter. this refresh row address counter is internal to the sdram. after being read, the row is automatically rewritten in the memory array. all logical banks must be in a precha rged state before executing a refresh. ? mode register set (for configur ation)?allows setting of ddr sd ram options. these options are: mcas latency, burst type , and burst length. mcas latency may be chosen as provided by the preferred sdram (some sdrams provide mcas latency {1,2,3}, some provide mcas latency {1,2,3,4}, and so on). burst type is always seque ntial. although some sdrams provide burst lengths of 1, 2, 4, 8, and page size, this memory controller supports a burst length of 4. the mode register set command is performed by the ddr memory controller duri ng system initialization. parameters such as m ode register data, mcas latency, burst length, a nd burst type, are set by software in ddr_sdram_mode[sdmode] and tr ansferred to the sdram array by the ddr memory controller after ddr_sdram_cfg[mem_en] is set. ? self refresh (for long periods of standby)?used when the device is in standby for very long periods of time. automatically generates internal refresh cycles to keep the data in all memory banks refreshed. before execution of this command, all logical banks are in a precharged state. table 9-29. sdram command table operation cke prev. cke current mcs mras mcas mwe mba ma10 ma activate h h l l h h logical bank select row row precharge select logical bank h h l l h l logical bank select lx precharge all logical banks hhllhl x h x 4 datasheet u .com
ddr memory controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 9-33 9.5.4 sdram interface timing the ddr memory controller supports four-beat bur sts to sdram. for single-beat reads, the ddr memory controller performs a four-b eat burst read, but ignores the last three beats. single-beat writes are performed by masking the last three beats of the four -beat burst using the data mask mdm[0:8]. if ecc is disabled, writes smaller than double words are pe rformed by appropriately activ ating the data mask. if ecc is enabled, the controller performs a read-modify write. note if a second read or writ e is pending, reads shorter than four beats are not terminated early even if some data is irrelevant. to accommodate available memory technologies across a wide spectr um of operating frequencies, the ddr memory controller allows the se tting of the intervals defined in table 9-30 with granularity of one memory clock cycle, except for caslat, which can be programmed with 1/2 clock granularity. read h h l h l h logical bank select lcolumn read with auto precharge h h l h l h logical bank select hcolumn write h h l h l l logical bank select lcolumn write with auto precharge h h l h l l logical bank select hcolumn mode register seth h llll opcodeopcodeopc ode and mode auto refresh h h l l l h x x x self refresh h l l l l h x x x table 9-30. ddr sdram interface timing intervals timing intervals definition acttoact the number of clock cycles from a bank-activ ate command until another bank-activate command within a physical bank. this interval is listed in the ac specifications of the sdram. actopre the number of clock cycles from an activate comma nd until a precharge command is allowed. this interval is listed in the ac specifications of the sdram. actorw the number of clock cycles from an activate co mmand until a read or write command is allowed. this interval is listed in the ac specifications of the sdram. bstopre the number of clock cycles to maintain a page open after an access. the page open duration counter is reloaded with bstopre each time the page is accessed (including page hits). when the counter expires, the open page is closed with a sdram precharge bank command as soon as possible. table 9-29. sdram command table (continued) operation cke prev. cke current mcs mras mcas mwe mba ma10 ma 4 datasheet u .com
ddr memory controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 9-34 freescale semiconductor the value of the above parameters (i n whole clock cycles) must be set by boot code at system start-up (in the timing_cfg_1 and timing_cfg _2 registers as described in section 9.4.1.3, ?ddr sdram timing configuration 1 (timing_cfg_1),? and section 9.4.1.4, ?ddr sdram timing configuration 2 (timing_cfg_2)? ) and be kept in the ddr memory cont roller configuration register space. the following figures show sdram timing for various t ypes of accesses. system software is responsible (at reset) for optimally configuring sdram timi ng parameters. the program mable timing parameters apply to both read and wr ite timing configuration. the configurati on process must be completed and the ddr sdram initialized before a ny accesses to sdram are attempted. figure 9-26 through figure 9-28 show ddr sdram timing for various types of accesses; see figure 9-26 for a back-to-back burst read operation, figure 9-27 for a single-beat write operation, and figure 9-28 for a burst-write operation. note that al l signal transitions occur on the risi ng edge of the memory bus clock and that single-beat read operati ons are identical to burst-reads. caslat read latency. the number of clock cycles between the registration of a read command by the sdram and the availability of the first piec e of output data. if a read command is registered at clock edge n , and the latency is m clocks, the data is available nominally coincident with clock edge n + m . pretoact the number of clock cycles from a precharge comm and until an activate or a refresh command is allowed. this interval is listed in the ac specifications of the sdram. refint refresh interval. represents the number of memo ry bus clock cycles between refresh cycles. one row is refreshed in each sdram bank during each refresh cycle. the val ue of refint depends on the specific sdrams used and the frequency of the interface. refrec the number of clock cycles from the refresh comm and until an activate command is allowed. this can be calculated by referring to the ac specification of the sdram device. the ac specification indicates a maximum refresh to activate interval in nanoseconds. wr_data_ delay provides different options for the timing between a wr ite command and the write data strobe. this allows write data to be sent later than the nominal time to meet the sdram timi ng requirement between the registration of a write command and the reception of a data strobe a ssociated with the write command. the specification dictates that the dat a strobe may not be received earlier than 75% of a cycle, or later than 125% of a cycle, from the registration of a write co mmand. this parameter is not defined in the sdram specification. it is implementation-specific, defin ed for the ddr memory controller in timing_cfg_2. wrrec the number of clock cycles from the last beat of a write until a precharge command is allowed. this interval, write recovery time, is listed in th e ac specifications of the sdram. wrtord last write pair to read command. controls the num ber of clock cycles from the last write data pair to the subsequent read command to the same bank. table 9-30. ddr sdram interface timing intervals (continued) timing intervals definition 4 datasheet u .com
ddr memory controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 9-35 figure 9-26. ddr sdram burst read timing?acttorw = 3, mcas latency = 2 figure 9-27. ddr sdram single-beat (d ouble-word) write timing?acttorw = 3 acttorw row col sdram clock mcs mcas ma[13:0] mdq[0:63] mwe mras mdqs col d1 d2 d3 d1 d2 d0 d3 d0 01 2345 67 89101112 caslat acttorw row col sdram clock mcs mcas ma[0:13] mdq[0:63] mwe mras mdqs d0 d1 d2 d3 00 mdm[0:7] wrrec a10=0 precharge pretoact row 01 2345 67 89101112 ff ff ff 4 datasheet u .com
ddr memory controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 9-36 freescale semiconductor figure 9-28. ddr sdram burst write timing?acttorw = 4 9.5.4.1 clock distribution ? if running with many devices, zero- delay pll clock buffers, jede c-jesd82 standard, should be used. these buffers were de signed for ddr applications. ? a 72 bit 64 mbytes ddr bank has 9-byte-wide ddr chips, resulting in 18 ddr chips in a two-bank system. in this case, each mck/mck signal pair should driv e exactly three devices. ? pcb traces for ddr clock signals should be short, all on the same layer, and of equal length and loading. ? ddr sdram manufacturers provide detailed information on pcb layout and termination issues. row col sdram clock mcs0 mcas ma[0:13] mdq[0:63] mwe mras mdqs mdm[0:7] 00 col mcs1 row? col? col? d1 d2 d3 d1 d2 d0 d3 d0 d1 d2 d3 d1 d2 d0 d3 d0 01 2345 67 89101112 acttorw 4 datasheet u .com
ddr memory controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 9-37 figure 9-29. ddr sdram clock distribution example 9.5.5 ddr sdram mode-set command timing the ddr memory controller transfers the ex tended mode and base mode register data ddr_sdram_mode[esdmode,sdmode] to the sdram array by issuing two mode-set commands separated by two sdram clock periods. figure 9-30 shows the timing of the mode-set command. the first tran sfer corresponds to the esdmode code ; the second corresponds to sdmode. following commands must wait two sdram cycles. figure 9-30. ddr sdram mode-set command timing mck[1], mck [1] mck[2], mck [2] mck[0], mck [0] dq[0:7], dqs[0], dm[0] dq[8:15], dqs[1], dm[1] dq[16:23], dqs[2], dm[2] dq[24:31], dqs[3], dm[3] dq[32:39], dqs[4], dm[4] dq[40:47], dqs[5], dm[5] dq[48:55], dqs[6], dm[6] dq[56:63], dqs[7], dm[7] ecc[0:7], dqs[8], dm[8] ddr cs [0] a[13:0], ba[1:0], mras , mcas , mwe , cke mck[4], mck [4] mck[5], mck [5] mck[3], mck [3] cs [1] sdram clock mcs mcas ma[0:14] mdq[0:63] mwe mras mdqs mba[0:1] 01 2345 67 89101112 0x1 0x0 code code 4 datasheet u .com
ddr memory controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 9-38 freescale semiconductor 9.5.6 ddr sdram registered dimm mode to reduce loading, registered dimms latch the ddr sdram control signals internally before using them to access the array. setting ddr_ sdram_cfg[rd_en] compensates for this delay on the dimms? control bus by delaying the data and data mask writes (on sdram buses) by an extra sdram clock cycle. enabling registered dimm mode does not affect bus timing for ddr reads. however to compensate for latch delay on the registered dimms? control si gnals, the programmed sd ram read latency value (timing_cfg_1[caslat]) must be one greater than the value needed for non-registered dimms. figure 9-31 shows the registered ddr sdram di mm back-to-back burst write timing. figure 9-31. registered ddr sdram dimm burst write timing 9.5.7 ddr sdram source synchronous clock control the ddr memory controller provides the ability to compensate for system-specific timing conditions resulting from, for instance , trace length variations, or significant memory interface signal loading. the ddr_sdram_clk cntl register may be used to source synchronously delay launching of the mck/mck_b clock signa ls relative to address/command info rmation. when enabled, the sdram clock may be shifted up to one full cycle within the address/command data vali d eye with 1/4 cycle granularity. refer to section 9.4.1.8, ?ddr sdram clock control (ddr_sdram_clk_cntl),? for register and configuration details. 9.5.8 ddr sdram write timing adjustments the ddr memory controller facilitates system desi gn flexibility by providing a write timing adjustment parameter, write data delay, (timing_cfg_ 2[wr_data_delay]) for data and dqs. the ddr sdram specification requires dqs be received no sooner than 75% of an sdram clock period?and no later than 125% of a clock period?from the captu ring clock edge of the command/address at the row col sdram clock mcs mcas ma[13:0] mdq[0:63] mwe mras mdqs mdm[0:7] col d1 d2 d3 d1 d2 d0 d3 d0 01 2345 67 89101112 acttorw 00 4 datasheet u .com
ddr memory controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 9-39 sdram. the wr_data_delay parameter may be used to meet this timing re quirement for a variety of system configurations , ranging from a system with one dimm to a fully populated system with two dimms. timing_cfg_2[wr_data_delay] specifies how much to delay the launching of dqs and data from the first clock edge occurring one sdra m clock cycle after the command is launched. the delay increment step sizes are in 1/4 th sdram clock periods starting wi th the default value of 1/4 th period delay. figure 9-32 shows the use of the wr_data_delay parameter. figure 9-32. write timing adjustments example 9.5.9 ddr sdram refresh the ddr memory controller supports auto-refresh a nd self-refresh. auto refresh is used during normal operation and is cont rolled by the ddr_sdram_inter val[refint] value; self -refresh is used only when the ddr memory controller is set to enter a sl eep power management state or a soft-stop state. the refint value, which represents th e number of memory bus clock cycl es between refresh cycles, must allow for possible outstanding tr ansactions to complete before a refres h request is sent to the memory after the refint value is reached. if a memory transaction is in progress when the refresh interval is reached, the refresh cycle waits for the transaction to complete . in the worst case, the refresh cycle must wait the number of bus clock cycles required by the longest programmed access. to ensure that the latency caused by a memory transaction does not violate the devi ce refresh period, it is recommended that the programmed value of refint be le ss than that required by the sdram. row col sdram clock mcs mcas ma[0:13] mwe mras col 01 2345 67 89101112 acttorw mdq[0:63] mdqs mdm[0:7] d1 d2 d3 d1 d2 d0 d3 d0 00 mdq[0:63] mdqs mdm[0:7] d1 d2 d3 d1 d2 d0 d3 d0 00 1/4 delay 1/2 delay 4 datasheet u .com
ddr memory controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 9-40 freescale semiconductor when a refresh cycle is required, the dd r memory controller does the following: 1. completes all current memory requests 2. closes all open pages with a precharge-a ll command to each ddr sdram bank with an open page (as indicated by the row open table) 3. issues an auto-refresh command to each ddr sdram bank (as identified by its chip select) to refresh one row in each logical bank of the selected physical bank the auto-refresh commands are staggered across the four possible banks to reduce the system?s instantaneous power requirements. three sets of auto refresh commands must be issued on consecutive cycles when the memory is fu lly populated with two dimms. th e initial precharge-all commands are also staggered in three groups fo r convenience. it is important to not e that when entering self-refresh mode, only one refresh command is issued simultaneous ly to all physical banks. cke is negated at this time, so it would not be pos sible to stagger two more refresh comman ds. for this entire refresh sequence, no cycle optimization occurs for the usual case where fewer than four banks are installe d. after the refresh sequence completes, any pending memory request is initiated after an inactive period specified by timing_cfg_1 [refrec]. 9.5.9.1 ddr sdram refresh timing refresh timing for the ddr sdram is contro lled by the programmable timing parameter timing_cfg_1 [refrec], which spec ifies the number of memory bus clock cycles from the refresh command until a logical ba nk activate command is allowed. the dd r memory controller implements bank staggering for refre shes, as shown in figure 9-33 (timing_cfg_1 [refrec] = 10 in this example). figure 9-33. ddr sdram bank-sta ggered auto-refresh timing system software is responsible for optimal configuration of ti ming_cfg_1 [refrec] at reset. configuration must be co mpleted before ddr sdra m accesses are attempted. sdram clock mcs (0,3) mcas mras mcs (1) mcs (2) ma[13:0] row cke refrec 01 2345 67 89101112 13 14 4 datasheet u .com
ddr memory controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 9-41 9.5.9.2 ddr sdram refresh and power-saving modes in full-on mode, the ddr memory controller supplies the normal auto refresh to sdram. in sleep mode, the ddr memory controller can be configured to ta ke advantage of self-refres hing sdrams or to provide no refresh support. self-refresh support is enabled with the sren memory control parameter of the ddr_sdram_cfg register. table 9-31 summarizes the refresh types available in each power-saving mode. note that in the absence of refres h support, system softwa re must preserve ddr sdram data (such as by copying the data to disk) before entering the power-saving mode. all open pages are precharged before self refresh mode is entered. the dynamic power-saving mode uses the cke ddr sdram pin to dynamically power down when there is no system memory activity. th e cke pin is negated when both of the following conditions are met: ? no memory refreshes are scheduled. ? no memory accesses are scheduled. cke is reasserted when a new access or refresh is scheduled or the dynamic pow er mode is disabled. this mode is controlled with ddr_sdram_cfg[dyn_pwr]. dynamic power management mode offers tight cont rol of the memory system?s power consumption by trading power for performance through the use of ddr_sdram_interval[ bstopre]. powering up the ddr sdram when a new memory reference is scheduled causes a one-clock access latency penalty, as shown in figure 9-34 . figure 9-34. ddr sdram power-down mode table 9-31. ddr sdram power-saving modes refresh configuration power saving mode refresh type sren sleep self 1 none 0 mem bus clock nop nop command act cke 4 datasheet u .com
ddr memory controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 9-42 freescale semiconductor 9.5.9.2.1 self-re fresh in sleep mode the entry and exit timing for self -refreshing sdrams is shown in figure 9-35 and figure 9-36 . figure 9-35. ddr sdram self-refresh entry timing figure 9-36. ddr sdram self-refresh exit timing 9.5.10 ddr data beat ordering transfers to and from memory are always perfor med in four-beat bursts (four beats = 32 bytes). for transfer sizes other than four beat s, the data transfers are still opera ted as four-beat bursts. if ecc is enabled for a sub-doubleword write tr ansaction, a full read-modify-write is performed to properly update sdram clock mcs mcas ma[13:0] mdq[0:63] mwe mras mdqs (high impedance) cke 01 2345 67 89101112 200 cycles sdram clock mcs mcas ma[13:0] mdq[0:63] mwe mras mdqs 01 2345 67 202203204205206 cke (high impedance) 4 datasheet u .com
ddr memory controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 9-43 ecc bits. if ecc is disabled then no read-modify-write is required for sub-doubleword writes, and the data masks (mdm[0:8]) are used to pr event writing unwanted data to sd ram. the ddr memory controller also uses data masks to prevent all unintended full double words from writing to sdram. for example, if a write transaction is desired wi th a size of one double word (8 bytes), then the second, third, and fourth beats of data are not written to dram. table 9-32 lists the data beat sequenci ng to and from the ddr sdram an d the data queues for each of the possible transfer sizes with each of the possible starting double-word offsets. all underlined double-word offsets are va lid for the transaction. 9.5.11 page mode and logical bank retention the ddr memory controller supports an open/closed page mode with an allowable open page for each logical bank of dram used. in cl osed page mode, the ddr memory controller uses the sdram auto precharge feature, which allows the controller to in dicate that the page must be automatically closed by the ddr sdram after the read or write access. this is performe d by using ma[10] of the address during the command phase of the access to en able auto precharge. auto precharge is non-persistent in that it is either enabled or disa bled for each individual read or write command. it can however, be enabled or disabled separately for each chip select. when the ddr memory controller operates in open pa ge mode, it retains the currently active sdram page by not issuing a precharge co mmand. the page remains opens until one of the following conditions occurs: ? refresh interval is met ? the user-programmable ddr_sdram_interval[bstopre] value is exceeded. ? there is a logical bank row collision with another transaction that must be issued. page mode can dramatically reduce access latencie s for page hits. depending on the memory system design and timing parameters, using page mode can save two to thr ee clock cycles for subsequent burst accesses that hit in an active page. also, better performance can be obtained by using more banks, table 9-32. memory controller?data beat ordering transfer size starting double-w ord offset double-word sequence 1 to/from dram and queues 1 all underlined double-word offsets are valid for the transaction. 1 double word 0 1 2 3 0 - 1 - 2 - 3 1 - 2 - 3 - 0 2 - 3 - 0 - 1 3 - 0 - 1 - 2 2 double words 0 1 2 0 - 1 - 2 - 3 1 - 2 - 3 - 0 2 - 3 - 0 - 1 3 double words 0 1 0 - 1 - 2 - 3 1 - 2 - 3 - 0 4 double words 0 1 2 3 0 - 1 - 2 - 3 1 - 2 - 3 - 0 2 - 3 - 0 - 1 3 - 0 - 1 - 2 4 datasheet u .com
ddr memory controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 9-44 freescale semiconductor especially in systems which use many different channels. page mode is disabled by clearing ddr_sdram_interval[bstopr e] and cs_n_config[ap_n_en] 9.5.12 error checking and correcting (ecc) the ddr memory controller supports error checking and correcting (ecc) for the data path between the core master and system memory. the memory detect s all double-bit errors, dete cts all multi-bit errors within a nibble, and corrects all singl e-bit errors. other errors may be detected, but are not guaranteed to be corrected or detected. multiple -bit errors are always reported when error reporting is enabled. when a single-bit error occurs, the single-bit error counter register is incremented, and its value compared to the single-bit error trigger register. an error is reported when these valu es are equal. the single-bit error registers can be programme d such that minor memory faults are corrected and ignored, but a catastrophic memory failure generates an interrupt. for writes that are smaller than 64 bits, the ddr memory controller performs a double-word read from system memory of the address for the write (checking fo r errors), and merges the write data with the data read from memory. then, a new ecc code is genera ted for the merged double word. the data and ecc code is then written to memory. if a multi-bit error is detected on th e read, the transaction completes the read-modify-write to keep the ddr memory contro ller from hanging. this read-modify-write operation is performed as an atomic transaction in the ddr controller. the write command is then issued 3?5 memory clocks after the completion of the read, de pending on various system parameters. however, the corrupt data is masked on the writ e, so the original contents in sdram remain uncha nged. the syndrome encodings for the ecc code are shown in table 9-33 and table 9-34 . table 9-33. ddr sdram ecc syndrome encoding data bit syndrome bit data bit syndrome bit 01234567 01234567 0 ?? ? 32 ?? ? 1 ?? ? 33 ?? ? 2 ?? ? 34 ??? 3 ??? 35 ?? ? 4 ?? ? 36 ?? ? 5 ?? ? 37 ??? 6 ??? 38 ????? 7 ??? 39 ?? ?? ? 8 ?? ? 40 ?? ? 9 ?? ? 41 ??? 10 ??? 42 ????? 11 ??? 43 ????? 12 ?? ??? 44 ?? ??? 13 ? ? ??? 45 ? ???? 4 datasheet u .com
ddr memory controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 9-45 14 ? ? ??? 46 ? ? ??? 15 ? ???? 47 ?? ??? 16 ?? ? 48 ??? 17 ?? ? 49 ??? 18 ??? 50 ??? 19 ?? ? 51 ??? 20 ?? ? 52 ??? 21 ??? 53 ??? 22 ??? 54 ??? 23 ?? ?? ? 55 ??? 24 ?? ? 56 ??? 25 ?? ? 57 ??? 26 ??? 58 ??? 27 ?? ? ?? 59 ??? 28 ?? ??? 60 ?? ? 29 ? ? ??? 61 ????? 30 ? ???? 62 ????? 31 ?? ??? 63 ??? ?? table 9-34. ddr sdram ecc sy ndrome encoding (check bits) check bit syndrome bit 01234567 0 ? 1 ? 2 ? 3 ? 4 ? 5 ? 6 ? 7 ? table 9-33. ddr sdram ecc syndrome encoding (continued) data bit syndrome bit data bit syndrome bit 01234567 01234567 4 datasheet u .com
ddr memory controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 9-46 freescale semiconductor 9.5.13 error management the ddr memory controller detects three different ki nds of errors: single-bit, multi-bit, and memory select errors. the following discussion assumes all th e relevant error detection, correction, and reporting functions are enabled as described in section 9.4.1.17, ?memory error inte rrupt enable (err_int_en),? section 9.4.1.16, ?memory error disable (err_disable),? and section 9.4.1.15, ?memory error detect (err_detect).? single-bit errors are counted a nd reported based on the err_sbe value. when a single-bit error is detected, the ddr memory controller does the following: ? corrects the data ? increments the single-bit error counter err_sbe[sbec] ? generates an interrupt if the counter value e rr_sbe[sbec] equals the programmable threshold err_sbe[sbet] ? completes the transaction normally if a multi-bit error is detected for a read, the ddr memory controller logs the error and generates an interrupt (if enabled, as described in section 9.4.1.16, ?memory error disable (err_disable)? ). the final error the ddr memory controller detects is a memory select error, which causes the ddr memory controller to log the error and generate an interrupt (i f enabled, as described in section 9.4.1.15, ?memory error detect (err_detect)? ). this error is detected if the a ddress from the memory request does not fall into any of the enabled, progr ammed chip select address ranges. table 9-35 shows the errors with their descriptions. 9.6 initialization/application information system software must configure the ddr memory cont roller, using a memory po lling algorithm at system start-up, to correctly map the size of each bank in me mory. then, the ddr memory controller uses its bank map to assert the appropriate mcs [0:3] signal for memory accesses acco rding to the provided bank depths. system software must also configure the ddr memo ry controller at system start-up to multiplex appropriately the row and column address bits fo r each bank. refer to row-address configuration in section 9.4.1.2, ?chip select c onfiguration (csn_config).? address multiplexing occurs according to these configuration bits. table 9-35. memory controller errors category error descriptions action detect register notification single-bit ecc threshold the number of ecc errors has reached the threshold specified in the err_sbe. the error is reported through an interrupt if enabled the error control register only logs read versus write, not full type. access error multi-bit ecc error a multi-bit ecc error is detected during a read, or read-modify-write memory operation. memory select error read, or write, address does not fall within the address range of any of the memory banks. 4 datasheet u .com
ddr memory controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 9-47 at system reset, initialization software (bootcode ) must set up the programmable parameters in the memory interface configurat ion registers (micrs). see section 9.4.1, ?regis ter descriptions,? for more detailed descriptions of the configuration registers. these parameters are shown in table 9-36 . 9.6.1 ddr sdram initialization sequence after configuration of all parameters is complete, system software must set ddr_sdram_clk_cntl[ss_en] and ddr_sdram_c fg[mem_en] to enable the memory interface. note that 200 s must elapse after the memory clocks are stable (that is , initialization is complete of all clock related configuration regi sters) before mem_en can be set, so a delay loop in the initialization code may be necessary if software is enabling the memory controller. after mem_en has been set, the ddr memory controller automatically performs the je dec-compliant initialization sequence to initialize memories according to the information in the sdmode and esdmode fields of the ddr_sdram_mode register. the initia lization sequence is as follows: 1. precharge all 2. mode register set for extended mode register 3. mode register set for mode register 4. precharge all 5. two auto refresh commands 6. mode register set for mode regist er with reset dll bit deactivated table 9-36. memory interface configuration register initialization parameters name description parameter section/page cs n _bnds chip select memory bounds sa n ea n 9.4.1.1/9-9 cs n _config chip select configuration cs_ n _en row_bits_cs_ n col_bits_cs_ n 9.4.1.2/9-10 timing_cfg_1 ddr sdram timing configuration pretoact acttopre acttorw caslat refrec wrrec acttoact wrtord wr_data_delay 9.4.1.3/9-11 ddr_sdram_cfg ddr sdram control configuration sren ecc_en rd_en sdram_type dyn_pwr 9.4.1.5/9-13 ddr_sdram_mode ddr sdram mode configuration esdmode sdmode 9.4.1.6/9-14 ddr_sdram_interval ddr sdram interval configuration refint bstopre 9.4.1.7/9-15 4 datasheet u .com
ddr memory controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 9-48 freescale semiconductor note that the ba0 and ba1 bits are automaticall y driven appropriately during the mode register set commands. after this automatic initialization is complete the memory array is ready for access and the memory controller begi ns processing memory trans actions as they arrive. 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 10-1 chapter 10 programmable interrupt controller this chapter describes the programma ble interrupt controller (pic) inte rrupt protocol, various types of interrupt sources controlled by the pic unit, and th e pic registers with so me programming guidelines. 10.1 introduction a block diagram of portions of th e MPC8555E showing the relationship of the various functional blocks and external signals to the pic unit is shown in figure 10-1 . the MPC8555E pic unit prioritizes and manages in terrupts from the l2 cache, the ecm, the ddr controller, the local bus controll er (lbc), the 4-channel dma c ontroller, the pci block, the dual three-speed ethernet controllers (tsecs), the duart, the cpm, the performance monitor, and the i 2 c controller. it also manages the in terrupts generated by the pic itself and by off-chip interrupt sources. the pic unit receives interrupt signals from three sources: external to the integrated device, internal to the integrated device, and intrinsic to the pic itself. the pic selects among all current interrupts the one with the highest priority and forwards it to the internal processor core, or, in pass- through mode, off-chip for external servicing. 10.1.1 overview the pic is compliant with the op enpic architecture. the interrupt controller provides interrupt management, and is responsible for receiving hardware-generated interr upts from different sources (both internal and external), prioritizing them, a nd delivering them to the cpu for servicing. 4 datasheet u .com
programmable interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 10-2 freescale semiconductor figure 10-1. MPC8555E interrupt sources block diagram core_wrs_[0:1] core_hreset core_hreset_req e500 core core_ude core_mcp timer facility watchdog timer global utilities core_halt core_tbint core_ckstop_out ckstp_in ckstp_out hreset hreset_req sreset mcp ude wake up the core and service the interrupt core_reset pic 4 4 message registers timers 4 inter- processor three-speed ethernet controller 1 10/100/1000 mac ddr controller cpm l2 local bus controller three-speed ethernet controller 2 10/100/1000 mac pci controller interrupt i 2 c dma (4-channel) controller e500 coherency module ecm dma dma 4 3 performance monitor controller irq_out int cint irq[0:8] irq9 dma_dreq3 / irq10 dma_dack3 / irq11 dma_ddone3 / int cint watchpoint unit trace buffer 3 sreset sdram cache captive core_fault core_ude ?unconditional debug event core_mcp ?processor machine check int ?normal interrupt cint ?critical interrupt rtc duart security 4 datasheet u .com
programmable interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 10-3 10.1.2 features ? programming model compliant wi th the openpic architecture ? support for 12 external and 21 internal interrupt sources. serial inte rrupts are not supported. ? four interprocessor interrupt channels ? four 32-bit messaging interrupt channels ? four global high resolution timers that can be cl ocked with the ccb (platf orm) clock or the rtc input. ? fully-nested interrupt delivery ? processor initialization control ? programmable resetting of the pic unit through the global configuration register ? 16 programmable interrupt priority levels ? support for connection of external interrupt co ntroller device such as an 8259 programmable interrupt controller ? in 8259 mode, it generates a local (inter nal) interrupt output signal, irq_out . ? recovery from spurious interrupts 10.1.3 interrupts to the processor core the int signal, which causes the external interrupt excep tion, is the main interrupt output from the pic unit to the processor core. interrupts can alternately be c onfigured as critical inte rrupts (in the destination registers); these are reporte d to the core through the cint signal. the book e arch itecture implemented by the e500 core defines a separate critical interrupt type with its own save and restore registers (csrr0 and csrr1) and return instruction (return from critical interrupt, rfci ). in addition to the external and critical interrupts that are generated by the pi c, other MPC8555E conditions (shown in table 10-1 ) cause interrupts to the core (and wake up the core when it is in a low-power state). note that interrupts from port c of the cpm are a special case and do not reach the pic when the device is asleep. therefore, they do not cause the device to wake up. table 10-1. processor interrupts generated outside the core?types and sources core interrupt type signaled by (input to core) sources pic-programmable interrupts external interrupt int generated by the pic, as described in section 10.1.5, ?int errupt sources.? critical interrupt cint generated by the pic, as described in section 10.1.5, ?int errupt sources.? other interrupts generated outside the core machine check core_mcp (MPC8555E causes) ? mcp ? sreset ? assertion of core_mcp by global utilities block 4 datasheet u .com
programmable interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 10-4 freescale semiconductor the global utilities block monito rs two additional interrupt condi tions generated by the e500 core ( core_tbint and core_fault_out signals), as shown in table 10-2 . assertion of either of these signals causes the processor to exit a low-power state. these cases are caused by co re conditions, and after the global utilities logic wakes up the core, they are handled by the core as shown in table 10-2 . 10.1.4 modes of operation mixed or pass-through mode can be chosen by se tting or clearing gcr[ m] as described in section 10.3.1.2, ?global confi guration register (gcr).? 10.1.4.1 mixed mode (gcr[m] = 1) in mixed mode, the external and internal interrupts are delivered using the normal priority and delivery mechanisms detailed in section 10.3.6.1, ?external interrupt vector/priority registers (eivpr0?eivpr11),? through section 10.3.6.4, ?internal interru pt destination registers (iidr0?iidr31).? unconditional debug event core_ude ude . asserting ude generates an unconditional debug exception type debug interrupt and sets a bit in the debug status register, dbsr[ude], as described in section 6.13.2, ?debug status register (dbsr).? reset core_hreset ? hreset assertion (and negation) ? core_hreset_req . internal signal to the device, output from core, input to the platform?caused by writing to the core db cr0[rst]. this condition is additionally qualified with msr[de] and dbcr0[idm] bits. note that assertion of this signal causes a hard reset of the core only. ? core_hreset_req can also be caused by a second timer timeout condition as described in section 6.6.1, ?timer control register (tcr).? ? core_reset . output from pic. see section 10.3.1.4, ?processor initialization register (pir).? table 10-2. e500 core-generated interrupts that cause a wake-up core interrupt type signaled by (output from core) sources fixed interval timer core_tbint the source of both of these interrupts is th e time base facility within the e500 core. the MPC8555E monitors this core output signal and considers it a processor interrupt for the purposes of power management (causes the co re to exit a low-power state). for more information about the interaction between core-generated signals and power management, see chapter 18, ?global utilities.? decrementer machine check core_fault_out occurs when the l1 cache has a parity error on a snoop push operation, which can occur while the core is halted. the MPC8555E monito rs this signal and considers it a processor interrupt for the purposes of power managem ent (causes the core to exit a low-power state). table 10-1. processor interrupts generated outside the core?types and sources (continued) core interrupt type signaled by (input to core) sources 4 datasheet u .com
programmable interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 10-5 10.1.4.2 pass-through mode (gcr[m] = 0) the pic unit provides a mechan ism to support alternate external inte rrupt controllers such as the pc/at compatible 8259 interrupt controller architecture. after a ha rd reset, the pic unit defaults to pass-through mode, in which active-high interrupts from external s ource irq0 are passed directly to the e500 core, as shown in table 10-2 , all other external interrupt signals are ignored. thus, the interrupt signal from an external interrupt cont roller can be connected to irq0 and cause di rect interrupts to th e processor. the pic does not perform a vector fetch fr om an 8259 inte rrupt controller. figure 10-2. pass-through mode example when pass-through mode is enabled, the in ternally-generated interrupts shown in table 10-3 , are not forwarded to the e500 core. instead, the pic passes the raw interrupts from the internal sources to irq_out . note that in pass-through mode, in terrupts generated by the pic itself (global timers, interprocessor, and message register interrupts) cannot be used. if internal or pic- generated interrupts must be reported internally to the processor, pass- through mode must be disabled. 10.1.5 interrupt sources aside from the sources of machin e check, unconditional debug event, and reset interrupts to the core described in table 10-1 , the pic unit can receive 45 separate in terrupts from five di fferent sources as follows: ? 12 external?off-chip signals, irq[0:11] ? 21 internal?on-chip. sources are l2, ecm, ddr, lbc, dma, pci, tsec, duart, cpm, performance monitor, and i 2 c. ? four global timers?from inside the pic ? 4 inter-processor (ipi)?intended for communica tion between different processor cores on the same device. only used for se lf-interrupt in a single-core device such as the MPC8555E. ? 4 message registers?from inside the pic. tri ggered on register write, cl eared on read. used for inter-process communication. irq_out MPC8555E internal interrupts (see table 10-3 ) (not including pic-generated interrupts) pic e500 core irq0 external pc/at-compatible 8259 interrupt controller MPC8555E gcr[m] = 0 irq[1:11] (disabled) 4 datasheet u .com
programmable interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 10-6 freescale semiconductor 10.1.5.1 interrupt routing?mixed mode when the pic receives an internal or external interrupt , its destination register is checked to determine if it should be routed off-chip to the external irq_out signal (if the incoming in terrupt has its xidr[ep] bit set). alternatively, if the incomi ng interrupt has been configured in xi dr[ci] as a critic al interrupt, the pic completes its processing of the interrupt by asserting the cint input to the core, causi ng it to be serviced as a critical interrupt. as a third al ternative (if neither xidr [ci] or xidr[ep] are se t), the interrupt can be serviced as a normal external interr upt by the processor core (through the int signal). in this case, the interrupt is latched by the interrupt pending regi ster (ipr) and the interrupt flow described in section 10.4.1, ?flow of interrupt control,? is followed. 10.1.5.2 internal interrupt sources table 10-3 shows the assignments of the 21 internal inte rrupt sources for the MPC8555E. note that this list does not include the inte rrupts generated by the pic unit. 10.2 external signal description the following sections provide an overview a nd detailed descriptions of the pic signals. table 10-3. internal interrupt assignments internal interrupt number interrupt source internal interrupt number interrupt source 0 l2 cache 15?17 reserved 1 ecm 18 tsec 1 receive/tr ansmit error interrupt 2 ddr dram 19 tsec 2 transmit interrupt 3 lbc 20 tsec 2 receive interrupt 4 dma channel 0 21?23 reserved 5 dma channel 1 24 tsec 2 receive/transmit error interrupt 6 dma channel 2 25 reserved 7 dma channel 3 26 duart 8pci1 27i 2 c controller 9 pci2 28 performance monitor interrupt 10?12 reserved 29 security 13 tsec 1 transmit interrupt 30 cpm (not e that interrupts from port c are not signaled to the pic when the device is asleep) 14 tsec 1 receive interrupt 31 reserved 4 datasheet u .com
programmable interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 10-7 10.2.1 signal overview pic interface signals are described in table 10-4 . there are 12 distinct exte rnal interrupt request input signals (irq[0:11]) and 1 interr upt request output signal (irq_out ). as table 10-4 shows, three irq inputs are multiplexed with dma signals for dma channel 3. 10.2.2 detailed signal descriptions table 10-5 provides detailed descriptions of the external pic signals. table 10-4. pic interface signals signal name i/o description irq[0:8] i external interrupts irq9/dma_dreq3 1 1 irq9?irq11 are multiplexed with dma3 signals. these f unctions are mutually exclus ive; the active function is specified in pmuxcr of the global utilities block as described in section 18.4.1.10, ?alternate function signal multiplex control register (pmuxcr).? i external interrupt/dma channel 3 request irq10/dma_dack3 1 i or o external interrupt (input)/dm a channel 3 acknowledge (output) irq11/dma_ddone3 1 i or o external interrupt (input )/dma channel 3 done (output) irq_out o interrupt request out mcp i processor machine check ude i unconditional debug event table 10-5. interrupt signals?detailed signal descriptions signal i/o description irq[0:11] i interrupt request 0?11. the polarity and sense of each of these signals is programmable. all of these inputs can be driven completely asynchronously. state meaning asserted?when an external interrupt signal is asserted (according to the programmed polarity), the priority is checked by the pic unit, and the interrupt is condit ionally passed to the processor. in pass-through mode, only interrupts detected on irq0 are passed directly to the processor core. negated?there is no incoming in terrupt from that source. timing assertion?all of these inputs can be asserted completely asynchronously. negation?interrupts programmed as level-sensit ive must remain asserted until serviced. 4 datasheet u .com
programmable interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 10-8 freescale semiconductor 10.3 memory map/register definition the pic programmable register ma p occupies 256 kbytes of memory -mapped space. undefined 4-byte address spaces within offset 0x000?0xfff are reserve d. reading undefined portions of the memory map returns all zeros; wr iting has no effect. all pic registers are 32 bits wide and, although located on 128-bi t address boundaries, should only be accessed as 32-bit quantities. the pic address offset map, shown in table 10-6 , is divided into the following three areas: ?0x nn 4_0000?0x nn 4_fff0?global registers ?0x nn 5_0000?0x nn 5_fff0?interrupt source configuration registers ?0x nn 6_0000?0x nn 7_fff0?per-cpu registers irq_out o interrupt request out. active-low, open drain. when th e pic is programmed in pass-through mode, this output reflects the raw interrupts generated by on-chip sources. see section 10.1.4, ?modes of operation,? for more details. state meaning asserted?at least one interrupt is currently being signaled to the external system. negated?indicates no interrupt source currently routed to irq_out . timing because external interrupts are asynchronous with respect to the system clock, both assertion and negation of irq_out occurs asynchronously with respect to the interrupt source. all timing given here is approximate. assertion?internal interrupt source: 2 ccb clock cycles after interrupt occurs. external interrupt source: 4 cycles after interrupt occurs. message interrupts: 2 cycles afte r write to message register. negation?follows interrupt source negation with the following delay: internal interrupt: 2 ccb clock cycles external interrupt: 4 cycles. message interrupts: 2 cycles a fter message register cleared. mcp i machine check processor. assertion causes a machine ch eck interrupt to the e500 core. note that if the e500 core is not configured to process machine ch eck interrupts (msr[me] = 0), assertion of mcp causes a checkstop condition. note that internal sources for the internal core_mcp signal can also cause a machine check interrupt to the processor core, as described in section 18.4.1.13, ?machine check summary register (mcpsumr),? ta bl e 1 0 - 1 and ta bl e 1 0 - 2 . state meaning asserted?the MPC8555E should initiate a machine check interrupt or enter the checkstop state as directed by the msr. negated?machine check handling is not be ing requested by the external system. timing assertion?may occur at any time, asynchronous to any clock. negation?because mcp is edge-triggered, it can be negated one clock after its assertion. ude i unconditional debug event. assertion signal causes an unconditional debug exception to the e500 core. state meaning asserted?indicates that the MPC8555E should initiate an unconditional debug event interrupt to the processor core. negated?indicates that unconditional debug ev ent handling is not being requested by ude . timing assertion?may occur at any time, asynchronous to any clock. negation?should remain asserted until software in the unconditional debug event interrupt handler causes the external device asserting the ude signal to negate it. table 10-5. interrupt signals?detaile d signal descriptions (continued) signal i/o description 4 datasheet u .com
programmable interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 10-9 table 10-6. pic register address map offset register access reset section/page pic register address map?global registers 0x4_0000? 0x4_0030 reserved ? ? ? 0x4_0040 ipidr0?interprocessor interrupt 0 (ipi 0) dispatch register w 0x0000_0000 10.3.7.1/10-37 0x4_0050 ipidr1?ipi 1 dispatch register 0x4_0060 ipidr2?ipi 2 dispatch register 0x4_0070 ipidr3?ipi 3 dispatch register 0x4_0080 ctpr?current task prio rity register r/w 0x0000_000f 10.3.7.2/10-38 0x4_0090 whoami?who am i register r 0x0000_0000 10.3.7.3/10-39 0x4_00a0 iack?interrupt acknowledge register r 0x0000_0000 10.3.7.4/10-39 0x4_00b0 eoi?end of interrupt register w 0x0000_0000 10.3.7.5/10-40 0x4_00c? 0x4_0ff0 reserved ? ? ? 0x4_1000 frr?feature report ing register r 0x0037_0002 10.3.1.1/10-15 0x4_1010 reserved ? ? ? 0x4_1020 gcr?global configuration register r/w 0x0000_0000 10.3.1.2/10-15 0x4_1030 reserved ? ? ? 0x4_1040? 0x4_1070 vendor reserved ? ? ? 0x4_1080 vir?vendor identificat ion register r 0x0000_0000 10.3.1.3/10-16 0x4_1090 pir?processor initialization register r/w 0x0000_0000 10.3.1.4/10-16 0x4_10a0 ipivpr0?ipi 0 vector/priority register r/w 0x8000_0000 10.3.1.5/10-17 0x4_10b0 ipivpr1?ipi 1 vector/priority register 0x4_10c0 ipivpr2?ipi 2 vector/priority register 0x4_10d0 ipivpr3?ipi 3 vector/priority register 0x4_10e0 svr?spurious vector register r/w 0x0000_ffff 10.3.1.6/10-18 0x4_10f0 tfrr?timer frequency reporting register r/w 0x0000_0000 10.3.2.1/10-19 0x4_1100 gtccr0?global timer 0 curr ent count register r 0x0000_0000 10.3.2.2/10-19 0x4_1110 gtbcr0?global timer 0 base count register r/w 0x8000_0000 10.3.2.3/10-20 0x4_1120 gtvpr0?global timer 0 vector/priority register r/w 0x8000_0000 10.3.2.4/10-20 0x4_1130 gtdr0?global timer 0 destination register r/w 0x0000_0001 10.3.2.5/10-21 0x4_1140 gtccr1?global timer 1 curr ent count register r 0x0000_0000 10.3.2.2/10-19 0x4_1150 gtbcr1?global timer 1 base count register r/w 0x8000_0000 10.3.2.3/10-20 0x4_1160 gtvpr1?global timer 1 vector/priority register r/w 0x8000_0000 10.3.2.4/10-20 4 datasheet u .com
programmable interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 10-10 freescale semiconductor 0x4_1170 gtdr1?global timer 1 destination register r/w 0x0000_0001 10.3.2.5/10-21 0x4_1180 gtccr2?global timer 2 curr ent count register r 0x0000_0000 10.3.2.2/10-19 0x4_1190 gtbcr2?global timer 2 base count register r/w 0x8000_0000 10.3.2.3/10-20 0x4_11a0 gtvpr2?global timer 2 vector/priority register r/w 0x8000_0000 10.3.2.4/10-20 0x4_11b0 gtdr2?global timer 2 destination register r/w 0x0000_0001 10.3.2.5/10-21 0x4_11c0 gtccr3?global timer 3 curr ent count register r 0x0000_0000 10.3.2.2/10-19 0x4_11d0 gtbcr3?global timer 3 base count register r/w 0x8000_0000 10.3.2.3/10-20 0x4_11e0 gtvpr3?global timer 3 vector/priority register r/w 0x8000_0000 10.3.2.4/10-20 0x4_11f0 gtdr3?global timer 3 destination register r/w 0x0000_0001 10.3.2.5/10-21 0x4_1200? 0x4_12f0 reserved ? ? ? 0x4_1300 tcr?timer control register r/w 0x0000_0000 10.3.2.6/10-22 0x4_1310 irqsr0?irq_out summary register 0 r 0x0000_0000 10.3.3.1/10-24 0x4_1320 irqsr1?irq_out summary register 1 r 0x0000_0000 10.3.3.2/10-25 0x4_1330 cisr0?critical interrupt summary register 0 r 0x0000_0000 10.3.3.3/10-26 0x4_1340 cisr1?critical interrupt summary register 1 r 0x0000_0000 10.3.3.4/10-26 0x4_1350 pm0mr0?performance monito r 0 mask register 0 r/w 0x00ff_ffff 10.3.4.1/10-27 0x4_1360 pm0mr1?performance monito r 0 mask register 1 r/w 0xffff_ffff 10.3.4.2/10-28 0x4_1370 pm1mr0?performance monito r 1 mask register 0 r/w 0x00ff_ffff 10.3.4.1/10-27 0x4_1380 pm1mr1?performance monito r 1 mask register 1 r/w 0xffff_ffff 10.3.4.2/10-28 0x4_1390 pm2mr0?performance monito r 2 mask register 0 r/w 0x00ff_ffff 10.3.4.1/10-27 0x4_13a0 pm2mr1?performance monito r 2 mask register 1 r/w 0xffff_ffff 10.3.4.2/10-28 0x4_13b0 pm3mr0?performance monito r 3 mask register 0 r/w 0x00ff_ffff 10.3.4.1/10-27 0x4_13c0 pm3mr1?performance monito r 3 mask register 1 r/w 0xffff_ffff 10.3.4.2/10-28 0x4_13d0? 0x4_13f0 reserved ? ? ? 0x4_1400 msgr0?message register 0 r/w 0x0000_0000 10.3.5.1/10-28 0x4_1410 msgr1?message register 1 0x4_1420 msgr2?message register 2 0x4_1430 msgr3?message register 3 0x4_1440? 0x4_14f0 reserved ? ? ? 0x4_1500 mer?message enable register r/w 0x0000_0000 10.3.5.2/10-29 0x4_1510 msr?message status register r/w 0x0000_0000 10.3.5.3/10-29 table 10-6. pic register address map (continued) offset register access reset section/page 4 datasheet u .com
programmable interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 10-11 0x4_1520? 0x4_fff0 reserved ? ? ? pic register address map?interrup t source configuration registers 0x5_0000 eivpr0?external interrupt 0 (irq0) vector/priority register r/w 0x8000_0000 10.3.6.1/10-30 0x5_0010 eidr0?external interrupt 0 (irq 0) destination register r/w 0x0000_0001 10.3.6.2/10-31 0x5_0020 eivpr1?external interrupt 1 (irq1) vector/priority register r/w 0x8000_0000 10.3.6.1/10-30 0x5_0030 eidr1?external interrupt 1 (irq 1) destination register r/w 0x0000_0001 10.3.6.2/10-31 0x5_0040 eivpr2?external interrupt 2 (irq2) vector/priority register r/w 0x8000_0000 10.3.6.1/10-30 0x5_0050 eidr2?external interrupt 2 (irq 2) destination register r/w 0x0000_0001 10.3.6.2/10-31 0x5_0060 eivpr3?external interrupt 3 (irq3) vector/priority register r/w 0x8000_0000 10.3.6.1/10-30 0x5_0070 eidr3?external interrupt 3 (irq 3) destination register r/w 0x0000_0001 10.3.6.2/10-31 0x5_0080 eivpr4?external interrupt 4 (irq4) vector/priority register r/w 0x8000_0000 10.3.6.1/10-30 0x5_0090 eidr4?external interrupt 4 (irq 4) destination register r/w 0x0000_0001 10.3.6.2/10-31 0x5_00a0 eivpr5?external interrupt 5 (irq5) vector/priority register r/w 0x8000_0000 10.3.6.1/10-30 0x5_00b0 eidr5?external interrupt 5 (irq 5) destination register r/w 0x0000_0001 10.3.6.2/10-31 0x5_00c0 eivpr6?external interrupt 6 (irq6) vector/priority register r/w 0x8000_0000 10.3.6.1/10-30 0x5_00d0 eidr6?external interrupt 6 (irq 6) destination register r/w 0x0000_0001 10.3.6.2/10-31 0x5_00e0 eivpr7?external interrupt 7 (irq 7) vector/priority register r/w 0x8000_0000 10.3.6.1/10-30 0x5_00f0 eidr7?external interrupt 7 (irq 7) destination register r/w 0x0000_0001 10.3.6.2/10-31 0x5_0100 eivpr8?external interrupt 8 (irq8) vector/priority register r/w 0x8000_0000 10.3.6.1/10-30 0x5_0110 eidr8?external interrupt 8 (irq 8) destination register r/w 0x0000_0001 10.3.6.2/10-31 0x5_0120 eivpr9?external interrupt 9 (irq9) vector/priority register r/w 0x8000_0000 10.3.6.1/10-30 0x5_0130 eidr9?external interrupt 9 (irq 9) destination register r/w 0x0000_0001 10.3.6.2/10-31 0x5_0140 eivpr10?external interrupt 10 (irq 10) vector/priority register r/w 0x8000_0000 10.3.6.1/10-30 0x5_0150 eidr10?external interrupt 10 (irq 10) destination register r/w 0x0000_0001 10.3.6.2/10-31 0x5_0160 eivpr11?external interrupt 11 (irq 11) vector/priority register r/w 0x8000_0000 10.3.6.1/10-30 0x5_0170 eidr11?external interrupt 11 (irq 11) destination register r/w 0x0000_0001 10.3.6.2/10-31 0x5_0180? 0x5_01f0 reserved ? ? ? 0x5_0200 iivpr0?internal interrupt 0 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_0210 iidr0?internal interrupt 0 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_0220 iivpr1?internal interrupt 1 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_0230 iidr1?internal interrupt 1 destination register r/w 0x0000_0001 10.3.6.4/10-33 table 10-6. pic register address map (continued) offset register access reset section/page 4 datasheet u .com
programmable interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 10-12 freescale semiconductor 0x5_0240 iivpr2?internal interrupt 2 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_0250 iidr2?internal interrupt 2 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_0260 iivpr3?internal interrupt 3 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_0270 iidr3?internal interrupt 3 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_0280 iivpr4?internal interrupt 4 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_0290 iidr4?internal interrupt 4 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_02a0 iivpr5?internal interrupt 5 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_02b0 iidr5?internal interrupt 5 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_02c0 iivpr6?internal interrupt 6 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_02d0 iidr6?internal interrupt 6 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_02e0 iivpr7?internal interrupt 7 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_02f0 iidr7?internal interrupt 7 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_0300 iivpr8?internal interrupt 8 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_0310 iidr8?internal interrupt 8 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_0320 iivpr9?internal interrupt 9 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_0330 iidr9?internal interrupt 9 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_0340 iivpr10?internal interrupt 10 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_0350 iidr10?internal interrupt 10 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_0360 iivpr11?internal interrupt 11 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_0370 iidr11?internal interrupt 11 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_0380 iivpr12?internal interrupt 12 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_0390 iidr12?internal interrupt 12 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_03a0 iivpr13?internal interrupt 13 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_03b0 iidr13?internal interrupt 13 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_03c0 iivpr14?internal interrupt 14 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_03d0 iidr14?internal interrupt 14 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_03e0 iivpr15?internal interrupt 15 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_03f0 iidr15?internal interrupt 15 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_0400 iivpr16?internal interrupt 16 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_0410 iidr16?internal interrupt 16 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_0420 iivpr17?internal interrupt 17 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_0430 iidr17?internal interrupt 17 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_0440 iivpr18?internal interrupt 18 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 table 10-6. pic register address map (continued) offset register access reset section/page 4 datasheet u .com
programmable interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 10-13 0x5_0450 iidr18?internal interrupt 18 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_0460 iivpr19?internal interrupt 19 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_0470 iidr19?internal interrupt 19 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_0480 iivpr20?internal interrupt 20 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_0490 iidr20?internal interrupt 20 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_04a0 iivpr21?internal interrupt 21 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_04b0 iidr21?internal interrupt 21 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_04c0 iivpr22?internal interrupt 22 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_04d0 iidr22?internal interrupt 22 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_04e0 iivpr23?internal interrupt 23 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_04f0 iidr23?internal interrupt 23 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_0500 iivpr24?internal interrupt 24 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_0510 iidr24?internal interrupt 24 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_0520 iivpr25?internal interrupt 25 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_0530 iidr25?internal interrupt 25 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_0540 iivpr26?internal interrupt 26 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_0550 iidr126?internal interrupt 26 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_0560 iivpr27?internal interrupt 27 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_0570 iidr27?internal interrupt 27 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_0580 iivpr28?internal interrupt 28 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_0590 iidr28?internal interrupt 28 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_05a0 iivpr29?internal interrupt 29 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_05b0 iidr29?internal interrupt 29 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_05c0 iivpr30?internal interrupt 30 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_05d0 iidr30?internal interrupt 30 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_05e0 iivpr31?internal interrupt 31 vector/priority register r/w 0x8080_0000 10.3.6.3/10-32 0x5_05f0 iidr31?internal interrupt 31 destination register r/w 0x0000_0001 10.3.6.4/10-33 0x5_0600? 0x5_15f0 reserved ? ? ? 0x5_1600 mivpr0?messaging interrupt 0 (msg 0) vector/priority register r/w 0x8000_0000 10.3.6.5/10-34 0x5_1610 midr0?messaging interrupt 0 (msg 0) destination register r/w 0x0000_0001 10.3.6.6/10-35 0x5_1620 mivpr1?messaging interrupt 1 (msg 1) vector/priority register r/w 0x8000_0000 10.3.6.5/10-34 0x5_1630 midr1?messaging interrupt 1 (msg 1) destination register r/w 0x0000_0001 10.3.6.6/10-35 table 10-6. pic register address map (continued) offset register access reset section/page 4 datasheet u .com
programmable interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 10-14 freescale semiconductor 10.3.1 global registers most registers have one address. some registers ar e replicated for each processor in a multiprocessor device. in this case , each processor accesses its separate registers using the same address, the address decoding being sensitive to the processor id. a copy of the per-cpu registers is available to each processor core at the same physical address, that is , the private access address space. the private access address space acts like an alias to a processor?s own copy of the per-cpu registers. as shown in figure 10-31 , the id of the processor initiating the read/w rite transaction is used to determine which processor?s per-cpu registers to access. for more information on per-cpu registers, see section 10.3.7, ?per-cpu registers . ? note register fields designated as write-1- to-clear are cleared only by writing ones to them. writing zeros to them has no effect. 0x5_1640 mivpr2?messaging interrupt 2 (msg 2) vector/priority register r/w 0x8000_0000 10.3.6.5/10-34 0x5_1650 midr2?messaging interrupt 2 (msg 2) destination register r/w 0x0000_0001 10.3.6.6/10-35 0x5_1660 mivpr3?messaging interrupt 3 (msg 3) vector/priority register r/w 0x8000_0000 10.3.6.5/10-34 0x5_1670 midr3?messaging interrupt 3 (msg 3) destination register r/w 0x0000_0001 10.3.6.6/10-35 0x5_1680? 0x5_fff0 reserved ? ? ? pic register address map?per-cpu registers 0x6_0000? 0x6_0030 reserved ? ? ? 0x6_0040 ipidr0?p0 ipi 0 dispatch register w all zeros 10.3.7.1/10-37 0x6_0050 ipidr1?p0 ipi 1 dispatch register 0x6_0060 ipidr2?p0 ipi 2 dispatch register 0x6_0070 ipidr3?p0 ipi 3 dispatch register 0x6_0080 ctpr0?p0 current task pr iority register r/w 0x0000_000f 10.3.7.2/10-38 0x6_0090 whoami0?p0 who am i register r all zeros 10.3.7.3/10-39 0x6_00a0 iack0?p0 interrupt acknowledge register r all zeros 10.3.7.4/10-39 0x6_00b0 eoi0?p0 end of interrupt register w all zeros 10.3.7.5/10-40 table 10-6. pic register address map (continued) offset register access reset section/page 4 datasheet u .com
programmable interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 10-15 10.3.1.1 feature repo rting register (frr) the feature reporting regi ster (frr) shown in figure 10-3 provides information about interrupt and processor configurations. it also informs the pr ogramming environment of the controller version. figure 10-3. feature reporting register (frr) table 10-7 describes the frr fields. 10.3.1.2 global configuration register (gcr) the global configuration re gister (gcr) shown in figure 10-4 controls the pic?s operating mode, and allows software to reset the pic. figure 10-4. global config uration register (gcr) 0 4 5 1516 1819 2324 31 r00000 nirq 000 ncpu vid w reset 0000_0000_0011_0111_0000_0000_0000_0010 offset 0x4_1000 table 10-7. frr field descriptions bits name description 0?4 ? reserved. 5?15 nirq number of interrupts. contains the binary value of 1 minus the maximum number of interrupt sources supported. the value is 55 (0x37) because this device s upports 56 interrupts: 12 external sources, 32 internal sources (only 21 used), four timer sources, four ipi so urces and four messaging sources. a zero in this field corresponds to one source. 16?18 ? reserved. 19?23 ncpu number of cpus. the number of the highest physical cpu supported. the MPC8555E implements one cpu (the processor core), referenced as p0. 24?31 vid version id. version id for this interrupt controller. reports the openpic specification revision level supported by this implementation. a value of two corresponds to revision 1.2, which is the revision level currently supported. 0123 31 r rst 0 m 00000000000000000000000000000 w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x4_1020 4 datasheet u .com
programmable interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 10-16 freescale semiconductor table 10-8 describes the gcr fields. 10.3.1.3 vendor identifi cation register (vir) the vendor identification register (vir) shown in figure 10-5 has specific read-only information about the vendor and the device revision. figure 10-5. vendor identi fication register (vir) table 10-9 describes the vir fields. 10.3.1.4 processor initiali zation register (pir) the processor initialization register in the pic provides a mechanism for software to reset the processor. the core_reset signal to the processor is held active until a ze ro is written to the processor initialization register field. thus, pir should only be written by an external host and the external host should wait at least 100 sec to clear this field after writing it. the proc essor should not attempt to write to pir because table 10-8. gcr field descriptions bits name description 0 rst reset. setting this field forces the pic to be reset. cleared automatically when the reset sequence is complete. see section 10.4.7, ?reset of the pic,? for more information on resetting the pic. 1 ? reserved 2m mode. pic operating mode. 0 pass-through mode. on-chip pic is disabled and interr upts detected on irq0 are passed directly to the processor core. see section 10.1.4, ?modes of operation,? for more details. 1 mixed mode. interrupts are handled by the normal priority and delivery mechanisms of the pic. see section 10.1.4, ?modes of operation,? for more details. 3?31 ? reserved 0 7 8 1516 2324 31 r00000000 step device id vendor id w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x4_1080 table 10-9. vir field descriptions bits name description 0?7 ? reserved 8?15 step stepping. indicates the silicon revision for th is device. has no meaning when the vendor id value is zero. 16?23 device id device identification. vendor-specified identi fier for this device. has no meaning when the vendor id value is zero. 24?31 vendor id vendor identification. specifies the manufact urer of this part. a value of zero implies a generic pic-compliant device. 4 datasheet u .com
programmable interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 10-17 writing to it resets the core, and the core will not be able to clear the reset field, and so it would remain in reset indefinitely. note that although the architectur e was designed to support multiple processing cores, only fields corresponding to processors on the de vice are implemented, as shown in figure 10-6 . in a uniprocessor system, such as th e MPC8555E, only pir[p0] is implemented. figure 10-6. processor initialization register (pir) table 10-10 describes the pir fields. 10.3.1.5 ipi vector/priority registers (ipivpr n ) the interprocessor interrupt (ipi) vect or/priority registers contain the inte rrupt vector and priority fields for the four interprocessor inte rrupt channels as shown in figure 10-7 . there is one ipi vector/priority register per channel. the vector and priori ty values should not be changed while ipivpr n [a] is set. figure 10-7. ipi vector/priority register (ipivpr n ) 0 30 31 r000000000000000o000000000000000 p0 w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x4_1090 table 10-10. pir field descriptions bits name description 0?30 ? reserved 31 p0 processor 0 core reset. setting this bit causes the pic unit to assert the core_reset signal to processor 0 (the e500 core). 0 1 2 11 12 15 16 31 rm s k a0000000000 priority vector w reset 1000_0000_0000_0000_0000_0000_0000_0000 offset 0x4_10a0, 0x4_10b0, 0x4_10c0, 0x4_10d0 4 datasheet u .com
programmable interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 10-18 freescale semiconductor table 10-11 describes the ipivpr n fields. 10.3.1.6 spurious vector register (svr) the spurious vector register (svr) shown in figure 10-8 contains the 16-bit vector returned to the processor when the iack register is read for a spurious interrupt. figure 10-8. spurious vector register (svr) table 10-12 describes the svr fields. 10.3.2 global timer registers this section describes the global time r registers. note that each of th e four timers have four individual configuration registers (gtccr n , gtbcr n , gtvpr n , gtdr n ), but they are only shown once in this section. table 10-11. ipivpr n field descriptions bits name description 0 msk mask. mask interrupts from this source. always set following reset. 0 an interrupt request is generated if the corresponding ipr bit is set. 1 further interrupts from this source are disabled. 1 a activity. indicates an interrupt has been reported or is in-service. note that this field is read only. the vector and priority values should not be changed while ipivpr n [a] is set. 0 no current interrupt activity associated with this source. 1 the interrupt bit for this source in the ipr or isr is set. 2?11 ? reserved 12?15 priority priority. specifies the interrupt priority. the lowest priority is 0 and the highest priority is 15. a priority le vel of 0 disables interrupt reporting from this source. 16?31 vector vector. the vector value in this field is return ed when the interrupt acknowledge (iack) register is read and this interrupt resides in the interrupt request register (irr) shown in figure 10-37 . 015 31 r0000000000000000 vector w reset 0000_0000_0000_0000_1111_1111_1111_1111 offset 0x4_10e0 table 10-12. svr field descriptions bits name description 0?15 ? reserved 16?31 vector spurious interrupt vector. value returned when the interrupt acknowledge (iack) register is read during a spurious vector fetch. see section 10.4.4, ?spurious vector generation,? for more information about the events and conditions that may cause a spurious vector fetch. 4 datasheet u .com
programmable interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 10-19 10.3.2.1 timer frequency reporting register (tfrr) the timer frequency reporting register (tfrr), shown in figure 10-9 , is written by software to report the clocking frequency of the pic timers. note that although tfrr is read/wri te, the value of th is register is ignored by the pic unit. figure 10-9. timer frequency reporting register (tfrr) table 10-13 describes the tfrr register. 10.3.2.2 global timer current count registers (gtccr n ) the global timer current count registers (gtccrs), shown in figure 10-10 , contain the current count for each of the four pic timers. figure 10-10. global timer current count registers (gtccr n ) 0 31 r freq w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x4_10f0 table 10-13. tfrr field descriptions bits name description 0?31 freq timer frequency (in ticks/second (hz)). used to co mmunicate the frequency of the global timers? clock source, (identically the core complex bus (ccb) clock, to user software. see section 4.4.4, ?clocking,? for more details. tfrr is set only by software for later use by other applications and its value in no way affects the operating frequency of the global timers. the timers operate at a ratio of this clock frequency set by tcr[clkr]. see section 10.3.2.6, ?timer control register (tcr).? 01 31 r tog count w reset 0000_0000_0000_0000 offset 0x4_1100, 0x4_1140, 0x4_1180, 0x4_11c0 4 datasheet u .com
programmable interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 10-20 freescale semiconductor table 10-14 describes the gtccr n fields. 10.3.2.3 global ti mer base count registers (gtbcr n ) the global timer base count registers (gtbcrs) contai n the base counts for each of the four pic timers as shown in figure 10-11 . this value is reloaded into the corresponding gtccr n when the current count reaches zero. note that when zero is writ ten to the base count field, (and gtccr n [ci] = 0), the timer generates an interrupt on every timer cycle. figure 10-11. global timer base count register (gtbcr n ) table 10-15 describes the gtbcr n fields. 10.3.2.4 global timer vector/priority registers (gtvpr n ) the global timer vector/priority regist ers (gtvprs) contain the interrupt vector and the interrupt priority as shown in figure 10-12 . they also contain the mask and activity fields. table 10-14. gtccr n field descriptions bits name description 0 tog toggle. toggles when the current count decrements to zero. cleared when gtbcr n [ci] goes from 1 to 0. 1?31 count current count. decremented while gtbcr n [ci] is zero. when the timer count reaches zero, an interrupt is generated (provided it is not masked), the toggle bit is inverted, and the count is reloaded. for non-cascaded timers, the reload value is the contents of the co rresponding base count register. cascaded timers are reloaded with either all ones, or t he contents of the base count re gister, depending on the value of tcr[rovr]. see section 10.3.2.6, ?timer control register (tcr),? for more details. 01 31 r ci base cnt w reset 1000_0000_0000_0000_0000_0000_0000_0000 offset 0x4_1110, 0x4_1150, 0x4_1190, 0x4_11d0 table 10-15. gtbcr n field descriptions bits name description 0 ci count inhibit. always set following reset 0 counting enabled 1 counting inhibited 1?31 base cnt base count. when ci transitions from 1 to 0, this value is copied into the correspon ding current count register and the toggle bit is cleared. if ci is alread y cleared (counting is in progress), the base count is copied to the current count register at the next zero crossing of the current count. 4 datasheet u .com
programmable interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 10-21 figure 10-12. global timer vect or/priority register (gtvpr n ) table 10-16 describes the gtvpr n fields. 10.3.2.5 global timer dest ination registers (gtdr n ) the global timer destination register controls the destination processor fo r this timer?s interrupt, as shown in figure 10-13 . figure 10-13. global timer de stination register (gtdr n ) 012 1112 1516 31 r msk a0000000000 priority vector w reset 1000_0000_0000_0000_0000_0000_0000_0000 offset 0x4_1120, 0x4_1160, 0x4_11a0, 0x4_11e0 table 10-16. gtvpr n field descriptions bits name description 0 msk mask. inhibits interrupts from this source 0 interrupt requests are generated when the corresponding ipr bit is set. 1 further interrupts from this source are disabled. 1 a activity. this field is read-only. 0 no current interrupt activity associated with this source. 1 an interrupt has been requested by the correspondi ng source or is currently being serviced. the interrupt bit for this source is set in the ipr or isr. the vector and priority values should not be changed while the a bit is set. 2?11 ? reserved 12?15 priority priority. specifies the interrupt priority. the lowest priority is 0 and the highest priority is 15. a priority le vel of 0 disables interrupts from this source. 16?31 vector vector. the vector value in this field is return ed when the interrupt acknowledge (iack) register is read and this interrupt resides in the interrupt request register shown in figure 10-37 . 0 30 31 r0000000000000000000000000000000p0 w reset 0000_0000_0000_0000_0000_0000_0000_0001 offset 0x4_1130, 0x4_1170, 0x4_11b0, 0x4_11f0 4 datasheet u .com
programmable interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 10-22 freescale semiconductor table 10-17 describes the gtdr n fields. 10.3.2.6 timer contro l register (tcr) the timer control register (tcr) shown in figure 10-15 provides various configur ation options such as count frequency and roll-over behavior. there are two choices for the clock s ource for the timers: a selectable frequency ratio from the ccb clock, or the rtc signal. the tcr also provi des the ability to create timers la rger than the default 31-bit global timers. timer cascade fields allow c onfiguration of up to tw o 63-bit timers, one 95-b it timer or one 127-bit timer. with one exception mentioned below, the value reloaded into a timer is determined by its roll-over control field tcr[rovr]. setting a timer?s ro ll-over field causes its current count register to roll over to all ones when the count reaches zero. this is equivalent to reloading the count register with 0xffff_ffff instead of its base count value. clearing a timer?s associated rovr bit ensures the timer al ways reloads with its base count value. when timers are cascaded the last (most significant) counter in the cas cade also affects their roll-over behavior. cascaded timers always reload their base count wh en the most significant counter has decremented to zero, regardless of the settings in tcr[rovr]. for example, timers 0, 1, and 2 can be cascaded to generate one interrupt every hour. as shown in table 10-18 , given a ccb clock of 333 mhz, letting the time r clock frequency default to 1/8 the system clock, (tcr[clkr] = 0 sets a clock ratio of 8), provides a basic input of 41.625 mhz to timer 0. setting timer 0 to count 41,625,000 (0x27b_25a8) ti mer clock cycles will generate one output per second. setting both timers 1 and 2 to 59, and cascadi ng all three timers, gene rates one interrupt ev ery hour from timer 2. figure 10-14. example calculation for cascaded timers table 10-17. gtdr n field descriptions bits name description 0?30 ? reserved 31 p0 processor 0. indicates that processor 0 handles any in terrupt. this bit is meaningful only in a multi-core device. because the MPC8555E is a single-core device, internally serviced interrupts are always directed to processor 0. permanently set and read only. 1 interrupt directed to processor 0. table 10-18. parameters for hourly interrupt timer cascade example system clock clock ratio timer clock tim er 0 count timer 1 count timer 2 count 333 mhz 1 / 8 41.625 mhz 41.625 10 6 (0x027b_25a8) 59 1 (0x0000_0036) 1 counting down from 59 through 0 requires 60 ticks. 59 (0x0000_0036) (41.625 106 ticks/sec) (60 sec/min) (60 min/hr) = total ticks/hr generating 1 interrupt/hr 4 datasheet u .com
programmable interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 10-23 figure 10-15. timer control register (tcr) table 10-19 describes the tcr fields. 0 4 5 7 8 15 16 21222324 2829 31 r00000 rovr 0000000 rtm 000000 clkr 00000 casc w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x4_1300 table 10-19. tcr field descriptions bits name description 0?4 ? reserved 5?7 rovr roll-over control for cascaded timers only. specifie s behavior when count reaches zero by identifying the source of the reload value. cascaded timers are always reloaded with their base count value when the more significant timer in the cascade (the upstream timer) is zero. bits 5?7 correspond to timers 2?0. note that global timer 3 always reloads with its base count register. 0 timer does not roll over. when the count reaches zero, current count register is reloaded with the base count register value. 1 timer rolls over at zero to all ones. (when the count reaches zero, current count register is reloaded with 0xffff_ffff.) 000 all timers reload with base count. 001 timers 1 and 2 reload with base count, timer 0 rolls over (reloads with 0xffff_ffff) 010 timers 0 and 2 reload with base count, timer 1 rolls over (reloads with 0xffff_ffff) 011 timer 2 reloads with base count, timers 0 and 1 roll over (reload with 0xffff_ffff) 100 timers 0 and 1 reload with base count, timer 2 rolls over (reloads with 0xffff_ffff) 101 timer 1 reloads with base count, timers 0 and 2 roll over (reload with 0xffff_ffff) 110 timer 0 reloads with base count, timers 1 and 2 roll over (reload with 0xffff_ffff) 111 timers 0, 1, and 2 roll over (reload with 0xffff_ffff). 8?14 ? reserved 15 rtm real time mode. specifies the clock source for the pic timers 0 timer clock frequency is a ratio of the frequency of the platform (ccb) clock as determined by the clkr field. this is the default value. 1 the rtc signal is used to clock the pic timers. if this bit is set, the cl kr field has no meaning. 16?21 ? reserved 22?23 clkr clock ratio. specifies the ratio of the timer frequen cy to the platform (ccb) clock. the following clock ratios are supported: 00 default. divide by 8 01 divide by 16 10 divide by 32 11 divide by 64 4 datasheet u .com
programmable interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 10-24 freescale semiconductor 10.3.3 summary registers the summary registers can be read to determine which interrupt sour ce was directed to the irq_out output pin or caused a critical interrupt. the irq_out summary registers shown in figure 10-16 and figure 10-17 contain one bit for each interrupt source. the corresponding bi t is set if the interrupt is act ive and is directed to irq_out (that is, if the corresponding x idr[ep] is set). the critical interrupt summary registers shown in figure 10-18 and figure 10-19 contain one bit for each interrupt source. the corresponding bit is set if the inte rrupt is active and is di rected to the processor?s critical interrupt signal cint (if the ci field in its corresponding de stination register is set). the summary register bits are clear ed when the corresponding interrupt that caused a bit to be sett is negated. note that only level sensitive interrupts can be directed to irq_out . 10.3.3.1 irq_out summary register 0 (irqsr0) figure 10-16 shows the irqsr0 fields. figure 10-16. irq_out summary register 0 (irqsr0) 24?28 ? reserved 29?31 casc cascade timers. specifies the output of particular global timers as input to others 000 default. timers not cascaded 001 cascade timers 0 and 1 010 cascade timers 1 and 2 011 cascade timers 0, 1, and 2 100 cascade timers 2 and 3 101 cascade timers 0 and 1; timers 2 and 3 110 cascade timers 1, 2, and 3 111 cascade timers 0, 1, 2, and 3 0 151617181920 31 r0000000000000000msg0msg1msg2msg3 ext n w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x4_1310 table 10-19. tcr field descriptions (continued) bits name description 4 datasheet u .com
programmable interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 10-25 table 10-20 describes the irqsr0 fields. 10.3.3.2 irq_out summary register 1 (irqsr1) figure 10-17 shows the irqsr1 fields. figure 10-17. irq_out summary register 1 (irqsr1) table 10-21 describes the irqsr1 fields. table 10-20. irqsr0 field descriptions bits name description 0?15 ? reserved 16 msg0 message interrupt 0 status 0 interrupt is not active or not directed to irq_out 1 interrupt is active and is directed to the irq_out pin (that is, if the corresponding x idr[ep] is set 17 msg1 message interrupt 1 status 0 interrupt is not active or not directed to irq_out 1 interrupt is active and is directed to the irq_out pin (that is, if the corresponding x idr[ep] is set 18 msg2 message interrupt 2 status 0 interrupt is not active or not directed to irq_out 1 interrupt is active and is directed to irq_out (that is, if the ep corresponding x idr[ep] is set 19 msg3 message interrupt 3 status 0 interrupt is not active or not directed to irq_out 1 interrupt is active and is directed to irq_out (that is, if corresponding x idr[ep] is set 20?31 ext n external interrupts 0?11. each bit corresponds to a different interrupt according to the following: bit interrupt 20irq0 21irq1 31irq11 0 the corresponding interrupt is not active or not directed to irq_out . 1 the corresponding interrupt is active and directed to irq_out (if the corresponding x idr[ep] is set. 0 31 rint n w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x4_1320 table 10-21. irqsr1 field descriptions bits name description 0?31 int n internal interrupts 0?31 status. bit 0 represents int0. bit 31 represents int31. 0 the corresponding interrupt is not active or not directed to irq_out . 1 the corresponding interrupt is active and is directed to irq_out (that is, if the corresponding x idr[ep] is set). 4 datasheet u .com
programmable interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 10-26 freescale semiconductor 10.3.3.3 critical interrupt su mmary register 0 (cisr0) figure 10-18 shows the cisr0 fields. figure 10-18. critical interrupt summary register 0 (cisr0) table 10-22 describes the cisr0 fields. 10.3.3.4 critical interrupt su mmary register 1 (cisr1) figure 10-19 shows the cisr1 fields. figure 10-19. critical interrupt summary register 1 (cisr1) table 10-23 describes cisr1 register. 0 1516 1920 31 r0000000000000000 msg n ext n w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x4_1330 table 10-22. cisr0 field descriptions bits name description 0?15 ? reserved 16?19 msg n message interrupts 0?3. bit 16 represents msg0; bit 19 represents msg3. 0 the corresponding interrupt is not active or not directed to cint . 1 the corresponding interrupt is active and is directed to the cint (if the corresponding xidr[ci] is set). 20?31 ext n external interrupts 0?11. bit 20 re presents irq0. bit 31 represents irq11. 0 the corresponding interrupt is not active or not directed to cint . 1 the corresponding interrupt is active and is directed to the cint (if the corresponding xidr[ci] is set). 0 31 rint n w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x4_1340 table 10-23. cisr1 field descriptions bits name description 0?31 int n internal interrupts 0?31. bit 0 represents int0. bit 31 represents int31. 0 the corresponding interrupt is not active or not directed to cint . 1 the corresponding interrupt is active and is directed to the cint (if the corresponding xidr[ci] is set). 4 datasheet u .com
programmable interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 10-27 10.3.4 performance monitor mask registers (pmmrs) the eight performance monitor ma sk registers consist of four pairs of 32-bit registers, pm n mr0 and pm n mr1. each pair can be configured to select one interrupt source (ipi, timer, me ssage, or external) to generate a performance monitor even t, the performance monitor can be c onfigured to track this event in the performance monitor loca l control registers. see section 19.3.2.2, ?performance monitor local control registers (pmlcan, pmlcbn).? 10.3.4.1 performance monitor mask register (lower) (pm n mr0) figure 10-20 shows the pm n mr0 registers. each regist er is paired with a pm n mr1 register. because each unreserved bit in th e 64-bit pair (pm n mr0/1) specifies a different interr upt, only one bit in each pair can be unmasked at a time. unmasking more than one bi t per pair is considered a programming error and results in unpredictable behavior. figure 10-20. performance monitor mask registers (pm n mr0) table 10-24 describes the pm n mr0 fields. 0 7 8 1112 1516 1920 31 r00000000 ipi timer msg ext w reset 0000_0000_1111_1111_1111_1111_1111_1111 offset pm0mr0 0x4_1350, pm1mr0 0x4_1 370, pm2mr0 0x4_1390, pm3mr0 0x4_13b0 table 10-24. pm n mr0 field descriptions bits name description 0?7 ? reserved 8?11 ipi ipi interrupts 0?3 0 the corresponding interrupt source generates a performance monitor event when the interrupt occurs. 1 the corresponding interrupt does not generate a performance monitor event. 12?15 timer timer interrupts 0?3 0 the corresponding interrupt source generates a performance monitor event when the interrupt occurs. 1 the corresponding interrupt does not generate a performance monitor event. 16?19 msg message interrupts 0?3 0 the corresponding interrupt source generates a performance monitor event when the interrupt occurs. 1 the corresponding interrupt does not generate a performance monitor event. 20?31 ext external interrupts irq[0:11] 0 the corresponding interrupt source generates a performance monitor event when the interrupt occurs. 1 the corresponding interrupt does not generate a performance monitor event. 4 datasheet u .com
programmable interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 10-28 freescale semiconductor 10.3.4.2 performance monitor mask registers (upper) (pm n mr1) figure 10-21 shows the pm0mr1, pm1mr1, pm2mr1, and pm3mr1 fields. figure 10-21. performance monitor mask registers (pm n mr1) table 10-25 describes the pm n mr1 registers. 10.3.5 message registers writing to one of the four message registers (m sgr0?msgr3) causes a messaging interrupt to the processor. reading this register cl ears the messaging interrupt. note that a messaging interrupt can also be cleared by writing a one to the corres ponding status field of the pic messa ge status register (msr), shown in figure 10-24 . 10.3.5.1 message registers (msgr0?msgr3) the message registers (msgr0?m sgr3) contain a 32-bit message. figure 10-22. message registers (msgrs) table 10-26 describes the msgr registers. 0 31 r int w reset 1111_1111_1111_1111_1111_1111_1111_1111 offset pm0mr1 0x4_1360, pm1mr1 0x4_13 80, pm2mr1 0x4_13a0, pm3mr1 0x4_13c0 table 10-25. pm n mr1 field descriptions bits name description 0?31 int internal interrupts 0?31 0 the corresponding interrupt source generates a performance monitor event when the interrupt occurs. 1 the corresponding interrupt does not generate a performance monitor event. 0 31 r msg w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset msgr0 0x4_1400, msgr1 0x4_141 0, msgr2 0x4_1420, msgr3 0x4_1430 table 10-26. msgr n field descriptions bits name description 0?31 msg message. contains the 32-bit message data 4 datasheet u .com
programmable interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 10-29 10.3.5.2 message enable register (mer) the message enable register (mer) shown in figure 10-23 contains the enable bits for each message register. the enable bit must be set to enable inte rrupt generation when the co rresponding message register is written. figure 10-23. message enable register (mer) table 10-27 describes the mer fields. 10.3.5.3 message status register (msr) the pic message status register (msr) shown in figure 10-24 contains status bits for each message register. the status bit is set when the corres ponding messaging interrupt is active. reading the corresponding message register or wr iting a 1 to a status bit or writi ng a 1 to a status bit clears the corresponding message interrupt and the status bit. 0 27 28 29 30 31 r0000000000000000000000000000 e3 e2 e1 e0 w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x4_1500 table 10-27. mer field descriptions bits name description 0?27 ? reserved 28 e3 enable 3. used to enable interrupt generation for msgr3 0 interrupt generation for msgr3 disabled 1 interrupt generation for msgr3 enabled 29 e2 enable 2. used to enable interrupt generation for msgr2 0 interrupt generation for msgr2 disabled 1 interrupt generation for msgr2 enabled 30 e1 enable 1. used to enable interrupt generation for msgr1 0 interrupt generation for msgr1 disabled 1 interrupt generation for msgr1 enabled 31 e0 enable 0. used to enable interrupt generation for msgr0 0 interrupt generation for msgr0 disabled 1 interrupt generation for msgr0 enabled 4 datasheet u .com
programmable interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 10-30 freescale semiconductor figure 10-24. message status register (msr) table 10-28 describes the msr fields. 10.3.6 interrupt source configuration registers the interrupt source configuration re gisters control the source of each interrupt, specifying parameters such as the interrupting event, si gnal polarity, and relative priority. 10.3.6.1 external interrupt vector/p riority registers (eivpr0?eivpr11) the external interrupt vector/priorit y registers (eivprs) cont ain polarity and sense fi elds for the external interrupts caused by the assertion of any of irq[ 0:11]. the format of the eivprs is shown in figure 10-25 . 0 27 28 29 30 31 r0000000000000000000000000000 s3 s2 s1 s0 w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x4_1510 table 10-28. msr field descriptions bits name description 0?27 ? reserved 28 s3 status 3. reports status of messaging in terrupt 3. writing a 1 clears this field. 0 messaging interrupt 3 is not active 1 messaging interrupt 3 is active 29 s2 status 2. reports status of messaging interrupt 2. writing a 1 clears this field. 0 messaging interrupt 2 is not active 1 messaging interrupt 2 is active 30 s1 status 1. reports status of messaging interrupt 1. writing a 1 clears this field. 0 messaging interrupt 1 is not active 1 messaging interrupt 1 is active 31 s0 status 0. reports status of messaging interrupt 0. writing a 1 clears this field. 0 messaging interrupt 0 is not active 1 messaging interrupt 0 is active 4 datasheet u .com
programmable interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 10-31 figure 10-25. external interrupt vector/priority registers (eivpr0 ? eivpr11) table 10-29 describes the eivpr fields. 10.3.6.2 external interrupt destin ation registers (eidr0?eidr11) the external interrupt destinati on registers (eidrs), shown in figure 10-26 , control the destination of external interrupts caused by the asse rtion of any of irq[0:11]. all exte rnal interrupts are directed to the processor 0 interrupt, int , by default. external interrupts can be selectively directed to irq_out or to the processor 0 critical interrupt signal, cint , instead of int by writing to the appropriate eidr n fields. note the behavior of the pic unit is not defi ned if both the ep a nd ci bits of the same interrupt destinat ion register are set. 0 1 2 7 8 9 10 11 12 15 16 31 r msk a000000 ps 00 priority vector w reset 1000_0000_0000_0000_0000_0000_0000_0000 offset eivpr0 0x5_0000, eivpr1 0x5_0020, eivpr2 0x5_0040, eivpr3 0x5_0060 , eivpr4 0x5_0080, eivpr5 0x5_00a0, eivpr6 0x5_00c0, eivpr7 0x5_00e0, eivpr8 0x5_ 0100, eivpr9 0x5_0120, eivpr10 0x5_0140, eivpr11 0x5_0160 table 10-29. eivpr n field descriptions bits name description 0 msk mask. masks interrupts from this source 0 if the corresponding ipr bit is set an interrupt request is generated. 1 interrupts from this source are disabled. 1 a activity. a read-only field indicating that an interrupt has been requested or is in-service. note: the p (polarity), s (sense), vector and priority val ues should not be changed while the corresponding interrupt is active, that is, while eivpr n [a] is set. 0 no current interrupt activity associated with this source 1 the interrupt bit for this source is set in the ipr or isr. 2?7 ? reserved 8 p polarity. specifies the polarity for the external interrupt. 0 polarity is active-low or negative edge triggered 1 polarity is active-high or positive edge-triggered 9 s sense. specifies the sense for external interrupts 0 the external interrupt is edge sensitive. 1 the external interrupt is level-sensitive. 10?11 ? reserved 12?15 priority priority. specifies the interrupt priority. the lowest priority is 0 and the highest priority is 15. a priority le vel of 0 disables interrupts from this source. 16?31 vector vector. contains the value returned when the interrupt acknowledge (iack) register is read and this interrupt resides in the interrupt request register (irr) shown in figure 10-37 . 4 datasheet u .com
programmable interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 10-32 freescale semiconductor figure 10-26. external interrupt destination registers (eidrs) table 10-30 describes the eidr fields. because external in terrupts can be channeled only to processor 0, the p0 bit is permanently set. as shown in figure 10-37 , if either the ci or ep bi ts are set, the interrupt is not sent to the processor?s interrupt input. the ep or ci fields must be set only for level-sensitive interrupts. setting these fields for edge-sensitive interrupts does not provide re liable interrupt response. 10.3.6.3 internal interrupt vector/p riority registers (iivpr0?iivpr31) the internal interrupt vector/prior ity registers (iivprs), shown in figure 10-27 , have the same fields and format as the gtvprs, except th at they apply to the internal interrupt sources listed in table 10-3 . these interrupts are all level sensitive. note because all internal interrupts ar e active-high, clearing any iivpr n polarity field disables that interrupt. care should be taken to ensure this field is not inadvertently corrupted when loading or reloading iivprs with priority, mask, or vector data. 012 30 31 r ep ci 00000000000000000000000000000p0 w reset 0000_0000_0000_0000_0000_0000_0000_0001 offset eidr0 0x5_0010, eidr1 0x5_003 0, eidr2 0x5_0050, eidr3 0x5_0070, eidr4 0x5_0090, eidr5 0x5_00b0, eidr6 0x5_00d0, eidr7 0x5_00f0, eidr8 0x5_0110, eidr9 0x5_0130, eidr10 0x5_0150, eidr11 0x5_0170 table 10-30. eidr n field descriptions bits name description 0 ep external pin. allows external interrupt to be serviced externally 0 external interrupt is serviced internally with int signal to the processor core 1 external interrupt is directed to irq_out for external service 1 ci critical interrupt 0 external interrupt is serviced internally with int signal to the processor core 1 external interrupt is directed to the pr ocessor 0 as a critical interrupt with the cint signal 2?30 ? reserved 31 p0 processor 0. indicates that processor 0 handles any in terrupt. this bit is meaningful only in a multi-core device. because the MPC8555E is a single-core device, all interrupts that are serviced internally are always directed to processor 0. permanently set and read only 1 interrupt directed to processor 0 4 datasheet u .com
programmable interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 10-33 figure 10-27. internal interrupt vector/priority registers (iivprs) table 10-31 describes the iivpr fields. 10.3.6.4 internal interrupt destin ation registers (iidr0?iidr31) internal interrupt destinati on registers (iidr s), shown in figure 10-28 , have the same fields and format as eivdrs, except that they apply to th e internal interrupt sources listed in table 10-3 . like external interrupts, internal interrupts can be directed only to processor 0. note the behavior of the pic unit is not defi ned if both the ep a nd ci bits of the same interrupt destinat ion register are set. 0 1 2 7 8 9 11 12 15 16 31 r msk a000000 p 000 priority vector w reset 1000_0000_1000_0000_0000_0000_0000_0000 offset iivpr0?7 0x5_0200, 0x5_0220, 0x5_0240, 0x5 _0260, 0x5_0280, 0x5_02a0, 0x5_02c0, 0x5_02e0 iivpr8?15 0x5_0300, 0x5_0320, 0x5_0340, 0x5_0360, 0x5_0380, 0x5_03a0, 0x5_03c0, 0x5_03e0 iivpr16?23 0x5_0400, 0x5_0420, 0x5_0440, 0x5_0460, 0x5_0480, 0x5_04a0, 0x5_04c0, 0x5_04e0 iivpr24?31 0x5_0500, 0x5_0520, 0x5_0540, 0x5_0560, 0x5_0580, 0x5_05a0, 0x5_05c0, 0x5_05e0 table 10-31. iivpr n field descriptions bits name description 0 msk mask. mask interrupts from this source. 0 an interrupt request is generated when the corresponding ipr field is set. 1 further interrupts from this source are disabled. 1 a activity. indicates an interrupt has been requested or is in-service. note this field is read only. the vector and priority values should not be changed while iivpr n [a] is set. 0 no current interrupt activity associated with this source 1 the interrupt field for this source is set in the ipr or isr. 2?7 ? reserved 8 p polarity. specifies the polarity for the internal interrupt. note: because all internal interrupts are active-high, clearing this bit disables the interrupt. 0 interrupt polarity is active-low. this value disables the interrupt. 1 interrupt polarity is active-high. this is the reset value should not be changed. 9?11 ? reserved 12?15 priority priority. specifies the interrupt priority. the lowest priority is 0 and the highest priority is 15. a priority le vel of 0 disables interrupts from this source. 16?31 vector vector. the vector value in this field is return ed when the interrupt acknowledge (iack) register is read and this interrupt resides in the interrupt request register (irr) shown in figure 10-37 . 4 datasheet u .com
programmable interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 10-34 freescale semiconductor figure 10-28. internal interrupt destination registers (iidrs) table 10-32 describes the iidr fields. 10.3.6.5 messaging interrupt vector/priority registers (mivpr0?mivpr3) the messaging interrupt vector/prior ity registers (mivprs) have the same fields and format as the gtvprs, except they apply to messaging interrupts. figure 10-29. messaging interrupt vector/priority registers (mivprs) 012 30 31 r ep ci 0000000000000000000000000000 0 p0 w reset 0000_0000_0000_0000_0000_0000_0000_0001 offset iidr0?7 0x5_0210, 0x5_0230, 0x5_0250, 0x 5_0270, 0x5_0290, 0x5_02b0, 0x5_02d0, 0x5_02f0 iidr8?15 0x5_0310, 0x5_0330, 0x5_0350, 0x5_03 70, 0x5_0390, 0x5_03b0, 0x5_03d0, 0x5_03f0 iidr16?23 0x5_0410, 0x5_0430, 0x5_0450, 0x5_0470, 0x5_0490, 0x5_04b0, 0x5_04d0, 0x5_04f0 iidr24?31 0x5_0510, 0x5_0530, 0x5_0550, 0x5_0570, 0x5_0590, 0x5_05b0, 0x5_05d0, 0x5_05f0 table 10-32. iidr n field descriptions bits name description 0 ep external pin. allows internal interrupt to be serviced externally 0 internal interrupt is serviced internally with int signal to the processor core 1 internal interrupt is directed to irq_out for external service. the behavio r of the pic is not defined if both ep and ci are set on the same interrupt destination register. 1 ci critical interrupt 0 internal interrupt is serviced internally with int signal to the processor core 1 internal interrupt is directed to the proc essor 0 as a critical interrupt with the cint signal. the behavior of the pic is not defined if both ep and ci are se t on the same interrupt destination register. 2?30 ? reserved 31 p0 processor 0. indicates that processor 0 handles any in terrupt. this bit is meaningful only in a multi-core device. because the MPC8555E is a single-core device, all interrupts that are serviced internally are always directed to processor 0. permanently set and read only. 1 interrupt directed to processor 0 0 1 2 1112 1516 31 r msk a0000000000 priority vector w reset 1000_0000_0000_0000_0000_0000_0000_0000 offset 0x5_1600, 0x5_1620, 0x5_1640, 0x5_1660, 4 datasheet u .com
programmable interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 10-35 table 10-33 describes the mivpr fields. 10.3.6.6 messaging interrupt destination registers (midr0?midr3) the messaging interrupt destinati on registers (midrs), shown in figure 10-30 , control the destination for the messaging interrupts. midr enables the user to direct the interrupt to either the external interrupt output pin (irq_out ), the core?s critical interrupt input ( cint ), or to its normal interrupt input ( int ). note the behavior of the pic unit is not defi ned if both the ep a nd ci bits of the same interrupt destinat ion register are set. figure 10-30. messaging interrupt destination registers (midrs) table 10-33. mivpr n field descriptions bits name description 0 msk mask. mask interrup ts from this source 0 an interrupt request is generated when the corresponding ipr field is set. 1 further interrupts from this source are disabled. 1 a activity. indicates an interrupt has been requested or is in-service. note this field is read only. the vector and priority values should not be changed while mivpr n [a] is set. 0 no current interrupt activity associated with this source. 1 the interrupt field for this source is set in the ipr or isr. 2?11 ? reserved 12?15 priority priority. specifies the interrupt priority. the lowest priority is 0 and the highest priority is 15. a priority le vel of 0 disables interrupts from this source. 16?31 vector vector. the vector value in this field is return ed when the interrupt acknowledge (iack) register is read and this interrupt resides in the interrupt request register (irr) shown in figure 10-37 . 012 30 31 r ep ci 00000000000000000000000000000p0 w reset 0000_0000_0000_0000_0000_0000_0000_0001 offset 0x5_1610, 0x5_1630, 0x5_1650, 0x5_1670 4 datasheet u .com
programmable interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 10-36 freescale semiconductor table 10-34 describes the midr fields. 10.3.7 per-cpu registers the openpic programming model supports multiprocesso r systems of up to 32 se parate processors. as such, the openpic interface specification provides fo r coordinating both the requesting and servicing of interrupts among several processor cores within a singl e integrated device. to fully comply with the openpic specification, the MPC8555E pic incorporates several of these multiprocessor capabilities. because the value of features such as private a ddress space for per-cpu registers and interprocessor interrupts is fully realized only in a multi-core envir onment, their utility in this single-core device is not intuitive. the registers in table 10-35 are called per-cpu registers, because they would be duplicated for each core in a multi-core device. the openpic interface specifies that a copy of thes e registers be av ailable to each core at the same physical a ddress by using the id of the processor that initiates th e transaction to determine the set of per-cpu registers to access. table 10-34. midr n field descriptions bits name description 0 ep external pin. allows message interrupt to be serviced externally 0 message interrupt is serviced internally with int signal to the processor core. 1 message interrupt is directed to irq_out for external service. the behavior of the pic is not defined if both ep and ci are set on the same interrupt destination register. 1 ci critical interrupt 0 message interrupt is serviced internally with int signal to the processor core. 1 message interrupt is directed to the processor 0 as a critical interrupt with the cint signal. the behavior of the pic is not defined if both ep and ci are se t on the same interrupt destination register. 2?30 ? reserved 31 p0 processor 0. indicates that processor 0 handles any in terrupt. this bit is meaningful only in a multi-core device. because the MPC8555E is a single-core device, all interrupts that are serviced internally are always directed to processor 0. permanently set and read only. 1 interrupt directed to processor 0 table 10-35. per-cpu registers?private access address offsets register name offset ipi 0 dispatch register (ipidr0) 0x4_0040 ipi 1 dispatch register (ipidr1) 0x4_0050 ipi 2 dispatch register (ipidr2) 0x4_0060 ipi 3 dispatch register (ipidr3) 0x4_0070 current task priority register (ctpr) 0x4_0080 who am i register (whoami) 0x4_0090 interrupt acknowledge register (iack) 0x4_00a0 end of interrupt register (eoi) 0x4_00b0 4 datasheet u .com
programmable interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 10-37 these addresses, shown in table 10-35 , appear in the memory map at the same offset for every processor, and are called the private access sp ace. because the MPC8555E has only one core, there is only one set of per-cpu registers, each register having two addresses. for example, the ctpr is located normally at 0x6_0080, and also at the private access addr ess of 0x4_0080. while this double mapping seems superfluous on a single-core de vice, the purpose of this f eature is to enable user code to execute correctly in a multiprocessor environment wi thout needing to know which cpu it is running on. it is included on this device to simplify the porting of such code. an example of how the different registers are addr essed in a four-core devi ce is illustrated in figure 10-31 . note that when accessing a register normally, each core sources a di fferent address. however, when accessing the same register using the per-cpu addr ess space, each core sources the same address. figure 10-31. per-cpu register address decoding in a four-core device 10.3.7.1 interprocessor interrupt di spatch register (ipidr0?ipidr3) there are four interprocessor interrupt dispatch registers (ipidrs), one for each ipi channel, as shown in figure 10-32 . writing to an ipidr with a bit set causes a se lf interrupt. while the concept of interprocessor interrupts apparently makes little sense in a single-cor e device, this feature can serve as a doorbell type interrupt because external bus masters can write to these registers. reg 3 reg 2 reg 1 reg 0 id3 id2 id1 id0 0 x 6 3 0 x 6 2 0 x 6 1 0 x 6 0 0 x 4 0 + 3 0 x 4 0 + 2 0 x 4 0 + 1 0 x 4 0 + 0 per-cpu register normal register uses core id processor iack registers (one per core) address 0x40 0x40 0x40 0x40 address cores address decode address decode 0x61 0x62 0x63 0x60 4 datasheet u .com
programmable interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 10-38 freescale semiconductor figure 10-32. interprocessor interrupt dispatch registers (ipidr0?ipidr3) table 10-36 describes the ipidr n fields. 10.3.7.2 processor current task priority register (ctpr) there is one ctpr on this device (MPC8555E) shown in figure 10-33 . software must write the priority of the current processor task in the ctpr. the pic us es this value for comparison with the priority of incoming interrupts. given se veral concurrent incoming interrupts, the highest priority inte rrupt is asserted to the core if the following apply: ? the interrupt is not masked. ? the priority of the interrupt is higher than the values in the ctpr and isr. priority levels from 0 (lowest) to 15 (highest) are supported. setting the task priority to 15 masks all interrupts to the processor. hardwa re sets the task register to 0x00 00_000f during reset or when the px field of the processor initialization register is set. figure 10-33. processor current task priority register (ctpr) 0 30 31 r0000000000000000000000000000000 w p0 reset 0000_0000_0000_0000_0000_0000_0000_0000 offset ipidr0 0x6_0040, ipidr1 0x6_ 0050 ipidr2 0x6_0060, ipidr3 0x6_0070 table 10-36. ipidr n field descriptions bits name description 0?30 ? reserved 31 p0 processor 0. determines if processor 0 receives the interrupt (write only) 0 processor 0 does not receive the interrupt. 1 directs the interrupt to processor 0 0 27 28 31 r0000000000000000000000000000 taskp w reset 0000_0000_0000_0000_0000_0000_0000_1111 offset 0x6_0080 4 datasheet u .com
programmable interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 10-39 table 10-37 describes the ctpr. 10.3.7.3 who am i register (whoami) the processor who am i regi ster (whoami), shown in figure 10-34 , can be read by the processor to determine its physical connection to th e pic. the value returned when reading this register may be used to determine the value for the destinati on masks used for di spatching interrupts. figure 10-34. processor who am i register (whoami) table 10-38 describes the whoami fields. 10.3.7.4 processor interrupt acknowledge register (iack) in systems based on processors th at implement the power architec ture technology, the interrupt acknowledge function occurs as an explicit read operation to a me mory-mapped interrupt acknowledge register (iack), shown in figure 10-35 . reading the interrupt acknowledge register returns the interrupt vector corresponding to the highest priority pending interrupt. reading iack also has the following side effects: ? the associated field in the interrupt pending re gister is cleared for edge-sensitive interrupts. ? the in-service register (isr) is updated. ? the interrupt signal ( int or cint ) to the processor is negated. reading this register when there is no pending interrupt returns the spurious vect or value as described in section 10.3.1.6, ?spurious vect or register (svr).? table 10-37. ctpr field descriptions bits name description 0?27 ? reserved 28?31 taskp task priority. this field is set from 0 to 15, where 15 corresponds to the highest priority for processor tasks. if ctpr[taskp] = 0xf, no interrupts are signaled to the processor. 0 26 27 31 r000000000000000000000000000 id w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x6_0090 table 10-38. whoami field descriptions bits name description 0?26 ? reserved 27?31 id id. returns the id of the processor reading this register. always returns zero. 00000 processor core 4 datasheet u .com
programmable interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 10-40 freescale semiconductor figure 10-35. processor interrupt acknowledge register (iack) table 10-39 describes the iack fields. 10.3.7.5 processor end of interrupt register (eoi) writing to the end of interru pt (eoi) register shown in figure 10-36 signals the end of processing for the highest-priority interrupt currently in-service by the processor. the write to the eoi updates the isr by retiring the highest priority interrupt . data values written to this regi ster are ignored, and zero is assumed. figure 10-36. end of interrupt register (eoi) table 10-40 describes the eoi fields. 01516 31 r0 00000000000000 0 vector w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x6_00a0 table 10-39. iack field descriptions bits name description 0?15 ? reserved 16?31 vector interrupt vector. vector of the highest pending interrupt (read only) 0 27 28 31 r000000000000000000000000000 0 w eoi code reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x6_00b0 table 10-40. eoi field descriptions bits name description 0?27 ? reserved 28?31 eoi code 0000 (write only) 4 datasheet u .com
programmable interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 10-41 10.4 functional description this section is a functional description of the pic. 10.4.1 flow of in terrupt control figure 10-37 is a block diagram of the pic unit showing th e flow of interrupt processing. this figure is intended to aid in understanding a nd does not fully represent all in ternal circuitry of the actual implementation. the pic receives inte rrupt signals from both external and internal sources. these signals are qualified and latched in the inte rrupt pending register (ipr). the ipr feeds the interrupt selector (is). the interrupt router of the pic monito rs the outputs of its internal interr upt request register (irr) and other configuration registers. when the priority of the interr upt latched in the irr is higher than the value in the processor?s task priority register, the interrupt router asserts the inte rnal interrupt signal ( int ) to indicate an interrupt request to the processor. this causes the pr ocessor to vector to the external interrupt handler. note that the ipr, is, and irr are internal re gisters that are not accessible to the programmer. the interrupt handler executing on the processor shoul d then acknowledge the interrupt by explicitly reading iack (at which point the interr upt is considered to be in-service) . the pic unit interprets this read as an interrupt acknowledge (iack) cy cle; in response, the pic unit returns the vector associated with the interrupt source to the interrupt handler routine. the handler can further vector to different branches of interrupt handling accordingly. note that reading iack also negates th e interrupt signal to the processor. see section 10.3.7.4, ?processor interrupt acknowledge register (iack),? for more details. the internal in-service register (isr) tracks all in-service interrupts. an interrupt is considered in-service from the time its vect or is read (through an iack cy cle) until the end of interrupt (eoi) register is written, generating what the pic considers an eoi signal. 4 datasheet u .com
programmable interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 10-42 freescale semiconductor figure 10-37. pic interrupt processing flow diagram 10.4.1.1 interrupt source priority each interrupt source is assigned a priority value th rough its corresponding vector/pri ority register. priority values range from 0 to 15, where 15 is the highest. interrupts are delivered only when the priority of the pic configuration and status registers interrupt pending register internal, external, & interrupt selector in-service register int iack eoi cint mask critical interrupt xidr[ci] external pin xidr[ep] irq_out global timers (4) inter-processor message interrupts (is) to processor core note: all signal lines represent buses except for int , cint , and irq_out . the behavior of the pic unit is not defined if both the ep and ci bits of the same interrupt destination register are set. interrupt router to p r o c e s s o r c o r e end of interrupt register highest priority interrupt (isr) processor?s task priority register interrupt request register pipeline latch (irr) activity bit (ipr) 4 datasheet u .com
programmable interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 10-43 interrupt source is greater than the cu rrent task priority. therefore setting a source priority to zero inhibits that interrupt. the pic unit services simultaneous in terrupts occurring with the same pr iority according to the following order: 1. msg0?msg3 2. ipi0?ipi3 3. timer0?timer3 4. irq[0:11] 5. internal0?internal31 for example, if msg0, msg 2, and ipi0 all have the same priority and receive simultane ous interrupts, the MPC8555E services them in the following order: 1. msg0 2. msg2 3. ipi0 10.4.1.2 processor current task priority the ctpr is set by system softwa re to indicate the relative im portance of the task running on the processor. the processor does not receive interrupts with a priority level equal to or lower than its current task priority. therefore sett ing the current task priority to 15 for a pa rticular processor pr events the delivery of any interrupt to the processor. 10.4.1.3 interrupt acknowledge the pic unit notifies the processor core of an interrupt by asserting the int signal. when the processor core acknowledges the interrupt request by reading the interrupt acknowledge re gister (iack) in the pic unit, the pic returns the 16-bit vector associated with the in terrupt source to the processor. the interrupt is then considered to be in-service, and remains in-service unt il the processor performs a write to the pic unit end of interrupt register (eoi). writing to th e eoi is referred to as an eoi cycle. 10.4.2 nesting of interrupts if the processor is servicing an inte rrupt, it can only be interrupted agai n if the pic receives an interrupt request from a source with higher pr iority than the one currently being serviced. this is true even if software, as part of its interr upt service routine, writes a ne w and lower value into the ctpr. thus, although several interrupts may be in-service simultaneo usly, the code currently executing is always handling the highest priority of all the interrupts that are in se rvice. when the processor performs an eoi cycle, this highest priority interr upt is taken out-of-service. the next eoi cycle takes the next-highest priority interrupt out-of-serv ice, and so on. an interrupt with lower pr iority than those currently in-service is not started until all highe r priority interrupts complete even if its priority is greater than the ctpr value. 4 datasheet u .com
programmable interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 10-44 freescale semiconductor 10.4.3 processor initialization the processor can reset itself by writing to the proce ssor initialization register (pir). this causes the assertion of the core_reset output signal. when this occurs, the pr ocessor also gets written to 0x000f to disable the delivery of any interrupts. 10.4.4 spurious vector generation under certain circumstances, the pic has no valid vector to return to the processor during an interrupt acknowledge cycle. in these cases, the spurious vector from the spurious vector register is returned. the following cases cause a spurious vector fetch: ? int is asserted in response to an externally sourced interrupt which is activat ed with level-sensitive logic, and the asserted level is nega ted before the interrupt is acknowledged. ? int is asserted for an interrupt source that is late r masked (using the mask bi t in the vector/priority register corresponding to that source) before the interrupt is acknowledged. ? int is asserted for an interrupt source that is late r masked by an increase in the task priority level before the interrupt is acknowledged. ? an interrupt acknowledge cycle is performed by the processor in spite of the fact that the int signal has not been asserted by the pic. in all cases, a spurious vect or is not returned if there is another pending interrupt th at has sufficient priority to interrupt the processor. if such an interrupt is availa ble, the vector for that in terrupt source is returned. the eoi register should not be written in response to the spurious vector. otherwise, a previously-accepted interrupt might be cleared unintentionally. 10.4.5 messaging interrupts there are four 32-bit message registers that can be used to send 32-bit messages to the processor. a messaging interrupt is generated by writing a messag e register if the corresponding enable bit in the message enable/status register is set, and the interr upt is not masked. reading the message register or writing a 1 to the status bit clears the interrupt. 10.4.6 global timers there are appropriate clock prescalers and synchronizers to provi de a time base for the four internal timers of the pic unit. the timers can be individually progr ammed to generate a processor interrupt when they count down to zero and can be used to generate regu lar periodic interrupts. each timer has the following four configuration and control registers: ? global timer current count register (gtccr n ) ? global timer base count register (gtbcr n ) ? global timer vector-priority register (gtvpr n ) ? global timer destination register (gtdr n ) the timer frequency should be written to the tfrr. (all of the timers ope rate at this frequency.) refer to section 10.3.2.1, ?timer frequency reporting register (tfrr),? for a description of this register. 4 datasheet u .com
programmable interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 10-45 timer interrupts are all edge-triggere d interrupts. if a timer period expire s while a previous interrupt from the same source is pending or in-servi ce, the subsequent interrupt is lost. the timer control register (tcr) provi des users with the ability to crea te timers larger than the 31-bit global timers. the option also exists to change the timer frequency by sett ing the appropriate fields of the tcr. see section 10.3.2.6, ?timer control register (tcr).? 10.4.7 reset of the pic the pic unit is reset by a device power -on reset (por) or by software that sets the gcr[rst] bit. both of these actions cau se the following: ? all pending and in-service interrupts are cleared. ? all interrupt mask bits are set. ? polarity, sense, external pin, cr itical interrupt, and activity fields, are reset to their default values. ? pir, tfrr, tcr, mer, msr, and msgr0?3 are cleared. ? msg and timer destination fields are set. ? the ipi dispatch registers are cleared. ? all timer base count values are reset to zero and count inhibited. ? the ctpr[taskp] is reset to 0xf, thus disa bling interrupt delivery to the processor. ? the spurious interrupt vector resets to 0xffff. ? the pmmrs are reset to 0xffff. ? the pic defaults to the pa ss-through mode (gcr[m] = 0). ? all other registers remain at their pre-reset programmed values. the gcr[rst] bit is automatically cleared when the reset sequence is complete. 10.5 initialization/application information this section contains initialization a nd application information for the pic. 10.5.1 programming guidelines the following subsections contain info rmation about programming pic registers. 10.5.1.1 pic registers most pic control and status registers are readable and return the la st value written. the exceptions to this rule are as follows: ? ipi dispatch registers and the eoi register, which return zeros on reads. ? activity bit (a) of the vector/pri ority registers, which returns the value according to the status of the current interrupt source. 4 datasheet u .com
programmable interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 10-46 freescale semiconductor ? iack register, which returns the vector of highe st priority which is currently pending, or the spurious vector. ? reserved fields always return 0. the following guidelines are r ecommended when the pic unit is programmed in mixed mode (gcr[m] = 1): ? all pic registers must be located in a cache- inhibited and guarded area (through the processor mmu). ? the pic portion of the address map must be set-up appropriately. in addition, the following initia lization sequence is recommended: 1. write the vector, priority, and polarity values in each interrupt?s vector/p riority register, leaving their msk (mask) bit set. this is required only if interrupts are used. 2. clear the ctpr (ctpr = 0x0000_0000). 3. program the pic to mixed mode by setting gcr[m]. 4. clear the msk bit in the vector /priority registers to be used. 5. perform a software loop to clear all pending interrupts: ? load counter with fpr[nirq]. ? while counter > 0, perform iack and eois to guarantee all the interrupt pending and in-service registers are cleared. 6. set the processor ctpr value to the desired value. depending on the interrupt system configuration, the pic may generate spurious interrupts to clear interrupts latched during power-up. a spurious or non-spurious vector is returned for an interrupt acknowledge cycle in this case . see the programming note belo w for the non-spurious case. note because the default polarity/sense for ex ternal interrupts is edge-sensitive, and edge-sensitive interr upts are not cleared until they are acknowledged, it is possible for the pic to store spurious edges de tected during power-up as pending external interrupts. if software permanently configures an external interrupt source to be edge-sensitive , it may receive the vector for the interrupt source and not a spurious interrupt vector when software clears the mask bit. this can occur once for any e dge-sensitive interrupt when its mask bit is first cleared and the pic is in mixed mode. to avoid having to handle a false interr upt for this case, software can clear the pic interrupt pending regi ster of these spurious edge detections by first configuring the polarity/sense of ex ternal interrupt sources to be level-sensitive; high-level if the input is a positive- edge source, low-level if it?s a negative-edge source (while the mask bit remains set). after this is complete, configuring the external inte rrupt source as edge-sensitive will not cause a false interrupt. 4 datasheet u .com
programmable interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 10-47 10.5.1.2 changing interrupt source configuration to change the vector, priority, polarit y, sense or destination of an acti ve (unmasked) inte rrupt source, the following sequence should be performed: 1. mask the source using the mask (msk) bit in the vector/priority register. 2. wait for the activity (a) bit for that source to be cleared. 3. make the desired changes. 4. unmask the source. 4 datasheet u .com
programmable interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 10-48 freescale semiconductor 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 11-1 chapter 11 i 2 c interface this chapter describes the inter-ic (iic or i 2 c) bus interface implemented on this device. 11.1 introduction the i 2 c bus is a two-wire?serial data (sda) and serial clock (scl)? bidirectional serial bus that provides a simple efficient method of data exchange between this devi ce and other devices, such as microcontrollers, eeproms, real-time clock devices, a/ d converters, and lcds. figure 11-1 shows a block diagram of the i 2 c interface. figure 11-1. i 2 c block diagram i2cadr i2cfdr i2ccr i2csr i2cdr addr decode data mux address compare input sync in/out data shift register clock control sda address and control interrupt data arb_lost and digital filter start/ stop/ restart and arbitration control and i2cdsrr scl 4 datasheet u .com
i 2 c interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 11-2 freescale semiconductor 11.1.1 overview the two-wire i 2 c bus minimizes interconnecti ons between devices. the s ynchronous, multiple-master i 2 c bus allows the connection of additi onal devices to the bus for expansi on and system development. the bus includes collision detection and arbitration that prevent data corrup tion if two or more masters attempt to control the bus simultaneously. 11.1.2 features the i 2 c interface includes the following features: ? two-wire interface ? multiple-master operation ? arbitration lost interrupt with automati c mode switching from master to slave ? calling address iden tification interrupt ? start and stop signal generation/detection ? acknowledge bit generation/detection ? bus busy detection ? software-programmable clock frequency ? software-selectable acknowledge bit ? on-chip filtering for spikes on the bus 11.1.3 modes of operation the i 2 c unit on this device can operate in one of the following modes: ? master mode?the i 2 c is the driver of the sda line. it cannot use its own slave address as a calling address. the i 2 c cannot be a master and a slave simultaneously. ? slave mode?the i 2 c is not the driver of the sda line. the module must be enabled before a start condition from a non-i 2 c master is detected. ? interrupt-driven byte-to-byte da ta transfer?when succe ssful slave addressing is achieved (and scl returns to zero), the data tr ansfer can proceed on a byte-to-byte basis in the direction specified by the r/w bit sent by the calling master. each byte of data must be followed by an acknowledge bit, which is signaled from the receiving device. several bytes can be transferred during a data transfer session. ? boot sequencer mode?this mode can be used to initialize the conf iguration register s in the device after the i 2 c module is initialized. note that the device powers up with b oot sequencer mode disabled as a default, but this mode can be selected with the cfg_boot_seq[0:1] power-on reset (por) configuration signals that are located on the lgpl3 and lgpl5 signals. additionally, the following three i 2 c-specific states are defined for the i 2 c interface: ? start condition?this condition denotes the beginning of a new data transfer (each data transfer contains several bytes of da ta) and awakens all slaves. 4 datasheet u .com
i 2 c interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 11-3 ? repeated start condition?a start condition that is generated without a stop condition to terminate the previous transfer. ? stop condition?the master can terminate the tr ansfer by generating a stop condition to free the bus. 11.2 external signal descriptions the following sections give an overview of si gnals and provide detail ed signal descriptions. 11.2.1 signal overview the i 2 c interface uses the sda and scl signals, described in table 11-1 , for data transfer. note that the signal patterns driven on sda represen t address, data, or read/write info rmation at different stages of the protocol. 11.2.2 detailed signal descriptions sda and scl, described in table 11-2 , serve as a communication interc onnect with other devices. all devices connected to these two signa ls must have open-drain or open -collector outputs. the logic and function is performed on both of these signals wi th external pull-up resistors. refer to the MPC8555E powerquicc? iii integrated proces sor family hardware specifications for the electrical characteristics of these signals. table 11-1. i 2 c interface signal descriptions signal name idle state i/o state meaning serial clock (iic_scl) high i when the i 2 c module is idle or acts as a slave, sc l defaults as an input. the unit uses scl to synchronize incoming data on sda. the bus is assumed to be busy when scl is detected low. o as a master, the i 2 c module drives scl along with sda when transmitting. as a slave, the i 2 c module drives scl low for data pacing. serial data (iic_sda) high i when the i 2 c module is idle or in a receiving mode, sda defaults as an input. the unit receives data from other i 2 c devices on sda. the bus is assumed to be busy when sda is detected low. o when writing as a master or slave, the i 2 c module drives data on sda synchronous to scl. 4 datasheet u .com
i 2 c interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 11-4 freescale semiconductor 11.3 memory map/register definition table 11-3 lists the i 2 c-specific registers and their offsets. it lists the offset , name, and a cross-reference to the complete description of each register. note that the full regist er address is comprised of ccsrbar together with the block base address and offset listed in table 11-3 . in this table and in the register figures and field descriptions, th e following access definitions apply: ? reserved fields are always ignored for the purposes of determining access type. ? r/w, r, and w (read/write, read only, and write only) indicate that all the non-reserved fields in a register have the same access type. ? w1c indicates that all of the non-reserved fields in a register are cleared by writing ones to them. ? mixed indicates a combination of access types. ? special is used when no other cate gory applies. in this case the re gister figure and field description table should be read carefully. all i 2 c registers are one byte wide. reads and writes to these registers must be byte-wide operations. table 11-2. i 2 c interface signal?detailed signal descriptions signal i/o description iic_scl i/o serial clock. performs as an input when the device is programmed as an i 2 c slave. scl also performs as an output when the device is programmed as an i 2 c master. o as outputs for the bidirectional serial clock, these signals operate as described below. state meaning asserted/negated?driven along with sda as the clock for the data. i as inputs for the bidirectional serial clock, these signals operate as described below. state meaning asserted/negated?the i 2 c unit uses this signal to synchronize incoming data on sda. the bus is assumed to be busy when this signal is detected low. iic_sda i/o serial data. performs as an input when the device is in a receiving mode. sda also performs as an output signal when the device is transmitting (as an i 2 c master or a slave). o as outputs for the bidirectional serial data, these signals operate as described below. state meaning asserted/negated? data is driven. i as inputs for the bidirectional serial data , these signals operate as described below. state meaning asserted/negated?used to receive data from othe r devices. the bus is assumed to be busy when sda is detected low. 4 datasheet u .com
i 2 c interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 11-5 11.3.1 register descriptions this section describes the i 2 c registers in detail. note reserved bits should always be writte n with the value they returned when read. that is, the register should be programmed by reading the value, modifying appropriate fields, and writi ng back the value. the return value of the reserved fields should not be assumed, even though th e reserved fields return zero. this note does not apply to the i 2 c data register (i2cdr). 11.3.1.1 i 2 c address register (i2cadr) figure 11-2 shows the i2cadr register, which c ontains the address to which the i 2 c interface responds when addressed as a slave. note that this is not the address that is sent on the bus during the address-calling cycle when the i 2 c module is in master mode. table 11-3. i 2 c memory map offset i 2 c register access reset section/page i 2 c registers block base address: 0x0_3000 0x000 i2cadr?i 2 c address register r/w 0x00 11.3.1.1/11-5 0x004 i2cfdr?i 2 c frequency divide r register r/w 0x00 11.3.1.2/11-6 0x008 i2ccr?i 2 c control register mixed 0x00 11.3.1.3/11-7 0x00c i2csr?i 2 c status register mixed 0x81 11.3.1.4/11-9 0x010 i2cdr?i 2 c data register r/w 0x00 11.3.1.5/11-10 0x014 i2cdfsrr?i 2 c digital filter sampling rate register r/w 0x10 11.3.1.6/11-11 offset 0x000 access: read/write 0 67 r addr ? w reset all zeros figure 11-2. i 2 c address register (i2cadr) 4 datasheet u .com
i 2 c interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 11-6 freescale semiconductor table 11-4 describes the fields of i2cadr. 11.3.1.2 i 2 c frequency divider register (i2cfdr) figure 11-3 shows the bits of the i 2 c frequency divider register. re fer to application note an2919, determining the i2c frequency divider ratio for scl , for additional guidance regarding the proper use of i2cfdr and i2cdfsrr. table 11-4. i2cadr field descriptions bits name description 0?6 addr slave address. contains the specific slave address that is used by the i 2 c interface. note that the default mode of the i 2 c interface is slave mode for an address ma tch. note that an address match is one of the conditions that can cause i2cs r[mif] to be set, signaling an interrupt pending condition. 7?reserved offset 0x004 access: read/write 012 7 r ?fdr w reset all zeros figure 11-3. i 2 c frequency divider register (i2cfdr) 4 datasheet u .com
i 2 c interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 11-7 table 11-5 describes the bit settings of i2cfdr. it also maps the i2cfdr [fdr] field to the clock divider values. 11.3.1.3 i 2 c control register (i2ccr) figure 11-4 shows the i 2 c control register, i2ccr. table 11-5. i2cfdr field descriptions bits name description 0?1 ? reserved 2?7 fdr frequency divider ratio. used to prescale the clock for bit rate selection. the serial bit clock frequency of scl is equal to the ccb clock divided by the designated divider. note that the frequency divider value can be changed at any point in a program. the serial bit cloc k frequency divider selections are described as follows: fdr divider (decimal) 0x00 384 0x01 416 0x02 480 0x03 576 0x04 640 0x05 704 0x06 832 0x07 1024 0x08 1152 0x09 1280 0x0a 1536 0x0b 1920 0x0c 2304 0x0d 2560 0x0e 3072 0x0f 3840 0x10 4608 0x11 5120 0x12 6144 0x13 7680 0x14 9216 0x15 10240 fdr divider (decimal) 0x16 12288 0x17 15360 0x18 18432 0x19 20480 0x1a 24576 0x1b 30720 0x1c 36864 0x1d 40960 0x1e 49152 0x1f 61440 0x20 256 0x21 288 0x22 320 0x23 352 0x24 384 0x25 448 0x26 512 0x27 576 0x28 640 0x29 768 0x2a 896 fdr divider (decimal) 0x2b 1024 0x2c 1280 0x2d 1536 0x2e 1792 0x2f 2048 0x30 2560 0x31 3072 0x32 3584 0x33 4096 0x34 5120 0x35 6144 0x36 7168 0x37 8192 0x38 10240 0x39 12288 0x3a 14336 0x3b 16384 0x3c 20480 0x3d 24576 0x3e 28672 0x3f 32768 offset 0x008 access: mixed 01234567 r men mien msta mtx txak ?bcst wrsta reset all zeros figure 11-4. i 2 c control register (i2ccr) 4 datasheet u .com
i 2 c interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 11-8 freescale semiconductor table 11-6 describes the bit settings of the i2ccr. . table 11-6. i2ccr field descriptions bits name description 0 men module enable. this bit cont rols the software reset of the i 2 c module. 0 the module is reset and disabled. when low, the interface is held in reset but the registers can still be accessed. 1 the i 2 c module is enabled. this bit must be set before any other control register bits have any effect. all i 2 c registers for slave receive or master start can be initialized before setting this bit. 1 mien module interrupt enable 0 interrupts from the i 2 c module are disabled. this does not clear any pending interrupt conditions. 1 interrupts from the i 2 c module are enabled. an interrupt occurs provided i2csr[mif] is also set. 2 msta master/slave mode start 0 when this bit is changed from one to zero, a stop condition is generated and the mode changes from master to slave. 1 cleared without generating a stop condition when th e master loses arbitration. when this bit is changed from zero to one, a start condition is generated on the bus, and master mode is selected. 3 mtx transmit/receive mode select. this bit selects the di rection of the master and slave transfers. when configured as a slave, this bit should be set by software according to i2csr[srw]. in master mode, the bit should be set according to the type of transfer r equired. therefore, for address cycles, this bit will alwa ys be high. the mtx bit is cleared when the master loses arbitration. 0 receive mode 1 transmit mode 4 txak transfer acknowledge. this bit specifies the value driven onto the sda line during acknowledge cycles for both master and slave receivers. the value of this bit only applies when the i 2 c module is configured as a receiver, not a transmitter. it also does not apply to address cycles; when the device is addressed as a slave, an acknowledge is always sent. 0 an acknowledge signal (low value on sda) is sent out to the bus at the 9th clock after receiving one byte of data. 1 no acknowledge signal response (high value on sda) is sent. 5 rsta repeated start. setting this bit always generates a repeated start condition on the bus, provides the device with the current bus master. attempting a repeated start at the wrong time (or if the bus is owned by another master), results in loss of arbitration. note t hat this bit is not readable, which means if a read is performed to i2ccr[rsta], a zero value will be returned. 0 no start condition is generated 1 generates repeated start condition 6?reserved 7 bcst broadcast 0 disables the broadcast accept capability 1 enables the i 2 c to accept broadcast messages at address zero 4 datasheet u .com
i 2 c interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 11-9 11.3.1.4 i 2 c status register (i2csr) the i 2 c status register, shown in figure 11-5 , is read only with the exception of the mif and mal bits, which can be cleared by software. the mcf and rxak bits are set at reset; all other i2csr bits are cleared on reset. table 11-7 describes the bit settings of the i2csr. offset 0x00c access: mixed 01234567 r mcf maas mbb mal bcstm srw mif rxak w reset10000001 figure 11-5. i 2 c status register (i2csr) table 11-7. i2csr field descriptions bits name description 0 mcf data transfer. when one byte of data is transferred, t he bit is cleared. it is set by the falling edge of the 9th clock of a byte transfer. 0 byte transfer in progress. mcf is cleared under the following conditions: ? when i2csr is read in receive mode or ? when i2cdr is written in transmit mode 1 byte transfer is completed 1 maas addressed as a slave. when the value in i2cdr matches with the calling address, this bit is set. the processor is interrupted, if i2ccr[mien] is set. next, the processor must check the srw bit and set i2ccr[mtx] accordingly. writing to t he i2ccr automatically clears this bit. 0 not addressed as a slave 1 addressed as a slave 2 mbb bus busy. indicates the status of the bus. when a start condition is detected, mbb is set. if a stop condition is detected, it is cleared. 0i 2 c bus is idle 1i 2 c bus is busy 3 mal arbitration lost. automatically set when the arbitr ation procedure is lost. note that the device does not automatically retry a failed transfer attempt. 0 arbitration is not lost. can only be cleared by software 1 arbitration is lost 4 bcstm broadcast match 0 there has not been a broadcast match. 1 the calling address matches with the broadcast addres s instead of the programmed slave address. this will also be set if this i 2 c drives an address of all 0s and broadcast mode is enabled. 5 srw slave read/write. when maas is set, srw indicates t he value of the r/w command bit of the calling address, which is sent from the master. 0 slave receive, master writing to slave 1 slave transmit, master reading from slave. this bit is valid only when both of the following conditions are true: ? a complete transfer occurred and no other transfers have been initiated. ? the i 2 c interface is configured as a slave and has an address match. by checking this bit, the processor can select slave transmit/receive mode according to the command of the master. 4 datasheet u .com
i 2 c interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 11-10 freescale semiconductor 11.3.1.5 i 2 c data register (i2cdr) the i2c data register is shown in figure 11-6 . table 11-8 shows the bit descriptions for i2cdr. 6 mif module interrupt. the mif bit is set when an interr upt is pending, causing a processor interrupt request (provided i2ccr[mien] is set). 0 no interrupt is pending. can be cleared only by software. 1 interrupt is pending. mif is set when one of the following events occurs: ? one byte of data is transferred (set at the falling edge of the 9th clock). ? the value in i2cadr matches with the calling address in slave-receive mode. ? arbitration is lost. 7 rxak received acknowledge. the value of sda during the reception of acknowledge bit of a bus cycle. if the received acknowledge bit (rxak) is low, it indicates that an acknowledge signal has been received after the completion of eight bits of data transmission on the bus. if rxak is high, it means no acknowledge signal has been detected at the 9th clock. 0 acknowledge received 1 no acknowledge received offset 0x010 access: read/write 0 7 r data w reset all zeros figure 11-6. i 2 c data register (i2cdr) table 11-8. i2cdr field descriptions bits name description 0?7 data transmission starts when an address and the r/w bit are written to the data register and the i 2 c interface performs as the master. a data transfer is initiated when data is written to the i2cdr. the most significant bit is sent first in both cases. in master receive mode, re ading the data register allows the read to occur, but also allows the i 2 c module to receive the next byte of data on the i 2 c interface. in slave mode, the same function is available after it is addressed. note that the very first read is always a dummy read. table 11-7. i2csr field descriptions (continued) bits name description 4 datasheet u .com
i 2 c interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 11-11 11.3.1.6 digital filter samplin g rate register (i2cdfsrr) the digital filter sampling rate re gister (i2cdfsrr) is shown in figure 11-7 . refer to application note an2919, ?determining the i2c frequency divider ratio for scl,? for additional guidance regarding the proper use of i2cfdr and i2cdfsrr. table 11-9 shows the field descriptions for i2cdfsrr. 11.4 functional description the i 2 c unit always performs as a slave receiver as a default, unless explicitly progra mmed to be a master or slave transmitter. af ter the boot sequencer has completed (when powered up in boot sequencer mode), the i 2 c interface will perform as a slave receiver. 11.4.1 transaction protocol a standard i 2 c transfer consists of the following: ? start condition ? slave target a ddress transmission ? data transfer ? stop condition figure 11-8 shows the interaction of these four parts with the calling address, data byte, and new calling address components of the i 2 c protocol. the details of the protocol are described in the following sections. offset 0x014 access: read/write 012 7 r dfsr w reset00010000 figure 11-7. i 2 c digital filter sampling rate register (i2cdfsrr) table 11-9. i2cdfsrr field descriptions bits name description 0?1 ? reserved 2?7 dfsr digital filter sampling rate. to assist in filtering out signal noise, the sample rate is programmed. this field is used to prescale the frequency at which t he digital filter takes samples from the i 2 c bus. the resulting sampling rate is calculated by dividing the platform (ccb clock) frequency by the non-zero value of dfsr. 4 datasheet u .com
i 2 c interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 11-12 freescale semiconductor figure 11-8. i 2 c interface transaction protocol 11.4.1.1 start condition when the i 2 c bus is not engaged (bot h sda and scl lines are at logic high), a master can initiate a transfer by sending a start condition. as shown in figure 11-8 , a start condition is de fined as a high-to-low transition of sda while scl is high. this condition de notes the beginning of a new data transfer. each data transfer can contain several bytes and awaken s all slaves. the start condition is initiated by a software write that sets i2ccr[msta]. 11.4.1.2 slave address transmission the first byte of data is transfer red by the master immediately afte r the start condition is the slave address. this is a seven-bit calling address followed by a r/w bit, which indicates the direction of the data being transferred to the slave. e ach slave in the system has a unique address. in addition, when the i 2 c module is operating as a master, it must not transmit an address that is the same as its slave address. an i 2 c device cannot be master and slave at the same time; if this is attempted, the results are boundedly undefined. only the slave with a calling addres s that matches the one transmitted by the master responds by returning an acknowledge bit (pulling the sda signal low at the 9th clock) as shown in figure 11-8 . if no slave acknowledges the address, the master should generate a stop condition or a repeated start condition. when slave addressing is successful (and scl returns to zero), the data transfer can proceed on a byte-to-byte basis in the direction specified by the r/w bit sent by the calling master. the i 2 c module responds to a general call (broadcast) co mmand when i2ccr[bcst] is set. a broadcast address is always zero; however the i 2 c module will not check the r/w bit. the second byte of the broadcast message is the master address. because the second byte is automatically acknowledged by 123456789 12 345678 9 a0 a1 a2 a3 a4 a5 a6 r/w a0 a1 a2 a3 a4 a5 a6 r/w d0 d1 d2 d3 d4 d5 d6 d7 xx xx scl sda start stop no ack read/ write calling address data byte 123456789 123456789 a0 a1 a2 a3 a4 a5 a6 r/w scl sda start stop ack no ack read/ write calling address new calling address repeated start ack 4 datasheet u .com
i 2 c interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 11-13 hardware, the receiver device software must verify that the broadcast message is intended for itself by reading the second byte of the message. if the master address is for another receiver device and the third byte is a write command, software can ignore the third byte during the broa dcast. if the ma ster address is for another receiver device and the third byte is a read command, software mu st write 0xff to i2cdr with i2ccr[txak] = 1, so that it does not interfere with the data written from the addressed device. each data byte is 8 bits l ong. data bits can be changed only while scl is low and must be held stable while scl is high, as shown in figure 11-8 . there is one clock pulse on scl for each data bit, and the most significant bit (msb) is tran smitted first. each byte of data must be followed by an ac knowledge bit, which is signaled from the receiving devi ce by pulling the sda line low at the 9th clock. therefore, one complete data byte transfer takes 9 clock pul ses. several bytes can be transfer red during a data transfer session. if the slave receiver does not acknowledge the master, the sda line must be left high by the slave. the master can then generate a stop condition to abort the data transfer or a start condition (repeated start) to begin a new calling. if the master receiver does not ac knowledge the slave transmitter afte r a byte of transmission, the slave interprets that the end-of-data has been reached. then the slave releases the sda line for the master to generate a stop or a start condition. 11.4.1.3 repeated start condition figure 11-8 shows a repeated start condition, which is generated without a stop condition that can terminate the previous transfer. the master uses this method to communicate with another slave or with the same slave in a different mode (trans mit/receive mode) without releasing the bus. 11.4.1.4 stop condition the master can terminate the tran sfer by generating a stop condition to free the bus. a stop condition is defined as a low-to-high transition of the sda signal while scl is high. for more information, see figure 11-8 . note that a master can generate a stop even if the slave has transmit ted an acknowledge bit, at which point the slave must release the bus. the stop condition is initiated by a software write that clears i2ccr[msta]. as described in section 11.4.1.3, ?repeated start condition,? the master can generate a start condition followed by a calling address without ge nerating a stop condition fo r the previous transfer. this is called a repe ated start condition. 11.4.1.5 protocol implementation details the following sections give deta ils of how aspects of the protoc ol are implemented in this i 2 c module. 11.4.1.5.1 transaction monitori ng?implementation details the different conditions of the i 2 c data transfers are monitored as follows: ? start conditions are detected when an sda fall occurs while scl is high. ? stop conditions are detected when an sda rise occurs while scl is high. 4 datasheet u .com
i 2 c interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 11-14 freescale semiconductor ? data transfers in progress are canceled when a stop condition is detected or if there is a slave address mismatch. cancellation of data tran sactions resets the clock module. ? the bus is detected to be bu sy upon the detection of a start c ondition, and idle upon the detection of a stop condition. 11.4.1.5.2 control transfer?implementation details the i 2 c module contains logic that contro ls the output to the serial data (sda) and serial clock (scl) lines of the i 2 c. the scl output is pulled low as determined by th e internal clock generated in the clock module. the sda output can only change at the midpoint of a low cycle of the scl, unless it is performing a start, stop, or restart condition. otherw ise, the sda output is held constant. the sda signal is pulled low when one or more of the following conditions are true in either master or slave mode: ? master mode ? data bit (transmit) ? ack bit (receive) ? start condition ? stop condition ? restart condition ? slave mode ? acknowledging address match ? data bit (transmit) ? ack bit (receive) the scl signal corresponds to the internal scl signal when one or more of the follow ing conditions are true in either master or slave mode: ? master mode ? bus owner ? lost arbitration ? start condition ? stop condition ? restart condition begin ? restart condition end ? slave mode ? address cycle ? transmit cycle ? ack cycle 4 datasheet u .com
i 2 c interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 11-15 11.4.1.6 address compare? implementation details address compare block determines if a slave has been properly addresse d, either by its slave address or by the general broadcast address (which addresses all slaves). the three performed a ddress comparisons are described as follows: ? whether a broadcast message has been received, to update the i2csr ? whether the module has been addressed as a slave, to update the i2csr and to generate an interrupt ? if the address transmitted by the current ma ster matches the gene ral broadcast address 11.4.2 arbitration procedure the i 2 c interface is a true multiple-master bus that allows more than one master device to be connected on it. if two or more masters simultaneously try to control the bus, each master ?s clock synchronization procedure (including the i 2 c module) determines the bus clock?the low period is equal to the longest clock low period and the high is equal to the shortest one among the ma sters. a bus master loses arbitration if it transmits a logic 1 on sda while another master transmits a logic 0. the losing ma sters immediately switch to slave-receive mode and stop driving the sda line. in this case, the transition from master to slave mode does not generate a stop condition. meanwhile, the i 2 c unit sets the i2csr[mal] status bit to indicate the loss of arbitration and, as a slave, services the transacti on if it is directed to itself. if the i 2 c module is enabled in the middle of an ongoing byt e transfer, the interfac e behaves as follows: ? slave mode?the i 2 c module ignores the curren t transfer on the bus and starts operating whenever a subsequent start c ondition is detected. ? master mode?the i 2 c module cannot tell whether the bus is busy; therefore, if a start condition is initiated, the current bus cycle can be corrupted. this ultimately results in the current bus master of the i 2 c interface losing arbitration, after wh ich bus operations return to normal. 11.4.2.1 arbitration control the arbitration control block controls the arbitration procedure of the ma ster mode. a loss of arbitration occurs whenever the master detect s a 0 on the external sda line whil e attempting to drive a 1, tries to generate a start or restart at an inappropriate time, or detects an unexpected stop request on the line. in master mode, arbitrati on by the master is lost (a nd i2csr[mal] is set) unde r the following conditions: ? sda samples low when the master drives high during an address or data-trans mit cycle (transmit). ? sda samples low when the master drives hi gh during a data-receive cy cle of the acknowledge (ack) bit (receive). ? a start condition is attempted when the bus is busy. ? a repeated start condition is requested in slave mode. ? a start condition is attemp ted when the requesting de vice is not the bus owner ? unexpected stop condition detected note that the i 2 c module does not automatically re try a failed tran sfer attempt. 4 datasheet u .com
i 2 c interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 11-16 freescale semiconductor 11.4.3 handshaking the clock synchronization mechanism can be used as a handshake in data transfer . slave devices can hold scl low after completion of a 1-byte transfer (9 bits). in such cases, it halts the bus clock and forces the master clock into wait states until the slave releases the scl line. 11.4.4 clock control the clock control block handles requests from the cl ock signal for transferring and controlling data for multiple tasks. a 9-cycle data transfer clock is re quested for the following conditions: ? master mode ? transmit slave address after start condition ? transmit slave address after restart condition ? transmit data ? receive data ? slave mode ? transmit data ? receive data ? receive slave address after start or restart condition 11.4.4.1 clock synchronization due to the wire and logic on the scl line, a high-to -low transition on the scl line affects all devices connected on the bus. the devices be gin counting their low period when the master drives the scl line low. after a device has driven scl low, it holds th e scl line low until the clock high state is reached. however, the change of low-to-high in a device clock may not change the state of the scl line if another device is still within its low period. therefore, the synchronized clock signal, scl, is held low by the device with the longest low period. de vices with shorter low periods ente r a high wait state during this time. when all devices concerned have counted off their low period, the synchronized scl line is released and pulled high. then there is no diff erence between the devices? clocks a nd the state of th e scl line, and all the devices begin counting their hi gh periods. the fi rst device to co mplete its high period pulls the scl line low again. 11.4.4.2 input synchronizat ion and digital filter the following sections describes th e synchronizing of the input signals, and the filtering of the scl and sda lines in detail. 11.4.4.2.1 input si gnal synchronization the input synchronization bl ock synchronizes the input scl and sd a signals to the system clock and detects transitions of these signals. 4 datasheet u .com
i 2 c interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 11-17 11.4.4.2.2 filtering of scl and sda lines the scl and sda inputs are filtered to el iminate noise. three consecutive samples of the scl and sda lines are compared to a pre-determined sampling rate. if they are all high, the output of the filter is high. if they are all low, the output is lo w. if they are any combination of hi ghs and lows, the output is whatever the value of the line was in the previous clock cycle. the sampling rate is equal to a bi nary value stored in the frequency register i2cdfsrr . the duration of the sampling cycle is contro lled by a down counter. this allows a software write to the fr equency register to control the filtered sampling rate. 11.4.4.3 clock stretching slaves can use the clock synchronization mechanism to slow down the transfer bi t rate. after the master has driven the scl line low, the slave can drive scl low for the required period and then release it. if the slave scl low period is greater than the master sc l low period, then the resulting scl bus signal low period is stretched. 11.4.5 boot sequencer mode if boot sequencer mode is selected on por (by the settings on the lgpl3 and lgpl 5 reset configuration signals, as described in section 4.4.3.6, ?boot sequencer configuration? ), the i 2 c module communicates with one or more eeproms through the i 2 c interface. the boot se quencer accesses the i 2 c serial rom device at the interf ace frequency designated by the default value of the i2cd fr[dfr] field, 0x2c, which corresponds to a di vider of 1280. see section 11.3.1.2, ?i 2 c frequency divider register (i2cfdr) ,? for additional details of the i2cfdr. the eeprom(s) can be programmed to initialize one or more configuration registers of this integrated device. the boot sequencer mode also supports an extension of the standard i 2 c interface that uses more address bits to allow for eeprom devices that have more th an 256 bytes, and this exte nded addressing mode is selectable during por with a different encoding on th e lgpl3 and lgpl5 reset c onfiguration signals (see section 4.4.3.6, ?boot seque ncer configuration? ). in this mode, only one ee prom device may be used, and the maximum number of registers is limited by the size of the eeprom. if the standard i 2 c interface is used, the i 2 c module addresses the first eeprom, and reads 256 bytes. then it issues a repeated start and addresses the ne xt eeprom address. this sequence continues until the cont bit is cleared. if the last regi ster is not detected befo re wrapping back to the first address, an error condition is detected . in other words, if the cont bit for not cleared on the final 7 bytes, an error condition is detected, causing the devi ce to hang and the hreset_req signal to assert externally. the i 2 c module continues to read from the eeprom as long as the continue (cont) bit is set in the eeprom. the cont bit resides in the ad dress/attributes field that is transfer red from the eeprom, as described in section 11.4.5.1, ?eeprom calling address.? there should be no other i 2 c traffic when the boot sequencer is active. note that as described in section 4.4.3.6, ?boot seque ncer configuration,? the default value for the lgpl3 and lgpl5 reset configuration pi ns is 0b11, which corresponds to the i 2 c boot sequencer being disabled at power-up. 4 datasheet u .com
i 2 c interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 11-18 freescale semiconductor 11.4.5.1 eeprom calling address the MPC8555E uses 0b101_0000 for the eeprom calling address. the first eeprom to be addressed must be programmed to respond to this address, or an error is generated. if mo re eeproms are used, they are addressed in sequential order. 11.4.5.2 eeprom data format the i 2 c module expects that a particular data format be used for data in the eeprom. a preamble should be the first 3 bytes programmed into the eeprom. it should ha ve a value of 0xaa55aa. the i 2 c module checks to ensure that this preamble is correctly detected before proceeding further. following the preamble, there should be a series of configuration registers (known as register preloads) programmed into the eeprom. each configuration register should be programmed according to a particular format, as shown in figure 11-9 . the first 3 bytes hold the attributes and a ddress offset, as follows. the attributes contained are alternate configur ation space (acs), byte enables, and continue (cont). the boot sequencer expects the address offset to be a 32-bit (word) offset, that is, the 2 low-order bits are not included in the boot sequencer co mmand. for example, to access la wbar0 (byte offset of 0x00c08), the boot sequencer addr[0:17] should be set to 0x00302. after the first 3 bytes, 4 bytes of data should hold the desired value of the confi guration register, regardless of the size of the transa ction. byte enables should be asserted fo r any byte that will be written to the configuration register, and they should be asserted contiguously, creating a 1-, 2-, or 4-byte write to a register. the boot sequencer assumes that a big-endian address is stored in th e eeprom. in addition, byte enable bit 0 (bit 1 of the byte) corresponds to the most -significant byte of data (d ata[0:7]), and byte enable bit 3 (bit 4 of the byte) corresponds to the lsb of data (data[24:31]). by setting acs, an alternate config uration space address is prepended to the write request from the boot sequencer. otherwise, ccsrbar is prepended to the eeprom address. if cont is cleared, the first 3 bytes, including acs, the byte enables, and the address, must also be cleared. also, the data contains th e final cyclic redundanc y check (crc). a crc-32 algorithm is used to check the integrity of the data. the polynomial used is: 1 + x 1 + x 2 + x 4 + x 5 + x 7 + x 8 + x 10 + x 11 + x 12 + x 16 + x 22 + x 23 + x 26 + x 32 crc values are calculated using the above polynom ial with a start value of 0xffff_ffff and an xor with 0x0000_0000. the crc should cover all bytes stored in the eeprom prior to the crc. this includes the preamble, all register pr eloads, and the first 3 bytes of th e last 7-byte preload (which should be all zeros). if a preamble or crc fail is dete cted, the device hangs and the external hreset_req signal asserts. if there is a prea mble fail, the boot sequencer may continue to pull i 2 c pins low until a hard reset occurs. 4 datasheet u .com
i 2 c interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 11-19 figure 11-10 shows an example of the eeprom contents, including the preamble, data format, and crc. 01 4 5 6 7 acs byte_en cont addr[0?1] addr[2?9] addr[10?17] data[0?7] data[8?15] data[16?23] data[24?31] figure 11-9. eeprom data format fo r one register preload command 01234567 10101010 preamble 01010101 10101010 acs byte_en 1 addr[0?1] first configuration preload command addr[2?9] addr[10?17] data[0?7] data[8?15] data[16?23] data[24?31] acs byte_en 1 addr[0?1] second configuration preload command addr[2?9] addr[10?17] data[0?7] data[8?15] data[16?23] data[24?31] . . . figure 11-10. eeprom contents 4 datasheet u .com
i 2 c interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 11-20 freescale semiconductor 11.5 initialization/application information this section describes some program ming guidelines recommended for the i 2 c interface. figure 11-11 is a recommended flowchart for i 2 c interrupt service routines. the i 2 c registers in this chapter are shown in big-endian format. if the system is in little-endian mode, software must swap the bytes appropriately. th is appropriate byte sw apping is needed as i 2 c registers are byte registers. also, an msync assembly instruction must be executed after each i 2 c register read/write access to guarantee in-order execution. the i 2 c controller does not guarantee its recovery from all illegal i 2 c bus activity. in addition, a malfunctioning device may hold the bus captive. a good program ming practice is for so ftware to rely on a watchdog timer to help recover from i 2 c bus hangs. the recovery routine should also handle the case when the status bits returned after an interrupt are not consistent with what was expected due to illegal i 2 c bus protocol behavior. 11.5.1 initialization sequence a hard reset initializes all the i 2 c registers to their defa ult states. the following initialization sequence initializes the i 2 c unit: 1. all i 2 c registers must be located in a cache-inhibited page. 2. update i2cfdr[fdr] and select the required division ratio to obt ain the scl frequency from the ccb (platform) clock. note that the platform frequency must first be divided by two; see section 11.3.1.2, ?i 2 c frequency divider register (i2cfdr) ,? for more details. 3. update i2cadr to define the slave address for this device. acs byte_en 1 addr[0?1] last configuration preload command addr[2?9] addr[10?17] data[0?7] data[8?15] data[16?23] data[24?31] 00000000 end command 00000000 00000000 crc[0?7] cyclic redundancy check crc[8?15] crc[16?23] crc[24?31] figure 11-10. eeprom c ontents (continued) 4 datasheet u .com
i 2 c interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 11-21 4. modify i2ccr to select master/slave mode, transmit/receive mode, a nd interrupt-enable or disable. 5. set the i2ccr[men] to enable the i 2 c interface. 11.5.2 generation of start after initialization, the following seque nce can be used to generate start: 1. if the device is connected to a multimaster i 2 c system, test the state of i2csr[mbb] to check whether the serial bus is free (i2csr[m bb] = 0) before switching to master mode. 2. select master mode (set i2ccr[msta]) to transm it serial data and sele ct transmit mode (set i2ccr[mtx]) for the address cycle. 3. write the slave address being called into i2cd r. the data written to i2cdr[0?6] comprises the slave calling address. i2ccr[mtx] indicates the direction of transf er (transmit/receive) required from the slave. the scenario above assumes that the i 2 c interrupt bit (i2csr[mif]) is cl eared. if mif is set at any time, an i 2 c interrupt is generated (provided interrupt reportin g is enabled with i2ccr[mien] =1) so that the i 2 c interrupt handler can handle the interrupt. 11.5.3 post-transfer software response transmission or reception of a byte automatically sets the data tr ansferring bit (i2csr[mcf]), which indicates that one byte ha s been transferred. the i 2 c interrupt bit (i2csr[mif]) is also set and an interrupt is generated to the processor if the interrupt f unction is enabled during the initialization sequence (i2ccr[mien] is set). in the interrupt handler , software must take the following steps: 1. clear i2csr[mif] 2. read the contents of the i 2 c data register (i2cdr) in receive m ode or write to i2cdr in transmit mode. note that this causes i2 csr[mcf] to be cleared. see section 11.5.8, ?interrupt service routine flowchart.? when an interrupt occurs at the end of the address cy cle, the master remains in transmit mode. if master receive mode is required, i2ccr[mtx] must be toggled at this stage. see section 11.5.8, ?interrupt service routine flowchart.? if the interrupt function is disabl ed, software can service the i2cdr in the main program by monitoring i2csr[mif]. in this case, i2csr[mif] must be pol led rather than i2csr[mcf] because mcf behaves differently when arbitration is lost. note that interr upt or other bus conditions ma y be detected before the i 2 c signals have time to settle. thus , when polling i2csr[mif] (or any ot her i2csr bits), software delays may be needed in order to give the i 2 c signals sufficient time to settle. during slave-mode address cycles (i2csr[maas] is set), i2csr[srw] should be read to determine the direction of the subsequent transfer and i2cc r[mtx] should be programmed accordingly. for slave-mode data cycles (maas is cl eared), i2csr[srw] is not valid a nd i2ccr[mtx] must be read to determine the direction of the current transfer. see section 11.5.8, ?interrupt service routine flowchart,? for more details. 4 datasheet u .com
i 2 c interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 11-22 freescale semiconductor 11.5.4 generation of stop a data transfer ends with a stop condition genera ted by the master device. a master transmitter can generate a stop condition after al l the data has been transmitted. if a master receiver wants to te rminate a data transfer, it must inform the slave transmitter by not acknowledging the last byte of data (by setting the transmit acknow ledge bit (i2ccr[txak])) before reading the next-to-last byte of data. at this time, the next-to-last byte of data ha s already been transferred on the i 2 c interface, so the last byte will not receive the data acknowledge (because i2ccr[txak] is set). for 1-byte transfers, a dummy read should be pe rformed by the interrupt service routine (see section 11.5.8, ?interrupt se rvice routine flowchart? ). before the interrupt service routine reads the last byte of data, a stop conditi on must first be generated. the i 2 c controller automatically generates a stop if i2ccr[txak] is set. therefore, i2ccr[txak] must be set before allowing the i 2 c module to receive the last data byte on the i 2 c bus. eventually, i2ccr[txak] needs to be clea red again for subsequent i 2 c transactions. this can be accomplished when setting up the i2ccr for the next transfer. 11.5.5 generation of repeated start at the end of a data transfer, if the master still wants to communicate on the bus, it can generate another start condition followed by another slave address without first gene rating a stop condition. this is accomplished by se tting i2ccr[rsta]. 11.5.6 generation of scl when sda low it is sometimes necessary to force the i 2 c module to become the i 2 c bus master out of reset and drive scl (even though sda may already be driven, which indicates that the bus is busy). this can occur when a system reset does not cause all i 2 c devices to be reset. thus, sda can be dr iven low by another i 2 c device while this i 2 c module is coming out of reset and will stay low indefinitely. the fo llowing procedure can be used to force this i 2 c module to generate scl so that the devi ce driving sda can fi nish its transaction: 1. disable the i 2 c module and set the master bit by setting i2ccr to 0x20 2. enable the i 2 c module by setting i2ccr to 0xa0 3. read the i2cdr 4. return the i 2 c module to slave mode by setting i2ccr to 0x80 11.5.7 slave mode interrupt service routine in the slave interrupt service routine, the module addressed as a slave shoul d be tested to ch eck if a calling of its own address has been received. if i2csr[maas ] is set, software should set the transmit/receive mode select bit (i2ccr[mt x]) according to the r/w command bit (i2csr[srw]). writing to i2ccr clears maas automatically. maas is read as set only in the interrupt handler at the end of that address cycle where an address match occurre d; interrupts resulting from subse quent data transfers clear maas. a data transfer can then be initiated by writing to i2cdr for slave transmits or dummy reading from i2cdr in slave-receive mode. the slave drives scl lo w between byte transfers. sc l is released when the i2cdr is accessed in the required mode. 4 datasheet u .com
i 2 c interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 11-23 11.5.7.1 slave transmitter and received acknowledge in the slave transmitter routine, the received acknowledge bit (i2csr [rxak]) must be tested before sending the next byte of data. the ma ster signals an end-of -data by not acknowledging the data transfer from the slave. when no acknowledge is received (i 2csr[rxak] is set), the slave transmitter interrupt routine must clear i2ccr[mtx] to switch the slave from tr ansmitter to receiver mode. a dummy read of i2cdr then releases scl so that the ma ster can generate a stop condition. see section 11.5.8, ?interrupt service routine flowchart.? 11.5.7.2 loss of arbitration and forcing of slave mode when a master loses arbitration the following conditions all occur: ? i2csr[mal] is set ? i2ccr[msta] is cleared (changing the master to slave mode) ? an interrupt occurs (if enabled) at the fall ing edge of the 9th clock of this transfer thus, the slave interrupt service routine should first te st i2csr[mal] and software should clear it if it is set. see section 11.4.2.1, ?arbit ration control,? for more information. 11.5.8 interrupt service routine flowchart figure 11-11 shows an example algorithm for an i 2 c interrupt service routine. deviation from the flowchart may result in unpredictable i 2 c bus behavior. however, in the slave receive mode (not shown), the interrupt service routine may n eed to set i2ccr[txak] when the ne xt-to-last byte is to be accepted. it is recommended that an msync instruction follow each i 2 c register read or writ e to guarantee in-order instruction execution. 4 datasheet u .com
i 2 c interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 11-24 freescale semiconductor figure 11-11. example i 2 c interrupt service routine flowchart clear i2csr[mif] i2ccr[msta] == 0 == 1 i2csr[mal] i2ccr[mtx] == 1 == 1 == 0 clear i2csr[mal] eoi i2csr[maas] i2csr[srw] set i2ccr[mtx] == 0 clear i2ccr[mtx] write i2cdr dummy read eoi == 1 slave addr. phase slave data cycle i2ccr[mtx] == 1 == 0 slave xmit i2csr[rxak] == 1 == 0 write next byte to i2cdr eoi slave received read i2cdr and store all done y n set i2ccr[txak] read i2cdr (dummy read) y n last byte next-to-last generate read i2cdr and store eoi y n set master rcv stop i2ccr[txak] byte last byte yn i2csr[rxak] == 1 write next byte to i2cdr == 0 eoi generate master xmit stop b == 0 == 1 a == 0 a b i2csr[maas] b == 0 == 1 clear i2ccr[mtx] end of address phase for master receive mode? n only one byte to receive? y y set i2ccr[txak] read i2cdr (dummy read) clear i2ccr[mtx] n 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 12-1 chapter 12 duart this chapter describes the dual universal asynchronous receiver/transmitters (duart). it describes the functional operation, the duart initialization seque nce, and the programming details for the duart registers and features. 12.1 overview the duart consists of two universal asynchronous receiver/transmitters (uarts). the uarts act independently; all references to uart refer to one of these receiver/t ransmitters. each uart is clocked by the core complex bus (ccb) clock. the duart programming model is compatible with the pc16552d. the uart interface is point to point, meaning that only two uart de vices are attached to the connecting signals. as shown in figure 12-1 , each uart module cons ists of the following: ? receive and transmit buffers ? clear to send (cts ) input port and request to send (rts ) output port for data flow control ? 16-bit counter for baud rate generation ? interrupt control logic 12.1.1 features the duart includes these distinctive features: ? full-duplex operation ? programming model compatib le with the original pc 16450 uart and the pc16550d (an improved version of the pc16450 that also operates in fifo mode) ? pc16450 register reset values ? fifo mode for both transmitter a nd receiver, providing 16-byte fifos ? serial data encapsulation and decapsulation with standard asynchro nous communication bits (start, stop, and parity) ? maskable transmit, receive, line status, and modem status interrupts ? software-programmable baud generators that divide the ccb clock by 1 to (2 16 ? 1) and generate a 16x clock for the transmit ter and receiver engines 4 datasheet u .com
duart MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 12-2 freescale semiconductor figure 12-1. uart block diagram ? clear to send (cts ) and ready to send (rts ) modem control functions ? software-selectable serial inte rface data format (data length, pa rity, 1/1.5/2 stop bit, baud rate) ? line and modem status registers ? line-break detection and generation ? internal diagnostic support, lo cal loopback, and break functions ? prioritized interrupt reporting ? overrun, parity, and framing error detection 12.1.2 modes of operation the communication channel provides a full-duplex asynchronous recei ver and transmitter using an operating frequency deri ved from the ccb clock. the transmitter accepts parallel da ta from a write to the transmitter holding register (uthr). in fifo mode, the data is placed directly in to an internal transmitter shift re gister of the transmitter fifo. the transmitter converts the data to a se rial bit stream inserting the appropr iate start, stop, and optional parity bits. finally, it outputs a composite serial data stream on the cha nnel transmitter serial data output signal (sout). the transmitter status ma y be polled or interrupt driven. the receiver accepts serial data bits on the channel re ceiver serial data input si gnal (sin), converts it to parallel format, checks for a start bi t, parity (if any), stop bits, and tr ansfers the assembled character (with start, stop, parity bits re moved) from the receiver buffer (or fifo) in response to a read of the uart?s receiver buffer register (urbr). the receiver status may be polled or interrupt driven. receive buffer input port output port uart module internal bus address bus control data 16-bit counter/ baud rate generator rts sin sout interrupt control logic control transmit buffer cts hreset int ccb_clk 4 datasheet u .com
duart MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 12-3 12.2 external signal descriptions this section contains a signal overvie w and detailed sign al descriptions. 12.2.1 signal overview table 12-1 summarizes the duart signals. note that although the actual device signal names are prepended with the uart_ prefix as shown in the table, the functional (abbr eviated) signal names are often used throughout this chapter. 12.2.2 detailed signal descriptions the duart signals are described in detail in table 12-2 . table 12-1. duart signal overview signal name i/o pins reset value state meaning uart_sin[0:1] i 2 1 serial in data uart0 and uart1 uart_sout[0:1] o 2 1 serial out data uart0 and uart1 uart_cts [0:1] i 2 1 clear to send uart0 and uart1 uart_rts [0:1] o 2 1 request to send uart0 and uart1 table 12-2. duart signals?detailed signal descriptions signal i/o description uart_sin[0:1] i serial data in. data is received on the receivers of uart0 and uart1 through its respective serial data input signal, with the least-significant bit received first. state meaning asserted/negated?represents the data being received on the uart interface. timing assertion/negation?an internal logic sample signal, rxcnt , uses the frequency of the baud-rate generator to sample the data on sin. 4 datasheet u .com
duart MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 12-4 freescale semiconductor 12.3 memory map/register definition table 12-3 lists the duart registers and their offsets. it lists the address, name, and a cross-reference to the complete description of each register. note that the full register address is comprised of ccsrbar together with the block base address and offset listed in table 12-3 . there are two complete sets of duart registers (one for uart0 a nd one for uart1). the two uarts on the device are identical, except that the register s for uart0 are located at offset 0x4500 (local), and the registers for uart1 are located at offset 0x4600 (l ocal). throughout this chapter, the registers are described by a singular acronym: for ex ample, lcr represents the line control register for either uart0 or uart1. the registers in each uart interface are used for conf iguration, control, and status. the divisor latch access bit, ulcr[dlab], is used to access the divisor latch least- a nd most-significant bit registers and the alternate function register. refer to section 12.3.1.7, ?line control re gisters (ulcr0, ulcr1),? for more information on ulcr[dlab]. all the duart registers are one byte wide. reads a nd writes to these regist ers must be byte-wide operations. table 12-3 provides a register summary with referenc es to the section and page that contains detailed information about each register. undefi ned byte address spaces within offset 0x000?0xfff are reserved. in this table and in the register figures and field descriptions, th e following access definitions apply: ? reserved fields are always ignored for the purposes of determining access type. uart_sout[0:1] o serial data out. the serial data output signals for the uart0 and uart1 are set ('mark' condition) when the transmitter is disabled, idle, or operating in the local loopback mode. data is shifted out on these signals, with the least significant bit transmitted first. state meaning asserted/negated?represents the data being transmitted on the respective uart interface. timing assertion/negation? an internal logic sample signal, rxcnt , uses the frequency of the baud-rate generator to update and drive the data on sout. uart_cts [0:1] i clear to send. these active-l ow inputs are the clear-to-send inputs. they are connected to the respective rts outputs of the other uart devices on the bus. they can be programmed to generate an interrupt on change-of-state of the signal. state meaning asserted/negated?represent the clear to send condition for their respective uart. timing assertion/negation?sampled at the rising edge of every ccb clock. uart_rts [0:1] o request to send. uart_rts x are active-low output signals that can be programmed to be automatically negated and asserted by either the receiver or transmitter. when connected to the clear-to-send (cts ) input of a transmitter, this signal can be used to control serial data flow. state meaning asserted/negated?represents the data being transmitted on the respective uart interface. timing assertion/negation?updated and driven at the rising edge of every ccb clock. table 12-2. duart signals?detailed signal descriptions (continued) signal i/o description 4 datasheet u .com
duart MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 12-5 ? r/w, r, and w (read/write, read only, and write only) indicate that all the non-reserved fields in a register have the same access type. ? w1c indicates that all of the non-reserved fields in a register are cleared by writing ones to them. ? mixed indicates a combination of access types. ? special is used when no other cate gory applies. in this case the re gister figure and field description table should be read carefully. table 12-3. duart register summary offset register access reset section/page block base address: 0x0_4000 0x500 urbr?ulcr[dlab] = 0 uart0 receiver buffer register r 0x00 12.3.1.1/12-6 0x500 uthr?ulcr[dlab] = 0 uart0 transmitter holding register w 0x00 12.3.1.2/12-6 0x500 udlb?ulcr[dlab] = 1 uart0 divisor leas t significant byte register r/w 0x00 12.3.1.3/12-7 0x501 uier?ulcr[dlab] = 0 uart0 interrupt enable register r/w 0x00 12.3.1.4/12-9 0x501 udmb?ulcr[dlab] = 1 uart0 divisor most significant byte register r/w 0x00 12.3.1.3/12-7 0x502 uiir?ulcr[dlab] = 0 uart0 interrupt id register r 0x01 12.3.1.5/12-9 0x502 ufcr?ulcr[dlab] = 0 uart0 fifo control register w 0x00 12.3.1.6/12-11 0x502 uafr?ulcr[dlab] = 1 uart0 alternate function register r/w 0x00 12.3.1.12/12-17 0x503 ulcr?ulcr[dlab] = x uart0 line control register r/w 0x00 12.3.1.7/12-12 0x504 umcr?ulcr[dlab] = x uart0 modem control register r/w 0x00 12.3.1.8/12-14 0x505 ulsr?ulcr[dlab] = x uart0 line status register r 0x60 12.3.1.9/12-14 0x506 umsr?ulcr[dlab] = x uart0 modem status register r 0x00 12.3.1.10/12-16 0x507 uscr?ulcr[dlab] = x uart0 scratch register r/w 0x00 12.3.1.11/12-17 0x510 udsr?ulcr[dlab] = x uart0 dma status register r 0x01 12.3.1.13/12-18 0x600 urbr?ulcr[dlab] = 0 uart1 receiver buffer register r 0x00 12.3.1.1/12-6 0x600 uthr?ulcr[dlab] = 0 uart1 transmitter holding register w 0x00 12.3.1.2/12-6 0x600 udlb?ulcr[dlab] = 1 uart1 divisor leas t significant byte register r/w 0x00 12.3.1.3/12-7 0x601 uier?ulcr[dlab] = 0 uart1 interrupt enable register r/w 0x00 12.3.1.4/12-9 0x601 udmb_ulcr[dlab] = 1 uart1 divisor most significant byte register r/w 0x00 12.3.1.3/12-7 0x602 uiir?ulcr[dlab] = 0 uart1 interrupt id register r 0x01 12.3.1.5/12-9 0x602 ufcr?ulcr[dlab] = 0 uart1 fifo control register w 0x00 12.3.1.6/12-11 0x602 uafr?ulcr[dlab] = 1 uart1 alternate function register r/w 0x00 12.3.1.12/12-17 0x603 ulcr?ulcr[dlab] = x uart1 line control register r/w 0x00 12.3.1.7/12-12 0x604 umcr?ulcr[dlab] = x uart1 modem control register r/w 0x00 12.3.1.8/12-14 0x605 ulsr?ulcr[dlab] = x uart1 line status register r 0x60 12.3.1.9/12-14 0x606 umsr?ulcr[dlab] = x uart1 modem status register r 0x00 12.3.1.10/12-16 0x607 uscr?ulcr[dlab] = x uart1 scratch register r/w 0x00 12.3.1.11/12-17 0x610 udsr?ulcr[dlab] = x uart1 dma status register r 0x01 12.3.1.13/12-18 4 datasheet u .com
duart MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 12-6 freescale semiconductor 12.3.1 register descriptions the following sections describe the uart0 and uart1 registers. 12.3.1.1 receiver buffer register s (urbr0, urbr1) (ulcr[dlab] = 0) these registers contain the data received from the transmitter on the uart bus es. in fifo mode, when read, they return the first byte received. for fi fo status information, refer to the udsr[rxrdy] description. except for the case when there is an overrun, urbr returns the data in the order it was received from the transmitter. refer to the ulsr[oe] description, section 12.3.1.9, ?line status registers (ulsr0, ulsr1).? figure 12-3 shows the receiver buffer regist ers. note that these register s have same offset as the uthrs. figure 12-2 shows the bits in the urbrs. table 12-4 describes the fields of urbr. 12.3.1.2 transmitter holding registers (uthr0, uthr1) (ulcr[dlab] = 0) a write to these 8-bit registers cause s the uart devices to transfer 5?8 data bits on the uart bus in the format set up in the ulcr (line control register). in fifo mode, data written to uthr is placed into the fifo. the data written to uthr is the data sent onto the uart bus, and the fi rst byte written to uthr will be the first byte onto the bus. udsr[txrdy ] indicates when the fifo is full. refer to the table 12-21 and the table 12-22 for more details. offset 0x500 0x600 access: read only 0 7 r w reset all zeros figure 12-2. receiv er buffer regist ers (urbr0, urbr1) table 12-4. urbr fi eld descriptions bits name description 0?7 data data received from the transmitter on the uart bus (read only) 4 datasheet u .com
duart MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 12-7 figure 12-3 shows the bits in the uthrs. table 12-5 describes the fields of uthr. 12.3.1.3 divisor most and least signi ficant byte registers (udmb and udlb) (ulcr[dlab] = 1) the divisor least significant byte register (udlb) is c oncatenated with the divisor most significant byte register (udmb) to create the divi sor used to divide the input cloc k into the duart. the output frequency of the baud generator is 16 times the baud rate; therefore the de sired baud rate = plat form clock frequency / (16 [udmb||udlb]). equivalently , [udmb||udlb:0b0000] = platform clock frequency / desired baud rate. baud rates that can be generated by sp ecific input clock frequencies are shown in table 12-8 . figure 12-4 shows the bits in the udmbs. table 12-6 describes the fields of udmb registers. offset 0x500 0x600 access: write only 0 7 r w reset all zeros figure 12-3. transmitter holding registers (uthr0, uthr1) table 12-5. uthr field descriptions bits name description 0?7 data data that is written to uthr (write only) offset 0x501 0x601 access: read/write 0 7 r udmb w reset all zeros figure 12-4. divisor most significant byte registers (udmb0, udmb1) table 12-6. udmb field descriptions bits name description 0?7 udmb divisor most-significant byte 4 datasheet u .com
duart MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 12-8 freescale semiconductor figure 12-5 shows the bits in the udlbs. table 12-7 describes the fields of udlb registers. table 12-8 shows baud rate when the input clock is at certain frequencies. note that because only integer values can be used as divisors, the actual baud rate differs sl ightly from the desired (target) baud rate; for this reason, both target and actual baud rates are given, along with the percentage of error. offset 0x500 0x600 access: read/write 0 7 r udlb w reset all zeros figure 12-5. divisor leas t significant byte registers (udlb0, udlb1) table 12-7. udlb field descriptions bits name description 0?7 udlb divisor least-significant by te. this is concatenated with udmb. table 12-8. baud rate examples target baud rate (decimal) divisor input clock (ccb) frequency (mhz) actual baud rate (decimal) percent error (decimal) decimal hex 9,600 1736 6c8 266 9600.61444 0.0064 19,200 868 364 266 19,201.22888 0.0064 38,400 434 1b2 266 38,402.45776 0.0064 56,000 298 12a 266 55,928.41163 0.1280 128,000 130 82 266 128,205.12821 0.1600 256,000 65 41 266 256,410.25641 0.1600 9,600 2170 87a 333 9600.61444 0.0064 19,200 1085 43d 333 19,201.22888 0.0064 38,400 543 21f 333 38,367.09638 0.0858 56,000 372 174 333 56,003.58423 0.0064 128,000 163 a3 333 127,811.86094 0.1472 256,000 81 51 333 257,201.64609 0.4672 4 datasheet u .com
duart MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 12-9 12.3.1.4 interrupt enable regi ster (uier) (ulcr[dlab] = 0) the uier gives the user the ability to mask sp ecific uart interrupts to the MPC8555E programmable interrupt controller (pic). figure 12-6 shows the bits in the uier. table 12-9 describes the fields of uier. 12.3.1.5 interrupt id registers (uiir0, uiir1) (ulcr[dlab] = 0) the uiirs indicate when an interrupt is pending from the corresponding uart and what type of interrupt is active. they also indicate if the fifos are enabled. the duart prioritizes interrupts into four levels and records these in the corresponding uiir. the four levels of interrupt conditions in order of priority are: 1. receiver line status 2. received data rea dy/character time-out 3. transmitter holding register empty offset 0x501, 0x601 access: read/write 0 34567 r ? emsi erlsi ethrei erdai w reset all zeros figure 12-6. interrupt enable register (uier) table 12-9. uier field descriptions bits name description 0?3 ? reserved. 4 emsi enable modem status interrupt. 0 mask interrupts caused by umsr[dcts] being set 1 enable and assert interrupts when the clear-to-send bit in the uart modem status register (umsr) changes state 5 erlsi enable receiver line status interrupt. 0 mask interrupts when ulsr?s overrun, parity error, framing error or break interrupt bits are set 1 enable and assert interrupts when ulsr?s overrun, parity error, framing error or break interrupt bits are set 6 ethrei enable transmitter holding register empty interrupt. 0 mask interrupt when ulsr[thre] is set 1 enable and assert interrupts when ulsr[thre] is set 7 erdai enable received data available interrupt. 0 mask interrupt when new receive data is available or receive data time out has occurred 1 enable and assert interrupts when a new data character is received from the external device and/or a time-out interrupt occurs in the fifo mode 4 datasheet u .com
duart MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 12-10 freescale semiconductor 4. modem status see table 12-11 for more details. when the uiir is read, the associated duart seri al channel freezes all interrupts and indicates the highest priority pending interrupt. while this read tr ansaction is occurring, the associated duart serial channel records new inte rrupts, but does not change the contents of uiir until the read access is complete. figure 12-7 shows the bits in the uiir. table 12-10 describes the fiel ds of the uiir. the bits contained in the uiir registers are described in table 12-11 . offset 0x502 0x602 access: read only 0 1234567 rfe ? iid3 iid2 iid1 iid0 w reset 0 0 0 0 0 0 0 1 figure 12-7. interrupt id registers (uiir) table 12-10. uiir field descriptions bits name description 0?1 fe fifos enabled. reflects the setting of ufcr[fen] 2?3 ? reserved 4 iid3 interrupt id bits identify the highest priori ty interrupt that is pending as indicated in table 12-11 . iid3 is set along with iid2 only when a timeout interrupt is pending for fifo mode. 5?6 iid2?1 interrupt id bits identify the highest prio rity interrupt that is pending as indicated in table 12-11 . 7 iid0 iid0 indicates when an interrupt is pending. 0 the uart has an active interrupt ready to be serviced. 1 no interrupt is pending. table 12-11. uiir iid bits summary iid bits iid[3?0] priority level interrupt type interrupt descri ption how to reset interrupt 0b0001 ? ? ? ? 0b0110 highest receiver line status overrun error, parity error, framing error, or break interrupt read the line status register. 0b0100 second received data available receiver data available or trigger level reached in fifo mode read the receiver buffer register or interrupt is automatically reset if the number of bytes in the receiver fifo drops below the trigger level. 4 datasheet u .com
duart MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 12-11 12.3.1.6 fifo control register s (ufcr0, ufcr1) (ulcr[dlab] = 0) the ufcr, a write-only register, is used to enable and clear the receiver and transmitter fifos, set a receiver fifo trigger level to cont rol the received data available inte rrupt, and select the type of dma signaling. when the ufcr bits are written, the fifo enable bit must also be set or else the ufcr bits are not programmed. when changing from fifo mode to 16450 mode (non-fifo m ode) and vice versa, data is automatically cleared from the fifos. after all the bytes in the receiver fifo are cleared, the receiver internal shif t register is not cleared. similarly, the bytes are cleared in the transmitter fifo , but the transmitter internal shift register is not cleared. both tfr and rfr are self-clearing bits. figure 12-8 shows the bits in the ufcrs. table 12-12 describes the fields of the ufcrs. 0b1100 second character time-out no characters have been removed from or input to the receiver fifo during the last 4 character times and there is at least one character in the receiver fifo during this time. read the receiver buffer register. 0b0010 third uthr empty transmitter holding register is empty read the uiir or write to the uthr. 0b0000 fourth modem status cts input value changed since last read of umsr read the umsr. offset 0x502 0x602 access: write only 0 1234567 r ? w rtl dms tfr rfr fen reset all zeros figure 12-8. fifo control registers (ufcr0, ufcr1) table 12-12. ufcr field descriptions bits name description 0?1 rtl receiver trigger level. a received data available interrupt occurs when uier[erdai] is set and the number of bytes in the receiver fifo equals the designated interrupt trigger level as follows: 00 1 byte 01 4 bytes 10 8 bytes 11 14 bytes 2?3 ? reserved table 12-11. uiir iid bits summary (continued) iid bits iid[3?0] priority level interrupt type interrupt descri ption how to reset interrupt 4 datasheet u .com
duart MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 12-12 freescale semiconductor 12.3.1.7 line control registers (ulcr0, ulcr1) the ulcrs specify the data format for the uart bus and set the divisor latc h access bit ulcr[dlab], which controls the ability to access the divisor latch least and most signi ficant bit registers and the alternate function register. after initializing the ulcr, the soft ware should not re-write the ulcr when valid transfers on the uart bus are active. the software should not re-write th e ulcr until the last stop bit has been received and there are no new characters be ing transferred on the bus. the stick parity bit, ulcr[sp] , assigns a set parity value for the pari ty bit time slot se nt on the uart bus. the set value is defined as mark parity (logic 1) or space parity (logic 0). ulcr[pen] and ulcr[eps] help determine the set parity value. see table 12-14 for more information. ulcr[nstb], defines the number of stop bits to be sent at the end of the data transfer. the receiver only checks the first stop bit, regardless of the number of stop bits selected. the word length select bits (1 and 0) define the number of data bits that are tran smitted or received as a serial characte r. the word length does not include start, parity, and stop bits. figure 12-9 shows the bits in the ulcrs. 4 dms dma mode select. see section 12.4.5.2, ?dma mode select,? for more information. 0 udsr[rxrdy] and udsr[txrdy] bits are in mode 0. 1 udsr[rxrdy] and udsr[txrdy] bits are in mode 1 if ufcr[fen] = 1. 5 tfr transmitter fifo reset 0 no action 1 clears all bytes in the transmitter fifo a nd resets the fifo co unter/pointer to 0 6 rfr receiver fifo reset 0 no action 1 clears all bytes in the receiver fifo an d resets the fifo counter/pointer to 0 7 fen fifo enable 0 fifos are disabled and cleared 1 enables the transmitter and receiver fifos offset 0x503 0x603 access: read/write 0 1234567 r dlab sb sp eps pen nstb wls w reset all zeros figure 12-9. line control register (ulcr) table 12-12. ufcr field descriptions (continued) bits name description 4 datasheet u .com
duart MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 12-13 table 12-13 describes the fields of the ulcrs. table 12-13. ulcr field descriptions bits name description 0 dlab divisor latch access bit. 0 access to all registers e xcept udlb, uafr, and udmb 1 ability to access divisor la tch least and most significant byte regi sters and alternate function register (uafr) 1 sb set break. 0 send normal uthr data onto the serial output (sout) signal 1 force logic 0 to be on the sout signal. data in the uthr is not affected 2 sp stick parity. 0 stick parity is disabled. 1 if pen = 1 and eps = 1, space parity is selected. and if pen = 1 and ep s = 0, mark parity is selected. 3 eps even parity select. see table 12-14 for more information. 0 if pen = 1 and sp = 0, odd parity is selected. 1 if pen = 1 and sp = 0, even parity is selected. 4 pen parity enable. 0 no parity generation and checking 1 generate parity bit as a transmitter, and check parity as a receiver 5 ntsb number of stop bits. 0 one stop bit is generated in the transmitted data. 1 when a 5-bit data length is selected, 1 stop bits are generated. when either a 6-, 7-, or 8-bit word length is selected, two stop bits are generated. 6?7 wls word length select. number of bits that comprise th e character length. the word length select values are as follows: 00 5 bits 01 6 bits 10 7 bits 11 8 bits table 12-14. parity sel ection using ulcr[pen], ulcr[sp], and ulcr[eps] pen sp eps parity selected 000 no parity 001 no parity 010 no parity 011 no parity 1 0 0 odd parity 101 even parity 110 mark parity 1 1 1 space parity 4 datasheet u .com
duart MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 12-14 freescale semiconductor 12.3.1.8 modem control registers (umcr0, umcr1) the umcrs control the interface with the ex ternal peripheral devi ce on the uart bus. figure 12-10 shows the bits in the umcrs table 12-15 describes the fields of umcrs. . 12.3.1.9 line status registers (ulsr0, ulsr1) the ulsrs are read-only registers that monitor the st atus of the data transfer on the uart buses. to isolate the status bits from the proper character received through the uart bus, software should read the ulsr and then the urbr. offset 0x504 0x604 access: read/write 0 234567 r ?loop?rts? w reset all zeros figure 12-10. modem control register (umcr) table 12-15. umcr field descriptions bits name description 0?2 ? reserved. 3 loop local loopback mode. 0 normal operation 1 functionally, the data written to uthr can be read from urbr of the same uart, and umcr[rts] is tied to umsr[cts]. 4?5 ? reserved. 6 rts ready to send. 0 negates corresponding uart_ rts output 1 assert corresponding uart_ rts output. informs external modem or pe ripheral that the uart is ready for sending/receiving data 7 ? reserved. 4 datasheet u .com
duart MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 12-15 figure 12-11 shows the bits in the ulsrs. table 12-16 describes the fiel ds of the ulsrs. offset 0x505 0x605 access: read only 0 1234567 r rfe temt thre bi fe pe oe dr w reset 0 1 1 0 0 0 0 0 figure 12-11. line status register (ulsr) table 12-16. ulsr field descriptions bits name description 0 rfe receiver fifo error. 0 this bit is cleared when there are no errors in the re ceiver fifo or on a read of the ulsr with no remaining receiver fifo errors. 1 set to one when one of the characters in the receiver fifo encounters an error (framing, parity, or break interrupt) 1 temt transmitter empty. 0 either or both the uthr or the internal transmitter shift register has a data character. in fifo mode, a data character is in the transmitter fifo or the internal transmitter shift register. 1 both the uthr and the internal transmitter shift register are empty. in fifo mode, both the transmitter fifo and the internal transmitter shift register are empty. 2 thre transmitter holding register empty. 0 the uthr is not empty. 1 a data character has transferred from the uthr into the internal transmitter shift r egister. in fifo mode, the transmitter fifo contains no data character. 3 bi break interrupt. 0 this bit is cleared when the ulsr is read or when a vali d data transfer is detected (tha t is, stop bit is received). 1 received data of logic 0 for more than start bit + data bits + parity bit + one stop bits length of time. a break condition is expected to last at least two character le ngths and a new character is not loaded until sin returns to the mark state (logic 1) and a valid start is detected . in fifo mode, a zero character is encountered in the fifo (the zero character is at the t op of the fifo). in fifo mode, only one zero character is stored. note that the ulsr[bi] is set immediately after ulsr is read if bus remains zero and no mark state followed by a valid new character has been detected. 4 fe framing error. 0 this bit is cleared when ulsr is read or when a new character is loaded into the urbr from the receiver shift register. 1 invalid stop bit for receive data (only the first stop bi t is checked). in fifo mode , this bit is set when the character that detected a framing error is encountered in the fifo (that is the characte r at the top of the fifo). an attempt to resynchronize occurs after a framing erro r. the uart assumes that the framing error (due to a logic 0 being read when a logic 1 (stop) was expected) was due to a stop bit overlapping with the next start bit, so it assumes this logic 0 sample is a true start bit and then will receive the following new data. 5 pe parity error. 0 this bit is cleared when ulsr is read or when a new character is loaded into the urbr. 1 unexpected parity value encountered w hen receiving data. in fifo mode, the character with the error is at the top of the fifo. 4 datasheet u .com
duart MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 12-16 freescale semiconductor 12.3.1.10 modem status registers (umsr0, umsr1) the umsrs track the status of the modem (or external peripheral devi ce) clear to send (cts ) signal for the corresponding uart. figure 12-12 shows the bits in the umsrs. table 12-17 describes the fiel ds of the umsrs. 6 oe overrun error. 0 this bit is cleared when ulsr is read. 1 before the urbr is read, the urbr was overwritten with a new character. the old character is loss. in fifo mode, the receiver fifo is full (regardless of the receiv er fifo trigger level setting) and a new character has been received into the internal receiver shift register. the old character was overwritten by the new character. data in the receiver fifo was not overwritten. 7 dr data ready. 0 this bit is cleared when urbr is read or when all of the data in the receiver fifo is read. 1 a character has been received in the urbr or the receiver fifo. offset 0x506 0x606 access: read only 023467 r ? cts ? dcts w reset all zeros figure 12-12. modem status register (umsr) table 12-17. umsr field descriptions bits name description 0?2 ? reserved. 3 cts clear to send. represents the inverted value of the cts input pin from the external peripheral device 0 corresponding cts n is negated 1 corresponding cts n is asserted. the modem or peripheral device is ready for data transfers. 4?6 ? reserved. 7 dcts clear to send. 0 no change on the corresponding cts n signal since the last read of umsr[cts] 1 the cts n value has changed, since the last read of umsr[c ts]. causes an interrupt if uier[emsi] is set to detect this condition table 12-16. ulsr field descriptions (continued) bits name description 4 datasheet u .com
duart MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 12-17 12.3.1.11 scratch regi sters (uscr0, uscr1) the uscr registers are for debugging software or the duart hardware. the uscrs do not affect the operation of the duart. figure 12-13 shows the bits in uscrs. table 12-18 describes the fields of the uscrs. 12.3.1.12 alternate function registers (uafr0, uafr1) (ulcr[dlab] = 1) the uafrs give software the ability to write to both uart0 and uart1 registers simultaneously with the same write operation. the uafrs also provide a m eans for the device's performance monitor to track the baud clock. figure 12-14 shows the bits in the uafrs. table 12-19 describes the fiel ds of the uafrs. offset 0x507 0x607 access: read/write 0 7 r data w reset all zeros figure 12-13. scratch register (uscr) table 12-18. uscr field descriptions bits name description 0?7 data data offset 0x502 0x602 access: read/write 0 567 r ?bocw w reset all zeros figure 12-14. alternate function register (uafr) table 12-19. uafr field descriptions bits name description 0?5 ? reserved. 4 datasheet u .com
duart MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 12-18 freescale semiconductor 12.3.1.13 dma status re gisters (udsr0, udsr1) the dma status registers (udsrs) are read-only registers that return tran smitter and receiver fifo status. udsrs also provide the ability to assist dma data operations to and from the fifos. figure 12-15 shows the bits in udsrs. table 12-20 describes the fiel ds of the udsrs. 6 bo baud clock select. 0 the baud clock is not gated off. 1 the baud clock is gated off. 7 cw concurrent write enable. 0 disables writing to both uart0 and uart1 1 enables concurrent writes to corresponding uart registers. a write to a register in uart0 is also a write to the corresponding register in uart1 and vice vers a. the user needs to ensure that the lcr[dlab] of both uarts are in the same state before executing a co ncurrent write to register addresses 0x500, 0x501 and 0x502. offset 0x510 0x610 access: read only 0 567 r ? txrdy rxrdy w reset 0 0 0 0 0 0 0 1 figure 12-15. dma stat us register (udsr) table 12-20. udsr field descriptions bits name description 0?5 ? reserved 6 txrdy transmitter ready. this read-only bit reflects the st atus of the transmitter fifo or the uthr. the status depends on the dma mode selected, which is det ermined by the dms and fen bits in the ufcr. 0 the bit is cleared, as shown in table 12-22 . 1 this bit is set, as shown in ta b l e 1 2 - 2 1 . 7 rxrdy receiver ready. this read-only bit reflects the status of the receiver fifo or urbr. the status depends on the dma mode selected, which is determined by the dms and fen bits in the ufcr. 0 the bit is cleared, as shown in table 12-24 . 1 this bit is set, as shown in ta b l e 1 2 - 2 3 . table 12-19. uafr field d escriptions (continued) bits name description 4 datasheet u .com
duart MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 12-19 12.4 functional description the communication channel provides a full-duplex asynchronous recei ver and transmitter using an operating frequency derived from the ccb clock signal. the transmitter accepts parallel da ta with a write access to the transm itter holding register (uthr). in fifo mode, the data is placed directly into an intern al transmitter shift register , or into the transmitter fifo?see section 12.4.5, ?fifo mode.? the transmitting registers convert the data to a serial bit stream, by inserting the appropriate start, stop, and opti onal parity bits. finally, the registers output a table 12-21. udsr[txrdy] set conditions dms fen dma mode meaning 0 0 0 txrdy is set after the first character is loaded into the transmitter fifo or uthr. 01 0 10 0 1 1 1 txrdy is set when the transmitter fifo is full. table 12-22. udsr[txrdy] cleared conditions dms fen dma mode meaning 0 0 0 txrdy is cleared when there are no characters in the transmitter fifo or uthr. 01 0 10 0 1 1 1 txrdy is cleared when there are no charac ters in the transmitter fifo or uthr. txrdy remains clear when the transm itter fifo is not yet full. table 12-23. udsr[rxrdy] set conditions dms fen dma mode meaning 0 0 0 rxrdy is set when there are no characters in the receiver fifo or urbr. 01 0 10 0 1 1 1 rxrdy is set when the trigger level has not been reached and there has been no time out. table 12-24. udsr[rxrdy] cleared dms fen dma mode meaning 0 0 0 rxrdy is cleared when there is at least one character in the receiver fifo or urbr. 01 0 10 0 1 1 1 rxrdy is cleared when the trigger level or a time-out has been reached. rxrdy remains cleared until the receiver fifo is empty. 4 datasheet u .com
duart MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 12-20 freescale semiconductor composite serial data str eam on the channel transmitter serial data output (sout). the transmitter status may be polled or interrupt-driven. the receiver accepts serial data on the channel receiver serial data input (sin), converts the data into parallel format, and checks for start, stop, and pari ty bits. in fifo mode, the receiver removes the start, stop, and parity bits and then transfers th e assembled character from the receiver buffer, or receiver fifo. this transfer occurs in response to a read of the ua rt receiver buffer register (urbr). the receiver status may be polled or interrupt driven. 12.4.1 serial interface the uart bus is a serial, full-duple x, point-to-point bus as shown in figure 12-16 . therefore, only two devices are attached to the same signals and there is no need for address or arbitration bus cycles. figure 12-16. uart bus interface transaction protocol example a standard uart bus transfer is compos ed of either three or four parts: ? start bit ? data transfer bits (lea st-significant bit is fi rst data bit on the bus) ? parity bit (optional) ?stop bits an internal logic sample signal, rxcnt , uses the frequency of the baud-rate generator to drive the bits on sout. the following sections describe the four components of the serial interf ace, the baud-rate generator, local loopback mode, different errors, and fifo mode. 12.4.1.1 start bit a write to the transmitter holding register (uth r) generates a start bit on the sout signal. figure 12-16 shows that the start bit is defined as a logic 0. the start bit denotes the beginning of a new data transfer which is limited to the bit le ngth programmed in the uart line control register (ulcr).when the bus is idle, sout is high. 123456789 1 23456789 d6 d5 d4 d3 d2 d1 d0 pty d6 d5 d4 d3 d2 d1 d0 pty rxcnt sout1 stop bits optional data bits data bits stop bits 10 10 two 7-bit data transmissions with parity and 2-bit stop transactions even/odd parity start optional even/odd parity start 4 datasheet u .com
duart MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 12-21 12.4.1.2 data transfer each data transfer contains 5?8 bits of data. the ul cr data bit length for the transmitter and receiver uart devices must agree before a tr ansfer begins; otherwise, a parity or framing error may occur. a transfer begins when uthr is writ ten. at that time a start bit is generated followed by 5?8 of the data bits previously written to the uthr . the data bits are driven from the least significant to the most significant bits. after the parity and stop bits, a ne w data transfer can begin if new data is written to the uthr. 12.4.1.3 parity bit the user has the option of using eve n, odd, no parity, or stick parity (see section 12.3.1.7, ?line control registers (ulcr0, ulcr1).? both the receiver and transmitter pa rity definition must agree before attempting to transfer data. when receiving data a pari ty error can occur if an unexpected parity value is detected. (see section 12.3.1.9, ?line status registers (ulsr0, ulsr1).? ) 12.4.1.4 stop bit the transmitter device ends the write transfer by generating a stop bit. the stop bit is always high. the user can program the length of the stop bit(s) in the ulcr. both the receiver and tr ansmitter stop bit length must agree before attempting to transfer data. a framing error can occur if an invalid stop bit is detected. 12.4.2 baud-rate generator logic each uart contains an independent programmable baud-rate generator, that is capable of taking the ccb clock input and dividing the input by any divisor from 1 to 2 16 ?1. the baud rate is defined as the num ber of bits per second that can be sent over the uart bus. the formula for calculating baud rate is as follows: baud rate = (1/16) (ccb clock frequency/divisor value) therefore, the output frequency of the baud -rate generator is 16 times the baud rate. the divisor value is determined by the following tw o 8-bit registers to form a 16-bit binary number: ? uart divisor most significa nt byte register (udmb) ? uart divisor least significa nt byte register (udlb) upon loading either of the divisor latches, a 16-bit baud-rate counter is loaded. the divisor latches must be loaded during initiali zation to ensure proper ope ration of the baud-rate generator. both uart devices on th e same bus must be pr ogrammed for the same ba ud-rate before starting a transfer. the baud clock can be passed to the performance monitor by enabling the ua fr[bo] bit. this can be used to determine baud rate errors. 4 datasheet u .com
duart MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 12-22 freescale semiconductor 12.4.3 local loopback mode local loopback mode is provided for diagnostic testing. the data written to uthr can be read from the receiver buffer register (urbr) of th e same uart. in this mode, the modem control register umcr[rts] is internally tied to the modem st atus register umsr[cts]. the transm itter sout is set to a logic 1 and the receiver sin is di sconnected. the output of the tran smitter shift register is l ooped back into the receiver shift register input. the cts (input signal) is disconnected, rts is internally connected to cts , and the rts (output signal) becomes inactive. in this diagnostic mode, data that is transmitted is immediately received. in local loopback mode the transmit and receive data paths of the duart can be verified. note that in local loopback mode, the tr ansmit/receive interrupts are fully ope rational and can be controlled by the interrupt enable register (uier). 12.4.4 errors the following sections describe framing, parity, and overrun errors which may occur while data is transferred on the uart bus. each of the error bits are usuall y cleared, as described below, when the line status register (ulsr) is read. 12.4.4.1 framing error when an invalid stop bit is detecte d, a framing error occurs and ulsr[fe] is set. note that only the first stop bit is checked. in fifo mode, ulsr[fe] is set when the character at the top of the fifo detects a framing error. an attempt to re-synchronize occurs after a framing error. the uart assumes that the framing error (due to a logic 0 being read when a logic 1 (stop) was expected) was due to a stop bit overlapping with the next start bit. ulsr[fe] is cleared when ulsr is read or when a new character is loaded into the urbr from the receiver shift register. 12.4.4.2 parity error a parity error occurs, and ulsr[p e] is set, when unexpected pari ty values are encountered while receiving data. in fifo mode, ulsr[pe] is set when the character with the error is at the top of the fifo. ulsr[pe] is cleared when ulsr is read or when a new character is loaded into the urbr. 12.4.4.3 overrun error when a new (overwriting character) stop bit is detect ed and the old character is lost, an overrun error occurs and ulsr[oe] is set. in fi fo mode, ulsr[oe] is se t after the receiver fifo is full (despite the receiver fifo trigger level setting) and a new character has been received into the internal receiver shift register. data in the fifo is not overwritten; only the shift register da ta is overwritten. therefore, the interrupt occurs immediately. ulsr[o e] is cleared when ulsr is read. 12.4.5 fifo mode the uarts use an alternate mode (fifo mode) to re lieve the processor core from excessive software overhead. the fifo control register (u fcr) is used to enable and clea r the receiver and transmitter fifos 4 datasheet u .com
duart MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 12-23 and set the fifo receiver trigger level ufcr[rtl] to control the r eceived data available interrupt uier[erdai]. the ufcr also selects the type of dma signali ng. the udsr[rxrdy] indicates the status of the receiver fifo. the dma status regi sters (udsr[txrdy]) indicate when the transmitter fifo is full. when in fifo mode, data written to uthr is placed into the transmitter fifo. the first byte written to uthr is the first byte onto the uart bus. 12.4.5.1 fifo interrupts in fifo mode, the uier[erdai] is set when a time- out interrupt occurs. when a receive data time-out occurs there is a maskable interr upt condition (through uier[erdai]). see section 12.3.1.4, ?interrupt enable register (uier) (ulcr[dlab] = 0),? for more details on interrupt enables. the interrupt id register (uiir) i ndicates if the fifos are enabled. in terrupt id3 uiir[iid3] bit is only set for fifo mode interrupts. the character time-o ut interrupt occurs when no characters have been removed from or input to the receive r fifo during the last four characte r times and there is at least one character in the receiver fifo during this time. the character time-out interrupt (controlled by uiir[iid]) is cleared when the urbr is read. see section 12.3.1.5, ?interrupt id registers (uiir0, uiir1) (ulcr[dlab] = 0),? for more information. the uiir[fe] bits indicate if fifo mode is enabled. 12.4.5.2 dma mode select the udsr[rxrdy] bit reflects the status of the re ceiver fifo or urbr. in mode 0 (ufcr[dms] is cleared), udsr[rxrdy] is cleared when there is at least one character in the receiver fifo or urbr and it is set when there are no more characters in the receiver fifo or urbr. this occurs regardless of the setting of the ufcr[fen] bit. in mode 1 (ufcr[dms] and ufcr[fen ] are set), udsr[rxrdy] is cleared when the trigger level or a time-out has been reached an d it is set when there are no more characters in the receiver fifo. the udsr[txrdy] bit reflects the status of the tran smitter fifo or uthr. in mode 0 (ufcr[dms] is cleared), udsr[txrdy] is cleared when there are no ch aracters in the transmitter fifo or uthr and it is set after the first character is loaded into the transmitter fifo or uthr. this occurs regardless of the setting of the ufcr[fen] bit. in mode 1 (ufcr[dms] and ufcr [fen] are set), udsr[txrdy] is cleared when there are no characters in the transmitter fifo or uthr and it is set when the transmitter fifo is full. see section 12.3.1.13, ?dma status re gisters (udsr0, udsr1),? for a complete description of the usdr[rxrdy] and usdr[txrdy] bits. 12.4.5.3 interrupt control logic an interrupt is active when duart interrupt id regist er bit 0 (uiir[0]), is cl eared. the interrupt enable register (uier) is used to mask specific interrupt t ypes. for more details refer to the description of uier in section 12.3.1.4, ?interrupt enable re gister (uier) (ulcr[dlab] = 0).? 4 datasheet u .com
duart MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 12-24 freescale semiconductor when the interrupts are disabled in uier, polling software can not use uiir[0] to determine whether the uart is ready for service. the software must monitor th e appropriate bits in the line status (ulsr) and/or the modem status (umsr) registers. uiir[0] can be used for polling if the interrupts are enabled in uier. 12.5 duart initialization/application information the following requirements must be met for duart accesses: ? all duart registers must be mapped to a cache -inhibited and guarded area. (that is, the wimg setting in the mmu needs to be 0b01x1.) ? all duart registers are 1 byte wide. reads and writes to these registers must be byte-wide operations. a system reset puts the duart registers to a default st ate. before the interface can transfer serial data, the following initializati on steps are recommended: 1. update the programmable interrupt controller (pic) duart channel interrupt vector source registers. 2. set data attributes and control bits in the ulcr, ufcr, uafr, umcr, udlb, and udmb. 3. set the data attributes and control bits of the external modem or peripheral device. 4. set the interrupt enable register (uier). 5. to start a write transfer, write to the uthr. 6. poll uiir if the interrupts ge nerated by the duart are masked. 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-1 chapter 13 local bus controller this chapter describes the local bus controller (lbc) block. it describes the external signals and the memory-mapped registers as well as a functional desc ription of the general-pur pose chip-select machine (gpcm), sdram machine, and user-p rogrammable machines (upms) of the lbc. finally, it includes an initialization and applications information sect ion with many specific examples of its use. 13.1 introduction figure 13-1 is a functional block diagram of the lbc, which supports thre e interfaces: gpcm, upm, and sdram controller. figure 13-1. local bus c ontroller block diagram upm ctrl gpcm sdram memory controller address and data machine banks and config regs upm ram transfer acknowledge local address local data refresh timers/ counters local memory compare control signal timing generator gpcm ctrl loe lgta lbctl upm ctrl lgpl[0:3] lgpl4/lupwait lgpl5 sdram ctrl lsda10 lsdwe lsdras lsdcas lcs [0:7] lwe [0:3] lsddqm [0:3] lbs [0:3] la[27:31] ldp[0:3] lale clock divider gasket and mux addr/data mux lad[0:31] lpbse lcke lsync_in lsync_out msrcid[0:4] mdval lclk[0:2] chapter 13 local bus controller this chapter describes the local bus controller (lbc) block. it describes the external signals and the memory-mapped registers as well as a functional desc ription of the general-pur pose chip-select machine (gpcm), sdram machine, and user-p rogrammable machines (upms) of the lbc. finally, it includes an initialization and applications information sect ion with many specific examples of its use. 13.1 introduction figure 13-1 is a functional block diagram of the lbc, which supports thre e interfaces: gpcm, upm, and sdram controller. figure 13-1. local bus c ontroller block diagram upm ctrl gpcm sdram memory controller address and data machine banks and config regs upm ram transfer acknowledge local address local data refresh timers/ counters local memory compare control signal timing generator gpcm ctrl loe lgta lbctl upm ctrl lgpl[0:3] lgpl4/lupwait lgpl5 sdram ctrl lsda10 lsdwe lsdras lsdcas lcs [0:7] lwe [0:3] lsddqm [0:3] lbs [0:3] la[27:31] ldp[0:3] lale clock divider gasket and mux addr/data mux lad[0:31] lpbse lcke lsync_in lsync_out msrcid[0:4] mdval lclk[0:2] 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-2 freescale semiconductor 13.1.1 overview the main component of the lbc is its memory cont roller, which provides a seamless interface to many types of memory devices and peri pherals. the memory cont roller is responsible for controlling eight memory banks shared by a high perf ormance sdram machine, a gpcm, and up to three upms. as such, it supports a minimal glue logic interface to synchronous dram (sdram), sram, eprom, flash eprom, burstable ram, regular dram devices, extended data output dram devices, and other peripherals. the external address la tch signal (lale) allows multiplexi ng of addresses w ith data signals to reduce the device signal count. the lbc also includes a number of data checking and pr otection features such as data parity generation and checking, write protection and a bus monitor to en sure that each bus cycle is terminated within a user-specified period. 13.1.2 features the lbc main features are as follows: ? memory controller with eight memory banks ? 32-bit 1 address decoding with mask ? variable memory block sizes (32 kbytes to 4 gbytes) ? selection of control signal generation on a per-bank basis ? data buffer controls activ ated on a per-bank basis ? up to 256-byte bursts, arbitrarily aligned ? automatic segmentation of large transactions ? odd/even parity checking including read-modi fy-write (rmw) parity for single accesses ? write-protection capability ? atomic operation ? parity byte-select ? sdram machine ? provides the control functions and signals for glueless connection to jedec-compliant sdram devices ? supports up to four concurrent open pages per device ? supports sdram port size of 32, 16, and 8 bits ? supports external address a nd/or command lines buffering ? general-purpose chip-select machine (gpcm) ? compatible with sram, eprom, feprom, and peripherals ? global (boot) chip-select av ailable at system reset ? boot chip-select support for 8-, 16-, 32-bit devices ? minimum 3-clock access to external devices 1.refers to the logical address space of the lbc. once the address is deco ded by the lbc, it is the rightmost 32-bits which are used for the transaction (32-bit physical address space). 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-3 ? four byte-write-enable signals (lwe [0:3]) ? output enable signal (loe ) ? external access termination signal (lgta ) ? three user-programmable machines (upms) ? programmable-array-based machine controls exte rnal signal timing with a granularity of up to one-quarter of an external bus clock period ? user-specified control-signal patterns run when an internal master requests a single-beat or burst read or write access. ? upm refresh timer runs a us er-specified control signal pattern to support refresh ? user-specified control-signal patter ns can be initiated by software ? each upm can be defined to support dram devices with depths of 64, 128, 256, and 512 kbytes, and 1, 2, 4, 8, 16, 32, 64, 128, and 256 mbytes ? support for 8-, 16-, 32-bit devices ? page mode support for successive transfers within a burst ? internal address multiplexing supporting 64-, 128-, 256- , and 512-kbyte, and 1-, 2-, 4-, 8-, 16-, 32-, 64-, 128-, and 256-mbyte page banks ? optional monitoring of transfers be tween local bus internal masters and local bus slaves (local bus error reporting) ? support for delay locked loop (dll) with softwa re-configurable bypass for low frequency bus clocks 13.1.3 modes of operation the lbc provides one gpcm, one sdram machine, and three upms for the local bus, with no restriction on how many of the eight banks (chip sel ects) can be programmed to operate with any given machine. when a memory transaction is dispatched to the lbc, the memo ry address is compared with the address information of ea ch bank (chip select). the corresponding ma chine assigned to that bank (gpcm, sdram, or upm) then takes ownership of the exte rnal signals that contro l the access and maintains control until the transact ion ends. thus, with the lbc in gpcm, sdram, or upm mode , only one of the eight chip selects is active at any ti me for the duration of the transaction. 13.1.3.1 lbc bus clock and clock ratios the lbc supports ratios of 2, 4, and 8 between the faster system (ccb) clock and the slower external bus clock (lclk[0:2]). this ratio is software programmable through the clock ratio register (lcrr[clkdiv]). in addition to esta blishing the frequency of the extern al local bus clock, clkdiv also affects the resolution of signal timin g shifts in gpcm mode and the in terpretation of upm array words in upm mode. the bus clock is driven identically onto signals lclk[0:2] to allow the clock load to be shared equally across a pair of signal nets, thereby enhancing th e edge rates of the bus clock. 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-4 freescale semiconductor 13.1.3.2 source id debug mode in debug mode, the lbc provides the id of a transac tion source on external devi ce signals. this mode is enabled on power-on rese t, as described in section 20.4.4, ?local bus interface debug.? when placed in this mode, the 5-bit internal id of the current tr ansaction source appears on ms rcid[0:4] whenever valid address or data is available on the lbc external signals. the reserved valu e of 0x1f, which indicates invalid address or data, appears on the source id signals at all othe r times. the combination of a valid source id (any value except 0x1f) and the value of external address latch enable (lale) and data valid (mdval) facilitate capturing us eful debug data as follows: ? if a valid source id is detect ed on msrcid[0:4] and lale is asse rted, a valid full 32-bit address may be latched from lad[0:31]. note that in sd ram mode the address vector contains the full address as {row, bank, column, ls bs} where row corresponds to the same row address for the given column address and lsbs are the unconnected lsbs of the address for a given port size. ? if a valid source id is detected on msrcid[0 :4] and mdval is asserted, valid data may be latched from lad[0:31]. 13.1.4 power-down mode the lbc can enter a power-dow n mode when the system stops the inte rnal (system) clock to the block by using a handshake protocol initiated by the devdis r[lbc] setting in the global utilities block. on entering power-down mode, th e lbc places any sdram devi ces, if used, in self-r efresh mode before the bus clock is stopped. the lbc also allows the dll su fficient time to recover following the reapplication of the system clock. once the lbc has been put into power-down mode, th e only way to exit from this mode is through hreset . 13.2 external signal descriptions table 13-1 contains a list of external signals relate d to the lbc and summar izes their function. i/o impedance of designated local bus signals is determined by porimpscr, as described in section 18.4.1.3, ?por i/o impedance status and control register (porimpscr).? table 13-1. signal properties?summary name number of signals direction function lale 1 output external address latch enable lcs 8 output chip selects lwe n / lsddqm n / lbs n 4 output output output gpcm mode: write enable sdram mode: byte lane data mask upm mode: byte (lane) select lsda10/ lgpl0 1 output output sdram mode: row address bit/command bit upm mode: general-purpose line 0 lsdwe / lgpl1 1 output output sdram mode: write enable upm mode: general-purpose line 1 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-5 table 13-2 contains detailed external si gnal descriptions for the lbc. loe / lsdras / lgpl2 1 output output output gpcm mode: output enable sdram mode: row address strobe upm mode: general-purpose line 2 lsdcas / lgpl3 1 output output sdram mode: column address strobe upm mode: general-purpose line 3 lgta / lgpl4/ lupwait/ lpbse 1 input output input output gpcm mode: transaction termination upm mode: general-purpose line 4 upm mode: external device wait local bus parity byte select lgpl5 1 output upm mode: general-purpose line 5 lbctl 1 output data buffer control la[27:31] 5 output local bus non-multiplexed address lsbs lad[0:31] 32 input/output multiplexed address/data bus ldp 4 input/output local bus data parity lcke 1 output local bus clock enable lclk[0:2] 3 output local bus clocks lsync_in 1 input dll synchronize input lsync_out 1 output dll synchronize output mdval 1 output in lbc debug mode: local bus data valid msrcid 5 output in lbc debug mode: local bus source id table 13-2. local bus controller detailed signal descriptions signal i/o description lale o external address latch enable. the local bus memory controller provides control for an external address latch, which allows address and data to be multiplexed on the device signals. state meaning asserted/negated?lale is asserted with the address at the beginning of each memory controller transaction. the number of cycles for which it is asserted is governed by the orn[ead] and lcrr[eadc] fields. the exact timi ng of the negation of lale is controlled by the lbcr[ahd] field. note that no other control signals are asserted during the assertion of lale. lcs [0:7] o chip selects. eight chip selects are provided which are mutually exclusive. state meaning asserted/negated?used to enable specific memory devices or peripherals connected to the lbc. lcs [0:7] are provided on a per-bank basis with lcs0 corresponding to the chip select for memory bank 0, which has the memory type and attributes defined by br0 and or0. table 13-1. signal properties?summary (continued) name number of signals direction function 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-6 freescale semiconductor lwe [0:3]/ lsddqm [0:3]/ lbs [0:3] o gpcm write enable/sdram data mask/upm byte select. these signals select or validate each byte lane of the data bus. for banks with port sizes of 32 bits (as set by br n [ps]), all four signals are defined. for a 16-bit port size, only bits 0:1 are defined; and for an 8-bit port size, bit 0 is the only defined signal. the least-significant address bits of each access also de termine which byte lanes are considered valid for a given data transfer. state meaning asserted/negated?for gpcm operation, lwe [0:3] assert for each byte lane enabled for writing. for sdram operation, lsddqm [0:3] function as the dqm or data mask signals provided by jedec-compliant sdram devices, with one dqm provided per byte lane. lsddqm [0:3] are driven high when the lbc wishes to mask a write or disable read data output from the sdram. lbs [0:3] are programmable byte-select signals in upm mode. see section 13.4.4.4, ?ram array,? for programming details about lbs [0:3]. timing assertion/negation?see section 13.4.2, ?general-purpose chip-select machine (gpcm),? for details regarding the timing of lwe [0:3]. lsda10/ lgpl0 o sdram a10/general-purpose line 0 state meaning asserted/negated?for sdram accesses, repres ents address bit 10. when the row address is driven, it drives the value of address bit 10. when the column address is driven, it forms part of the sdram command. one of six general-purpose signals when in up m mode; it drives a value programmed in the upm array. lsdwe / lgpl1 o sdram write enable/general-purpose line 1 state meaning asserted/negated?should be connected to the s dram device we input. acts as the sdram write enable when accessing sdram. one of six general-purpose signals when in upm mode, and drives a value programmed in the upm array. loe / lsdras / lgpl2 o gpcm output enable/sdram ras /general-purpose line 2 state meaning asserted/negated?controls the output buffer of memory when accessing memory/devices in gpcm mode. for sdram accesses, it is the row address strobe (ras ). one of six general-purpose lines when in upm mode; it drives a value programmed in the upm array. lsdcas / lgpl3 o sdram cas /general-purpose line 3 state meaning asserted/negated?in sdram mode, dr ives the column address strobe (cas ). one of six general-purpose signals when in upm mode, and drives a value programmed in the upm array. lgta / lgpl4/ lupwait/ lpbse i/o gpcm transfer acknowledge/general-purpose line 4/upm wait/parity byte select state meaning asserted/negated?input in gpcm mode used for transaction termination. it may also be configured as one of six general-purpose output signals when in upm mode or as an input to force the upm controller to wait for the memory/device. when configured as lpbse, it disables any use in gpcm or upm modes. because systems that use read-modify-writ e parity require an additional memory device, they must generate a byte-select like a normal data device. anding lbs [0:3] through external logic to achieve the logical function of this byte-select adds a delay to the byte-select path that can affect memory access timing. the lbc provid es this optional byte-select signal that is an internal and of the four (active low) byte selects, allowing glueless, faster connection to rmw-parity devices. table 13-2. local bus controller detailed signal descriptions (continued) signal i/o description 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-7 lgpl5 o general-purpose line 5 state meaning asserted/negated?one of six general-purpose sign als when in upm mode, and drives a value programmed in the upm array. lbctl o data buffer control. the memory controller activates lbctl for the local bus when a gpcm- or upm-controlled bank is accessed. access to an sdram machine-controlled bank does not activate the buffer control. buffer control is disabled by setting or n [bctld]. state meaning asserted/negated?the lbctl signal no rmally functions as a write/read control for a bus transceiver connected to the lad lines. note that an external data buffer must not drive the lad lines in conflict with the lbc when lbctl is high, because lbctl remains high after reset and during address phases. la[27:31] o local bus non-multiplexed addr ess lsbs. all bits driven on la[27:31] are defined for 8-bit port sizes. for 32-bit port sizes, la[30:31] are don?t cares; for 16-bit port sizes la31 is a don?t care. state meaning asserted/negated?although the lb c shares an address and data bus, up to five lsbs of the ram address always appear on the dedicated ad dress signals, la[27:31]. these may be used, unlatched, in place of lad[27:31] to connect the five lsbs of the address for address phases. for some ram devices, such as fast -page dram, la[27:31] serve as the column address offset during a burst access. lad[0:31] i/o multiplexed address/data bus. for configuration of a port size in br n [ps] as 32 bits, all of lad[0:31] must be connected to the external ram data bus, with la d[0:7] occupying the most significant byte lane (at address offset 0). for a port size of 16 bits, lad[ 0:7] connect to the most significant byte lane (at address offset 0), while lad[8:15] co nnect to the least-significant byte lane (at address offset 1); lad[16:31] are unused for 16-bit port sizes. for a por t size of 8 bits, only lad[0:7] are connected to the external ram. state meaning asserted/negated?lad[0:31] is the shared 32-bit address/data bus through which external ram devices transfer data and receive addresses. timing assertion/negation?during assertion of lale, lad[0:31] are driven with the ram address for the access to follow. external logic should propagate the address on lad[0:31] while lale is asserted, and latch the address upon n egation of lale. after lale is negated, lad[0:31] are either driven by write data or are made high impedance by the lbc in order to sample read data driven by an external device. following the last data transfer of a write access, lad[0:31] are again taken into a high-impedance state. ldp[0:3] i/o local bus data parity. drives and receives the da ta parity corresponding with the data phases on lad[0:31]. state meaning asserted/negated?during write accesses, a parity bi t is generated for each 8 bits of lad[0:31], such that ldp0 is even/odd parity for la d[0:7], while ldp3 is even/odd parity for lad[24:31]. unused byte lanes for port sizes less than 32 bits have undefined parity. timing assertion/negation?drive and receive the data parity corresponding with the data phases on lad[0:31]. for read accesses, the parity bits for each byte lane are sampled on ldp[0:3] with the same timing that read data is sampled on lad[0:31]. ldp[0:3] change impedance in concert with lad[0:31]. lcke o local bus clock enable state meaning asserted/negated?lcke is the bus clock enable signal (cke) for jedec-standard sdram devices. asserted during normal sdram operation. table 13-2. local bus controller detailed signal descriptions (continued) signal i/o description 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-8 freescale semiconductor 13.3 memory map/register definition table 13-3 shows the memory mapped regist ers of the lbc and their offsets. it lists the offset, name, and a cross-reference to the complete de scription of each register. note that the full register address is comprised of ccsrbar togeth er with the block base a ddress and offset listed in table 13-3 . undefined 4-byte address spaces within offset 0x000?0xfff are reserved. in this table and in the register figures and field descriptions, th e following access definitions apply: ? reserved fields are always ignored for the purposes of determining access type. ? r/w, r, and w (read/write, read only, and write only) indicate that all the non-reserved fields in a register have the same access type. lclk[0:2] o local bus clocks state meaning asserted/negated?lclk[0:2] drive an identical bus clock signal for distributed loads. if the lbc dll is enabled (see lcrr[dbyp], figure 13-19 on page 13-31 ), the bus clock phase is shifted earlier than transitions on other lbc signals (such as lad[0:31] and lcs n ) by a time delay matching the delay of the dlltiming loop set up between lsync_out and lsync_in. lsync_out o dll synchronization out state meaning asserted/negated?a replica of the bus cloc k, appearing on lsync_out, should be propagated through a passive timing loop and returned to lsync_in for achieving correct dll lock. timing assertion/negation?the time delay of the timing loop should be such that it compensates for the round-trip flight time of lclk[2] and clo cked drivers in the system. no load other than a timing loop should be placed on lsync_out. lsync_in i dll synchronization in state meaning asserted/negated?see description of lsync_out. mdval o local bus data valid (lbc debug mode only) state meaning asserted/negated?for a read, mdval asserts for one bus cycle in the cycle immediately preceding the sampling of read data on lad[0:31]. for a write, mdval asserts for one bus cycle during the final cycle for which the curr ent write data on lad[0:31 ] is valid. during burst transfers, mdval asserts for each data beat. timing assertion/negation?valid only wh ile the lbc is in system debug mode. in debug mode, mdval asserts when the lbc generates a data transfer acknowledge. msrcid[0:4] o local bus source id (lbc debug mode only). in debug mode, all msrcid[0:4] signals are driven high unless msrcid[0:4] is driving a debug source id for identifying the internal syst em device controlling the lbc. state meaning asserted/negated?remain high unti l the last bus cycle of the asse rtion of lale, in which case the source id of the address is indicated, or until mdval is asserted, in which case the source id relating to the data transfer is indica ted. in case of address debug, msrcid[0:4] is valid only when the address on lad[0:31] consists of all physical address bits?with optional padding?for reconstructing the system address presented to the lbc. for example, msrcid[0:4] is valid only during cas phases of sdram accesses, because the column, bank select, and (normally unused) ro w address bits are all present on lad[0:31] during a cas cycle table 13-2. local bus controller detailed signal descriptions (continued) signal i/o description 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-9 ? w1c indicates that all of the non-reserved fields in a register are cleared by writing ones to them. ? mixed indicates a combination of access types. ? special is used when no other cate gory applies. in this case the re gister figure and field description table should be read carefully. table 13-3. local bus controller memory map offset use access reset section/page local bus block base address: 0x0_6000 0x000 br0?base register 0 r/w 0x0000_ nn 01 1 13.3.1.1/13-10 0x008 br1?base register 1 0x0000_0000 0x010 br2?base register 2 0x018 br3?base register 3 0x020 br4?base register 4 0x028 br5?base register 5 0x030 br6?base register 6 0x038 br7?base register 7 0x004 or0?options register 0 r/w 0x0000_0ff7 13.3.1.2/13-12 0x00c or1?options register 1 0x0000_0000 0x014 or2?options register 2 0x01c or3?options register 3 0x024 or4?options register 4 0x02c or5?options register 5 0x034 or6?options register 6 0x03c or7?options register 7 0x068 mar?upm address register r/w 0x0000_0000 13.3.1.3/13-17 0x070 mamr?upma mode register r/w 0x0000_0000 13.3.1.4/13-18 0x074 mbmr?upmb mode register r/w 0x0000_0000 13.3.1.4/13-18 0x078 mcmr?upmc mode register r/w 0x0000_0000 13.3.1.4/13-18 0x084 mrtpr?memory refresh timer prescaler register r/w 0x0000_0000 13.3.1.5/13-20 0x088 mdr?upm data register r/w 0x0000_0000 13.3.1.6/13-21 0x094 lsdmr?sdram mode register r/w 0x0000_0000 13.3.1.7/13-21 0x0a0 lurt?upm refresh timer r/w 0x0000_0000 13.3.1.8/13-23 0x0a4 lsrt?sdram refresh timer r/w 0x0000_0000 13.3.1.9/13-24 0x0b0 ltesr?transfer error status register w1c 0x0000_0000 13.3.1.10/13-25 0x0b4 ltedr?transfer error disable register r/w 0x0000_0000 13.3.1.11/13-26 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-10 freescale semiconductor 13.3.1 register descriptions this section provides a detailed de scription of the lbc configuration, status, and control registers with detailed bit and fi eld descriptions. address offsets in the lbc addres s range that are not defined in table 13-3 should not be accessed for reading or writing. similarly, only zero should be written to reserved bits of defined registers, as writing ones can have unpredictable results in some cases. bits designated as write-one -to-clear are cleared only by writing ones to them. writing zer os to them has no effect. 13.3.1.1 base regi sters (br0?br7) the base registers (br n ), shown in figure 13-2 , contain the base address and address types for each memory bank. the memory controller uses this inform ation to compare the address bus value with the current address accessed. each regist er (bank) includes a memory attr ibute and selects the machine for memory operation handling. note that after system reset, br 0[v] is set, br1[v]? br7[v] are cleared, and the value of br0[ps] reflects th e initial port size configured by the boot rom location signals. 0x0b8 lteir?transfer error interrupt register r/w 0x0000_0000 13.3.1.12/13-27 0x0bc lteatr?transfer error attributes register r/w 0x0000_0000 13.3.1.13/13-28 0x0c0 ltear?transfer error address register r/w 0x0000_0000 13.3.1.14/13-29 0x0d0 lbcr?configuration register r/w 0x0000_0000 13.3.1.15/13-29 0x0d4 lcrr?clock ratio register r/w 0x8000_0008 13.3.1.16/13-31 1 port size for br0 is configured from external signals during reset, hence ? nn ? is either 0x08, 0x10, or 0x18. offset 0x000 (br0) 0x008 (br1) 0x010 (br2) 0x018 (br3) 0x020 (br4) 0x028 (br5) 0x030 (br6) 0x038 (br7) access: read/write 0 16171819202122 2324 262728293031 r ba ? ps decc wp msel ? atom ? v w reset br000000000000000000 0 0 nn 0 0 0 0000 0 0 01 1 reset br1?br7 all zeros 1 br0 has its valid bit set during reset. thus bank 0 is valid with the port size ( ps) configured from external boot rom configuration signals during reset. all other base registers have all bits cleared to zero during reset. figure 13-2. base registers (br n ) table 13-3. local bus controller memory map (continued) offset use access reset section/page 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-11 table 13-4 describes br n fields. table 13-4. br n field descriptions bits name description 0?16 ba base address. the upper 17 bits of each base r egister are compared to the address on the address bus to determine if the bus master is accessing a memory b ank controlled by the memory controller. used with the address mask bits or n [am]. 17?18 ? reserved 19?20 ps port size. specifies the port size of this memory re gion. for br0, ps is configured from the boot rom location signals during reset. for all other banks the value is reset to 00 (port size not defined). 00 reserved 01 8-bit 10 16-bit 11 32-bit 21?22 decc specifies the method for data error checking. 00 data error checking disabled, but normal parity generation 01 normal parity generation and checking 10 read-modify-write parity generation and normal parity checking (32-bit port size only) 11 reserved 23 wp write protect 0 read and write accesses are allowed. 1 only read accesses are allowed. the memory controller does not assert lcs n on write cycles to this memory bank. ltesr[wp] is set (if wp is set) if a writ e to this memory bank is attempted, and a local bus error interrupt is generated (if enabled), terminating the cycle. 24?26 msel machine select. specifies the machine to use for handling memory operations. 000 gpcm (reset value) 001 reserved 010 reserved 011 sdram 100 upma 101 upmb 110 upmc 111 reserved 27 ? reserved 28?29 atom atomic operation. writes (reads) to the address spac e handled by the memory controller bank reserve the selected memory bank for the exclusive use of the accessing device. the reservation is released when the device performs a read (write) operation to this memory controller bank. if a subsequent read (write) request to this memory controller bank is not detected within 256 bus cl ock cycles of the last write (read), the reservation is released and an atomic error is reported (if enabled). 00 the address space controlled by this b ank is not used for atomic operations. 01 read-after-write-atomic (rawa) 10 write-after-read-atomic (wara) 11 reserved 30 ? reserved 31 v valid bit. indicates th at the contents of the br n and or n pair are valid. lcs n does not assert unless v is set (an access to a region that has no valid bit set may cause a bus ti me-out). after a system reset, only br0[v] is set. 0 this bank is invalid. 1 this bank is valid. 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-12 freescale semiconductor 13.3.1.2 option registers (or0?or7) the or n registers define the sizes of memo ry banks and access attributes. the or n attribute bits support the following three modes of operation as defined by br n [msel]. ? gpcm mode ? upm mode ? sdram mode the or n registers are interpreted differently depending on which of the three machine types is selected for that bank. 13.3.1.2.1 address mask the address mask field of the option registers (or n [am]) mask up to 17 corresponding br n [ba] fields. the 15 lsbs of the 32-bit internal address do not participat e in bank address matching in selecting a bank for access. masking address bits indepe ndently allows external devices of different size address ranges to be used. address mask bits can be set or cleared in a ny order in the field, allowing a resource to reside in more than one area of the address map. table 13-5 shows memory bank sizes from 32 kbytes to 4 gbytes. table 13-5. memory bank sizes in relation to address mask address mask memory bank size address mask memory bank size 0000_0000_0000_0000_0 4 gbytes 1111_1111_1000_0000_0 8 mbytes 1000_0000_0000_0000_0 2 gbytes 1111_1111_1100_0000_0 4 mbytes 1100_0000_0000_0000_0 1 gbyte 1111_1111_1110_0000_0 2 mbytes 1110_0000_0000_0000_0 512 mbytes 1111_1111_1111_0000_0 1 mbyte 1111_0000_0000_0000_0 256 mbytes 1111_1111_1111_1000_0 512 kbytes 1111_1000_0000_0000_0 128 mbytes 1111_1111_1111_1100_0 256 kbytes 1111_1100_0000_0000_0 64 mbytes 1111_1111_1111_1110_0 128 kbytes 1111_1110_0000_0000_0 32 mbytes 1111_1111_1111_1111_0 64 kbytes 1111_1111_0000_0000_0 16 mbytes 1111_1111_1111_1111_1 32 kbytes 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-13 13.3.1.2.2 option registers (or n )?gpcm mode figure 13-3 shows the bit fields for or n when the corresponding br n [msel] selects the gpcm machine. table 13-6 describes or n fields for gpcm mode. offset 0x004 (or0) 0x00c (or1) 0x014 (or2) 0x01c (or3) 0x024 (or4) 0x02c (or5) 0x034 (or6) 0x03c (or7) access: read/write 0 161718 19 2021222324 2728 29 30 31 r am ? bctld csnt acs xacs scy seta trlx ehtr ead w reset or00000000000000000 0 0 0 0 1 1 1 1 1 11 1 0 1 1 1 1 1 or0 has this value set during reset (gpcm is the default control machine for all banks coming out of reset). all other option registers have all bits cleared. reset or1?7 all zeros figure 13-3. option registers (or n ) in gpcm mode table 13-6. or n ? gpcm field descriptions bits name description 0?16 am gpcm address ma sk. masks corresponding br n bits. masking address bits independently allows external devices of different size address ranges to be used. ad dress mask bits can be set or cleared in any order in the field, allowing a resource to reside in more than one area of the address map. 0 corresponding address bits are masked. 1 corresponding address bits are used in the comparison between base and transaction addresses. 17?18 ? reserved 19 bctld buffer control disable. disables assertion of lbctl during access to the current memory bank. 0 lbctl is asserted upon access to the current memory bank. 1 lbctl is not asserted upon access to the current memory bank. 20 csnt chip select negation time. determines when lcs n and lwe are negated during an external memory write access handled by the gpcm, provided that acs 00 (when acs = 00, only lwe is affected by the setting of csnt). this helps meet address/data hold times for slow memories and peripherals. 0lcs n and lwe are negated normally. 1lcs n and lwe are negated subject to the value of lcrr[clkdiv]. lcrr [clkdiv] csnt meaning x0lcs n and lwe are negated normally. 21lcs n and lwe are negated normally. 4 or 8 1 lcs n and lwe are negated quarter of a bus clock cycle earlier. 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-14 freescale semiconductor 21?22 acs address to chip-select setup. determines the delay of the lcs n assertion relative to the address change when the external memory access is handled by the gpcm. at system reset, or0[acs] = 11. lcrr [clkdiv] value meaning x00lcs n is output at the same time as the address lines. note that this overrides the value of csnt such that csnt = 0. 01 reserved. 210lcs n is output a half bus clock cycle after the address lines. 11 lcs n is output a half bus clock cycle after the address lines. 4 or 8 10 lcs n is output a quarter bus clock cycle after the address lines. 11 lcs n is output a half bus clock cycle after the address lines. 23 xacs extra address to chip-select setup. setting this bit increases the delay of the lcs n assertion rela tive to the address change when the external memory access is handled by the gpcm. after a system reset, or0[xacs] = 1. 0 address to chip-select setup is determined by orx[acs] and lcrr[clkdiv]. 1 address to chip-select setup is extended (see table 13-23 and table 13-24 for lcrr[clkdiv] = 4 or 8, table 13-25 and table 13-26 for lcrr[clkdiv] = 2). 24?27 scy cycle length in bus clocks. determines the number of wait states inserted in the bus cycle, when the gpcm handles the external memory access. thus it is the main parameter for determin ing cycle length. the total cycle length depends on other timing attribute settings. after a system reset, or0[scy] = 1111. 0000 no wait states 0001 1 bus clock cycle wait state ... 1111 15 bus clock cycle wait states 28 seta external address termination 0 access is terminated internally by the memory controller unless the external device asserts lgta earlier to terminate the access. 1 access is terminated exter nally by asserting the lgta external signal. (only lgta can terminate the access). 29 trlx timing relaxed. modifies the settings of timing parameters for slow memories or peripherals. 0 normal timing is generated by the gpcm. 1 relaxed timing on the following parameters: ? adds an additional cycle between the address and control signals (only if acs 00) ? doubles the number of wait states specif ied by scy, providing up to 30 wait states ? works in conjunction with ehtr to extend hold time on read accesses ?lcs n (only if acs 00) and lwe signals are negated one cycle earlier during writes. table 13-6. or n ? gpcm field descriptions (continued) bits name description 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-15 13.3.1.2.3 option registers (or n )?upm mode figure 13-4 shows the bit fields for or n when the corresponding br n [msel] selects a upm machine. table 13-7 describes br n fields for upm mode. 30 ehtr extended hold time on read accesses. indicates with trlx how many cycles are inserted between a read access from the current bank and the next access. trlx ehtr meaning 0 0 the memory controller generates no rmal timing. no additional cycles are inserted. 0 1 1 idle clock cycle is inserted. 1 0 4 idle clock cycles are inserted. 1 1 8 idle clock cycles are inserted. 31 ead external address latch delay. allow extra bus cl ock cycles when using external address latch (lale). 0 no additional bus clock cycles (lale asserted for one bus clock cycle only) 1 extra bus clock cycles are added (lale is asserted for the number of bus clock cycles specified by lcrr[eadc]). offset 0x004 (or0) 0x00c (or1) 0x014 (or2) 0x01c (or3) 0x024 (or4) 0x02c (or5) 0x034 (or6) 0x03c (or7) access: read/write 0 161718 19 20 222324 28 29 30 31 r am ? bctld ? bi ? trlx ehtr ead w reset all zeros figure 13-4. option registers (or n ) in upm mode table 13-7. or n ? upm field descriptions bits name description 0?16 am upm address mask. masks corresponding br n bits. masking address bits independently allows external devices of different size address ranges to be used. address mask bits can be set or cleared in any order in the field, allowing a resource to reside in more than one area of the address map. 0 corresponding address bits are masked. 1 the corresponding address bits are used in the comparison with address signals. 17?18 ? reserved 19 bctld buffer control disable. disables assertion of lbctl during access to the current memory bank. 0 lbctl is asserted upon access to the current memory bank. 1 lbctl is not asserted upon access to the current memory bank. 20?22 ? reserved table 13-6. or n ? gpcm field descriptions (continued) bits name description 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-16 freescale semiconductor 13.3.1.2.4 option registers (or n )?sdram mode figure 13-5 shows the bit fields for or n when the corresponding br n [msel] selects the sdram machine. table 13-8 describes br n fields for sdram mode. 23 bi burst inhibit. indicates if this memory bank supports burst accesses. 0 the bank supports burst accesses. 1 the bank does not support burst accesses. the select ed upm executes burst accesses as a series of single accesses. 24?28 ? reserved 29 trlx timing relaxed. works in conjunction with ehtr to extend hold time on read accesses. 30 ehtr extended hold time on read accesses. indicates with trlx how many cycles are inserted between a read access from the current bank and the next access. trlx ehtr meaning 0 0 the memory controller generates normal timing. no additional cycles are inserted. 0 1 1 idle clock cycle is inserted. 1 0 4 idle clock cycles are inserted. 1 1 8 idle clock cycles are inserted. 31 ead external address latch delay. allow extra bus cl ock cycles when using external address latch (lale). 0 no additional bus clock cycles (lale asserted for one bus clock cycle only) 1 extra bus clock cycles are added (lale is asserted for the number of bus clock cycles specified by lcrr[eadc]). offset 0x004 (or0) 0x00c (or1) 0x014 (or2) 0x01c (or3) 0x024 (or4) 0x02c (or5) 0x034 (or6) 0x03c (or7) access: read/write 0 16171819 212223 25 26 27 30 31 r am ? cols ? rows pmsel ? ead w reset all zeros figure 13-5. option registers (or n ) in sdram mode table 13-8. or n ? sdram field descriptions bits name description 0?16 am sdram address mask. masks corresponding br n bits. masking address bits independently allows external devices of different size address ranges to be used. ad dress mask bits can be set or cleared in any order in the field, allowing a resource to reside in more than one area of the address map. am can be read or written at any time. 0 corresponding address bits are masked. 1 the corresponding address bits are used in the comparison with address signals. 17?18 ? reserved table 13-7. or n ? upm field descriptions (continued) bits name description 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-17 13.3.1.3 upm memory ad dress register (mar) figure 13-6 shows the fields of the upm memory address register (mar). table 13-9 describes the mar fields. 19?21 cols number of column address lines. sets the number of column address lines in the sdram device. 000 7 001 8 010 9 011 10 100 11 101 12 110 13 111 14 22 ? reserved 23?25 rows number of row address lines. sets the number of row address lines in the sdram device. 000 9 001 10 010 11 011 12 100 13 101 14 110 15 111 reserved 26 pmsel page mode select. selects page mode for the sdram connected to the memory controller bank. 0 back-to-back page mode (normal operation). page is closed when the bus becomes idle. 1 page is kept open until a page miss or refresh occurs. 27?30 ? reserved 31 ead external address latch delay. allow extra bus cl ock cycles when using external address latch (lale). 0 no additional bus clock cycles (lale asserted for one bus clock cycle only) 1 extra bus clock cycles are added (lale is asserted for the number of bus clock cycles specified by lcrr[eadc]). offset 0x068 access: read/write 0 31 r a w reset all zeros figure 13-6. upm memory address register (mar) table 13-9. mar field descriptions bits name description 0?31 a address that can be output to the address signals under control of the amx bits in the upm ram word. table 13-8. or n ? sdram field descriptions (continued) bits name description 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-18 freescale semiconductor 13.3.1.4 upm mode registers (m x mr) the upm machine mode registers (mamr, mbmr and mcmr), shown in figure 13-7 , contain the configuration for the three upms. table 13-10 describes upm mode fields. offset 0x070 (mamr) 0x074 (mbmr) 0x078 (mcmr) access: read/write 01234578910121314171821222526 31 r ? rfen op uwpl am ds g0cl gpl4 rlf wlf tlf mad w reset all zeros figure 13-7. upm mode registers (m x mr) table 13-10. m x mr field descriptions bits name description 0?reserved 1 rfen refresh enable. indicates that the upm needs refres h services. this bit must be set for upma (refresh executor) if refresh services are required on any up m assigned chip selects. if mamr[rfen] = 0, no refresh services can be provided, even if upmb and/or upmc have their rfen bit set. 0 refresh services are not required 1 refresh services are required 2?3 op command opcode. determines the command executed by the upm n when a memory access hits a upm assigned bank. see section 13.4.4.2, ?p rogramming the upms,? for important programming considerations. 00 normal operation 01 write to upm array. on the next memory access that hits a upm assigned bank, write the contents of the mdr into the ram location pointe d to by mad. after the access, mad is automatically incremented. 10 read from upm array. on the next memory access that hits a upm assigned bank, read the contents of the ram location pointed to by ma d into the mdr. after the access, mad is automatically incremented. 11 run pattern. on the next memory access that hits a upm assigned bank, run the pattern written in the ram array. the pattern run starts at the location point ed to by mad and continues until the last bit is set in the ram word. 4 uwpl lupwait polarity active low. sets the pola rity of the lupwait signal when in upm mode. 0 lupwait is active high. 1 lupwait is active low. 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-19 5?7 am address multiplex size. determines how the addre ss of the current memory cycle can be output on the address signals. this field is needed when interfacing with devices requiring row and column addresses multiplexed on the same signals. 8?9 ds disable timer period. guarantees a minimum time between accesses to the same memory bank controlled by upm n . the disable timer is turned on by the todt bit in the ram array word, and when expired, the upm n allows the machine access to handle a memory patter n to the same bank. accesses to a different bank by the same upm n is also allowed. to avoid conflicts between successive accesses to different banks, the minimum pattern in the ram array for a request serviced , should not be shorter than the period established by ds. 00 1-bus clock cycle disable period 01 2-bus clock cycle disable period 10 3-bus clock cycle disable period 11 4-bus clock cycle disable period 10?12 g0cl general line 0 control. determines which logical address line can be output to the lgpl0 signal when the upm n is selected to control the memory access. 000 a12 001 a11 010 a10 011 a9 100 a8 101 a7 110 a6 111 a5 13 gpl4 lgpl4 output line disable. determines how the lgpl4/lupwait signal is controlled by the corresponding bits in the upm n array. see table 13-30 . table 13-10. m x mr field descriptions (continued) bits name description value la0?la15 la16 la17 la18 la19?la28 la29 la30 la31 000 0 a8 a9 a10 a11?a20 a21 a22 a23 001 0 a7 a8 a9 a10?a19 a20 a21 a22 010 0 a6 a7 a8 a9?a18 a19 a20 a21 011 0 a5 a6 a7 a8?a17 a18 a19 a20 100 0 a4 a5 a6 a7?a16 a17 a18 a19 101 0 a3 a4 a5 a6?a15 a16 a17 a18 110 reserved 111 reserved value lgpl4/lupwait signal function interpretation of upm word bits g4t1/dlt3 g4t3/waen 0 lgpl4 (output) g4t1 g4t3 1 lupwait (input) dlt3 waen 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-20 freescale semiconductor 13.3.1.5 memory refresh timer prescaler register (mrtpr) the refresh timer prescaler re gister (mrtpr), shown in figure 13-8 , is used to divide the system clock to provide the sdram and up m refresh timers clock. 14?17 rlf read loop field. determines the number of times a loop defined in the upm n will be executed for a burst- or single-beat read pattern or when m x mr[op] = 11 ( run command) 0000 16 0001 1 0010 2 0011 3 ... 1110 14 1111 15 18?21 wlf write loop field. determines the number of times a loop defined in the upm n will be executed for a burst- or single-beat write pattern. 0000 16 0001 1 0010 2 0011 3 ... 1110 14 1111 15 22?25 tlf refresh loop field. determines the number of times a loop defined in the upm n will be executed for a refresh service pattern. 0000 16 0001 1 0010 2 0011 3 ... 1110 14 1111 15 26?31 mad machine address. ram address pointer for the command executed. this field is incremented by 1 each time the upm is accessed, and the op field is set to write or read. address range is 64 words per upm n . offset 0x084 access: read/write 078 31 r ptp ? w reset all zeros figure 13-8. memory refresh timer prescaler register (mrtpr) table 13-10. m x mr field descriptions (continued) bits name description 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-21 table 13-11 describes mrtpr fields. 13.3.1.6 upm data register (mdr) the memory data register (mdr), shown in figure 13-9 , contains data written to or read from the ram array for upm read or writ e commands. mdr must be set up before issuing a write command to the upm. table 13-12 describes mdr[d]. 13.3.1.7 sdram machine mode register (lsdmr) the local bus sdram mode register (lsdmr), shown in figure 13-10 , is used to configure operations pertaining to sdram. table 13-11. mrtpr field descriptions bits name description 0?7 ptp refresh timers prescaler. determines the period of th e refresh timers input clock. the system clock is divided by ptp except when the value is 0000_0000, which represents the maximum divider of 256. 8?31 ? reserved offset 0x088 access: read/write 0 31 r d w reset all zeros figure 13-9. upm data register (mdr) table 13-12. mdr field descriptions bits name description 0?31 d the data to be read or written into the ram array when a write or read command is supplied to the upm (m x mr[op] = 01 or m x mr[op] = 10). offset 0x094 access: read/write 0 1 2 4 5 7 8 1011 1314 16 17 19 20 22 23 2425262728 29 3031 r ? rfen op ? bsma ? rfcr pretoact acttorw bl ? wrc ? bufcmd cl w reset all zeros figure 13-10. sdram machine mode register (lsdmr) 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-22 freescale semiconductor table 13-12 describes lsdmr fields. table 13-13. lsdmr field descriptions bits name description 0?reserved 1 rfen refresh enable. indicates that the sdram requires refresh services. 0 refresh services are not required. 1 refresh services are required. 2?4 op sdram operation. selects the operation that occurs when the sdram device is accessed. 5?7 ? reserved 8?10 bsma bank select multiplexed address line. selects which address signals serve as the 2-bit bank-select address for sdram. note that only 4-bank sdrams are supported. 000 la12:la13 001 la13:la14 010 la14:la15 011 la15:la16 100 la16:la17 101 la17:la18 110 la18:la19 111 la19:la20 11?13 ? reserved 14?16 rfcr refresh recovery. sets the refresh recovery interval in bus clock cycles. defines the earliest timing for an activate or refresh comma nd after a refresh command. 000 reserved 001 3 clocks 010 4 clocks 011 5 clocks 100 6 clocks 101 7 clocks 110 8 clocks 111 16 clocks 17?19 pretoact defines the earliest timing for activa te or refresh command after a precharge command (number of bus clock cycle wait states). 000 8 001 1 010 2 011 3 100 4 101 5 110 6 111 7 value meaning use 000 normal operation normal operation 001 auto refresh initialization 010 self refresh power-down mode or debug 011 mode register write initialization 100 precharge bank debug 101 precharge all banks initialization 110 activate bank debug 111 read/write without valid data transfer debug 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-23 13.3.1.8 upm refresh timer (lurt) the upm refresh time r (lurt), shown in figure 13-11 , generates a refresh reques t for all valid banks that selected a upm machine and are refresh-enabled (m x mr[rfen] = 1). each time the timer expires, a qualified bank generates a re fresh request using the selected upm. the qualified banks rotate their requests. 20?22 acttorw defines the earliest timing for read/write command after an activate command (number of bus clock cycle wait states). 000 8 001 reserved 010 2 011 3 100 4 101 5 110 6 111 7 23 bl sets the burst length for sdram accesses. 0 sdram burst length is 4. use this value if the device port size is16. 1 sdram burst length is 8. use this value if the device port size is 32 or 8. 24?25 ? reserved 26?27 wrc write recovery time. defines the earliest timing for precharge command after the last data is written to the sdram. 00 4 01 reserved 10 2 11 3 28 ? reserved 29 bufcmd control line assertion timing. if external buffers are placed on the control lines going to both the sdram and address lines, setting bufcmd causes all sdram control lines except lcs n , lcke, lale, and lsddqm [0:3] to be asserted for lcrr[bufcmdc] cycles, instead of one. 0 normal timing fo r the control lines 1 all control lines except lcs n are asserted for the number of cycles specified by lcrr[bufcmdc]. 30?31 cl cas latency. defines the timing for first read data after sdram samples a column address. 00 extended cas latency. a ccording to lcrr[ecl]. see table 13-22 . 01 1 10 2 11 3 offset 0x0a0 access: read/write 078 31 r lurt ? w reset all zeros figure 13-11. upm refresh timer (lurt) table 13-13. lsdmr field descriptions (continued) bits name description 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-24 freescale semiconductor table 13-14 describes lurt fields. 13.3.1.9 sdram refresh timer (lsrt) the sdram refresh time r (lsrt), shown in figure 13-12 , generates a refresh request for all valid banks that selected a sdram machine and are refresh- enabled (lsdmr[rfen] = 1). each time the timer expires, all qualifying banks generate a bank stagge ring auto-refresh request using the sdram machine. table 13-15 describes lsrt fields. table 13-14. lurt field descriptions bits name description 0?7 lurt upm refresh timer period. determ ines, along with the timer prescaler (mrtpr), the timer period according to the following equation: example : for a 266-mhz system clock and a required servic e rate of 15.6 s, giv en mrtpr[ptp] = 32, the lurt value should be 128 decimal. 128/(266 mhz/32) = 15. 4 s, which is less than the required service period of 15.6 s. note that the reset value (0x00) sets the maximum period to 256 mrtpr[ptp] system clock cycles. 8?31 ? reserved offset 0x0a4 access: read/write 078 31 r lsrt ? w reset all zeros figure 13-12. lsrt sdram refresh timer (lsrt) table 13-15. lsrt field descriptions bits name description 0?7 lsrt sdram refresh timer period. determines, along with the timer prescaler (mrtpr), the timer period according to the following equation: example: for a 266-mhz system clock and a required service rate of 15.6 s, given ptp = 32, the lsrt value should be 128 decimal. 128/(266 mhz/32) = 15.4 s, which is less than the required service period of 15.6 s. note that the reset value, 0x00, sets the maximum period to 256 mrtpr[ptp] system clock cycles. 8?31 ? reserved timerperiod lurt fsystemclock mrtpr ptp [] --------------------------------------- - ?? ?? --------------------------------------------- - = timerperiod lsrt fsystemclock mrtpr ptp [] --------------------------------------- - ?? ?? --------------------------------------------- - = 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-25 13.3.1.10 transfer error status register (ltesr) the lbc has the following registers for error management: ? the transfer error status register (l tesr) indicates the ca use of an error. ? the transfer error check disable register (ltedr) is used to en able (and disable) error checking. ? the transfer error check interrupt register (ltei r) enables reporting of er rors through an interrupt. ? the transfer error attributes register (lteat r) captures source at tributes of an error. ? the transfer error address regist er (ltear) captures the address of a transaction that caused an error. ltesr, shown in figure 13-13 , is a write-one-to-clear register . reading ltesr occurs normally; however, write operations can clear but not set bits. a bit is cleared when ever the register is written and the data in the corresponding bit location is a 1. fo r example, to clear only the write protect error bit (ltesr[wp]) without affecting ot her ltesr bits, 0x0400_0000 should be wr itten to the register. note that lteatr[v] bit has to be cleared to register subsequent errors in ltesr. table 13-16 describes ltesr fields. offset 0x0b0 access: w1c 0 1 2 3 4 5 6 7 8 9 10 11 12 13 31 rbm ? pa r ? wp ? at m w at m r ? cs ? w w1c w1c w1c w1c w1c w1c reset all zeros figure 13-13. transfer error status register (ltesr) table 13-16. ltesr field descriptions bits name description 0 bm bus monitor time-out 0 no local bus monitor time-out occurred. 1 local bus monitor time-out occurred. no data beat was acknowledged on the bus within lbcr[bmt] 8 bus clock cycles from the start of a transaction. 1?reserved 2parparity 0 no local bus parity error 1 local bus parity error. lteatr [pb] indicates the byte lane that caused the error and lteatr[bnk] indicates which memory cont roller bank was accessed. 3?4 ? reserved 5 wp write protect error 0 no write protect error occurred. 1 a write was attempted to a local bus memory region th at was defined as read-only in the memory controller. usually, in this case, a bus monitor time-out will occur (as the cycle is not automatically terminated). 6?7 ? reserved 8 atmw atomic error write 0 no atomic write error occurred. 1 the subsequent write (wara) to a memory bank did not occur within 256 bus clock cycles. 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-26 freescale semiconductor 13.3.1.11 transfer error check disable register (ltedr) the transfer error check disabl e register (ltedr), shown in figure 13-14 , is used to disable error checking. note that control of erro r checking is independent of contro l of reporting of errors (lteir) through the interrupt mechanism. table 13-17 describes ltedr fields. 9 atmr atomic error read 0 no atomic read error occurred. 1 the subsequent read (rawa) to a memory bank did not occur within 256 bus clock cycles. 10?11 ? reserved 12 cs chip select error 0 no chip select error occurred. 1 a transaction was sent to the lbc that did not hit any memory bank. 13?31 ? reserved offset 0x0b4 access: read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 31 r bmd ? pard ? wpd ? wara rawa ? csd ? w reset all zeros figure 13-14. transfer error check disable register (ltedr) table 13-17. ltedr field descriptions bits name description 0 bmd bus monitor disable 0 bus monitor is enabled 1 bus monitor is disabled 1?reserved 2 pard parity error checking disabled. note that unco rrectable read errors may cause the assertion of core_fault_in , which causes the core to generate a machine check inte rrupt, unless it is disabled (by clearing hid1[rfxe]). if rfxe is zero and this error occu rs, pard must be cleared and lteir[pari] must be set to ensure that an interrupt is generated. for more information, see section 6.10.2, ?hardware implementation-dependent register 1 (hid1).? 0 parity error checking is enabled. 1 parity error checking is disabled. 3?4 ? reserved 5 wpd write protect error checking disable 0 write protect error checking is enabled. 1 write protect error checking is disabled. 6?7 ? reserved table 13-16. ltesr field descriptions (continued) bits name description 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-27 13.3.1.12 transfer error interru pt enable register (lteir) the transfer error interrupt enab le register (lteir), shown in figure 13-15 , is used to send or block error reporting through the lbc internal in terrupt mechanism. software shoul d clear pending er rors in ltesr before enabling interrupts. after an interrupt has occurred, cl earing relevant ltesr error bits negates the interrupt. table 13-18 describes lteir fields. 8 wara write-after-read atomic (wara) error checking disable 0 wara error checking is enabled. 1 wara error checking is disabled. 9 rawa read-after-write atomic (rawa) error checking disable 0 rawa error checking is enabled. 1 rawa error checking is disabled. 10?11 ? reserved 12 csd chip select error checking disable 0 chip select error checking is enabled. 1 chip select error checking is disabled. 13?31 ? reserved offset 0x0b8 access: read/write 01234567 8 9 10111213 31 r bmi ? pari ? wpi ? wara rawa ? csi ? w reset all zeros figure 13-15. transfer error interrupt enable register (lteir) table 13-18. lteir field descriptions bits name description 0 bmi bus monitor error interrupt enable 0 bus monitor error reporting is disabled. 1 bus monitor error reporting is enabled. 1?reserved 2 pari parity error interrupt enable. note that uncorrectable read errors may cause the assertion of core_fault_in , which causes the core to generate a machine check inte rrupt, unless it is disabled (by clearing hid1[rfxe]). if rfxe is zero and this error occurs, ltedr[pard] mu st be cleared and pari must be set to ensure that an interrupt is generated. for more information, see section 6.10.2, ?hardware implementation-dependent register 1 (hid1).? 0 parity error reporting is disabled. 1 parity error reporting is enabled. 3?4 ? reserved table 13-17. ltedr field descriptions (continued) bits name description 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-28 freescale semiconductor 13.3.1.13 transfer error attributes register (lteatr) figure 13-16 shows the lteatr. after lteatr[v] has been se t, software must clear this bit to allow lbc error registers to update fo llowing any subsequent errors. table 13-19 describes lteatr fields. 5 wpi write protect error interrupt enable 0 write protect error reporting is disabled. 1 write protect error reporting is enabled. 6?7 ? reserved 8 wara write-after-read atomic (wara) error interrupt enable 0 wara error reporting is disabled. 1 wara error reporting is enabled. 9 rawa read-after-write atomic (rawa) error interrupt enable 0 rawa error reporting is disabled. 1 rawa error reporting is enabled. 10?11 ? reserved 12 csi chip select error interrupt enable 0 chip select error reporting is disabled. 1 chip select error reporting is enabled. 13?31 ? reserved offset 0x0bc access: read/write 0 2 3 4 10 11 15 16 19 20 27 28 30 31 r ? rwb ? srcid pb bnk ? v w reset all zeros figure 13-16. transfer error attributes register (lteatr) table 13-19. lteatr field descriptions bits name description 0?2 ? reserved 3 rwb transaction type for the error 0 the transaction for the error was a write transaction. 1 the transaction for the error was a read transaction. 4?10 ? reserved 11?15 srcid captures the source of the transaction when this information is provided on the internal interface to the lbc. 16?19 pb parity error on byte. there are four parity error status bits, one per byte lane. a bit is set for the byte that had a parity error (bit 16 represents byte 0, the most significant byte lane). table 13-18. lteir field descriptions (continued) bits name description 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-29 13.3.1.14 transfer error address register (ltear) the transfer error address re gister (ltear) is shown in figure 13-17 . table 13-20 describes ltear fields. 13.3.1.15 local bus configuration register (lbcr) the local bus configuration re gister (lbcr) is shown in figure 13-18 . 20?27 bnk memory controller bank. there is one error status bi t per memory controller bank (bit 20 represents bank 0). a bit is set for the local bus memory controller bank that had an error. note that bnk is invalid if the error was not caused by parity checks. 28?30 ? reserved 31 v error attribute capture is valid. indicates that the captured error information is valid 0 captured error attributes and address are not valid 1 captured error attributes and address are valid offset 0x0c0 access: read/write 0 31 r a w reset all zeros figure 13-17. transfer error address register (ltear) table 13-20. ltear field descriptions bits name description 0?31 a transaction address for the error. holds the 32-bit address of the transaction resulting in an error. offset 0x0d0 access: read/write 01 7891011 1314 1516 2324 31 r ldis ? bctlc ahd ? lpbse epar bmt ? w reset all zeros figure 13-18. local bus configuration register table 13-19. lteatr field descriptions (continued) bits name description 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-30 freescale semiconductor table 13-21 describes lbcr fields. table 13-21. lbcr field descriptions bits name description 0 ldis local bus disable 0 local bus is enabled 1 local bus is disabled. no internal transactions will be acknowledged. 1?7 ? reserved 8?9 bctlc defines the use of lbctl 00 lbctl is used as w/r control for gpcm or upm accesses (buffer control). 01 lbctl is used as loe for gpcm accesses only. 10 lbctl is used as lwe for gpcm accesses only. 11 reserved. 10 ahd address hold disable. removes part of the hold time for lad with respect to lale in order to lengthen the lale pulse 0 during address phases on the local bus, the lale signal negates two platform clock periods prior to the address being invalidated. at 666 mhz, this provides 3 ns of additional address hold time at the external address latch. 1 during address phases on the local bus, the lale signal negates one platform clock period prior to the address being invalidated. this halves the address hold time, but extends the latch enable duration. this may be necessary for very high frequency designs. 11?13 ? reserved 14 lpbse enables parity byte select on lgta /lgpl4/lupwait/lpbse signal. 0 parity byte select is disabled. lgta /lgpl4/lupwait/lpbse signal is available for memory control as lgpl4 (output) or lgta /lupwait (input). 1 parity byte select is enabled. lgta /lgpl4/lupwait/lpbse signal is dedicated as the parity byte select output, and lgta /lupwait is disabled. 15 epar determines odd or even parity. writing the memory with epar = 1 and reading the memory with epar = 0 generates parity errors for testing. 0 odd parity 1even parity 16?23 bmt bus monitor timing. defines the bus monitor time-out period. clearing bmt (reset value) selects the maximum count of 2048 bus clock cycles. for non-zero values of bmt, the number of lclk clock cycles to count down before a time-out error is generated is given by: bus cycles = bmt x 8. apart from bmt = 0x00, the minimum value of bmt is 5, corresponding with 40 bus cycles. shorter time-outs may result in spurious errors during sdram operation. 24?31 ? reserved 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-31 13.3.1.16 clock ratio register (lcrr) the clock ratio register sets th e system (ccb) clock to lbc bus frequency ratio. it also provides configuration bits for extra delay cycl es for address and control signals. table 13-22 describes lcrr fields. offset 0x0d4 access: read/write 0 1 2 3 45678 13141516 2728 31 r dbyp ? bufcmdc ? ecl ? eadc ? clkdiv w reset 1 0 0 0 0000000000 0 0 00 00000000001000 figure 13-19. clock ratio register (lcrr) table 13-22. lcrr field descriptions bits name description 0 dbyp dll bypass. this bit should be set when using low bus clock frequencies if the dll is unable to lock. when in dll bypass mode, incoming data is captur ed in the middle of the bus clock cycle.it is recommended that dll bypass mode be used at frequencies of 83 mhz or less. 0 the dll is enabled. 1 the dll is bypassed. 1?reserved 2?3 bufcmdc additional delay cycles for sdram control signals. defines the number of cycles to be added for each sdram command when lsdmr[bufcmd] = 1. 00 4 01 1 10 2 11 3 4?5 ? reserved 6?7 ecl extended cas latency. determines the extended cas latency for sdram accesses when lsdmr[cl] = 00. 00 4 01 5 10 6 11 7 8?13 ? reserved 14?15 eadc external address delay cycles. defines the number of cycles for the assertion of lale. note that lale negates prior to the end of the final loca l bus clock, as controlled by lbcr[ahd]. 00 4 01 1 10 2 11 3 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-32 freescale semiconductor 13.4 functional description the lbc allows the implementation of memory sy stems with very specif ic timing requirements. ? the sdram machine provides an interface to sdrams using bank interleaving and back-to-back page mode to achieve high perfor mance through a multiplexed addr ess/data bus. an internal dll for bus clock generation ensures improved data set-up margins for board designs. ? the gpcm provides interfacing for simpler, lower-performance memories and memory-mapped devices. it has inherently lower performance be cause it does not support bursting. for this reason, gpcm-controlled banks are used primarily fo r boot-loading and access to low-performance memory-mapped peripherals. ? the upm supports refresh timers , address multiplexing of the ex ternal bus and generation of programmable control signal s for row address and column addre ss strobes, to allow for a minimal glue logic interface to drams, burstable srams, and almost any other kind of peripheral. the upm can be used to generate flexible, user-defined timing patterns for cont rol signals that govern a memory device. these patterns define how the external contro l signals behave during a read, write, burst-read, or burst-write access. refresh timers are also av ailable to periodi cally initiate user-defined refresh patterns. 16?27 ? reserved 28?31 clkdiv system (ccb) clock divider. sets the frequen cy ratio between the system (ccb) clock and the memory bus clock. only the values shown in the table below are allowed. note: it is critical that no transactions are being executed via the local bus while clkdiv is being modified. as such, prior to modification, the user must ensure that code is not executing out of the local bus. once lcrr[clkdiv] is writt en, the register should be read, and then an isync should be executed. 0000?0001 reserved 0010 2 0011 reserved 0100 4 0101?0111 reserved 1000 8 1001?1111 reserved table 13-22. lcrr field d escriptions (continued) bits name description 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-33 figure 13-20. basic operation of memory controllers in the lbc each memory bank (chip select) can be assigned to any one of these th ree type of machines through the machine select bits of the ba se register for that bank (br n [msel]), as illustrated in figure 13-20 . if a bank match occurs, the corresponding mach ine (gpcm, sdram or upm) then takes ownership of the external signals that control the access and mainta ins control until the transaction ends. 13.4.1 basic architecture the following sections describe the basic architecture of the lbc. 13.4.1.1 address and ad dress space checking the defined base addresses are written to the br n registers, while the corresponding address masks are written to the or n registers. each time a loca l bus access is requested, the in ternal transaction address is compared with each bank. addresses are decoded by co mparing the 17 msbs of the address, masked by or n [am], with the base address for each bank (br n [ba]). if a match is f ound on a memory controller bank, the attributes defined in the br n and or n for that bank are used to c ontrol the memory access. if a match is found in more than one bank, the lowest- numbered bank handles the memory access (that is, bank 0 has priority over bank 1). 13.4.1.2 external address latch enable signal (lale) the local bus uses a multiplexed a ddress/data bus. therefore, the lbc must distinguish between address and data phases, which take place on the same bus (lad [0:31] signals). the lale signal, when asserted, signifies an address phase during which the lbc drives the memory address on the lad[0:31] signals. address comparator bank select upm a/b/c gpcm msel field signals timing generator mux internal memory access request select 32-bit system external signals sdram machine address 32-bit physical ram address (a) 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-34 freescale semiconductor an external address latch uses this signal to capture the addr ess and provide it to th e address signals of the memory or peripheral device. when lale is negated, lad[0:31] then serves as the (bidirectional) data bus for the access. any address phase initiates the asserti on of lale, which has a programmable duration of between 1 and 4 bus clock cycles. to ensure adequate hold time on the external addre ss latch, lale negate s earlier than the address changes on lad[0:31] during address phases. by default, la le negates earlier by two platform clock periods (which, divided by lcrr[cl kdiv], yields the local bus clock). for example, if the lbc is operating at 666 mhz internally, then an additional 3 ns of a ddress hold time is introduced. however, when lcrr[clkdiv] = 2 and the lclk frequency exceeds 100 mhz, the duration of the shortened lale pulse may not meet the minimum latch enable pulse widt h specifications of some latches. in such cases, setting lbcr[ahd] = 1 increases the lale pulse width by one platform clock cycle, and decreases the address hold time by the same am ount. at 666 mhz and with lcrr[c lkdiv] = 2, the duration of lale would then be 4.5 ns, with 1.5 ns of hold time. if both longer hold time and longer lale pulse duration are needed, then the address phase can be extende d using the orn[ead] a nd lcrr[eadc] fields, and the lbcr[ahd] bit can be left at 0. however, this will add latency to all address tenures. the frequency of lale assertion vari es across the three memory controllers. for gpcm, every assertion of lcs n is considered an independent access, and accord ingly, lale asserts prior to each such access. for example, gpcm driving an 8- bit port would assert lale and lcs n 32 times in order to satisfy a 32-byte cache line transfer. the sdram controller asserts lale only to in itiate a burst transfer with a starting address, therefore no more than one assertion of lale may be required for sdram to transfer a 32-byte cache line through a 32- bit port. in the case of upm, the fr equency of lale assertion depends on how the upm ram is programmed. upm single accesses typically as sert lale once, on commencement, but it is po ssible to program upm to as sert lale several times, an d to change the values of la[27:31] with and without lale being involved. in general, when using the gpcm and sdram controllers it is not necessary to us e la[27:31] if a sufficiently wide la tch is used to capture the entire address during lale phases. upm may require la[27:31] if the lbc is generating its own burst address sequence. to illustrate how a large transaction is handled by the lbc, figure 13-21 shows lbc signals for gpcm performing a 32-byte write starting at address 0x5420. note that during each of the 32 assertions of lale, la[27:31] exactly mirror la d[27:31], but during data pha ses, only lad[0:7] and ld p[0] are driven with valid data and parity, respectively. 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-35 figure 13-21. example of 8-bit gpcm writing 32 bytes to address 0x5420 13.4.1.3 data transf er acknowledge (ta) the three memory controllers in the lbc generate an internal transfer acknowle dge signal, ta, to allow data on lad[0:31] to be either samp led (for reads) or changed (on writ es). the data sampling/data change always occurs at the end of the bus cycle in which the lbc asserts ta internal ly. in lbc debug mode, ta is also visible externally on the mdval signal. gpcm and sdram controllers automatically generate ta according to the timing parameters programmed for them in option and mode registers; a upm generates ta only when a upm pattern has the uta ram word bit set. figure 13-22 shows lale, ta (internal), and lcs n . note that ta and lale ar e never asserted together, and that for the duration of lale, lcs n (or any other control signal ) remains negated or frozen. figure 13-22. basic lbc bus cycle with lale, ta, and lcs n 00 00 00 00 00 00 00 00 01 02 03 1c 1d 1e 1f 0p(b0) 000 00 0 p(b1) p(b2) p(b29) p(b30) p(b31) d(b0) d(b1) d(b2) d(b29) d(b30) d(b31) 54 54 54 54 54 54 54 0 000 0 0 0 20 21 22 23 3f 3e 3d note : all address and signal values are shown in hexadecimal. d(bk) = k th of 32 data bytes, p(bk) = parity bit of k th data byte. lclk lale lcs n lwe la[27:31] lad[0:7] lad[8:31] ldp[0] ldp[1:3] lad lale lcs n ta address data lclk 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-36 freescale semiconductor 13.4.1.4 data buffer control (lbctl) the memory controller provides a data buffer contro l signal for the local bus (lbctl). this signal is activated when a gpcm or upm controlled bank is accessed. lbc tl can be disabled by setting or n [bctld]. access to an sdram machine controll ed bank does not activate the lbctl control. lbctl can be further configured by lb cr[bctlc] to act as an extra lwe or an extra loe signal when in gpcm mode. if lbctl is configured as a data buffer control (lbcr[bctlc] = 00), the signal is asserted (high) on the rising edge of the bus clock on the fi rst cycle of the memory controller operation, coin cident with lale. if the access is a write, lbctl remains high for the whole duration. howe ver, if the access is a read, lbctl is negated (low) with the negation of lale so that the memory device is able to drive the bus. if back-to-back read accesses are pending, lbctl is asse rted (high) one bus clock cycle before the next transaction starts (that is, one bus clock cycle before lale) to allow a whole bus cycle for the bus to turn around before the next address is driven. if an external bus transceiver is used, lbctl should be used to signify the write direction when high. note that the default (reset and bus id le) value of lbctl is also high. 13.4.1.5 atomic operation the lbc supports the following kinds of atomic bus operations (set by br n [atom]): ? read-after-write atomic (rawa) . when a write access hits a memory bank in which atom = 01, the lbc reserves the selected memory bank fo r the exclusive use of the accessing master. while the bank is reserved, no ot her device can be granted access to this bank. the reservation is released when the master that created it accesse s the same bank with a read transaction. additional write transactions prior to the releasing read do not change reservation status, but are otherwise processed normally. if the master fails to releas e the reservation within 256 bus clock cycles, the reservation is released and an atomic error is re ported (if enabled). this feature is intended for cam operations. ? write-after-read atomic (wara) . when a read access hit a me mory bank in which atom = 10, the lbc reserves the bus for the exclusive use of the accessing master. during the reservation period, no other device ca n be granted access to the atomic bank. the reservation is released when the device that created it accesses the same bank with a write transaction. additional read tran sactions prior to the releasi ng write are otherwise processed normally and do not change the reservation status. if the device fails to release the reservation within 256 bus clock cycles, the reservation is releas ed and an atomic error is reported (if enabled). 13.4.1.6 parity genera tion and checking (ldp) parity can be configured for any bank by programming br n [decc]. parity is gene rated and checked on a per-byte basis using ldp[ 0:3] for the bank if br n [decc] = 01 (normal parity) or br n [decc] = 10 for read-modify-write (rmw) parity. byte lane parity on ldp[0:3] is generated regardless of the br n [decc] setting. note that rmw parity can be used only for 32-bit port size banks. lbcr[epar] determines the global type of parity (odd or even). 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-37 13.4.1.7 bus monitor a bus monitor is provided to ensure that each bus cy cle is terminated within a reasonable (user defined) period. when a transaction starts , the bus monitor starts counti ng down from the time-out value (lbcr[bmt]) until a data b eat is acknowledged on the bus . it then reloads the ti me-out value and resumes the countdown until the data tenure completes and th en idles if there is no pending transaction. setting ltedr[bmd] disables bus monitor error checking (i.e ,. the ltesr[bm] bit is not set by a bus monitor time-out); however, the bus monito r is still active and can generate a upm exception (as noted in section 13.4.4.1.4, ?exception requests ?) or terminate a gpcm access. it is very important to ensure that the value of lbcr[bmt] is not set too lo w; otherwise spurious bus time-outs may occur duri ng normal operation?particular ly for sdrams? resulting in incomplete data transfers. accordingly, apart from the reset value of 0x00 (corresponding with the maximum time-out of 2048 bus cycles), lbcr[bmt] must not be set be low 0x05 (or 40 bus cycles for time-out) under any circumstances. 13.4.2 general-purpose chip-select machine (gpcm) the gpcm allows a minimal glue logic and fl exible interface to sram, eprom, feprom, rom devices, and external peri pherals. the gpcm contains two ba sic configuration register groups?br n and or n . figure 13-23 shows a simple connection between an 8-b it port size sram device and the lbc in gpcm mode. byte-write enable signals (lwe ) are available for each byte writ ten to memory. also, the output enable signal (loe ) is provided to minimize external glue logic. on system reset, a global (boot) chip-select is available that pr ovides a boot rom chip-select (lcs0 ) prior to the system being fully configured. figure 13-23. local bus to gpcm device interface ce oe w data[7:0] memory/peripheral lale lwe0 loe lcs n la[30:31] la[27:29] lad[12:26] a[19:5] a[4:2] a[1:0] lbc in gpcm mode latch lad[0:7] 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-38 freescale semiconductor figure 13-24 shows lcs as defined by the setup time require d between the address lines and lcs . the user can configure or n [acs] to specify lcs to meet this requirement. figure 13-24. gpcm basic read timing (xacs = 0, acs = 1x, trlx = 0, clkdiv = 4, 8) 13.4.2.1 timing configuration if br n [msel] selects the gpcm, the attributes for the memory cycle are taken from or n . these attributes include the csnt, acs, xacs , scy, trlx, ehtr, and seta fields. table 13-23 shows signal behavior and system response for a write access with lcrr[clkdiv] = 4 or lcrr[clkdiv] = 8. table 13-23. gpcm write control signal timing for lcrr[clkdiv] = 4 or 8 option register attributes sign al behavior (bus clock cycles) trlx xacs acs csnt address to lcs n asserted lcs n negated to address change lwe negated to address/data invalid total cycles 1 0 0 00 0 0 0 0 3+scy 0 0 10 0 1/4 0 0 3+scy 0 0 11 0 1/2 0 0 3+scy 0 1 00 0 0 0 0 3+scy 0 1 10 0 1 0 0 3+scy 0 1 11 0 2 0 0 4+scy 0 0 00 1 0 0 ?1/4 3+scy 0 0 10 1 1/4 ?1/4 ?1/4 3+scy 0 0 11 1 1/2 ?1/4 ?1/4 3+scy 0 1 00 1 0 0 ?1/4 3+scy 0 1 10 1 1 ?1/4 ?1/4 3+scy 0 1 11 1 2 ?1/4 ?1/4 4+scy lclk lad lale lcs n loe address read data a[19:5] latched address ta acs = 11 acs = 10 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-39 table 13-24 shows the signal behavior and system re sponse for a read access with lcrr[clkdiv] = 4 or lcrr[clkdiv] = 8. 1 0 00 0 0 0 0 3+2*scy 1 0 10 0 1+1/4 0 0 4+2*scy 1 0 11 0 1+1/2 0 0 4+2*scy 1 1 00 0 0 0 0 3+2*scy 1 1 10 0 2 0 0 4+2*scy 1 1 11 0 3 0 0 5+2*scy 1 0 00 1 0 0 ?1?1/4 4+2*scy 1 0 10 1 1+1/4 ?1?1/4 ?1?1/4 5+2*scy 1 0 11 1 1+1/2 ?1?1/4 ?1?1/4 5+2*scy 1 1 00 1 0 0 ?1?1/4 4+2*scy 1 1 10 1 2 ?1?1/4 ?1?1/4 5+2*scy 1 1 11 1 3 ?1?1/4 ?1?1/4 6+2*scy 1 total cycles when lale is a sserted for one cycle only (or n [ead] = 0; or n [ead] = 1 and lcrr[eadc] = 01). asserting lale for more than one cycle in creases the total cycl e count accordingly. table 13-24. gpcm read control sign al timing for lcrr[clkdiv] = 4 or 8 option register attributes sign al behavior (bus clock cycles) trlx ehtr xacs acs address to lcs n asserted lcs n negated to address change total cycles 1 0 0 0 00 0 1 4+scy 0 0 0 10 1/4 1 4+scy 0 0 0 11 1/2 1 4+scy 0 0 1 00 0 1 4+scy 0 0 1 10 1 1 4+scy 0 0 1 11 2 1 5+scy 0 1 0 00 0 2 5+scy 0 1 0 10 1/4 2 5+scy 0 1 0 11 1/2 2 5+scy 0 1 1 00 0 2 5+scy 0 1 1 10 1 2 5+scy 0 1 1 11 2 2 6+scy table 13-23. gpcm write control signal timing for lcrr[clkdiv] = 4 or 8 (continued) option register attributes sign al behavior (bus clock cycles) trlx xacs acs csnt address to lcs n asserted lcs n negated to address change lwe negated to address/data invalid total cycles 1 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-40 freescale semiconductor table 13-25 and table 13-26 show the write and read signa l behavior, respectively, when lcrr[clkdiv] = 2. 1 0 0 00 0 5 8+2*scy 1 0 0 10 1+1/4 5 9+2*scy 1 0 0 11 1+1/2 5 9+2*scy 1 0 1 00 0 5 8+2*scy 1 0 1 10 2 5 9+2*scy 10111 3 5 10+2*scy 11000 0 9 12+2*scy 1 1 0 10 1+1/4 9 13+2*scy 1 1 0 11 1+1/2 9 13+2*scy 11100 0 9 12+2*scy 11110 2 9 13+2*scy 11111 3 9 14+2*scy 1 total cycles when lale is a sserted for one cycle only (or n [ead] = 0; or n [ead] = 1 and lcrr[eadc] = 01). asserting lale for more than one cycle increases the total cycle count accordingly. table 13-25. gpcm write control signal timing for lcrr[clkdiv] = 2 option register attributes sign al behavior (bus clock cycles) trlx xacs acs csnt address to lcs n asserted lcs n negated to address change lwe negated to address/data invalid total cycles 1 0 0 00 0 0 0 0 3+scy 0 0 10 0 1/2 0 0 3+scy 0 0 11 0 1/2 0 0 3+scy 0 1 00 0 0 0 0 3+scy 0 1 10 0 1 0 0 3+scy 0 1 11 0 2 0 0 4+scy 0 0 00 1 0 0 0 3+scy 0 0 10 1 1/2 0 0 3+scy 0 0 11 1 1/2 0 0 3+scy 0 1 00 1 0 0 0 3+scy 0 1 10 1 1 0 0 3+scy 0 1 11 1 2 0 0 4+scy table 13-24. gpcm read control signal timing for lcrr[clkdiv] = 4 or 8 (continued) option register attributes sign al behavior (bus clock cycles) trlx ehtr xacs acs address to lcs n asserted lcs n negated to address change total cycles 1 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-41 1 0 00 0 0 0 0 3+2*scy 1 0 10 0 1+1/2 0 0 4+2*scy 1 0 11 0 1+1/2 0 0 4+2*scy 1 1 00 0 0 0 0 3+2*scy 1 1 10 0 2 0 0 4+2*scy 1 1 11 0 3 0 0 5+2*scy 10001 0 0 ?1 4+2*scy 1 0 10 1 1+1/2 ?1 ?1 5+2*scy 1 0 11 1 1+1/2 ?1 ?1 5+2*scy 11001 0 0 ?1 4+2*scy 1 1 10 1 2 ?1 ?1 5+2*scy 1 1 11 1 3 ?1 ?1 6+2*scy 1 total cycles when lale is a sserted for one cycle only (or n [ead] = 0; or n [ead] = 1 and lcrr[eadc] = 01). asserting lale for more than one cycle in creases the total cycl e count accordingly. table 13-26. gpcm read control signal timing for lcrr[clkdiv] = 2 option register attributes sign al behavior (bus clock cycles) trlx ehtr xacs acs address to lcs n asserted lcs n negated to address change total cycles 1 0 0 0 00 0 1 4+scy 0 0 0 10 1/2 1 4+scy 0 0 0 11 1/2 1 4+scy 0 0 1 00 0 1 4+scy 0 0 1 10 1 1 4+scy 0 0 1 11 2 1 5+scy 0 1 0 00 0 2 5+scy 0 1 0 10 1/2 2 5+scy 0 1 0 11 1/2 2 5+scy 0 1 1 00 0 2 5+scy 0 1 1 10 1 2 5+scy 0 1 1 11 2 2 6+scy 1 0 0 00 0 5 8+2*scy 1 0 0 10 1+1/2 5 9+2*scy table 13-25. gpcm write control signal timing for lcrr[clkdiv] = 2 (continued) option register attributes sign al behavior (bus clock cycles) trlx xacs acs csnt address to lcs n asserted lcs n negated to address change lwe negated to address/data invalid total cycles 1 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-42 freescale semiconductor 13.4.2.2 chip-select assertion timing the banks selected to work with the gpcm support an option to drive the lcs n signal with different timings (with respect to the ex ternal address/data bus). lcs n can be driven in any of the following ways: ? simultaneous with the latched memo ry address. (this refers to the externally latched address, not the address timing on lad[0:31]. that is, ch ip select does not assert during lale). ? one quarter of a clock cycle la ter (for lcrr[clkdiv] = 4 or 8). ? one half of a clock cycle late r (for lcrr[clkdiv] = 2, 4 or 8). ? one clock cycle later (f or lcrr[clkdiv] = 4) when or n [xacs] = 1. ? two clock cycles later (for l crr[clkdiv] = 2, 4 or 8), when or n [xacs] = 1. ? three clock cycles later (for lcrr[clkdiv] = 2, 4 or 8), when or n [xacs] = 1 and or n [trlx] = 1. the timing diagram in figure 13-24 shows two chip-select asse rtion timings for the case lcrr[clkdiv] = 4 or 8. if lcrr[clkdiv] = 2, lcs n asserts identically for or n [acs] = 10 or 11. 13.4.2.2.1 programmable wa it state configuration the gpcm supports internal generation of transfer ack nowledge. it allows betwee n zero and 30 wait states to be added to an access by programming or n [scy] and or n [trlx]. internal gene ration of transfer acknowledge is enabled if or n [seta] = 0. if lgta is asserted externally tw o bus clock cycles or more before the wait state count er has expired (to allow for synchronizat ion latency), the current memory cycle is terminated by lgta ; otherwise it is terminated by the expira tion of the wait state counter. regardless of the setting of or n [seta], wait states prolong the assertion duration of both loe and lwe n in the same 1 0 0 11 1+1/2 5 9+2*scy 1 0 1 00 0 5 8+2*scy 1 0 1 10 2 5 9+2*scy 10111 3 5 10+2*scy 11000 0 9 12+2*scy 1 1 0 10 1+1/2 9 13+2*scy 1 1 0 11 1+1/2 9 13+2*scy 11100 0 9 12+2*scy 11110 2 9 13+2*scy 11111 3 9 14+2*scy 1 total cycles when lale is asserted for 1 cycle only (or n [ead] = 0; or n [ead] = 1 and lcrr[eadc] = 01). asserting lale for more than 1 cycle in creases the total cycl e count accordingly. table 13-26. gpcm read control signal timing for lcrr[clkdiv] = 2 (continued) option register attributes sign al behavior (bus clock cycles) trlx ehtr xacs acs address to lcs n asserted lcs n negated to address change total cycles 1 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-43 manner. when trlx = 1, the number of wait states inserted by the memo ry controller is doubled from or n [scy] cycles to 2 or n [scy] cycles, allowing a maxi mum of 30 wait states. 13.4.2.2.2 chip-select and wri te enable negation timing figure 13-23 shows a basic connection betwee n the local bus and a static me mory device. in this case, lcs n is connected directly to ce of the memory device. the lwe [0:3] signals are connected to the respective we [3:0] signals on the memo ry device where each lwe [0:3] signal corresponds to a different data byte. figure 13-25. gpcm basic write timing (xacs = 0, acs = 00, csnt = 1, scy = 1, trlx = 0, clkdiv = 4 or 8) as figure 13-25 shows, the timing for lcs n is the same as for the latched address. the strobes for the transaction are supplied by loe or lwe n , depending on the transaction dire ction?read or write (write case shown in figure 13-25 ). or n [csnt] controls the timing for the appropriate strobe negation in write cycles. when this attribute is asserted, the strobe is negated one qua rter of a clock before the normal case provided that lcrr[clkdiv] = 4 or 8. for exam ple, when acs = 00 and csnt = 1, lwe n is negated one quarter of a clock earlier, as shown in figure 13-25 . if lcrr[clkdiv] = 2, lwe n is negated either coincident with lcs n or one cycle earlier. 13.4.2.2.3 relaxed timing or x [trlx] is provided for memory systems that requi re more relaxed timing between signals. setting trlx = 1 has the following effect on timing: ? an additional bus cycle is adde d between the address and cont rol signals (but only if acs 00). ? the number of wait states specified by scy is doubled, providing up to 30 wait states. ? the extended hold time on read ac cesses (ehtr) is extended further. ?lcs n signals are negated 1 cycle earlier during wr ites (but only if acs 00). ?lwe [0:3] signals are negated 1 cycle earlier during writes. lclk lad lale lcs n lwe n address write data a latched address ta loe csnt = 1 scy = 1 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-44 freescale semiconductor figure 13-26 and figure 13-27 show relaxed timing read and wr ite transactions. the effect of clkdiv = 2 for these examples is on ly to delay the assertion of lcs n in the acs = 10 case to the acs = 11 case. the example in figure 13-27 also shows address and data multiplexing on lad[0:31] for a pair of writes issued consecutively. figure 13-26. gpcm relaxed timing read (xacs = 0, acs = 1x, scy = 1, ehtr = 0, trlx = 1) figure 13-27. gpcm relaxed timing back-to-back writes (xacs = 0, acs = 1x, scy = 0, csnt = 0, trlx = 1, clkdiv = 4 or 8) when trlx and csnt are set in a write access, the lwe [0:3] strobe signals are negated one clock earlier than in the normal case, as shown in figure 13-28 and figure 13-29 . if acs 00, lcs n is also negated one clock earlier. lclk lad lale lcs n lbctl a latched address ta loe address read data acs = 10 acs = 11 address scy = 1, trlx = 1 lclk lad lale lcs n lbctl address 1 a latched address 1 ta lwe n acs = 10 write data 1 loe acs = 11 address 2 latched address 2 write data 2 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-45 figure 13-28. gpcm relaxed timing write (xacs = 0, acs = 10, scy = 0, csnt = 1, trlx = 1, clkdiv = 4 or 8) figure 13-29. gpcm relaxed timing write (xacs = 0, acs = 00, scy = 1, csnt = 1, trlx = 1, clkdiv = 4 or 8) 13.4.2.2.4 output enable (loe ) timing the timing of loe is affected only by trlx. it always asserts and negates on the rising edge of the bus clock. loe asserts either on the rising edge of the bus clock after lcs n is asserted or coinciding with lcs n (if xacs = 1 and acs = 10 or 11). accordingly, assertion of loe can be delayed (along with the lclk lad lale lcs n lbctl address a latched address ta lwe n acs = 10 write data loe csnt = 1 lclk lad lale lcs n lbctl address a latched address ta lwe n write data loe csnt = 1 scy = 1, trlx = 1 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-46 freescale semiconductor assertion of lcs n ) by programming trlx = 1. loe negates on the rising clock edge coinciding with lcs n negation 13.4.2.2.5 extended hold time on read accesses slow memory devices that take a long time to disa ble their data bus drivers on read accesses should choose some combination of or n [trlx,ehtr]. any access following a read access to the slow er memory bank is delayed by the number of clock cycles specified by the configuration of or n [trlx,ehtr], as described in section 13.3.1.2.2, ?option regi sters (orn)?gpcm mode,? in addition to any existing bus turnaround cycle. the final bus turnaround cycle is auto matically inserted by the lbc for reads, regardless of the setting of or n [ehtr]. figure 13-30 , and figure 13-31 present various gpcm timing examples. figure 13-30. gpcm read followed by read (trlx = 0, ehtr = 0, fastest timing) lclk lad lale lcs n lbctl address 1 a latched address 1 ta loe read data 1 address 2 data 2 latched address 2 lcsy bus turnaround 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-47 figure 13-31. gpcm read followed by write (trlx = 0, ehtr = 1, 1-cycle extended hold time on reads) 13.4.2.3 external access termination (lgta ) external access termination is supporte d by the gpcm using the asynchronous lgta input signal, which is synchronized and sampled internally by the local bus. if, duri ng assertion of lcs n , the sampled lgta signal is asserted, it is converted to an internal ge neration of transfer acknowle dge, which terminates the current gpcm access (regardle ss of the setting of or n [seta]). lgta should be asserted for at least one bus cycle to be effective. note that because lgta is synchronized, bus terminat ion occurs two cycles after lgta assertion, so in the case of a read cycle, the device still mu st drive data as long as loe is asserted. the user selects whether transf er acknowledge is generated inte rnally or externally (lgta ) by programming or n [seta]. asserting lgta always terminates an access, even if or n [seta] = 0 (internal transfer acknowledge gene ration), but it is the only means by which an access can be terminated if or n [seta] = 1. the timing of lgta is illustrated by the example in figure 13-32 . lclk lad lale lcs n lbctl rd. address a latched read address ta loe wr. address wr. address lcsy extended hold bus turnaround wr. data read data 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-48 freescale semiconductor figure 13-32. external termination of gpcm access 13.4.2.4 boot chip-select operation boot chip-select operation allows address decoding for a boot rom before system initialization. lcs0 is the boot chip-select output; its operation differs from other exte rnal chip-select outputs after a system reset. when the core begins accessing me mory after system reset, lcs0 is asserted for every local bus access until br0 or or0 is reconfigured. the boot chip-select also provides a programmable port size, which is c onfigured during reset. the boot chip-select does not provi de write protection. lcs0 operates this way until the first write to or0 and it can be used as any other chip-select register after the prefer red address range is loaded into br0. after the first write to or0, the boot chip-select can be restarted only with a hardware reset. table 13-27 describes the initial values of the boot bank in the memory controller. table 13-27. boot bank field values after reset register field setting register field setting br0 ba ps decc wp msel ato m v 0000_0000_0000_0000_0 from signal during reset. 00 0 000 00 1 or0 am bctld csnt acs xacs scy seta trlx ehtr ead 0000_0000_0000_0000_0 0 1 11 1 1111 0 1 1 1 lclk lad lale lcs n lbctl address a latched address ta loe lgta read data 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-49 13.4.3 sdram machine the lbc provides an sdram interface (machine) for the local bus. the machine provides the control functions and signals for intel pc133 and jedec-comp liant sdram devices. each bank can control an sdram device on the local bus. 13.4.3.1 supported sd ram configurations the memory controller suppor ts any sdram configurati on with the restrictions that all sdram devices that reside on the bus should have the same port si ze and timing parameters (as defined in lsdmr). figure 13-33 shows an example connection between the lbc and a 32-bit sdram de vice with 12 address lines. note that address signals a[ 2:0] of the sdram conne ct directly to la[27: 29], address signal a10 connects to the lbcs dedicated lsda 10 signal, while the remaining addr ess bits (except a10) are latched from lad[20:26]. figure 13-33. connection to a 32-bit sdram with 12 address lines 13.4.3.2 sdram power-on initialization following a system reset, initialization software must set up the programmable parameters in the memory controller banks registers (or n , br n , lsdmr). after all memory para meters are configured, system software should execute the following init ialization sequence for each sdram device. ? issue a precharge- all-banks command ? issue eight auto-refresh commands lsda10 lsddqm [0:3] lcs1 lad[0:31] sdram local bus latch memory address lale lsdwe 32-bit port size lsdras lsdcas controller lcke lclk la[27:29] we ras cas cs dqm[3:0] a10 a[11,9:3] dq[31:0] clk cke a[2:0] lad[18,20:26] memory data 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-50 freescale semiconductor ? issue a mode-set command to initialize the mode register the initial commands are executed by setting lsdmr[op] and accessing the sdram with any write that hits the relevant bank. since the resu lt of any update to the lsdmr must be in eff ect before accessing the sdram with any write, a write to lsdmr should be followed immediately by a read from lsdmr, which must complete prior to an initial write to sdram. further, the first write to sdram should be followed immediately by an sdram read, which must complete prior to additional lsdmr updates. this enforces a proper ordering between updates to the lsdmr and write accesses to the sdram. if the initialization is being done by the e500, this described protocol is guaranteed only if the sdram is mapped as cache-inhibited and guar ded, as the ccsr memory region c ontaining lsdmr should be. if the initialization is from an external host, said hos t must ensure completion of lsdmr and sdram reads prior to subsequent writes, as described above. note that software should ensure that no memory operations begin until th is process completes. note in general (not only during power- on reset) the lsdmr/sdram access ordering protocol should be observed for proper operation. 13.4.3.3 intel pc133 and jedec-st andard sdram in terface commands the sdram machine performs all accesses to sdram by using intel pc133 and jedec-standard sdram interface commands. the sd ram device samples the command and data inputs on the rising edge of the bus clock. data at the output of the sdram device is sampled on th e rising edge of the bus clock. the following sdram interface co mmands are provided by setting lsdmr[op] to a non-zero value (lsdmr[op] = 000 sets norma l read/write operation): table 13-28. sdram interface commands command (lsdmr[op]) description activate (110) latches the row address and initiates a memory read of that row. row data is latched in sdram sense amplifiers and must be restored with a precha rge command before another activate is issued. mode-set (011) allows setting of sdram options?cas latency and burst length. cas latency depends on the sdram device used. although some sdrams provide burst length s of 1, 2, 4, 8, or a page, the local bus memory controller supports only 8-beat bursts for 8-bit and 32-b it port size, or 4-beat bursts for 16-bit port size. the lbc does not support burst lengths of 1, 2 and a pag e for sdrams. the mode register data (cas latency and burst length) is programmed into the lsdmr regist er by initialization software after reset. after the lsdmr is set, the lbc transfers the information to the sdram device by issuing a mode-set command. precharge (100: single bank) (101: all-banks) restores data from the sense amplifiers to the appropr iate row in the sdram device array. also initializes the sense amplifiers to prepare for activating another row in the sdram device. note that the lbc uses lsda10 to distinguish between precharge-all-banks (lsda10 is high) and precharge-single-bank (lsda10 is low). the s drams must be compatible with this format. read (111) latches the column address and transfers data from t he selected sense amplifier on the sdram device, to the output buffer as determined by the column address. during each successive clock, additional data is driven without additional read commands. at the en d of the burst, the page remains open. burst length is the one set for this bank. read data is discarded by the lbc. 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-51 13.4.3.4 page hit checking the sdram machine supports page-mode operation. e ach time a page is activated on the sdram device, the sdram machine stores it s address in a page register. the page information, which the user writes to the or n register, is used along with th e bank size to compare page bits of the address to the page register each time a bus-cycle access is requested. if a match is found, t ogether with a bank match, the bus cycle is defined as a page hit. an open page is automatically closed by the sdram machine if the bus becomes idle, unless or n [pmsel] = 1. 13.4.3.5 page management the lbc can manage at most four open pages (one page per sdram bank) fo r a single sdram device. after a page is opened, it remains open unless: ? the next access is to a page in a different sdram device, in which case all open pages on the current device are closed with a precharge-all-banks command. ? the next access is to a page in an sdram bank that has a differen t page open on it, in which case the old page is closed with a precharge-single-bank command. ? the current sdram device requires refresh serv ices, in which case all open pages on the current device are closed with a precharge-all-banks command. ? the bus becomes idle and or n [pmsel] = 0, in which case all open pages in the current device are closed with a precharge-all-banks command. 13.4.3.6 sdram address multiplexing the lower address bus bits are connect ed to the memory device?s addre ss port with the memory controller multiplexing the row/column and the internal bank sel ect lines. the position of the bank select lines are set according to lsdmr[bsma]. figure 13-34 shows how the sdram controll er shifts the row address down to the lower output address sign als during activate and shifts the ba nk select bits up to the address write (111) latches the column address and transfers data from t he data signals to the selected sense amplifier on the sdram device, as determined by the column address. during each successive clock, additional data is transferred to the sense amplifiers from the data si gnals without additional write commands. at the end of the burst, the page remains open. burst lengt h is the one set for this bank. lsddqm [0:3] are inactive and write data is undefined. auto-refresh (001) causes a row to be read in all memory banks (jedec sdram) as determined by the refresh row address counter (similar to cbr). the refresh row address counter is internal to the sdram device. after being read, a row is automatically rewritten into the memory array. all banks must be in a precharged state before executing refresh. self-refresh (010) allows data to be retained in the sdram device, even when the rest of the lbc is in a power saving mode with clocks turned off. when placed in this mode, the sdram device is capable of issuing its own refresh commands, without external clocking from the lbc and the lcke signal from the lbc is negated. this command can be issued at any time. normal operat ion can be resumed only by setting lsdmr[op] = 000, and waiting a minimum of 200 bus cycles bef ore issuing reads or writes to the lbc. table 13-28. sdram interface commands (continued) command (lsdmr[op]) description 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-52 freescale semiconductor signals specified by lsdmr[bsma], supporting page -based interleaving. the lsb of the logical row address (a n in figure 13-34 ) is aligned with the connected lsb of lad (bits 29, 30, and 31 for port sizes of 32, 16, and 8 bits, respectively). figure 13-34. sdram address multiplexing note that during normal operation (re ad/write), a full 32-bi t address that includes row and column is generated on lad[0:31]. however, address/data signa l multiplexing implies that the address must be latched by an external latch that is controlled by lale. all sdram device address signals need to be connected to the latched address bits and burst address bits (la[27:31]) of the lbc, with the exception of a10, which has a dedicated connect ion on lsda10. lsda10 is driven wi th the appropriate row address bit for sdram commands that require a10 to be an address. 13.4.3.7 sdram device -specific parameters the software is responsible for sett ing correct values for de vice-specific parameters that can be extracted from the device?s data sheet. th e values are stored in the or n and lsdmr registers. these parameters include the following: ? precharge to activate in terval (lsdmr[pretoact]) ? activate to read/write interval (lsdmr[acttorw]) ? cas latency, column address to firs t data out (lsdmr[cl] and lcrr[ecl]) ? write recovery, last data in to precharge (lsdmr[wrc]) ? refresh recovery interval (lsdmr[rfrc]) ? external buffers on the control lines pr esent (lsdmr[bufcmd] and lcrr[bufcmdc]) in addition, the lbc hardware ensures a default activ ate to precharge interval of 10 bus cycles. the following sections describe sdram parameters programmed in lsdmr. row column activate address (ras ): msbs bs lsbs row lsbs bs to memory device signals, 031 logical address: lsbs bs row column r/w address (cas ): ? a n except a10 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-53 13.4.3.7.1 precharge-to-activate interval the precharge-to-activate interval parameter, cont rolled by lsdmr[pretoact], defines the earliest timing for an activate or refresh command af ter a precharge command to the same sdram bank. figure 13-35. pretoact = 2 (2 clock cycles) 13.4.3.7.2 activate-to -read/write interval this parameter, controlled by lsdmr[acttorw], defines the earliest ti ming for a read/write command after an activate command to the same sdram bank. figure 13-36. acttorw = 2 (2 clock cycles) 1111 0000 1111 z zzzzzzz ras add xxxxx cas add d0 zzzzzzzz lclk lale lcs n lsdras lsdcas lsdwe lsddqm [0:3] lad[0:31] pretoact = 2 precharge command bank a activate command bank a ras add 1111 0000 1111 zzzzzzzz ras add xxxx cas add d0 zzzzzzzz lclk lale lcs n lsdras lsdcas lsdwe lsddqm [0:3] lad[0:31] d1 d2 d3 acttorw = 2 activate write command command 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-54 freescale semiconductor 13.4.3.7.3 column address to fi rst data out?cas latency this parameter, controlled by lsdmr[cl] for late ncy of 1, 2, or 3 and by lcrr[ecl] for latency of more than 3, defines the timing for first read data after a column address is sampled by the sdram. figure 13-37. cl = 2 (2 clock cycles) 13.4.3.7.4 last data in to precharge?write recovery this parameter, controlled by lsdmr[wrc], defi nes the earliest timing for a precharge command after the last data was written to the sdram. figure 13-38. wrc = 2 (2 clock cycles) 1111 0000 1111 zzzzzzzz ras add zzzzzzzz cas add d0 d1 d2 lclk lale lcs n lsdras lsdcas lsdwe lsddqm [0:3] lad[0:31] d3 xxxx cl = 2 read first data out command 1111 0000 1111 zzzzzzzz cas add d0 ras add cas add lclk lale lcs n lsdras lsdcas lsdwe lsddqm [0:3] lad[0:31] d1 d2 d3 x 0000 d0 d1 last data in precharge command write command wrc = 2 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-55 13.4.3.7.5 refresh recovery interval (rfrc) this parameter, controlled by lsdmr[rfrc], de fines the earliest timing for an activate or refresh command after a refresh command to the same sdram device. figure 13-39. rfrc = 4 (6 clock cycles) 13.4.3.7.6 external address and command buffers (bufcmd) if the additional delay of any buffers placed on the command strobes (lsdras , lsdcas , lsdwe , and lsda10), is endangering th e device setup time, lsdm r[bufcmd] should be set. setting this bit causes the memory controller to add lcrr[bufcmdc] extr a bus cycles to the asse rtion of sdram control signals (lsdras , lsdcas , lsdwe , and lsda10) for each sdram command. figure 13-40. bufcmd = 1, lcrr[bufcmdc] = 2 13.4.3.8 sdram interface timing the following figures show sdram t iming for various types of accesses. 1111 zzzzzzzz ras add xxxx cas add lclk lale lcs n lsdras lsdcas lsdwe lsddqm [0:3] lad[0:31] rfrc = 4 (6 clocks) auto refresh command activate command precharge all command (if needed) pretoact = 3 1111 1111 0000 1111 zzzzzz ras add xxxxxxxx cas add d3 zzzzzzzz lclk lale lcs n lsdras lsdcas lsdwe lsddqm lad d0 d1 d2 xxxx command setup cycle command setup cycle 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-56 freescale semiconductor figure 13-41. sdram single-beat read, page closed, cl = 3 figure 13-42. sdram single-beat read, page hit, cl = 3 figure 13-43. sdram two-beat burst read, page closed, cl = 3 figure 13-44. sdram four-beat burst read, page miss, cl = 3 1111 0000 1111 zzzzzzzz zzzzzzzz zzzzzzzz d0 zzzzzzzz lclk lale lcs n lsdras lsdcas lsdwe lsddqm [0:3] lad[0:31] col add row add ta 1111 0000 1111 zzzzzzzz col add zzzzzzzz lclk lale lcs n lsdras lsdcas lsdwe lsddqm [0:3] lad[0:31] ta d0 1111 0000 1111 zzzzzzzz zzzzzzzz zzzzzzzz d0 zzzzzzzz lclk lale lcs n lsdras lsdcas lsdwe lsddqm [0:3] lad[0:31] col add row add ta d1 1111 0000 1111 zzzzzzzz row add zzzzzzzz col add zzzzzzzz d0 zzzzzzzz lclk lale lcs n lsdras lsdcas lsdwe lsddqm [0:3] lad[0:31] ta d1 d2 d3 deactivate activate zzzzzzzz 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-57 figure 13-45. sdram single-beat write, page hit figure 13-46. sdram three-beat write, page closed figure 13-47. sdram read-after-read pipelined, page hit, cl = 3 figure 13-48. sdram write-after-write pipelined, page hit 1111 0000 1111 zzzzzzzz col add d0 zzzzzzzz lclk lale lcs n lsdras lsdcas lsdwe lsddqm [0:3] lad[0:31] ta 1111 0000 1111 zzzzzzzz ras add xxxxxxxx col add d0 d1 d2 zzzzzzzz lclk lale lcs n lsdras lsdcas lsdwe lsddqm [0:3] lad[0:31] ta 1111 0000 1111 0000 1111 z col add 1 z d0 d1 z col add 2 z x d0 d1 lclk lale lcs n lsdras lsdcas lsdwe lsddqm [0:3] lad[0:31] ta 1111 0000 1111 0000 z col add 1 d0 d1 d2 d3 col add 2 d0 d1 d2 d3 lclk lale lcs n lsdras lsdcas lsdwe lsddqm [0:3] lad[0:31] ta z 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-58 freescale semiconductor figure 13-49. sdram read-after-write pipelined, page hit 13.4.3.9 sdram read/write transactions the sdram interface supports read an d write transactions of between 1 and 8 data beats for transaction sizes ranging from 1 to 32 bytes. a full burst is pe rformed for each transaction, with the burst length dependent on the port size. a maximum burst of 8 beats is used for an 8-bit or 32-bit port size, while a maximum burst of 4 beats is used for a 16-bit port size, as programmed in lsdmr[bl]. for reads that require less than the full burst length, extraneous data in the burst is ignored and suppressed by the assertion of lsddqm [0:3]. for writes that require less th an the full burst length, the non-targeted addresses are protected by driving corresponding lsddqm bits high (inactive) on the irrelevant cycles of the burst. however, system performa nce is not compromised because, if a new transaction is pending, the sdram controller begins executi ng it immediately, effectively terminating the burst early. 13.4.3.10 sdram mode-set command timing the lbc transfers mode register data (cas latency and burst length) stor ed in the lsdmr register to the sdram device by issuing the mo de-set command, as shown in figure 13-50 . in this case, the latched address carries the mode bits for the command. figure 13-50. sdram mode-set command 13.4.3.11 sdram refresh the memory controller supplies auto-refresh commands to any c onnected sdram device according to the interval specified in lsrt (and prescaled by mrtpr[ptp]). this represents the time period required between refreshes. the values of lsrt and mrtpr depend on the specific sdram devices used and the system clock frequency of the lbc. this value should allow for a potential collision 0000 1111 0000 1111 z col add 1 d0 d1 d2 d3 col add 2 z d0 d1 d2 d3 z lclk lale lcs n lsdras lsdcas lsdwe lsddqm [0:3] lad[0:31] ta 1111 1111 zzzzzzzz mode zzzzzzzz lclk lale lcs n lsdras lsdcas lsdwe lsddqm [0:3] lad[0:31] mode-set command 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-59 between memory accesses and refresh cycles. the period of the refresh interval must be greater than the access time to ensure that read and write operations complete successfully. there are two levels of refresh re quest priority?low and high. the low priority request is generated as soon as the refresh timer expires; th is request is granted only if no othe r requests to the memory controller are pending. if the request is not granted (memory controller is busy) and the refresh timer expires two more times, the request becomes high priority and is served when the current me mory controller operation finishes. 13.4.3.11.1 sdram refresh timing the sdram memory controller implements bank stagge ring for the auto refresh function. this reduces instantaneous current consumpti on for memory refresh operations. after a refresh request is granted, the memory c ontroller begins issuing an auto-refresh command to each device associated with the refresh timer. afte r a refresh command is issu ed to an sdram device, the memory controller waits for the number of bus clock cycles programmed in the s dram machine?s mode register (lsdmr[rfcr]) before issuing a ny subsequent activate command to the same device. to avoid viol ating sdram device timing constraints, the user should ensure that the refresh request interval, defined by lsrt and mrtpr, is greater than the refresh recovery interval, defined by lsdmr[rfcr]. figure 13-51. sdram bank-staggered auto-refresh timing 13.4.4 user-programmable machines (upms) upms are flexible interfaces that connect to a wide ra nge of memory devices. at the heart of each upm is an internal ram array that spec ifies the logical value driven on th e external memory control signals (lcs n , lbs [0:3], and lgpl[0:5]) for a give n clock cycle. each word in th e ram array provides bits that allow a memory access to be controlled with a resolu tion of up to one quarter of the external bus clock period on the byte select and chip select lines. 1111 0000 1111 z row add x col add d0 z lclk lale lcs1 lcs2 lcs3 lcs4 lsdras lsdcas lsdwe lsddqm [0:3] lad[0:31] ta auto ref auto ref auto ref auto ref activate lsdmr[rfcr] 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-60 freescale semiconductor note if the lgpl4/lgta /lupwait/lpbse signal is used as both an input and an output, a weak pull-up is required. refe r to the hardware specification for details regarding termination options. figure 13-52 shows the basic operation of each upm. figure 13-52. user-programmable machine functional block diagram the following events initiate a upm cycle: ? any internal device requests an external memo ry access to an address space mapped to a chip-select serviced by the upm ? a upm refresh timer expires and request s a transaction, such as a dram refresh ? a bus monitor time-out error during a normal upm cycle redirects the upm to execute an exception sequence the ram array contains 64 words of 32-bits each. the signa l timing generator loads the ram word from the ram array to drive the genera l-purpose lines, byte-select s, and chip-selects. if the upm reads a ram word with waen set, the external lupwait si gnal is sampled and synchronized by the memory controller and the current request is frozen. 13.4.4.1 upm requests a special pattern location in the ram array is asso ciated with each of the possible upm requests. an internal device?s request for a memory acces s initiates one of the following patterns (m x mr[op] = 00): ? read single-beat pattern (rss) ? read burst cycle pattern (rbs) ? write single-beat pattern (wss) ? write burst cycle pattern (wbs) run command upm refresh timer request array index generator internal / external memory access request exception request index signals timing generator internal signals latch wait request logic ram array lupwait waen bit internal controls lgpl n increment index (last = 0) hold (issued in software) lbs n lcs n 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-61 a upm refresh timer request pattern initiates a refresh timer pattern (rts). an exception (caused by a bus monitor time-out erro r) occurring while anothe r upm pattern is running initiates an exception condition pattern (exs). figure 13-53 and table 13-29 show the start addresses of these pa tterns in the upm ram, according to cycle type. run commands (m x mr[op] = 11), however, can initiate patterns starting at any of the 64 upm ram words. figure 13-53. ram array indexing 13.4.4.1.1 memory access requests the user must ensure that the upm is appropr iately initialized before a request occurs. the upm supports two types of memory reads and writes: ? a single-beat transfer transfers one operand c onsisting of up to a single word (dependent on port size). a single-beat cycle starts with one transfer start and ends with one transfer acknowledge. ? a burst transfer transfers exactly 4 double words regardless of port size. for 32-bit accesses, the burst cycle starts with one tran sfer start but ends af ter eight transfer acknowledges, whereas an 8-bit device requires 32 transfer acknowledges. table 13-29. upm routines start addresses upm routine routine start address read single-beat (rss) 0x00 read burst (rbs) 0x08 write single-beat (wss) 0x18 write burst (wbs) 0x20 refresh timer (rts) 0x30 exception condition (exs) 0x3c write single-beat request read burst request read single-beat request write burst request ram array refresh timer request exception condition request rss rbs wss wbs rts exs 64 ram words array index generator 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-62 freescale semiconductor the user must ensure that patterns for single- beat transfers contain one, and only one, transfer acknowledge (uta bit in ram word set high) and for a burst transfer, cont ain the exact number of transfer acknowledges required. any transfers that do not naturally fit single or burst transfers ar e synthesized as a series of single transfers. these accesses are treated by the upm as back-to-back, single-beat transf ers. burst transfers can also be inhibited by setting or n [bi]. burst performance can be achieved by ensuring that upm transactions are 32-byte aligned with a transaction size being some multiple of 32-bytes, which is a natural fit for cache-line transfers, for example. 13.4.4.1.2 upm refresh timer requests each upm contains a refresh timer that can be programmed to generate refresh service requests of a particular pattern in the ram array. figure 13-54 shows the clock division ha rdware associated with memory refresh timer request generation. the upm refr esh timer register (lurt) defines the period for the timers associated with all three upms. figure 13-54. memory refresh timer request block diagram by default, all local bus refreshes are performed usi ng the refresh pattern of upma. this means that if refresh is required, mamr[rfen] must be set. it also means that only one refresh routine should be programmed and be placed in upma, which serves as the refresh executor. any banks assigned to a upm are provided with the refresh patter n if the rfen bit of the corresp onding upm is set. upma assigned banks, therefore, always receive refresh services when mamr[rfen] is set, while upmb and upmc assigned banks also receive (the same) refresh services if the corresponding m x mr[rfen] bits are set. note that the upm refresh timer request should not be used in a system with sdram refresh enabled. the system designer must choose to us e either sdram refresh or upm re fresh. using both may result in missing refresh pe riods to memory. 13.4.4.1.3 software requests?run command software can start a request to the upm by issuing a run command to the upm. some memory devices have their own signal handshaking prot ocol to put them into special m odes, such as self-refresh mode. other memory devi ces require special commands to be issued on their control signals , such as for sdram initialization. for these special cycles, the user cr eates a special ram patter n that can be stored in any unused areas in the upm ram. then a run command is used to run the cycle. the upm runs the pattern beginning at the specified ram location until it encounters a ram word with its last bit set. the run command is issued by setting m x mr[op] = 11 and accessing upm n memory region with an y write transaction that hits the corresponding upm machine. m x mr[mad] determines the starting address in the ram array for the pattern. upm refresh timer request system clock divide by lurt ptp prescaling 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-63 note that transfer acknowledges (u ta bit in the ram word) are ignor ed for software (run command) requests, and hence the lad signals remain high-impedance unless the normal initial lale occurs or the run pattern causes assertion of lale to occur on changes to the ram word amx field. 13.4.4.1.4 exception requests when the lbc under upm control initiates an access to a memory device and an exception occurs (bus monitor time-out), the upm provides a mechanism by which memory contro l signals can meet the device?s timing requirements without losing data. the mechanis m is the exception pattern that defines how the upm negates its signals in a controlled manner. 13.4.4.2 programming the upms the upm is a micro sequencer that requires microins tructions or ram words to generate signal timings for different memory cycles. follow these steps to program upms: 1. set up br n and or n registers. 2. write patterns into the ram array. 3. program mrtpr, lurt and mamr [rfen] if refresh is required. 4. program m x mr. patterns are written to the ram array by setting m x mr[op] = 01 and accessing th e upm with any write transaction that hits the relevant ch ip select. the entire array is thus programmed by an alternating series of writes: to mdr (ram word to be written) each time followed by a read fro m mdr and then followed by a (dummy) write transaction to the relevant up m assigned bank. a read from mdr is required to ensure that the mdr update has occurred prior to the (dummy) write transaction. ram array contents may also be read for debug purposes, for example, by alternating dummy read transactions, each time foll owed by reads of mdr (when m x mr[op] = 10). note m x mr/mdr registers should not be updated while dummy read/write accesses are still in progress. dummy transaction completion is indicated by incremented m x mr[mad]. in order to enforce proper ordering between updates to the m x mr register and the dummy accesses to the upm memory region, two rules must be followed: 1.) since the result of any update to the m x mr/mdr register must be in effect before the dummy read or write to the upm region, a write to m x mr/mdr should be followed immediately by a read of m x mr/mdr. 2.) the upm memory region should have the same mmu settings as the memory region containing the m x mr configuration register; both should be mapped by the mmu as ca che-inhibited and guarded. this prevents the core from re-ordering a read of the upm memory around the read of m x mr. once the programming of the upm array is complete the mmu setting for the associated addr ess range can be set to the proper mode for normal operation, such as cacheable and copyback. 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-64 freescale semiconductor 13.4.4.2.1 upm programming example (two sequential writes to the ram array) the following example further illust rates the steps required to perform two writes to the ram array at non-sequential addresses assu ming that the relevant br n and or n registers have been previously setup. 1. program m x mr for the first write (with desired ram array address). 2. write pattern/data to mdr to ensure that the m x mr has already been updated with the desired configuration. 3. read mdr to ensure that the mdr has already b een updated with the desi red pattern. (or, read m x mr if step 2 is not performed.) 4. preform a dummy write tr ansaction. (write transact ion can now be performed.) 5. read/check m x mr[mad]. if incremented, then the previous dummy write transaction is completed; proceed to step 6. repeat step 5 until incremented. 6. program m x mr for the second write with the desired ram array address. 7. write pattern/data to mdr to ensure that the m x mr has already been updated with the desired configuration. 8. read mdr to ensure that the mdr has alre ady been updated with the desired pattern. 9. perform a dummy write tr ansaction.(write transacti on can now be performed.) 10. read/check m x mr[mad]. if incremented, then the previous dummy write transaction is completed. note that if step 1 (or 6) and 2 (or 7) are revers ed, then step 3 (or 8) is replaced by the following: ? read m x mr to ensure that the m x mr has already been updated wi th the desired configuration. 13.4.4.2.2 upm programming example (two sequential reads from the ram array) ram array contents may also be read for debug purposes, for example, by alternating dummy read transactions, each time foll owed by reads of mdr (when m x mr[op] = 0b10). the following example further illustrates the st eps required to perform two reads from th e ram array at non-se quential addresses assuming that the relevant br n and or n registers have been previously setup. 1. program m x mr for the first read with the desired ram array address. 2. read m x mr to ensure that the m x mr has already been updated wi th the desired configuration, such as ram array address. 3. perform a dummy read tr ansaction.(read transacti on can now be performed.) 4. read/check m x mr[mad]. if incremented, then the previous dummy read transaction is completed; proceed to step 5. repeat step 4 until incremented. 5. read mdr. 6. program m x mr for the second read with the desired ram array address. 7. read m x mr to ensure that the m x mr has already been updated wi th the desired configuration, such as ram array address. 8. perform a dummy read tr ansaction.(read transacti on can now be performed.) 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-65 9. read/check m x mr[mad]. if incremented, then the previous dummy read transaction is completed; proceed to step 10. re peat step 9 until incremented. 10. read mdr. 13.4.4.3 upm signal timing ram word fields specify the value of the various external signa ls at a granularity of up to four values for each bus clock cycle. the signal timing generator caus es external signals to be have according to timing specified in the current ram wor d. for lcrr[clkdiv] = 4 or 8, each bit in the ram word relating to lcs n and lbs timing specifies the value of the corresponding external signal at each quarter phase of the bus clock. if lcrr[clkdiv] = 2, the ex ternal signal can change value onl y on each half phase of the bus clock. if the ram word in this case (lcrr[clkdiv ] = 2) specifies a quarter phase signal change, the signal timing generator interprets this as a half cycle change. the division of upm bus cycles into phases is shown in figure 13-55 and figure 13-56 . if lcrr[clkdiv] = 2, the bus cycle co mprises only two active phases, t1 and t3, which correspond with the first and second halves of the bus clock cycle, respectively. however, if lcrr[clkdiv] = 4 or 8, four phases, t1?t4, define four quarter s of the bus clock cycle. because t2 and t4 are inactive when lcrr[clkdiv] = 2, upm ignores signa l timing programmed for assertion in either of these phases in the case lcrr[clkdiv] = 2. figure 13-55. upm clock scheme for lcrr[clkdiv] = 2 figure 13-56. upm clock scheme for lcrr[clkdiv] = 4 or 8 lclk t1 t2 t3 t4 lclk t1 t2 t3 t4 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-66 freescale semiconductor 13.4.4.4 ram array the ram array for each upm is 64 locations deep and 32 bits wide, as shown in figure 13-57 . the signals at the bottom of the figure are upm outputs. the selected lcs n is for the bank that matches the current address. the selected lbs is for the byte lanes read or written by the access. figure 13-57. ram array and signal generation 13.4.4.4.1 ram words the ram word is a 32-bit microinstruction stored in one of 64 locations in the ram array. it specifies timing for external signals controlled by the upm. figure 13-58 shows the ram word fields. when lcrr[clkdiv] = 4 or 8, the cst n and bst n bits determine the state of upm signals lcs n and lbs [0:3] at each quarter phase of the bus clock. when lcrr[clkdiv] = 2, cst2 and cst4 are ignored and the external has the values defined by cst1 and cst3 but ex tended to half the cl ock cycle in duration. the same interpretation occurs for the bst n bits when lcrr[clkdiv] = 2. access: read/write 01 2 3 4567 8 9101112131415 r cst1 cst2 cst3 cst4 bst1 bst2 bst3 bst4 g0l g0h g1t1 g1t3 g2t1 g2t3 w reset all zeros 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r g3t1 g3t3 g4t1/dlt3 g4t3/waen g5t1 g5t3 redo loop exen amx na uta todt last w reset all zeros figure 13-58. ram word field descriptions t1, t2, t3, t4 lgpl0 lgpl2 lgpl3 lgpl4 lgpl5 external signals timing generator ram array cs line selector byte select logic lcs [0:7] lbs [0:3] current bank brn[ps], la[30,31] 32 bits 64 deep lgpl1 clock phases 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-67 table 13-30 describes ram word fields. table 13-30. ram word field descriptions bits name description 0 cst1 chip select timing 1. defines the state (0 or 1) of lcs n during bus clock quarter phase 1 if lcrr[clkdiv] = 4 or 8. defines the state (0 or 1) of lcs n during bus clock half phase 1 if lcrr[clkdiv] = 2. 1 cst2 chip select timing 2. defines the state (0 or 1) of lcs n during bus clock quarter phase 2 if lcrr[clkdiv] = 4 or 8. ignored when lcrr[clkdiv] = 2. 2 cst3 chip select timing 3. defines the state (0 or 1) of lcs n during bus clock quarter phase 3 if lcrr[clkdiv] = 4 or 8. defines the state (0 or 1) of lcs n during bus clock half phase 2 if lcrr[clkdiv] = 2. 3 cst4 chip select timing 4. defines the state (0 or 1) of lcs n during bus clock quarter phase 4 if lcrr[clkdiv] = 4 or 8. ignored when lcrr[clkdiv] = 2. 4 bst1 byte select timing 1. defi nes the state (0 or 1) of lbs during bus clock quarter phase 1 (lcrr[clkdiv] = 4 or 8) or bus clock half pha se 1 (lcrr[clkdiv] = 2), in conjunction with br n [ps] and the state of la[30:31]. 5 bst2 byte select timing 2:. defi nes the state (0 or 1) of lbs during bus clock quarter phase 2 (lcrr[clkdiv] = 4 or 8), in conjunction with br n [ps] and the state of la[30:31]. ignored when lcrr[clkdiv] = 2. 6 bst3 byte select timing 3. defi nes the state (0 or 1) of lbs during bus clock quarter phase 3 (lcrr[clkdiv] = 4 or 8) or bus clock half pha se 2 (lcrr[clkdiv] = 2), in conjunction with br n [ps] and the state of la[30:31]. 7 bst4 byte select timing 4. defi nes the state (0 or 1) of lbs during bus clock quarter phase 4 (lcrr[clkdiv] = 4 or 8), in conjunction with br n [ps] and the state of la[30:31]. ignored when lcrr[clkdiv] = 2. 8?9 g0l general-purpose line 0 lower. defines the state of lgpl0 during the bus clock quarter phases 1 and 2 (first half phase). 00 value defined by m x mr[g0cl] 01 reserved 10 0 11 1 10?11 g0h general-purpose line 0 higher. defines the state of lgpl0 during the bus clock quarter phases 3 and 4 (second half phase). 00 value defined by m x mr[g0cl] 01 reserved 10 0 11 1 12 g1t1 general-purpose line 1 timing 1. defines the stat e (0 or 1) of lgpl1 during bus clock quarter phases 1 and 2 (first half phase). 13 g1t3 general-purpose line 1 timing 3. defines the stat e (0 or 1) of lgpl1 during bus clock quarter phases 3 and 4 (second half phase) 14 g2t1 general-purpose line 2 timing 1. defines state (0 or 1) of lgpl2 during bus clock quarter phases 1 and 2 (first half phase). 15 g2t3 general-purpose line 2 timing 3. defines the stat e (0 or 1) of lgpl2 during bus clock quarter phases 3 and 4 (second half phase). 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-68 freescale semiconductor 16 g3t1 general-purpose line 3 timing 1. defines the stat e (0 or 1) of lgpl3 during bus clock quarter phases 1 and 2 (first half phase). 17 g3t3 general-purpose line 3 timing 3. defines the stat e (0 or 1) of lgpl3 during bus clock quarter phases 3 and 4 (second half phase). 18 g4t1/dlt3 general-purpose line 4 timing 1/delay time 3. the function of this bit is determined by m x mr[gpl4]. if m x mr[gpl4] = 0 and lgpl4/lupwait signal functions as an output (lgpl4), g4t1/dlt3 defines the state (0 or 1) of lgpl4 during bus clock quarter phases 1 and 2 (first half phase). if m x mr[gpl4] = 1 and lgpl4/lupwait functions as an input (lupwait), if a read burst or single read is executed, g4t1/dlt3 defines th e sampling of the data bus as follows: 0 in the current word, the data bus should be sampled at the start of bus clock quarter phase 1 of the next bus clock cycle. 1 in the current word, the data bus should be sampled at the start of bus clock quarter phase 3 of the current bus clock cycle. 19 g4t3/waen general-purpose line 4 timing 3/wait enable. bit function is determined by m x mr[gpl4]. if m x mr[gpl4] = 0 and lgpl4/lupwait signal func tions as an output (lgpl4), g4t3/waen defines the state (0 or 1) of lgpl4 during bus clock quarter phases 3 and 4 (second half phase). if m x mr[gpl4] = 1 and lgpl4/lupwait functions as an input (lupwait), g4t3/waen is used to enable the wait mechanism: 0 lupwait detection is disabled. 1 lupwait is enabled. if lupwait is detected as being asserted, a freeze in the external signals logical values occurs until lupwait is detected as being negated. 20 g5t1 general-purpose line 5 timing 1. defines the stat e (0 or 1) of lgpl5 during bus clock quarter phases 1 and 2 (first half phase). 21 g5t3 general-purpose line 5 timing 3. defines the stat e (0 or 1) of lgpl5 during bus clock quarter phases 3 and 4 (second half phase). 22?23 redo redo current ram word. defines the number of times to execute the current ram word. 00 once (normal operation) 01 twice 10 three times 11 four times 24 loop loop start/end. the first ram word in the ram ar ray where loop is 1 is recognized as the loop start word. the next ram word where loop is 1 is th e loop end word. ram words between, and including the start and end words, are defined as part of t he loop. the number of times the upm executes this loop is defined in the corresponding loop fields of the m x mr. 0 the current ram word is not the loop start word or loop end word. 1 the current ram word is the start or end of a loop. 25 exen exception enable. allows branching to an exc eption pattern at the exception start address (exs). when an internal bus monitor time-out exception is recognized and exen in the ram word is set, the upm branches to the special exception start a ddress (exs) and begins operating as the pattern defined there specifies. the user should provide an exception pattern to negate signals controlled by the upm in a controlled fashion. for dram control, a handler should negate ras and cas to prevent data corruption. if exen = 0, exceptions are ignored by upm (but not by local bus) and execution continues. after the upm branches to the exception start address, it continues reading until the last bit is set in the ram word. 0 the upm continues executing the remaining ram words, ignoring any internal bus monitor time-out. 1 the current ram word allows a branch to the exception pattern after the current cycle if an exception condition is detected. table 13-30. ram word field descriptions (continued) bits name description 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-69 13.4.4.4.2 chip-select signal timing (cst n ) if br n [msel] of the accessed bank sel ects a upm on the curren tly requested cycle, the upm manipulates the lcs n for that bank with timing as specified in the upm ram word cst n fields. the selected upm affects only the assertion and ne gation of the appropriate lcs n signal. the state of the selected lcs n signal of the correspon ding bank depends on th e value of each cst n bit. figure 13-59 shows how upms control lcs n signals. 26?27 amx address multiplexing. determines the source of lad[0:31] during a lale phase. any change in the amx field initiates a new lale (address) phase. 00 lad[0:31] is the non-multiplexed address. for example, column address. 01 reserved 10 lad[0:31] is the address multiplexed according to m x mr[am]. for example, row address. 11 lad[0:31] is the contents of mar. used, for example, to initialize a mode. note that source id debug mode is only supported for the amx = 00 setting. 28 na next burst address. determines when the address is incremented during a burst access. 0 the address increment function is disabled. 1 the address is incremented in the next cycle. in conjunction with the br n [ps], the increment value of the state of la[27:31] is 1, 2 or 4 for port si zes of 8-bits, 16-bits and 32-bits, respectively. 29 uta upm transfer acknowledge. i ndicates assertion of transfer acknowledge in the current cycle. 0 transfer acknowledge is not asserted in the current cycle. 1 transfer acknowledge is asserted in the current cycle. 30 todt turn-on disable timer. the disable timer associated with each upm allows a minimum time to be guaranteed between two successive accesses to the same memory bank. this feature is critical when dram requires a ras precharge time. todt turns the timer on to prevent another upm access to the same bank until the timer expires.the disable timer period is determined in m x mr[ds n ]. the disable timer does not affect memory accesses to different banks. note that todt must be set together with last, otherwise it is ignored. 0 the disable timer is turned off. 1 the disable timer for the current bank is activated preventing a new access to the same bank (when controlled by the upms) until the disable timer expires. for example, precharge time. 31 last last word. when last is read in a ram word, the current upm pattern terminates and control signal timing set in the ram word is applied to the current (and last) cycle. however, if the disable timer is activated and the next access is to the same bank, execution of the next upm pattern is held off and the control signal values specified in the last wo rd are extended in duration for the number of clock cycles specified in m x mr[ds n ]. 0 the upm continues executing ram words. 1 indicates the last ram word in the program. the service to the upm request is done after this cycle concludes. table 13-30. ram word field descriptions (continued) bits name description 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-70 freescale semiconductor figure 13-59. lcs n signal selection 13.4.4.4.3 byte select signal timing (bst n ) if br n [msel] of the accessed memory ba nk selects a upm on the currently requested cycle, the selected upm affects the assertion and ne gation of the appropriate lbs [0:3] signal. the timing of all four byte-select signals is specified in the ram word. however, lbs [0:3] are also controlled by the port size of the accessed bank, the numb er of bytes to transfer , and the address accessed. figure 13-60 shows how upms control lbs [0:3]. figure 13-60. lbs signal selection the uppermost byte select (lbs0 ), when asserted, indicates that la d[0:7] contains valid data during a cycle. likewise, lbs1 indicates that lad[8:15] contains valid data, lbs2 indicates that lad[16:23] contains valid data, and lbs3 indicates that lad[24:31] contains valid data. for a upm refresh timer request, all lbs [0:3] signals are asserted/negated by the upm according to the refresh pattern only. following any internal bus monitor exception, lbs [0:3] signals are negated re gardless of the exception handling provided by any upm exception pattern to prevent spurious writ es to external ram. upma/b/c sdram gpcm mux br n [msel] lcs3 lcs5 lcs6 lcs7 switch bank selected lcs0 lcs1 lcs2 lcs4 upma mux br n [msel] lbs0 lbs1 lbs2 lbs3 bank selected br n [ps] a[29:31] byte count byte-select logic upmb upmc 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-71 13.4.4.4.4 general-p urpose signals (g n t n , go n ) the general-purpose signals (lgpl[0:5] ) each have two bits in the ram wo rd that define the logical value of the signal to be changed at the rising edge of the bus clock and/or at the falling edge of the bus clock. lgpl0 offers enhancements beyond the other lgpl n lines. gpl0 can be controlled by an address line specified in m x mr[g0cl]. to use this feature, g0h and g0l should be set in the ram word. for example, for a si mm with multiple banks, th is address line can be used to switch between internal memory device banks. 13.4.4.4.5 loop control (loop) the loop bit in the ram word specifies the beginni ng and end of a set of up m ram words that are to be repeated. the first time loop = 1, the memory cont roller recognizes it as a loop start word and loads the memory loop counter with the correspon ding contents of the loop field shown in table 13-31 . the next ram word for which loop = 1 is recognized as a loop end word. when it is reached, the loop counter is decremented by one. continued loop execution depends on the loop counter. if the counter is not zero, the next ram word executed is the loop start wo rd. otherwise, the next ram word execut ed is the one after the loop end word. loops can be executed sequentially but cannot be nest ed. also, special care must be taken if last and loop must not be set together. 13.4.4.4.6 repeat execution of current ram word (redo) the redo function is useful for wait -state insertion in a long upm rou tine that would otherwise need too many ram words. setting the redo bits of the ra m word to a nonzero value causes the upm to re-execute the current ram word up to three more time s, as defined in the redo field of the current ram word. special care must be take n in the following cases: ? when uta and redo are set together, ta is asse rted the number of times specified by the redo function. ? when na and redo are set together, the address is incremented the number of times specified by the redo function. ? when loop and redo are set together, the l oop mechanism works as usual and the line is repeated according to the redo function. table 13-31. m x mr loop field use request serviced loop field read single-beat cycle rlf read burst cycle rlf write single-beat cycle wlf write burst cycle wlf refresh timer expired tlf run command rlf 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-72 freescale semiconductor ? last and redo must not be set together. ? redo should not be used within the exception routine. 13.4.4.4.7 address multiplexing (amx) the address lines can be controlled by the pattern th e user provides in the upm. the address multiplex bits can choose between driving the tr ansaction address, driving it acco rding to the multiplexing specified by the m x mr[am] field, or driving the ma r contents on the address signals . in all cases, la[27:31] of the lbc are driven by the five lsbs of the address selected by amx, regardless of whether the na bit of the ram word is used to increment the current a ddress. the effect of na = 1 is visible only when amx = 00 chooses the column address. table 13-32 shows how m x mr[am] settings affect address multiplexing when the ram word amx = 10. the 16 msbs of the lad[0:31] bus during an address phase are driven with zero in the amx = 10 case. note that any change to the amx fi eld from one ram word to the next ram word executed results in an address phase on the lad[0: 31] bus with the as sertion of lale for the number of cycles set for lale in the or n and lcrr registers. the lgpl[0:5] signals ma intain the value specified in the ram word during the lale phase. 13.4.4.4.8 data valid and data sample control (uta) when a read access is handled by the upm, and the ut a bit is 1 (data is to be sampled by the lbc), the value of the dlt3 bit in the same ram word, in conjunction with m x mr[gpl n 4dis], determines when the data input is sampled by the lbc as follows: ?if m x mr[gpl n 4dis] = 1 (g4t4/dlt3 func tions as dlt3) and dlt3 = 1 in the ram word, data is latched on the falling edge of the bus clock in stead of the rising edge. the lbc samples the data on the next falling edge of the bus clock, which is during the middle of the current bus cycle. this feature should be used only in systems without external synchr onous bus devices that require mid-cycle sampling. ?if gpl n 4dis = 0 (g4t4/dlt3 functions as g4t4), or if gpl n 4dis = 1 but dlt3 = 0, data is latched on the rising edge of the bus clock, which occurs at the e nd of the current bus clock cycle (normal operation). table 13-32. upm address multiplexing am lad[0:31] as address signals a0?a15 a16 a17 a18 a19 a20 a21 a22 a23 a24 a25 a26 a27 a28 a29 a30 a31 000 signal driven on external signal when address multiplexing is enabled? ram word amx = 10 0 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 a23 001 0 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 010 0 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 011 0 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 100 0 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 101 0 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-73 figure 13-61 shows how data sampling is controlled by the upm. figure 13-61. upm read access data sampling 13.4.4.4.9 lgpl[0:5] signal negation (last) when the last bit is read in a ra m word, the current upm pattern is te rminated at the end of the current cycle. on the next cycle (following last) all th e upm signals are negated unconditionally (driven to logic 1), unless there is a back-to-back upm request pending. in this case, the si gnal values for the cycle following the one in which the last bit was set are taken from th e first ram word of the pending upm routine. 13.4.4.4.10 wait mechanism (waen) the waen bit in the ram array word can be used to enable the up m wait mechanism in selected upm ram words. if the upm reads a ram word with wa en set, the external lupwait signal is sampled and synchronized by the memory contro ller as if it were an asynchronous signal. the waen bit is ignored if last = 1 in the same ram word. synchronization of lupwait starts at the rising edge of th e bus clock and takes at least 1 bus cycle to complete. if lupwait is asserted and waen = 1 in the current upm word, th e upm is frozen until lupwait is negated. the value of external signals driven by the upm remains as indicated in the previous ram word. when lupwait is negated, the upm continues nor mal functions. note that during wait cycles, the upm does not handle data. figure 13-62 shows how the waen bit in the word read by the upm and the lupwait signal are used to hold the upm in a particular state until lupw ait is negated. as the example shows, the lcs n and lgpl1 states and the waen valu e are frozen until lupwait is recognized as negated. waen is typically set before the line that contains uta = 1. no te that if waen and na are both set in the same ram word, na causes the burst address to incremen t once as normal regardless of whether the upm freezes. to internal data bus lclk upm read and gpl4ndis = 1 and dlt3 = 1 lad[0:31] 1 0 multiplexor 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-74 freescale semiconductor figure 13-62. effect of lupwait signal 13.4.4.5 synchronous sampling of lupwait for early transfer acknowledge if lupwait is to be considered an asynchronous signal, which can be asserted/negated at any time, no upm ram word must contain both waen = 1 and uta = 1 simultaneously. however, programming waen = 1 and uta = 1 in the same ram word allows upm to treat lupwait as a synchronous signal, whic h must meet set-up and hold times in relation to the rising edge of the bus clock. in this case, as soon as upm samples lupwai t negated on the rising edge of the bus clock, it immediately generates an in ternal transfer acknowledge, which allows a data transfer one bus clock cycle later. the generation of transfer acknowledge is early because lupwai t is not re-synch ronized, and the acknowledge occurs regardless of whet her upm was already frozen in wa it cycles or not. this feature allows the synchronous negation of lupwait to affect a data transfer, even if uta, waen, and last are set simultaneously. 13.4.4.6 extended hold time on read accesses slow memory devices that take a long time to turn off their data bus drivers on read accesses should choose some non-zero combination of or n [trlx] and or n [ehtr]. the next accesses af ter a read access to the slow memory device is delayed by the num ber of clock cycles specified in the or n register in addition to any existing bus turn around cycle. lcs n lgpl1 waen word n word n+1 c1 c2 c3 c4 c5 c6 c7 c8 lupwait c9 c10 c11 c12 c13 c14 word n+2 wait word n+3 lclk t1 t2 t3 t4 a b c d ta 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-75 13.4.4.7 memory system inte rface example using upm connecting the local bus upm contro ller to a dram de vice requires a detailed ex amination of the timing diagrams representing the possible memory cycles th at must be performed wh en accessing this device. this section shows timing diagrams for various upm configurations , using fast-page mode dram as an example, with lcrr[clkdiv] = 4 or 8. these illustrative exampl es may not represent the timing necessary for any specific device used with the lbc. here, lgpl1 is programmed to drive r/w of the dram, although any lgpl n signal may be used for this purpose. 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-76 freescale semiconductor figure 13-63. single-beat read access to fpm dram cst1 0 lale pause (due to change in amx) 00bit 0 cst2 0 0 0 bit 1 cst3 0 0 0 bit 2 cst4 0 0 0 bit 3 bst1 1 1 0 bit 4 bst2 1 0 0 bit 5 bst3 1 0 0 bit 6 bst4 1 0 0 bit 7 g0l0 bit 8 g0l1 bit 9 g0h0 bit 10 g0h1 bit 11 g1t1 1 1 1 bit 12 g1t3 1 1 1 bit 13 g2t1 bit 14 g2t3 bit 15 g3t1 bit 16 g3t3 bit 17 g4t1 bit 18 g4t3 bit 19 g5t1 bit 20 g5t3 bit 21 redo[0] bit 22 redo[1] bit 23 loop 0 0 0 bit 24 exen 0 0 0 bit 25 amx0 1 0 0 bit 26 amx1 0 0 0 bit 27 na 0 0 0 bit 28 uta 0 0 1 bit 29 todt 0 0 1 bit 30 last 0 0 1 bit 31 rss rss+1 rss+1 rss+2 lclk lad lale lcs n lgpl1 address a row la read data column address ta row lsbs column lsbs (ras ) lbs n (cas ) lbctl (r/w ) 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-77 figure 13-64. single-beat write access to fpm dram cst1 0 lale pause (due to change in amx) 00bit 0 cst2 0 0 0 bit 1 cst3 0 0 0 bit 2 cst4 0 0 1 bit 3 bst1 1 1 0 bit 4 bst2 1 1 0 bit 5 bst3 1 0 0 bit 6 bst4 1 0 1 bit 7 g0l0 bit 8 g0l1 bit 9 g0h0 bit 10 g0h1 bit 11 g1t1 0 0 0 bit 12 g1t3 0 0 0 bit 13 g2t1 bit 14 g2t3 bit 15 g3t1 bit 16 g3t3 bit 17 g4t1 bit 18 g4t3 bit 19 g5t1 bit 20 g5t3 bit 21 redo[0] bit 22 redo[1] bit 23 loop 0 0 0 bit 24 exen 0 0 0 bit 25 amx0 1 0 0 bit 26 amx1 0 0 0 bit 27 na 0 0 0 bit 28 uta 0 0 1 bit 29 todt 0 0 1 bit 30 last 0 0 1 bit 31 wss wss+1 wss+1 wss+2 lclk lad lale lcs n lgpl1 address a row la column write data ta row lsbs column lsbs (ras ) lbs n (cas ) address write data lbctl (r/w ) 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-78 freescale semiconductor figure 13-65. burst read access to fp m dram using loop (two beats shown) cst1 0 0 0 1 bit 0 cst2 0 0 0 1 bit 1 cst3 0 lale pause (due to change in amx) 001bit 2 cst4 0 0 0 1 bit 3 bst1 1 1 0 1 bit 4 bst2 1 1 0 1 bit 5 bst3 1 1 0 1 bit 6 bst4 1 0 0 1 bit 7 g0l0 bit 8 g0l1 bit 9 g0h0 bit 10 g0h1 bit 11 g1t1 1 1 1 1 bit 12 g1t3 1 1 1 1 bit 13 g2t1 bit 14 g2t3 bit 15 g3t1 bit 16 g3t3 bit 17 g4t1 bit 18 g4t3 bit 19 g5t1 bit 20 g5t3 bit 21 redo[0] bit 22 redo[1] bit 23 loop 0 1 1 0 bit 24 exen 0 0 1 0 bit 25 amx0 1 000bit 26 amx1 0 000bit 27 na 0 010bit 28 uta 0 0 1 0 bit 29 todt 0 0 0 1 bit 30 last 0 001bit 31 rbs rbs+1 rbs+2 rbs+3 lclk lad lale lcs n lgpl1 address a row la data 1 column 1 address ta row lsbs (ras ) lbs n (cas ) data 2 column 2 column 1 lsbs column 2 lsbs lbctl (r/w ) 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-79 figure 13-66. refresh cycle (cbr) to fpm dram cst1 1 0 0 bit 0 cst2 1 0 0 bit 1 cst3 1 0 1 bit 2 cst4 1 0 1 bit 3 bst1 1 0 0 bit 4 bst2 0 0 0 bit 5 bst3 0 0 1 bit 6 bst4 0 0 1 bit 7 g0l0 bit 8 g0l1 bit 9 g0h0 bit 10 g0h1 bit 11 g1t1 bit 12 g1t3 bit 13 g2t1 bit 14 g2t3 bit 15 g3t1 bit 16 g3t3 bit 17 g4t1 bit 18 g4t3 bit 19 g5t1 bit 20 g5t3 bit 21 redo[0] bit 22 redo[1] bit 23 loop 0 0 0 bit 24 exen 0 0 0 bit 25 amx0 0 0 0 bit 26 amx1 0 0 0 bit 27 na 0 0 0 bit 28 uta 0 0 0 bit 29 todt 0 0 1 bit 30 last 001bit 31 pts pts+1 pts+2 lclk lad lale lcs n lbctl a la ta (ras ) lbs n (cas ) 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-80 freescale semiconductor figure 13-67. exception cycle cst1 1 bit 0 cst2 1 bit 1 cst3 1 bit 2 cst4 1 bit 3 bst1 1 bit 4 bst2 1 bit 5 bst3 1 bit 6 bst4 1 bit 7 g0l0 bit 8 g0l1 bit 9 g0h0 bit 10 g0h1 bit 11 g1t1 bit 12 g1t3 bit 13 g2t1 bit 14 g2t3 bit 15 g3t1 bit 16 g3t3 bit 17 g4t1 bit 18 g4t3 bit 19 g5t1 bit 20 g5t3 bit 21 redo[0] bit 22 redo[1] bit 23 loop 0 bit 24 exen 0 bit 25 amx0 0 bit 26 amx1 0 bit 27 na 0 bit 28 uta 0 bit 29 todt 1 bit 30 last 1 bit 31 exs lclk lad lale lcs n lbctl ta (ras ) lbs n (cas ) 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-81 13.5 initialization/application information 13.5.1 interfacing to peripherals 13.5.1.1 multiplexed address/data bu s and non-multiplexed address signals to save signals on the local bus, a ddress and data are multiplexed onto the same 32 bit bus. an external latch is needed to demultiplex and reconstruct the orig inal address. no external intelligence is needed, because the lale signal provides the correct timing to control a standard logi c latch. the lad signals can be directly connected to the da ta signals of the memory/peripheral. transactions on the local bus start with an address phase, where the l bc drives the transaction address on the lad signals and asserts the lale signal. this can be used to latch the addr ess and then the lbc can continue with the data phase. the lbc supports port sizes of 8,16, and 32 bits. for devi ces smaller than 32 bits, transactions must be broken down. for this reason, la[30: 31] are driven non-mul tiplexed. for 8-bit devi ces, la[30:31] should be used and for 16-bit devices, la[30] should be used. 32-bit devi ces use neither of these signals. in addition, the lbc supports burst transfers (not in the gpcm ma chine). la[27:29] are the burst addresses within a natural 32-byte burst. to minimi ze the amount of address phases needed on the local bus and to optimize the throughput, those signals are dr iven separately and should be used whenever a device requires the five least si gnificant addresses. those shoul d not be used from lad[27:31]. all other addresses, a[0:26], must be reconstructed through the latch. figure 13-68. multiplexed address/data bus muxed address/data non-muxed address la[27:31] lad[0:31] lale local bus interface latch a[0:26] d q le a[27:31] d[0:31] 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-82 freescale semiconductor 13.5.1.2 peripheral hierarchy on the local bus to achieve high bus speed inte rfaces for synchronous srams or sdrams, a hierarchy of the memories/peripherals connected to the local bus is suggested, as shown in figure 13-69 . figure 13-69. local bus peripheral hierarchy the multiplexed address/data bus sees the capacitive loading of the da ta signals of the fast sdrams or synchronous srams plus one load for an address latch plus one load for a buffer to the slow memories. the loadings of all other memories and peripherals are hidden behi nd the buffer and the latch. the system designer needs to investigate the load ing scenario and ensure that i/o ti mings can be met with the loading determined by the connected components. 13.5.1.3 peripheral hierarchy on the local bus for very high bus speeds to achieve the highest possible bus speeds on the local bus, it is recommended to reduce the number of devices connected directly to the local bus even further. for those cases probably only one bank of synchronous srams or sdrams should be used and instead of using a se parate latch and a separate bus transceiver, a bus demultiplexer combining thos e two functions into one device should be used. ma muxed address/data non-muxed address buffered data la[27:31] lad[0:31] lale lbctl local bus interface latch buffer slower memories and peripherals a dq a dq sdram a dq ssram d q le a dir b 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-83 figure 13-70 shows an example of such a hierarchy. this section is only a guideline and the board designer must simulate the electric characteristics of his s cenario to determine the maximum operating frequency. figure 13-70. local bus peripheral hierarchy for very high bus speeds 13.5.1.4 gpcm timings in case a system contains a me mory hierarchy with high spee d synchronous memories (sdram, synchronous sram) and lower speed asynchronous memories (for example, flash eprom and peripherals) the gp cm-controlled memories should be decoupled by buffers to reduce capacitive loading on the bus. those buffers have to be take n into account for the timing calculations. figure 13-71. gpcm address timings to calculate address setup timing fo r a slower peripheral/memory device , several parameters have to be added: propagation delay for the a ddress latch, propagation delay for th e buffer and the a ddress setup for the actual peripheral. typical values for the 2 propa gation delays are in the order of 3?6 ns, so for a 166-mhz bus frequency, lcs should arrive on the orde r of 3 bus clocks later. for data timings, only the propagation delay of one buf fer plus the actual data setup time has to be considered. ma muxed address/data non-muxed address buffered data la[27:31] lad[0:31] lale lbctl local bus interface latch slower memories and peripherals a dq a dq sdram a/d le dir q b a muxed address/data non-muxed address buffered address slower memories and peripherals device input a signal buffer latch lad[0:31] lale lbctl local bus interface 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-84 freescale semiconductor figure 13-72. gpcm data timings 13.5.2 bus turnaround because the local bus uses multiplexed address and data, spec ial consideration must be given to avoid bus contention at bus turnaround. the foll owing cases must be examined: ? address phase after previous read ? read data phase after address phase ? read-modify-write cycle for parity protected memory banks ? upm cycles with additional address phases the bus does not change direction for the follow ing cases so they need no special attention: ? continued burst after the first beat ? write data phase after address phase ? address phase after previous write 13.5.2.1 address phase after previous read during a read cycle, the memory/peripheral drives th e bus and the bus transceive r drives lad. after the data has been sampled, the output driv ers of the external device must be disabled. this can take some time; for slow devices the ehtr feature of the gpcm or the programmability of th e upm should be used to guarantee that those device s have stopped driving the bus when the lbc memory controller ends the bus cycle. in this case, after the previous cycle ends, lb ctl goes high and changes the direction of the bus transceiver. the lbc then inserts a bus turnaround cycle to avoid cont ention. the external device has now already placed its data signals in high impedance and no bus contention will occur. 13.5.2.2 read data phas e after address phase during the address phase, lad actively drives the address and lbctl is high, driving the bus transceivers in the same direction as during a write. after the end of the address phase, lbctl goes low and changes the direction of the bus transceiver. the lbc places the lad signals in high impedance after its t dis (lb). the lbctl will have its new state after t en (lb) and, because this is an asynchronous input, the transceiver starts to drive those signals after its t en (transceiver) time. the system designer has to ensure, that [t en (lb) + t en (transceiver)] is larger than t dis (lb) to avoid bus contention. muxed address/data buffered data lad[0:31] lbctl local bus interface buffer slower memories and peripherals device input d signal 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-85 13.5.2.3 read-modify-write cycle fo r parity protected memory banks principally, a read-modify-w rite cycle is a read cycl e immediately followed by a write cycle. because the write cycle will have a new address pha se in any case, this basically is the same case as an address phase after a previous read. 13.5.2.4 upm cycles with additional address phases the flexibility of the upm allows the user to in sert additional address phases during read cycles by changing the amx field, therefore, turning around the bus during one pattern. the lbc automatically inserts a single bus turnaround cycle if the bus (lad) was previously high impedance for any reason, such as a read, before lale is driven and lad is driven with the new address. the turnaround cycle is not inserted on a write, because the bus was already driven to begin with. however, bus contention could potentially still occur on the far side of a bus transceiver. it is the responsibility of the designer of the upm pattern to guarantee that enough idle cycl es are inserted in the upm pattern to avoid this. 13.5.3 interface to different port-size devices the lbc supports 8-, 16-, a nd 32-bit data port sizes. howe ver, the bus requires that the portion of the data bus used for a transfer to or from a particular port size be fixed. a 32-bit port must reside on d[0:31], a 16-bit port must reside on d[0:15], and an 8-bit port must reside on d[0:7]. the local bus always tries to transfer the maximum amount of data on all bus cycles. 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-86 freescale semiconductor figure 13-73 shows the device connect ions on the data bus. figure 13-73. interface to different port-size devices table 13-33 lists the bytes required on th e data bus for read cycles. table 13-33. data bus requirements for read cycle transfer size address state 1 a[29:31] port size/data bus assignments 32-bit 16-bit 8-bit 0?7 8?15 16?23 24?31 0?7 8?15 0?7 byte 000 op0 2 ? 3 ? ? op0 ? op0 001 ? op1 ? ? ? op1 op1 010 ? ?op2?op2?op2 011 ? ? ? op3 ? op3 op3 100 op4 ? ? ? op4 ? op4 101 ? op5 ? ? ? op5 op5 110 ? ?op6?op6?op6 111 ? ? ? op7 ? op7 op7 0 31 63 op0 op1 op2 op3 op4 op5 op6 op7 d[0:7] d[8:15] d[ 15:23] d[24:31] op0 op1 op2 op3 op4 op5 op6 op7 op0 op1 op2 op3 op4 op5 op6 op7 op0 op7 32-bit port size interface output register 16-bit port size 8-bit port size 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-87 13.5.4 interfacing to sdram the following sections provide applicat ion information on interfacing to sdram. 13.5.4.1 basic sdram capabi lities of the local bus the lbc provides one sdram machine for the local bu s. although there is only one machine, multiple chip selects (lcs n ) can be programmed to support multiple sdram devices. note that no limitation exists on the number of chip sele cts that can be prog rammed for sdram. this means that lcs [1:7] can be programmed to support sdram, assuming lcs0 is reserved for the gpcm to connect to flash memory. if multiple chip selects are conf igured to support sdram on the lo cal bus, each sdram device should have the same port size and t iming parameters. this means th at all option registers (or n ) for the sdram chip selects should be pr ogrammed exactly the same. note although in principle it is possible to mix different port sizes and timing parameters, combinations are li mited and this operation is not recommended. all the chip selects share the same local bus sdram mode register (lsdmr) fo r initialization along with the local bus-assigned sdram refresh timer register (lsrt) and the memory refresh timer prescaler register (mptpr) for refresh. half word 000 op0 op1 ? ? op0 op1 op0 001 ? op1 op2 ? ? op1 op1 010 ? ? op2 op3 op2 op3 op2 100 op4 op5 ? ? op4 op5 op4 101 ? op5 op6 ? ? op5 op5 110 ? ? op6 op7 op6 op7 op6 word 000 op0 op1 op2 op3 op0 op1 op0 100 op4 op5 op6 op7 op4 op5 op4 1 address state is the calculated address for port size. 2 op n : these lanes are read or written during that bus tr ansaction. op0 is the most-significant byte of a word operand and op3 is the least-significant byte. 3 ? denotes a byte not driven during that write cycle. table 13-33. data bus requirements for read cycle (continued) transfer size address state 1 a[29:31] port size/data bus assignments 32-bit 16-bit 8-bit 0?7 8?15 16?23 24?31 0?7 8?15 0?7 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-88 freescale semiconductor for refresh, the memory controller supplies auto re fresh to sdram according to the time interval specified in lsrt and mptpr as follows: this represents the time period re quired between refreshes. when the refresh timer expires, the memory controller issues a cbr to each ch ip select. each cbr is separated by one clock. a refresh timing diagram for multiple chip selects is shown in figure 13-51 in section 13.4.3.11.1, ?sdram refresh timing.? during a memory transaction dispatched to the local bus, the memory controller compares the memory address with the address information of each chip select (programmed with br n and or n ). if the comparison matches a chip select that is controlled by sdram, the memory controller requests service to the local bus sdram machine, de pending on the information in br n . although multiple chip selects may be programmed for sdram, only one ch ip select is active at any given time; thus, multiple chip selects can share the same sdram machine. 13.5.4.2 maximum amount of sdram supported table 13-34 summarizes information based on typical sdram data sheets. the data port size is progr ammable, but the following examples use all 32 bits of the local bus. the 32-bit port size requires 4 sdram devices (with 8-bit i/o ports) connected in parallel to a single chip select. if 128-mbit devices are used, 1 chip select provides 128-mbit/device 4 devices = 64 m bytes. if 4 chip selects are programmed for sdram us e, the result is 64 mbytes 4 = 256 mbytes. if 256-mbit sdram devices are used, the total available memory is 512 mbytes. consequently, 512-mbit devices allow for 1 gbyte. although there is no technical difficulty in supporting multiple chip select configurations, in practice, the user may want to maximize the amount of sdram a ssigned to each chip se lect to minimize cost. 13.5.4.3 sdram machine limitations this section describes limitations of the local bus sdram machine. table 13-34. typical sdram devices sdram device 64-mbit 128-mbit 256-mbit 512-mbit i/o port x4 x8 x16 x32 x4 x8 x16 x32 x4 x8 x16 x32 x4 x8 x16 x32 bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 row 12 12 12 11 12 12 12 12 13 13 13 13 13 13 13 ? column 10 9 8 8 11 10 9 8 11 10 9 8 12 11 10 ? refresh period lsrtx mptpr ptp [] () system frequency ----------------------------------------------------------------- = 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-89 13.5.4.3.1 analysis of maximum row num ber due to bank se lect multiplexing lsdmr[bsma] is used to multiplex the bank se lect address. the bsma field and corresponding multiplexed address are shown below: 000 la12?la13 001 la13?la14 ? 111 la19?la20 note that la12 is the latched value of lad12. the highest address signals that th e bank selects can be multiplexed wi th are la[12:13], which limits the signals for the row address to la[ 14:31]. for a 32-bit port, the maximum width of the local bus, la[30:31] are not connected, and the maximu m row is la[14:29]. the local bus sdram machine supports 15 rows, which is sufficient for all devices. 13.5.4.3.2 bank select signals page-based interleaving allows bank si gnals to be multiplexed to the hi gher-order address signals to leave room for future upgrades. for example, a user coul d multiplex the bank select signals to la[14:15], leaving la16 to connect to the addre ss signal for a larger memory size. this allows the system designer to design one board that can be used with a current generation of sdram devices and upgraded to the next genera tion without requiri ng a new board layout. 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-90 freescale semiconductor 13.5.4.3.3 128-mbyte sdram figure 13-74 shows the connection to an sdram of 128 m bytes. note that all circuit diagrams are principal connection diagrams and do not show any means of signal integrity. figure 13-74. 128-mbyte sdram diagram table 13-35 shows details about lad n signal connections for the example in figure 13-74 . table 13-35. lad n signal connections to 128-mbyte sdram lad (latch address) sdram address signal lad29 a0 lad28 a1 lad27 a2 lad26 a3 lad25 a4 lad24 a5 lad23 a6 lad22 a7 data[0:7] data[24:31] lcs n lsdwe lad[0:31] lsdras lale lclk lcke lsdcas latch dqm0 dqm3 lsddqm [0:3] local bus interface cas 32m x 8 cs ras we ba[1:0] dqm cke clk addr[12:0] sdram dq[0:7] cas 32m x 8 cs ras we ba[1:0] dqm cke clk addr[12:0] sdram dq[0:7] x4 ? ? ? lsda10 a10 a10 ? ? ? 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-91 consider the following sdram organization: ? the 32-bit port size is organized as 8 8 32 mbits. ? each device has 4 internal banks, 13 row a ddress lines, and 10 column address lines. the logical address is pa rtitioned as shown in table 13-36 . the following parameters are extracted: ? cols = 011, 10 column lines ? rows = 100, 13 row lines during the address phase, the sdram address port is set as shown in table 13-37 . because the internal bank selects are multiplexed over la[15:16], lsdmr[bsma] must be set to 011. table 13-38 shows the address port configur ation during a read/write command. lad21 a8 lad20 a9 lad19 (no connect) a10 is connected to lsda10 lad18 a11 lad17 a12 lad16 ba0 (if lsdmr[bsma] = 011) lad15 ba1 (if lsdmr[bsma] = 011) table 13-36. logical address bus partitioning a[0:4] a[5:17] a[18:19] a[20:29] a[30:31] msb of start address row bank select column lsb table 13-37. sdram device addres s port during address phase la[0:14] la[15:16] la[17:29] la[30:31] ? internal bank select a[18:19] row a[5:17] no connect table 13-38. sdram device address port during read/write command la[0:14] la[15:16] la[17:18] la[19] la[20:29] la[30:31] msb of start address internal bank select don?t care ap column no connect table 13-35. lad n signal connections to 128-mbyte sdram (continued) lad (latch address) sdram address signal 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-92 freescale semiconductor table 13-39 shows the register configurat ion for this example. psrt and mptpr are not shown but should be programmed according to the devi ce?s specific refresh requirements. 13.5.4.3.4 256-mbyte sdram this example uses the same micron sdram as in the previous example, but doubles the number of devices connected and theref ore uses two chip selects. 13.5.4.3.5 512-mbyte sdram this example uses the mt48lc64m4a2fb from micron to implement 512 mbytes. in this sdram organization: ? the 32-bit port size is 8 4 64 mbit 2 chip select lines. ? each device has 4 internal banks, 13 row a ddress lines, and 11 column address lines. the logical address is pa rtitioned as shown in table 13-40 . the following parameters can be extracted: ? cols = 100, 11 column lines ? rows = 100, 13 row lines table 13-39. register settings for 128-mbyte sdrams register field value br n ba ps ms v base address 11 = 32-bit port size 011 = sdram-local bus 1 or n am cols rows 11_1111_1000_0000_0000_0 011 100 lsdmr rfen op bsma rfrc pretoact acttorow bl wrc bufcmd cl 1 000 011 from device data sheet from device data sheet from device data sheet 0 from device data sheet 0 from device data sheet table 13-40. logical address partitioning a[0:3] a[4:16] a[17:18] a[19:29] a[30:31] msb of start address row bank select column lsb 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-93 during the address phase, the sdra m address port is set as in table 13-41 . because the internal bank selects are multiplexed over la[15:16], lsdmr[bsma] must be set to 011. table 13-42 shows the address port setti ngs during a read/write command. table 13-43 shows the register configuration. psrt a nd mptpr are not shown, but they should be programmed according to the specific device?s refresh requirements. 13.5.4.3.6 power-down mode sdrams offer a power-down mode dur ing which the device is not refres hed, and therefore, data is not maintained. this mode is invoked by driving cke low, while all internal banks are idle; note that they must be precharged first. figure 13-75 shows the timing. note that the figure does not show the precharge-all command that is issued by the lbc automatically prior to the self-refresh command. table 13-41. sdram device addres s port during address phase la[0:13] la[15:16] la[17:29] la[30:31] ? internal bank select (a[17: 18]) row (a[4:16]) no-connect table 13-42. sdram device address port during read/write command la[0:14] la[15:16] la[17] la[18] la[19:29] la[30:31] msb of start address internal bank select don?t care ap column no-connect table 13-43. register settings for 512-mbyte sdrams register field value br n ba ps ms v base address 11 = 32-bit port size 011 = sdram-local bus 1 or n am bpd cols rows 11_1110_0000_0000_0000_0 01 100 100 psdmr rfen op bsma rfrc pretoact acttorow bl wrc bufcmd cl 1 000 011 from device data sheet from device data sheet from device data sheet 0 from device data sheet 0 from device data sheet 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-94 freescale semiconductor figure 13-75. sdram power-down timing cke remains low, as long as the device is powered dow n. after cke transitions to high, the sdram exits the power-down mode. 13.5.4.3.7 self-refresh in order to be able to stop activity on the local bus (for power save or debug), while the content of the sdram is maintained, the se lf-refresh mode is supported. this mode is invoked by issu ing a self-refresh command to the sdram. the lbc applies the same ti ming as for the auto refresh, but also pulls the sdram cke (lcke) signal low in the same cycle. th is can only be done with all banks being idle; the sdram machine must precharge them ahead of this. as long as cke stay s low, the device refreshes itself and does not need to see any refreshes from the local bus. to exit se lf refresh, cke simply has to be pulled high. note that after returning from self-refresh m ode the sdram needs a supplier-specific time before it can accept new commands and the auto-ref resh mechanism has to be started again. figure 13-76 shows this timing. the sdram controller always uses 200 local bus clocks, which should satisfy any sdram requirements. as in the case of the power-down mode, the figure does not show the precharge-all command that is issued by the lbc automatically prior to the self-refresh command. 1. refer to section 13.4.3.3, ?intel pc133 a nd jedec-standard sdram interface commands,? for sdram interface commands and inform ation on the self-refresh command. command cke nop nop nop supplier specific minimum time new command accepted here all banks idle cannot violate minimum refresh specification (as defined by s , re , ce , w , and addr) clock low-to-high transitions 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-95 t figure 13-76. sdram self-refresh mode timing 13.5.4.3.8 sdram timing to allow for very high speeds on the memory bus, the capacitive loading on the local bus must be taken into consideration as shown in table 13-44 . note: capacitance values compiled from worst case numbers from various data sheets from samsung and micron to implement a system us ing the hierarchy describe d earlier for 2 synchronous memory banks, 1 address latch, and 1 buffer loading the multiplexed address/da ta bus sees a loading of 4 loads of about 6.5 pf maximum. for a nominal load, 30 pf can be used. table 13-44. sdram capacitance signal min max unit clk 2.0 4.0 pf ras , cas , we , cs , cke, dqm 2.0 5.0 pf address 2.0 5.0 pf dq 0 ?dq 31 3.5 6.5 pf external ck cke s re ce w an supplier-specific minimum time new command can occur here self-refresh exit self-refresh entry all banks idle nop stable clock 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-96 freescale semiconductor note: ac characteristics compiled from worst-case numb ers from various data sheets from samsung and micron. setup and hold timing calculations: address tof (time of fli ght): board layout delay data tof (time of flight): board layout delay clock skew (time of flight ): clock skew between the lbc and the clock at the memory device. the local bus dll feedback mechanism must be used to cont rol this skew to optimize the timing margins, as described in the rest of this subsection. address setup margin = cy cle time ? local bus address ctq ? sdram address input setup time ? address tof + clock skew address hold margin = local bus address output hol d time + address tof ? sdram address input hold time ? clock skew data write to sdram setup margin = cycle time ? lo cal bus data ctq ? sdram data input setup time ? data tof + clock skew data write to sdram hold margin = local bus data output hold time + data tof ? sdram data input hold time ? clock skew data read from sdram setup margin = cycle time ? sdram data ctq ? local bus da ta input setup time ? data tof ? clock skew data read from sdram hold margin = sdram data output hold time + data tof ? local bus data input hold time + clock skew table 13-45. sdram ac characteristics parameter device speed unit 166 mhz 133 mhz min max min max clk cycle time cas latency = 3 6 1000 7.5 1000 ns cas latency = 2 ? 7.5 clk to valid output delay cas latency = 3 ? 5 ? 5.4 ns cas latency = 2 ? ? ? 5.4 output data hold time cas latency = 3 2.5 ? 3 ? ns cas latency = 2 ? ? 3 ? input setup time 1.5 ? 2 ? ns input hold time 1 ? 1 ? ns clk to output in hi-z cas latency = 3 ? 5 5.4 ? ns cas latency = 2 ? ? 5.4 ? 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-97 to improve the timing margins a dll is used to ge nerate external clocks, which minimize the skew between the local bus and the memory clock. figure 13-77 shows relative timings for the local bus clock dll. figure 13-77. local bus dll operation 13.5.4.4 parity support for sdram contrary to older dram technologi es, sdram devices typically are or ganized either x4, x8, x16, or x32. there are no mainstream devices that include parity support. to allow for error protection on the local bus an additional sdram for the 4 parity bits must be used. since the lo cal bus allows for sdram accesses with less than the full port size, read-modify-wr ite cycles are supported for sdram write cycles. t d = t dll + t p rbc (reference bus clock) lsync_out lsync_in lclk lbc output signals on pins t p t l 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-98 freescale semiconductor figure 13-78 shows a connection diagram. figure 13-78. parity support for sdram 13.5.5 interfacing to zbt sram in many applications, sdram provides sufficient performance for the lo cal bus. however, especially in networking applications, me mory access patterns are often random and sdram is not optimized for that case. zbt srams have been designe d to optimize the performance in networking applications. this section describes how to interface to zbt srams. figure 13-79 shows the connections. the upm is used to generate control signals. the sa me interfacing is used for pipeline d and flow-through versions of zbt srams. however different upm patt erns must be generated for thos e cases. because zbt srams will mostly be used by performance-criti cal applications, we assume here that, typically, the maximum width of the local bus of 32 bits will be used. zbt srams allow different configura tions. for the local bus the burst or der should be set to linear burst order by tying the mode signal to gnd; cke should also be tied to ground. ? ? ? 4 dp[0:3] ? ? ? data[0:7] data[24:31] lcs n lsdwe lad[0:31] lsdras lale lclk lcke lsdcas latch dqm0 dqm3 lsddqm [0:3] local bus interface cas 32m 8 cs ras we ba[1:0] dqm cke clk addr[12:0] sdram dq[0:7] lsda10 a10 cas 32m 4 cs ras we ba[1:0] dqm cke clk addr[12:0] sdram dq[0:3] a10 cas 32m 8 cs ras we ba[1:0] dqm cke clk addr[12:0] sdram dq[0:7] a10 ldp[0:3] lpbse 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-99 zbt srams perform four-beat bursts. because the lb c generates eight-beat tr ansactions (for 32-bit ports) the upm breaks down each burst into two cons ecutive four-beat bursts. the internal address generator of the lbc generates the new a27 for the second burst. figure 13-79. interface to zbt sram because we use linear burst on the sram, the devi ce will itself burst with the burst addresses of [0:1:2:3]. the local bus always generates linear bursts and expe cts [0:1:2:3:4:5:6:7]. therefore, two consecutive linear bursts of the zbt sram with a27 = 0 for the first burst a nd a27 = 1 for the second burst give the desired burst pattern. the upm also supports single beat accesses. becaus e the zbt sram does not s upport this and always responds with a burst, the upm pattern has to take care th at data for the critical be at is provided (for write) or sampled (for read), and that the rest of the burst is ignored (by negating we ). the upm controller basically has to wait for the end of the sram burst to avoid bus cont ention with further bus activities. zbt srams have a power down mode, which is invoke d by the zz signal. conn ecting a gpio signal to zz allows use of that power down mode; however, accesses to the sram whil e in power down mode do not create valid results. this should be taken care of by the system software. another observation is that srams are available w ith natural parity. in the example, we use a 18 sram, which holds two data bytes and two parity bits. while for the support of parity on sdram banks the local dp[2:3] data[0:15] data[16:31] bw [0:1] bw [2:3] dp[0:1] ce 1m 18 adv/ld we zz bw [0:1] mode cke clk sa[19:0] zbt dq[0:17] oe sram ce 1m 18 adv/ld we zz bw [0:1] mode cke clk sa[19:0] zbt dq[0:17] oe sram lbs [0:3] lcs n lgpl0 lgpl2 lad[0:31] lgpl1 local bus interface lale ldp[0:3] lclk gpio la[27:29] latch 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-100 freescale semiconductor bus has to use read-modify-write cycles and compro mise performance, sram banks can be used with natural parity and do not compromise performance for parity support. 13.5.6 interfacing to dsp host ports in many applications, an integrated communications processor aggregates traffic for dsps and distributes that traffic to the dsps. the local bus allows connec tion to a variety of differ ent dsp host ports and this section gives some information on how to interface to some example dsps. 13.5.6.1 interfacing to msc8101 hdi16 this section describes how to interface to the hd i16 peripheral interface of the msc8101. after initial set-up of the interface, the host and hdi16 device can communicate either by a re ad and write transaction from the core or, if the setup on the dsp and the host are implemented appropriately, by dma transfers of the host dma controller, which can be trigge red automatically by signals generated by the hdi16 peripheral. 13.5.6.1.1 hdi16 peripherals the host interface (hdi16) is a 16- bit-wide, full-duplex, doubl e-buffered parallel port that can directly connect to the data bus of a host pr ocessor. it supports a variety of buses and gluelessly connects with a number of industry-standard microc omputers, microprocessors, and d sps. the hdi16 also supports the 8-bit host data bus, which makes it fully compatible with the dsp 56300 hi08 (as viewed by the host side, not from the dsp side). the host bus can operate asynchronously to the sc140 core clock, and the hdi16 registers are divided into two banks. the host register ba nk is accessible to the external host, and the core register bank is accessible to the sc140 core. the msc8101hdi16 host port peripheral has two sets of 16-bit-wide registers ?one set is only visible internally to the dsp, while the other set is visible only to the external host processor. figure 13-81 illustrates the relationshi p between the two sides. all of the hdi16 peripheral?s regi sters are mapped direc tly onto the msc8101 qbus, as defined by the msc8101 16-bit digital signal processor reference manual (msc8101rm); the tran smit and receive fifos are mapped onto the dma data bus such that th e dma controller can acces s them directly without core intervention. the addressing for each of these registers is defined in section 13.5.6.1.2, ?physical interconnections.? the hdi16 host port itself is a 16-bi t-wide parallel port with various strobe and multiplexing options. the most important hdi16 host port facet is that it is specified as an asynchronous interface and so reduces concerns over clock skew between th e hdi16 host port and the host device ?s buses. furthermore, with all the host port registers being accessed wi th a single chip select and four address lines, as far as the local bus is concerned, the dsp host port is akin to an as ynchronous memory mapped re gion. so, for the hdi16 port in single strobe mode, the host device asserts a chip select, a single data strobe and a read/write line to select hdi16 read or write bus operations. 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-101 the read and write strobes ar e also used as the data latch control to complete the bus tr ansactions, obviating the need for any handshake termination signal from the dsp. the upm programmer is responsible for satisfying the ac timings of the hdi16 transactions. through appropriate mode selection, the hdi16 periphera l?s feature set can be fu lly supported by the local bus?s upm controlled signals. the up m defined interface can be used with any of the local bus?s eight chip selects to give the 16-bit port size and strobe generation that matches that of the hdi16 host port. figure 13-80 shows the internal register diagram of the hdi16. figure 13-80. msc8101 hdi16 peripheral registers 13.5.6.1.2 physical interconnections the physical interconnections betw een the upm controlled local bus and the hdi16 of the msc8101 hdi16 peripheral are given in table 13-46 and figure 13-81 . table 13-46. local bus to msc8101 hdi16 connections msc8101 signal(s) type description connect with local bus signal hd[0:15] i/o/z host data bus lad[0:15] ha[0] i host address line eit her la[27] or latched a25 ha[1] i host address line eit her la[28] or latched a26 ha[2] i host address line la[29] ha[3] i host address line la[30] hcs1 i host chip select 1 lcs n hcs2 i host chip select 2 tie this to v dd hrdrw i host r/w signal lgpl1 or inverted lbctl signal tx0 tx1 tx2 tx3 horx hcr hsr hcvr hpcr rx0 rx1 rx2 rx3 16 16 16 16 hotx isr icr cvr 16 16 16 64 64 qbus data bus dma data bus host bus 16 16 16 16 16 16 16 16 64 64 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-102 freescale semiconductor figure 13-81. interface to msc8101 hdi16 the connections are sp ecified as follows: ? one chip select, lcs n (whatever is available in the system), is used to memory map accesses from the host local bus to the hdi16 msc8101 hdi16 peripheral, and is connected to the hdi16 chip select line (hcs). ? this interface uses two separate genera l-purpose strobe lines (lgpl1 and lgply): ? lgpl1 is programmed to generate the hdi16 re ad/write signal (hrdrw), which is typically high for a read access and low for write acces s. in any case, the host port requires a hr/w signal. this can be generated by using lgpl1, and allows it to adopt the timing virtually without restrictions. alternatively the designer can invert lbctl to generate this signal. it is the responsibility of the upm patt ern designer to plan for the addi tional delay of that inverter in the upm pattern to satisfy th e ac timings at the dsp host port. ? lgply is programmed to genera te the hdi16 data strobe (hds ), which must be asserted every 16-bit read or write transaction. ? data lines?the bus data lines (lad n ) are directly connected to the hdi16 data lines (hd n ). ? dma request/service request signals (hrrq and htrq)?as a ppropriate in the application hds i host data strobe signal lgply hrrq/hack o receive host request op as required in application htrq/hreq o transmit host request op as required in application table 13-46. local bus to msc8101 hdi16 connections (continued) msc8101 signal(s) type description connect with local bus signal hd[0:15] ha[0:1] latch ha[2:3] hcs1 hrdrw hds hrrq/hack htrq/hreq lad[0:31] lale la[29:30] lcs n lgply as required lgpl1 local bus interface lad[0:15] hcs2 msc8101 la[27:28] in application or inverted lbctl 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-103 ? address lines?the address lines between th e lbc and the hdi16 msc8101 can either be connected in a straightforward or a specific manner to enable bur st transfers across the hdi16. the connections are defined as follow s and are described in more deta il in the follow ing sub-section: ? either la[27] or latched value of a25 -> ha0 ? either la[28] or latched value of a26 -> ha1 ? la[29] -> ha2 ? la[30] -> ha3 ? ground lines?in order to provide the best ground pl ane, it is highly advised that all grounds are common and connected together. 13.5.6.1.3 supporting burst transfers as mentioned previously, to facilitate burst transfers the host?s local bus address lines can be connected in a very specific way. first, the local bus a31 signal is not required, as the hdi16 registers are 16-bit word addressed. secondly, local bus la[27] and la[28] signals can be eliminate d, so that the host side transmit and receive registers wrap around th e same four 16-bit word addresses. for example, host transmit register 0 on the hdi16 periphera l (address 0x04) can be obtained by the host by accessing any of the following memory mapped addresses: 0x20, 0x28, 0x30, or 0x38. this is critical for burst accesses as the source or de stination addresses increment after each 16-bit access to the interface for all 16 transactions within that burst. by using th e addressing as defined, if the first access is at 0x20, the last will be at 0x3e but, more importantly, the four host tx/rx re gisters will have been looped around four times. 13.5.6.1.4 host 60x bus: hdi16 peri pheral interface hardware timings the host upm-controlled loca l bus and the hdi16 msc8101 hd i16 host interface are both programmable. careful programming of the host ch ip select registers and upm can meet the hdi16 msc8101 host port timings. on any bus access the critical timing for both read and write is typically around th e data latch point. for the upm based read access, the host has the flexibility to latch data on a rising or falling lclk edge. the falling lclk edge is used here to latch the hdi16 data into the host msc8101 at its earliest convenience. after the data is latched, appropriate hdi16 port data hol d time is ensured before the data strobe (ds) and chip select (cs1) are negated. on a upm write cycle, the critical action is in envel oping the ds assertion with cs asserted to ensure proper write data hold time after latching by the hdi16 host port. special attention needs to be given to both the host read and write access strobe (ds) negation times (hds assert). the hdi16 msc8101 specifies some rest rictions for consecutive register access, which results in a hold off negation time for the re ad and write access strobes. 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-104 freescale semiconductor rather than restrict the firmware to avoid consecutiv e bus accesses to host port registers, the negation hold off times should be accommodated in the upm hardware interface sett ings. additional clocks must be built into the end of upm based cycle giving appr opriate time before the next bus cycle starts. the timings can be readily adapted to allow external decode logic to be added to support chip selects for a larger number of dsp hdi16 host ports. 13.5.6.2 interfacing to msc8102 dsi the msc8102 direct-slave interface (dsi) gives an external host direct access to the msc8102. it provides the following slave in terfaces to an external host: ? asynchronous sram-like interf ace giving the host single accesse s (with no external clock). ? synchronous ssram-like interface giving the host singl e or burst accesses of 256 bits (eight beats of 32 bits or four beat s of 64 bits) with its external clock decoupled from the msc8102 internal bus clock. the dsi supports a 32- or 64-bit data bus. for connection to the local bus the dsi has to be configured in 32-bit mode. this is achieved thr ough the dsp reset configuration. the dsi supports two addressing mode s, which are determined during the msc8102 boot sequence. refer to details in the msc8102 documentation. ? full address bus mode with ha[ 11:29] used in both 32-bit data mode and 64-bit data mode ? sliding window mode with ha[14:29] used in both 32-bit data mode and 64-bit data mode 13.5.6.2.1 dsi in asynchronous sram-like mode the local bus supports the dsi singl e strobe as well as the dsi double strobes of operation. as an example the dual strobe configuration is shown below. 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-105 figure 13-82 shows the interface to the ms c8102 dsi for asynchronous mode. figure 13-82. interface to msc8102 dsi in asynchronous mode the asynchronous sram-like mode of the dsi is i nherently slower than the synchronous mode and should be used, if only relatively small amounts of data are transf erred between th e communications controller and the msc8102. to allow for maximum timing flexibility, the upm machine of the lbc should be used. the upm programmer is responsible for ensuring correct setup and hold timings for all signals. the upm allows sufficient control to satisfy any requirements here. figure 13-83 shows an asynchronous write ac cess. the dsi samples the host chip id signals (hcid[0:3]) on the first falling edge of the ho st write byte strobe signals (hwbs ) on which the host chip select signal (hcs ) is asserted. if the hcid[0:3] signals match the chipid value, the dsi is accessed. the dsi will signal with the assertion of the ho st transfer acknowledge signal (hta ), whether it is ready to sample the host data bus (hd), and the host can termin ate the access by imme diately negating hwbs . the waen feature of the upm must be used to insert wait states while the ds i is busy. the uwpl bit in the m x mr must be cleared to interpre t the correct polarity of hta . the dsi samples the hos t address bus (ha) and the host data bus (hd) on the rising edge of hwbs . in addition the assertion of hwbs [0:3] are sampled at the end and are part of the access attributes. because the upm is used for this mode, the d cr[4]:htaad should be set to 1 and dcr[9?10]:htadt should be defined to a valu e different than 00. this m ode is to be used in im plementations with a pull-up resistor on hta . the host can start its next access (back- to-back accesses) without negating hcs between accesses. if the next access is not to the same msc8102, then to prevent contention on the hta signal, the host must wait until the previous dsi stops driving hta before it accesses the ne xt device. if the next access is to the same msc8102, the host must not start cons ecutive accesses before hta is actively driven to a value of 1 by the previous access. the easiest way to achieve this is to insert idle cycles at the end of the upm pattern to guarantee that hta is inactive. hwbs /hdbs / hwbe /hdbe [0:3] hd[0:31] ha[11:26] latch hcid[0:3] ha[27:29] hrds /hrde hta hint hbcs hcs msc8102 local bus interface lad[0:31] lale la[27:29] lgpl2 lbs [0:3] lupwait int n lcs n lcs y 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-106 freescale semiconductor figure 13-83. asynchronous write to msc8102 dsi figure 13-84 shows an asynchronous read access. th e dsi samples the host address bus (ha ) and the hcid on the first falling edge of the host read strobe signal (hrds ) on which the hcs is asserted. if hcid[0:3] match the chipid value, the dsi is accessed. when the dcr[8]:r pe bit is set, read access to the memory space (not to the regist er space) initiates data prefetching from consecutive addresses in the internal memory space. the dsi signa ls (with the assertion of the host transfer acknowledge signal (hta )) that data is valid, and the host can sample the hos t data bus (hd) and term inate the access by negating hrds . if the data for this access is al ready in the read buffer due to the prefetch mechanism, assertion time of hta is improved. the waen feature of the upm must be used to insert wait states while the dsi is busy. m x mr[uwpl] has to be cleared to inte rpret the correct polarity of the hta signal. because the upm is used in the m ode, the dcr[4]:htaad should be set to 1 and the drive time control field, dcr[9?10]:htadt, should be defined to a value di fferent than 00. this mode is specially designed to be used for implementations with a pull-up resistor on hta . the host can start its next access (back-to -back accesses) without negating the hcs signal between accesses. if the next access is not to the same msc8102, then to prevent contention on hta , the host must wait until the previous dsi stops driving hta before it accesses the next de vice. if the next access is to the same msc8102, the host must not start consecutive access before hta is actively driven to 1 by the previous access. the easiest way to achieve this is to insert idle cycles at the end of the upm pattern to guarantee that hta is inactive. hcs hcid[0:3] ha[11:29] hdst[0:1] hd[0:63] hwbs [0:7] hrds hta legend: timing conventions: valid value that can be 1 or 0 don?t care three-state output signal that is not driven by the dsi 1 0 1 0 htaad = 0 & htadt = 00 htaad=1 & htadt = 01,10,11 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-107 figure 13-84. asynchronous read from msc8102 dsi 13.5.6.2.2 dsi in synchronous mode the synchronous ssram-like mode of the dsi is i nherently faster than the asynchronous mode and should be used if larger amounts of data are transf erred between the communica tions controller and the msc8102. this will optimize the bus utilization, especially if several msc8102s are connected to one local bus. the upm machine of the lbc must be used to implement this interface. figure 13-85 shows the interface for synchronous mode. b ecause the dsi will assert and negate hta in synchronous mode even with in a burst transfer on a clock-by-clock basis and be cause the dsi expects the host to react within one clock cycl e, some tricks can be implemente d to support the synchronous mode. hta drives lupwait of the upm. m x mr[uwpl] must be cleared to in terpret the correct polarity of hta . because this signal influences th e internal state machine of the lo cal bus clock, the local bus cannot react to hta changes correctly within one local bus clock. refer to section 13.4.4.4.10, ?wait mechanism (waen),? for more detailed information. the solution to this lies in that the local bus operat es at a higher frequency than the dsi interface of the dsp. the local bus clock can be divi ded by an integer divider (1:2, 1:3, or 1:4) to generate the dsi clock. this should not be a problem because the local bus is designed for much higher fr equencies than the dsi. because all timings are given in d sp dsi clock cycles, the upm patterns must be adjusted appropriately and need to assert a signal for 2, 3, or 4 clocks (as many as the divider ratio) instead of one. fortunately, the upm has the redo feature, which allo ws every upm ram entry to be executed 1 , 2 , 3 , or 4 , which should be sufficient for any divider ratio that would be used in this case. hcs hcid[0:3] ha[11:29] hdst[0:1] hd[0:63] hwbs [0:7] hrds hta legend: timing conventions: valid value that can be 1 or 0 don?t care three-state output signal that is not driven by the dsi 1 0 1 0 htaad = 0 & htadt = 00 htaad = 1 & htadt = 01,10,11 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-108 freescale semiconductor figure 13-85. interface to msc8102 dsi in synchronous mode this solution allows the local bus to react within multiple local bus clocks to the hta signal and be still within one dsi clock. typically, lupwait is synchr onized internally, and only 2 clocks after lupwait changes, new data can be sampled or presented. for example, if the local bus clock ratio is 3 the dsi clock, data can be sampled in the th ird local bus sub-clock, which is the last third of the dsi clock. if the local bus clock ratio is only 2 the dsi clock, there is a special mode, where the lupwait is not synchronized. refer to section 13.4.4.5, ?synchronous sampling of lupwait for early transfer acknowledge,? for more detailed information. in this m ode, data is sampled in the second sub-clock, which is the second half of the ds i clock. ac timing of lupwait must be met in this mode; otherwise indeterministic beha vior may occur. the remaining issue is the synchroni zation of the upm cycles to the beginning of the dsi clock cycle. because the upm executes n cycles for every cycle of th e dsi, a mechanism must be used to ensure that the upm changes transitions in a way that is synchronized to the dsi clock. the solution is to use a special synchronize cycle at the beginning of the pattern. a gpl signal is used to control a multiplexer and to activate external synchronization lo gic, which uses the dsi clock to stall the upm by asserting lupwait until the beginning of the ne xt dsi cycle. after that, this gpl signa l must be negated and the multiplexer connects lupwait to hta instead, for the rest of the bus cycle. note that the gpl signals should be used in the inverted state of their inactiv e state (gpl[0:4] are 1 wh en inactive, gpl5 is 0 when inactive) to start the synchronization process. hwbs /hdbs / hwbe /hdbe [0:3] hd[0:31] ha[11:26] latch hcid[0:3] ha[27:29] hrds /hrde hint hbrst hbcs hcs msc8102 local bus interface lad[0:31] lale la[27:29] lgpl2 lbs [0:3] int n lgpl n lcs n lcs y hclkin hta clock lclk lupwait lgply divider sync logic 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-109 figure 13-86 shows an example for a synchronization mechan ism for a clock divider of 3. note that the length of the synchronization cycle depends on the relative st art of the synchronizati on process and varies with every access. it can vary in length from one to n (clock ratio) local bus clocks. figure 13-86. upm synchronization cycle the second column (com pensation cycle) of table 13-47 is intended to compensate for the reaction time of lupwait to get in lockstep with the dsi clock. fo r example, if the clock divider ratio is 1:3 and the lupwait reaction time is two local bus clocks, b ecause lupwait is synchronized, then one local bus clock should be inserted. table 13-47. upm synchronization cycles sync cycle compensation cycle dsi cycle 1 bits cst1?cst4 0?3 bst1?bst4 4?7 g0xx 8?11 g1tx 12?13 g2tx 14?15 g3tx 16?17 g4t1 18 g4t3 10 19 g5tx 20?21 redo[0] 0 0 1 22 redo[1] 0 0 0 23 loop 0 0 24 exen 0 25 amx0 0 0 26 amx1 0 0 27 na 0 28 uta 0 29 todt 0 30 last 0 31 lclk dsi_clk lgply lupwait 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-110 freescale semiconductor this section describes synchronous single write and read, and synchronous burst write and read operations. the local bus supports the dsi single strobe as well as the dsi double st robes of operation. the dual strobe configuration is shown as an example. synchronous single write figure 13-87 shows a synchronous single write access. figure 13-87. synchronous single write to msc8102 dsi the dsi samples ha, hdst, hcid, hd, hwbe , hrde , and hbrst on the first hclkin rising edge on which hcs is asserted. if hcid[0:3] match the chipid value, the dsi is accessed. at least one hwbe signal is asserted, and hrde and hbrst are negated. assertion of hta indicates that the dsi is ready to complete the current access and the host must terminate this access. because hta is connected to the lupwait signal of the upm, all loca l bus signals are frozen until hta goes to 0 and then the upm continues in its pattern. typically, hta is asserted immediately. if the write buffer is full, hta assertion is delayed. hta is asserted for one hclkin cycle, driven to logic 1 in the next cycle, and stops being driven on the next rising edge of hclkin. the host can start its next access to the same msc8102 immediately on the next hclkin rising edge without negating hcs between accesses. if the next access is not to the same msc8102, then, to prevent contention on hta , the host must wait to access the next device until the previous dsi stops driving hta . the easiest way to achieve this is to insert idle cycles at the end of the upm pattern to guarantee that hta is inactive. hclkin hcs hcid[0:3] ha[11:29] hdst[0:1] hd[0:63] hwbe [0:7] hrde hbrst hta legend: timing conventions: valid value that can be 1 or 0 don?t care three-state output signal that is not driven by the dsi 1 0 1 0 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-111 synchronous single read figure 13-88 shows a synchronous single read access. figure 13-88. synchronous single read from msc8102 dsi the dsi samples ha, hdst, hcid, hwbe , hrde , and hbrst on the first hclkin rising edge on which hcs is asserted. if the hcid[0:3] signals matc h the chipid value, th e dsi is accessed. hrde is asserted, and hwbe and hbrst are negated. if dcr[8]:rpe is set (see msc8102 documentation), read access to the memory space (not to th e register space) initia tes prefetching data from consecutive addresses in the internal memory space. assertion of hta indicates that data is vali d and the host must sample the hd and terminate the access. because hta is connected to the upm lupwait signal, all local bus signals are frozen until hta goes to 0; then the upm continues in its pattern. hta is asserted earlier when the data for this access is already prefetched to th e read buffer. it asserted for one hclkin cycle and driven to logic 1 in the next cycl e. it stops being driven on the next rising edge of hclkin. the host can start its next access to th e same msc8102 immediately in the next hclkin rising edge without negating hcs between accesses. if the next access is not to the same msc8102, then, to prevent contention on hta , the host must wait to access the next device until the previous dsi stops driving hta . the easiest way to achieve this is to insert idle cycles at th e end of the upm pattern to guarantee that hta is inactive. hclkin hcs hcid[0:3] ha[11:29] hdst[0:1] hd[0:63] hwbe [0:7] hrde hbrst hta legend: timing conventions: valid value that can be 1 or 0 don?t care three-state output signal that is not driven by the dsi 1 0 1 0 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-112 freescale semiconductor synchronous burst write figure 13-89 shows a synchronous burst write access. figure 13-89. synchronous burst write to msc8102 dsi the dsi samples ha, hdst, hcid, hd, hwbe , hrde , and hbrst on the first hclkin rising edge on which hcs is asserted. if hcid[0:3] match the chipid value, the dsi is accessed. hwbe are asserted, hbrst is asserted, and hrde is negated. assertion of hta indicates that the dsi is ready to complete the current beat of the access and the host must proceed to the next beat of this access. when the host reaches the last beat of the access, it must terminate the burst access. typically hta is asserted immediately for each beat of the acces s. if the write buffer is full, hta assertion is delayed. because hta is connected to the lupwait signal of the upm, all local bus signals are frozen until hta goes to 0 and then the upm continues in its pattern. af ter the last beat of the access, hta is driven to logic 1 and stops being driven on the next rising edge of hclkin. the host can start its next access to the same msc8102 immediately in the next hclkin rising edge without negating hcs between accesses. if the next access is not to the same msc8102, then, to prevent contention on hta , the host must wait to access the next device until the previous dsi stops driving hta . the easiest way to achieve this is to insert idle cycles at the end of the upm pattern to guarantee that hta is inactive. hclkin d(a+ n ) d(a+2) d(a+1) d(a) d(a+2) hcs hcid[0:3] ha[11:29] hdst[0:1] hd[0:63] hwbe [0:7] hrde hbrst hta legend: timing conventions: valid value that can be 1 or 0 don?t care three-state output signal that is not driven by the dsi 1 0 1 0 n = 3 in 64-bit data bus interface n = 7 in 32-bit data bus interface a 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-113 synchronous burst read figure 13-90 shows a synchronous burst read access. the dsi samp les ha, hdst, hcid, hwbe , hrde , and hbrst on the first hclkin ri sing edge on which hcs is asserted. if hcid[0:3] match the chipid value, the dsi is accessed. figure 13-90. synchronous burst read from msc8102 dsi hrde and hbrst are asserted and hwbe are negated. when the dcr[8]:rpe bit (see the msc8102 documentation) is set, a burst read access initiates da ta prefetching from consecutive addresses in the internal memory space. assertion of hta indicates that data is valid for the current beat of the access and the host must proceed to the next beat of this access. because hta is connected to the lupwait signal of the upm, all local bus signals are frozen until hta goes to 0 and then the up m continues in its pattern. when the host reaches the last beat of the acces s, it must terminate the burst access. the hta is asserted earlier when the data for this access is already prefetched to the read buf fer. typically, after the first beat of the burst access, hta remains asserted until the e nd of the access. after the last beat of the access, hta is driven to 1 and stops being driven in the next ri sing edge of hclkin. the host can start its next access to the same msc8102 immediately in the next h clkin rising edge without negating hcs between accesses. if the next access is not to th e same msc8102, to prevent contention on hta , the host must wait to access the next device until the previous dsi stops driving the hta signal. the easiest way to achieve this is insert idle cycles at the end of the upm pattern to guarantee that hta is inactive. 13.5.6.2.3 broadcast accesses using hbcs , a host can share one chip-select signal betw een multiple msc8102 devices for broadcasting write accesses. in broadcast mode, the dsi does not drive its hta signal to prevent contention between multiple devices driving different values to the sa me signal. also, the dsi does not decode hcid[0:3]. hclkin d(a+ n ) d(a+2) d(a+1) d(a+2) hcs hcid[0:3] ha[11:29] hdst[0:1] hd[0:63] hwbe [0:7] hrde hbrst hta legend: timing conventions: valid value that can be 1 or 0 don?t care three-state output signal t hat is not driven by the dsi 1 0 1 0 n = 3 in 64-bit data bus interface n = 7 in 32-bit data bus interface a d(a) 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-114 freescale semiconductor note that broadcasting is al lowed only for write accesses. the dsi sets the dsi error register (der) ovf bit if there is an overflow during broadcast accesses. this bit can be cleared by wri ting a value of 1 to it. note to avoid overflow when accessing dsi registers dur ing broadcast accesses, wait at least 10 host clock cycles in synchronous mode or 8 internal clock cycles in asynchronous mode between each dsi register access. to avoid data corruption, if der[0]:ovf is set, no broadcast access is written until the bit is reset. therefore, after the last broadcas t access, and before any regular write access, der[0]:ovf must first be read and reset if it is set. note in asynchronous mode, write data fro m a previous access (even a normal write access) may be lost due to ov erflow during broadcast accesses. to prevent such a loss, ensure that previous access data has propagated to the fifo or dsi registers, depending on th e type of previous access. this can be achieved by performing a read access prior to the first broadcast access. in broadcast accesses, the host must comply with the following rules: ? in asynchronous mode, h wbs [0:3]/hdbs [0:3] assertion time should be at least the minimum, which is defined in the ac ch aracteristics section of the msc8102 technical data sheet. ? in synchronous mode single access, the host must wait 1 cycle before terminating the access. access signals must be in the sa me valid state du ring two positive edges of the host clock cycles. access duration is two clock cycles (the dsi may translate accesses lasti ng longer than two clock cycles as two or more back-to-back accesses). ? in synchronous mode burst accesses, broadcast accesses are not allowed. 13.5.6.3 interfacing to ehpi from texas instruments tms320c xxxx dsps the enhanced host port interface (e hpi) on dsps from texas instrume nts provides a 16-bit-wide parallel port through which a host processor ca n directly access the memory of the dsp. the host and the dsp can exchange information through memory internal or external to the dsp a nd within the address reach of the ehpi. the ehpi uses 23-bit addresse s, where each address is assigned to a 16-bit word in memory. the ehpi has two modes, one for multiplexed addres s/data and one with separate buses.to allow the connection of multiple ds ps and other peripherals on the local bus , the use of the eh pi non-multiplexed mode is recommended. the eh pi uses the signals in figure 13-48 . 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-115 to achieve the timings required by the dsp host port and optimize the bus usage, the use of one of the upms is recommended. note that th e dsp address signals reflect 16-bit addresse s, whereas local bus address signals reflect byte addr esses. this essentially shif ts address signals by 1 bit. the ehpi host port?s tw o strobe signals, hds1 and hds2 , allow different options to control transfers. the upm supports any of those options; how ever, the easiest is to use the single active-low strobe mode and connect one upm lgpl signal (w hatever is available) to hds . in any case, the host port requires a hr/w signal. this can be generated by using another lgpl signal and allows to adopt the t iming virtually without restrictions. alternatively the designer can invert lbctl to generate this signal. it is the responsibility of the upm pattern designer to plan for the additional delay of that inverter in the upm pattern to satisfy ac timings at the dsp host port. table 13-48. ehpi signals signals type description connect with hd[15:0] i/o/z host data bus: non-muxed mode: data only lad[0:15] ha[19:4] i host address bus: non-muxed mode: addresses latched a[11:26] ha[3:0] host address bus: lsbs la[27:30] hbe[1:0] i host byte-enable signals 00 word, 0 msb, 10 lsb, 11 reserved lbs [0:1] hcs i chip select signal lcs n hr/w ir/w signal lgply or inverted lbctl hds1 , hds2 i data strobe signals must be at least 2 dsp clocks wide ? host has separate active-low read and write strobe signals: connect one to hds1 , one to hds2 ? host has one active-low strobe signal: connect to hds1 or hds2 , the other to 1 ? host has one active high-strobe signal: connect to hds1 or hds2 , the other to 0 lgpl n hrdy o ehpi ready signal lupwait hcntl0 i ehpi control signals. non-muxed mode: ? hcntl = 1: access dsp data memory ? hcntl = 0: access eh pi control register application specific: either gpio signal or latched address lines has i address strobe signal hmode i ehpi mode signal high: non-muxed mode low: muxed mode high rst_mode i reset mode signal hint o dsp to host interrupt signal int n 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-116 freescale semiconductor figure 13-91. interface to texas instruments ehpi in non-multiplexed mode the dsp does not necessarily have de terministic access times. hrdy indi cates whether the ehpi is ready for an access. if the signal is low, wait states must be inserted in th e cycle. the lupwait function of the upm provides this mechanism. m x mr[uwpl] must be set to connect to this active-low signal. figure 13-92 shows read timing required by the ehpi in non-multiplexed mode. figure 13-92. ehpi non-mu ltiplexed read timings hd[15:0] ha[19:4] latch hcntl0 ha[3:0] hr/w hcs hbe[1:0] hrdy hint hds1 /hds2 lad[0:31] lale la[27:30] lgply or inverted lbctl lcs n lbs[1:0] lupwait int n lgpl n local bus interface lad[16:31] rst_mode hmode ehpi MPC8555E hcs hds hr/w ha[18:0] hd[15:0] hrdy 1 data valid address 1 while hcs is not selected, hrdy is in hi-z state. 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 13-117 figure 13-93 shows write timing required by th e ehpi in non-multiplexed mode. figure 13-93. ehpi non-multiplexed write timings 13.5.6.3.1 expansion to multiple dsps the connection shown above can be adapted easily to interface to multiple dsps instead of only one. each dsp host port needs to receive its own chip select and interrupt signals, and hrdy must be connected differently, depending on which dsp is used. all other signals can be connect ed to all host ports in parallel. hrdy signals can be bussed for certain dsps (such as, tms320vc5510); for others (such as, tms320vc5509), an external multiplexer must be used to decide which hrdy signal is routed to the local bus. this multiplexer can be cont rolled by the respective chip selects. for a larger number of dsps, this scheme must be extended with external logi c, which uses additional address signals to generate multiple dsp hcss for one local bus chip select and to multiplex the hint and hrdy signals. the flexibility of the upm allows for additional delay for that external logic. hcs hds hr/w ha[18:0] hd[15:0] hrdy 1 valid address data valid data valid valid address 1 while hcs is not selected, hrdy is in hi-z state. 4 datasheet u .com
local bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 13-118 freescale semiconductor 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-1 chapter 14 three-speed ethernet controllers this chapter describes the two three-speed ethernet controllers of the MPC8555E . the two controllers are referenced as tsec1 and tsec2. 14.1 introduction the ethernet ieee 802.3 standard prot ocol is widely used on lans that are based on the carrier-sense multiple access/collision detect (csma/cd) approach. because et hernet and ieee 802.3 standard protocols are similar and can coexist on the same lan, both are referred to as et hernet in this manual, unless otherwise noted. 10/100 ethernet provides increased ethernet sp eed from 10 to 100 megabits per second (mbps) and provides a simple, cost-effective opt ion for backbone and server connectivity. this three-speed ethernet contro ller (tsec) also impleme nts a gigabit ethernet pr otocol, which builds on top of the ethernet protocol , but increases speed tenfold over 10/100 et hernet to 1000 mbps, or one gigabit per second (gbps). gigabit ethernet looks identical to ethernet from th e data link layer upward but it uses the ansi x3t11 fiberchannel fc-0 (interfa ce and media) and fc-1 (encode/decode) for the phy layer. in this manner, the standard takes advantage of the existing high-speed physical interface technology of fiberchannel while maintaining the ieee 802.3 standard ethernet fra me format, backward comp atibility for installed media, and the use of full - or half-duplex csma/cd. the ethernet protocol implements the bottom two laye rs of the open systems in terconnection (osi) 7-layer model, that is, the data link and physical sublayers. figure 14-1 shows the typical ethe rnet protocol stack and the relationship to the osi model. 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-2 freescale semiconductor figure 14-1. ethernet protocol in relation to the osi protocol stack gigabit ethernet provides the following sublayers: ? media access control (mac) sublayer?the mac sublayer provides a logi cal connection between the mac and its peer station. its primary responsibility is to initialize, cont rol, and manage the connection with the peer station. ? reconciliation sublayer?the rec onciliation sublayer acts as a co mmand translator. it maps the terminology and commands used in the mac laye r into electrical format s appropriate for the physical layer entities. ? mii (media-independent interface) sublayer?the mii sublayer provide s a standard interface between the mac layer and the physical layer fo r 10/100 mbps operations. it isolates the mac layer and the physical layer, enab ling the mac layer to be used wi th various implementations of the physical layer. ? gmii (gigabit media-independent interface) su blayer?the gmii sublayer provides a standard interface between the mac layer and the physical layer for 1-gbps operati on. it isolates the mac layer and the physical layer, enab ling the mac layer to be used wi th various implementations of the physical layer. ? pcs (physical coding sublayer)?the pcs sublayer is responsible for en coding and decoding data stream to and from the mac sublayer. medium (1000basex) 8b/10b coding is used for fiber. medium (1000baset) 8b1q coding is used for unshielded twisted pair (utp). ? pma (physical medium attachme nt) sublayer?the pma sublayer is responsible for serializing code groups into a bit stream suitable for serial bit-oriented physical de vices (serdes) and vice versa. synchronization is also performed for prope r data decoding in this sublayer. the pma sits between the pcs and the pmd sublayers. for fi ber medium (1000basex) the interface on the pmd side of the pma is a 1-bit 1250-mhz signal, while on the pma?s pcs si de the interface is a 10-bit interface (tbi) at 125 mhz. the tbi is an al ternative to the gmii interface. if the tbi is data link physical logical link control (llc) media access control (mac) osi reference model layers lan csma/cd layers higher layers 10/100 mbps 1-gbps 10/100 ethernet ethernet reconciliation pcs pma pmd mdi mii physical medium reconciliation pcs pma pmd mdi gmii physical medium phy 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-3 used, the gigabit ethernet controller must be capable of performing the pcs function. for utp medium, the pmd interface side of the pma cons ists of four pair of 62.5-mhz pam5 encoded signals, while the pcs side provides the 1250 mbps input to a 8b1q4 pcs. ? pmd (physical medium depende nt) sublayer?the pmd sublayer is responsible for signal transmission. the typical pmd functionality includes amplif ier, modulation, and wave shaping. different pmd devices may support different media. ? mdi (medium-dependent interface ) sublayer?mdi is a connector. it defines different connector types for different physical media and pmd devices. figure 14-2 describes the different phys ical interface standards. figure 14-2. ieee 802.3z and 80 2.3ab physical standards ethernet/ieee 802.3 standard frames are based on the frame structure shown in figure 14-3 . the term ?packet? is sometimes used to refer to the frame plus the preamble and star t frame delimiter (sfd). figure 14-3. ethernet/ieee 802. 3 standard frame structure the elements of an ethernet frame are as follows: ? preamble? the 7-byte preamble of alterna ting ones and zeros used for receiver timing synchronization (each byte containing the value 0x55). ? start frame delimiter (sfd)?a sequence of 0xd5 (10101011 because th e bit ordering is lsb first) indicates the beginning of the frame. ? 48-bit destination address (da)?the first bit identifies the addr ess as an individu al address (0) or a group address (1). the second bit is used to indicate whether the address is locally-defined (1) or globally-defined (0). gigabit media-independent in terface (gmii) (optional) 1000basex pcs 8 bytes/10 bytes auto-negotiation 1000baselx fiber optics 1000basesx fiber optics 1000basecx copper mac full-duplex and/or half-duplex 802.3ab 1000baset pcs 1000baset pma shielded copper cable (25 m) multimode fiber (500 m) single-mode or multimode fiber (3 km) tbi 802.3z unshielded twisted pair (100 m) start frame delimiter preamble data destination address source address ty p e / length 6 bytes 1 byte 7 bytes 2 bytes 6 bytes 46?1500 bytes 4 bytes frame check sequence frame length is 64?1518 bytes 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-4 freescale semiconductor ? 48-bit source address (sa)? (original versions of the ieee 802.3 standard allowed 16-bit addressing, which has never been used widely.) ? ethernet type field/i eee 802.3 standard length field?the type field signifies the protocol (for example, tcp/ip) used in the rest of the frame. the length field specifies the length of the data portion of the frame. for both ethernet and ieee 802.3 standard frames to exist on the same lan, the length field must be unique from any type fields used in ethern et. this limitation requires that a type field be identified by a decimal number equal to or great er than 1536 (0x0600) but less than 65535 (0xffff). if the number, however, is between 0 and 1,500 (0x0000 through 0x05dc) then this field indicates the length of the mac client data. the range from 1,501 to 1,535 (0x5dd through 0x5ff) was intentionally left undefined. ? data and padding?padding is optional. it is only needed if the data is smaller than 46 octets (one octet = one byte) to ensure the minimum frame size of 64 octets as specified in the ieee 802.3 standard. in the 802.3x standard, th e first two octets of the data field are used as opcode (op) (pause = 0x0001) and the second two octets are used to transmit a pause time (pt) parameter (pausetime = 0x0000 for on and 0xffff for off). in a ddition, a third two-octet field can be used for an extended pause control parameter (pte). be cause the use of these fields varies with the protocol used, the ability to examine them a nd report their content can significantly accelerate ethernet frame processing. ? frame-check sequence (fcs)?specifies the st andard 32-bit cyclic redundancy check (crc) obtained using the standard ccitt-crc polynomia l on all fields except the preamble, sfd and crc. figure 14-4 provides additional details of the ethe rnet/ieee 802.3 standa rd frame structure. figure 14-4. ethernet/ieee 80 2.3 standard frame structure with more details relative to figure 14-4 , the ieee 802.3 standard, section 3.11 (m ac frame format) defines the frame format such that the octets of a frame are transmitted from left to right (preambl e first, the fcs last), and the bits of each octet are transmit ted least-significant bit (lsb) first. the destination address example shown in figure 14-4 (02608c:876543) which would normally be written as: 0000 0010 0110 0000 1000 1100 1000 0111 0110 0101 0100 0011 start frame delimiter preamble data destination address source address ty p e / length 6 bytes 1 byte 7 bytes vendor uservalue 2 bytes control ssap dsap information 6 bytes 46?1500 bytes 4 bytes llc frame yzxx_xxxx xxxx_xxxx xxxx_xxxx xxxx_xxxx xxxx_xxxx xxxx_xxxx bit 0 bit 47 destination address u/l i/g example: 02608c: 876543 (02608c = 3com, 876543 = uservalue assigned by 3com) 3 bytes frame check sequence frame length is 64?1518 bytes 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-5 is transmitted bit by bit as: 0100 0000 0000 0110 0011 0001 1110 0001 1010 0110 1100 0010 which is an individual address (because the lsb is cleared) but locally-defined (because the second least-significant bit is set). when first originated, a type field was used for protocol id entification. the ieee 802.3 standard eliminated the type field, replacing it with the length field. the length fi eld is used to identify the length, in bytes, of the data field. the protocol type in th e ieee 802.3 standard frames are held within the data portion of the packet. the l ogical link control (llc) is responsible for providing services to the network layer regardless of media type, such as fddi, ethe rnet, token ring, and others . the llc layer makes use of llc protocol data units (pdus ) in order to communicate betwee n the media access control (mac) layer and the upper layers of the protocol stack. th ree variables determine a ccess into the upper layers through the llc-pdu. the variables include the destinati on service access point (dsap), the source service acce ss point (ssap), and a control variable. the dsap address specifies a unique identifier with in the station providing protocol information for th e upper layer. the ssap prov ides the same informati on for the source address. the llc defines service access for protocols that conform to the open syst em interconnection (osi) model for network protocols. however, many prot ocols do not obey the rules for those layers and additional information must be added to the llc in order to provide information regarding those protocols. protocols that fall into this category include ip and ipx. the method used to provide this additional protocol information is called a subnetwork access pr otocol (snap) frame. a snap encapsulation is indicated by the dsap and ssap addre sses being set to 0xaa and the llc control field being set to 0x03. if that address is seen, a snap header follows. the s nap header is five bytes long. the first three bytes consist of the orga nization code (snap oui), which is assigned by the ieee. the last two bytes become the type value set fr om the original ethernet specifi cations if snap oui = 0, or they become a snap protocol identi fier if snap oui is non zero. the three-speed ethernet controller (tsec) allows the flexibility to accelerate the identification and retrieval of all the standard and non- standard protocols mentioned above. figure 14-5 shows the block diagram of the tsec. 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-6 freescale semiconductor figure 14-5. tsec block diagram 14.1.1 three-speed ethern et controller overview the tsec is designed to supp ort 10-, 100-, and 1000-mbps etherne t/ieee 802.3 standard networks and contains the following components: ? ethernet media acces s controller (mac) ? first-in first-out (fifo) controller ? direct memory acces s (dma) controller ? ten-bit interface (tbi) ? register-based statistical module that supports management information base (mib) remote monitoring (rmon) the most-significant byte of data in a receive or transmit data buffer corresponds to the most-significant byte of a frame, respectively. address/data filtering mac layer dma tx system clk data path pack words unpack words rx fifo 2 kbytes fifo control tx fifo 2 kbytes tx/rx descriptors tx/rx data tx/rx status block interface clocks to p h y to p h y to p h y to p h y gmii reduced signal reduced signal tbi tbi gmii rgmi rtbi tbi or or or mii mgmt mib counters interface interface 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-7 the complete tsec is designed for single mac a pplications. the tsec supports several standard mac-phy interfaces to c onnect to an external ethernet transceiver: ? mii interface running at 10/100 mbps ? gmii interface running at 1 gbps ? tbi interface that can be connected to a serdes device for fibre channel applications. ? reduced signal count versions of the gm ii (rgmii) and ten-bit (rtbi) interfaces while most of this document refers to the non-reduced signal count interfaces, it must be understood that these references also apply to the reduced signal count interfaces. the tsec software programming mode l is similar to the mpc8260 (pow erquicc ii) device. hence, it enables freescale customers to leve rage already implemented ethernet drivers, reducing the software development cycle. 14.2 features the MPC8555E tsec includes these distinctive features: ? ieee 802.3, 802.3u, 802.3x, 802.3z, 802.3ac, 802.3ab compliant ? support for different ethe rnet physical interfaces: ? 10/100/1gb ieee 802.3 gmii ? 10/100 mbps ieee 802.3 mii ? 10-mbps ieee 802.3 mii ? 1-gbps ieee 802.3z tbi ? 10/100 mbps rgmii ? 1-gbps full-duplex rgmii ? 1-gbps rtbi ? full- and half-duplex support (1 gbps supports only full-duplex) ? ieee 802.3 full-duplex flow cont rol (automatic pause frame gene ration or software programmed pause frame genera tion and recognition) ? support for out-of-sequence transmit que ue (for initiating flow-control) ? programmable maximum frame length supports jumbo frames (up to 9.6 kbytes) and ieee 802.1 virtual local area ne twork (vlan) frames ? retransmission from transmit fifo following a collision ? support for crc generation and veri fication of inbound/outbound packets ? address recognition ? each exact match can be program med to be accept ed or rejected ? broadcast address (accept/reject) ? exact match 48-bit indivi dual (unicast) address ? hash (256-bit hash) check of individual (unicas t) addresses ? hash (256-bit hash) check of group (multicast) addresses 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-8 freescale semiconductor ? promiscuous mode ? extraction data and its associated buffer descriptors can be directed to the processor?s l2 cache to reduce access latency ? interrupt coalescing subject to a threshold frame count er and/or a threshol d timer (independent functionality for received and tran smitted frames) ? rmon statistics support 14.3 modes of operation the primary tsec operationa l modes are the following: ? full- and half-duplex operation this is determined by maccfg2 re gister?s full-duplex bit. full- duplex mode is intended for use on point to point links between switches or end node to switch. half-duplex mode is used in connections between an end node and a repeater or between repeaters. if configured in half-duplex mode (only 10- and 100-mbps operation; maccfg2 register?s full-duplex bit is cleared), the mac comp lies with the ieee csma/cd access method. if configured in full-duplex m ode (10/100/1gb operation; maccfg2 register?s full-duplex bit is set), the mac supports flow control. if flow control is enabled, it allows the mac to receive or send pause frames. ? 10- and 100-mbps mii interface operation the mac-phy interface operates in mii mode by configuring bits maccfg2[22?23] = 01. the mii is the media-independent interface define d by the 802.3 standard for 10/100 mbps operation. the speed of operation is determined by the tsec n _tx_clk and tsec n _rx_clk signals, which are driven by the transceiver. the transceive r either auto-negotiates the speed or it may be controlled by software through the serial mana gement interface (ec_mdc/ec_mdio signals) to the transceiver. ? 1-gbps gmii and tbi interface operation the mac-phy interface operates in gmii mode by configuring bits maccfg2[22?23] = 10. the gmii is the gigabit media-independent inte rface defined by the 802.3 standard for 1-gbps operation. independently, the mac-phy interface can also oper ate in tbi mode. note that either the tbi or gmii interface is chosen; not both at the same time. tbi is the ten-bit interfac e which contains pcs functions (ten-bit encoding/decodi ng) as defined by the 802.3 standard. in reduced signal count mode (rgm ii or rtbi), the mac remains c onfigured in gmii or tbi but the tsec multiplexes and decodes the input si gnals and provides the mac with the expected interface. tsec provides the tsec n _gtx_clk to the phy in either gmii or tbi mode of operation. ? address recognition options the options supported are promiscuous, broadcast, exact individual address hash or exact match, and multicast hash match. for detailed descriptions refer to section 14.5.3.8.1, ?individual address registers 0?7 (iaddrn),? section 14.5.3.8.2, ?group address registers 0?7 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-9 (gaddrn),? section 14.5.3.4.1, ?receive cont rol register (rctrl),? and section 14.6.2.6, ?frame recognition.? ? rmon support see section 14.6.2.5, ?rmon support.? ? internal loopback internal loopback mode is selected through the loopback bit in the maccfg1 register. see section 14.6.2.10, ?internal and external loopback,? for details. 14.4 external signals description this section defines the tsec signals. the buses ar e described using the bus convention used in ieee 802.3 because the phy follows this same convention (tha t is, txd[7:0] means 0 is the lsb). notice that except for external physical in terfaces the buses and register s follow a big-endian format. the tsec network interface supports multiple options: ? the mii option requires 18 i/o signals (incl uding the ec_mdio and ec_mdc mii management interface) and supports both a da ta and a management interface to the phy (transceiver) device. the mii option supports both 10- and 100-mbps ethernet rates. ? the gmii option is a superset of the mii signals and supports a 1- gbps ethernet rate. ? the tbi interface shares signals with the gmii interface signals. ? finally, rgmii and rtbi opti ons are reduced-signal implemen tations of the gmii and tbi interfaces. 14.4.1 detailed signal descriptions table 14-1 contains detailed descriptions of the tsec interface signals. for rgmii mode details please refer to the hewlett-pack ard reduced gigabit media-independent in terface (rgmii) specification version 1.2a, dated 9/22/2000. all other mode s follow the ieee 802.3 standard, 2000 edition. input signals not used are internally disabled. output signals not used are driven low. 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-10 freescale semiconductor table 14-1. tsec signals?detailed signal descriptions signal i/o description tsec n _col i collision input. the behavior of this signal is not specified while in full-duplex mode. state meaning asserted/negated?in mii mode, this signal is asserted upon detection of a collision, and must remain asserted while the collision persists. this signal is not used in the tsec gmii, tbi, rtbi and rgmii modes. timing asserted/negated?this signal is not required to transition synchronously with tsec n _tx_clk or tsec n _rx_clk. tsec n _crs i carrier sense input. in tbi and rtbi modes this signal can be used as sdet (signal detect), an optional signal that some phys generate in tbi or rt bi modes. this signal is not used in the tsec gmii or rgmii modes. state meaning asserted/negated?in mii mode, tsec n _tx_clk is asserted while the transmit or receive medium is not idle. in the event of a collision, tsec n _crs must remain asserted for the duration of the collision. timing asserted/negated?this signal is not required to transition synchronously with tsec n _tx_clk or tsec n _rx_clk. tsec n _gtx_ clk o gigabit transmit clock. this signal is an output from the tsec into the phy. in gmii, tbi, or rtbi mode tsec n _gtx_clk is a 125-mhz clock that provides a timing reference for tx_en, txd, and tx_er. in rgmii mode tsec n _gtx_clk becomes the transmit clock and provides timing reference during 1000base-t (125-mhz), 100base-t (25-mhz) and 10base-t (2.5-mhz) transmissions. this signal is not used in mii mode. ec_gtx_ clk125 i gigabit transmit 125-mhz source. this signal must be generated externally with a crystal or oscillator, or is sometimes provided by the phy. in gmii, rgmii, rtbi or tbi mode, ec_gtx_clk125 is a 125-mhz input into the tsec and is used to generate all 125-mhz related signals and clocks. this input is not used in mii mode. ec_mdc o management data clock. in gmii, mii, rgmii, rtbi or tbi mode this signal is a clock (typically 2.5 mhz) supplied by the mac (ieee?set minimum period of 400 ns or a frequency of 2.5 mhz, but the device may be configured up to 12.5 mhz if su pported by the phy at that speed). this clock is generated by dividing the core complex bus (ccb) clock by eight. the ratio can be modified further by writing to miimcfg[29:31]. note that this signal is used during reset to configure the tsec interface to ?reduced-signal? or ?non-reduced-signal? mode. see section 4.4.3, ?power-on reset configuration ,? for more information. ec_mdio i/o management dat a input/output, bidi state meaning asserted/negated?in gmii, mii, rgmii, rtbi or tbi mode ec_mdio is a bidirectional signal to input phy-supplied status du ring management read cycles and output control during mii m anagement write cycles. timing asserted/negated?this signal is required to be synchronous with the ec_mdc signal. tsec n _rx_ clk i receive clock. in gmii, mii or rgmii mode, the receive clock tsec n _rx_clk is a continuous clock (2.5, 25, or 125 mhz) that provides a timing reference for tsec n _rx_dv, tsec n _rxd, and tsec n _rx_er. in tbi mode, tsec n _rx_clk is the input for a 62.5-mhz pma receive clock, 0 split phase with pma_rx_clk1 and is supplied by the serdes. in rtbi mode it is a 125-mhz receive clock. 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-11 tsec n _rx_dv i receive data valid. in gmii or mii mode, if tsec n _rx_dv is asserted, the phy is indicating that valid data is present on the gmii and mii interfaces. in rgmii mode, tsec n _rx_dv becomes rx_ctl. the rx_dv and rx_err are received on this signal on the rising and falling edges of tsec n _rx_clk. in tbi mode, tsec n _rx_dv represents receive code group (rcg) bit 8. together, with rcg[9] and rcg[7:0], they represents the 10-bit encoded symbol of gmii receive signals. in rtbi mode, tsec n _rx_dv represents receive code group (rcg) bit 4 and 9. on the positive edge of the tsec n _rx_clk, rcg[4] and rcg[3:0] represents the first half of the 10-bit encoded symbol. on the negative edge of the tsec n _rx_clk, rcg[9] and rcg[8:4] represents the second half of the 10-bit encoded symbol. tsec n _ rxd[7:0] i receive data in. in gmii mode, tsec n _rxd[7:4] with tsec n _rxd[3:0], represent one complete octet of data to be transferred fr om the phy to the mac when tsec n _rx_dv is asserted. in tbi mode, tsec n _rxd[7:4] represents rcg[7:4]. together, with rcg[9:8] and rcg[3:0], they represent the 10-bit encoded sy mbol of gmii receive signals. in gmii mode, tsec n _rxd[3:0] represents a nibble of data to be transferred from the phy to the mac when tsec n _rx_dv is asserted. a completely-form ed sfd must be passed across the mii. while tsec n _rx_dv is not asserted, tsec n _rxd has no meaning. in rgmii or rtbi mode, tsec n _rxd[3:0] are received on the rising edge of tsec n _rx_clk and tsec n _rxd[7:4] are received on the falling edge of tsec n _rx_clk. in tbi mode, tsec n _rxd[3:0] represents rcg[3:0]. together , with rcg[9:4], they represent the 10-bit encoded symbol of gmii receive signals. tsec n _rx_er i receive error state meaning asserted/negated?in gmii or mii mode, if tsec n _rx_er and tsec n _rx_dv are asserted, the phy has detected an error in the current frame. in tbi mode, tsec n _rx_er represents rcg[9]. toget her, with rcg[8:0], they represent the 10-bit encoded symbol of gmii receive signals. this signal is not used in the tsec rtbi or rgmii modes. tsec n _tx_ clk i transmit clock in. in mii mode, tsec n _tx_clk is a continuous clock (2 .5 or 25 mhz) that provides a timing reference for the tsec n _tx_en, tsec n _txd, and tsec n _tx_er signals. in gmii mode, tsec n _tx_clk provides the 2.5 or 25-mhz timing reference during 10base-t and 100base-t and comes from the phy. in 1000base-t this clock is not used and tsec n _gtx_clk (125 mhz) becomes the timing reference. the tsec n _gtx_clk is generated in the tsec and provided to the phy and the mac. the tsec n _tx_clk is generated in the phy and provided to the mac. in tbi mode, this signal is pma receive clock 1 62.5 mhz, split phase with pma_rx_clk0, and is supplied by the serdes. this signal is not used in the tsec rtbi or rgmii modes. table 14-1. tsec signals?detailed signal descriptions (continued) signal i/o description 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-12 freescale semiconductor 14.5 memory map/register definition the tsec uses a software model si milar to that employed by the fast ethernet function supported on the freescale mpc8260 cpm fcc and in the fec of the mpc860t. the tsec device is programmed by a combination of control/status registers (csr) and buffer descriptors. the csrs are used for mode control, interrupts, and to access status information. the descriptors are used to pass data buffers and rela ted buffer status or frame information between the hardware and software. all accesses to and from the regist ers must be made with 32-bit acces ses. there is no support for accesses of sizes other than 32 bits. this section of the document define s the memory map and describes th e registers in detail. the buffer descriptor is described in section 14.6.3, ?buffer descriptors.? the ten-bit interface (tbi) module mii registers are also described in this sect ion. the tbi registers are defined like phy registers and, as such, are accessed through the mii ma nagement interface in the same tsec n _ txd[7:0] o transmit data out. in gmii mode, tsec n _txd[7:4], together with tsec n _txd[3:0], represent one complete octet of data to be sent from the mac to the phy when tsec_tx_dv is asserted and has no meaning while tsec n _tx_en is negated. in tbi mode, tsec n _txd[7:4] represents transmit code group (tcg) bits 7:4. together, with tcg[9:8] and tcg[3:0], they re present the 10-bit encoded symbol. in gmii or mii mode, tsec n _txd[3:0] represent a nibble of data to be sent from the mac to the phy when tsec n _tx_en is asserted and have no meaning while tsec n _tx_en is negated. in rgmii or rtbi mode, tsec n _txd[3:0] are transmitted on the rising edge of tsec n _tx_clk, and tsec n _txd[7:4] are transmitted on the falling edge of tsec n _tx_clk. in tbi mode, tsec n _txd[3:0] represents tcg[ 3:0]. together, with tcg[ 9:4], they represent the 10-bit encoded symbol. note that some of these signals are also used duri ng reset to configure the tsec interface in gmii or tbi mode. additionally, some of these signals ar e used for other reset conf iguration settings for the MPC8555E. see section 4.4.3, ?power-on reset configuration,? for more information. tsec n _tx_en o transmit data valid. in gmii or mii mode, if tsec n _tx_en is asserted, the mac is indicating that valid data is present on the gmii?s or the mii?s tsec n _txd signals. in rgmii mode, tsec n _tx_en becomes tx_ctl. tx_en and tx_err are asserted on this signal on rising and falling edges of the tsec n _tx_clk, respectively. in tbi mode, tsec n _tx_en represents tcg[8]. together, with tcg[9] and tcg[7:0], they represent the 10-bit encoded symbol. in rtbi mode, tsec n _tx_en represents tcg[4]. together with tcg[9], tcg[3:0] and tcg[8:5], they represent the 10-bit encoded symbol. tsec n _tx_er o transmit error. in gmii or mii mode, assertion of tsec n _tx_er for one or more clock cycles while tsec n _tx_en is asserted causes the phy to transmit one or more illegal symbols. asserting tsec n _tx_er has no effect while operating at 10 mbps or while tsec n _tx_en is negated. this signal transitions synchronously with respect to tsec n _tx_clk. in tbi mode, tsec n _tx_er represents tcg[9]. together, wit h tcg[8:0], they represents the 10-bit encoded symbol. this signal is not used in the tsec rtbi or rgmii modes. table 14-1. tsec signals?detailed signal descriptions (continued) signal i/o description 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-13 way as the phys are accessed. for deta iled descriptions of the tbi regist ers (the mii register set for the ten-bit interface) please refer to section 14.5.4, ?ten-bit interface (tbi).? 14.5.1 top-level module memory map the tsec implementation requires 4 kbytes of memory-mapped space, of which more than 1 kbyte is reserved for future expansion. the space is divided into the following sections: ? general control/status registers ? transmit-specific cont rol/status registers ? receive-specific cont rol/status registers ? mac registers ? event/statistic counters held in the mib block ? hash function registers table 14-2 defines the top-level memory map. 14.5.2 detailed memory map? control/status registers table 14-3 lists the address, name, and a cross-reference to the complete description of each register. the offsets to the memory map table are defined for both tsecs. that is, tsec1 st arts at address offset 0x2_4000 and tsec2 starts at ad dress offset 0x2_5000. the registers for tsec1 are listed in table 14-3 , but the registers for tsec 2 are not. note that in table 14-3 the registers are the same for tsec2 except that the offset changes from 0x2_4 nnn to 0x2_5 nnn . undefined 4-byte addres s spaces within offset 0x000?0xfff are reserved. table 14-2. module memory map summary address function 000?0ff tsec general control/status registers 100?2ff tsec transmit c ontrol/status registers 300?4ff tsec receive control/status registers 500?5ff tsec mac registers 600?7ff tsec rmon mib registers 800?8ff tsec hash function registers 900?aff reserved b00?bff tsec attribute registers c00?fff future expansion space 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-14 freescale semiconductor table 14-3. module memory map offset name access 1 reset section/page tsec1 general control and status registers 0x2_4000? 0x2_400c reserved r 0x0000_0000 ? 0x2_4010 ievent?interrupt event register r/w 0x0000_0000 14.5.3.1.1/14-19 0x2_4014 imask?interrupt mask register r/w 0x0000_0000 14.5.3.1.2/14-22 0x2_4018 edis?error disabled register r/w 0x0000_0000 14.5.3.1.3/14-24 0x2_401c reserved r 0x0000_0000 ? 0x2_4020 ecntrl?ethernet cont rol register r/w 0x0000_0000 14.5.3.1.4/14-25 0x2_4024 minflr?minimum frame length register r/w 0x0000_0040 14.5.3.1.5/14-26 0x2_4028 ptv?pause time value register r/w 0x0000_0000 14.5.3.1.6/14-26 0x2_402c dmactrl?dma control register r/w 0x0000_0000 14.5.3.1.7/14-27 0x2_4030 tbipa?tbi phy address register r/w 0x0000_0000 14.5.3.1.8/14-28 0x2_4034? 0x2_4088 reserved r 0x0000_0000 ? tsec1 fifo control and status registers 0x2_404c fifo_pause_ctrl?fifo pause control register r/w 0x0000_0000 14.5.3.2.1/14-30 0x2_408c fifo_tx_thr?fifo transmit threshold register r/w 0x0000_0100 14.5.3.2.2/14-30 0x2_4090? 0x2_4094 reserved r 0x0000_0000 ? 0x2_4098 fifo_tx_starve?fi fo transmit starve register r/w 0x0000_0080 14.5.3.2.3/14-31 0x2_409c fifo_tx_starve_shutoff?fifo transmit starve shutoff register r/w 0x0000_0100 14.5.3.2.4/14-31 0x2_40a0? 0x2_40fc reserved r 0x0000_0000 ? tsec1 transmit control and status registers 0x2_4100 tctrl?transmit control register r/w 0x0000_0000 14.5.3.3.1/14-32 0x2_4104 tstat?transmit status register r/w 0x0000_0000 14.5.3.3.2/14-33 0x2_4108 reserved r 0x0000_0000 ? 0x2_410c tbdlen?txbd data length register r 0x0000_0000 14.5.3.3.3/14-34 0x2_4110 txic?transmit interrupt coalescing configuration register r/w 0x0000_0000 14.5.3.3.4/14-34 0x2_4114? 0x2_4120 reserved r 0x0000_0000 ? 0x2_4124 ctbptr?current txbd pointer register r 0x0000_0000 14.5.3.3.5/14-35 0x2_4128? 0x2_4180 reserved r 0x0000_0000 ? 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-15 0x2_4184 tbptr?txbd pointer register r/w 0x0000_0000 14.5.3.3.6/14-35 0x2_4188? 0x2_4200 reserved r 0x0000_0000 ? 0x2_4204 tbase?txbd base address register r/w 0x0000_0000 14.5.3.3.7/14-36 0x2_4208? 0x2_42ac reserved r 0x0000_0000 ? 0x2_42b0 ostbd?out-of-sequence txbd register r/w 0x0800_0000 14.5.3.3.8/14-36 0x2_42b4 ostbdp?out-of-sequence tx data buffer pointer register r/w 0x0000_0000 14.5.3.3.9/14-38 0x2_42b8? 0x2_42fc reserved r 0x0000_0000 ? tsec1 receive control and status registers 0x2_4300 rctrl?receive control register r/w 0x0000_0000 14.5.3.4.1/14-39 0x2_4304 rstat?receive status register r/w 0x0000_0000 14.5.3.4.2/14-40 0x2_4308 reserved r 0x0000_0000 ? 0x2_430c rbdlen?rxbd data length register r 0x0000_0000 14.5.3.4.3/14-40 0x2_4310 rxic?receive interrupt coalescing configuration register r/w 0x0000_0000 14.5.3.4.4/14-41 0x2_4314? 0x2_4320 reserved r 0x0000_0000 ? 0x2_4324 crbptr?current rxbd pointer register r 0x0000_0000 14.5.3.4.5/14-42 0x2_4328? 0x2_433c reserved r 0x0000_0000 ? 0x2_4340 mrblr?maximum receive buffer length register r/w 0x0000_0000 14.5.3.4.6/14-42 0x2_4344? 0x2_4380 reserved r 0x0000_0000 ? 0x2_4384 rbptr?rxbd pointer register r/w 0x0000_0000 14.5.3.4.7/14-43 0x2_4388? 0x2_4400 reserved r 0x0000_0000 ? 0x2_4404 rbase?rxbd base address register r/w 0x0000_0000 14.5.3.4.8/14-44 0x2_4408? 0x2_44fc reserved r 0x0000_0000 ? tsec1 mac registers 0x2_4500 maccfg1?mac configuration register 1 r/w 0x0000_0000 14.5.3.6.1/14-47 0x2_4504 maccfg2?mac configuration register 2 r/w 0x0000_7000 14.5.3.6.2/14-48 0x2_4508 ipgifg?inter-packet gap/inter-frame gap register r/w 0x4060_5060 14.5.3.6.3/14-49 0x2_450c hafdup?half-duplex register r/w 0x00a1_f037 14.5.3.6.4/14-50 table 14-3. module memory map (continued) offset name access 1 reset section/page 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-16 freescale semiconductor 0x2_4510 maxfrm?maximum frame length register r/w 0x0000_0600 14.5.3.6.5/14-51 0x2_4514? 0x2_451c reserved r 0x0000_0000 ? 0x2_4520 miimcfg?mii management configuration register r/w 0x0000_0000 14.5.3.6.6/14-52 0x2_4524 miimcom?mii management command register r/w 0x0000_0000 14.5.3.6.7/14-53 0x2_4528 miimadd?mii management address register r/w 0x0000_0000 14.5.3.6.8/14-53 0x2_452c miimcon?mii management control register w 0x0000_0000 14.5.3.6.9/14-54 0x2_4530 miimstat?mii management status register r 0x0000_0000 14.5.3.6.10/14-55 0x2_4534 miimind?mii management indicator register r 0x0000_0000 14.5.3.6.11/14-55 0x2_4538 reserved r 0x0000_0000 ? 0x2_453c ifstat?interface status register r/w 0x0000_0000 14.5.3.6.12/14-56 0x2_4540 macstnaddr1?station address register, part 1 r/w 0x0000_0000 14.5.3.6.13/14-56 0x2_4544 macstnaddr2?station address register, part 2 r/w 0x0000_0000 14.5.3.6.14/14-57 0x2_4548? 0x2_467c reserved r 0x0000_0000 ? tsec1 rmon mib registers tsec1 transmit and receive counters 0x2_4680 tr64?transmit and receive 64-byte frame counter register r/w 0x0000_0000 14.5.3.7.1/14-58 0x2_4684 tr127?transmit and receive 65- to 127-byte frame counter register r/w 0x0000_0000 14.5.3.7.2/14-58 0x2_4688 tr255?transmit and receive 128- to 255-byte frame counter register r/w 0x0000_0000 14.5.3.7.3/14-59 0x2_468c tr511?transmit and receive 256- to 511-byte frame counter register r/w 0x0000_0000 14.5.3.7.4/14-59 0x2_4690 tr1k?transmit and receive 512- to 1023-byte frame counter register r/w 0x0000_0000 14.5.3.7.5/14-60 0x2_4694 trmax?transmit and receive 1024- to 1518-byte frame counter register r/w 0x0000_0000 14.5.3.7.6/14-60 0x2_4698 trmgv?transmit and receive 1519- to 1522-byte good vlan frame count register r/w 0x0000_0000 14.5.3.7.7/14-61 tsec1 receive counters 0x2_469c rbyt?receive byte counter register r/w 0x0000_0000 14.5.3.7.8/14-61 0x2_46a0 rpkt?receive packet counter register r/w 0x0000_0000 14.5.3.7.9/14-62 0x2_46a4 rfcs?receive fcs error counter register r/w 0x0000_0000 14.5.3.7.10/14-62 0x2_46a8 rmca?receive multicast packet counter register r/w 0x0000_0000 14.5.3.7.11/14-63 table 14-3. module memory map (continued) offset name access 1 reset section/page 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-17 0x2_46ac rbca?receive broadcast packet counter register r/w 0x0000_0000 14.5.3.7.12/14-63 0x2_46b0 rxcf?receive control frame packet counter register r/w 0x0000_0000 14.5.3.7.13/14-64 0x2_46b4 rxpf?receive pause frame packet counter register r/w 0x0000_0000 14.5.3.7.14/14-64 0x2_46b8 rxuo?receive unknown op code counter register r/w 0x0000_0000 14.5.3.7.15/14-65 0x2_46bc raln?receive alignment error counter register r/w 0x0000_0000 14.5.3.7.16/14-65 0x2_46c0 rflr?receive frame length error counter register r/w 0x0000_0000 14.5.3.7.17/14-66 0x2_46c4 rcde?receive code error counter register r/w 0x0000_0000 14.5.3.7.18/14-66 0x2_46c8 rcse?receive carrier sense error counter register r/w 0x0000_0000 14.5.3.7.19/14-67 0x2_46cc rund?receive undersize packet counter register r/w 0x0000_0000 14.5.3.7.20/14-67 0x2_46d0 rovr?receive oversize packet counter register r/w 0x0000_0000 14.5.3.7.21/14-68 0x2_46d4 rfrg?receive fragments counter register r/w 0x0000_0000 14.5.3.7.22/14-68 0x2_46d8 rjbr?receive jabber counter register r/w 0x0000_0000 14.5.3.7.23/14-69 0x2_46dc rdrp?receive drop register r/w 0x0000_0000 14.5.3.7.24/14-69 tsec1 transmit counters 0x2_46e0 tbyt?transmit byte counter register r/w 0x0000_0000 14.5.3.7.25/14-70 0x2_46e4 tpkt?transmit packet counter register r/w 0x0000_0000 14.5.3.7.26/14-70 0x2_46e8 tmca?transmit multicast packet counter register r/w 0x0000_0000 14.5.3.7.27/14-71 0x2_46ec tbca?transmit broadcast packet counter register r/w 0x0000_0000 14.5.3.7.28/14-71 0x2_46f0 txpf?transmit pause control frame counter register r/w 0x0000_0000 14.5.3.7.29/14-72 0x2_46f4 tdfr?transmit deferral packet counter register r/w 0x0000_0000 14.5.3.7.30/14-72 0x2_46f8 tedf?transmit excessive deferral packet counter register r/w 0x0000_0000 14.5.3.7.31/14-73 0x2_46fc tscl?transmit single collision packet counter register r/w 0x0000_0000 14.5.3.7.32/14-73 0x2_4700 tmcl?transmit multiple collisio n packet counter register r/w 0x0000_0000 14.5.3.7.33/14-74 0x2_4704 tlcl?transmit late collision packet counter register r/w 0x0000_0000 14.5.3.7.34/14-74 0x2_4708 txcl?transmit excessive collision packet counter register r/w 0x0000_0000 14.5.3.7.35/14-75 0x2_470c tncl?transmit total collision counter register r/w 0x0000_0000 14.5.3.7.36/14-75 0x2_4710 reserved r 0x0000_0000 ? 0x2_4714 tdrp?transmit drop fram e counter register r/w 0x0000_0000 14.5.3.7.37/14-76 0x2_4718 tjbr?transmit jabber frame counter register r/w 0x0000_0000 14.5.3.7.38/14-76 0x2_471c tfcs?transmit fcs error counter register r/w 0x0000_0000 14.5.3.7.39/14-77 0x2_4720 txcf?transmit control fram e counter register r/w 0x0000_0000 14.5.3.7.40/14-77 0x2_4724 tovr?transmit oversize frame counter register r/w 0x0000_0000 14.5.3.7.41/14-78 table 14-3. module memory map (continued) offset name access 1 reset section/page 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-18 freescale semiconductor 0x2_4728 tund?transmit undersize frame counter register r/w 0x0000_0000 14.5.3.7.42/14-78 0x2_472c tfrg?transmit fragments frame counter register r/w 0x0000_0000 14.5.3.7.43/14-79 tsec1 general registers 0x2_4730 car1?carry register one register r/w 0x0000_0000 14.5.3.7.44/14-79 0x2_4734 car2?carry register two register r/w 0x0000_0000 14.5.3.7.45/14-80 0x2_4738 cam1?carry register one mask register r/w 0xfe01_ffff 14.5.3.7.46/14-82 0x2_473c cam2?carry register two mask register r/w 0x000f_ffff 14.5.3.7.47/14-83 0x2_4740? 0x2_47fc reserved r 0x0000_0000 ? tsec1 hash function registers 0x2_4800 iaddr0?individual address register 0 r/w 0x0000_0000 14.5.3.8.1/14-84 0x2_4804 iaddr1?individual address register 1 r/w 0x0000_0000 0x2_4808 iaddr2?individual address register 2 r/w 0x0000_0000 0x2_480c iaddr3?individual address register 3 r/w 0x0000_0000 0x2_4810 iaddr4?individual address register 4 r/w 0x0000_0000 0x2_4814 iaddr5?individual address register 5 r/w 0x0000_0000 0x2_4818 iaddr6?individual address register 6 r/w 0x0000_0000 0x2_481c iaddr7?individual address register 7 r/w 0x0000_0000 0x2_4820? 0x2_487c reserved r 0x0000_0000 ? 0x2_4880 gaddr0?group address register 0 r/w 0x0000_0000 14.5.3.8.2/14-85 0x2_4884 gaddr1?group address register 1 r/w 0x0000_0000 0x2_4888 gaddr2?group address register 2 r/w 0x0000_0000 0x2_488c gaddr3?group address register 3 r/w 0x0000_0000 0x2_4890 gaddr4?group address register 4 r/w 0x0000_0000 0x2_4894 gaddr5?group address register 5 r/w 0x0000_0000 0x2_4898 gaddr6?group address register 6 r/w 0x0000_0000 0x2_489c gaddr7?group address register 7 r/w 0x0000_0000 0x2_48a0? 0x2_4aff reserved r 0x0000_0000 ? tsec1 attribute registers 0x2_4b00? 0x2_4bf4 reserved r 0x0000_0000 ? 0x2_4bf8 attr?attribute register r/w 0x0000_0000 14.5.3.9.1/14-85 table 14-3. module memory map (continued) offset name access 1 reset section/page 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-19 14.5.3 memory-mapped register descriptions this section provides a detailed desc ription of all the tsec registers. because all of the tsec registers are 32 bits wide, only 32-bit register accesses are supported. 14.5.3.1 tsec general contro l and status registers this section describes general control and status regi sters used for both transmitt ing and receiving ethernet frames. all of the registers are 32 bits wide. 14.5.3.1.1 interrupt e vent register (ievent) if an event occurs that sets a bit in the interrupt event (ievent) register, shown in figure 14-6 , an interrupt is generated if the corresponding bit in the inte rrupt enable register (ima sk) is also set. clearing the ievent bit clears the interrupt signa l. the bit in the ievent register is cleared if a 1 is written to that bit position. a write of 0 has no effect. these interrupts can be divided into operational inte rrupts, transceiver/networ k error interrupts, and internal error interrupts. interrupts that may occur in normal operation are: ? gtsc, grsc, txf, txb, txc, rxf, rxb, rxc, mmrd, mmwr, and msro interrupts resulting from erro rs/problems detected in the network or transceiver are: ? babr, babt, lc, and crl/xda interrupts resulting from internal errors are: ? eberr, xfun, and bsy some of the error interrupts are i ndependently counted in the manageme nt information ba se (mib) block counters. software may choose to mask off these in terrupts because these errors are visible to network management through the mib counters. 0x2_4bfc attreli?attribute el & ei register r/w 0x0000_0000 14.5.3.9.2/14-87 tsec1 future expansion space 0x2_4c00? 0x2_4fff reserved r 0x0000_0000 ? tsec2 registers 0x2_5000? 0x2_5fff tsec2 registers note: tsec2 has the same memory-mapped registers that are described for tsec1 from 0x 2_4000 to 0x2_4fff except the offsets are from 0x 2_5000 to 0x2_5fff. 1 r = means read-only, w = write only, r/w = read and write, lh = latches high, sc = self-clearing. table 14-3. module memory map (continued) offset name access 1 reset section/page 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-20 freescale semiconductor table 14-4 describes the fields of the ievent register. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r babr rxc bsy eberr 0 msro gtsc babt txc txe txb txf 0 lc crl/ xda xfun w reset 0000_0000_0000_0000 16 17 20 21 22 23 24 25 31 r rxb 00 00 mmrd mmwr grsc rxf 0000000 w reset 0000_0000_0000_0000 offset tsec1:0x2_4010; tsec2:0x2_5010 figure 14-6. ievent register definition table 14-4. ievent field descriptions bits name description 0 babr babbling receive error. this bit indicates that a frame was received wit h length in excess of the mac?s maximum frame length register wh ile maccfg2[huge frame] is set. 0 excessive frame not received. 1 excessive frame received. 1 rxc receive control interrupt. a control frame was receiv ed. if maccfg1[rx_flow] is set, a pause operation is performed lasting for the duration specified in the received pause control frame and beginning when the frame was received. 0 control frame not received. 1 control frame received. 2 bsy busy condition interrupt. indicates that a frame was received and discarded due to a lack of buffers. when ievent[bsy] is set rstat[qhlt] is also set. in order to begin receiving packets ag ain, the user must clear rstat[qhlt]. this bit and rstat[qhlt] are set when ever the tsec reads an rxbd with its empty field cleared. 0 no frame received and discarded. 1 frame received and discarded. 3 eberr ethernet bus error. this bit in dicates that a system bus error for a memory read occurred while a dma transaction was underway. if the eberr is set while tr ansmission is in progress, the dma stops sending data to the tx fifo which eventua lly causes an underrun error (xfun) and tstat[thlt] is set. if the eberr is set while receiving a frame, the dm a discards the frame and rstat[qhlt] is set. 0 no system bus error occurred. 1 system bus error occurred. 4?reserved 5 msro mstat register overflow. this interrupt is asse rted if the count for one of the mstat registers has exceeded the size of the register. 0 mstat count not exceeding register size. 1 mstat count exceeds register size. 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-21 6 gtsc graceful transmit stop complete. graceful stop means that the transmitter is put into a pause state after completion of the frame currently being transmitted. this interrupt is asserted for one of two reasons. ? a graceful stop, which was initiated by setting dmactrl[gts], is now complete. ? a graceful stop, which was initiated by setting tctrl[tfc_pause], is now complete. 0 graceful transmit stop not complete or not initiated. 1 graceful transmit stop completed. 7 babt babbling transmit error. this bit indicates that the transmitted frame length has exceeded the value in the mac?s maximum frame length register and maccfg2[huge frame] is cleared. frame truncation occurs when this condition occurs. txbd[txtrunc] is set in the last txbd (txbd[l] is set) of the frame. 0 transmitted frame length not exceeding maximum frame length. 1 transmitted frame length exceeding maximum frame length. 8 txc transmit control interrupt. this bit indi cates that a control frame was transmitted. 0 control frame not transmitted. 1 control frame transmitted. 9 txe transmit error. this bit indicates that an erro r occurred on the transmitted channel that has caused tstat[thlt] to be set by tsec. this bit is set wh enever any transmit error occurs that causes the transmitter to halt (eberr, lc, crl/xda, xfun). it is not set if dmactrl[wop] is set and tsec runs out of txbds to process. in order to begin transmi tting packets again, the user must clear tstat[thlt]. 0 no transmit channel error occurred. 1 transmit channel error occurred. 10 txb transmit buffer. this bit indicates that a transmit buffer descriptor was updated whose i (interrupt) bit was set in its status word and was not the last buffer descriptor of the frame. 0 no transmit buffer descriptor updated. 1 transmit buffer descriptor updated. 11 txf transmit frame interrupt. this bit indicates that a frame was transmitted and that the last corresponding transmit buffer descriptor (txbd) was updated. this only oc curs if the i (interrupt) bit in the status word of the buffer descriptor is set. 0 no frame transmitted/txbd not updated. 1 frame transmitted/txbd updated. 12 ? reserved 13 lc late collision. this bit indicates that a collisi on occurred beyond the collision window (slot time) in half-duplex mode. the frame is truncated with a ba d crc and the remainder of the frame is discarded. 0 no late collision occurred. 1 late collision occurred. 14 crl/ xda collision retry limit/excessive defer abort. this bit indicates either one of two conditions occurred while attempting to transmit a frame: 1) the number of successive transmission collisions has exceeded the mac?s hafdup[retransmission maximum] count or 2) an excessive defer abort condition has occurred. an excessive defer abort condition occurs when the tsec waits more than 3036 bytes while attempting to send a frame and hafd up[excess_defer] is 0. the txbd[def] or ostbd[def] is also set. in either case the frame is discarded without being transmitted and the tsec is halted (tstat[thlt] is set). the crl or xda condition can only occur while in half-duplex mode. 0 successive transmission collisions do not exceed maximum and/or no excessive defer abort condition has occurred. 1 successive transmission collisions exceed maximum or an excessive defer abort condition has occurred. table 14-4. ievent field descriptions (continued) bits name description 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-22 freescale semiconductor 14.5.3.1.2 interrupt m ask register (imask) the interrupt mask register provide s control over which possible interrupt events are allowed to generate an actual interrupt. all implemented bits in this csr are r/w. this register is cleared upon a hardware reset. if the corresponding bits in bot h the ievent and imask registers ar e set, an interrupt is generated. the interrupt signal can be cleared by clearing the corresponding ievent bit. 15 xfun transmit fifo underrun. this bit indicates that th e transmit fifo became empty before the complete frame was transmitted. 0 transmit fifo not underrun. 1 transmit fifo underrun. 16 rxb receive buffer. these bits indicate that a receive buffer descriptor was updated which had the i (interrupt) bit set in its status word and was not the last buffer descriptor of the frame. 0 receive buffer descriptor not updated. 1 receiver buffer descriptor updated. 17?20 ? reserved 21 mmrd mii management read completion 0 mii management read not issued or in process. 1 mii management read completed that was initiated by a user through the mii scan or read cycle command. 22 mmwr mii management write completion 0 mii management write not issued or in process. 1 mii management write completed that was initiated by a user write to the miimcon register. 23 grsc graceful receive stop complete. this interrupt is asse rted if a graceful receive stop is completed. it allows the user to know if the system has completed the stop an d it is safe to write to receive registers (status, control or configuration regist ers) that are used by the system during normal operation. 0 graceful stop not completed. 1 graceful stop completed. 24 rxf receive frame interrupt. the last receive buffer de scriptor (rxbd) of a frame was updated. this occurs only if the i (interrupt) bit in the buffer descriptor status word is set. 0 frame not received. 1 frame received. 25?31 ? reserved table 14-4. ievent field descriptions (continued) bits name description 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-23 figure 14-7 shows the imask register. table 14-5 describes the fields of the imask register. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r bren rxcen bsyen eberren 0 msroen gtscen bten txcen txeen txben txfen 0 lcen crl/ xdaen xfunen w reset 0000_0000_0000_0000 16 17 20 21 22 23 24 25 31 r rxben 00 00 mmrd mmwr grscen rxfen 000000 0 w reset 0000_0000_0000_0000 offset tsec1:0x2_4014; tsec2:0x2_5014 figure 14-7. imask register definition table 14-5. imask field descriptions bits name description 0 bren babbling receiver interrupt enable 1 rxcen receive control interrupt enable 2 bsyen busy interrupt enable 3 eberren ethernet controller bus error enable 4?reserved 5 msroen mstat register overflow interrupt enable 6 gtscen graceful transmit stop complete interrupt enable 7 bten babbling transmitter interrupt enable 8 txcen transmit control interrupt enable 9 txeen transmit error interrupt enable 10 txben transmit buffer interrupt enable 11 txfen transmit frame interrupt enable 12 ? reserved 13 lcen late collision enable 14 crl/xdaen collision retry limit/excessive defer enable 15 xfunen transmit fifo underrun enable 16 rxben receive buffer interrupt enable 17?20 ? reserved 21 mmrd mii management read completion enable 22 mmwr mii management write completion enable 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-24 freescale semiconductor 14.5.3.1.3 error disabled register (edis) the error disabled register, shown in figure 14-8 , controls error reporting by the tsec. the ievent bit corresponding to an error will not be se t if the error is disabled in edis. table 14-6 describes the fields of the edis register. 23 grscen graceful receive stop complete interrupt enable 24 rxfen receive frame interrupt enable 25?31 ? reserved 0 1 2 3 4 8 10 12 13 16 31 r00 bsydis eberrdis 00000000 0 lcdis 000000000000000000 w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_4018; tsec2:0x2_5018 figure 14-8. error disabled register (edis) table 14-6. edis field descriptions bits name description 0?1 ? reserved 2 bsydis busy disable 0 allow tsec to report ievent[bsy] status and halt buffer descriptor queue if bsy condition occurs. 1 do not set ievent[bsy] and do not halt buffer descriptor queue if bsy condition occurs. 3 eberrdis ethernet controller bus error disable 0 allow tsec to report ievent[eberr] status and halt buffer descriptor queue if eberr condition occurs. 1 do not set ievent[eberr] and do not halt buffer descriptor queue if ebe rr condition occurs. 4?12 ? reserved 13 lcdis late collision disable 0 allow tsec to report ievent[lc] stat us, set the buffer descriptor lc field, and halt buffer descriptor queue if lc condition occurs. 1 do not set ievent[lc] nor the buffer descriptor lc field, and do no t halt buffer descriptor queue if lc condition occurs. 14?31 ? reserved table 14-5. imask field descriptions (continued) bits name description 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-25 14.5.3.1.4 ethernet cont rol register (ecntrl) ecntrl, shown in figure 14-9 , is used to reset, configure, and initialize the tsec. table 14-7 describes the fields of the ecntrl register. 01617181920252627282931 r0000000000000000 0 clrcnt autoz sten 000000tbimrpm r100m 000 w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_4020; tsec2:0x2_5020 figure 14-9. ecntrl register definition table 14-7. ecntrl field descriptions bits name description 0?16 ? reserved 17 clrcnt clear all statistics counters 0 allow mstat counters to continue to increment. 1 reset all mstat counters. this bit is self-resetting. 18 autoz automatically zero addressed statistical counter values, input to mstat module. 0 the user must write the addressed counter zero after a host read. 1 the addressed counter value is zeroed on a host read. this is a steady state signal and must be set prior to enabling the ethernet controller and must not be changed without proper care. 19 sten statistics enabled, input to mstat module. 0 statistics not enabled 1 enables internal counters to update this is a steady state signal and must be set prior to enabling the ethernet controller and must not be changed without proper care. 20?25 ? reserved 26 tbim ten-bit interface mode. if this bit is set, ten-bit in terface mode is enabled. this bit can be signal configured at reset to set or clear using the tsec n _gtx_clk signal. 0 gmii or mii mode interface 1 tbi mode interface 27 rpm reduced signal mode. if this bit is set, a reduced signal interface is expected. ecntrl[tbi mode] selects gmii or tbi. if rpm is selected, the mac must be in gmii or tbi mode (rmii is not supported). this register can be signal configured at reset to 0 or 1 with the ec_mdc signal. 0 gmii or tbi in non-reduced signal mode configuration 1 rgmii or rtbi reduced signal mode 28 r100m rgmii 100 mode. this bit is ignored unless rpm is set and maccfg2[i/f mode] is assigned to 10/100 (01). if this bit is set, the tsec interface is in 100 mbps speed. 0 rgmii is in 10 mbps mode 1 rgmii is in 100 mbps mode 29?31 ? reserved 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-26 freescale semiconductor 14.5.3.1.5 minimum frame length register (minflr) minflr is written by the user. it tells tsec the sm allest packet to accept and place in a receive buffer pointed to by the rxbd. figure 14-10 shows the minflr register. table 14-8 describes the fields of the minflr register. 14.5.3.1.6 pause time va lue register (ptv) ptv, shown in figure 14-11 , is written by the user to store the pause duration used when the tsec initiates a pause frame through tctrl[tfc_pause]. the low-orde r 16 bits (pt) represent the pause time and the high-order 16 bits (pte) represent the extended pause control parameter. the paus e time is measured in units of pause_quanta, equal to 512 bit times. the pause time can ra nge from 0 to 65,535 pause_quanta, or 0 to 33,553,920 bit times. see section 14.6.2.7, ?flow control , ? for additional details. 0 24 25 31 r0000000000000000000000000 minflr w reset 0000_0000_0000_0000_0000_0000_0100_0000 offset tsec1:0x2_4024; tsec2:0x2_502 figure 14-10. minflr register definition table 14-8. minflr field descriptions bits name description 0?24 ? reserved 25?31 minflr minimum receive frame length (typically 64 deci mal). if the ethernet receives an incoming frame shorter than minflr, it discards that frame unless rctrl[rsf] (receive short frames) is set, in which case rxbd[sh] (frame too short) is set in the last rxbd . the largest allowable value for minflr is 64. unlike the mpc8260, in which pads are added to make the tr ansmit frame equal to minflr bytes, if padding is requested, tsec always pads transmit frames to 64 bytes ignoring minflr. minflr is only used to determine the minimum size of acceptable receive frames. 0151631 r pte pt w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_4028; tsec2:0x2_5028 figure 14-11. ptv register definition 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-27 table 14-9 describes the fields of the ptv register. 14.5.3.1.7 dma control register (dmactrl) dmactrl, shown in figure 14-12 , is used to configure the dma block. register. table 14-10 describes the fields of the dmactrl register. table 14-9. ptv field descriptions bits name description 0?15 pte extended pause control. this field allows software to add a 16-bit additional control parameter into the pause frame to be sent when tctrl[tfc_pause] is set. note that current ieee 802.3 paus e frame format requires this parameter to be set to 0. 16?31 pt pause time value. represents the 16-bit pause quanta (that is, 512 bit times). this pause value is used as part of the pause frame to be sent when tctrl[tfc_pause] is set. see section 14.6.2.7, ?flow control,? for more information. 022232425262728293031 r 0 000000000000000000000 0 0 tdsen tbdsen 0 grs gts 0 wwr wop w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_402c; tsec2:0x2_502c figure 14-12. dmactrl register definition table 14-10. dmactrl field descriptions bits name description 0?23 ? reserved 24 tdsen tx data snoop enable 0 disables snooping of all transmit frames from memory. 1 enables snooping of all transmit frames from memory. 25 tbdsen txbd snoop enable 0 disables snooping of all transmit bd memory accesses. 1 enables snooping of all transmit bd memory accesses. 26 ? reserved 27 grs graceful receive stop. if this bit is set, the etherne t controller stops receiving frames following completion of the frame currently being received. (that is, after a valid end of frame was received). the buffer of the receive frame associated with the eof is closed and the ievent[grsc] is set. because the mac?s receive enable bit (maccfg[rx_en]) may still be set, the mac may continue to receive but the tsec ignores the receive data until grs is cleared. if this bit is cleare d, the tsec scans the input data stream for the start of a new frame (preamble sequence and start of frame delimiter) and the first valid frame received uses the next rxbd. if grs is set, the user must monitor the graceful rece ive stop complete (grsc) bi t in the ievent register to insure that the graceful receive stop was comp leted. the user can then clear ievent[grsc] and can write to receive registers that are accessible to both user and the tsec hardwar e without fear of conflict. 0 tsec scans input data stream for valid frame. 1 tsec stops receiving frames following completion of current frame. 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-28 freescale semiconductor 14.5.3.1.8 tbi physical ad dress register (tbipa) this tbipa, shown in figure 14-13 , is writable by the us er to assign a physical a ddress to the tbi for mii management configuration. the tb i registers are accessed at the of fset of tbipa. for detailed descriptions of the tbi registers (the mii regist er set for the ten-bit interface) please refer to section 14.5.4, ?ten-bit interface (tbi).? 28 gts graceful transmit stop. if this bit is set, the ether net controller stops transmission after the completion of any frame that is currently being transmitted and the gtsc interrupt in the ievent register is asserted. if frame transmission is not currently underway, the gtsc interrupt is asserted immediately. once transmission has completed, a ?restart? can be accomplished by clearing gts. 0 controller continues. 1 controller stops transmission a fter completion of current frame. 29 ? reserved 30 wwr write with response. this bit gives the user the assurance that a bd was updated in memory before it receives an interrupt concerning a transmit or receive frame. 0 do not wait for acknowledgement from system for bd writes before setting ievent bits. 1 before setting ievent bits txb, txf, txe, ie, xfun, lc, crl/xda, rxb, rxf, the tsec waits for acknowledgement from system that the transmit or receive bd being updated was stored in memory. 31 wop wait or poll. this bit, which is applicable only to t he transmitter, provides the user the option for the tsec to periodically poll txbd or to wait for software to tell tsec to fetch a buffer descriptor. while operating in the ?wait? mode, the tsec allows two additional reads of a descriptor which is not ready before entering a halt state. no interrupt is driven. (ievent[txe] is clear.) to resume transmission, software must clear tstat[thlt]. note that if this bit is set, the user must ensure th at all txbds involved with sending a frame have their ready bits set before any transmission begins. otherwise, tsec behaves in a boundedly undefined fashion. a buffer descriptor is considered not ready when its txbd[ready] field is clear or its txbd[data length] field is zero. it is considered ready when both txbd[ready] is set and txbd[data length] is non-zero. in wait mode (dmactrl[wop] is set) when tsec is processing a frame and an intermediate txbd?s ready bit is cleared, tsec does not halt, but instead continuously polls the same txbd until the txbd becomes ready or an ethernet interface error or a memory error is encountered. if the txbd becomes ready, tsec continues to process the frame. if an error occurs before the txbd becomes ready, tsec reports the error in both the ievent register as well as the txbd fo r ethernet interface errors, or the ievent[eberr] for a memory error and sets the tstat[thlt] bit. note t hat software must eventually set all of its txbds for a frame, because tsec continuousl y reads an intermediate txbd until it becomes ready if insufficient data has been read to surpass the fifo transmit threshold (fifo_tx_thr) register value. note, the polling in wait mode differs from the polling in poll mode. in poll mode polling is performed every 512 ethernet bus tx clocks. in wait mode polling is performed as fast as possible after the txbd[ready] = 0 is read. if software is slow in setting all txbd read y bits of a frame to a one, then the system performance may decrease. 0 poll txbd every 512 clocks. 1 do not poll, but wait for a write to tstat[thlt]. table 14-10. dmactrl field descriptions (continued) bits name description 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-29 table 14-11 describes the fields of the tbipa register. 14.5.3.2 tsec fifo contro l and status registers the following registers allow the user to change some of the default settings in the fifo that can be used to optimize operation for performance or for safety. they must be set carefully in order to avoid an underrun condition. underrun is an error condition in whic h data is not retrieved from external memory quickly enough, leaving the tx fifo empty before the complete frame is transmitted. be cause different combinations of events, several of which are dete rmined by the user, can le ad to underrun, the tsec provides several fifo register s that allow the user to se lect the proper setting to be able to tune the system and obtain the maximum perf ormance with minimal ch ance of underrun. the prin cipal causes for underrun in the tsec are: ? misaligned data buffer addresses ? small data buffer sizes ? combinations of the above it is recommended that the minimum size data buffers be 64 bytes and that data buf fers be 64-byte aligned. the user can deviate from these reco mmended values to try to increase performance or to use less memory, but unless the default values of some of the fifo re gisters are adjusted, the probability of an underrun may also increase. the fifo_tx_thr (def ault is 256 entries or 1 kbyte) indicates the amount of data required to be in the fifo before star ting the transmission of a frame. the fifo_tx_starve (default is 128 entries or 512 bytes) is used to indicate that the amount of data in the fifo is so low that the risk of underrun is extremely high. the fifo_tx_starve_s hutoff (default is 256 entries or 1 kbyte) contains the watermark level to be used for exiting the starve state. these registers are intended to allow the user to make the proper trade-off. if triggered, th e starve mode, for instance, automatically raises the priority of tsec fetches from memory. 0 26 27 31 r000000000000000000000000000 tbipa w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_4030; tsec2:0x2_5030 figure 14-13. tbipa register definition table 14-11. tbipa field descriptions bits name description 0?26 ? reserved 27?31 tbipa tbi phy address. this field is used to progra m the phy address of the ten-bit interface?s mii management bus. to access the tbi register the user must write the tbipa value to the miimadd[phy address] register located in the mac register section. refer to section 14.5.3.6.8, ?mii m anagement address register (miimadd).? 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-30 freescale semiconductor 14.5.3.2.1 fifo pause control register (fifo_pause_ctrl) fifo_pause_ctrl, shown in figure 14-14 , is writable by the user to configure the properties of the tsec fifo. table 14-12 describes the fields of th e fifo_pause_ctrl register. 14.5.3.2.2 fifo transmit threshol d register (fifo_tx_thr) the main purpose of the threshold regist er is to trigger the unloading of fifo data to the phy. it represents the numerical sram entry (0?511 for 2-kbyte fifo) to trigger the threshold function. if the number of valid entries in the fifo is equal to or greater th an the threshold register, transmission can begin. this register is read/write by software and is initialized to 0000_0000_0000_0000_0000_0001_0000_0000 at system reset. figure 14-15 shows the fifo_tx_thr register. 0 15 r0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset 0000_0000_0000_0000 16 29 30 31 r0 0 0 0 0 0 0 0 0 0 0 0 0 0 tfc_pause_en 0 w reset 0000_0000_0000_0000 offset tsec1:0x2_404c; tsec2:0x2_504c figure 14-14. fifo_pause_ctrl register definition table 14-12. fifo_pause_ctrl field descriptions bits name description 0?29 ? reserved 30 tfc_pause_en tfc_pause enable. this bit enables the abi lity to transmit a pause control frame by setting the tctrl[tfc_pause] bit. this bit is cleared at reset but should always be set during initialization as undefined behavior results during normal operation when left cleared. 0 pause control frame transmission disabled (default, but must be set during initialization). 1 pause control frame transmission enabled. 31 ? reserved 0 22 23 31 r00000000000000000000000 fifo_tx_thr w reset 0000_0000_0000_0000_0000_0001_0000_0000 offset tsec1:0x2_408c; tsec2:0x2_508c figure 14-15. fifo_tx_t hr register definition 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-31 table 14-13 describes the fields of the fifo_tx_thr register. 14.5.3.2.3 fifo transmit starve register (fifo_tx_starve) the purpose of the starve register, shown in figure 14-16 , is to inform the system of extremely imminent underrun conditions. it repres ents the numerical sram entry (0-511 for 2-kbyte fifo) to trigger the starve function. if the number of valid entries in the fifo is less than or e qual to the starve register, a starve alert is triggered. table 14-14 describes the fields of th e fifo_tx_starve register. 14.5.3.2.4 fifo transmit starve shuto ff register (fifo_tx_starve_shutoff) the starve shutoff register, shown in figure 14-17 , contains the watermark level to be used for exiting the starve state. if the starve state is in effect and the number of valid entries in the fifo becomes greater than or equal to the value in the fifo transmit starve shut off register, the starve condi tion ends. this register is read/write by software. table 14-13. fifo_tx_thr field descriptions bits name description 0?22 ? reserved 23?31 fifo_tx_thr fifo transmit threshold. th ese bits mark the number of entries in the transmit fifo that, if reached, trigger the unloading of frame data into the mac. 0 22 23 31 r00000000000000000000000 fifo_tx_starve w reset 0000_0000_0000_0000_0000_0000_1000_0000 offset tsec1:0x2_4098; tsec2:0x2_5098 figure 14-16. fifo_tx_starve register definition table 14-14. fifo_tx_starve field descriptions bits name description 0?22 ? reserved 23?31 fifo_tx_starve fifo transmit starve. these bits indicate the value to trigger the transmit starve function. it triggers once the number of valid entries in the fi fo is less than or equal to the fifo tx starve. the starve state turns off if the number of valid entries in the fifo becomes greater than or equal to the fifo tx st arve shutoff register. 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-32 freescale semiconductor table 14-15 describes the fields of the fifo transmit starve shutoff register. 14.5.3.3 tsec transmit control and status registers this section describes the control an d status registers that are used sp ecifically for transmitting ethernet frames. all of the registers are 32 bits wide. 14.5.3.3.1 transmit cont rol register (tctrl) tctrl, shown in figure 14-18 , is writable by the user to configure the transmit block. table 14-16 describes the fields of the tctrl register. 0 22 23 31 r00000000000000000000000 fifo_tx_starve_shutoff w reset 0000_0000_0000_0000_0000_0001_0000_0000 offset tsec1:0x2_409c; tsec2:0x2_509c figure 14-17. fifo_tx_starve_shutoff register definition table 14-15. fifo_tx_starve_shutoff field descriptions bits name description 0?22 ? reserved 23?31 fifo_tx_starve_shutoff fifo transmit starve shutof f. indicates the value beyond which to exit the starve state. the starve st ate turns off if the number of valid entries in the fifo becomes greater than or equal to the fifo tx starve shutoff register. 0 1516 192021 26 27 28 29 31 r000000000000000 0 0 00 0 thdf 0 0000 0 rfc_pause tfc_pause 000 w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_4100; tsec2:0x2_5100 figure 14-18. tctrl register definition table 14-16. tctrl field descriptions bits name description 0?19 ? reserved 20 thdf transmit half-duplex flow control. writte n by user. this bit is not self-resetting. 0 disable back pressure. 1 back pressure is applied to media. 21?26 ? reserved 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-33 14.5.3.3.2 transmit stat us register (tstat) tstat, shown in figure 14-19 , is written by tsec to c onvey dma status information. table 14-17 describes the fields of the tstat register. 27 rfc_pause receive flow control pause frame. written by ts ec. this read-only status bit is set if a flow control pause frame was received and the transmitter is paus ed for the duration defined in the received pause frame. this bit automatically clears after the pause duration is complete. 0 pause duration complete. 1 pause duration in progress. 28 tfc_pause transmit flow control pause frame. use this bi t to transmit a pause frame. to transmit a flow control pause frame, first set fifo_pause_ctrl[tfc_pause_en]. next, set maccfg1[gts]. if tfc_pause is then set, the mac st ops transmission of data frames after the current transmission completes. the gtsc interr upt in the ievent register is asserted . with transmission of data frames stopped, the mac transmits a mac control pause frame with the duration value obtained from the ptv register. the txc interrupt occurs after sendi ng the control pause frame. next, the mac clears tfc_pause and resumes transmitting data frames. note that if the transmitter is paused due to user assertion of gts or reception of a pause frame, the mac may still transmit a mac control pause frame. 0 no outstanding pause frame transmission request. 1 pause frame transmission requested. 29?31 ? reserved 01 31 r thlt 0000000000000000000000000000000 w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_4104; tsec2:0x2_5104 figure 14-19. tstat register definition table 14-17. tstat field descriptions bits name description 0 thlt transmit halt 0 no hardware-initiated transmission halt. 1 tsec transmission function halted. this bit is written by tsec to inform the user that it is no longer processing transmit frames and that th e transmit dma function is disabled by hardware. to restart the transmission function, the user must clear this bit by writing a one. 1?31 ? reserved table 14-16. tctrl field descriptions (continued) bits name description 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-34 freescale semiconductor 14.5.3.3.3 txbd data len gth register (tbdlen) tbdlen is a dma register that co ntains the number of bytes remaini ng in the current transmit buffer. figure 14-20 shows the tbdlen register. table 14-18 describes the fields of the tbdlen register. 14.5.3.3.4 transmit interrupt coalesc ing configuration register (txic) txic, shown in figure 14-21 , enables and configures the operational parameters for interrupt coalescing associated with transmitted frames. refer to section 14.6.2.8.1, ?interrupt coalescing,? for a functional description of interrupt coalescing. table 14-18 describes the fields of the txic register. 0151631 r0000000000000000 tbdlen w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_410c; tsec2:0x2_510c figure 14-20. tbdlen register definition table 14-18. tbdlen field descriptions bits name description 0?15 ? reserved 16?31 tbdlen internally written by the dma module. the transmit channel remains active until tbdlen is 0. 0 1 2 3 10 11 15 16 31 r icen 00 icfct 00000 ictt w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_4110; tsec2:0x2_5110 figure 14-21. txic register definition table 14-19. txic field descriptions bits name description 0 icen interrupt coalescing enable 0 interrupt coalescing is disabled. interrupts are raised as they are received if the tsec transmit frame interrupt is enabled (imask[txfen] is set). 1 interrupt coalescing is enabled. if the tsec transmit frame interrupt is enabled (imask[tx fen] is set), an interrupt is raised when the threshold number of frames is reached (defined by txic[icfct]) or when the threshold timer expires (defined by txic[ictt]). 1?2 ? reserved 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-35 14.5.3.3.5 current transmit buffer de scriptor pointer register (ctbptr) ctbptr contains the address of th e transmit buffer descriptor eith er currently being processed, or processed most recently. figure 14-22 shows the ctbptr register. table 14-20 describes the fields of the ctbptr register. 14.5.3.3.6 transmit buffer descrip tor pointer register (tbptr) tbptr, shown in figure 14-23 , contains the low-order 32 bits of the next transmit buffer descriptor address. tbptr takes on the tbas e value when tbase is written by software. although not necessary 3?10 icfct interrupt coalescing frame count threshold. while interrupt coalescing is enabled (txic[icen] is set), this value determines how many frames are transmitted before raising an interrupt 1 . valid values for this field are from 1 to 255. a value of 0 is illegal. if set to 0, an interrupt can only be cleared by first clearing txic[icen] and then clearing th e ievent[txf] bit. note that a value of 1 functionally defeats the advant ages of interrupt coalescing since the frame threshold is reached with each frame transmitted. 11?15 ? reserved 16?31 ictt interrupt coalescing timer threshold. while interrup t coalescing is enabled (txic[icen] is set), this value determines the maximum amount of time after transmitting a frame before raising an interrupt 1 , subject also to imask[txfen]. if frames have been transmitted but the frame count thresh old has not been met, an interrupt is raised when the threshold timer expires. the threshold timer is reset once an interrupt has been asserted. it begins counting once the interrupt is cl eared and ievent[txf] is set. the threshold value is represented in units equal to 64 tsec interface clocks. valid values for this field are from 1 to 65535. a value of 0 is illegal and results in behavior identical to that when interrupt coalescing is disabled (txic[icen] is cleared). 1 interrupts resulting from the interrupt bit (i) of the buffer descriptor in question and enabled subject to the imask register (imask[txfen] is set). 0 28 29 31 r ctbptr 0 0 0 w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_4124; tsec2:0x2_5124 figure 14-22. ctbptr register definition table 14-20. ctbptr field descriptions bits name description 0?28 ctbptr the ctbptr register is internally written by t he dma module. the value of this field increments by one (causing the register value to increment by eight) each time a descriptor is read from memory. 29?31 ? reserved table 14-19. txic field descriptions (continued) bits name description 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-36 freescale semiconductor in most applications, the user can modify this register wh en the transmitter has be en gracefully stopped or halted, as indicated by ieve nt[gtsc] or tstat[thlt]. table 14-21 describes the fields of the tbptr register. 14.5.3.3.7 transmit descriptor b ase address register (tbase) the tbase register, shown in figure 14-24 , is written by the user with th e txbd base address. the value must be divisible by eight for th e 8-byte data buffer descriptors. table 14-22 describes the fields of the tbase register. 14.5.3.3.8 out-of-sequence txbd register (ostbd) the out-of-sequence txbd re gister, ostbd, shown in figure 14-25 , includes the status/control and data length in the same format as a regular txbd. it is useful for sending flow cont rol frames. ostbd[r] is always checked between frames. if it is not ready, a re gular frame is sent. if a fl ow control frame is sent 0 28 29 31 r tbptr 000 w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_41 84; tsec2:0x2_5184 figure 14-23. tbptr register definition table 14-21. tbptr field descriptions bits name description 0?28 tbptr the tbptr register is internally written by th e dma module. the value of this field increments by one (causing the register value to increment by eight) each time a descriptor is read from memory. 29?31 ? reserved 0 28 29 31 r tbase 000 w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_4204; tsec2:0x2_5204 figure 14-24. tbase register definition table 14-22. tbase field descriptions bits name description 0?28 tbase transmit base. tbase defin es the starting location in the memory ma p for the tsec txbds. this field must be 8-byte aligned. together with setting the w (wrap) bit in the last bd, the user can select how many bds to allocate for the transmit packets. the user must in itialize tbase before enabling the tsec transmit function. 29?31 ? reserved 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-37 and ostbd[i] is set, a txc event is generated after frame transmission. this area must be cleared while not in use. once the tsec is in paused mode the out -of-sequence buffer descriptor cannot be used to send another flow control frame because th e mac regards it as a regular txbd. table 14-23 describes the fields of the ostbd register. 0 1 2 3 4 5 6 7 8 9 10 13 14 15 16 31 r r pad/crc w i l tc def to1 hfe/lc rl rc un 0 ostbdlen w reset 0000_1000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_42b0; tsec2:0x2_52b0 figure 14-25. ostbd register definition table 14-23. ostbd field descriptions bits name description 0 r ready. written by tsec and user. 0 the data buffer associated with this bd is not read y for transmission. the user is free to manipulate this bd or its associated data buffer. the tsec clear s this bit after the buffer is transmitted or after an error condition is encountered. 1 the data buffer, which was prepared for transmission by the user, was not transmitted or is currently being transmitted. no fields of this bd may be written by the user once this bit is set. 1 pad/crc padding and crc attachment for short frames. (valid only when maccfg2[pad/crc] is cleared, and maccfg2[crc en] bit is cleared.) if maccfg2[pad/crc] is set, pads are added to all short frames; however, this bit is ignored. 0 do not add pads to short frames unless ostbd[tc] is set. 1 add pads to short frames. pad bytes are inserted until the length of the transmitted frame equals 64 bytes. unlike the mpc8260 which pads up to mi nflr value, tsec always pads up to the ieee minimum frame length of 64 bytes. 2 w wrap. written by user. this bit is ignored by tsec. 3 i interrupt. written by user. 0 no interrupt is generated after this buffer is serviced. 1 ievent[txf] is set after this buff er is serviced. this bit can caus e an interrupt if imask[txfen] is enabled. 4 l last in frame. the ostbd is always the last in the fram e, so l is always set. (hardwired to a value of 1.) 5 tc tx crc. written by user. (valid only while it is set in the first bd and ostbd[pad/crc] is cleared, maccfg2[pad/crc] is cleared, and maccfg2[crc en] is cleared. ) if maccfg2[pad/crc] is set or maccfg2[crc en] is set, a crc is added to all frames and this bit is ignored. 0 end transmission immediately after the last data byte, unless ostbd[pad/crc] is set. 1 transmit the crc sequence after the last data byte. 6 def defer indication. written by tsec. hardware updates this bit after transmitting a frame if used as a ?defer indicator.? software/user updates this bit while building a transmit buffer descriptor if used as a ?hardware event indicator.? 0 this frame was not deferred. 1 this frame did not have a collision before it wa s sent but it was sent late because of deferring. 7 to1 transmit software ownership. this read/write bit may be utilized by software, as necessary. its state does not affect the hardware nor is it affected by the hardware. 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-38 freescale semiconductor 14.5.3.3.9 out-of-sequence tx data bu ffer pointer register (ostbdp) the out-of-sequence tx data buffer pointer regist er (ostbdp), shown in figure 14-26 , contains the data buffer pointer fields in the same fo rmat as a regular txbd, with ostb d, it provides the complete 8-byte descriptor. this area must be cleared while not in use. 8 hfe/lc huge frame enable (written by user)/late collision (written by tsec) huge frame enable. written by user. valid only while it is set in first bd and the maccfg2[huge frame] is cleared. if maccfg2[huge frame] is set, this bit is ignored. 0 truncate transmit frame if its length is great er than the mac?s maximu m frame length register. 1 do not truncate the transmit frame. late collision. written by tsec. 0 no late collision. 1 a collision occurred after 64 bytes are sent. t he tsec terminates the transmission and updates lc. 9 rl retransmission limit. written by tsec. 0 transmission before maximum retry limit is hit. 1 the transmitter failed (max. retry limit + 1) attempts to successfully send a message due to repeated collisions. the tsec terminates the transmission and updates rl. 10?13 rc retry count. written by tsec. 0 the frame is sent correctly the first time. 1 more than zero attempts were needed to send the transmit frame. if this field is 15, 15 or more retries were needed. the ethernet controller updates rc after sending the buffer. 14 un underrun. written by tsec. 0 no underrun encountered (data was retrieved from external memory in time to send a complete frame). 1 the ethernet controller encountered a transmitter underrun condition while sending the associated buffer. the tsec terminates the transmission and updates un. 15 ? reserved 16?31 ostbdlen out-of-sequence txbd data length. written by user. data length is the nu mber of octets the tsec transmits from this bd?s data buffer. it is never mo dified by the tsec. this field must be greater than zero in order for a transfer to take place. 0 31 r ostbdp w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_42b 4; tsec2:0x2_52b4 figure 14-26. ostbdp register definition table 14-23. ostbd field descriptions (continued) bits name description 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-39 table 14-24 describes ostbdp. 14.5.3.4 tsec receive control and status registers this section describes the control an d status registers that are used sp ecifically for receiving ethernet frames. all of the registers are 32 bits wide. 14.5.3.4.1 receive contro l register (rctrl) rctrl, shown in figure 14-27 , controls the operational m ode of the receive block. it must be written only after a system reset (at initializati on) or if dmactrl[grs] is cleared. table 14-25 describes the fields of the rctrl register. table 14-24. ostbdp field descriptions bits name description 0?31 ostdbp out-of-sequence tx data buffer pointer. written by user. the transmit data buffer pointer contains the address of the associated data buffer. there are no alignment requirements for this address. 0 26 27 28 29 30 31 r000000000000000 0 0 000000000 0 bc_rej prom rsf 00 w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_4300; tsec2:0x2_5300 figure 14-27. rctrl register definition table 14-25. rctrl field descriptions bits name description 0?26 ? reserved 27 bc_rej broadcast frame reject. if this bit is set, fr ames with da (destination address) = ffff_ffff_ffff are rejected unless rctrl[prom] is set. if both bc_rej and rctrl[prom] are set, then frames with broadcast da are accepted and the m (miss) bit is set in the receive bd. 0 broadcast frame reject is disabled. 1 broadcast frame reject is enabled. 28 prom promiscuous mode. when set, all frames except pause frames are accepted. 0 promiscuous mode is disabled. 1 promiscuous mode is enabled. 29 rsf receive short frame mode. when set, enables the reception of frames shorter than minflr bytes. note that in order for short frames to be received when rsf is set, a da hit must occur. when rsf is cleared, all frames shorter than minflr are automatically rejected. 0 receive short frame mode is disabled. 1 receive short frame mode is enabled. 30?31 ? reserved 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-40 freescale semiconductor 14.5.3.4.2 receive stat us register (rstat) tsec writes to rstat, shown in figure 14-28 , under the following conditions: ? the receiver runs out of descriptors ? the receiver was halted becau se an error condition was encount ered while receiving a frame software must clear the qhlt bit to take th e tsec receiver function out of a halt state. table 14-26 describes the fields of the rstat register. 14.5.3.4.3 rxbd data le ngth register (rbdlen) rbdlen is a dma register that contains the number of bytes remaining in the current receive buffer. figure 14-29 shows the rbdlen register. 01 7 8 9 31 r0 0000000 qhlt 00000000000000000000000 w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_4304; tsec2:0x2_5304 figure 14-28. rstat register definition table 14-26. rstat field descriptions bits name description 0?7 ? reserved 8 qhlt rxbd queue is halted. when ievent[bsy] or ieven t[eberr] is set during reception of a packet, rstat[qhlt] is also set. in order to begin receiving packets again, the user must clear rstat[qhlt]. this bit is set whenever the tsec reads an rxbd with it s empty field cleared or encounters a system bus error while processing an rx packet. it is a hardware-initiate d stop indication (dma_ctrl[grs] being set by the user does not cause this bit to be set.). the current frame and all other frames directed to the halted queue are discarded. a write with a value of 1 re-enables the queue for receiving. 0 rxbd queue is enabled for ethernet rec eption. (that is, it is not halted.) 1 all ethernet controller receive activity to rxbd queue is halted. 9?31 ? reserved 0151631 r0000000000000000 rbdlen w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_430c; tsec2:0x2_530c figure 14-29. rbdlen register definition 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-41 table 14-27 describes the fields of the rbdlen register. 14.5.3.4.4 receive interr upt coalescing configurat ion register (rxic) the rxic register enables and conf igures the operational parameters fo r interrupt coalescing associated with received frames. refer to section 14.6.2.8.1, ?interrupt coalescing,? for a functional description of interrupt coalescing as additional detail s regarding the use of this register. figure 14-30 shows the rxic register. table 14-18 describes the fields of the rxic register. table 14-27. rbdlen field descriptions bits name description 0?15 ? reserved 16?31 rbdlen the rbdlen is internally written by the dma mo dule. if rbdlen is cleared, all activity in the receive channel stops. 0 1 2 3 10 11 15 16 31 r icen 00 icfct 0 000 0 ictt w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_4310; tsec2:0x2_5310 figure 14-30. rxic re gister definition table 14-28. rxic field descriptions bits name description 0 icen interrupt coalescing enable 0 interrupt coalescing is disabled. interrupts are raised as they are received if the tsec receive frame interrupt is enabled (imask[rxfen] is set). 1 interrupt coalescing is enabled. if the tsec receiv e frame interrupt is enabled (imask[rxfen] is set), an interrupt is raised when the threshold number of fram es is reached (defined by rxic[icfct]) or when the threshold timer expires (defined by rxic[ictt]). 1?2 ? reserved 3?10 icfct interrupt coalescing frame count threshold. while interrupt coalescing is enabled (rxic[icen] is set), this value determines how many frames are received before raising an interrupt 1 . valid values for this field are from 1 to 255. a value of 0 is illegal. if set to 0, an interrupt can only be cleared by first clearing rxic[icen] and then clearing th e ievent[rxf] bit. note that a value of 1 functionally defeats the advant ages of interrupt coalescing since the frame threshold is reached with each frame received. 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-42 freescale semiconductor 14.5.3.4.5 current receive buffer d escriptor pointer register (crbptr) crbptr contains the address of the receive buffer descriptor either curren tly being processed, or processed most recently. figure 14-31 shows the crbptr register. table 14-29 describes the fields of the crbptr register. \ 14.5.3.4.6 maximum receive buff er length register (mrblr) the mrbl register is written by the user. it inform s the tsec how much space is in the receive buffer pointed to by the rxbd. figure 14-32 shows the mrblr. 11?15 ? reserved 16?31 ictt interrupt coalescing timer threshold. while interrup t coalescing is enabled (rxic[icen] is set), this value determines the maximum amount of time after receiving a frame before raising an interrupt 1 , subject also to imask[rxfen]. if frames have been received but the fr ame count threshold has not been met, an interrupt is raised when the threshold timer expires. the threshold timer is reset once an interrupt has been asserted. it begins counting once t he interrupt is cleared and ievent[rxf] is set. the threshold va lue is represented in units equal to 64 tsec interface clocks. valid values for this field are from 1 to 65535. a value of 0 is illegal and results in behavior identical to that when inte rrupt coalescing is disabled (rxic[icen] is cleared). 1 interrupts resulting from the interrupt bit (i) of the buffer descriptor in question and enabled subject to the imask register (imask[rxfen] is set). 0 28 29 31 r crbptr 0 0 0 w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_4324; tsec2:0x2_5324 figure 14-31. crbptr register definition table 14-29. crbptr field descriptions bits name description 0?28 crbptr the crbptr register is internally written by t he dma module. the value of this field increments by one (causing the register value to increment by eight) each time a descriptor is read from memory. 29?31 ? reserved 0 1516 2526 31 r0000000000000000 mrbl 000000 w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_4340; tsec2:0x2_5340 figure 14-32. mrbl register definition table 14-28. rxic field descriptions (continued) bits name description 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-43 table 14-30 describes the fields of the mrbl register. \\ 14.5.3.4.7 receive buffer descrip tor pointer register (rbptr) rbptr contains the receive buffer descriptor address. figure 14-33 shows the rbptr register. this register takes on the value of rbase when the rb ase register is writte n by software. although not necessary in most applicati ons, the user can modify this register when the transm itter has been gracefully stopped or halted, as indicated by tstat[thlt]. table 14-31 describes the fields of the rbptr register. table 14-30. mrblr field descriptions bits name description 0?15 ? to ensure that mrbl is a multiple of 64, these bits are reserved and must be cleared. 16?25 mrbl maximum receive buffer length. mrbl is the number of bytes that the tsec receiver writes to the receive buffer. the mrbl register is written by the user with a multiple of 64 for all modes. tsec can write fewer bytes to the buffer than the value set in mrbl if a condition such as an error or end-of-frame occurs, but it never exceeds the mrbl value; therefore, user-suppl ied buffers must be at least as large as the mrbl. 26?31 ? to ensure that mrbl is a multiple of 64, these bits are reserved and must be cleared. 0 28 29 31 r rbptr 000 w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_4384; tsec2:0x2_5384 figure 14-33. rbptr register definition table 14-31. rbptr field descriptions bits name description 0?28 rbptr the rbptr register is internally written by th e dma module. the value of this field increments by one (causing the register value to increment by eight) each time a descriptor is read from memory. 29?31 ? reserved 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-44 freescale semiconductor 14.5.3.4.8 receive descriptor base address register (rbase) the rbase register is written by the user with the rxbd base address and must be divisible by eight for the 8-byte buffer descriptors. figure 14-34 shows the rbase register. table 14-32 describes the fields of the rbase register. \ 14.5.3.5 mac functionality this section describes the mac regi sters and provides a brief overview of the functionality that can be exercised through the use of these re gisters, particularly those that pr ovide functionality not explicitly required by the ieee 802.3 standard. all of the mac registers are 32 bits wide. 14.5.3.5.1 configuring the mac mac configuration registers 1 a nd 2 provide a way to configur e the mac in multiple ways: ? adjusting the preamble length?the length of the preamble can be adjusted from the nominal seven bytes to some other (non-zero) value. ? varying pad/crc combinations?t hree pad/crc combinations ar e provided to handle a variety of system requirements. the most simple are frames that already have a valid fcs field. in this case, the crc is checked and reported through the tr ansmit statistics vector (tsv[51:0]). the other two options include appending a valid crc, or padding and then appending a valid crc, resulting in a minimum frame of 64 octets. in addition to the programmable register set, the pad/crc behavior can be dynamically adjusted on a per-packet basis. 14.5.3.5.2 controlling csma/cd the half-duplex register (hafdu p) allows control over the carri er-sense multiple access/collision detection (csma/cd) logic of th e tsec. half-duplex is only supported for 10 mbps and 100 mbps operation. following the comple tion of the packet transmission the part begins timing the inter packet gap (ipg) as programmed in the back-to- back ipg configuration register. th e system is now free to begin another frame transfer. 0 28 29 31 r rbase 000 w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_4404; tsec2:0x2_5404 figure 14-34. rbase register definition table 14-32. rbase field descriptions bits name description 0?28 rbase receive base. rbase defines the starting location in the memory map for the tsec rxbd. 29?31 ? reserved. these bits must be set to zero, to cause the value of rbase to be a multiple of eight. 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-45 in full-duplex mode both the carrier sense (crs) and collision (col) indica tions from the phy are ignored, but in half-duplex mode th e tsec defers to crs and, followi ng a carrier event, times the ipg using the non-back-to-back ipg configuration values that include support for the optional two-thirds/one-third crs deferral pr ocess. this optional ipg mechanis m enhances system robustness and ensures fair access to the medium. duri ng the first two-thirds of the ipg, the ipg timer is cleared if crs is sensed. during the final one-third of the ipg, cr s is ignored and the transm ission begins once ipg is timed. the two-thirds/one-third ra tio is the recommended value. 14.5.3.5.3 handling packet collisions while transmitting a packet in half-duplex mode, the ts ec is sensitive to col. if a collision occurs, it aborts the packet and outputs the 32- bit jam sequence. the jam sequence is comprised of several bits of the crc, inverted to guarantee an invalid crc upon re ception. a signal is sent to the system indicating that a collision occurred and that the start of the fr ame is needed for retransm ission. the tsec then backs off of the medium for a time determined by the tr uncated binary exponential back-off (beb) algorithm. following this back-off time, the packet is retried. th e back-off time can be sk ipped if configured through the half-duplex register. however, this is non-standa rd behavior and its use mu st be carefully applied. should any one packet experience exce ssive collisions, the packet is aborted. the system must flush the frame and move to the next one in li ne. if the system requests to send a packet while the tsec is deferring to a carrier, the tsec simply wait s until the end of the carrier event and the timing of ip g before it honors the request. if packet transmission attempts e xperience collisions, the tsec output s the jam sequence and waits some amount of time before retrying the packet. this amount of time is determined by a controlled randomization process called truncated binary exponential back-off . the amount of time is an integer number of slot times. the number of slot times to delay before the n th retransmission attempt is chosen as a uniformly-distributed random integer r in the range: 0 r 2 k , where k = min( n ,10). so, after the first collision, tsec backs-off either 0 or 1 slot time s. after the fifth collision, tsec backs-off between 0 and 32 slot times. after the te nth collision, the maximum number of slot times to back-off is 1024. this can be adjusted through the hal f-duplex register. an altern ate truncation point, such as 7 for instance, can be programmed. on average, the mac is more aggres sive after seven collisions than other stations on the network. 14.5.3.5.4 controlling packet flow packet flow can be dealt with in a number of ways within tsec. a default retransm it attempt limit of 15 can be reduced using the half-duplex register. the slot time or collision window can be used to gate the retry window and possibly reduce the amount of transm it buffering within the system. the slot time for 10/100 mbps is 512 bit times. because the slot time begins at the begi nning of the packet, the end occurs around the 56th byte of the frame data. slot time in 1-gbps mode is not supported. full-duplex flow control is provided for in ieee 802.3x. currently the standard does not address flow control in half-duplex environments . common in the industry, however, is the concept of back pressure. the tsec implements the optional back pressure me chanism using the raise carrier method. if the system receive logic wishes to st op the reception of p ackets in a network-friendly way, transmit half -duplex flow 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-46 freescale semiconductor control (thdf) is set (tctrl[thdf]) . if the medium is idle, the ts ec raises carrier by transmitting preamble. other stations on the half-duplex network th en defer to the carrier. in the event the preamble transmission happens to cause a collision, tsec ensures the minimum 96-bit presence on the wire, then drops preamble and wait s a back-off time depending on the value of the configuration bit, back pressure no back-off (hal f-duplex) [bpnb]. these tran smitting-preamble-for-back pressure collisions are not counted. if bpnb is set, the tsec waits an inter-packet gap before resuming the transmission of preamble following the collision a nd does not defer. if cleared, the tsec adheres to the truncated beb algorithm that allows the possibilit y of packets being received. this also can be detrimental in that packets can no w experience excessive collisions, causing them to be dropped in the stations from which they originate. to reduce the likelihood of lost packets and packets leaking through the back pressure mechanism, bpnb must be set. the tsec drops carrier (cease transm itting preamble) pe riodically to avoid excessi ve defer conditions in other stations on the shared networ k. if, while applying back pressure, the tsec is requested to send a packet, it stops sending preamble, and waits one ip g before sending the packet. bpnb applies for any collision that occurs during the sending of this packet. tsec does not defer while attempting to send packets while in back pressure. again, back pressure is non-standard, yet it can be effective in reducing the flow of receive packets. 14.5.3.5.5 controlling phy links control and status to and from the phy is provi ded through the two-wire mii management interface described in ieee 802.3u. the mii management regi sters (mii management configuration, command, address, control, status, a nd indicator registers) are used to exerci se this interface between a host processor and one or more phy devices (including the tbi). ex ternal phys may only be configured using the mii management interface of tsec1 si nce the interface signals (ec_mdc and ec_mdio) are only driven by tsec1. the tsec mii?s registers provide the ability to perfor m continuous read cycles, called a scan cycle. if requested (by setting miimcom[scan cy cle]), the part performs repetitive read cycles of the phy status register, for example. in this way, link characteristics may be monito red more efficiently. the different fields in the mii management indicator register (scan, no t valid and busy) are used to indicate availability of each read of the scan cycle to the host from miimstat[phy status]. yet another parameter that can be m odified through the mii re gisters is the length of the mii management interface preamble. after establishing that a ph y supports preamble suppr ession, the host may so configure the tsec. while enabled, the length of mii management frames are reduc ed from 64 clocks to 32 clocks. this effectively doubles the efficiency of the interface. 14.5.3.6 mac registers the mac registers are describe d in the following sections. 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-47 14.5.3.6.1 mac configurati on register 1 (maccfg1) the maccfg1 register is written by the user. figure 14-35 shows the maccfg1 register. table 14-33 describes the fields of the maccfg1 register. \ 012 11 12 131415 r soft_reset 0 0000 0 0 0 0 0 0 reset rx mc reset tx mc reset rx fun reset tx fun w reset 0000_0000_0000_0000 16 22 23 24 25 26 27 28 29 30 31 r 0 00000 0 loopback 00 rx_flow tx_flow sync?d rx en rx_en sync?d tx en tx_en w reset 0000_0000_0000_0000 offset tsec1:0x2_4500; tsec2:0x2_5500 figure 14-35. maccfg1 register definition table 14-33. maccfg1 field descriptions bits name description 0 soft_reset soft reset. this bit is cleared by default. see section 14.6.2.2, ?soft reset and reconfiguring procedure,? for more information on setting this bit. 0 normal operation. 1 place all modules within the mac in reset. 1?11 ? reserved 12 reset rx mc reset receive mac control block. this bit is cleared by default. 0 normal operation. 1 place the receive mac control block in reset. th is block detects control frames and contains the pause timers. 13 reset tx mc reset transmit mac control bl ock. this bit is cleared by default. 0 normal operation. 1 place the petmc transmit mac control block in reset. this block multiplexes data and control frame transfers. it also responds to xoff pause control frames. 14 reset rx fun reset receive function block. this bit is cleared by default. 0 normal operation. 1 place the receive function block in reset. th is block performs the receive frame protocol. 15 reset tx fun reset transmit function bl ock. this bit is cleared by default. 0 normal operation. 1 place the transmit function block in reset. this block performs the frame transmission protocol. 16?22 ? reserved 23 loopback loopback. this bit is cleared by default. 0 normal operation. 1 loopback the mac transmit outputs to the mac receive inputs. 24?25 ? reserved 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-48 freescale semiconductor 14.5.3.6.2 mac configurati on register 2 (maccfg2) the maccfg2 register is written by the user. figure 14-36 shows the maccfg2 register. table 14-34 describes the fields of the maccfg2 register. 26 rx_flow receive flow. this bit is cleared by default. 0 the receive mac control ignores pause flow control frames. 1 the receive mac control detects and acts on pause flow control frames. 27 tx_flow transmit flow. this bit is cleared by default. 0 the transmit mac control may not send pause fl ow control frames if requested by the system. 1 the transmit mac control may send pause flow control frames if requested by the system. 28 sync?d rx en receive enable synchronized to the receive stream (read-only) 0 frame reception is not enabled. 1 frame reception is enabled. 29 rx_en receive enable. this bit is cleared by default. if set, prior to clearing this bit, set dmactrl[grs] then confirm subsequent occurrence of the graceful receive stop interrupt (ievent[grsc] is set). 0 the mac may not receive frames from the phy. 1 the mac may receive frames from the phy. 30 sync?d tx en transmit enable synchronized to the transmit stream (read-only) 0 frame transmission is not enabled. 1 frame transmission is enabled. 31 tx_en transmit enable. this bit is cleared by default. if set, prior to clearing this bit, set dmactrl[gts] then confirm subsequent occurrence of the graceful transmit stop interrupt (ievent[gtsc] is set). 0 the mac may not transmit frames from the system. 1 the mac may transmit frames from the system. 0 15 16 19 202122 232425 26 27 28 29 30 31 r000000000000000 0 preamble length 00 i/f mode 00 huge frame length check 0 pa d / crc crc en full duplex w reset 0000_0000_0000_0000_0111_0000_0000_0000 offset tsec1:0x2_4504; tsec2:0x2_5504 figure 14-36. maccfg2 register definition table 14-34. maccfg2 field descriptions bits name description 0?15 ? reserved 16?19 preamble length determines the length in bytes of the preamble fiel d of the packet. its default is 0x7. a preamble length of 0 is not supported. 20?21 ? reserved table 14-33. maccfg1 field descriptions (continued) bits name description 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-49 14.5.3.6.3 inter-packet gap/inte r-frame gap register (ipgifg) the ipgifg register is written by the user. figure 14-37 shows the ipgifg register. 22?23 i/f mode determines the type of interface to which the mac is connected. its default is 00. 00 reserved 01 nibble mode (mii) 10 byte mode (gmii/tbi) 11 reserved 24?25 ? reserved 26 huge frame huge frame enable. cleared by default. 0 limit the length of frames to the maximum frame length value. 1 frames longer than the maximum frame le ngth may be transmitted and received. 27 length check length check. this bit is cleared by default. 0 no length field checking is performed. 1 the mac checks the frame?s length field to ens ure it matches the actual data field length. 28 ? reserved 29 pad/crc pad and append crc. this bit is cleared by default. 0 frames presented to the mac have a valid length and contain a crc. 1 the mac pads all transmitted short frames and appends a crc to every frame regardless of padding requirement. 30 crc en crc enable. if the configuration bit pad/crc or the per-packet pad/crc bit is set, crc en is ignored. this bit is cleared by default. 0 frames presented to the mac have a valid length and contain a valid crc. 1 the mac appends a crc on all frames. clear this bit if frames presented to the mac have a valid length and contain a valid crc. 31 full duplex full duplex configure. this bit is cleared by default. 0 the mac to operate in half-duplex mode only. 1 the mac operates in full-duplex mode. 0 1 7 8 9 1516 232425 31 r 0 non-back-to-back inter-packet-gap, part 1 0 non-back-to-back inter-packet-gap, part 2 minimum ifg enforcement 0 back-to-back inter-packet-gap w reset 0100_0000_0110_0000_0101_0000_0110_0000 offset tsec1:0x2_4508; tsec2:0x2_5508 figure 14-37. ipgifg register definition table 14-34. maccfg2 field descriptions (continued) bits name description 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-50 freescale semiconductor table 14-35 describes the fields of the ipgifg register. 14.5.3.6.4 half-duplex register (hafdup) the hafdup register is written by the user. figure 14-38 shows the hafdup register. table 14-35. ipgifg field descriptions bits name description 0?reserved 1?7 non-back-to-back inter-packet-gap, part 1 programmable field representing the optiona l carrier sense windo w referenced in ieee 802.3/4.2.3.2.1 ?carrier deference?. if carrier is detected during the ti ming of ipgr1, the mac defers to carrier. if, however, carrier becomes active after ipgr1, th e mac continues timing ipgr2 and transmits, knowingly causing a collision; thus, ensuring fair access to medium. its range of values is 0x00 to ipgr2. its default is 0x40 (64d) which follows the two-thirds/one-third guideline. 8?reserved 9?15 non-back-to-back inter-packet-gap, part 2 programmable field representing the non-back-to-back inter-packet-gap in bits. its default is 0x60 (96d), which represents the minimum ipg of 96 bits. 16?23 minimum ifg enforcement programmable field representing the minimum number of bits of ifg to enforce between frames. a frame is dropped whose ifg is less than that programmed. the default setting of 0x50 (80d) represents half of the nominal minimum ifg which is 160 bits. 24 ? reserved 25?31 back-to-back inter-packet-gap programmable field representing the ipg between back-to-back packets. this is the ipg parameter used exclusively in full-duplex mode and in half-duplex mode if two transmit packets are sent back-to-back. set this field to the number of bits of ipg desired. the default setting of 0x60 (96d) represents the minimum ipg of 96 bits. 0781112131415 r0 0000000 alternate beb truncation alt beb bp no backoff no backoff excess defer w reset 0000_0000_1010_0001 16 19 20 25 26 31 r retransmission maximum 00 0 0 0 0 collision window w reset 1111_0000_0011_0111 offset tsec1:0x2_450c; tsec2:0x2_550c figure 14-38. half-duplex register definition 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-51 table 14-36 describes the fields of the hafdup register. 14.5.3.6.5 maximum frame length register (maxfrm) the maxfrm register is written by the user. figure 14-39 shows the maxfrm register. table 14-36. hafdup field descriptions bits name description 0?7 ? reserved 8?11 alternate beb truncation this field is used while alternate binary exponential back-off enable is set. the value programmed is substituted for the ethernet standar d value of ten. its default is 0xa. 12 alt beb alternate binary exponential back-off. this bit is cleared by default. 0 the tx mac follows the standard binary exponential back-off rule. 1 the tx mac uses the alternate binary exponential back-off truncation setting instead of the 802.3 standard tenth collision. the standard specifies that any collision after the tenth uses one less than 210 as the maximum back-off time. 13 bp no backoff back pressure no back-off. this bit is cleared by default. 0 the tx mac follows the binary exponential back-off rule. 1 the tx mac immediately re-transmits, following a collision, during back pressure operation. 14 no backoff no back-off. this bit is cleared by default. 0 the tx mac follows the binary exponential back-off rule. 1 the tx mac immediately re-transmits following a collision. 15 excess defer excessively deferred. this bit is set by default. 0 the tx mac aborts the transmission of a packet that is excessively deferred. 1 the tx mac allows the transmission of a packet that is excessively deferred. 16?19 retransmission maximum this is a programmable field specifying the number of retransmission attempts following a collision before aborting the packet due to excessive collisions. the standard specifies the attempt limit to be 0xf (15d). its default value is 0xf. 20?25 ? reserved 26?31 collision window this is a programmable field representing the slot time or collision window during which collisions occur in properly configured networks. because the collision window starts at the beginning of transmission, the preamble and sfd are included. its default of 0x37 (55d) corresponds to the count of frame bytes at the end of the window. 0151631 r0000000000000000 maximum frame w reset 0000_0000_0000_0000_0000_0110_0000_0000 offset tsec1:0x2_4510; tsec2:0x2_5510 figure 14-39. maximum frame length register definition 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-52 freescale semiconductor table 14-37 describes the fields of the maxfrm register. 14.5.3.6.6 mii management conf iguration regist er (miimcfg) the miimcfg register is written by the user. figure 14-40 shows the miimcfg register. table 14-38 describes the fields of the miimcfg register. table 14-37. maxfrm field descriptions bits name description 0?15 ? reserved 16?31 maximum frame by default this field is set to 0x0600 (1536d). it sets the maximum frame size in both the transmit and receive directions. (refer to maccfg2[huge frame].) 01 26 27 28 29 31 r reset mgmt 00000000000000000000000000 no pre 0mgmt clock select w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_4520; tsec2:0x2_5520 figure 14-40. mii management conf iguration register definition table 14-38. miimcfg field descriptions bits name description 0 reset mgmt reset management. this bit is cleared by default. 0 allow the mii mgmt to perform management read/write cycles if requested. 1 reset the mii mgmt. 1?26 ? reserved 27 no pre preamble suppress. this bit is cleared by default. 0 the mii mgmt performs management read/write cycles with 32 clocks of preamble. 1 the mii mgmt suppresses preamble generation and reduces the management cycle from 64 clocks to 32 clocks. this is in acco rdance with ieee 802.3/22. 2.4.4.2. 28 ? reserved 29?31 mgmt clock select this field determines the clock frequency of the mg mt clock (ec_mdc). its default value is 000. the source clock frequency is equal to the core complex bus clock divided first by eight and then further divided by the following value: 000 source clock divided by 4 001 source clock divided by 4 010 source clock divided by 6 011 source clock divided by 8 100 source clock divided by 10 101 source clock divided by 14 110 source clock divided by 20 111 source clock divided by 28 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-53 14.5.3.6.7 mii management co mmand register (miimcom) the miimcom register is written by the user. figure 14-41 shows the miimcom register. table 14-39 describes the fields of the miimcom register. 14.5.3.6.8 mii management address register (miimadd) the miimadd register is written by the user. figure 14-42 shows the miimadd register. 0 29 30 31 r0 00000000000000000000000000000 scan cycle read cycle w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_4524; tsec2:0x2_5524 figure 14-41. miimcom register definition table 14-39. miimcom field descriptions bits name description 0?29 ? reserved 30 scan cycle scan cycle. this bit is cleared by default. 0 normal operation. 1 the mii management continuously performs read cycles. this is useful for polling a phy register, for example, monitoring link fails. data is returned in register miimstat[phy status]. ievent[mmrd] is set once a read has been completed. 31 read cycle read cycle. this bit is cleared by default but is not self-clearing once set. 0 normal operation. 1 the mii management performs a si ngle read cycle upon the transition of this bit from 0 to 1 using the phy address (at miimadd[phy address]) and the register address (at miimadd[register address]). the 0 to 1 transition of this bit also ca uses the miimind[busy] bit to be set. the read is complete when the miimind[busy] bit clears. data is returned in register miimstat[phy status]. ievent[mmrd] is also set once the read has been completed. 0 18 19 23 24 26 27 31 r0000000000000000000 phy address 000 register address w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_4528; tsec2:0x2_5528 figure 14-42. miimadd register definition 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-54 freescale semiconductor table 14-40 describes the fields of the miimadd register. 14.5.3.6.9 mii management c ontrol register (miimcon) the miimcon register is written by the user. figure 14-43 shows the miimcon register. table 14-41 describes the fields of the miimcon register. table 14-40. miimadd field descriptions bits name description 0?18 ? reserved 19?23 phy address this field represents the 5-bit phy addr ess field of management cycles. up to 31 phys can be addressed. at least one phy address is reserved for the tbi phy address as programmed in the tbipa register ( section 14.5.3.1.8, ?t bi physical address register (tbipa),? figure 14-13 ). the default of the tbi phy address is 0x00. the user mu st be sure to assign a physical address to the tbi so as to not conflict with the external phy physical address as discussed in the register initialization steps in section 14.7, ?initializatio n/application information.? 24?26 ? reserved 27?31 register address this field represents the 5-bit regi ster address field of management cycles. up to 32 registers can be accessed. its default value is 0x00. 0151631 r0000000000000000 phy control w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_452c; tsec2:0x2_552c figure 14-43. mii management control register definition table 14-41. miimcon field descriptions bits name description 0?15 ? reserved 16?31 phy control if written, an mii mgmt write cycle is performed usin g this 16-bit data, the pre-configured phy address (at miimadd[phy address]) and the register address (at miimadd[register address]). its default value is 0x0000. ievent[mmwr] is set onc e the write has been completed. 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-55 14.5.3.6.10 mii management status register (miimstat) the miimstat, shown in figure 14-44 , is read-only by the user. table 14-42 describes the fields of the miimstat register. 14.5.3.6.11 mii management i ndicator regist er (miimind) the miimind register is read-only by the user. figure 14-45 shows the miimind register. table 14-43 describes the fields of the miimind register. 0151631 r0000000000000000 phy status w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_4530; tsec2:0x2_5530 figure 14-44. miimstat register definition table 14-42. miimstat field descriptions bits name description 0?15 ? reserved 16?31 phy status following an mii mgmt read cycle, the 16-bit data can be read from this location. its default value is 0x0000. 0 28 29 30 31 r0 000000000000000000000000000 0not validscanbusy w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_4534; tsec2:0x2_5534 figure 14-45. mii management indicator register definition table 14-43. miimind field descriptions bits name description 0?28 ? reserved 29 not valid not valid 0 mii mgmt read cycle has completed and the read data is valid. 1 mii mgmt read cycle has not completed and the read data is not yet valid. 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-56 freescale semiconductor 14.5.3.6.12 interface stat us register (ifstat) the ifstat register is written by the user. figure 14-46 shows the ifstat register. table 14-44 describes the fields of the ifstat register. 14.5.3.6.13 station address r egister part 1 (macstnaddr1) the macstnaddr1 register is written by the user. figure 14-47 shows the macstnaddr1 register. the value of the station address written by th e user into macstnaddr1 and macstnaddr2 is byte-reversed from how it would appear in the da fi eld of a frame in memory. for example, for a station address of 0x12345678abcd, perform a write to macstnaddr1 of 0xcdab7856, and to macstnaddr2 of 0x34120000. when the user read s macstnaddr1, 0xcdab 7856 is returned. a read of macstnaddr2 returns a value of 0x34120000. no te, the i/g and u/l bits of the frame?s da field is located at the lsbs of th e 1st octet stored in macstnaddr2, where the i/g bit is bit 15, and the u/l bit is bit 14. 30 scan scan in progress 0 a scan operation (continuous mii mgmt read cycles) is not in progress. 1 a scan operation (continuous mii mgmt read cycles) is in progress. 31 busy busy 0 mii mgmt block is not currently perfo rming an mii mgmt read or write cycle. 1 mii mgmt block is currently performing an mii mgmt read or write cycle. ievent[mmrd] or ievent[mmwr] is set once the read or wr ite, respectively, has been completed. 0 21 22 23 31 r000000000000000000000 0 excess defer 0 0000000 0 w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_453c; tsec2:0x2_553c figure 14-46. interface status register definition table 14-44. ifstat field descriptions bits name description 0?21 ? reserved 22 excess defer excessive transmission defer. this bit latches high and is cleared when read. this bit is cleared by default. 0 normal operation. 1 the mac excessively defers a transmission. 23?31 ? reserved table 14-43. miimind field descriptions (continued) bits name description 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-57 table 14-45 describes the fields of the macstnaddr1 register. 14.5.3.6.14 station address r egister part 2 (macstnaddr2) the macstnaddr2 register is written by the user. figure 14-48 shows the macstnaddr2 register. note, the i/g and u/l bits of the frame?s da field is located at the lsbs of the 1st octet stored in macstnaddr2, where the i/g bit is bit 15, and the u/l bit is bit 14. table 14-46 describes the fields of the macstnaddr2 register. 0781516232431 r station address, 6th octet station address, 5th octet s tation address, 4th octet station address, 3rd octet w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_4540; tsec2:0x2_5540 figure 14-47. station address part 1 register definition table 14-45. macstnaddr1 field descriptions bits name description 0?7 station address, 6th octet this field holds the sixth octet of the station addre ss. the sixth octet (station address bits 40?47) defaults to a value of 0x00. 8?15 station address, 5th octet this field holds the fifth octet of the station addr ess. the fifth octet (station address bits 32?39) defaults to a value of 0x00. 16?23 station address, 4th octet this field holds the fourth octet of the station add ress. the fourth octet (station address bits 24?31) defaults to a value of 0x00. 24?31 station address, 3rd octet this field holds the third octet of the station ad dress. the third octet (station address bits 16?23) defaults to a value of 0x00. 0781516 31 r station address, 2nd octet station address, 1st octet 0000000000000000 w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_4544; tsec2:0x2_5544 figure 14-48. station address part 2 register definition table 14-46. macstnaddr2 field descriptions bits name description 0?7 station address, 2nd octet this field holds the second octet of the station addr ess. the second octet (station address bits 8?15) defaults to a value of 0x00. 8?15 station address, 1st octet this field holds the first octet of the station addres s. the first octet (station address bits 0?7) defaults to a value of 0x00. 16?31 ? reserved 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-58 freescale semiconductor 14.5.3.7 mib registers this section describe s the mib registers. the tsec mstat module has 37 sepa rate statistics counters, which simply count or accumulate statistical events that occur as packets are transmitte d and received. these c ounters support rmon mib group 1, rmon mib group 2, rm on mib group 3, rmon mib group 9, rmon mib 2, and the 802.3 ethernet mib. the detection of one or more of these statistical events triggers the mstat module to upda te its statistics counters. these counters are stored in internal data registers. the user may access the internal data registers at any time. an interru pt can be generated upon any one c ounter?s rollover condition through a carry interrupt output from the mstat. each counter?s rollover condi tion can be discreetly masked from causing an interrupt by internal mask ing registers. in additi on, each indivi dual counter value may be reset on read access, or all counters may be simultaneously reset by assertion of an external module input signal. figure 14-49 shows the tr64 register. 14.5.3.7.1 transmit and receive 64-byte frame counter register (tr64) table 14-47 describes the fields of the tr64 register. 14.5.3.7.2 transmit and receive 65- to 127-byte frame c ounter register (tr127) figure 14-50 shows the tr127 register. 0910 31 r0000000000 tr64 w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_4680; tsec2:0x2_5680 figure 14-49. transmit and receive 64-byte frame register definition table 14-47. tr64 field descriptions bits name description 0?9 ? reserved 10?31 tr64 transmit and receive 64-byte frame counter?increment for each good or bad frame transmitted and received which is 64 bytes in length, inclusive (excluding preamble and sfd but including fcs bytes) 0910 31 r0 000000000 tr127 w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_4684; tsec2:0x2_5684 figure 14-50. transmit and receive 65- to 127-byte frame register definition 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-59 table 14-48 describes the fields of the tr127 register. 14.5.3.7.3 transmit and receive 128- to 255-byte frame c ounter register (tr255) figure 14-51 shows the tr255 register. table 14-49 describes the fields of the tr255 register. 14.5.3.7.4 transmit and receive 256- to 511-byte frame c ounter register (tr511) figure 14-52 shows the tr511 register. table 14-48. tr127 field descriptions bits name description 0?9 ? reserved 10?31 tr127 transmit and receive 65- to 127-byte frame count er?increment for each good or bad frame transmitted and received which is 65 to 127 bytes in length, inclusive (excluding preamble and sfd but including fcs bytes) 0910 31 r0 000000000 tr255 w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_4688; tsec2:0x2_5688 figure 14-51. transmit and receive 128- to 255-byte frame register definition table 14-49. tr255 field descriptions bits name description 0?9 ? reserved 10?31 tr255 transmit and receive 128- to 255-byte frame count er?increments for each good or bad frame transmitted and received which is 128 to 255 bytes in length, inclusive (excluding preamble and sfd but including fcs bytes) 0910 15 r0000000000 tr511 w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_468c; tsec2:0x2_568c figure 14-52. transmit and receive 256- to 511-byte frame register definition 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-60 freescale semiconductor table 14-50 describes the fields of the tr511 register. 14.5.3.7.5 transmit and receive 512- to 1023-byte frame co unter register (tr1k) figure 14-53 shows the tr1k register. table 14-51 describes the fields of the tr1k register. 14.5.3.7.6 transmit and receive 1024- to 1518-by te frame counter register (trmax) figure 14-54 shows the trmax register. table 14-50. tr511 field descriptions bits name description 0?9 ? reserved 10?31 tr511 increments for each good or bad frame transmitted and received which is 256 to 511 bytes in length, inclusive (excluding preamble and sfd but including fcs bytes) 0910 15 r0 000000000 tr1k w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_4690; tsec2:0x2_5690 figure 14-53. transmit and receive 512- to 1023-byte frame register definition table 14-51. tr1k field descriptions bits name description 0?9 ? reserved 10?31 tr1k increments for each good or bad frame transmitted and received which is 512 to 1023 bytes in length, inclusive (excluding preamble and sfd but including fcs bytes) 0910 15 r0 000000000 trmax w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_4694; tsec2:0x2_5694 figure 14-54. transmit and receive 1024- to 1518-byte frame register definition 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-61 table 14-52 describes the fields of the trmax register. 14.5.3.7.7 transmit and receive 1519- to 1522- byte vlan frame counter register (trmgv) figure 14-55 shows the trmgv register. table 14-53 describes the fields of the trmgv register. 14.5.3.7.8 receive byte c ounter register (rbyt) figure 14-56 shows the rbyt register. table 14-52. trmax field descriptions bits name description 0?9 ? reserved 10?31 trmax increments for each good or bad frame transmitte d and received which is 1024 to 1518 bytes in length, inclusive (excluding preamble and sfd but including fcs bytes) 0910 15 r0 000000000 trmgv w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_4698; tsec2:0x2_5698 figure 14-55. transmit and receive 1519- to 1522-byte vlan frame register definition table 14-53. trmgv field descriptions bits name description 0?9 ? reserved 10?31 trmgv increments for each good or bad frame transmitte d and received which is 1519 to 1522 bytes in length, inclusive (excluding preamble and sfd but including fcs bytes) 0 15 r0 rbyt w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_469c; tsec2:0x2_569c figure 14-56. receive byte counter register definition 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-62 freescale semiconductor table 14-54 describes the fields of the rbyt register. 14.5.3.7.9 receive packet counter register (rpkt) figure 14-57 shows the rpkt register. table 14-55 describes the fields of the rpkt register. 14.5.3.7.10 receive fcs erro r counter register (rfcs) figure 14-58 shows the rfcs register. table 14-54. rbyt field descriptions bits name description 0?reserved 1?31 rbyt receive byte counter. increments by the byte count of frames received, including those in bad packets, excluding preamble and sfd but including fcs bytes. 0910 15 r0 000000000 rpkt w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_46a0; tsec2:0x2_56a0 figure 14-57. receive packet counter register definition table 14-55. rpkt field descriptions bits name description 0?9 ? reserved 10-31 rpkt receive packet counter. increments for each frame received packet (including bad packets, all unicast, broadcast, and multicast packets). 0151631 r0 000000000000000 rfcs w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_46a4; tsec2:0x2_56a4 figure 14-58. receive fcs error counter register definition 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-63 table 14-56 describes the fields of the rfcs register. 14.5.3.7.11 receive multicast pa cket counter register (rmca) figure 14-59 shows the rmca register. table 14-57 describes the fields of the rmca register. 14.5.3.7.12 receive broadcast pac ket counter register (rbca) figure 14-59 shows the rbca register. table 14-56. rfcs field descriptions bits name description 0?15 ? reserved 16?31 rfcs receive fcs error counter. increments for eac h frame received that has an integral 64 to 1518 length and contains a frame check sequence error. 0910 15 r0000000000 rmca w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_46a8; tsec2:0x2_56a8 figure 14-59. receive multicast pa cket counter register definition table 14-57. rmca field descriptions bits name description 0?9 ? reserved 10?31 rmca receive multicast packet counter. increments for ea ch multicast good frame of lengths 64 to 1518 (non vlan) or 1522 (vlan), excluding broadcast frames. this count does not include range/length errors. 0910 31 r0000000000 rbca w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_46ac; tsec2:0x2_56ac figure 14-60. receive broadcast packet counter register definition 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-64 freescale semiconductor table 14-58 describes the fields of the rbca register. 14.5.3.7.13 receive control frame packet counter register (rxcf) figure 14-61 shows the rxcf register. table 14-59 describes the fields of the rxcf register. 14.5.3.7.14 receive pause frame pa cket counter register (rxpf) figure 14-62 shows the rxpf register. table 14-58. rbca field descriptions bits name description 0?9 ? reserved 10?31 rbca receive broadcast packet counter. increments for each broadcast good frame of lengths 64 to 1518 (non vlan) or 1522 (vlan), excluding multicast frames. does not include range/length errors. 01516 31 r0 0000000000 0 0 0 0 0 rxcf w reset 0000_0000_0000_0000)0000_0000_0000_0000 offset tsec1:0x2_46b0; tsec2:0x2_56b0 figure 14-61. receive control frame packet counter register definition table 14-59. rxcf field descriptions bits name description 0?15 ? reserved 16?31 rxcf receive control frame packet counter. increments for each mac control frame received (both pause control frames and control frames unsupported by ieee). 01516 31 r0 0000000000 0 0 0 0 0 rxpf w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_46b4; tsec2:0x2_56b4 figure 14-62. receive pause frame pa cket counter register definition 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-65 table 14-60 describes the fields of the rxpf register. 14.5.3.7.15 receive unknown opcode pa cket counter register (rxuo) figure 14-63 shows the rxuo register. table 14-61 describes the fields of the rxuo register. 14.5.3.7.16 receive alignment er ror counter register (raln) figure 14-64 shows the raln register. table 14-60. rxpf field descriptions bits name description 0?15 ? reserved 16?31 rxpf receive pause frame packet counter. increments each time a valid pause mac control frame is received. 01516 31 r0 0000000000 0 0 00 0 rxuo w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_46b8; tsec2:0x2_56b8 figure 14-63. receive unknown opcode packet counter register definition table 14-61. rxuo field descriptions bits name description 0?15 ? reserved 16?31 rxuo receive unknown opcode counter. increments each ti me a mac control frame is received which contains an opcode other than a pause. 01516 31 r0 0000000000 0 0 0 0 0 raln w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_46bc; tsec2:0x2_56bc figure 14-64. receive alignment error counter register definition 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-66 freescale semiconductor table 14-62 describes the fields of the raln register. 14.5.3.7.17 receive fr ame length error count er register (rflr) figure 14-65 shows the rflr register. table 14-63 describes the fields of the rflr register. 14.5.3.7.18 receive code erro r counter regi ster (rcde) figure 14-66 shows the rcde register. table 14-62. raln field descriptions bits name description 0?15 ? reserved 16?31 raln receive alignment error counter. increments for each received frame from 64 to 1518 (non vlan) or 1522 (vlan) which contains an invalid fcs and is not an integral number of bytes. 01516 31 r0 0000000000 0 0 0 0 0 rflr w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_46c0; tsec2:0x2_56c0 figure 14-65. receive frame length error counter register definition table 14-63. rflr field descriptions bits name description 0?15 ? reserved 16?31 rflr receive frame length error counter. increments for each frame received in which the 802.3 length field did not match the number of data bytes actually received (4 6 ?1500 bytes). the counter does not increment if the length field is not a valid 802.3 length, such as an ethertype value. 01516 31 r00000000000 0 0 00 0 rcde w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_46c4; tsec2:0x2_56c4 figure 14-66. receive code error counter register definition 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-67 table 14-64 describes the fields of the rcde register. 14.5.3.7.19 receive carrier sense error counter register (rcse) figure 14-67 shows the rcse register. table 14-65 describes the fields of the rcse register. 14.5.3.7.20 receive undersize pa cket counter register (rund) figure 14-68 shows the rund register. table 14-64. rcde field descriptions bits name description 0?15 ? reserved 16?31 rcde receive code error counter. increments each time a valid carrier is present and at least one invalid data symbol is detected. 01516 31 r0 0000000000 0 0 00 0 rcse w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_46c8; tsec2:0x2_56c8 figure 14-67. receive carrier sense error counter register definition table 14-65. rcse field descriptions bits name description 0?15 ? reserved 16?31 rcse receive false carrier counter. increments each time a false carrier is detected during idle, as defined by a 1 on tsec n _rx_er and an 0xe on tsec n _rxd. the event is reported alo ng with the statistics generated on the next received frame. only one false carrier condition can be detected and logged between frames. 01516 31 r0 0000000000 0 0 00 0 rund w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_46cc; tsec2:0x2_56cc figure 14-68. receive undersize packet counter register definition 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-68 freescale semiconductor table 14-66 describes the fields of the rund register. 14.5.3.7.21 receive oversize pa cket counter register (rovr) figure 14-69 shows the rovr register. table 14-67 describes the fields of the rovr register. 14.5.3.7.22 receive fragment s counter register (rfrg) figure 14-70 shows the rfrg register. table 14-66. rund field descriptions bits name description 0?15 ? reserved 16?31 rund receive undersize packet counter. increments each ti me a frame is received which is less than 64 bytes in length and contains a valid fcs and were otherwise we ll formed. this count does not include range length errors. 01516 31 r0 0000000000 0 0 0 0 0 rovr w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_46d0; tsec2:0x2_56d0 figure 14-69. receive oversize packet counter register definition table 14-67. rovr field descriptions bits name description 0?15 ? reserved 16?31 rovr receive oversize packet counter. increments each time a frame is received which exceeded 1518 (non vlan) or 1522 (vlan) and contains a valid fcs and was ot herwise well formed. this count does not include range length errors. 0 15 16 31 r0 0000000000 0 0 0 0 0 rfrg w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_46d4; tsec2:0x2_56d4 figure 14-70. receive fragments counter register definition 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-69 table 14-68 describes the fields of the rfrg register. 14.5.3.7.23 receive jabber counter register (rjbr) figure 14-71 shows the rjbr register. table 14-69 describes the fields of the rjbr register. 14.5.3.7.24 receive dropped pac ket counter r egister (rdrp) figure 14-72 shows the rdrp register. table 14-68. rfrg field descriptions bits name description 0?15 ? reserved 16?31 rfrg receive fragments counter. increments for each frame received which is less than 64 bytes in length and contains an invalid fcs. this includes integral and non-integral lengths. 01516 31 r00000000000 0 0 0 0 0 rjbr w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_46d8; tsec2:0x2_56d8 figure 14-71. receive jabber counter register definition table 14-69. rjbr field descriptions bits name description 0?15 ? reserved 16-31 rjbr receive jabber counter. increments for frames received which exceed 1518 (non vlan) or 1522 (vlan) bytes and contain an invalid fcs. this includes alignment errors. 01516 31 r0 0000000000 0 0 0 0 0 rdrp w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_46dc; tsec2:0x2_56dc figure 14-72. receive dropped packet counter register definition 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-70 freescale semiconductor table 14-70 describes the fields of the rdrp register. 14.5.3.7.25 transmit byte counter register (tbyt) figure 14-73 shows the tbyt register. table 14-71 describes the fields of the tbyt register. 14.5.3.7.26 transmit packet counter register (tpkt) figure 14-74 shows the tpkt register. table 14-70. rdrp field descriptions bits name description 0?15 ? reserved 16?31 rdrp receive dropped packets counter. increments for fr ames received which are streamed to system but are later dropped due to lack of system resources. 01 31 r0 tbyt w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_46e0; tsec2:0x2_56e0 figure 14-73. transmit byte counter register definition table 14-71. tbyt field descriptions bits name description 0?reserved 1?31 tbyt transmit byte counter. increments by the number of bytes that were put on the wire including fragments of frames that were involved with collisions. this coun t does not include preamble/sfd or jam bytes. this counter does not count if the frame is truncated. 0910 31 r0 000000000 tpkt w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_46e4; tsec2:0x2_56e4 figure 14-74. transmit packet counter register definition 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-71 table 14-72 describes the fields of the tpkt register. 14.5.3.7.27 transmit multicast pa cket counter register (tmca) figure 14-75 shows the tmca register. table 14-73 describes the fields of the tmca register. 14.5.3.7.28 transmit broadcast pack et counter register (tbca) figure 14-76 shows the tbca register. table 14-72. tpkt field descriptions bits name description 0?9 ? reserved 10?31 tpkt transmit packet counter. increments for each transmitted packet (including bad packets, excessive deferred packets, excessive collision packets, late collision packets, all unicast, broadcast, and multicast packets). 0910 31 r0 000000000 tmca w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_46e 8; tsec2:0x2_56e8 figure 14-75. transmit multicast pa cket counter register definition table 14-73. tmca field descriptions bits name description 0?9 ? reserved 10?31 tmca transmit multicast packet counter. increments for ea ch multicast valid frame transmitted (excluding broadcast frames). 0910 31 r0000000000 tbca w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_46e c; tsec2:0x2_56ec figure 14-76. transmit broadcast packet counter register definition 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-72 freescale semiconductor table 14-74 describes the fields of the tbca register. 14.5.3.7.29 transmit pause control frame counter register (txpf) figure 14-77 shows the txpf register. table 14-75 describes the fields of the txpf register. 14.5.3.7.30 transmit deferral pa cket counter register (tdfr) figure 14-78 shows the tdfr register. table 14-74. tbca field descriptions bits name description 0?9 ? reserved 10?31 tbca transmit broadcast packet counter. increments fo r each broadcast frame transmitted (excluding multicast frames). 01516 31 r0 0000000000 0 0 0 0 0 txpf w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_46f 0; tsec2:0x2_56f0 figure 14-77. transmit pause control frame counter register definition table 14-75. txpf field descriptions bits name description 0?15 ? reserved 16?31 txpf transmit pause frame packet counter. increments each time a valid pause mac control frame is transmitted. 0 19 20 31 r0 0000000000 0 0 0 0 00000 tdfr w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_46f4; tsec2:0x2_56f4 figure 14-78. transmit deferral packet counter register definition 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-73 table 14-76 describes the fields of the tdfr register. 14.5.3.7.31 transmit excessive deferral packet counter register (tedf) figure 14-79 shows the tedf register. table 14-77 describes the fields of the tedf register. 14.5.3.7.32 transmit single collisi on packet counter register (tscl) figure 14-80 shows the tscl register. table 14-76. tdfr field descriptions bits name description 0?19 ? reserved 20?31 tdfr transmit deferral packet counter. increments for each frame, which was deferred on its first transmission attempt. this count does not include frames involved in collisions. 0 19 20 31 r0 0000000000 0 0 0 0 00000 tedf w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_46f8; tsec2:0x2_56f8 figure 14-79. transmit excessive deferra l packet counter register definition table 14-77. tedf field descriptions bits name description 0?19 ? reserved 20?31 tedf transmit excessive deferral packet counter. increments for frames aborted which were deferred for an excessive period of ti me (3036-byte times). 0 19 20 31 r0 0000000000 0 0 0 0 00000 tscl w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_46fc; tsec2:0x2_56fc figure 14-80. transmit single collision packet counter register definition 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-74 freescale semiconductor table 14-78 describes the fields of the tscl register. 14.5.3.7.33 transmit multiple collisio n packet counter register (tmcl) figure 14-81 shows the tmcl register. table 14-79 describes the fields of the tmcl register. 14.5.3.7.34 transmit late collision packet counter register (tlcl) figure 14-82 shows the tlcl register. table 14-78. tscl field descriptions bits name description 0?19 ? reserved 20?31 tscl transmit single collision packet counter. increments for each frame transmitted which experienced exactly one collision during transmission. 0 19 20 31 r0 0000000000 0 0 0 0 00000 tmcl w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_4700; tsec2:0x2_5700 figure 14-81. transmit multiple collision packet counter register definition table 14-79. tmcl field descriptions bits name description 0?19 ? reserved 20?31 tmcl transmit multiple collision packet counter. increm ents for each frame transmitted which experienced 2-15 collisions (including any late collisions) during transmission as defined using the half_duplex[retransmi ssion maximum] field. 0 19 20 31 r0 0000000000 0 0 0 0 00000 tlcl w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_4704; tsec2:0x2_5704 figure 14-82. transmit late collision packet counter register definition 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-75 table 14-80 describes the fields of the tlcl register. 14.5.3.7.35 transmit excessive collisi on packet counter register (txcl) figure 14-83 shows the txcl register. table 14-81 describes the fields of the txcl register. 14.5.3.7.36 transmit total collis ion counter register (tncl) figure 14-84 shows the tncl register. table 14-80. tlcl field descriptions bits name description 0?19 ? reserved 20?31 tlcl transmit late collision packet counter. increments for each frame transmitted which experienced a late collision during a transmission attempt. 0 19 20 31 r0 0000000000 0 0 0 0 00000 txcl w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_4708; tsec2:0x2_5708 figure 14-83. transmit excessive collision packet counter register definition table 14-81. txcl field descriptions bits name description 0?19 ? reserved 20?31 txcl transmit excessive collision packet counter. increments for each frame that experienced 16 collisions during transmission and was aborted. 0 181920 31 r0 0000000000 0 0 0 0 00000 tncl w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_470c; tsec2:0x2_570c figure 14-84. transmit total collision counter register definition 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-76 freescale semiconductor table 14-82 describes the fields of the tncl register. 14.5.3.7.37 transmit drop fram e counter register (tdrp) figure 14-85 shows the tdrp register. table 14-83 describes the fields of the tdrp register. 14.5.3.7.38 transmit jabber fram e counter register (tjbr) figure 14-86 shows the tjbr register. table 14-82. tncl field descriptions bits name description 0?19 ? reserved 20?31 tncl transmit total collision counter. increments by the number of collisions experienced during the transmission of a frame as defined as the simultaneous presence of signals on the do and rd circuits (that is, transmitting and receiving at the same time). note: this count does not include collisions that result in an excessive collision condition. 01516 31 r00000000000 0 0 0 0 0 tdrp w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_4714; tsec2:0x2_5714 figure 14-85. transmit drop frame counter register definition table 14-83. tdrp field descriptions bits name description 0?15 ? reserved 16?31 tdrp transmit drop frame counter. increments each time a memory error or an underrun has occurred. 0 19 20 31 r0 0000000000 0 0 0 0 0 0 0 0 0 tjbr w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_4718; tsec2:0x2_5718 figure 14-86. transmit jabber fr ame counter register definition 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-77 table 14-84 describes the fields of the tjbr register. 14.5.3.7.39 transmit fcs erro r counter regi ster (tfcs) figure 14-87 shows the tfcs register. table 14-85 describes the fields of the tfcs register. 14.5.3.7.40 transmit control fram e counter regi ster (txcf) figure 14-88 shows the txcf register. table 14-86 describes the fields of the txcf register. table 14-84. tjbr field descriptions bits name description 0?19 ? reserved 20?31 tjbr transmit jabber frame counter. increments for each oversized transmitted frame with an incorrect fcs value. 0 19 20 31 r00000000000000000000 tfcs w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_471c; tsec2:0x2_571c figure 14-87. transmit fcs error counter register definition table 14-85. tfcs field descriptions bits name description 0?19 ? reserved 20?31 tfcs transmit fcs error counter. increments for every valid sized packet with an incorrect fcs value. 0 19 20 31 r0 0000000000 0 0 0 0 0 0 0 0 0 txcf w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_4720; tsec2:0x2_5720 figure 14-88. transmit control frame counter register definition table 14-86. txcf field descriptions bits name description 0?19 ? reserved 20?31 txcf transmit control frame counter. increments for ever y valid size frame with a type field signifying a control frame. 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-78 freescale semiconductor 14.5.3.7.41 transmit oversize fr ame counter register (tovr) figure 14-89 shows the tovr register. table 14-87 describes the fields of the tovr register. 14.5.3.7.42 transmit undersize fr ame counter register (tund) figure 14-90 shows the tund register. table 14-88 describes the fields of the tund register. 0 19 20 31 r00000000000000000000 tovr w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_4724; tsec2:0x2_5724 figure 14-89. transmit oversized frame counter register definition table 14-87. tovr field descriptions bits name description 0?19 ? reserved 20?31 tovr transmit oversize frame counter. increments for each oversized transmitted frame with a correct fcs value. 0 19 20 31 r0 0000000000 0 0 00 0 0 0 0 0 tdfr w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_4728; tsec2:0x2_5728 figure 14-90. transmit undersize frame counter register definition table 14-88. tund field descriptions bits name description 0?19 ? reserved 20?31 tdfr transmit undersize frame counter. increments for ev ery frame less then 64 bytes, with a correct fcs value. 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-79 14.5.3.7.43 transmit fragment counter register (tfrg) figure 14-91 shows the tfrg register. table 14-89 describes the fields of the tfrg register. 14.5.3.7.44 carry register 1 (car1) carry register bits are clea red when written with a one. figure 14-92 shows the car1 register. table 14-90 describes the fields of the car1 register. 0 19 20 31 r00000000000 0 0 0 0 0 0000 tfrg w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_472c; tsec2:0x2_572c figure 14-91. transmit fragment counter register definition table 14-89. tfrg field descriptions bits name description 0?19 ? reserved 20?31 tfrg transmit fragment counter. increments for every frame less then 64 bytes, with an incorrect fcs value. 0 1 2 3 4 5 6 7 14 15 r c1 64 c1 127 c1 255 c1 511 c1 1k c1 max c1 mgv 00 0 00000 c1 rby w reset 0000_0000_0000_0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r c1 rpk c1 rfc c1 rmc c1 rbc c1 rxc c1 rxp c1 rxu c1 ral c1 rfl c1 rcd c1 rcs c1 run c1 rov c1 rfr c1 rjb c1 rdr w reset 0000_0000_0000_0000 offset tsec1:0x2_4730; tsec2:0x2_5730 figure 14-92. carry register 1 (car1) register definition table 14-90. car1 field descriptions bits name description 0 c164 carry register 1 tr64 counter carry bit 1 c1127 carry register 1 tr127 counter carry bit 2 c1255 carry register 1 tr255 counter carry bit 3 c1511 carry register 1 tr511 counter carry bit 4 c11k carry register 1 tr1k counter carry bit 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-80 freescale semiconductor 14.5.3.7.45 carry register 2 (car2) figure 14-93 shows the car2 register. 5 c1max carry register 1 trmax counter carry bit 6 c1mgv carry register 1 trmgv counter carry bit 7?14 ? reserved 15 c1rby carry register 1 rbyt counter carry bit 16 c1rpk carry register 1 rpkt counter carry bit 17 c1rfc carry register 1 rfcs counter carry bit 18 c1rmc carry register 1 rmca counter carry bit 19 c1rbc carry register 1 rbca counter carry bit 20 c1rxc carry register 1 rxcf counter carry bit 21 c1rxp carry register 1 rxpf counter carry bit 22 c1rxu carry register 1 rxuo counter carry bit 23 c1ral carry register 1 raln counter carry bit 24 c1rfl carry register 1 rflr counter carry bit 25 c1rcd carry register 1 rcde counter carry bit 26 c1rcs carry register 1 rcse counter carry bit 27 c1run carry register 1 rund counter carry bit 28 c1rov carry register 1 rovr counter carry bit 29 c1rfr carry register 1 rfrg counter carry bit 30 c1rjb carry register 1 rjbr counter carry bit 31 c1rdr carry register 1 rdrp counter carry bit 0 11 12 13 14 15 r0 0 0 0 0 0 0 0 0 0 0 0 c2 tjb c2 tfc c2 tcf c2 tov w reset 0000_0000_0000_0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r c2 tun c2 tfg c2 tby c2 tpk c2 tmc c2 tbc c2 tpf c2 tdf c2 ted c2 tsc c2 tma c2 tlc c2 txc c2 tnc 0 c2 tdp w reset 0000_0000_0000_0000 offset tsec1:0x2_4734; tsec2:0x2_5734 figure 14-93. carry register 2 (car2) register definition table 14-90. car1 field descriptions (continued) bits name description 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-81 carry register bits are clea red when written with a one. table 14-91 describes the fields of the car2 register. table 14-91. car2 field descriptions bits name description 0?11 ? reserved 12 c2tjb carry register 2 tjbr counter carry bit 13 c2tfc carry register 2 tfcs counter carry bit 14 c2tcf carry register 2 txcf counter carry bit 15 c2tov carry register 2 tovr counter carry bit 16 c2tun carry register 2 tund counter carry bit 17 c2tfg carry register 2 tfrg counter carry bit 18 c2tby carry register 2 tbyt counter carry bit 19 c2tpk carry register 2 tpkt counter carry bit 20 c2tmc carry register 2 tmca counter carry bit 21 c2tbc carry register 2 tbca counter carry bit 22 c2tpf carry register 2 txpf counter carry bit 23 c2tdf carry register 2 tdfr counter carry bit 24 c2ted carry register 2 tedf counter carry bit 25 c2tsc carry register 2 tscl counter carry bit 26 c2tma carry register 2 tmcl counter carry bit 27 c2tlc carry register 2 tlcl counter carry bit 28 c2txc carry register 2 txcl counter carry bit 29 c2tnc carry register 2 tncl counter carry bit 30 ? reserved 31 c2tdp carry register 2 tdrp counter carry bit 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-82 freescale semiconductor 14.5.3.7.46 carry mask register 1 (cam1) as long as one of the below mask bits is cleare d, the corresponding interrupt bit is allowed to cause interrupt indications on output carry. th ese bits all default to a set state. figure 14-94 shows the cam1 register. table 14-92 describes the fields of the cam1 register. 0 1 2 3 4 5 6 7 14 15 r m1 64 m1 127 m1 255 m1 511 m1 1k m1 max m1 mgv 00 0 00000 m1 rby w reset 1111_1110_0000_0001 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r m1 rpk m1 rfc m1 rmc m1 rbc m1 rxc m1 rxp m1 rxu m1 ral m1 rfl m1 rcd m1 rcs m1 run m1 rov m1 rfr m1 rjb m1 rdr w reset 1111_1111_1111_1111 offset tsec1:0x2_4738; tsec2:0x2_5738 figure 14-94. carry mask register 1 (cam1) register definition table 14-92. cam1 field descriptions bits name description 0 m164 mask register 1 tr64 counter carry bit mask 1 m1127 mask register 1 tr127 counter carry bit mask 2 m1255 mask register 1 tr255 counter carry bit mask 3 m1511 mask register 1 tr511 counter carry bit mask 4 m11k mask register 1 tr1k counter carry bit mask 5 m1max mask register 1 trm ax counter carry bit mask 6 m1mgv mask register 1 trmgv counter carry bit mask 7?14 ? reserved 15 m1rby mask register 1 rbyt counter carry bit mask 16 m1rpk mask register 1 rpkt counter carry bit mask 17 m1rfc mask register 1 rfcs counter carry bit mask 18 m1rmc mask register 1 rmca counter carry bit mask 19 m1rbc mask register 1 rb ca counter carry bit mask 20 m1rxc mask register 1 rxcf counter carry bit mask 21 m1rxp mask register 1 rxpf counter carry bit mask 22 m1rxu mask register 1 rxuo counter carry bit mask 23 m1ral mask register 1 raln counter carry bit mask 24 m1rfl mask register 1 rf lr counter carry bit mask 25 m1rcd mask register 1 rcde counter carry bit mask 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-83 14.5.3.7.47 carry mask register 2 (cam2) as long as one of the below mask bits is cleare d, the corresponding interrupt bit is allowed to cause interrupt indications on output carry. these bits default to a set state. figure 14-95 shows the cam2 register. table 14-93 describes the fields of the cam2 register. 26 m1rcs mask register 1 rcse counter carry bit mask 27 m1run mask register 1 rund counter carry bit mask 28 m1rov mask register 1 rovr counter carry bit mask 29 m1rfr mask register 1 rfrg counter carry bit mask 30 m1rjb mask register 1 rj br counter carry bit mask 31 m1rdr mask register 1 rdrp counter carry bit mask 0 11 12 13 14 15 r0 0 0 0 0 0 0 0 0 0 0 0 m2 tjb m2 tfc m2 tcf m2 tov w reset 0000_0000_0000_1111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r m2 tun m2 tfg m2 tby m2 tpk m2 tmc m2 tbc m2 tpf m2 tdf m2 ted m2 tsc m2 tma m2 tlc m2 txc m2 tnc 0 m2 tdp w reset 1111_1111_1111_1111 offset tsec1:0x2_473c; tsec2:0x2_573c figure 14-95. carry mask register 2 (cam2) register definition table 14-93. cam2 field descriptions bits name description 0?11 ? reserved 12 m2tjb mask register 2 tjbr counter carry bit mask 13 m2tfc mask register 2 tf cs counter carry bit mask 14 m2tcf mask register 2 tx cf counter carry bit mask 15 m2tov mask register 2 tovr counter carry bit mask 16 m2tun mask register 2 tund counter carry bit mask 17 m2tfg mask register 2 tfrg counter carry bit mask 18 m2tby mask register 2 tbyt counter carry bit mask 19 m2tpk mask register 2 tpkt counter carry bit mask 20 m2tmc mask register 2 tmca counter carry bit mask table 14-92. cam1 field descriptions (continued) bits name description 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-84 freescale semiconductor 14.5.3.8 hash function registers this section provides detailed descriptions of th e registers used for hash func tions. all of the registers are 32 bits wide. if the da field of a r eceive frame is processed through a 32-bit crc gene rator, the 8 bits of the crc remainder is mapped to a hash table entry. the user can enable a hash entry by setting the appropriate bit. a hash entry usuall y represents a set of addresses. a hash table hit occurs if the da crc result points to an enabled hash entry. the user must further filter the address. see section 14.6.2.6.2, ?hash table algorithm,? for more information on the hash algorithm. 14.5.3.8.1 individual addr ess registers 0?7 (iaddr n ) the iaddr n registers, shown in figure 14-96 , are written by the user. these registers represent 256 entries of the individual ( unicast) address hash table used in the address recognition proc ess. when the da field of a receive frame is processed through a 32-bit crc generator, the 8 high-order bits (0-7) of the crc remainder are mapped to one of the 256 entries. the user can enable a hash entry by setting the appropriate bit. a hash table hit occurs if the da cr c result points to an enabled hash entry. 21 m2tbc mask register 2 tbca counter carry bit mask 22 m2tpf mask register 2 txpf counter carry bit mask 23 m2tdf mask register 2 tdfr counter carry bit mask 24 m2ted mask register 2 te df counter carry bit mask 25 m2tsc mask register 2 tscl counter carry bit mask 26 m2tma mask register 2 tmcl counter carry bit mask 27 m2tlc mask register 2 tl cl counter carry bit mask 28 m2txc mask register 2 txcl counter carry bit mask 29 m2tnc mask register 2 t ncl counter carry bit mask 30 ? reserved 31 m2tdp mask register 2 tdrp counter carry bit mask 0 31 r iaddr n w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_4800, 0x2_4804, 0x2_4808, 0x2_480c, 0x2_4810, 0x2_4814, 0x2_4818, 0x2_481c tsec2:0x2_5800, 0x2_5804, 0x 2_5808, 0x2_580c, 0x2_5810, 0x2_5814, 0x2_5818, 0x2_581c figure 14-96. iaddr n register definition table 14-93. cam2 field descriptions (continued) bits name description 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-85 table 14-94 describes the field of the iaddr n registers. 14.5.3.8.2 group addre ss registers 0?7 (gaddr n ) the gaddr n registers are written by the user. together these regist ers represent 256 entries of the group (multicast) address hash table used in the address recognition process. while the da field of a receive frame is processed through a 32-bit crc generator, the 8 bits of the cr c remainder is mapped to one of the 256 entries. the user can enable a hash entry by se tting the appropriate bit. a hash table hit occurs if the da crc result points to an enabled hash entry. figure 14-97 shows the gaddr n registers. table 14-95 describes gaddr n . 14.5.3.9 attribute registers this section describes the two tsec frame attribute registers. 14.5.3.9.1 attribute register (attr) the attribute register, shown in figure 14-98 , defines attributes and transact ion types used to access buffer descriptors, to write receive data, a nd to read transmit data. snoop enable attributes may be set for reading buffer descriptors and for reading tran smit data. buffer descriptors may be written with attributes that cause allocation into the l2 cache wi th or without line locking. simila rly, sections of a receive frame header may have attributes attached that cause allocation and locking in the l2 cache. this process of table 14-94. iaddr n field descriptions bits name description 0?31 iaddr n represents the 32-bit value associated with the corresponding register. iaddr0 contains the high-order 32 bits of the 256-entry hash table and iaddr7 repres ents the low-order 32 bits. for instance, the msb of iaddr0 correlates to entry 0 and the lsb of iaddr7 correlates to entry 255. 0 31 r gaddr n w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_4880, 0x2_4884, 0x2_4888, 0x2_488c, 0x2_4890, 0x2_4894, 0x2_4898, 0x2_489c tsec2:0x2_5880, 0x2_5884, 0x2_5888, 0x 2_588c, 0x2_5890, 0x2_5894, 0x2_5898, 0x2_589c figure 14-97. gaddr n register definition table 14-95. gaddr n field descriptions bits name description 0?31 gaddr n represents the 32-bit value associated with the corresponding register. gaddr0 contains the high-order 32 bits of the 256 entry group hash table and gaddr7 represents the low-order 32 bits. for instance, the msb of gaddr0 correlates to entry 0 and the lsb of gaddr7 correlates to entry 255. 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-86 freescale semiconductor specifying a region of each frame to stash into the l2 cac he is referred to as extraction, which is specified in conjunction with attreli. attr[elcwt] only has meaning if a ttreli[el] is non-zero. table 14-96 describes the fields of the attr register. 0 151617 181920 212223 24 25 26 31 r 0000_0000_0000_0000 0 elcwt 0 bdlwt 00 rdsen rbdsen 0 0000 0 w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_4bf8; tsec2:0x2_5bf8 figure 14-98. attr register definition table 14-96. attr field descriptions bits name description 0?16 ? reserved 17?18 elcwt extracted l2 cache write type. specifies the write transaction type to perform for the extracted data. this occurs only if attreli[el] is non-zero. for maximum pe rformance, it is recomme nded that if elcwt is set to allocate, bdlwt must also be set to allocate. writes to cache are always performed with snoop. this setting overrides the rdsen bit setting. 00 no allocation performed. 01 reserved, no extraction occurs. 10 allocate l2 cache line. 11 reserved 19 ? reserved 20?21 bdlwt buffer descriptor l2 cache write type. specifies the wr ite transaction type to perform for the buffer descriptor for a receive frame. writes to cache are always performed with snoop. 00 no allocation performed. this setting overrides the rbdsen bit setting. 01 reserved 10 allocate l2 cache line. 11 reserved 22?23 ? reserved 24 rdsen rx data snoop enable. this bit is superseded by the elcwt settings. 0 disables snooping of all receive frames data to memory unless elcwt specifies l2 allocation. 1 enables snooping of all receive frames data to memory. 25 rbdsen rxbd snoop enable. this bit is superseded by the bdlwt settings. 0 disables snooping of all receive bd memory accesses unless bdlwt sp ecifies l2 allocation. 1 enables snooping of all re ceive bd memory accesses. 26?31 ? reserved 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-87 14.5.3.9.2 attribute extr act length and extract i ndex register (attreli) the attreli registers are written by the user to specify the extract index and extract length. figure 14-99 shows the attreli register. table 14-97 describes the fields of the attreli register. 14.5.4 ten-bit interface (tbi) this section describes the ten-bit interface (tbi) and the tbi mii set of registers. 14.5.4.1 tbi mii set register descriptions this section describes the tbi mii registers. all tb i registers are 16 bits wide and are accessed at the offset of the tbi physical address. the tbi physical address of the tsec is stored in tbipa. writing to the tbi registers is similar to writing to an external phy, by using the mii management interface. by using tbipa in place of the phy address, in th e miimadd[phy address] field, and setting miimadd[register address] to th e address offset that correspond s to the desired register (see table 14-98 ), the user can read (set miimcom[read cycle]) or write (wri ting to miimcon[phy control]) to the tbi block. refer to the tbi physical addr ess register in section 14.5.3.1, ?tsec general control and status registers,? and the tbi mii register set in table 14-98 . note that jitter diagnostics and tbi control are not ieee 802.3 required re gisters and are onl y used for test and control of the tsec tbi block. the tbi?s tbi c ontrol register (tbi) is for configuring the tsec 0 1 2 15 16 17 18 31 r00 el 00 ei w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_4bfc; tsec2:0x2_5bfc figure 14-99. attreli register definition table 14-97. attreli field descriptions bits name description 0?1 ? reserved 2?15 el extracted length. specifies the nu mber of bytes to extract from the receive frame. the dma controller uses this field to perform extraction. if set to zero, no extraction is performed. 16?17 ? reserved 18?31 ei extracted index. points to the first byte within the receive frame from which to begin extracting data. 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-88 freescale semiconductor ten-bit interface block. however, be cause this tbi block ha s an mii management in terface (just like any other phy), it has an ieee 802.3 register called the control register (cr). 14.5.4.2 control register (cr) figure 14-100 shows the cr register. table 14-99 describes the fields of the cr register. table 14-98. tbi mii register set offset name access size section/page ten-bit interface (tbi) registers 14.5.4/14-87 0x00 control (cr) r/w 1 1 r = means read only, wo = write only, r/w = read and write, lh = latches high, ll = latches low, sc = self-clearing, 16 bits 14.5.4.2/14-88 0x01 status (sr) r, lh, ll 16 bits 14.5.4.3/14-89 0x02?0x03 reserved r 2 bytes ? 0x04 an advertisement (ana) rw, r 16 bits 14.5.4.3/14-89 0x05 an link partner base page ability (anlpbpa) r 16 bits 14.5.4.5/14-92 0x06 an expansion (anex) r, lh 16 bits 14.5.4.6/14-93 0x07 an next page transmit (annpt) r/w, r 16 bits 14.5.4.7/14-94 0x08 an link partner ability next page (anlpanp) r 16 bits 14.5.4.8/14-95 0x0f extended status (exst) r 16 bits 14.5.4.9/14-96 0x10 jitter diagnostics (jd) r/w 16 bits 14.5.4.10/14-97 0x11 tbi control (tbicon) r/w 16 bits 14.5.4.11/14-98 0 1 2 3 4 5 6 7 8 9 10 15 r phy reset 0 speed_0 an enable 00 reset an full duplex 0 speed_1 000000 w reset 0000_0000_0000_0000 offset tbipa offset + 0x00 figure 14-100. control register definition table 14-99. cr field descriptions bits name description 0 phy reset phy reset. this bit is cleared by default. this bit is self-clearing. 0 normal operation. 1 the control and status registers are returned to their default value. this in turn may change the internal state of the tbi and its link partner. 1?reserved 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-89 14.5.4.3 status register (sr) figure 14-101 shows the sr register. 2 speed_0 speed selection. this bit defaults to a cleared state and must always be cleared, which corresponds to 1-gbps speed. 3 an enable auto-negotiation enable. this bit is cleared by default. 0 the values programmed in bits 2, 7 and 9 de termine the operating condition of the link. 1 auto-negotiation process enabled. 4?5 ? reserved 6 reset an reset auto-negotiation. this bit is cleared by default and is self-clearing. 0 normal operation. 1 the auto-negotiation process restarts. this action is only available if auto-negotiation is enabled. 7 full duplex duplex mode. this bit is cleared by default. 0 half-duplex operation. 1 full-duplex operation. 8 ? reserved, must be cleared. 9 speed_1 speed selection. defaults to a cleared state but must always be set, which corresponds to 1-gbps. 10?15 ? reserved 06789101112131415 r 00 0000 0 extend status 0 no pre an done remote fault an ability link status 0 extend ability w reset 0000_0001_0100_1001 offset tbipa offset + 0x01 figure 14-101. status register definition table 14-99. cr field descriptions (continued) bits name description maximum operating speed bit 2 bit 9 reserved 0 0 reserved 1 0 1 gbps 0 1 reserved 1 1 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-90 freescale semiconductor table 14-100 describes the fields of the sr register. 14.5.4.4 an advertisement register (ana) figure 14-102 shows the ana register. table 14-100. sr descriptions bits name description 0?6 ? reserved, must be cleared. 7extend status indicates that phy status information is also contai ned in the extended status register. returns 1 on read. this bit is read-only. 8 ? reserved, must be cleared. 9no pre mf preamble suppression enable. this bit indicates whether or not the phy is capable of handling mii management frames without the 32-bi t preamble field. returns 1, indicating support for suppressed preamble mii management frames. this bit is read-only. 10 an done auto-negotiation complete. this bit is read-only and is cleared by default. 0 either the auto-negotiation process is underway or the auto-negotiation function is disabled. 1 the auto-negotiation process has completed. 11 remote fault remote fault. this bit is read-only and is cleared by default. each read of sr clears this bit. 0 normal operation. 1 a remote fault condition was detected. latches high for software to detect the condition. 12 an ability auto-negotiation ability. while read as set, this bi t indicates that the phy has the ability to perform auto-negotiation. while read as cleared, this bit indicates the phy lacks the ability to perform auto-negotiation. returns 1 on read. this bit is read-only. 13 link status link status. this bit is read-only and is cleared by default. 0 a valid link is not established. latches low allowing for software polling to detect a failure condition. 1 a valid link is established. 14 ? reserved, must be cleared. 15 extend ability extended capability. this bit indicates that the phy co ntains the extended set of registers (those beyond control and status). returns 1 on read. this bit is read-only. 012 34 6 7 8 9 1011 15 r next page ack remote fault 00 0 pause half duplex full duplex 00 0 0 0 w reset 0000_0000_0000_0000 offset tbipa offset + 0x04 figure 14-102. an advertisement register definition 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-91 table 14-101 describes the fields of the ana register. table 14-101. ana field descriptions bits name description 0next page next page configuration. the local device sets this bit to either request next page transmission or advertise next page exchange capability. 0 the local device wishes not to engage in next page exchange. 1 the local device has no next pages but wishes to allo w reception of next pages. if the local device has no next pages and the link partner wishes to send next pages, the local device shall send null message codes and have the message page set to 0b000_0000_0001, as defined in annex 28c of the ieee 802.3 specification. 1 ack acknowledge. write 0, ignore on read.this bit is read-only. (reserved) 2?3 remote fault the local device?s remote fault condition is encoded in bits 2 and 3 of the base page. values are shown in the following table. the default value is 00. indicate a fault by setting a non-zero remote fault encoding and re-negotiating. 4?6 ? reserved, must be cleared. 7?8 pause the local device?s pause capability is encoded in bi ts 7 and 8, and the decodes are shown in the following table. for priority resolution information consult table 14-102 . 9half duplex half-duplex capability 0 designates local device as not capable of half-duplex operation. 1 designates local device as capable of half-duplex operation. 10 full duplex full-duplex capability 0 designates the local device as not capable of full-duplex operation. 1 designates the local device as capable of full-duplex operation. 11?15 ? reserved, must be cleared. rf1 bit[3] rf2 bit[2] description 0 0 no error, link ok 0 1 offline 1 0 link_failure 1 1 auto-negotiation_error pause bit[8] asm_dir bit[7] capability 0 0 no pause 0 1 asymmetric pause toward link partner 10symmetric pause 1 1 both symmetric pause and asymmetric pause toward local device 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-92 freescale semiconductor table 14-102 describes the resolution of pause priority. 14.5.4.5 an link partner base pa ge ability register (anlpbpa) figure 14-103 shows the anlpbpa register. table 14-103 describes the fields of the anlpbpa register. table 14-102. pause priority resolution local device link partner local resolution link partner resolution paus e as m _d ir paus e a sm _ dir 0 0 x x disable pause transmit disable pause receive disable pause transmit disable pause receive 0 1 0 x disable pause transmit disable pause receive disable pause transmit disable pause receive 0110disable pause transmit disable pause receive disable pause transmit disable pause receive 0 1 1 1 enable pause transmit disable pause receive disable pause transmit enable pause receive 1 0 0 x disable pause transmit disable pause receive disable pause transmit disable pause receive 1 0 1 x enable pause transmit enable pause receive enable pause transmit enable pause receive 1100disable pause transmit disable pause receive disable pause transmit disable pause receive 1101disable pause transmit enable pause receive enable pause transmit disable pause receive 1 1 1 x enable pause transmit enable pause receive enable pause transmit enable pause receive 012 34 67 8 9 10 11 15 rnext page ack remote fault 000 pause half duplex full duplex 00 0 0 0 w reset 0000_0000_0000_0000 offset tbipa offset + 0x05 figure 14-103. an link partner base page ability register definition table 14-103. anlpbpa field descriptions bits name description 0next page next page. this bit is read-only. the link partner sets or clears this bit. 0 link partner has no subsequent next pages or is not capable of receiving next pages. 1 link partner either requesting next page transmission or indicating the capability to receive next pages. 1 ack acknowledge. ignore on read. this bit is read-only 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-93 14.5.4.6 an expansi on register (anex) figure 14-104 shows the anex register. 2?3 remote fault the link partner?s remote fault condition is encoded in bits 2 and 3 of the base page. values are shown in the remote fault encoding field table below. this bit is read-only. 4?6 ? reserved, must be cleared. 7?8 pause encoding of the link partner?s pause capability is shown in the pause encoding table below. for priority resolution information consul t the ieee 802.3 spec ification. this bit is read-only. 9half duplex half-duplex capability. this bit is read-only. 0 link partner is not capable of half-duplex mode. 1 link partner is capable of half-duplex mode. 10 full duplex full-duplex capability. this bit is read-only. 0 link partner is not capable of full-duplex mode. 1 link partner is capable of full-duplex mode. 11?15 ? reserved, must be cleared. 0 12 13 14 15 r0000000000000np ablepage rx?d0 w reset 0000_0000_0000_0100 offset tbipa offset + 0x06 figure 14-104. an expansion register definition table 14-103. anlpbpa field descriptions (continued) bits name description rf1 bit[3] rf2 bit[2] description 0 0 no error, link ok 0 1 offline 1 0 link_failure 1 1 auto-negotiation_error pause bit[8] asm_dir bit[7] capability 0 0 no pause 0 1 asymmetric pause toward link partner 10symmetric pause 1 1 both symmetric pause and asymmetric pause toward local device 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-94 freescale semiconductor table 14-104 describes the fields of the anex register. 14.5.4.7 an next page tr ansmit register (annpt) figure 14-105 shows the annpt register. table 14-104. anex field descriptions bits name description 0?12 ? reserved, must be cleared. 13 np able next page able. this bit is read-only and returns 1 on read. while read as set, indicates local device supports next page function. 14 page rx?d page received. this bit is read-only. the bit clears on a read to the register. 0 normal operation. 1 a new page was received and stored in the applicable an link partner ability or an next page register. this bit latches high in order for software to detect while polling. 15 ? reserved, must be cleared. 012 345 15 r next page ack msg page ack2 toggle message/unformatted code field w reset 0000_0000_0000_0000 offset tbipa offset + 0x07 figure 14-105. an next page transmit register definition 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-95 table 14-105 describes the fields of the annpt register. 14.5.4.8 an link partner ability next page register (anlpanp) figure 14-106 shows the anlpanp register. table 14-105. annpt field descriptions bits name description 0 next page next page indication. [reference mii bit 7.15 in ieee 802.3, 2000 edition clause 28.2.4] 0 last page 1 additional next pages to follow 1 ack acknowledge. write 0, ignore on read. [reference mii bit 7.14] this bit is read-only. 2 msg page message page. [reference mii bit 7.13] 0 unformatted page 1 message page 3 ack2 acknowledge 2. used by the next page function to in dicate that the device has the ability to comply with the message. [reference mii bit 7.12] 0 the local device cannot comply with message. 1 the local device complies with message. 4 toggle toggle. used to ensure synchronization with the link partner during next page exchange. this bit always takes the opposite value of the toggle bit of the prev iously-exchanged link code word. the initial value in the first next page transmitted is the inverse of bit 11 in the base link code word. [reference mii bit 7.11] this bit is read-only. 0 toggle bit of the previously-exchanged link code word was set. 1 toggle bit of the previously-exchanged link code word was clear. 5?15 message/ unformatted code field message pages are formatted pages that carry a pr e-defined message code, which is enumerated in ieee 802.3u/annex 28c. unfo rmatted code fields take on an arbitr ary value. [referenc e mii field 7.10:0] 012 345 15 r next page ack msg page ack2 toggle message/unformatted code field w reset 0000_0000_0000_0000 offset tbipa offset + 0x08 figure 14-106. an link partner ability next page register definition 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-96 freescale semiconductor table 14-106 describes the anlpanp fields. 14.5.4.9 extended status register (exst) figure 14-107 shows the exst register. table 14-106. anlpan p field descriptions bits name description 0 next page next page. the link partner sets and clears this bit. 0 last page from link partner. 1 additional next pages to follow. 1 ack acknowledge. ignore on read. [referenc e mii bit 8.14] this bit is read-only. 2 msg page message page 0 unformatted page. 1 message page. 3 ack2 acknowledge 2. indicates the link partner?s ability to comply with the message. 0 link partner cannot comply with message. 1 link partner complies with message. 4 toggle toggle. used to ensure synchronization with the link partner during next page exchange. this bit always takes the opposite value of the toggle bit of the prev iously-exchanged link code word. the initial value in the first next page transmitted is the inverse of bit 11 in the base link code word. this bit is read-only. 0 toggle bit of the previously-exchanged link code word was set. 1 toggle bit of the previously-exchanged link code word was clear. 5?15 message/ unformatted code field message pages are formatted pages that carry a pr e-defined message code, which is enumerated in ieee 802.3u/annex 28c. unfo rmatted code fields take on an arbitrary value. 01234 15 r 1000x full 1000x half 1000t full 1000t half 0 0 0 000000000 w reset 1010_0000_0000_0000 offset tbipa offset + 0x0f figure 14-107. extended status register definition 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-97 table 14-107 describes the fields of the exst register. 14.5.4.10 jitter diagnostics register (jd) annex 36a in ieee 802.3z describes seve ral jitter test patterns. these can be configured to be sent by writing the jitter dia gnostics register. see the regist er description for more info rmation. it may be wise to auto-negotiate and advertise a remo te fault, signaling offline, prio r to beginning the test patterns. figure 14-108 shows the jd register. table 14-107. exst field descriptions bits name description 0 1000x full 1000x full-duplex capability. returns 1 on read. this bit is read-only. 0 phy cannot operate in 1000base-x full-duplex mode. 1 phy can operate in 1 000base-x full-duplex mode. 1 1000x half 1000x half-duplex capability. returns 0 on read. this bit is read-only. 0 phy cannot operate in 1000base-x half-duplex mode. 1 phy can operate in 1 000base-x half-duplex mode. 2 1000t full 1000t full-duplex capability. returns 1 on read. this bit is read-only. 0 phy cannot operate in 1000base-t full-duplex mode. 1 phy can operate in 1 000base-t full-duplex mode. 3 1000t half 1000t half-duplex capability. returns 0 on read. this bit is read-only. 0 phy cannot operate in 1000base-t half-duplex mode. 1 phy can operate in 1 000base-t half-duplex mode. 4?15 ? reserved 01 3456 15 r jitter enable jitter select 00 custom jitter pattern w reset 0000_0000_0000_0000 offset tbipa offset + 0x10 figure 14-108. jitter diagnostics register definition 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-98 freescale semiconductor table 14-108 describes the fields of the jd register. 14.5.4.11 tbi control register (tbicon) figure 14-109 shows the tbicon register. table 14-108. jd field descriptions bits name description 0 jitter enable jitter enable. this bit is cleared by default. 0 normal transmit operation. 1 enable the tbi to transmit t he jitter test patterns defined in annex 36a of the ieee 802.3 specification. 1?3 jitter select selects the jitter pattern to be transmitted in diagnostics mode. encoding of this field is shown in the following table. default is 0. 4?5 ? reserved 6?15 custom jitter pattern used in conjunction with jitter (pattern) select and jitte r (diagnostic) enable; set this field to the desired custom pattern which is continuously transmitted. its default is 0. 01234 6789101112131415 r soft_reset 0 disable rx dis disable tx dis 000 an sense 00 clock select mii mode 00 00 w reset 0000_0000_0000_0000 offset tbipa offset + 0x11 figure 14-109. tbi control register definition jitter pattern select bit[1] bit[2] bit[3] user defined uses custom jitter pattern, bits 6?15 0 0 0 high frequency (d21.5) 1010101010101010101010101010101010101010? 001 mixed frequency (k28.5) 1111101011000001010011111010110000010100? 010 low frequency 1111100000111110000011111000001111100000? 011 complex pattern (10?h17c,10?h0c9,10?h0e5,10?h2a3, 10?h17c,...) 1 0 0 square wave (-k28.7) 0011111000001111100000111110000011111000? 101 reserved 110 reserved 111 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-99 table 14-109 describes the fields of the tbicon register. 14.6 functional description this section describes many of the functions of the tsec controller. 14.6.1 connecting to physical interfaces this section describes how to connect the tsec to various interfaces: mii, gmii, rgmii, rtbi, and tbi. to avoid confusion, all of the buses follow the bus conventions used in the ieee 802.3 specification, because each phy follows the same convention. (for instance, in the bus tsec n _txd[7:0], bit 7 is the msb and bit 0 is the lsb.) table 14-109. tbicon field descriptions bits name description 0 soft_reset soft reset. this bit is cleared by default. 0 normal operation. 1 resets the functional modules in thetbi. 1 ? reserved. (ignore on read) 2 disable rx dis disable receive disparity. this bit is cleared by default. 0 normal operation. 1 disables the running disparity calculation and checking in the receive direction. 3 disable tx dis disable transmit disparity. this bit is cleared by default. 0 normal operation. 1 disables the running disparity calculation and checking in the transmit direction. 4?6 ? reserved 7 an sense auto-negotiation sense enable. this bit is cleared by default. 0 ieee 802.3z clause 37 behavior is desired, which results in the link not completing. 1 allow the auto-negotiation function to sense either a gigabit mac in auto-negotiation bypass mode or an older gigabit mac without auto-negotiation c apability. if sensed, auto-negotiation complete becomes true; however, the page received is lo w, indicating no page was exchanged. management can then act accordingly. 8?9 ? reserved 10 clock select clock select. this bit is cleared by default. 0 allow the tbi to accept dual split-phase 62.5-mhz receive clocks. 1 configure the tbi to accept a 125-mhz receiv e clock from the serdes/phy. the 125-mhz clock must be physically connected to ?pma receive clock 0?. 11 mii mode this bit describes the configuration mode of th e tbi. the user reads a 1 while the tbi is configured in gmii/mii mode (connected to a gmii/mii phy) an d a 0 while configured in tbi mode (connected to a 1000base-x serdes). its value is the inverse of ecntrl[tbim]. 0tbi mode. 1 gmii mode. 12?13 ? reserved 14?15 ? reserved 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-100 freescale semiconductor 14.6.1.1 media-independent interface (mii) this section describes the media-i ndependent interface (mii) intended to be used between the phys and the tsec. figure 14-110 shows the basic components of the mii including the si gnals required to establish tsec module connection with a phy. figure 14-110. tsec-mii connection an mii interface has 18 signals (including the ec_mdc and ec_mdio signals), as defined by the ieee 802.3u standard, for connect ing to an ethernet phy. 14.6.1.2 gigabit media-inde pendent interface (gmii) this section describes the gigabit media-independent interface (gmii) intended to be used between the phys and the tsec. figure 14-111 shows the basic components of the gmii including the signals required to establish the tsec module connection with a phy. transmit error (tsec n _tx_er) transmit data (tsec n _txd[3:0]) transmit enable (tsec n _tx_en) transmit clock (tsec n _tx_clk) collision detect (tsec n _col) receive data (tsec n _rxd[3:0]) receive error (tsec n _rx_er) receive clock (tsec n _rx_clk) receive data valid (tsec n _rx_dv) carrier sense output (tsec n _crs) management data i/o 1 (ec_mdio) management data clock 1 (ec_mdc) tsec 10/100 phy medium 1 the management signals (ec_mdc and ec_mdio) are common to all of the ethernet controllers? connections in the system, assuming that ea ch phy has a different management address. ethernet 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-101 figure 14-111. tsec-gmii connection a gmii interface has 28 signals (tsec n _gtx_clk + ec_gtx_clk125 in cluded), as defined by the ieee 802.3u standard, for connect ing to an ethernet phy. 14.6.1.3 reduced gigabit media- independent inte rface (rgmii) this section describes the reduced gigabit media- independent interface (rgmi i) intended to be used between the phys and the gmii mac. the rgmii is an alternative to the ieee802.3u mii, the ieee802.3z gmii, and the tbi. the rgmii reduces th e number of signals required to interconnect the mac and the phy from a maximum of 28 signals (g mii) to 15 signals (ec_ gtx_clk125 included) in a cost-effective and technology-indepe ndent manner. to accomp lish this objective, th e data paths and all associated control signals are multi plexed using both edges of the cloc k. for gigabit operation, the clocks operate at 125 mhz, and for 10/100 operation, the cl ocks operate at 2.5 or 25 mhz, respectively. figure 14-112 shows the basic components of the gigabit reduced media-independe nt interface and the signals required to establis h the gigabit ethernet c ontrollers? module connecti on with a phy. the rgmii is implemented as defined by the rgm ii specification ve rsion 1.2a 9/22/00. transmit error (tsec n _tx_er) transmit data (tsec n _txd[7:0]) transmit enable (tsec n _tx_en) receive data (tsec n _rxd[7:0]) receive error (tsec n _rx_er) receive clock (tsec n _rx_clk) receive data valid (tsec n _rx_dv) carrier sense output (tsec n _crs) management data i/o 1 (ec_mdio) management data clock 1 (ec_mdc) tsec gigabit phy medium 1 the management signals (ec_mdc and ec_mdio) ar e common to all of the ethernet controllers? connections in the system, assu ming that each phy has a di fferent manageme nt address. gigabit reference clock (ec_gtx_clk125) gigabit transmit clock (tsec n _gtx_clk) ethernet 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-102 freescale semiconductor figure 14-112. tsec-rgmii connection 14.6.1.4 ten-bit interface (tbi) this section describes the ten-bit in terface (tbi) intended to be used between the phys and the tsec to implement a standard serdes interface for opti cal-fiber devices in 1000b ase-sx/lx applications. figure 14-113 shows the basic components of the tbi incl uding the signals required to establish tsec module connection with a phy. rbc0 and rbc1 are differential 62.5- mhz receive clocks. transmit data (tsec n _txd[3:0]/tsec n _txd[7:4]) transmit control (tx_en/f(tx_en,tx_er)) gigabit transmit clock (tsec n _gtx_clk) receive data (tsec n _rxd[3:0]/tsec n _rxd[7:4]) receive control (rx_dv/f(rx_dv,rx_er)) receive clock (tsec n _rx_clk) management data i/o 1 (ec_mdio) management data clock 1 (ec_mdc) tsec medium 1 the management signals (ec_mdc and ec_mdio) are co mmon to all of the gigabit ethernet controllers? module connections in the system, assuming that each phy has a different management address . gigabit reference clock (ec_gtx_clk125) gigabit phy ethernet 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-103 figure 14-113. tsec-tbi connection a tbi interface has 27 signals (ec_gtx_clk125 incl uded) for connecting to an ethernet phy, as defined by ieee 802.3z gmii and tbi standards. 14.6.1.5 reduced ten-bit interface (rtbi) this section describes the reduced ten-bit interface (rtbi) intended to be used between the phys and the tsec to implement a reduced signal count version of a serdes interf ace for optical-fiber devices in 1000base-sx/lx applications. figure 14-114 shows the basic components of the rtbi including the signals required to establish tsec module connection with a phy. transmit data (tsec n _txd[9:0]) gigabit transmit clock (tsec n _gtx_clk) receive data (tsec n _rxd[9:0]) tbi receive clock 0 (tsec n _rx_clk0) tbi receive clock 1 (tsec n _rx_clk1) management data i/o 1 (ec_mdio) management data clock 1 (ec_mdc) tsec gigabit phy medium 1 the management signals (ec_mdc and ec_mdio) are common to all of the ethernet controllers? connections in the system, assuming that eac h phy has a different management address. gigabit reference clock (ec_gtx_clk125) signal detect (sdet) ethernet 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-104 freescale semiconductor figure 14-114. tsec-rtbi connection a rtbi interface has 15 signals (e c_gtx_clk125 included), as defi ned by the rgmii specification version 1.2a 9/22/00, and is intende d to be an alternative to th e ieee 802.3u mii, the ieee 802.3z gmii and the tbi standard for conne cting to an ethernet phy. table 14-110 describes the signal multiplexing for gmii, mii and tbi interfaces. table 14-110. gmii, mii, and tbi signal multiplexing tsec signals frequency [mhz] 125 voltage[v] 3.3/2.5 gmii interface frequency [mhz] 125 voltage[v] 3.3 mii interface frequency [mhz] 25 voltage[v] 3.3 tbi interface frequency [mhz] 62.5 voltag e[v] 3.3 signals (tsec n _) i/o no. of signals signals (tsec n _) i/o no. of signals signals (tsec n _) i/o no. of signals signals (tsec n _) i/o no. of signals gtx_clk o 1 gtx_clk o 1 gtx_clk o 1 tx_clk i 1 tx_clk i 1 tx_clk i 1 rx_clk1 i 1 txd[0] o 1 txd[0] o 1 txd[0] o 1 tcg[0] o 1 txd[1] o 1 txd[1] o 1 txd[1] o 1 tcg[1] o 1 txd[2] o 1 txd[2] o 1 txd[2] o 1 tcg[2] o 1 txd[3] o 1 txd[3] o 1 txd[3] o 1 tcg[3] o 1 txd[4] o 1 txd[4] o 1 tcg[4] o 1 txd[5] o 1 txd[5] o 1 tcg[5] o 1 txd[6] o 1 txd[6] o 1 tcg[6] o 1 txd[7] o 1 txd[7] o 1 tcg[7] o 1 tx_en o 1 tx_en o 1 tx_en o 1 tcg[8] o 1 transmit data (tsec n _txd[4:0]/tsec n _txd[9:5]) gigabit transmit clock (tsec n _gtx_clk) receive data (tsec n _rxd[4:0]/tsec n _rxd[9:5]) receive clock (tsec n _rx_clk) management data i/o 1 (ec_mdio) management data clock 1 (ec_mdc) tsec gigabit phy medium 1 the management signals (ec_mdc and ec_mdio) ar e common to all of the ethernet controllers? connections in the system, as suming that each phy has a different management address. gigabit reference clock (ec_gtx_clk125) ethernet 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-105 table 14-111 describes the signal multiplexi ng for rgmii and rtbi interfaces. tx_er o 1 tx_er o 1 tx_er o 1 tcg[9] o 1 rx_clk i 1 rx_clk i 1 rx_clk i 1 rx_clk0 i 1 rxd[0] i 1 rxd[0] i 1 rxd[0] i 1 rcg[0] i 1 rxd[1] i 1 rxd[1] i 1 rxd[1] i 1 rcg[1] i 1 rxd[2] i 1 rxd[2] i 1 rxd[2] i 1 rcg[2] i 1 rxd[3] i 1 rxd[3] i 1 rxd[3] i 1 rcg[3] i 1 rxd[4] i 1 rxd[4] i 1 rcg[4] i 1 rxd[5] i 1 rxd[5] i 1 rcg[5] i 1 rxd[6] i 1 rxd[6] i 1 rcg[6] i 1 rxd[7] i 1 rxd[7] i 1 rcg[7] i 1 rx_dv i 1 rx_dv i 1 rx_dv i 1 rcg[8] i 1 rx_er i 1 rx_er i 1 rx_er i 1 rcg[9] i 1 col i 1 col i 1 crs i 1 crs i 1 sdet i 1 sum 25 sum 23 sum 16 sum 24 table 14-111. rgmii and rtbi signal multiplexing tsec signals frequency [mhz] 125 voltage[v] 3.3/2.5 rgmii interface frequency [mhz] 125 voltage[v] 2.5 rtbi interface frequency [mhz] 62.5 voltag e[v] 2.5 signals (tsec n _) i/o no. of signals signals (tsec n _) i/o no. of signals signals (tsec n _) i/o no. of signals gtx_clk o 1 gtx_clk o 1 gtx_clk o 1 tx_clk i 1 txd[0] o 1 txd[0]/txd[4] o 1 tcg[0]/tcg[5] o 1 txd[1] o 1 txd[1]/txd[5] o 1 tcg[1]/tcg[6] o 1 txd[2] o 1 txd[2]/txd[6] o 1 tcg[2]/tcg[7] o 1 txd[3] o 1 txd[3]/txd[7] o 1 tcg[3]/tcg[8] o 1 table 14-110. gmii, mii, and tbi signal multiplexing (continued) tsec signals frequency [mhz] 125 voltage[v] 3.3/2.5 gmii interface frequency [mhz] 125 voltage[v] 3.3 mii interface frequency [mhz] 25 voltage[v] 3.3 tbi interface frequency [mhz] 62.5 voltag e[v] 3.3 signals (tsec n _) i/o no. of signals signals (tsec n _) i/o no. of signals signals (tsec n _) i/o no. of signals signals (tsec n _) i/o no. of signals 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-106 freescale semiconductor txd[4] o 1 txd[5] o 1 txd[6] o 1 txd[7] o 1 tx_en o 1 tx_ctl (tx_en/tx_err) o 1 tcg[4]/tcg[9] o 1 tx_er o 1 rx_clk i 1 rx_clk i 1 rx_clk i 1 rxd[0] i 1 rxd[0]/rxd[4] i 1 rcg[0]/rcg[5] i 1 rxd[1] i 1 rxd[1]/rxd[5] i 1 rcg[1]/rcg[6] i 1 rxd[2] i 1 rxd[2]/rxd[6] i 1 rcg[2]/rcg[7] i 1 rxd[3] i 1 rxd[3]/rxd[7] i 1 rcg[3]/rcg[8] i 1 rxd[4] i 1 rxd[5] i 1 rxd[6] i 1 rxd[7] i 1 rx_dv i 1 rx_ctl (rx_dv/rx_err) i 1 rcg[4]/rcg[9] i 1 rx_er i 1 col i 1 crs i 1 sum 25 sum 12 sum 12 table 14-111. rgmii and rtbi signal multiplexing (continued) tsec signals frequency [mhz] 125 voltage[v] 3.3/2.5 rgmii interface frequency [mhz] 125 voltage[v] 2.5 rtbi interface frequency [mhz] 62.5 voltag e[v] 2.5 signals (tsec n _) i/o no. of signals signals (tsec n _) i/o no. of signals signals (tsec n _) i/o no. of signals 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-107 table 14-112 describes the signals shared by all interfaces. 14.6.2 gigabit ethernet channel operation this section describes the operation of the tsec. first, the software initialization sequence is described. next, the software (ethernet driver ) interface for transmitting and re ceiving frames is re viewed. address recognition and hash table algorithm features are also discussed. the section concludes with interrupt handling, inter-packet gap time , and loopback descriptions. 14.6.2.1 initialization sequence this section describes which registers are reset due to a hard or software reset and what registers the user must initialize prior to enabling the tsec. 14.6.2.1.1 hardware controlled initialization a hard reset occurs when the system powers up. all ts ec registers and control logic are reset to their default states after a hard reset has occurred. 14.6.2.1.2 user initialization after the system has undergone a hard reset, software must initialize certain basi c tsec registers. other registers can also be initialized du ring this time, but they are optional and must be determined based on the requirements of the system. the module memory map in table 14-3 lists all the tsec registers. table 14-113 describes the minimum steps for register initialization. table 14-112. shared signals signals i/o no. of signals function ec_mdio i/o 1 management interface i/o ec_mdc o 1 management interface clock ec_gtx_clk125 i 1 reference clock sum 3 table 14-113. steps of minimum register initialization description 1. set, then clear maccfg1 [soft_reset] 2. initialize maccfg2 3. initialize mac station address 4. set up the phy using the mii mgmt interface 5. configure the tbi control to tbi or gmii 6. clear ievent 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-108 freescale semiconductor after the registers are initialized, the user must execu te the following steps in the order described below to bring the tsec into a func tional state (out of reset): 1. for the transmission of ethernet frames, txbds mu st first be built in memo ry, linked together as a ring, and pointed to by the tbase register. a minimum of two buffer de scriptors per ring is required. setting the ring to a size of one caus es the same frame to be transmitted twice. 2. likewise, for the reception of ethernet frames, th e receive queue must be ready, with its rxbd pointed to by the rbase register. both transm it and receive can be gracefully stopped after transmission and reception begins. 3. write to maccfg1 and set the appropriate bits. these need to include rx_en and tx_en. to enable flow control, rx_flow and tx_flow must also be set. 4. clearing dmactrl[gts] triggers the transmission of frame data if the transmitter had been previously stopped. dmactrl[grs] must be cl eared if the receiver had been previously stopped. see 14.5.3.1.7, ?dma control register (dmactrl),? and section 14.6.3.1, ?transmit data buffer descriptor (txbd),? for more information. 14.6.2.2 soft reset and reconfiguring procedure before issuing a soft reset to and/or reconfiguri ng the mac with new parameters, user must properly shutdown the dma and make su re it is in an idle state for the en tire duration. user must gracefully stop the dma by setting both grs and gts bits in the dmactrl register, then wait for both grsc and gtsc bits to be set in the ievent register befo re resetting the mac or cha nging parameters. both grs and gts bits must be cleared before re-enabling the mac to resume the dma. during the mac configuration, if a new set of tx buf fer descriptors are used, the user must load the pointers into the tbase register. likewise if a ne w set of rx buffer descriptors are used, the rbase register must be writte n with the new pointer. following is a procedure to gracef ully reset and reconfigure the mac: 1. set gts bit in dmactrl register 2. poll gtsc bit in ievent re gister until detected as set 3. clear both rx_en and tx_en bits in maccfg1 4. wait for a period of 9.6 kbytes worth of data on the interface (~8 ms worst case). 5. set grs bit in dmactrl register 6. poll grsc bit in ievent re gister until detected as set 7. set soft_reset bit in maccfg1 register 7. initialize imask 8. initialize iaddr n 9. initialize gaddr n 10. initialize rctrl 11. initialize dmactrl table 14-113. steps of minimum register initialization (continued) description 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-109 8. clear soft_reset bit in maccfg1 register 9. load tbase with new txbd pointer 10. load rbase with new rxbd pointer 11. set up other mac registers (maccfg2, maxfrm, etc.) 12. set wwr and wop bits in dmactrl register 13. clear thlt bit in tstat register and qhlt bi t in rstat register by writing 1 to these bits. 14. clear grs/gts bits in dmactrl (do not change other bits) 15. enable tx_en/rx_en in maccfg1 register 14.6.2.3 gigabit ethern et frame transmission the ethernet transmitter requires little core interventi on. after the software driver initializes the system, the tsec begins to poll the first transmit buffer descript or (txbd) in the txbd ring every 512 transmit clocks. if txbd[r] is set, tsec begins moving tr ansmit buffer from memory to its tx fifo. the transmitter takes data from the tx fifo and transmits data to the mac. the mac transmits the data through the gmii interface to the physical media. the transmitter, once initialized, runs until the end-of-frame (eof) condition is detected unless a collision with in the collision window occurs (half-duplex mode) or an a bort condition is encountered. if the user has a frame ready to transmit, a transmit-on- demand function may be em ulated while in polling mode by using the graceful-transmi t-stop feature. first, clear the imask[gtscen] bit to mask the graceful-transmit-stop complete inte rrupt. next set, then immediately clear the dmactrl[gts] bit. clear the resulting ievent[gtsc] bit. finally, th e imask[gtscen] bit may be set once again.there is one internal buffer for out-of-sequence flow contro l frames. while the tsec is between frames, this buffer is polled. the buffer must contain the whole frame. once the tsec is in paused mode, the out-of-sequence buffer descriptor cannot be used to send another flow control frame because the mac regards it as a regular txbd. in half-duplex mode (maccfg2[full duplex] is cleared) th e mac defers transmission if the line is busy (crs asserted). before transmitting, the mac waits fo r carrier sense to become inactive, at which point it then determines if crs remains negated for 60 clocks. if so, transm ission begins after an additional 36 bit times (96 bit times after crs originally became negated). if crs continues to be asserted, the mac follows a specified back-off procedure and tries to retransmit the frame unt il the retry limit is reached. data stored in the tx fifo is re-transmitted in case of a collision. this improves bus usage and latency. the transmitter also monitors for an abort condition and term inates the current frame if an abort condition is encountered. in full-duplex mode the protocol is independent of netw ork activity, and only the transmit inter-frame gap must be enforced. the transmit block also implements full-duplex flow control. if a flow control fr ame is received, the mac does not service the transmitter?s request to send da ta until the pause duration is over. if the mac is currently sending data when a pause frame is received, the mac finishes sending the current frame, then suspends subsequent frames (except a pause frame) unt il the pause duration is ove r. the pause duration is defined by the received pause contro l frame and begins when the frame was first received. in addition, the transmitter supports transmission of flow control frames through tctrl[tfc_pause]. the transmit 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-110 freescale semiconductor pause frame is generated internally based on the pause register that defines the pause value to be sent. note that it is possible to send a pause frame while the pause timer has not expired. the mac automatically appends fcs ( 32-bit crc) bytes to the frame if any of the following values are set: ? txbd[pad/crc] is set in first txbd ? txbd[tc] is set in first txbd ? maccfg2[pad/crc] is set ? maccfg2[crc en] is set following the transmission of the fcs, the ethernet cont roller writes the fr ame status bits into the bd and clears txbd[r]. if the end of the current buffer is r eached and txbd[l] is cleared (a frame is comprised of multiple buffer descriptors), only txbd[r] is cleared. for both half- and full-duplex modes, an interrupt can be issued depending on txbd[i]. the ethernet controller then proceeds to the next txbd in the table. in this way, the core can be interrupted after each frame, after each buffer, or after a sp ecific buffer is sent. if txbd[pad/c rc] is set, the ethernet controller pads any frame shorter than 64 bytes. to pause transmission or rearrange the transmit queue, set dmactrl[gts] . this can help in transmitting expedited data ahead of previously linked buffers or fo r error situations. if gts is set, the tsec transmitter performs a graceful transmit stop. the ethernet controller stops immediately if no transmission is in progress or continues transm ission until the current frame either finish es or terminates with an error. the ievent[gtsc] interrupt occurs once the graceful tr ansmit stop operation is completed. after gts is cleared, the tsec resumes transmission with the next frame. while the tsec is in 10/100 mbps m ode it sends bytes least-significant nibble first and eac h nibble is sent lsb first. while it is in 1-gbps mode it sends bytes lsb first. 14.6.2.4 gigabit ethern et frame reception the tsec ethernet receiver is designed to work wi th little core intervention and can perform address recognition, crc checking, short fr ame checking, and maximum frame- length checking. the receiver can also force frame headers and buffer descriptor s to be allocated into the l2 cache. see section 14.6.4, ?data extraction to the l2 cache,? for additional information. after a hardware reset, the softwa re driver clears the rstat regist er and sets maccfg1[rx_en]. the ethernet receiver is enabled and immediately starts proces sing receive frames. if tsec n _rx_dv is asserted and tsec n _col remains negated, the mac strips a valid preamble/sfd (start of frame delimiter) header and begins proce ssing the frame. if a valid header is not found, the frame is ignored. if the receiver detects the first bytes of a frame, the tsec controller begi ns to perform the frame recognition function through destinat ion address (da) recognition (see section 14.6.2.6, ?frame recognition,? for additional information.). based on this ma tch the frame can be accepted or rejected. once accepted, the tsec processes the fr ame based on user-defined attributes. 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-111 the receiver can also filter frames based on phys ical (individual), group (m ulticast), and broadcast addresses. because ethernet recei ve frame data is not written to memory until the internal frame recognition algorithm is complete, sy stem bus usage is not wasted on frames unwanted by this station. if a frame is accepted, the ethernet controller fetches the receive buffer descriptor (rxbd) from the queue. if rxbd is not being used by softwa re (rxbd[e] is set), th e tsec starts transferring the incoming frame. rxbd[f] is set for the first rxbd us ed for any particul ar receive frame. if the buffer is filled, the tsec c ontroller clears rxbd[e] and, if rxbd [i] is set, generates an interrupt. if the incoming frame is larger than the buffer, the ethernet controller fe tches the next rxbd in the table. if it is empty, the controller continues receiving the re st of the frame. in half-dupl ex mode, if a collision is detected during the frame, no rxbds are used; thus, no collision frames ar e presented to the user except late collisions, whic h indicate lan problems. the rxbd length is determined by the mrbl field in the maximum receive buffer length register (mrbl). the smallest valid value is 64 bytes. during reception, the ethernet controller checks for frames that are too short or too long. after the frame ends (crs is negate d), the receive crc field is checked and written to the data buffer. the data length written to the last rxbd in the ethernet frame is the length of the entire frame, which enables the softwa re to recognize a fr ame-too-long condition. receive frames are not truncated if they exceed maximum frame byt es in the mac?s maximum frame register if maccfg2[huge frame] is set, ye t the babbling receiver error interrupt occurs (ievent[babr] is set) and rxbd[lg] is set. after the receive frame is complete, the ethernet cont roller sets rxbd[l], updates the frame status bits in the rxbd, and clears rxbd[e]. if rxbd [i] is set, the ethernet controller next generates an interrupt (that can be masked) indica ting that a frame was received and is in me mory. the ethernet controller then waits for a new frame. to interrupt reception or rearrange th e receive queue, dmactrl[grs] must be set. if this bit is set, the tsec receiver performs a graceful receive stop. the ethernet controlle r stops immediately if no frames are being received or cont inues receiving until the cu rrent frame either finishes or an error condition occurs. the ievent[grsc] interrupt event is signa lled after the graceful receive stop operation is completed. while in this mode the user can then clear ievent[grsc] and can writ e to registers that are accessible to both the user and the tsec hardware without fear of conflict . after dmactrl[grs] is cleared, the tsec scans the input data stream for the start of a new fr ame (preamble sequence and start of frame delimiter), it resumes receiving, and the first va lid frame received is placed in the next available rxbd. 14.6.2.5 rmon support tsec automatically gathers netw ork statistics required for rmon without needing to receive all addresses. the rmon mib group 1, rmon mib group 2, rmon mib group 3, rmon mib group 9, rmon mib 2, and the 802.3 ethernet mib are supported. for rmon statistics and their corre sponding counters see the memory map. 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-112 freescale semiconductor 14.6.2.6 frame recognition the ethernet controller performs frame recognition using destination address (d a) recognition. a frame can be rejected or accep ted based on the outcome. 14.6.2.6.1 destinati on address recognition the ethernet controller can also pe rform the frame filtering using the tr aditional destinat ion address (da) recognition methods. figure 14-115 is a flowchart for address reco gnition on received frames that is used to explain the concept. in the actual implementation most of the decision points shown in the figure actually occur simultaneously. the ethernet controller compares the destination a ddress field of the receive d frame with the physical address the user programs in th e station address registers (mac stnaddr1 and macstnaddr2). if the da does not match the station a ddress, then the controller perf orms address recognition on multiple individual addresse s using the iaddr n hash table. the user must write ze ros to the hash in order to avoid a hash match, and ones to st ation address in order to avoid individual address matc h, or the user can turn on promiscuous mode. (see section section 14.5.3.4.1, ?receive cont rol register (rctrl).? ) in the group type of address recogni tion, the ethernet contro ller determines whethe r the group address is a broadcast address. if it is a br oadcast, and broadcast addresses are enabled, the frame is accepted. if the group address is not a broadcast address, the us er can perform address recognition on multiple group addresses using the gaddr n hash table. in promiscuous mode, the ethernet controller receives all of the incoming frames regardless of their address. 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-113 figure 14-115. ethernet address recognition flowchart i/g address station address match? i g broadcast address broadcast reject t f hash search use group ta bl e t hash match? t promiscuous? t f f f f t receive frame incoming frame hash search use individual ta b l e discard frame 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-114 freescale semiconductor 14.6.2.6.2 hash table algorithm the hash table process used in th e individual and group hash filtering operates as follows. the ethernet controller maps any 48-bit dest ination address into one of 256 bi ns, represented by the 256 bits in gaddr0?7 or iaddr0?7. the eight high-order bits of a cyclix redundancy check (crc) checksum are used to index into the hash table. th e high-order three bits of this 8-bit field are used to select one of the eight registers in either the individual or group hash ta ble. the low-order five bits select a bit within the 32-bit register. a value of 0 in the high- order three bits selects iaddr0/gaddr0. the same process is used if the ethe rnet controller receives a frame. if the crc check sum selects a bit that is set in the group/individual hash table, the frame is accepted. if 32 group addresse s are stored in the hash table and random group addresses are received, the hash table prevents roughly 224/256 (87.5%) of the group address frames from reaching memory. software mu st further filter those that reach memory to determine if they contain the correct addresses. better performance is achieved by using the group and i ndividual hash tables in combination. for instance, if 32 group and 32 physical a ddresses are stored in their respective hash tables, because 87.5% of all group addresses and 87.5% of all individual address are rejected, then 87.5% of all frames are prevented from reaching memory. the effectiveness of the hash table declines as the number of addresses increase s. for instance, as the number of addresses stored in the 256-bi n hash table increases, the vast ma jority of the hash table bits are set, preventing only a sm all fraction of frames from reaching memory. 14.6.2.6.3 crc computation examples there are many algorithms for calculating the crc va lue of a number. refer to the rfc 3309 standard, which can be found at http://www.f aqs.org/rfcs/rfc3309.html, to comput e the crc value for the purposes of tsec. the rfc 3309 algorithm uses the foll owing polynomial to calculate the crc value: x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x1 + x0 or 0x04c11db7 given a destination mac address of da = 01000cccccc c, the algorithm results in a crc remainder value of 0xa29f4bbc. bit-reversing the low-order byte of the crc value (0xbc) yields: br_crc = 0x3d = 0b00111101 the high-order 3-bits of the new br_c rc value are used to select which 32- bit register (of the 8) to use. this example maps the da to register 1. high-order 3 bits of br _crc: ho_crc = 0b001 = 1 the low-order 5 bits are used to select which bit to set in the given register (with a value of 0 setting 0x8000_0000 and 31 setting 0x0000_0001). therefore, the ex ample da maps to bit 29 of register 1. low-order 5 bits of br_crc: lo_crc = 0b11101 = 29 therefore, gaddr1 is ored with the value 0x0000_0004. 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-115 additional calculated examples follow: example 1: ? destination mac address: da = 01005e000128 ? crc remainder va lue: crc = 0x821d6cd3 ? bit-reversed least-signifi cant byte of crc value: br_crc = 0xcb = 0b11001011 ? high-order 3 bits of br_crc: ho_crc = 0b110 = 6 ? low-order 5 bits of br_crc: lo_crc = 0b01011 = 11 ? gaddr6 = 0x0010_0000 example 2: ? destination mac address: da = 0004f0604f10 ? crc remainder valu e: crc = 0x1f5a66b5 ? bit-reversed least-signifi cant byte of crc value: br_crc = 0xad = 0b10101101 ? high-order 3 bits of br _crc: ho_crc = 0b101 = 5 ? low-order 5 bits of br_crc: lo_crc = 0b01101 = 13 ? gaddr5 = 0x0004_0000 14.6.2.7 flow control because collisions cannot occur in fu ll-duplex mode, gigabit ethernet can operate at the maximum rate. if the rate becomes too fast for a stat ion?s receiver, the station?s transmit ter can send flow-control frames to reduce the rate. flow-control instruct ions are transferred by special fr ames of minimum frame size. the length/type fields of these fr ames have a special value. table 14-114 lists the flow-control frame structure. table 14-114. flow control frame structure size [octets] description value comment 7 preamble 1 sfd start frame delimiter 6 destination address 01-80c2-00-00-01 multicast address reserved for use in mac frames 6 source address 2 length/type 88-08 control frame type 2 mac opcode 00-01 pause command 2 mac parameter pause time as defined by the ptv[pt] field. the pause period is measured in pause_quanta, a speed-independent constant of 512 bit-times (unlike slot time). the most-significant octet is sent first. 2 extended mac parameter extended pause control parameter as defined by the ptv[pte] field. the most-significant octet is sent first. 40 reserved ? 4 fcs frame check sequence (crc) 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-116 freescale semiconductor if flow-control mode is enabled (maccfg1[rx_flow] is set) and the receiver identifies a pause-flow control frame, transmission stops fo r the time specified in the contro l frame. during this pause, only a control frame can be sent (tctrl[tfc_pause] is set). normal transmission resumes after the pause timer stops counting. if another paus e-control frame is received during the pause, the period changes to the new value received. 14.6.2.8 interrupt handling the following describes what usually oc curs within a tsec interrupt handler: ? if an interrupt occurs, read ievent to determine interrupt sources. ievent bits to be handled in this interrupt handler are norm ally cleared at this time. ? process the txbds to reuse them if the ievent[txb or txf] were set. if the transmit speed is fast or the interrupt de lay is long, more than one transmit buf fer may have been sent by the tsec; thus, it is important to check more than just one txbd during the inte rrupt handler. one common practice is to process all txbds in the interr upt handler until one is found with r set. see table 14-115 . ? obtain data from the rxbd if ievent[rxc,rxb or rxf] is set. if the receive speed is fast or the interrupt delay is long, the ts ec may have received more than one rxbd; thus, it is important to check more than just one rx bd during interrupt handling. typica lly, all rxbds in the interrupt handler are processed until one is found with e set. because the tsec pr e-fetches bds, the bd table must be big enough so th at there is always another empty bd to pre-fetch. see table 14-116 . ? clear any set halt bits in tstat and rstat registers, or dmactrl[gts] and dmactrl[grs]. ? continue normal execution. table 14-115. non-error transmit interrupts interrupt description action taken by tsec gtsc graceful transmit stop complete : transmitter is put into a pause state after completion of the frame currently being transmitted. none txc transmit control: instead of the ne xt transmit frame, a control frame was sent. none txb transmit buffer: a transmit buffer descriptor, that is not the last one in the frame, was updated. programmable ?write with response? txbd to memory before se tting ievent[txb]. txf transmit frame: a frame was transmitted and the last transmit buffer descriptor (txbd) of that frame was updated. programmable ?write with response? to memory on the last txbd befo re setting ievent[txf]. 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-117 14.6.2.8.1 interrupt coalescing interrupt coalescing offers the user the ability to cont our the behavior of the tsec with regard to frame interrupts. separate but identical mechanisms exis t for handling both transm itted frames and received frames. while interrupt coalescing is enabled a transm it or receive frame inte rrupt (resulting from the interrupt bit (i) of the buffer descriptor in questi on and appropriately-enabled by the imask register) is raised either when a counter thre shold-defined number of frames is received/transmitted or the timer threshold-defined period of time ha s lapsed, whichever occurs first. 14.6.2.8.2 interrupt coalesci ng by frame count threshold to avoid interrupt bandwidth congestion due to freque nt, consecutive interrupts, the user may enable and configure interrupt coalescing to deliberately group frame interrupt s, reducing the total number of interrupts raised. the number of frames received or tr ansmitted prior to an interrupt being raised is determined by the frame threshold field (icfct) in the appropriate interrupt coalescing configuration register (rxic or txic). the fr ame threshold field may be assigned a value between 1 and 255. a value of 0 results in boundedl y undefined behavior. note that a value of 1 func tionally defeats th e advantages of interrupt coalescing since the frame threshold is reac hed with each frame receiv ed or transmitted. once the number of frames transmitted or received reaches the threshold limit, an interrupt is raised (if the interrupt bit of the frame buffer desc riptor(s) is set and if appropriately-enabled in the imask register), the threshold counter is reset, and then continues counting frames while the interrupt is active. the threshold counter is also reset if an interrupt is raised subject to the corresponding threshold timer. 14.6.2.8.3 interrupt coale scing by timer threshold to avoid stale frame interrupts, the user may al so assign a timer threshold, beyond which any frame interrupts not yet raised are forced (i f the interrupt bit of the frame buffer descriptor(s) is set and if enabled in the imask register). the timer threshold fields of the receive and transmit interrupt coalescing configuration registers (rxic[ic tt] and txic[ictt]) are defined in units equivalent to 64 tsec interface clocks. that is , one timer threshold unit is 26.5 s, 2.56 s , or 512 ns, corresponding to interface modes 10 mbps, 100 mbps, or 1 gbps, respectively. table 14-116. non-error receive interrupts interrupt description action taken by tsec grsc graceful receive stop complete: receiver is put into a pause state after completion of the frame currently being received. none rxc receive control: a control frame was received. as soon as the transmitter finishes sending the current frame, a pause operation is performed lasting for the dura tion specified in the received pause control frame and beginning when the frame was first received. none rxb receive buffer: a receive buffer descriptor, that is not the last one of the frame, was updated. programmable ?write with response? rxbd to memory before se tting ievent[rxb]. rxf receive frame: a frame was received and the last receive buffer descriptor (rxbd) of that frame was updated. programmable ?write with response? to memory on the last rxbd befor e setting ievent[rxf]. 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-118 freescale semiconductor after transmitting a frame (with txbd[i] set, causing ievent[txf] to be set), the transmit interrupt coalescing threshold timer begins counting. when the timer threshol d has been reached an interrupt is raised if the interrupt bit of the buffer descriptor is se t and imask[txfen] is set. after receiving a frame (w ith rxbd[i] set, causing ievent[rxf] to be set), the receive interrupt coalescing threshold timer begins counting. when the timer threshol d has been reached an interrupt is raised if the interrupt bit of the buffer descriptor is se t and imask[rxfen] is set. the interrupt coalescing timer thre sholds (transmit and receive, opera ting independently) may be values ranging from 1 to 65535. a value of 0 is illegal and resu lts in behavior identical to that when interrupt coalescing is disabled (cor responding rxic[icen] or txic[icen] is cleared). table 14-117 specifies the range of possible timing thresholds subject to the interface frequency and the value of rxic[ictt] or txic[ictt]. the transmit or receive time r threshold counter is rese t when a corresponding interrupt is raised and begins counting again upon deassertion of that interrupt and once ie vent[txf or rxf] is set. 14.6.2.9 inter-packet gap time if a station must tr ansmit, it waits until the lan becomes silent for a specifie d period (inter-packet gap). after a station begins sending, it c ontinually checks for collisions on the lan. if a collision is detected, the station forces a jam signal (all ones) on its frame and stops transm itting. collisions us ually occur close to the beginning of a packet. the station then waits a ra ndom time period (back-off ) before attempting to send again. after the back-off completes, the statio n waits for silence on the lan and then begins retransmission on the lan. this process is called a retry. if the packet is not successfully sent within a specified number of retries, an error is indicated. the minimum inter-packet gap time for back-to-ba ck transmission is 96 serial clocks. the receiver receives back-to-back packets with this minimum spacing. in addition, after waiting a re quired number of clocks (based on the back-off algorithm), the transm itter waits for carrier sense to be negated before retransmitting the packet. retransmissi on begins 36 serial clocks after carrier sense is negated for at least 60 serial clocks. 14.6.2.10 internal and external loopback setting maccfg1[loop back] causes the mac transmit outputs to be looped back to the mac receive inputs. clearing this bit results in normal operation. this bit is cleared by default. table 14-117. interrupt coalescing timing threshold ranges tsec interface format and frequency interrupt coalescing threshold time minimum (ictt = 1) maximum (ictt = 65535) 10base-t at 2.5 mhz 25.6 s 1.678 s 100base-t at 25 mhz 2.56 s 167.8 ms 1000base-t at 125 mhz 512 ns 33.55 ms 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-119 14.6.2.11 error-handling procedure the ethernet controller reports fra me reception and transmission error conditions using the channel bds, the error counters, and the ievent register. programming note: when the tsec en counters a halt condition (tstat[thl t] is set), it stops processing the frame at the current txbd. the tsec relies on the user to manage the buffer descriptor pointer, tbptr, or the buffer descriptor queue before resumi ng transmissions. once the ts ec resumes, it fetches the txbd pointed to by tbptr. transmission errors are described in table 14-118 . reception errors are described in table 14-119 . table 14-118. transmission errors error response transmitter underrun the controller sends 32 bits that ensure a crc error, te rminates buffer transmission, sets txbd[un], closes the buffer, sets ievent[xf un] and ievent[txe]. the controller re sumes transmission after tstat[thlt] is cleared (and dmactrl[gts] is cleared). retransmission attempts limit expired the controller terminates buffer transmission, sets txbd[rl], closes the buffer, sets ievent[crl/xda] and ievent[txe]. transmission resumes after tstat[thlt] is cleared ( and dmactrl[gts] is cleared). excessive defer abort the controller terminates buffer transmission, sets txbd[def], closes the bu ffer, sets ievent[crc/xda], and ievent[txe]. transmission resume s after tstat[thlt] is cleared. late collision the controller terminates buffer transmission, sets txbd[lc], closes the buffer, sets ievent[lc] and ievent[txe]. the controller resumes transmission after tstat[thlt ] is cleared (and dmactrl[gts] is cleared). memory read error a system bus error occurred during a dma transactio n. the controller sets ievent[eberr], dma stops sending data to the fifo which causes an u nderrun error but ievent[xfun] is not set. the tstat[thlt] is set. transmits are continued once tstat[thlt] is cleared. babbling transmit error a frame is transmitted which exceeds the mac?s maximu m frame length and maccfg2[huge frame] is a 0. the controller sets ievent[babt] and continues without interruption. txbd[txtrunc] is set in the last txbd (txbd[l] is set) of the frame. table 14-119. reception errors error description overrun error the ethernet controller maintains an internal fifo buffer for receiving data. if a receiver fifo buffer overrun occurs, the controller sets rxbd[ov] , sets rxbd[l], closes the buffer, and sets ievent[rxf], the receiver then enters hunt mode (seeking start of a new frame). busy error a frame is received and discarded due to a lack of buffers. the controller sets ievent[bsy]. in addition, the rstat[qhlt] bit is set. the halted queue resumes re ception once the user clears the rstat[qhlt] bit. non-octet error (dribbling bits) the ethernet controller handles a nibble of dribbling bits if the receive frame terminates as non-octet aligned and it checks the crc of the frame on the last octet b oundary. if there is a crc error, the frame non-octet aligned (rxbd[no]) error is reported, ievent[rxf] is set, and the alignment error counter increments. the tsec relies on the statistics collector block to increment the receive alignment erro r counter (raln). if there is no crc error, no error is reported. 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-120 freescale semiconductor 14.6.3 buffer descriptors the tsec buffer descriptor (bd) is modeled after the mpc8260 fast ethe rnet controller bd for ease of reuse. drawing from the mpc8260 fec bd programmi ng model, the tsec descriptor base registers point to the beginning of bd rings. the 8-byte data bd format is similar to the mpc8260 bd model. data buffers are used in the transmissi on and reception of et hernet frames (see figure 14-116 ). data bds encapsulate all information necessary for the tsec to transmit or receive an et hernet frame. within each data bd there is a status field, a data length field, and a data pointer . the bd completely describes an ethernet packet by centralizing status information for the data packet in the status field of the bd and by containing a data bd pointer to the location of the data buffer. software is responsible for setting up the bds in memory. because of pre-fe tching, a minimum of two buffer desc riptors per ring are required. this applies to both the transmit and the receive descript or rings. software also must have the data pointer pointing to memory. within the status field, there exists an ownership bit which defines the current state of the buffer (pointed to by the data pointer). other bits in the status field of th e buffer descriptor are used to communicate status/control information be tween the tsec and the software driver. the status field of the bd is 16-bit field, as is th e length field. the data buffer pointer is a 32-bit field. therefore, the bds should be accesse d with the following c structure: typedef unsigned short uint_16; /* choose 16-bit native type */ typedef unsigned int uint_32; /* choose 32-bit native type */ typedef struct bd_struct { uint_16 flags; uint_16 length; uint_32 bufptr; }; because there is no next bd pointer in the transmit/receive bd (see figure 14-117 ), all bds must reside sequentially in memory. the tsec increments the cu rrent bd location appropriately to the next bd location to be processed. there is a wrap bit in the last bd that in forms the tsec to loopback to the beginning of the bd chain. software must initia lize tbase and rbase that point to the beginning transmit and receive bds for tsec. crc error if a crc error occurs, the controller sets rxbd[c r], closes the buffer, and sets ievent[rxf]. this tsec relies on the statistics collector block to record the event. after receiving a frame with a crc error, the receiver then enters hunt mode. memory read error a system bus error occurred during a dma transaction. the controller sets ievent[eberr] and discards the frame . in addition the rstat[qhlt] bit is set. the halted queue resumes reception once the rstat[qhlt] bit is cleared. babbling receive error a frame is received that exceeds the mac?s maximu m frame length. the contro ller sets ievent[babr] and continues table 14-119. reception errors (continued) error description 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-121 figure 14-116. example of tsec memory structure for bd figure 14-117. buffer descriptor ring 14.6.3.1 transmit data buffer descriptor (txbd) data is presented to the tsec for transmission by arranging it in memory buffers referenced by the txbds. in the txbd the user initializes the r, pad/ crc, w, l, and tc bits and the length (in bytes) in the first word, and the buffer pointer in the second word. status & control data length buffer pointer status & control data length buffer pointer rx buffer descriptors tx buffer descriptors rxbd ta b l e txbd ta b l e txbd table pointer rxbd table pointer (tbase) (rbase) memory map system memory tx buffer rx buffer beginning bd pointer 1 3 0 2 4 w = 1 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-122 freescale semiconductor the tsec clears the r bit in the first word of the bd after it finishes using the data buffer. the transfer status bits are then update d. additional transmit frame status can be found in stat istic counters in the mib block. figure 14-118 shows the txbd. the txbd fields are detailed in table 14-120 . 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 offset + 0 r pad/crc w i l tc def to1 hfe/lc rl rc un txtrunc offset + 2 data length offset + 4 tx data buffer pointer offset + 6 figure 14-118. transmit buffer descriptor table 14-120. transmit data buffer descriptor (txbd) field descriptions offset bits name description offset + 0 0 r ready. written by tsec and user. 0 the data buffer associated with this bd is not ready for transmission. the user is free to manipulate this bd or its associated data buff er. the tsec clears this bit after the buffer is transmitted or after an erro r condition is encountered. 1 the data buffer, which is prepared for transmission by the user, was not transmitted or is currently being transmitted. no fields of this bd may be written by the user once this bit is set. offset + 0 1 pad/crc pad/crc. padding and crc attachment fo r frames. (valid only while it is set in the first bd and maccfg2[pad/crc] is cleared.) if maccfg2 [pad/crc] is set, this bit is ignored. 0 do not add padding to short frames. no crc is appended unless txbd[tc] is set. 1 add pad/crcs to frames. pad bytes are insert ed until the length of the transmitted frame equals 64 bytes. unlike the mpc8260 which pads up to minflr value, tsec pads always up to the ieee minimum frame length of 64 bytes. crc is always appended to frames. offset + 0 2 w wrap. written by user. 0 the next buffer descriptor is found in the consecutive location. 1 the next buffer descriptor is found at the location defined in tbase. offset + 0 3 i interrupt. written by user. 0 no interrupt is generated after this buffer is serviced. 1 ievent[txb] or ievent[txf] are set after this buffer is serviced. these bits can cause an interrupt if they are ena bled (that is, ievent[txben] or ievent[txfen] are set). offset + 0 4 l last in frame. written by user. 0 the buffer is not the last in the transmit frame. 1 the buffer is the last in the transmit frame. offset + 0 5 tc tx crc. written by user. (valid only while it is set in first bd and txbd[pad/crc] is cleared and maccfg2[pad/crc] is cleared and maccfg2[crc en] is cleared.) if maccfg2[pad/crc] is set or maccfg2[crc en] is set, this bit is ignored. 0 end transmission immediately after the last data byte with no hardware generated crc appended, unless txbd[pad/crc] is set. 1 transmit the crc sequence after the last data byte. 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-123 14.6.3.2 receive buffer descriptor (rxbd) in the rxbd the user initializes the e, i, and w bits in the first word and the pointer in second word. if the data buffer is used, the tsec modifies the e, l, f, m, bc, mc, lg, no, sh, cr, ov, and tr bits and writes the length of the used porti on of the buffer in the first word. the m, bc, mc, lg, no, sh, cr, ov, offset + 0 6 def defer indication. hardware updates this bit if an excessive defer condition occurs. 0 this frame was not deferred. 1 if hafdup[excess_defer] = 1, this frame di d not have a collision before it was sent but it was sent late because of deferri ng. if hafdup[excess_defer] = 0, this frame was aborted and not sent. offset + 0 7 to1 transmit software ownership. this read/ write bit may be utilized by software, as necessary. its state does not affect the hardware nor is it affected by the hardware. offset + 0 8 hfe/lc huge frame enable (writt en by user)/late collision (written by tsec) huge frame enable. written by user. valid only while it is set in first bd and the maccfg2[huge frame] is cleared. if maccfg2[huge frame] is set, this bit is ignored. 0 truncate transmit frame if its length is greater than the mac?s maximum frame length register. 1 do not truncate the transmit frame. late collision. written by tsec. 0 no late collision. 1 a collision occurred after 64 bytes are sent. the tsec terminates the transmission and updates lc. offset + 0 9 rl retransmission limit. written by tsec. 0 transmission before maximum retry limit is hit. 1 the transmitter failed (max. retry limit + 1) attempts to successfully send a message due to repeated collisions. the tsec terminates the transmission and updates rl. offset + 0 10?13 rc retry count. written by tsec. 0 the frame is sent correctly the first time or if rl is set then the retry limit has been reached x one or more attempts were needed to send t he transmit frame. if this field is 15, then 15 or more retries were needed. the ethernet controller updates rc after sending the buffer. offset + 0 14 un underrun. written by tsec. 0 no underrun encountered (data was retrieved from external memory in time to send a complete frame). 1 the ethernet controller encountered a transmitter underrun condition while sending the associated buffer. the tsec terminates the transmission and updates un. offset + 0 15 txtrunc tx truncation. set in the last tx bd (txbd[l] is set) when ievent[babt] occurs for the frame. offset + 2 0?15 data length data length is the number of octets the tsec tr ansmits from this bd?s data buffer. it is never modified by the tsec. this fiel d must be greater than zero. offset + 4 0?31 tx data buffer pointer the transmit buffer pointer contains the addre ss of the associated data buffer. there are no alignment requirements for this address. table 14-120. transmit data buffer descriptor (txbd) field descriptions (continued) offset bits name description 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-124 freescale semiconductor and tr bits in the first word of th e buffer descriptor are onl y modified by the tsec if the l bit is set. the first word of the rxbd contains control a nd status bits. its format is detailed in figure 14-119 . table 14-121 describes the fields of the rxbd. 0123456789101112131415 offset + 0 e ro1 w i l f 0 m bc mc lg no sh cr ov tr offset + 2 data length offset + 4 rx data buffer pointer offset + 6 figure 14-119. receive buffer descriptor table 14-121. receive buffer descriptor field descriptions offset bits name description offset + 0 0 e empty. written by tsec (when cleared) and by user (when set). 0 the data buffer associated with this bd is filled with received data, or data reception is aborted due to an error condition. the status and length fields have been updated as required. 1 the data buffer associated with this bd is empty, or reception is currently in progress. offset + 0 1 ro1 receive software ownership bit. reserv ed for use by software. this read/write bit is not modified by hardware, nor does its value affect hardware. offset + 0 2 w wrap. written by user. 0 the next buffer descriptor is found in the consecutive location. 1 the next buffer descriptor is found at the location defined in rbase. offset + 0 3 i interrupt. written by user. 0 no interrupt is generated after this buffer is serviced. 1 ievent[rxb] or ievent[ rxf] are set after this buffer is serviced. this bit can cause an interrupt if enabled (imask[rxben] is set or im ask[rxfen] is set). if the user wants to be interrupted only if rxf occurs, then the user must disable rxb (imask[rxben] is cleared) and enable rxf (im ask[rxfen] is set). offset + 0 4 l last in frame. written by tsec. 0 the buffer is not the last in a frame. 1 the buffer is the last in a frame. offset + 0 5 f first in frame. written by tsec. 0 the buffer is not the first in a frame. 1 the buffer is the first in a frame. offset + 0 6 ? reserved offset + 0 7 m miss. written by tsec. (this bit is valid only if the l-bit is set and tsec is in promiscuous mode.) this bit is set by the tsec for frames that were accepted in promiscuous mode, but were flagged as a ?miss? by the internal address recognition; thus, while in promiscuous mode, the user can use the m-bit to quickly determine whether the frame was dest ined to this station. 0 the frame was received because of an address recognition hit. 1 the frame was received because of promiscuous mode. offset + 0 8 bc broadcast. written by tsec. (only valid if l is set.) is set if the da is broadcast (ff-ff-ff-ff-ff-ff). offset + 0 9 mc multicast. written by tsec. (only valid if l is set.) is set if the da is multicast and not bc. 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-125 14.6.4 data extraction to the l2 cache some applications require the ability to identify sele cted portions of data with in a frame?s data payload. this process is called extraction; although, the data is not truly removed. rather th an literally extracting a section of the data and copying it into a new memory location, the data is placed in the l2 cache. this allows the processor to qui ckly access critical frame information as soon as the processo r is ready without having to first fetch the data from main memory. this results in substantial im provement in throughput and hence reduction in latency. extraction functionality is controlled and configured with attr and attreli. see section 14.5.3.9.1, ?attribute register (attr),? and section 14.5.3.9.2, ?attribute extract lengt h and extract i ndex register (attreli),? for specific register information. offset + 0 10 lg rx frame length violatio n. written by tsec. (only valid if l is set.) a frame length greater than maximum frame length was recognized while maccfg2[huge frame] was set. note, if maccfg2[huge frame] is cleared, the frame is truncated to the value programmed in the maximum frame length register. offset + 0 11 no rx non-octet aligned frame. written by tsec . (only valid if l is set.) a frame that contained a number of bits not divisible by eight was received. offset + 0 12 sh short frame. written by tsec. (only vali d if l is set.) a frame length that was less than the minimum length defined for this channel (minflr) was recognized, provided rctrl[rsf] is set. offset + 0 13 cr rx crc error. written by tsec. (only vali d if l is set.) this frame contains a crc error and is an integral number of octets in length.this bit is also set if a receive code group error is detected. offset + 0 14 ov overrun. written by tsec. (only valid if l is set.) a receive fifo overrun occurred during frame reception. if this bit is set, the other stat us bits, m, lg, no, sh, and cr lose their normal meaning and are zero. offset + 0 15 tr truncation. written by tsec. (only valid if l is set.) is set if the receive frame is truncated. this can happen if a frame length greater than maximum frame length was received and the maccfg2[huge frame] is cleared. if this bit is set, the frame must be discarded and the other error bits must be ignored as they may be incorrect. offset + 2 0?15 data length data length. written by tsec. da ta length is the number of octets written by the tsec into this bd?s data buffer if l is cleared (the val ue is equal to mrbl), or the length of the frame including crc, if l is set. offset + 4 0?31 rx data buffer pointer receive buffer pointer. written by user. the receive buffer pointer, which always points to the first location of the associated data buffer, must be 64-byte aligned. the buffer must reside in memory external to the tsec. table 14-121. receive buffer descriptor field descriptions (continued) offset bits name description 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-126 freescale semiconductor 14.7 initialization/application information 14.7.1 interface mode configuration this section describes how to configure the tsec in different supported interf ace modes. these include mii, gmii, tbi, rgmii, rtbi. the pinout, the data regi sters that must be initialized, as well as speed selection options ar e described. the ecntrl[tbim] and ecnt rl[rpm] bits are written, assuming the part was not pin-configured at in itialization to the correct mode. 14.7.1.1 mii interface mode table 14-122 describes the signal configurati ons required for mii interface mode. table 14-122. mii interface mode signal configuration tsec signals frequency [mhz] 125 voltage[v] 3.3/2.5 mii interface frequency [mhz] 25/2.5 voltage[v] 3.3 signals i/o no. of signals signals i/o no. of signals gtx_clk o 1 leave unconnected o tx_clk i 1 tx_clk i 1 txd[0] o 1 txd[0] o 1 txd[1] o 1 txd[1] o 1 txd[2] o 1 txd[2] o 1 txd[3] o 1 txd[3] o 1 txd[4] o 1 leave unconnected o txd[5] o 1 leave unconnected o txd[6] o 1 leave unconnected o txd[7] o 1 leave unconnected o tx_en o 1 tx_en o 1 tx_er o 1 tx_er o 1 rx_clk i 1 rx_clk i 1 rxd[0] i 1 rxd[0] i 1 rxd[1] i 1 rxd[1] i 1 rxd[2] i 1 rxd[2] i 1 rxd[3] i 1 rxd[3] i 1 rxd[4] i 1 not used i rxd[5] i 1 not used i rxd[6] i 1 not used i rxd[7] i 1 not used i rx_dv i 1 rx_dv i 1 rx_er i 1 rx_er i 1 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-127 table 14-123 describes the shared signa ls of the mii interface. table 14-124 describes the register initiali zations required to r econfigure the phy to mii mode following initial auto-negotiation. col i 1 col i 1 crs i 1 crs i 1 sum 25 sum 16 table 14-123. shared mii signals tsec signals i/o no. of signals mii signals i/o no. of signals function ec_mdio i/o 1 ec_mdio i/o 1 management interface i/o ec_mdc o 1 ec_mdc o 1 management interface clock ec_gtx_clk125 i 1 not used i 0 reference clock sum 3 sum 2 table 14-124. mii mode register initialization steps have the tsec n _gtx_clk configuration signal pulled low for g/mii mode. set soft_reset, maccfg1[1000_0000_0000_0000_0000_0000_0000_0000] clear soft_reset, maccfg1[0000_0000_0000_0000_0000_0000_0000_0000] initialize maccfg2, for mii, half-duplex operation. set i/f mode bit, maccfg2[0000_0000_0000_0000_0111_0001_0000_0100] (this example has full duplex = 0, pr eamble count = 7, pad/crc append = 1) initialize ecntrl, ecntrl[0000_0000_0000_0000_0001_0000_0000_0000] (this example has statistics enable = 1) initialize mac station address, macstnaddr2[0110_0000_0000_0010_0000_0000_0000_0000] set station address to 02_60_8c_87_65_43, for example. (note that phy configuration register addresse s are not necessarily consistent in all phys.) initialize mac station address, macstnaddr1[0100_0011_0110_0101_1000_0111_1000_1100] set station address to 02_60_8c_87_65_43, for example. (note that phy configuration register addresse s are not necessarily consistent in all phys.) table 14-122. mii interface mode signal configuration (continued) tsec signals frequency [mhz] 125 voltage[v] 3.3/2.5 mii interface frequency [mhz] 25/2.5 voltage[v] 3.3 signals i/o no. of signals signals i/o no. of signals 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-128 freescale semiconductor assign a physical address to the tbi so as to not conflict with the external phy physical address, tbipa[0000_0000_0000_0000_0000_0000_0000_0101] set to 05, for example. (note that phy configuration register addresse s are not necessarily consistent in all phys.) reset the management interface. miimcfg[1000_0000_0000_0000_0000_0000_0000_0000] setup the mii mgmt clock speed, miimcfg[0000_0000_0000_0000_000_0000_0000_0101] set source clock divide by 14, for example, to insure that ec_mdc clock speed is approximately 2.5 mhz. read mii mgmt indicator register and check for busy = 0, miimind ---> [0000_0000_0000_0000_0000_0000_0000_0000] this indicates that the tsec mii mgmt bus is idle. setup the mii mgmt for a write cycle to the external phy auxiliary control and status register to configure the phy through the management interface (overrides c onfiguration signals of the phy). miimadd[0000_0000_0000_0000_0000_0000_0001_1100] perform an mii mgmt write cycle to the external phy writing to mii mgmt control with 16-bit dat a intended for the external phy register, miimcon[0000_0000_0000_0000_0000_0000_0000_0100] check to see if mii mgmt write is complete read mii mgmt indicator register and check for busy = 0, miimind ---> [0000_0000_0000_0000_0000_0000_0000_0000] this indicates that the write cycle was completed. setup the mii mgmt for a write cycle to the external phy extended phy control register 1 to set up the interface mode selection . miimadd[0000_0000_0000_0000_0000_0000_0001_0111] perform an mii mgmt write cycle to the external phy. write to mii mgmt control with 16-bit data intended for the external phy register, miimcon[0000_0000_0000_0000_0000_0000_0000_0000] check to see if mii mgmt write is complete. read mii mgmt indicator register and check for busy = 0, miimind ---> [0000_0000_0000_0000_0000_0000_0000_0000] this indicates that the write cycle was completed. setup the mii mgmt for a write cycle to the external phy mo de control register to set up the interface mode selection. miimadd[0000_0000_0000_0000_0000_0000_0000_0000] perform an mii mgmt write cycle to the external phy. write to mii mgmt control with 16-bit data intended for the external phy register, miimcon[0000_0000_0000_0000_00uu_00uu_0u00_0000] where u is user defined based on desired configuration. check to see if mii mgmt write is complete read mii mgmt indicator register and check for busy = 0, miimind ---> [0000_0000_0000_0000_0000_0000_0000_0000] this indicates that the write cycle was completed. if auto-negotiation was enabled in the phy, check to see if phy has completed auto-negotiation. setup the mii mgmt for a read cycle to phy mii mgmt r egister (write the phy addr ess and register address), miimadd[0000_0000_0000_0000_0000_0000_0000_0001] the phy status register is at address 0x1 and in this case the phy address is 0x00. table 14-124. mii mode register initialization steps (continued) 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-129 14.7.1.2 gmii interface mode table 14-125 describes the signal configurations required for gmii interface mode. perform an mii mgmt read cycle of status register. clear miimcom[read cycle]. set miimcom[read cycle]. (uses the phy address (0) and register address (1) placed in miimadd register), when miimind[busy] = 0, read the miimstat register and check bit 10 (an done and link is up) miimstat ---> [0000_0000_0000_0000_0000_000_0010_0100] other information about the link is also retu rned.(extend status, no pre, remote faul t, an ability, link status, extend ability ) check auto-negotiation attributes in the phy as necessary. clear ievent register, ievent[0000_0000_0000_0000_0000_0000_0000_0000] initialize imask, (optional) imask[0000_0000_0000_0000_0000_0000_0000_0000] initialize iaddr n, (optional) iaddr n [0000_0000_0000_0000_0000_0000_0000_0000] initialize gaddr n, (optional) gaddr n [0000_0000_0000_0000_0000_0000_0000_0000] initialize rctrl, (optional) rctrl[0000_0000_0000_0000_0000_0000_0000_0000] initialize dmactrl, (optional) dmactrl[0000_0000_0000_0000_0000_0000_0000_0000] initialize fifo_pause_ctrl, fifo_pause_ctrl[0000_0000_0000_0000_0000_0000_0000_0010] initialize (empty) transmit descriptor ring and fill buffers with data. initialize tbase, tbase[llll_llll_llll_llll_llll_llll_llll_l000] initialize (empty) receive descript or ring and fill with empty buffers. initialize rbase, rbase[llll_llll_llll_llll_llll_llll_llll_l000] enable rx and tx, maccfg1[0000_0000_0000_0000_0000_0000_0000_0101] table 14-125. gmii interface mode signal configuration tsec signals frequency [mhz] 125 voltage[v] 3.3/2.5 gmii interface frequency [mhz] 125 voltage[v] 3.3 signals i/o no. of signals signals i/o no. of signals gtx_clk o 1 gtx_clk o 1 tx_clk i 1 txd[0] o 1 txd[0] o 1 txd[1] o 1 txd[1] o 1 table 14-124. mii mode register initialization steps (continued) 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-130 freescale semiconductor table 14-126 describes the shared signa ls of the gmii interface. txd[2] o 1 txd[2] o 1 txd[3] o 1 txd[3] o 1 txd[4] o 1 txd[4] o 1 txd[5] o 1 txd[5] o 1 txd[6] o 1 txd[6] o 1 txd[7] o 1 txd[7] o 1 tx_en o 1 tx_en o 1 tx_er o 1 tx_er o 1 rx_clk i 1 rx_clk i 1 rxd[0] i 1 rxd[0] i 1 rxd[1] i 1 rxd[1] i 1 rxd[2] i 1 rxd[2] i 1 rxd[3] i 1 rxd[3] i 1 rxd[4] i 1 rxd[4] i 1 rxd[5] i 1 rxd[5] i 1 rxd[6] i 1 rxd[6] i 1 rxd[7] i 1 rxd[7] i 1 rx_dv i 1 rx_dv i 1 rx_er i 1 rx_er i 1 col i 1 crs i 1 sum 25 sum 22 table 14-126. shared gmii signals tsec signals i/o no. of signals gmii signals i/o no. of signals function ec_mdio i/o 1 ec_mdio i/o 1 management interface i/o ec_mdc o 1 ec_mdc o 1 management interface clock ec_gtx_clk125 i 1 ec_gtx_clk125 i 1 reference clock sum 3 sum 3 table 14-125. gmii interface mode signal configuration (continued) tsec signals frequency [mhz] 125 voltage[v] 3.3/2.5 gmii interface frequency [mhz] 125 voltage[v] 3.3 signals i/o no. of signals signals i/o no. of signals 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-131 table 14-127 describes the register init ializations required to reconf igure the phy to gmii mode following initial auto-negotiation. table 14-127. gmii mode register initialization steps have the tsec n _gtx_clk configuration signal pulled low for g/mii mode. set soft_reset, maccfg1[1000_0000_0000_0000_0000_0000_0000_0000] clear soft_reset, maccfg1[0000_0000_0000_0000_0000_0000_0000_0000] initialize maccfg2, for gmii, full-duplex operation. set i/f mode bit. maccfg2[0000_0000_0000_0000_0111_0010_0000_0101] (this example has full duplex = 1, pr eamble count = 7, pad/crc append = 1) initialize ecntrl, ecntrl[0000_0000_0000_0000_0001_0000_0000_0000] (this example has statistics enable = 1) initialize mac station address, macstnaddr2[0110_0000_0000_0010_0000_0000_0000_0000] set station address to 02_60_8c_87_65_43, for example. (note that phy configuration register addresse s are not necessarily consistent in all phys.) initialize mac station address, macstnaddr1[0100_0011_0110_0101_1000_0111_1000_1100] set station address to 02_60_8c_87_65_43, for example. (note that phy configuration register addresse s are not necessarily consistent in all phys.) assign a physical address to the tbi so as to not conflict with the external phy physical address, tbipa[0000_0000_0000_0000_0000_0000_0000_0101] set to 05, for example. (note that phy configuration register addresse s are not necessarily consistent in all phys.) reset the management interface, miimcfg[1000_0000_0000_0000_0000_0000_0000_0000] setup the mii mgmt clock speed, miimcfg[0000_0000_0000_0000_0000_0000_0000_0101] set source clock divide by 14, for example, to insure that ec_mdc clock speed is approximately 2.5 mhz. read mii mgmt indicator register and check for busy = 0, miimind ---> [0000_0000_0000_0000_0000_0000_0000_0000] this indicates that the tsec mii mgmt bus is idle. setup the mii mgmt for a write cycle to the external phy auxiliary control and status register to configure the phy through the management interface (overrides c onfiguration signals of the phy), miimadd[0000_0000_0000_0000_0000_0000_0001_1100] perform an mii mgmt write cycle to the external phy. write to mii mgmt control with 16-bit data intended for the external phy register, miimcon[0000_0000_0000_0000_0000_0000_0000_0100] check to see if mii mgmt write is complete. read mii mgmt indicator register and check for busy = 0, miimind ---> [0000_0000_0000_0000_0000_0000_0000_0000] this indicates that the write cycle was completed setup the mii mgmt for a write cycle to the external phy extended phy co ntrol register 1 to set up the interface mode selection miimadd[0000_0000_0000_0000_0000_0000_0001_0111] 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-132 freescale semiconductor perform an mii mgmt write cycle to the external phy. write to mii mgmt control wi th 16-bit data intended for the external phy register, miimcon[0000_0000_0000_0000_0000_0000_0000_0000] check to see if mii mgmt write is complete. read mii mgmt indicator register and check for busy = 0, miimind ---> [0000_0000_0000_0000_0000_0000_0000_0000] this indicates that the write cycle was completed. setup the mii mgmt for a write cycle to the external phy mo de control register to set up the interface mode selection, miimadd[0000_0000_0000_0000_0000_0000_0000_0000] perform an mii mgmt write cycle to the external phy. write to mii mgmt control wi th 16-bit data intended for the external phy register, miimcon[0000_0000_0000_0000_000u_00u1_0100_0000] where u is user defined based on desired configuration. check to see if mii mgmt write is complete. read mii mgmt indicator register and check for busy = 0, miimind ---> [0000_0000_0000_0000_0000_0000_0000_0000] this indicates that the write cycle was completed. if auto-negotiation was enabled in the phy, check to see if phy has completed auto-negotiation. setup the mii mgmt for a read cycle to phy mii mgmt r egister (write the phy addr ess and register address), miimadd[0000_0000_0000_0000_0000_0000_0000_0001] the phy status register is at address 0x 1 and in this case the phy address is 0x00 perform an mii mgmt read cycle of status register. clear miimcom[read cycle]. set miimcom[read cycle]. (uses the phy address (0) and register address (1) placed in miimadd register), when miimind[busy]=0, read the miimstat register and check bit 10 (an done and link is up), miimstat ---> [0000_0000_0000_0000_0000_000_0010_0100] other information about the link is also retu rned.(extend status, no pre, remote faul t, an ability, link status, extend ability ) check auto-negotiation attributes in the phy as necessary. clear ievent register, ievent[0000_0000_0000_0000_0000_0000_0000_0000] initialize imask, (optional) imask[0000_0000_0000_0000_0000_0000_0000_0000] initialize iaddr n, (optional) iaddr n [0000_0000_0000_0000_0000_0000_0000_0000] initialize gaddr n, (optional) gaddr n [0000_0000_0000_0000_0000_0000_0000_0000] initialize rctrl, (optional) rctrl[0000_0000_0000_0000_0000_0000_0000_0000] initialize dmactrl, (optional) dmactrl[0000_0000_0000_0000_0000_0000_0000_0000] initialize fifo_pause_ctrl, fifo_pause_ctrl[0000_0000_0000_0000_0000_0000_0000_0010] initialize (empty) transmit descriptor ring and fill buffers with data. initialize tbase, tbase[llll_llll_llll_llll_llll_llll_llll_l000] table 14-127. gmii mode register initialization steps (continued) 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-133 14.7.1.3 tbi interface mode table 14-128 describes the signal configurati ons required for tbi interface mode. initialize (empty) receive descript or ring and fill with empty buffers. initialize rbase, rbase[llll_llll_llll_llll_llll_llll_llll_l000] enable rx and tx, maccfg1[0000_0000_0000_0000_0000_0000_0000_0101] table 14-128. tbi interface mode signal configuration tsec signals frequency [mhz] 125 voltage[v] 3.3/2.5 tbi interface frequency [mhz] 62.5 voltage[v] 3.3 signals i/o no. of signals signals i/o no. of signals gtx_clk o 1 gtx_clk o 1 tx_clk i 1 rx_clk1 i 1 txd[0]o1 tcg[0]o1 txd[1]o1 tcg[1]o1 txd[2]o1 tcg[2]o1 txd[3]o1 tcg[3]o1 txd[4]o1 tcg[4]o1 txd[5]o1 tcg[5]o1 txd[6]o1 tcg[6]o1 txd[7]o1 tcg[7]o1 tx_en o 1 tcg[8] o 1 tx_er o 1 tcg[9] o 1 rx_clk i 1 rx_clk0 i 1 rxd[0] i 1 rcg[0] i 1 rxd[1] i 1 rcg[1] i 1 rxd[2] i 1 rcg[2] i 1 rxd[3] i 1 rcg[3] i 1 rxd[4] i 1 rcg[4] i 1 rxd[5] i 1 rcg[5] i 1 rxd[6] i 1 rcg[6] i 1 rxd[7] i 1 rcg[7] i 1 rx_dv i 1 rcg[8] i 1 rx_er i 1 rcg[9] i 1 col i 1 i table 14-127. gmii mode register initialization steps (continued) 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-134 freescale semiconductor table 14-129 describes the shared signa ls for the tbi interface. table 14-130 describes the register initiali zations required to re configure the phy to tbi mode following initial auto-negotiation. crs i 1 sdet i 1 sum 25 sum 24 table 14-129. shared tbi signals tsec signals i/o no. of signals tbi signals i/o no. of signals function ec_mdio i/o 1 ec_mdio i/o 1 management interface i/o ec_mdc o 1 ec_mdc o 1 management interface clock ec_gtx_clk125 i 1 ec_gtx_clk125 i 1 reference clock sum 3 sum 3 table 14-130. tbi mode register initialization steps have the tsec n _gtx_clk configuration signal pulled high and ec_mdc signal pulled high for tbi mode. (tsec attempts to auto-negotiate after system reset.) set soft_reset, maccfg1[1000_0000_0000_0000_0000_0000_0000_0000] clear soft_reset, maccfg1[0000_0000_0000_0000_0000_0000_0000_0101] initialize maccfg2, maccfg2[0000_0000_0000_0000_0111_0010_0000_0101] (i/f mode = 2, full duplex = 1) initialize ecntrl, ecntrl[0000_0000_0000_0000_0001_0000_0000_0000] (this example has statistics enable = 1) initialize mac station address macstnaddr2[0110_0000_0000_0010_0000_0000_0000_0000] to 02608c:876543, for example. (note that phy configuration register addresse s are not necessarily consistent in all phys.) initialize mac station address macstnaddr1[0100_0011_0110_0101_1000_0111_1000_1100] to 02608c:876543, for example. (note that phy configuration register addresse s are not necessarily consistent in all phys.) assign a physical address to the tbi, tbipa[0000_0000_0000_0000_0000_0000_0001_0000] set to 16, for example. (note that phy configuration register addresse s are not necessarily consistent in all phys.) table 14-128. tbi interface mode signal configuration (continued) tsec signals frequency [mhz] 125 voltage[v] 3.3/2.5 tbi interface frequency [mhz] 62.5 voltage[v] 3.3 signals i/o no. of signals signals i/o no. of signals 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-135 setup the mii mgmt clock speed, miimcfg[0000_0000_0000_0000_0000_0000_0000_0111] set source clock divide by 28, for example, to ensure that ec_mdc clock speed is not greater than 2.5 mhz. read mii mgmt indicator register and check for busy = 0, miimind ---> [0000_0000_0000_0000_0000_0000_0000_0000] this indicates that the tsec mii mgmt bus is idle. set up the mii mgmt for a read cycle to tbi control regi ster (write the tbi address and register address), miimadd[0000_0000_0000_0000_0001_0000_0000_0000] the tbi control register is at offset address 0x0 from tbipa. perform an mii mgmt read cycle to verify state of tbi control register (optional) clear miimcom[read cycle] set miimcom[read cycle] (uses the tbi address and register address placed in miimadd register), when miimind[busy] = 0, read the miimstat and look for an enable and other bit information. setup the mii mgmt for a write cycle to tb i?s an advertisement register (write the phy address and register address), miimadd[0000_0000_0000_0000_0001_0000_0000_0100] the an advertisement register is at offset address 0x04 from the tbi?s address. (in this case 0x10) perform an mii mgmt write cycle to tbi. writing to mii mgmt control with 16-bit data in tended for tbi?s an advertisement register, miimcon[0000_0000_0000_0000_0000_0001_1010_0000] this advertises to the link partner that the tbi supports pause and full duplex mode and does not support half duplex mode. check to see if mii mgmt write is complete. read mii mgmt indicator register and check for busy = 0, miimind ---> [0000_0000_0000_0000_0000_0000_0000_0000] this indicates that the write cycle was completed. setup the mii mgmt for a write cycle to tbi?s control register (write th e phy address and register address), miimadd[0000_0000_0000_0000_0001_0000_0000_0000] the control register is at offset address 0x00 from the tbi?s address. (in this case 0x10) perform an mii mgmt write cycle to tbi. writing to mii mgmt control with 16-bit data intended for tbi?s control register, miimcon[0000_0000_0000_0000_0001_0010_0000_0000] this enables the tbi to restart auto-negotiations using the configuration set in the an advertisement register. check to see if mii mgmt write is complete. read mii mgmt indicator register and check for busy = 0, miimind ---> [0000_0000_0000_0000_0000_0000_0000_0000] this indicates that the write cycle was completed. check to see if phy has completed auto-negotiation. setup the mii mgmt for a read cycle to phy mii mgmt r egister (write the phy address and register address), miimadd[0000_0000_0000_0000_0001_0000_0000_0001] the phy status control register is at address 0x1 and in this case the phy address is 0x10. perform an mii mgmt read cycle of status register. clear miimcom[read cycle] set miimcom[read cycle] (uses the phy address (2) and register address (2) placed in miimadd register), when miimind[busy]=0, read the miimstat register and check bit 10 (an done) miimstat ---> [0000_0000_0000_0000_0000_0000_0010_0000] other information about the link is also returned. (extend status , no pre, remote fault, an ability, link status, extend abilit y) table 14-130. tbi mode register initialization steps (continued) 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-136 freescale semiconductor perform an mii mgmt read cycl e of an expansion register. setup miimadd[0000_0000_0000_0000_0001_0000_0000_0110] clear miimcom[read cycle] set miimcom[read cycle] (uses the phy address (0x10) and register address (6) placed in miimadd register), when miimind[busy] = 0, read the mii mgmt an expansion register and check bits 13 and 14 (np able and page rx?d) mii mgmt an expansion ---> [0000_0000_0000_0000_0000_0000_0000_0110] perform an mii mgmt read cycle of an link partner base page ability register. (optional) setup miimadd[0000_0000_0000_0000_0001_0000_0000_0101] clear miimcom[read cycle] set miimcom[read cycle] (uses the phy address (0x10) and register address (5) placed in miimadd register), when miimind[busy]=0, read the mii mgmt an link partner base page ability register and check bits 2 and 3 (remote fault) and bits 9 and 10. (half and full duplex) mii mgmt an link partner base page ab ility ---> [0000_0000_000 0_0000_0000_000x_x110_0000] clear ievent register, ievent[0000_0000_0000_0000_0000_0000_0000_0000] initialize imask (optional) imask[0000_0000_0000_0000_0000_0000_0000_0000] initialize iaddr n (optional) iaddr n [0000_0000_0000_0000_0000_0000_0000_0000] initialize gaddr n (optional) gaddr n [0000_0000_0000_0000_0000_0000_0000_0000] initialize rctrl (optional) rctrl[0000_0000_0000_0000_0000_0000_0000_0000] initialize dmactrl (optional) dmactrl[0000_0000_0000_0000_0000_0000_0000_0000] initialize fifo_pause_ctrl, fifo_pause_ctrl[0000_0000_0000_0000_0000_0000_0000_0010] initialize (empty) transmit descri ptor ring and fill buffers with data initialize tbase, tbase[llll_llll_llll_llll_llll_llll_llll_l000] initialize (empty) receive descriptor ring and fill with empty buffers initialize rbase, rbase[llll_llll_llll_llll_llll_llll_llll_l000] enable rx and tx, maccfg1[0000_0000_0000_0000_0000_0000_0000_0101] table 14-130. tbi mode register initialization steps (continued) 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-137 14.7.1.4 rgmii interface mode table 14-131 shows the signals conf igurations required fo r rgmii interface mode. table 14-131. rgmii interface mode signal configuration tsec signals frequency [mhz] 125 voltage[v] 3.3/2.5 rgmii inrterface frequency [mhz] 125 voltage[v] 2.5 signals i/o no. of signals signals i/o no. of signals gtx_clk o 1 gtx_clk o 1 tx_clk i 1 txd[0] o 1 txd[0]/txd[4] o 1 txd[1] o 1 txd[1]/txd[5] o 1 txd[2] o 1 txd[2]/txd[6] o 1 txd[3] o 1 txd[3]/txd[7] o 1 txd[4] o 1 txd[5] o 1 txd[6] o 1 txd[7] o 1 tx_en o 1 tx_ctl (tx_en/tx_err) o 1 tx_er o 1 rx_clk i 1 rx_clk i 1 rxd[0] i 1 rxd[0]/rxd[4] i 1 rxd[1] i 1 rxd[1]/rxd[5] i 1 rxd[2] i 1 rxd[2]/rxd[6] i 1 rxd[3] i 1 rxd[3]/rxd[7] i 1 rxd[4] i 1 rxd[5] i 1 rxd[6] i 1 rxd[7] i 1 rx_dv i 1 rx_ctl (rx_dv/rx_err) i 1 rx_er i 1 col i 1 crs i 1 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-138 freescale semiconductor table 14-132 describes the shared signa ls for the rgmii interface. table 14-133 describes the register init ializations required to reconf igure the phy to rgmii mode following initial auto-negotiation. sum 25 sum 12 table 14-132. shared rgmii signals tsec signals i/o no. of signals rgmii signals i/o no. of signals function ec_mdio i/o 1 ec_mdio i/o 1 management interface i/o ec_mdc o 1 ec_mdc o 1 management interface clock ec_gtx_clk125 i 1 ec_gtx_clk125 i 1 reference clock sum 3 sum 3 table 14-133. rgmii mode register initialization steps have the tsec n _gtx_clk configuration signal pulled low and ec_mdc signal pulled low for rgmii mode. tbi control register?s auto-negotiation enable and reset bits are ignored. set soft_reset, maccfg1[1000_0000_0000_0000_0000_0000_0000_0000] clear soft_reset, maccfg1[0000_0000_0000_0000_0000_0000_0000_0101] initialize maccfg2, maccfg2[0000_0000_0000_0000_0111_0010_0000_0101] (i/f mode = 2, full duplex = 1) initialize ecntrl, ecntrl[0000_0000_0000_0000_0001_0000_0000_0000] (this example has rgmii 10-mbps mode, statistics enable = 1) initialize mac station address, macstnaddr2[0110_0000_0000_0010_0000_0000_0000_0000] to 02608c:876543, for example. (note that phy configuration register addresse s are not necessarily consistent in all phys.) initialize mac station address, macstnaddr1[0100_0011_0110_0101_1000_0111_1000_1100] to 02608c:876543, for example. (note that phy configuration register addresse s are not necessarily consistent in all phys.) assign a physical address to the tbi, tbipa[0000_0000_0000_0000_0000_0000_0001_0000] set to 16, for example. (note that phy configuration register addresse s are not necessarily consistent in all phys.) table 14-131. rgmii interface mode signal configuration (continued) tsec signals frequency [mhz] 125 voltage[v] 3.3/2.5 rgmii inrterface frequency [mhz] 125 voltage[v] 2.5 signals i/o no. of signals signals i/o no. of signals 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-139 setup the mii mgmt clock speed, miimcfg[0000_0000_0000_0000_000_0000_0000_0111] set source clock divide by 28, for example, to insure that ec_mdc clock speed is not greater than 2.5 mhz. read mii mgmt indicator register and check for busy = 0, miimind ---> [0000_0000_0000_0000_0000_0000_0000_0000] this indicates that the tsec mii mgmt bus is idle. setup the mii mgmt for a write cycle to external the phy an advertisement register (write the phy address and register address), miimadd[0000_0000_0000_0000_0001_0001_0000_0100] the an advertisement register is at offset address 0x04 from the external phy address. (in this case 0x11) perform an mii mgmt write cycle to the external phy. write to mii mgmt control with 16-bit data intended for the external phy an advertisement register, miimcon[0000_0000_0000_0000_u0uu_uuuu_uuuu_uuuu] where u must be selected by the us er for proper system configuration. check to see if mii mgmt write is complete. read mii mgmt indicator register and check for busy = 0, miimind ---> [0000_0000_0000_0000_0000_0000_0000_0000] this indicates that the write cycle was completed. setup the mii mgmt for a write cycle to the external phy cont rol register (write the phy address and register address), miimadd[0000_0000_0000_0000_0001_0001_0000_0000] the control register is at offset address 0x00 from the external phy address. (in this case 0x11) perform an mii mgmt write cycle to the external phy. write to mii mgmt control wit h 16-bit data intended for the ex ternal phy control register, miimcon[0000_0000_0000_0000_0001_0010_0000_0000] this enables the external phy to restart auto-negotiations us ing the configuration set in t he an advertisement register. check to see if mii mgmt write is complete. read mii mgmt indicator register and check for busy = 0, miimind ---> [0000_0000_0000_0000_0000_0000_0000_0000] this indicates that the write cycle was completed. check to see if phy has completed auto-negotiation. setup the mii mgmt for a read cycle to the phy mii mgmt r egister (write the phy address and register address), miimadd[0000_0000_0000_0000_0000_0010_0000_0001] the phy status register is at address 0x1 and in this case the phy address is 0x2. perform an mii mgmt read cycle of status register. clear miimcom[read cycle] set miimcom[read cycle] (uses the phy address (2) and register ad dress (2) placed in miimadd register) when miimind[busy]=0, read the miimstat register and check bit 10. (an done) miimstat ---> [0000_0000_0000_0000_0000_0000_0010_0000] other information about the link is also returned. (extend status , no pre, remote fault, an ability, link status, extend abilit y) perform an mii mgmt read cycl e of an expansion register. setup miimadd[0000_0000_0000_0000_0001_0001_0000_0110] clear miimcom[read cycle] set miimcom[read cycle] (uses the phy address (0x11) and register address (6) placed in miimadd register) when miimind[busy]=0, read the mii mgmt an expansion register and check bits 13 and 14. (np able and page rx?d) mii mgmt an expansion ---> [0000_0000_0000_0000_0000_0000_0000_0110] table 14-133. rgmii mode register initialization steps (continued) 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-140 freescale semiconductor 14.7.1.5 rtbi interface mode table 14-134 describes the signal configurations required for rtbi interface mode. perform an mii mgmt read cycle of an link partner base page ability register. (optional) setup miimadd[0000_0000_0000_0000_0001_0001_0000_0101] clear miimcom[read cycle] set miimcom[read cycle] (uses the phy address (0x11) and register address (5) placed in miimadd register) when miimind[busy]=0, read the mii mgmt an link partner base page ability register and check bits 9 and 10. (half and full duplex) mii mgmt an link partner base page ab ility ---> [0000_0000_000 0_0000_0000_000x_x110_0000] clear ievent register, ievent[0000_0000_0000_0000_0000_0000_0000_0000] initialize imask (optional) imask[0000_0000_0000_0000_0000_0000_0000_0000] initialize iaddr n (optional) iaddr n [0000_0000_0000_0000_0000_0000_0000_0000] initialize gaddr n (optional) gaddr n [0000_0000_0000_0000_0000_0000_0000_0000] initialize rctrl (optional) rctrl[0000_0000_0000_0000_0000_0000_0000_0000] initialize dmactrl (optional) dmactrl[0000_0000_0000_0000_0000_0000_0000_0000] initialize fifo_pause_ctrl, fifo_pause_ctrl[0000_0000_0000_0000_0000_0000_0000_0010] initialize (empty) transmit descriptor ring and fill buffers with data initialize tbase, tbase[llll_llll_llll_llll_llll_llll_llll_l000] initialize (empty) receive descriptor ring and fill with empty buffers initialize rbase, rbase[llll_llll_llll_llll_llll_llll_llll_l000] enable rx and tx, maccfg1[0000_0000_0000_0000_0000_0000_0000_0101] table 14-134. rtbi interlace mode signal configuration tsec signals frequency [mhz] 125 voltage[v] 3.3/2.5 rtbi interface frequency [mhz] 62.5 voltage[v] 2.5 signals i/o no. of signals signals i/o no. of signals gtx_clk o 1 gtx_clk o 1 tx_clk i 1 txd[0] o 1 tcg[0]/tcg[5] o 1 txd[1] o 1 tcg[1]/tcg[6] o 1 table 14-133. rgmii mode register initialization steps (continued) 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-141 txd[2] o 1 tcg[2]/tcg[7] o 1 txd[3] o 1 tcg[3]/tcg[8] o 1 txd[4] o 1 txd[5] o 1 txd[6] o 1 txd[7] o 1 tx_en o 1 tcg[4]/tcg[9] o 1 tx_er o 1 rx_clk i 1 rx_clk i 1 rxd[0] i 1 rcg[0]/rcg[5] i 1 rxd[1] i 1 rcg[1]/rcg[6] i 1 rxd[2] i 1 rcg[2]/rcg[7] i 1 rxd[3] i 1 rcg[3]/rcg[8] i 1 rxd[4] i 1 rxd[5] i 1 rxd[6] i 1 rxd[7] i 1 rx_dv i 1 rcg[4]/rcg[9] i 1 rx_er i 1 col i 1 crs i 1 i sum 25 sum 12 table 14-134. rtbi interlace mode signal configuration (continued) tsec signals frequency [mhz] 125 voltage[v] 3.3/2.5 rtbi interface frequency [mhz] 62.5 voltage[v] 2.5 signals i/o no. of signals signals i/o no. of signals 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-142 freescale semiconductor table 14-135 describes the shared signals for the rtbi interface. table 14-136 describes the register init ializations required to reconf igure the phy to rtbi mode following initial auto-negotiation. table 14-135. shared rtbi signals tsec signals i/o no. of signals rtbi signals i/o no. of signals function ec_mdio i/o 1 ec_mdio i/o 1 management interface i/o ec_mdc o 1 ec_mdc o 1 management interface clock ec_gtx_clk125 i 1 ec_gtx_clk125 i 1 reference clock sum 3 sum 3 table 14-136. rtbi mode register initialization steps have the tsec n _gtx_clk configuration signal pulled high and the ec_mdc signal pulled low for rtbi mode. (tsec attempts to auto-negotiate after system reset.) set soft_reset, maccfg1[1000_0000_0000_0000_0000_0000_0000_0000] clear soft_reset, maccfg1[0000_0000_0000_0000_0000_0000_0000_0101] initialize maccfg2, maccfg2[0000_0000_0000_0000_0111_0010_0000_0101] (i/f mode = 2, full duplex = 1) initialize ecntrl, ecntrl[0000_0000_0000_0000_0001_0000_0000_0000] (this example has statistics enable = 1) initialize mac station address, macstnaddr2[0110_0000_0000_0010_0000_0000_0000_0000] to 02608c:876543, for example. (note that phy configuration register addresse s are not necessarily consistent in all phys.) initialize mac station address, macstnaddr1[0100_0011_0110_0101_1000_0111_1000_1100] to 02608c:876543, for example. (note that phy configuration register addresse s are not necessarily consistent in all phys.) assign a physical address to the tbi, tbipa[0000_0000_0000_0000_0000_0000_0001_0000] set to 16, for example. (note that phy configuration register addresse s are not necessarily consistent in all phys.) setup the mii mgmt clock speed, miimcfg[0000_0000_0000_0000_0000_0000_0000_0111] set source clock divide by 28, for example, to insure that ec_mdc clock speed is not greater than 2.5 mhz. read mii mgmt indicator register and check for busy = 0, miimind ---> [0000_0000_0000_0000_0000_0000_0000_0000] this indicates that the tsec mii mgmt bus is idle. setup the mii mgmt for a read cycle to tbi control regi ster (write the tbi?s address and register address), miimadd[0000_0000_0000_0000_0001_0000_0000_0000] the tbi control register is at offset address 0x0 from tbipa. 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 14-143 perform an mii mgmt read cycle to verify state of tbi control register (optional) clear miimcom[read cycle] set miimcom[read cycle] (uses the tbi address and register address placed in miimadd register), when miimind[busy] = 0, read the miimstat and look for an enable and other bit information. setup the mii mgmt for a write cycle to tbi?s an advertisement register (write the phy ad dress and register address), miimadd[0000_0000_0000_0000_0001_0000_0000_0100] the an advertisement register is at offset address 0x04 from the tbi?s address. (in this case 0x10) perform an mii mgmt write cycle to tbi. write to mii mgmt control with 16-bit data intended for tbi?s an advertisement register, miimcon[0000_0000_0000_0000_0000_0001_1010_0000] this advertises to the link partner that the tbi supports pause and full duplex mode and does not support half duplex mode. check to see if mii mgmt write is complete. read mii mgmt indicator register and check for busy = 0, miimind ---> [0000_0000_0000_0000_0000_0000_0000_0000] this indicates that the write cycle was completed. setup the mii mgmt for a write cycle to tbi?s control r egister (write the phy addr ess and register address), miimadd[0000_0000_0000_0000_0001_0000_0000_0000] the control register is at offset address 0x00 from the tbi?s address. (in this case 0x10) perform an mii mgmt write cycle to tbi. writing to mii mgmt control with 16-bit data intended for tbi?s control register, miimcon[0000_0000_0000_0000_0001_0010_0000_0000] this enables the tbi to restart auto-negotiations using the configuration set in the an advertisement register. check to see if mii mgmt write is complete. read mii mgmt indicator register and check for busy = 0, miimind ---> [0000_0000_0000_0000_0000_0000_0000_0000] this indicates that the write cycle was completed. check to see if phy has completed auto-negotiation. setup the mii mgmt for a read cycle to the phy mii mgmt r egister (write the phy address and register address), miimadd[0000_0000_0000_0000_0001_0000_0000_0001] the phy status control register is at address 0x1 and in this case the phy address is 0x10. perform an mii mgmt read cycle of status register. clear miimcom[read cycle] set miimcom[read cycle] (uses the phy address (2) and register address (2) placed in miimadd register), when miimind[busy]=0, read the miimstat register and check bit 10 (an done) miimstat ---> [0000_0000_0000_0000_0000_0000_0010_0000] other information about the link is also returned. (extend status , no pre, remote fault, an ability, link status, extend abilit y) perform an mii mgmt read cycl e of an expansion register. setup miimadd[0000_0000_0000_0000_0001_0000_0000_0110] clear miimcom[read cycle] set miimcom[read cycle] (uses the phy address (0x10) and register address (6) placed in miimadd register), when miimind[busy] = 0, read the mii mgmt an expansion register and check bits 13 and 14. (np able and page rx?d) mii mgmt an expansion ---> [0000_0000_0000_0000_0000_0000_0000_0110] table 14-136. rtbi mode register initialization steps (continued) 4 datasheet u .com
three-speed ethernet controllers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 14-144 freescale semiconductor perform an mii mgmt read cycle of an link partner base page ability register. (optional) setup miimadd[0000_0000_0000_0000_0001_0000_0000_0101] clear miimcom[read cycle] set miimcom[read cycle] (uses the phy address (0x10) and register address (5) placed in miimadd register), when miimind[busy] = 0, read the mii mgmt an link partner base page ability register and check bits 9 and 10. (half and full duplex) mii mgmt an link partner base page ability ---> [0000_0000_0000_0000_0000_000x_x110_0000] clear ievent register, ievent[0000_0000_0000_0000_0000_0000_0000_0000] initialize imask (optional) imask[0000_0000_0000_0000_0000_0000_0000_0000] initialize iaddr n (optional) iaddr n [0000_0000_0000_0000_0000_0000_0000_0000] initialize gaddr n (optional) gaddr n [0000_0000_0000_0000_0000_0000_0000_0000] initialize rctrl (optional) rctrl[0000_0000_0000_0000_0000_0000_0000_0000] initialize dmactrl (optional) dmactrl[0000_0000_0000_0000_0000_0000_0000_0000] initialize fifo_pause_ctrl, fifo_pause_ctrl[0000_0000_0000_0000_0000_0000_0000_0010] initialize (empty) transmit descri ptor ring and fill buffers with data initialize tbase, tbase[llll_llll_llll_llll_llll_llll_llll_l000] initialize (empty) receive descriptor ring and fill with empty buffers initialize rbase, rbase[llll_llll_llll_llll_llll_llll_llll_l000] enable rx and tx, maccfg1[0000_0000_0000_0000_0000_0000_0000_0101] table 14-136. rtbi mode register initialization steps (continued) 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 15-1 chapter 15 dma controller this chapter describes the dm a controller of the MPC8555E. 15.1 introduction the dma controller transfers blocks of data between pci, the local bu s controller (lbc) interface, and the local address space, independent of the e500 core or external hosts. 15.1.1 block diagram figure 15-1 shows the block diagram of the dma controller. figure 15-1. dma block diagram chn 0 chn 1 chn 2 chn 3 arbitration and bandwidth control source controls destination controls address address address controls te n u r e data controls te n u r e address interface data interface dma controller 4 datasheet u .com
dma controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 15-2 freescale semiconductor 15.1.2 overview the dma controller has four high-speed dma channels. both the core and external devices can initiate dma transfers. all channels are capable of complex data movement and advan ced transaction chaining. figure 15-1 is a high-level block di agram of the dma controller. opera tions such as descriptor fetches and block transfers are initiated by each channel. a channel is selected by the arbitration logic and information is passed to the source and destinat ion control blocks for pr ocessing. the source and destination blocks ge nerate read and write reque sts to the address tenure e ngine, which manages the dma master port address interface. after a transaction is accepted by the master port, control is transferred to the data tenure engine that manage s the read and write data transfers. a channel remains active in the shared resources for the duration of the data transfer unless the allotted bandwidth per channel is reached. 15.1.3 features the dma controller offers the following features: ? four high-speed/high-bandwidth channels accessible by local and remote masters ? basic dma operation modes (direct, simple chaining) ? extended dma operation modes (advanced chaining and stride capability) ? cascading descriptor chains ? misaligned transfers ? programmable bandwidth control between channels ? three priority levels supported for s ource and destination transactions ? interrupt on error and comple ted segment, list, or link ? externally-controlled transfer using dma_dreq , dma_dack , and dma_ddone 15.1.4 modes of operation the MPC8555E has two modes of operation: basic a nd extended. basic mode is the dma legacy mode. it does not support advanced features . extended mode supports advanced fe atures like stri ding and flexible descriptor structures. these two basic modes allow us ers to initiate and end dma transfers in various ways. table 15-1 summarizes the relationship between th e modes and the following features: ? direct mode. no descript ors are involved. software must initialize the requi red fields as described in table 15-1 before starting a transfer. ? chaining mode. software must initi alize descriptors in memory and the required fields as described in table 15-1 before starting a transfer. ? single-write start mode. the dm a process can be started by us ing a single-write command to either the descriptor address regi ster in one of the chaining modes or the source/des tination address registers in one of the direct modes. ? external control capability. this allo ws an external agent to start, pause, and check the status of a dma transfer which has already been initialized. 4 datasheet u .com
dma controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 15-3 ? channel continue capability. the channel continue capability allows softwa re the flexibility of having the dma controller start with descriptors that have already been programmed while software continues to build more descriptors in memory. ? channel abort capability. the software can abort a previously initiated transfer by setting the bit mr n [ca]. the dma controller termin ates all outstanding transf ers initiated by the channel without generating any errors be fore entering an idle state. table 15-2 describes bit settings require d for each dma mode of operation. ( table 15-1. relationship of modes and features mode mode with one additional feature mode with two additional features b (basic) bd (basic direct) bds (bd single-write start) bde (bd external control) bc (basic chaining) bce (bc external control) bcs (bc single-write start) ext (extended) extd (extended direct ) extds (extd single-write start) extde (extd external control) extc (extended chaining) extce (extc external control) extcs (extc single-write start) table 15-2. dma mode bit settings modes with features mr n [xfe] mr n [ctm] mr n [srw] mr n [cdsm/swsm] mr n [ems_en] basic direct modes basic direct 0 1 0 0 0 basic direct external control 0 1 0 0 1 basic direct single-write start 0 1 1 1 or 0 0 basic chaining modes basic chaining 0 0 reserved 0 0 basic chaining external control 0 0 reserved 0 1 basic chaining single-write start 0 0 reserved 1 0 extended direct modes extended direct 1 1 0 0 0 extended direct external control 1 1 0 0 1 extended direct single-write start 1 1 1 1 or 0 0 4 datasheet u .com
dma controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 15-4 freescale semiconductor refer to section 15.4, ?functional description,? for details on these modes. figure 15-2 shows the general dma operational flow chart. figure 15-2. dma operational flow chart 15.2 external signal description this section describes the dma signals. extended chaining modes extended chaining 1 0 reserved 0 0 extended chaining external control 1 0 reserved 0 1 extended chaining single-write start 1 0 reserved 1 0 table 15-2. dma mode bit settings (continued) modes with features mr n [xfe] mr n [ctm] mr n [srw] mr n [cdsm/swsm] mr n [ems_en] software sets 1st link process link last link? is n y n chain or extended done?dma halts y is last list? n y advance list advance mode? in link 4 datasheet u .com
dma controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 15-5 15.2.1 signal overview figure 15-3 summarizes the dma controller signals. figure 15-3. dma signal summary note that the three dma signals for dma channel 3 are multiplexed with the irq9?11 signals on the MPC8555E device. these functions ar e mutually exclusive and the acti ve function is specified in the pmuxcr register of the global ut ilities block as described in section 18.4.1.10, ?alternate function signal multiplex contro l register (pmuxcr).? 15.2.2 detailed signal descriptions table 15-3 describes the dma signals. table 15-3. dma signals?detailed signal descriptions signal i/o description dma_dreq n dma request i dma request. the dma request signal indicates the start of a dma transfer or a restart from a paused request. assertion of dma_dreq n causes mr n [cs] to be set, thereby activating the corresponding dma channel. state meaning asserted?assertion of dma_dreq n while dma_dack n is negated causes a new transfer to start or resumes a paused transfer if the emp_en bit is set. assertion while dma_dack n is asserted results in an illegal condition. negated?negation while dma_dack n is asserted has no effect. negation before the assertion of dma_dack n results in an illegal condition. timing assertion?can be asserted asynchronously negation? must remain asserted at least until the assertion of the corresponding dma_dack n dma external control interface dma dma_ddone3 dma_dreq3 dma_dack3 1 1 1 unit dma_ddone1 dma_dreq1 dma_dack1 1 1 1 dma_ddone0 dma_dreq0 dma_dack0 1 1 1 dma_ddone2 dma_dreq2 dma_dack2 1 1 1 4 datasheet u .com
dma controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 15-6 freescale semiconductor 15.3 memory map/register definition this section provides a detailed desc ription of all accessible dma memory and registers. the descriptions include individual bit level descripti ons and reset states of each regist er. undefined 4-byte address spaces within offset 0x000?0xfff are reserved. 15.3.1 module memory map table 15-4 lists the dma registers and their offsets. note th at the full register address is comprised of the programmable ccsrbar together wi th the fixed dma block base a ddress and offset listed in table 15-4 . in this table and in the register figures and field descriptions, th e following access definitions apply: ? reserved fields are always ignored for the purposes of determining access type. ? r/w, r, and w (read/write, read only, and write only) indicate that all the non-reserved fields in a register have the same access type. ? w1c indicates that all of the non-reserved fields in a register are cleared by writing ones to them. ? mixed indicates a combination of access types. ? special is used when no other cate gory applies. in this case the re gister figure and field description table should be read carefully. dma_dack n o dma acknowledge. indicates that a dma transfer is currently in progress state meaning asserted?indicates that a dma transfer is current ly in progress. asserted after the assertion of dma_dreq n to indicate the start of a transfer negated?negated after finishing a complete tr ansfer or after entering a paused state if mr n [emp_en] is set timing assertion?asynchronous assertion; assert ed for more than three system clocks negation?asynchronous negation; negated for more than three system clocks dma_ddone n o dma done. indicates that a dma transfer is complete state meaning asserted?indicates transfer co mpletion. srn[cb] is clear. note, however, that write data may still be queued at the target interface or in the process of transfer on an external interface. negated?indicates that the current transfer is in process timing assertion?always asserts asynchronously after the negation of the final dma_dack n to indicate completion of a transfer. for a paused transfer, dma_ddone n is asserted asynchronously after the negation of the final dma_dack n . negation?negated asynchronously after the assertion of dma_dreq n for the next transfer table 15-3. dma signals?detailed signal descriptions (continued) signal i/o description 4 datasheet u .com
dma controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 15-7 table 15-4. dma register summary offset register acce ss reset section/page dma controller block base address: 0x2_1000 0x100 mr0?dma 0 mode register r/w 0x0000_0000 15.3.2.1/15-9 0x104 sr0?dma 0 status register mixed 0x0000_0000 15.3.2.2/15-11 0x10c clndar0?dma 0 current link descriptor address register r/w 0x0000_0000 15.3.2.3/15-12 0x110 satr0?dma 0 source attributes register r/w 0x0000_0000 15.3.2.4/15-14 0x114 sar0?dma 0 source address register r/w 0x0000_0000 15.3.2.5/15-15 0x118 datr0?dma 0 destination at tributes register r/w 0x0000_0000 15.3.2.6/15-16 0x11c dar0?dma 0 destination address register r/w 0x0000_0000 15.3.2.7/15-16 0x120 bcr0?dma 0 byte count register r/w 0x0000_0000 15.3.2.8/15-17 0x128 nlndar0?dma 0 next link descriptor address register r/w 0x0000_0000 15.3.2.9/15-17 0x134 clsdar0?dma 0 current list descriptor address register r/w 0x0000_0000 15.3.2.10/15-18 0x13c nlsdar0?dma 0 next list descriptor address register mixed 0x0000_0000 15.3.2.11/15-19 0x140 ssr0?dma 0 source stride register r/w 0x0000_0000 15.3.2.12/15-19 0x144 dsr0?dma 0 destination stride register r/w 0x0000_0000 15.3.2.13/15-20 0x148 ? 0x17c reserved ? ? ? 0x180 mr1?dma 1 mode register r/w 0x0000_0000 15.3.2.1/15-9 0x184 sr1?dma 1 status register mixed 0x0000_0000 15.3.2.2/15-11 0x18c clndar1?dma 1 current link descriptor address register r/w 0x0000_0000 15.3.2.3/15-12 0x190 satr1?dma 1 source attributes register r/w 0x0000_0000 15.3.2.4/15-14 0x194 sar1?dma 1 source address register r/w 0x0000_0000 15.3.2.5/15-15 0x198 datr1?dma 1 destination at tributes register r/w 0x0000_0000 15.3.2.6/15-16 0x19c dar1?dma 1 destination address register r/w 0x0000_0000 15.3.2.7/15-16 0x1a0 bcr1?dma 1 byte count register r/w 0x0000_0000 15.3.2.8/15-17 0x1a8 nlndar1?dma 1 next link descriptor address register r/w 0x0000_0000 15.3.2.9/15-17 0x1b4 clsdar1?dma 1 current list descriptor address register r/w 0x0000_0000 15.3.2.10/15-18 0x1bc nlsdar1?dma 1 next list descriptor address register r/w 0x0000_0000 15.3.2.11/15-19 0x1c0 ssr1?dma 1 source stride register r/w 0x0000_0000 15.3.2.12/15-19 0x1c4 dsr1?dma 1 destination stride register r/w 0x0000_0000 15.3.2.13/15-20 0x1c8 ? 0x1fc reserved ? ? ? 0x200 mr2?dma 2 mode register r/w 0x0000_0000 15.3.2.1/15-9 0x204 sr2?dma 2 status register mixed 0x0000_0000 15.3.2.2/15-11 0x20c clndar2?dma 2 current link descriptor address register r/w 0x0000_0000 15.3.2.3/15-12 0x210 satr2?dma 2 source attributes register r/w 0x0000_0000 15.3.2.4/15-14 4 datasheet u .com
dma controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 15-8 freescale semiconductor 15.3.2 dma register descriptions the following sections describe the dma registers. the majority of th ese registers are channel-specific and can be identified by one of the four offsets that describe the register. 0x214 sar2?dma 2 source address register r/w 0x0000_0000 15.3.2.5/15-15 0x218 datr2?dma 2 destination at tributes register r/w 0x0000_0000 15.3.2.6/15-16 0x21c dar2?dma 2 destination address register r/w 0x0000_0000 15.3.2.7/15-16 0x220 bcr2?dma 2 byte count register r/w 0x0000_0000 15.3.2.8/15-17 0x228 nlndar2?dma 2 next link descriptor address register r/w 0x0000_0000 15.3.2.9/15-17 0x234 clsdar2?dma 2 current list descriptor address register r/w 0x0000_0000 15.3.2.10/15-18 0x23c nlsdar2?dma 2 next list descriptor address register r/w 0x0000_0000 15.3.2.11/15-19 0x240 ssr2?dma 2 source stride register r/w 0x0000_0000 15.3.2.12/15-19 0x244 dsr2?dma 2 destination stride register r/w 0x0000_0000 15.3.2.13/15-20 0x248 ? 0x27c reserved ? ? ? 0x280 mr3?dma 3 mode register r/w 0x0000_0000 15.3.2.1/15-9 0x284 sr3?dma 3 status register mixed 0x0000_0000 15.3.2.2/15-11 0x28c clndar3?dma 3 current link descriptor address register r/w 0x0000_0000 15.3.2.3/15-12 0x290 satr3?dma 3 source attributes register r/w 0x0000_0000 15.3.2.4/15-14 0x294 sar3?dma 3 source address register r/w 0x0000_0000 15.3.2.5/15-15 0x298 datr3?dma 3 destination at tributes register r/w 0x0000_0000 15.3.2.6/15-16 0x29c dar3?dma 3 destination address register r/w 0x0000_0000 15.3.2.7/15-16 0x2a0 bcr3?dma 3 byte count register r/w 0x0000_0000 15.3.2.8/15-17 0x2a8 nlndar3?dma 3 next link descriptor address register r/w 0x0000_0000 15.3.2.9/15-17 0x2b4 clsdar3?dma 3 current list descriptor address register r/w 0x0000_0000 15.3.2.10/15-18 0x2bc nlsdar3?dma 3 next list descriptor address register r/w 0x0000_0000 15.3.2.11/15-19 0x2c0 ssr3?dma 3 source stride register r/w 0x0000_0000 15.3.2.12/15-19 0x2c4 dsr3?dma 3 destination stride register r/w 0x0000_0000 15.3.2.13/15-20 0x2c8 ? 0x2fc reserved ? ? ? 0x300 dgsr?dma general status register r 0x0000_0000 15.3.2.14/15-21 table 15-4. dma register summary (continued) offset register acce ss reset section/page 4 datasheet u .com
dma controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 15-9 15.3.2.1 mode registers (mr n ) the mode register allows software to start a dm a transfer and to control various dma transfer characteristics. figure 15-4 describes the mr n . table 15-5 describes the mr n fields. offset 0x100 0x180 0x200 0x280 access: read/write 0 34 7 8910 11 12 131415 r ? bwc ?emp_en ? ems_en dahts w reset all zeros 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r sahts dahe sahe ? srweosieeolnieeolsie eie xfe cdsm/swsm ca ctm cc cs w reset all zeros figure 15-4. dma m ode registers (mr n ) table 15-5. mr n field descriptions bits name description 0?3 ? reserved 4?7 bwc bandwidth/pause control. defined only if mr n [emp_en] is set. if multiple channels are executing transfers concurrently the value of mr n [bwc] determines how many bytes a given channel is allowed to transfer before the dma engine pauses the current channel and switches to the next channel. if only one channel is executing transfers the value of mr n [bwc] dictates how many bytes are allowed to transfer before pausing the channel, after which a new assertion of dreq resumes channel operation. 0000 1 byte 0001 2 bytes 0010 4 bytes 0011 8 bytes 0100 16 bytes 0101 32 bytes 0110 64 bytes 0111 128 bytes 1000 256 bytes 1001 512 bytes 1010 1024 bytes 1011?1110 reserved 1111 disable bandwidth sharing to allow uninterrupted transfers from each channel. 8?9 ? reserved 10 emp_en external master pause enable. valid only if mr n [ems_en] is set. 0 disable the external master pause feature. 1 enable the external master pause feature. channel is paused as described by mr n [bwc]. 11?12 ? reserved 13 ems_en external master start enable. this bit does not apply to single-write start modes (direct or chaining). 0 disable the channel from being started by an external dma start pin. 1 enable the channel to be started by an external dma start pin, which sets mr n [cs]. 4 datasheet u .com
dma controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 15-10 freescale semiconductor 14?15 dahts destination address hold transfer size. indicates the transfer size used for each transaction while mr n [dahe] is set. the byte count register must be in multiples of the size and the destination address register must be aligned based on the size. the transfer size assigned to mr n [dahts] must be equal to or smaller than that assigned to mr n [bwc] to avoid undefined behavior. 00 1 byte 01 2 bytes 10 4 bytes 11 8 bytes 16?17 sahts source address hold transfer size. indicates the transfer size used for each transaction while mr n [sahe] is set. the byte count register must be in multiples of the size and the source address register must be aligned based on the size. the transfer size assigned to mr n [sahts] must be equal to or smaller than that assigned to mr n [bwc] to avoid undefined behavior. 00 1 byte 01 2 bytes 10 4 bytes 11 8 bytes 18 dahe destination address hold enable 0 disable destination address hold 1 enable the dma controller to hold the destination a ddress of a transfer to the size specified by mr n [dahts]. hardware only supports aligned transfers for this feature. 19 sahe source address hold enable 0 disable source address hold 1 enable the dma controller to hold the source ad dress of a transfer to the size specified by mr n [sahts]. hardware only supports aligned transfers for this feature. 20 ? reserved 21 srw single register write (direct mode only; reserved for chaining mode.) 0 normal operation 1 enable a write to the source address register to simultaneously set mr n [cs], starting a dma transfer, when mr n [cdsm/swsm] is also set. setting this bit a nd clearing cdsm/swsm causes a write to the destination address register to simultaneously set mr n [cs], starting a dma transfer. 22 eosie end-of-segments interrupt enable 0 do not generate an interrupt at the co mpletion of a data transfer. clndar n [eosie] overrides this bit on a link descriptor basis. 1 generate an interrupt at the completion of a data transfer (that is, sr n [eosi] is set). this bit overrides the clndar n [eosie]. 23 eolnie end-of-links interrupt enable 0 do not generate an interrupt at the completion of a list of dma transfers. 1 generate an interrupt at the completion of a list of dma transfers (that is, nlndar n [eolnd] is set). 24 eolsie end-of-lists interrupt enable 0 do not generate an interrupt at the completion of all dma transfers. 1 generate an interrupt at the completion of all dma transfers (that is, nlndar n [eolnd] and nlsdar n [eolsd] are set). 25 eie error interrupt enable 0 do not generate an interrupt if a programming or transfer error is detected. 1 generate an interrupt if a programm ing or transfer error is detected. table 15-5. mr n field descriptions (continued) bits name description 4 datasheet u .com
dma controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 15-11 15.3.2.2 status registers (sr n ) the status registers, shown in figure 15-5 , report various dma conditions during and after a dma transfer. 26 xfe extended features enable 0 disable the new chaining features. 1 enable the new chaining features. 27 cdsm/ swsm ? in chaining mode: current descript or start mode/single-write start mode ? in basic mode (mr n [xfe] is cleared), setting this bit causes a write to the current link descriptor address register to simultaneously set mr n [cs], starting a dma transfer. ? in extended chaining mode (mr n [xfe] is set), setting this bit causes a write to the current list descriptor address register to simultaneously set mr n [cs], starting a dma transfer. ? in direct mode: setting this bit and mr n [srw] causes a write to the source address register to simultaneously set mr n [cs], starting a dma transfer. clearing this bit and setting mr n [srw] causes a write to the destination address register to simultaneously set mr n [cs], starting a dma transfer. this bit must be cleared when mr n [srw] is cleared. 28 ca channel abort 0 no effect 1 cause the current transfer to be aborted and sr n [cb] to be cleared if the channel is busy. the channel remains in the idle state until a new transfer is programmed. 29 ctm channel transfer mode 0 configure the channel in chaining mode. 1 configure the channel into direct mode. this means that software is responsible for placing all the required parameters into necessary registers to start the dma process. 30 cc channel continue. this bit applies only to chaining mode and is cleared by hardware after the first descriptor read when continuing a transfer. this bit is reserved for external master mode. 0 no effect 1 the dma transfer restarts the transferring process starting at the current descriptor address. 31 cs channel start. this bit is also automatically set by hardware during single-write start mode and external master start enable mode. 0 halt the dma process if channel is busy (sr n [cb] is set). no effect if the channel is not busy. 1 start the dma process if channel is not busy (cb is cleared). if the channel was halted (cs = 0 and cb = 1), the transfer continues from th e point at which it was halted. offset 0x104 0x184 0x204 0x284 access: mixed 0 23 24 25 26 27 28 29 30 31 r ? te ? ch pe eolni cb eosi eolsi ww1c w1c w1c w1c w1c reset all zeros figure 15-5. status registers (sr n ) table 15-5. mr n field descriptions (continued) bits name description 4 datasheet u .com
dma controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 15-12 freescale semiconductor table 15-6 describes the bits of the sr n . 15.3.2.3 current link descript or address registers (clndar n ) current link descriptor address regist ers contain the address of the curren t link descriptor. in basic chaining mode, shown in figure 15-6 , software must initialize these registers to point to the firs t link descriptors in memory. table 15-6. sr n field descriptions bits name description 0?23 ? reserved 24 te transfer error (bit reset, write 1 to clear) 0 no error condition during the dma transfer 1 error condition during the dma transfer. see section 15.4.3, ?dma errors,? for additional information. 25 ? reserved 26 ch channel halted. cleared automatically by hardware if mr n [cs] is set again for resuming a halted transfer 0 channel is not halted. if software at tempts to halt an idle channel (sr n [cb] is cleared), this bit will remain 0. 1 dma transfer was successfully halted by software and can be resumed. 27 pe programming error (bit reset, write 1 to clear) 0 no programming error detected 1 a programming error is detected that prevents the dma transfer from occurring. 28 eolni end-of-links interrupt. after transferring the last block of data in the last link descriptor, if mr n [eolsie] is set, then this bit is set and an interrupt is generated. (bit reset, write 1 to clear) 29 cb channel busy 0 dma transfer is finished, an error occurred, or a channel abort occurred. 1 a dma transfer is currently in progress. 30 eosi end-of-segment interrupt. in chaining mode, after finishing a data transfer, if mr n [eosie] is set or if clndar n [eosie] is set, this bit gets set and an interrupt is generated. in direct mode, if mrn[eosie] is set, this bit gets set and an interrupt is generated. (bit reset, write 1 to clear) 31 eolsi end-of-list interrupt. after transferring the la st block of data in the last list descriptor, if mr n [eolsie] is set, then this bit is set and an interrupt is generated. (bit reset, write 1 to clear) 4 datasheet u .com
dma controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 15-13 figure 15-6. basic chai ning mode flow chart after the current descriptor is proce ssed, the current link descri ptor address register is loaded from the next link descriptor address register and nlndar n [eolnd] in the next link desc riptor address register is examined. if eolnd is zero, the dm a controller reads in the new curr ent link descriptor for processing. if eolnd is set, the last descript or of the list was just completed. if extended chaining mode is not enabled, all dma transfers are comp lete and the dma controller halts. if extended chaining mode is enabled, the dm a controller examines the state of nlsdar n [eolsd] in the next list descriptor address regist er. if eolsd is clear, the controller loads the contents of the next list descriptor address register into the current list descriptor address re gister and reads the new list descriptor from memory. if eolsd is set, all dma transf ers are complete and the dma controller halts. software initializes clndar n with 1st link descriptor 1st link descriptor is processed current link descriptor <- next link descriptor nlndar n [eolnd] set? is n y n extended chaining enabled? is last link descriptor has been processed done ? dma halts y is nlsdar n [eolsd] set? n y clsdar n <- nlsdar n 4 datasheet u .com
dma controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 15-14 freescale semiconductor figure 15-7 shows clndar n. table 15-7 describes the fields of the clndar n . 15.3.2.4 source attributes registers (satr n ) the source attributes registers, shown in figure 15-8 , contain the transaction attr ibutes to be used for the dma operation. stride mode is enabled by setting satr n [ssme]. source read transaction type is specified using satr n [sreadttype]. offset 0x10c 0x18c 0x20c 0x28c access: read/write 0 26 27 28 29 31 r clnda ? eosie ? w reset all zeros figure 15-7. current link descriptor address registers (clndar n ) table 15-7. clndar n field descriptions bits name description 0?26 clnda current link descriptor address. contains the curr ent descriptor address of the buffer descriptor in memory. the descriptor must be aligned to a 32-byte boundary. 27 ? reserved 28 eosie end-of-segment interrupt enable 0 do not generate an interrupt upon completion of the cu rrent dma transfer for the current link descriptor. 1 generate an interrupt upon completion of the current dma transfer for the current link descriptor. 29?31 ? reserved offset 0x110 0x190 0x210 0x290 access: read/write 0 6 7 8 11 12 15 16 31 r ? ssme ? sreadttype ? w reset all zeros figure 15-8. source attributes registers (satr n ) 4 datasheet u .com
dma controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 15-15 table 15-8 describes the fields of the satr n . 15.3.2.5 source address registers (sar n ) the source address registers, shown in figure 15-9 , contain the address from which the dma controller reads data. in direct mode, if mr n [cdsm/swsm] and mr n [srw] are set, a write to this register simultaneously sets mr n [cs], starting a dma transfer. software must ensure that this is a valid address. table 15-9 describes the field of the sar n . table 15-8. satr n field descriptions bits name description 0?6 ? reserved 7 ssme source stride mode enable 0 stride mode disabled 1 stride mode enabled ignored in basic mode (mr n [xfe] is cleared). striding on the source address can be accomplished by enabling satr n [ssme] and setting the desired stride size and distance in the ssr n . 8?11 ? reserved 12?15 sreadttype dma source transaction type. reserved values will result in a programming error being detected and logged in sr[pe]. transaction type to run on local address space 0000?0001 reserved 0011 reserved 0100 read, don?t snoop local processor 0101 read, snoop local processor 0111 read, unlock l2 cache line 1000?1111 reserved 16?31 ? reserved offset 0x114 0x194 0x214 0x294 access: read/write 0 31 r sad w reset all zeros figure 15-9. source address registers (sar n ) table 15-9. sar n field descriptions bits name description 0?31 sad source address. this register contains the source address of the dma transfer. the contents are updated after every dma write operation unless the final stride of a striding operation is less than the stride size, in which case it remains equal to the ad dress from which the last stride began. 4 datasheet u .com
dma controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 15-16 freescale semiconductor 15.3.2.6 destination attributes registers (datr n ) the destination attributes registers, shown in figure 15-10 , contain the transaction attributes for the dma operation. stride mode is enabled by setting datr n [dsme]. destination write transaction type is specified using the datr n [dwritettype] field. the target interface is derived fr om the local access atmu mapping and the transac tion is obtained from the value specified in datr n [dwritettype] using the local address space category. table 15-10 describes the fields of the datr n . 15.3.2.7 destination ad dress registers (dar n ) the destination address registers, shown in figure 15-11 , contain the addresses to which the dma controller wr ites data. in direct mode, if mr n [srw] is set and mr n [cdsm/swsm] is cleared, a write to this register simultaneously sets mr n [cs], starting a dma transfer. software must ensure that this is a valid address. offset 0x118 0x198 0x218 0x298 access: read/write 0 6 7 8 11 12 15 16 31 r ? dsme ? dwritettype ? w reset all zeros figure 15-10. destination attributes registers (datr n ) table 15-10. datr n field descriptions bits name description 0?6 ? reserved 7 dsme destination stride mode enable 0 stride mode disabled 1 stride mode enabled ignored in basic mode (mr n [xfe] is cleared). striding on the destination address can be accomplished by setting dsme and setting the desired stride size and distance in dsr n . 8?11 ? reserved 12?15 dwritettype dma destination transaction type. reserved values will result in a programming error being detected and logged in sr[pe].transaction type to run on local address space 0000?0011 reserved 0100 write, don?t snoop local processor 0101 write, snoop local processor 0110 write, allocate l2 cache line 0111 write, allocate and lock l2 cache line 1000?1111 reserved 16?31 ? reserved 4 datasheet u .com
dma controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 15-17 table 15-11 describes the field of the dar n . 15.3.2.8 byte count registers (bcr n ) the byte count register, shown in figure 15-12 , contains the number of bytes to transfer. table 15-12 describes the fi elds of the bcr n . 15.3.2.9 next link descriptor address registers (nlndar n ) the next link descriptor address registers, shown in figure 15-13 , contain the address for the next link descriptor in memory. contents transferred to the curr ent descriptor address regi sters become effective for the current transfer in basi c and extended chaining modes. offset 0x11c 0x19c 0x21c 0x29c access: read/write 0 31 r dad w reset all zeros figure 15-11. destination address registers (dar n ) table 15-11. dar n field descriptions bits name description 0?31 dad destination address. this register contains the destination address of the dm a transfer. the contents are updated after every dma write operation unless the final stride of a striding operation is less than the stride size, in which case it remains equal to the address from which the last stride began. offset 0x120 0x1a0 0x220 0x2a0 access: read/write 056 31 r ?bc w reset all zeros figure 15-12. byte count registers (bcr n ) table 15-12. bcr n field descriptions bits name description 0?5 ? reserved 6?31 bc byte count. contains the number of bytes to transfer. the value in this register is decremented after each dma read operation. the maximum transfer size is (2 26 ) ? 1 bytes. 4 datasheet u .com
dma controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 15-18 freescale semiconductor table 15-13 describes the fields of the nlndar n registers. 15.3.2.10 current list descript or address registers (clsdar n ) the current list descriptor a ddress registers, shown in figure 15-14 , contain the current address of the list descriptor in memory in extended chaining mode. in extended chaining mode, soft ware must initialize clsdar n to point to the first list descriptor in memory. after finishing the last link descriptor in the current list, th e dma controller loads the contents of the next list descriptor addr ess register into the current list descriptor address register. if nlsdar n [eolsd] in the next list descript or address register is clear, the dma controller reads the new current list descriptor from memory to process that list. if eolsd in the next list de scriptor address register is set and the last link in the current list is finished all dma transfers are complete. offset 0x128 0x1a8 0x228 0x2a8 access: read/write 0 26 27 28 29 30 31 r nlnda ? ndeosie ? eolnd w reset all zeros figure 15-13. next link descriptor address registers (nlndar n ) table 15-13. nlndar n field descriptions bits name description 0?26 nlnda next link descriptor address. contains the next li nk descriptor address in memory. the descriptor must be aligned to a 32-byte boundary. 27 ? reserved 28 ndeosie next descriptor end-of-segment interrupt enable 0 do not generate an interrupt if the current dma transfer for the current descriptor is finished. 1 generate an interrupt if the current dma transfer for the current descriptor is finished. 29?30 ? reserved 31 eolnd end-of-links descriptor. this bit is ignored in direct mode. 0 this descriptor is not the last link descriptor in memory for this list. 1 this descriptor is the last link descriptor in memory for this list. if this bit is set, the dma controller advances to the next list descriptor in memory if nlsdar n [eolsd] is also set in extended mode. offset 0x134 0x1b4 0x234 0x2b4 access: read/write 0 26 27 31 r clsda ? w reset all zeros figure 15-14. current list descriptor address registers (clsdar n ) 4 datasheet u .com
dma controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 15-19 table 15-14 describes the fields of the clsdar n . 15.3.2.11 next list descriptor address registers (nlsdar n ) the next list descriptor a ddress registers, shown in figure 15-15 , contain the address for the next list descriptor in memory. if the contents are transferred to the current list descriptor address register they become effective for the current tr ansfer in extended chaining mode. table 15-15 describes the fields of the nlsdar n . 15.3.2.12 source stride registers (ssr n ) the source stride register, shown in figure 15-16 , contains the stride size and di stance. note that the source stride information is loaded when a new list descriptor is read from memory. theref ore, the source stride register is applicable for all link descriptors in th e new list. changing the source stride information for a link requires that a new list be generated. table 15-14. clsdar n field descriptions bits name description 0?26 clsda current list descriptor addr ess. contains the current list descripto r address of the buffer descriptor in memory in extended chaining mode. the descriptor must be aligned to a 32-byte boundary. 27?31 ? reserved offset 0x13c 0x1bc 0x23c 0x2bc access: mixed 0 26 27 30 31 r nlsda ? eolsd w reset all zeros figure 15-15. next list descriptor address registers (nlsdar n ) table 15-15. nlsdar n field descriptions bits name description 0?26 nlsda next list descriptor address. contains the next descriptor address of the buffer descriptor in memory. the descriptor must be aligned on a 32-byte boundary. 27?30 ? reserved 31 eolsd end-of-lists descriptor. this bit is ignored in direct mode. 0 this list descriptor is not the la st list descriptor in memory. 1 this list descriptor is the la st list descriptor in memory. if this bit is set, then the dma controller halts after the last link descriptor transaction is finished. 4 datasheet u .com
dma controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 15-20 freescale semiconductor table 15-16 describes the fields of the ssr n . 15.3.2.13 destination stride registers (dsr n ) the destination stride regi ster contains the stride size, and dist ance. note that the destination stride information is loaded when a new list descriptor is read from memory. therefor e, the destination stride register is applicable for all link descriptors in the ne w list. changing the destinat ion stride information for a link requires that a new list be generated. figure 15-17 describes the dsr n . table 15-17 describes the fi elds of the dsr n . offset 0x140 0x1c0 0x240 0x2c0 access: read/write 078 1920 31 r ? sss ssd w reset all zeros figure 15-16. source stride registers (ssr n ) table 15-16. ssr n field descriptions bits name description 0?7 ? reserved 8?19 sss source stride size. number of bytes to transfer befor e jumping to the next address as specified in the source stride distance field. 20?31 ssd source stride distance. the source stride distance in bytes from start byte to start byte. offset 0x144 0x1c4 0x244 0x2c4 access: read/write 078 1920 31 r ?dss dsd w reset all zeros figure 15-17. destination stride registers (dsr n ) table 15-17. dsr n field descriptions bits name description 0?7 ? reserved 8?19 dss destination stride size. number of bytes to transfe r before jumping to the next address as specified in the destination stride distance field. 20?31 dsd destination stride distance. the destination stride distance in bytes from start byte to start byte. 4 datasheet u .com
dma controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 15-21 15.3.2.14 dma general st atus register (dgsr) the dma general status register combines all of the st atus bits from each channe l into one register. this register is read-only. figure 15-18 describes the dgsr. table 15-18 describes the fiel ds of the dgsr. offset 0x300 access: read only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rte0 ? ch0 pe0 eolni0 cb0 eosi0 eolsi0 te1 ? ch1 pe1 eolni1 cb1 eosi1 eolsi1 w reset all zeros 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rte2 ? ch2 pe2 eolni2 cb2 eosi2 eolsi2 te3 ? ch3 pe3 eolni3 cb3 eosi3 eolsi3 w reset all zeros figure 15-18. dma general status register (dgsr) table 15-18. dgsr field descriptions bits name description 0 te0 transfer error, channel 0 0 normal operation 1 an error condition occurred during the dma transfer. 1?reserved 2 ch0 channel halted, channel 0 3 pe0 programming error, channel 0 4 eolni0 end-of-links interrupt, channel 0 5 cb0 channel busy, channel 0 6 eosi0 end-of-segment interrupt, channel 0 7 eolsi0 end-of-lists/direct interrupt, channel 0 8 te1 transfer error, channel 1 0 normal operation 1 an error condition occurred during the dma transfer. 9?reserved 10 ch1 channel halted, channel 1 11 pe1 programming error, channel 1 12 eolni1 end-of-links interrupt, channel 1 13 cb1 channel busy, channel 1 14 eosi1 end-of-segment interrupt, channel 1 15 eolsi1 end-of-lists/direct interrupt, channel 1 4 datasheet u .com
dma controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 15-22 freescale semiconductor 15.4 functional description this section describes the f unction of the dma controller. 15.4.1 dma channel operation all dma channels support tw o different modes of oper ation: a basic mode (mr n [xfe] is cleared) and an extended mode (mr n [xfe] is set). in both modes, a channel can be activated by clearing and setting mr n [cs], or through the single -write start mode using mr n [cdsm/swsm] and mr n [srw], or through an external control mode using mr n [ecs_en]. in basic mode, the channel can be programmed in basi c direct mode or basic chaining mode. in extended mode, the channel can be programmed in extended direct mode or extende d chaining mode. extended mode provides more capabilities, such as extended de scriptor chaining, striding capabilities, and a more flexible descriptor structure. the dma controller supports misali gned transfers for both the source and destination addresses. in order to maximize performance, the source and destination engi nes align the sour ce and destinati on addresses to a 64-byte boundary. the dma alwa ys reads/writes the maximum number of bytes for a given transfer as 16 te2 transfer error, channel 2 0 normal operation 1 an error condition occurred during the dma transfer. 17 ? reserved 18 ch2 channel halted, channel 2 19 pe2 programming error, channel 2 20 eolni2 end-of-links interrupt, channel 2 21 cb2 channel busy, channel 2 22 eosi2 end-of-segment interrupt, channel 2 23 eolsi2 end-of-lists/direct interrupt, channel 2 24 te3 transfer error, channel 3 0 normal operation 1 an error condition occurred during the dma transfer. 25 ? reserved 26 ch3 channel halted, channel 3 27 pe3 programming error, channel 3 28 eolni3 end-of-links interrupt, channel 3 29 cb3 channel busy, channel 3 30 eosi3 end-of-segment interrupt, channel 3 31 eolsi3 end-of-lists/direct interrupt, channel 3 table 15-18. dgsr field descriptions (continued) bits name description 4 datasheet u .com
dma controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 15-23 described by the capability inputs of the dma controller except for globally cohere nt transactions that use the size of the cache cohere nce granule as described by the mode select input. the dma controller supports bandwidth control, whic h prevents a channel from consuming all the data bandwidth in the controller. each channel is allowed to consume the bandwidth of the shared resources as specified by the bandwidth control va lue. after the channel uses its al lotted bandwidth, th e arbiter grants the next channel access to the shared resources. the arbitr ation is round robin betw een the channels. this feature is also used to im plement the external control pause feature. if the extern al control start and pause are enabled in the mr n , the channel enters a paused state afte r transferring the data described in the bandwidth control. external control can restart the ch annel from a paused state. the dma programming model permits so ftware to program each dma engi ne independently to interrupt on completed segment, chain, or error. it also provi des the capability for software to resume the dma engine from a hardware ha lted condition by setting the channel continue bit, mr n [cc]. see table 15-19 for more complete descriptions of th e channel states and state transitions. 15.4.1.1 basic dma mode transfer this mode is primarily included for backward comp atibility with existing dma controllers which use a simple programming model. this is the default mode out of reset. th e different modes of operation under the basic mode are explaine d in the following sections. 15.4.1.1.1 basic direct mode in basic direct mode, the dma controller does not r ead descriptors from memory, but instead uses the current parameters programmed in the dma registers to start the dma transfer. software is responsible for initializing sar n , satr n , dar n , datr n , and bcr n registers. the dma transfer is started when mr n [cs] is set. software is expected to pr ogram all the appropriate re gisters before setting mr n [cs] to a 1. the transfer is finished after al l the bytes specified in the byte count register have been transferred or if an error condition occurs. the sequence of events to start and complete a transf er in basic direct mode is as follows: 1. poll the channel state (see table 15-19 ), to confirm that the specific dma channel is idle. 2. initialize sar n , satr n , dar n , datr n and bcr n . 3. set the mode register cha nnel transfer mode bit, mr n [ctm], to indicate dir ect mode. other control parameters may also be initia lized in the mode register. 4. clear then set the mode register channel start bit, mr n [cs], to start the dma transfer. 5. sr n [cb] is set by the dma controller to i ndicate the dma transfer is in progress. 6. sr n [cb] is automatically cleared by the dma controll er after the transfer is finished, or if the transfer is aborted (mr n [ca] transitions from a 0 to 1), or if a transfer error occurs. 7. end of segment interru pt is generated if mr n [eosie] is set. 15.4.1.1.2 basic direct single-write start mode in basic direct single-write star t mode, the dma controller does not read descriptors from memory, but instead uses the current parameters programmed in th e dma registers to start the dma transfer. software is responsible for initializing the satr n , datr n , and bcr n registers. setting mr n [srw] configures the 4 datasheet u .com
dma controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 15-24 freescale semiconductor dma controller to begin the dm a transfer either when sar n is written or when dar n is written, determined by the state of mr n [cdsm/swsm]. writing to sar n initiates the dma transfer if mr n [cdsm/swsm] is set. writing to dar n initiates the dma transfer if mr n [cdsm/swsm] is cleared. the dma controller automatica lly sets the channel start bit, mr n [cs]. software is expected to program all the appropriate registers before writing the source or destination a ddress registers. the transfer is finished after all the bytes speci fied in the byte count register have been transferred or if an error condition occurs. the sequence of events to start and complete a tran sfer in single-write start basic direct mode is as follows: 1. poll the channel state (see table 15-19 ), to confirm that the specific dma channel is idle. 2. initialize the sour ce attributes (satr n ), datr n , and bcr n registers. 3. set the mode register cha nnel transfer mode bit, mr n [ctm], and the single-wr ite start direct mode bit, mr n [srw]. other control parameters may also be initialized in the mode register. set mr n [cdsm/swsm] for transfers started using sar n . clear mr n [cdsm/swsm] for transfers started using the dar n . 4. a write to the source or destination address regist er starts the dma transfer and automatically sets mr n [cs]. 5. sr n [cb] is set by the dma controller to i ndicate the dma transfer is in progress. 6. sr n [cb] is automatically cleared by the dma controll er after the transfer is finished, or if the transfer is aborted (mr n [ca] transitions from a 0 to 1), or if a transfer error occurs. 7. end of segment interru pt is generated if mr n [eosie] is set. 15.4.1.1.3 basic chaining mode in basic chaining mode, software must first build li nk descriptor segments in memory. then the current link descriptor address register must be initialized to point to the first descriptor in memory. the dma controller loads descriptors from me mory prior to a dma transfer. the dma controller begins the transfer according to the link descriptor information loaded fo r the segment. after the current segment is finished, the dma controller reads the next link descriptor from memory and begins another dma transfer. the transfer is finished if the current link descriptor is the last one in memory or if an error condition occurs. the sequence of events to start and complete a transfer in chaining mode is as follows: 1. build link descriptor segments in memory. 2. poll the channel state (see table 15-19 ), to confirm that the specific dma channel is idle. 3. initialize clndar n to point to the first link descriptor in memory. 4. clear the mode register ch annel transfer mode bit, mr n [ctm], as well as mr n [xfe], to indicate basic chaining mode. other contro l parameters may also be ini tialized in the mode register. 5. clear, then set the mode register channel start bit, mr n [cs], to start the dma transfer. 6. sr n [cb] is set by the dma controller to i ndicate the dma transfer is in progress. 7. sr n [cb] is automatically cleared by the dma controll er after finishing the transfer of the last descriptor segment, or if the transfer is aborted (mr n [ca] transitions from a 0 to 1), or if an error occurs during any of the transfers. 4 datasheet u .com
dma controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 15-25 15.4.1.1.4 basic chaining si ngle-write start mode basic chaining single-write start mode allows a chain to be started by writing the current link descriptor address register (clndar n ). setting mr n [cdsm/swsm] in the mode register causes mr n [cs] to be automatically set when the current lin k descriptor address register is wr itten. the sequence of events to start and complete a chain using sing le-write start mode is as follows: 1. set the mode register current descriptor start mode bit, mr n [cdsm/swsm], and the extended features enable bit mr n [xfe]. also, clear the chan nel transfer mode bit, mr n [ctm]. this initialization indicates basic chai ning and single-write start mode. also other control parameters may be initialized in the mode register. 2. build link descriptor segments in memory. 3. poll the channel state (see table 15-19 ), to confirm that the specific dma channel is idle. 4. initialize clndar n to point to the first descriptor segm ent in memory. this write automatically causes the dma controller to begin the link descriptor fetch and set mr n [cs]. 5. sr n [cb] is set by the dma controller to i ndicate the dma transfer is in progress. 6. sr n [cb] is automatically cleared by the dma controll er after finishing the transfer of the last descriptor segment, or if the transfer is aborted (mr n [ca] transitions from a 0 to 1), or if an error occurs during any of the transfers. 15.4.1.2 extended dma mode transfer the extended dma mode also operates in chaining and direct mode. it offers additional capability over the basic mode by supporting striding and a more fl exible descriptor stru cture. this additional functionality also requi res a new and more complex programmi ng model. the extended dma mode is activated by setting mr n [xfe]. 15.4.1.2.1 extended direct mode extended direct mode has the same functionality as basic direct mode with the addition of stride capabilities. the bit settings are the same as in direct mode with the exception of the mr n [xfe] being set. striding on the source address can be accomplished by setting satr n [ssme] and setting the desired stride size and distance in ssr n . striding on the destination addre ss can be accomplished by setting datr n [dsme] and setting the desired st ride size and distance in dsr n . 15.4.1.2.2 extended direct single-write start mode extended direct single-write start mo de has the same functionality as the basic direct single-write start mode with the addition of stride capabilities. the bi t settings are also the same with the exception of mr n [xfe] being set. striding on the source address can be accomplished by setting satr n [ssme] and setting the desired stride size and distance in ssr n . striding on the destination address can be accomplished by setting datr n [dsme] and setting the desired st ride size and distance in dsr n . 15.4.1.2.3 extended chaining mode in extended chaining mode, the software must first build list and link desc riptor segments in memory. then clsdar n must be initialized to point to the first list descriptor in me mory. the dma controller loads list 4 datasheet u .com
dma controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 15-26 freescale semiconductor descriptors and link descriptors from memory prior to a dma transfer . the dma controller begins the transfer according to the link descriptor information lo aded. once the current link descriptor is finished, the dma controller reads the next link descriptor fr om memory and begins another dma transfer. if the current link descriptor is the last in the list, the dma controller reads th e next list descriptor in memory. the transfer is finished if the current link descriptor is the last one in the last list in memory or if an error condition occurs. the sequence of events to start and complete a transfer in extended chaining mode is as follows: 1. build link and list descriptor segments in memory. 2. poll the channel state (see table 15-19 ), to confirm that the specific dma channel is idle. 3. initialize clsdar n to point to the first li st descriptor in memory. 4. clear the mode register ch annel transfer mode bit, mr n [ctm], to indicate chaining mode. mr n [xfe] must be set to indicate extended dma mode. other control parameters may also be initialized in the mode register. 5. clear, then set the mode register channel start bit, mr n [cs], to start the dma transfer. 6. sr n [cb] is set by the dma controller to i ndicate the dma transfer is in progress. 7. sr n [cb] is automatically cleared by the dma controll er after finishing the transfer of the last descriptor segment, or if the transfer is aborted (mr n [ca] transitions from a 0 to 1), or if an error occurs during any of the transfers. 15.4.1.2.4 extended chaining single-write start mode in the extended mode, the si ngle-write start f eature allows a chain to be st arted by writing the current list descriptor pointer. setting mr n [cdsm/swsm] causes mr n [cs] to be set automatically when clsdar n is written. the sequence of even ts to start and complete an extended chain using single-write start mode is as follows: 1. set mr n [cdsm/swsm], mr n [ctm], and mr n [xfe] to indicate extended chaining and single-write start mode. also othe r control parameters may be init ialized in the mode register. 2. build list and link descriptor segments in local memory. 3. poll the channel state (see table 15-19 ), to confirm that the specific dma channel is idle. 4. initialize the current list descript or address register to point to the first list descriptor segment in memory. this write automatically ca uses the dma controller to begin the list descriptor fetch and set mr n [cs]. 5. sr n [cb] is set by the dma controller to i ndicate the dma transfer is in progress. 6. sr n [cb] is automatically cleared by the dma controll er after finishing the transfer of the last descriptor segment, or if the transfer is aborted (mr n [ca] transitions from a 0 to 1), or if an error occurs during any of the transfers. 15.4.1.3 external control mode transfer an external control can be used to control all dma channels by setting mr n [ems_en]. the external control can control the dma channel in the following transfer modes: ? basic direct 4 datasheet u .com
dma controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 15-27 ? basic chaining ? extended direct ? extended chaining note that when operating the dma in chaining mode, the register byt e count field, bcr[bc], must be initialized to zero before enabling the pause featur e. in chaining modes, the channel does not pause for descriptor fetch transfer. the external control and the dma controller use a well defined protocol to communicate. the external control can start or restar t a paused dma transfer. the dma controller acknowle dges a dma transfer in progress and also indicate s a transfer completion. the pause feature can be enabled by setting mr n [emp_en]. mr n [bwc] specifies how much data to allow a specific channel to transfer befo re entering a paused state by clearing mr n [cs]. note, however, that write data for a paused transfer may not have reached the target interface when so indicated. the channel can be restarted from a paused state by the asserted edge of dreq as driven by an external master. in chaining modes, the channel does not pause for descriptor fetch transfer . it only pauses during the actual data transfer. the following signals are defined fo r the external control interface: ? dma_dreq - asserting edge triggers a dma transfer st art or restart from a pause request. sets mr n [cs]. ? dma_dack - indicates a dma transfer currently in progress. sr n [cb] is set. ? dma_ddone - indicates the completion of the dma controller?s involve ment in the transfer and the readiness to accept a new dma command. sr n [cb] is clear. note, how ever, that write data may still be queued at the target interface or in the process of transfer on an external interface. detailed descriptions of the ex ternal control interface are in table 15-3 . the timing diagram of the external control interface is shown in figure 15-19 . figure 15-19. external control interface timing dreq clock dack ddone transfer start transfer in progress transfer done transfer start transfer pause transfer restart emp_en 4 datasheet u .com
dma controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 15-28 freescale semiconductor 15.4.1.4 channel continue mode for cascading transfer chains the channel continue mode (enabled when mr n [cc] is set) offers software the flexibility of having the dma controller get started on descri ptors that have already been pr ogrammed while software continues to build more descriptors in memory. software can se t the end-of-links descript or (eolnd) in basic mode, or end-of-lists descriptor (eolsd) in extended mode, to cause the channe l to go into a halted state while software continues to build other de scriptors in memory. software can then set cc to force hardware to continue where it left off. channel continue is only meaningful for chaining modes, not direct mode. if cc is set by software while the ch annel is busy with a transfer, the dm a controller finishes all transfers until it reaches the eolnd in ba sic mode or eolsd in extended mode. the dma controller then refetches the last link descriptor in basic mode, or the last list descript or in extended mode and clears the channel continue bit. if eolnd or eolsd is still set for their resp ective modes, the dma controller remains in the idle state. if eolnd or eolsd is not set, the dma controller continues the transfer by refetching the new descriptor. if cc is set by software while the ch annel is not busy with a transfer, th e dma controller refetches the last link descriptor in basic mode, or th e last list descriptor in extended mode and clears the channel continue bit. if eolnd or eolsd is still set for their respec tive modes, the dma controller remains in the idle state. if the eolnd or eolsd bits are not set, th e dma controller continues the transfer by refetching the new descriptor. 15.4.1.4.1 basic mode on a channel continue, the descriptor at the current link descriptor address register (clndar n ) is refetched to get the next link de scriptor address field as updated by software. the channel halts if nlndar n [eolnd] is still set. if eolnd is zero, the next link descriptor address is copied into clndar n and the channel continues with another descriptor fetch of the current link descriptor address. as a result, two link descriptor fetche s always exist after channel continue before starting the first transfer. 15.4.1.4.2 extended mode on a channel continue, the descriptor at the curren t list descriptor (clsdar n ) address register is refetched to get the next list descriptor address fiel d as updated by software. the channel halts if nlsdar n [eolsd] is still set. if not, the next list descriptor address is copied into the clsdar n register and the channel continues with another descriptor fetch of the current list descriptor address. as a result, two list descriptor fetches al ways exist after channel continue before the first link descriptor fetch and the first transfer. 15.4.1.5 channel abort software can abort a previously initiated transfer by setting mr n [ca]. once the dma channel controller detects a zero-to-one transition of mr n [ca], it finishes the current sub-bl ock transfer and halts all further activity. the controller then waits fo r all previously initiated transfers from the specified channel to drain and clears sr n [cb]. successful completion of a software initiated abort request can be recognized by mr n [ca] being set and sr n [cb] being cleared. obviously, if the controller was already halted because of an error condition (sr n [te] is set), or the channel has completed all transfers, then sr n [cb] being cleared may not signify that the controller en tered a halt state due to the abort request. 4 datasheet u .com
dma controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 15-29 15.4.1.6 bandwidth control mr n [bwc] specifies how much data to allow a specifi c channel to transfer before allowing the next channel to use the shared data transfer hardware. this promotes eq uitable bandwidth allocation between channels. however, if only one channel is busy, hard ware overrides the specified bandwidth control size value. the dma controller allows a channel to transfer up to 1 kbyte at a time when no other channel is active. 15.4.1.7 channel state table 15-19 defines the state of a channel based on the values of the channel start (mr n [cs]), channel busy (sr n [cb]), transfer error (sr n [te]), and channel continue (mr n [cc]) bits. 15.4.1.8 illustration of stride size and stride distance if operating in stride mode, the stride size defines the am ount of data to transfer before jumping to the next quantity of data as specified by the st ride distance. the stride distance is added to the current base address to point to the next quantity of data to be transferred. figure 15-20 illustrates the stride size and distance parameters. as shown, each time the stride distance is added to the ba se address, the resulting address becomes the new base address. this sequence repeats until the amount of data transferred equals the transfer size. table 15-19. channel state table mr n [cs] sr n [cb] sr n [te] mr n [cc] channel state 0000idle state. this is the state of the bits out of reset. 0001channel continue unexpected. channel remains idle 0010error occurred after software halted the channel. 0011channel continue unexpected. channel remains in error halt state 0100software halted ch annel. the channel was busy and software cleared mr n [cs]. 0101channel remains in halt state. ? 1 1 ? the channel has encountered an error condition and it is trying to halt. 1000ready to start a transfer, or transfer completed 1001continue transfer (only meaningful in chaining mode, not direct mode). in direct mode, the channel continue has no effect. 1010error occurred during transfer 1011channel remains in error halt state 1100transfer in progress 1101continue after reaching the end of list/link, or the first descriptor fetch after cha nnel continue 4 datasheet u .com
dma controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 15-30 freescale semiconductor figure 15-20. stride size and stride distance 15.4.2 dma transfer interfaces the dma can be used to achieve data tr ansfers across the entire memory map. 15.4.3 dma errors on a transfer error (uncorrectable ecc errors on me mory accesses, parity errors on local bus or pci, address mapping errors, for example), the dma halts by setting sr n [te] and generates an interrupt if mr n [eie] is set. on a programming error, the dma sets sr n [pe] and generates an interrupt if mr n [eie] is set. the dma controller detect s the following programming errors: ? transfer started with a byte count of zero ? stride transfer started w ith a stride size of zero ? transfer started with a priority of three ? illegal type, defined by satr n [sreadttype] and datr n [dwritettype], used for the transfer. 15.4.4 dma descriptors the dma engine recognizes list desc riptors and link descriptors. list descriptors connect lists of link descriptors. link descriptor s describe the dma activity that is to take place. dm a descriptors are built in either local or remote memory a nd are connected by the next descript or fields. only link descriptors contain information for the dma contro ller to transfer data. software must ensure that each descriptor is 32-byte aligned. the last link descriptor in the last list in memory se ts the eolnd bit in the next link descriptor; the next list de scriptor fields indicating th at these are the last descriptors in memory. software initializes the current list descriptor address register to point to the first list descriptor in memory. the dma controller traverses through the descriptor lists unt il the last link descriptor is met. for each link descriptor in the chain, the dma controller starts a new dma transfer with the control parameters specified by that descriptor. link and list descriptor fetches alwa ys snoop the local memory space. note software must ensure that each desc riptor is aligned on a 32-byte boundary. the last link descriptor in the la st list in memory sets nlndar n [eolnd] in the next link descriptor and nlsdar n [eolsd] in the next list descript or fields indicating that thes e are the last descriptors in memory. software initializes the curren t list descriptor address register to point to th e first list descriptor in memory. the dma controller traverses through the desc riptor lists until the last link descriptor is met stride size stride distance base address new base address new base address 4 datasheet u .com
dma controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 15-31 as shown in figure 15-21 . for each link descriptor in the chai n, the dma controller starts a new dma transfer with the control paramete rs specified by that descriptor. table 15-20 summarizes the dma list descriptors. table 15-21 summarizes the dma link descriptors. table 15-20. list dma descriptor summary descriptor field description next list descriptor address points to the next list descriptor in memory. afte r the dma controller reads the descriptor from memory, this field is loaded into the next list descriptor address registers. first link descriptor address points to the first link descriptor in memory for this list. after the dma controller reads the descriptor from memory, this field is loaded into the current link descriptor address registers. source stride contains the stride information used for the data source if striding is enabled for a link in the list destination stride contains the stride information used for the data destination if striding is enabled for a link in the list table 15-21. link dma descriptor summary descriptor field description source attributes register contains source transaction attributes source address contains the source address of the dma tr ansfer. after the dma controller reads the descriptor from memory, this field is loaded into the source address register. destination attributes register contai ns destination transaction attributes destination address contains the destination address of the dma transfer. after the dma controller reads the descriptor from memory, this field is loaded into the destination address register. next link descriptor address points to the next link descriptor in memory. after t he dma controller reads the link descriptor from memory, this field is loaded into the next link descriptor address registers. byte count contains the number of bytes to transfer. after the dma controller reads the descriptor from memory, this field is loaded into the byte count register. 4 datasheet u .com
dma controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 15-32 freescale semiconductor figure 15-21 describes the dma transaction flow. figure 15-21. dma transaction flow with dma descriptors current list descriptor address register . . . list descriptor link descriptor link descriptor link descriptor (eolnd) list descriptor descriptors in memory dma controller flow (extended mode) mr n [cs] is set by software after programming start finish fetch the first list descriptor using the clsdar n address write nlsdar n , clndar n fetch the first link descriptor write programming model registers begin dma transfer using sar n , satr n , dar n , datr n after transfer check if nlndar n [eolnd] is set move nlndar n to clndar n fetch the current link descriptor write programming model registers begin dma transfer using sar n , satr n , dar n , datr n after dma transfer check if nlndar n [eolnd] is set check if nlsdar n [eolsd] is set move nlsdar n to clsdar n fetch the current list descriptor write nlsdar n , clndar n move nlndar n to clndar n fetch the first link descriptor write programming model registers begin dma transfer using sar n , satr n , dar n , datr n after dma transfer check if nlndar n [eolnd] is set move nlndar n to clndar n fetch the current link descriptor write programming model registers begin dma transfer using sar n , satr n , dar n , datr n after dma transfer check if nlndar n [eolnd] is set check if nlsdar n [eolsd] is set move nlsdar n to clsdar n fetch the current list descriptor write nlsdar n , clndar n fetch the first link descriptor write programming model registers begin dma transfer using sar n , satr n , dar n , datr n after dma transfer check if nlndar n [eolnd] is set move nlndar n to clndar n fetch the current link descriptor write programming model registers begin dma transfer using sar n , satr n , dar n , datr n after dma transfer check if nlndar n [eolnd] is set check if nlsdar n [eolsd] is set clear sr n [cb] dma transfer complete . . link descriptor link descriptor link descriptor (eolnd) list descriptor . link descriptor link descriptor link descriptor (eolnd/eolsd) . descriptors in memory 4 datasheet u .com
dma controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 15-33 figure 15-22 describes the format of the list descriptors. figure 15-22. list descriptor format figure 15-23 describes the format of the link descriptors. figure 15-23. link descriptor format 15.4.5 limitations and restrictions this section addresses some of the limitations and restricti ons of the dma controll er and is intended to help software maximize the dma perfor mance and avoid dma programming errors. the limitations of the dma c ontroller are the following: ? due to the limited number of buffers that the dma controller can use, stride sizes less than 64 bytes should be avoided. maximum utilization is obtained from strides greater than or equal to 256 bytes. however, small stride sizes can be used for scatter-gather functions. ? coherent reads or writes are broken up into cache line accesses in the dma. the dma controller restrictions are as follows: ? all interface capabilities from where descriptor s are being fetched must support read sizes of 32 bytes or greater. ?if mr n [sahe] is set, the source interface transfer si ze capability must be gr eater than or equal to mr n [sahts]. the source address must be al igned to a size specified by sahts. reserved next list descriptor address reserved first link descriptor address source stride destination stride reserved reserved offset 0x00 0x08 0x18 0x10 0x04 0x14 0x0c 0x1c byte count reserved source attributes destination attributes offset 0x00 0x08 0x18 0x10 0x04 source address next link descriptor address 0x14 0x0c destination address reserved 0x1c 4 datasheet u .com
dma controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 15-34 freescale semiconductor ?if mr n [dahe] is set, the destination interface transf er size capability must be greater than or equal to mr n [dahts]. the destination address must be aligned to the size specified by dahts. ? destination striding is not supported if mr n [dahe] is set and source striding is not supported if mr n [sahe] is set. 15.5 dma system considerations figure 15-24 shows the most important data paths within the MPC8555E. many of these paths are served by captive dma controllers and virtually all can be served by the general purpose four-channel dma controller. this section provides information about how to make most effective use of these dma channels including the following topics: ? dma transaction initiators (masters) ? dma targets, that is, da ta sources and destinations ? transparency of the bus in terfaces to dma operations ? what is useful as opposed to what is possible. fo r example, it is possible to address any internal register through the internal control bus, which m eans configuration and co ntrol registers can be dma source or destination targets. however, the typical use of dma functionality is to reduce host processor loading by moving large amounts of data with mi nimal cpu involvement. using a general-purpose dma controller to load small amounts of configur ation data only makes sense in special circumstances (perhaps du ring system boot, for example). 4 datasheet u .com
dma controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 15-35 figure 15-24. dma data paths table 15-22 lists all of the dma controller s (both captive and general-purpos e) on the device and the most likely dma targets on and off-chip. the bus controller s themselves cannot initiate dma transfers; rather, they operate transparently with respect to both on- a nd off-chip dma controllers. the codes in the table cells have the following meaning: ? y?supported ? nr?possible, but not recommended. in efficient use of system resources ? ns?possible, but not supported. resulti ng system behavior is not defined ocean local-dma tdms ddr sdram bus ddr sdram controller dpram i-memory cpm serial interface mphy miis/ i/os fcc fcc scc scc/usb scc smc smc spi i 2 c time slot assigner e500 core l2-cache parallel i/o baud rate generators timers local bus controller system-dma 64/32b pci controller ext dma pins cpm interrupt controller i 2 c dma (4-channel) controller boot sequencer register and control pci bus local bus risc e500 coherency module mcm serial dma open pic duart serial in/out rom rmiis utopia 0/32b pci controller pci bus 10/100/1000 mac 10/100/1000 mac mii, gmii, tbi, rtbi, rgmiis 4 datasheet u .com
dma controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 15-36 freescale semiconductor 15.5.1 unusual dma scenarios the following is a description of unusual dma path s including explanations of why some functional blocks cannot serve as dma targets. the following topics are addressed: ? transaction initiators (masters) ? dma targets, that is, da ta sources or destinations ? transparency of the bus cont rollers to dma transactions ? what is useful as opposed to what is possible. fo r example, any register can be addressed through an internal control bus, which means configurat ion and control registers can be dma targets. 15.5.1.1 dma to core the l1 cache cannot be a direct dma target because it cannot be directly addre ssed by software. however, dma access into the l1 cache occurs indi rectly if a block of memory that is cached in the l1 is specified as the dma target. this effect is deterministic if the target memory block was locked into the l1 with cache locking instructions. 15.5.1.2 dma to cpm the cpm?s dual port ram (dpram) can serve as bot h a source and destination for general-purpose dma transfers. however, because the cpm has its own dedicated dma controll er, using an external dma controller to access the dpram makes little sense except in special circumstances (such as, possibly, during syst em initialization). 15.5.1.3 dma to ethernet the ethernet controllers cannot serve as dma targets because they have no suitable internal memory for this purpose. the ethernet controll ers have dedicated dma channels to move data between the external transmit and receive buffers and the internal packet buffer. this dedicat ed channel is the only dma service to the internal packet buffers. table 15-22. MPC8555E dma paths dma controllers on-chip targets off-chip targets l2 cpm dpram configuration registers ddr local bus pci duart fifo ethernet buffers on-chip cpm ynr ns yyyy y ethernet yns ns yyyy y 4-channel y y nr yyyy ns off-chip pci controller yy ns yy?y y note: on-chip target configuration registers include i 2 c data register. on-chip cpm and ethernet are captive resources. not available to external masters. on-chip 4-channel controller can serve external masters. 4 datasheet u .com
dma controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 15-37 however, ethernet ports can serve as dma targets by using a general-purpose dma controller to access the transmit and receive buffers defi ned by the ethernet buffer descriptor s. because ethernet data buffers are located in ram outside of the ethernet controll ers, general-purpose dma e ngines can move data to or from these memory regions. also, because ethernet controllers automatically read buffer descriptors and send (or load) data buffers, a dma transfer into (or out of) these buffers is effectively a transfer into (or out of) the ethernet ports. 15.5.1.4 dma to configuration and control registers because any internal register can be addressed with the four-channel dma controller, configuration and control registers throughout the devi ce are valid dma targets. however, the primary purpose of dma?to reduce processor load by moving larg e blocks of data? is not served by dma transfers of configuration data. for example, while it is possible to dma into the i 2 c controller or programma ble interrupt controller (pic), doing so is extremely ineffi cient and is seldom beneficial in normal operation. the overhead of creating dma descriptors far exc eeds any savings in cpu cycles. 15.5.1.5 dma to i 2 c the i 2 c controller is not transparent to dma tr ansfers. observe the caveats listed in section 15.5.1.4, ?dma to configuration and control registers,? when accessing any i 2 c register, including the data register (i2cdr). 15.5.1.6 dma to duart the duart provides complete and sophisti cated dma support which is described in chapter 12, ?duart,? specifically, section 12.4.5, ?fifo mode.? 4 datasheet u .com
dma controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 15-38 freescale semiconductor 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 16-1 chapter 16 pci bus interface the MPC8555E pci interface complies with the pci local bus specification , rev. 2.2. it is beyond the scope of this manual to document the intricacies of th e pci. this chapter describes the pci controller of this device and provides a basic description of the pc i bus operations. the specif ic emphasis is directed at how the MPC8555E implements the pci. designers of systems incorporating pci devices should refer to the respective specification for a thorough description of the pci buses. note much of the available pci literature refers to a 16- bit quantity as a word and a 32-bit quantity as a dword. note th at this is inconsistent with the terminology in the rest of this manua l where the terms ?word? and ?double word? refer to a 32-bit and 64-bit quan tity, respectively. where necessary to avoid confusion, the precise number of bits or bytes is specified. 16.1 introduction the pci controller acts as a bridge between the pci interface and the ocean switch fabric. figure 16-1 is a high-level block diagram of the pci controller. 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 16-2 freescale semiconductor figure 16-1. pci controller block diagram 16.1.1 overview the pci controller connects the oc ean to the pci bus, to which i/o components are connected. the pci bus uses a 32- or 64-bit multiplexed address/data bus, plus various control and error signals. the pci interface supports address and data pa rity with error checking and reporting. the pci interface of the MPC8555E functions both as a ma ster (initiator) and a target device. internally, the design is divided into the following: ? data path blocks ? control logic blocks ? memory the data path blocks contain the queues, tables for tran saction tracking, and orde ring. the control blocks contain control logic and state-machines for buffer c ontrol, bus protocol, tag generation, and transaction resizing. the memory blocks are used solely for inbound and outbound data storage. ocean physical interface arb arb pci pci regs regs ocean gasket ocean gasket pci1 interface pci2 interface pci bus interface 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 16-3 this allows the MPC8555E to handle separate pci transacti ons simultaneously. for example, consider the case where a burst-write transact ion from the MPC8555E to anothe r pci device terminates with a disconnect before finishi ng the transaction. if another pci device is granted the pci bus and requests a burst-read from local memory, the MPC8555E, as a ta rget, can accept the burst-read transfer. when the MPC8555E is granted mastership of the pci bus, the burst-write transaction continues. there are two blocks of memory in the design: ? the inbound buffers ? the outbound read buffers combin ed with the outbound write buffers there are many blocks of control logic in the block. on the pci side there are m achines for pci controller initiated address and data tenures for inbound and outbound data, respectively. on the ocean side there are machines for fabric arbitr ation, outbound data, and inbound data. as an initiator, the MPC8555E s upports read and write operations to the pci memory space, the pci i/o space, and the 256-byte pci configuration header spa ce. as an initiator, the MPC8555E also supports generating pci special-cycle and in terrupt-acknowledge transactions. as a target, the MPC8555E supports read and write operations to local memory, and, when configured in ag ent mode, read and write operations to the internal pci configuration registers. the pci1 interface can function as ei ther a pci host bridge re ferred to as host mode or a peripheral device on the pci bus referred to as agent mode. see section 16.1.3.1.1, ?host mode,? for more information.the pci2 interface only supports host mode. in agent mode, all of the pci conf iguration registers in the MPC8555E can be programmed from the pci bus. see section 16.4.2.11.3, ?pci configuration in agent and agent lock modes,? for more information. the pci interface provides bus arbitration for the mp c8555e and up to five other pci bus masters. the arbitration algorithm is a programma ble two-level, round-robi n priority selector. th e on-chip pci arbiter can operate in both host and agent modes or it can be disabled to allow for an external pci arbiter. the MPC8555E also provides an a ddress translation mechanism to map inbound pci to ocean accesses and outbound ocean to pci accesses. 16.1.1.1 MPC8555E as a pci initiator upon detecting an ocean-to-pci transaction, the MPC8555E requests the use of the pci bus. for ocean-to-pci bus write operations, th e MPC8555E requests mastership of the pci bus when the source completes the write operation to the ocean. for ocean-to-pci read operati ons, the MPC8555E requests mastership of the pci bus when it decode s that the access is for pci address space. once granted, the MPC8555E drives the address (pci1_ad[63:0] or pci n _ad[31:0]) and the bus command (pci1_c/be [7:0] or pci n _c/be [3:0]) signals. the master part of the in terface can initiate master-abort cycles, r ecognizes target-abort, target-retry, and target-disconnect cycles, and supports various device select ion timings. the master interface does not run fast back-to-back or exclusive accesses. 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 16-4 freescale semiconductor 16.1.1.2 MPC8555E as a pci target upon detection of a pci address phase, the mpc 8555e decodes the address and bus command to determine if the transaction is with in the local memory access boundaries. if the transaction is destined for local memory, the target interface latches the addres s, decodes the pci bus command, and forwards the transaction to the ocean control unit. on writes to local memory, data is forwarded along with the byte enables (if applicable) to the internal control unit. on reads, the data is driven on the bus and the byte enables (if applicable) determine whic h byte lanes contain meaningful data. the target interface of the MPC8555E can issue target -abort, target-retry, and target-disconnect cycles. the target interface supports fast back-to-back trans actions. the target interface uses the fastest device selection timing. the MPC8555E supports data streaming to and from local memory. th is means that data can flow between the MPC8555E pci interface and local memory as long as the internal buffers are not filled. 16.1.2 features the following is a list of pc i features that is supported: ? pci interface 2.2 compatible ? 66- and 33-mhz support ? 64- and 32-bit pci interface support ? host and agent mode support on pci1; host mode only on pci2 ? 64-bit dual address cycle (dac) support ? on-chip arbitration with support for five high priority request and grant signal pairs ? support for accesses to all pci memory and i/o address spaces ? support for pci to memory a nd memory to pci streaming ? memory prefetching of pci read accesses ? support posting of processor to pci and pci to memory writes ? support selectable snoop for inbound accesses ? pci configuration registers ? pci 3.3-v compatible 16.1.3 modes of operation a number of parameters that affect the pci controller mode s of operation are determ ined at power-on reset (por) by reset configuration signals as described in chapter 4, ?reset, clocking, and initialization.? table 16-1 provides a summary of these modes. table 16-1. por parameters for pci controller parameter description section/page host/agent configuration selects between host and agent mode for the pci1 interface. 4.4.3.4/4-13 pci interface selection selects between one 64-bit pci interface or two 32-bit pci interfaces. 4.4.3.11/4-17 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 16-5 16.1.3.1 host/agent m ode configuration the pci1 controller can f unction as either a pci host bridge (referred to as host mode) or a peripheral device on the pci bus (referred to as agent mode). additionally, the pci1 controller can operate in agent configuration lock mode.the pci2 interface only supports hos t mode. note that host/ agent mode selection is determined at power-up as summarized in section 16.5.1, ?power-on reset configuration modes.? 16.1.3.1.1 host mode when the device powers up in host mode, all inbound conf iguration accesses are ignored (and thus master aborted). see section 16.5.1.1, ?host mode,? for more information. 16.1.3.1.2 agent mode when the device powers up in agent mode, it acknowledges inbound configuration accesses. see section 16.5.1.2, ?agent mode,? for more information. note that in pci agent mode, the pci controller ignores all pci memory accesses except those to th e memory-mapped registers) until inbound address translation is enabled. 16.1.3.1.3 agent configuration lock mode when the device powers up in agent configuration lock mode, it retries i nbound configuration accesses until the acl bit in the pci bus function register is cleared. see section 16.5.1.3, ?agent configuration lock mode,? for more information. 16.1.3.2 pci-64 or two pci- 32 interface configuration the interface can be configured to be one pci-64 interface or two independent pci-32 interfaces. see section 16.5.2, ?extended 64-bit pci1 signal connections,? on page 16-76 for more information on pin assignments for the pci-64 configuration. the initial value for pci interface selection is determined by the value on the pci2_frame power-on reset confi guration signal. see chapter 4, ?reset, clocking, and initialization,? and the appropriate hardware spec ifications for more information. pci clocking selects between asynchronous or synchronous clocking for pci 4.4.3.10/4-16 pci arbiter enable enables the on-chip pci bus arbiter 4.4.3.13/4-18 pci output hold selects the number of buffer dela ys for pci output signals.this provides flexibility in meeting minimum output hold specifications re lative to sysclk for pci 4.4.3.17/4-19 pci i/o impedance selects the impedance of the pci i/o drivers 4.4.3.12/4-17 pci debug mode enable selects between normal oper ation or debug mode for the pci1_ad[62:58] signals. 4.4.3.14/4-18 table 16-1. por parameters for pci controller (continued) parameter description section/page 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 16-6 freescale semiconductor 16.1.3.3 pci clocking configuration the interface can be configured to be clocked as ynchronously with a pci_cl k input or synchronously with the sysclk input. the initial value for pc i1 clocking is determined by the value on the tsec2_txd1 power-on reset configurat ion signal. the initial value for pci2 clocking is determined by the value on the tsec2_txd0 power-on reset configuration signal. see section 4.4.3.10, ?pci clock selection,? and the MPC8555E powerquicc? iii integrated processor hardware specifications for more information. 16.1.3.4 pci arbiter (i nternal/external arbiter) configuration the interface can be configured to use an on-chip or off-chip pci arbiter. the init ial value for pci1 arbiter is determined by the value on the pci1_gnt2 power-on reset configuration signal. the initial value for pci2 arbiter is determined by the value on the pci2_gnt2 power-on reset confi guration signal. see section 4.4.3.13, ?pci arbiter configuration,? and the MPC8555E powerquicc? iii integrated processor hardware specifications for more information. 16.1.3.5 pci signal output hold configuration the interface has a programmable output hold delay for pci bus signals to help meet minimum output hold specifications relative to sysclk for pci systems. th e initial value for pci1 ou tput hold is determined by the value on the pci1_gnt4 power-on reset configuration signal. the initial value for pci2 output hold is determined by the value on the pci2_gnt4 power-on reset configuratio n signal. note that in 64-bit mode, pci1_gnt4 controls the lower half of th e ad bus (ad[31:0]) and pci2_gnt4 controls the upper half of the ad bus (ad[63:32]). these must have the same value or the output hold will be different for the upper and lower halves of the bus. see chapter 4, ?reset, clocking, and initialization,? and the MPC8555E powerquicc? iii integrated processor hardware specifications for more information on these values and signal timing. 16.1.3.6 pci impeda nce configuration the interface has a programma ble impedance for pci bus signals. the initial value for pci1 impedance is determined by the value on the pci1_gnt1 power-on reset configuration signal. the initial value for pci2 impedance is determined by the value on the pci2_gnt1 power-on reset confi guration signal. note that in 64-bit mode, pci1_gnt1 controls the lower half of th e ad bus (ad[31:0]) and pci2_gnt1 controls the upper half of the ad bus (ad[63:32]). these must have th e same value or the impedance will be different for the upper and lower halves of the bus. see chapter 4, ?reset, cloc king, and initialization,? and the MPC8555E powerquicc? iii integrated processor hardware specifications for more information. 16.1.3.7 pci debug configuration the interface offers the ability to output source information for out bound transactions in a debug mode when pci1 is configured as a 64-bit interface. this may be useful info rmation for a logic analyzer to debug code. when this mode is enabled, pci1_ad[62:58] will display debug source information for the pci1 interface. the initial value for pci1 debug is determined by the value on the pci1_gnt3 power-on reset 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 16-7 configuration signal. debug informati on for pci2 is not available. see chapter 4, ?reset, clocking, and initialization,? and the appropriate hardware spec ifications, for more information. 16.2 external signal descriptions figure 16-2 shows the external pci signals. figure 16-2. pci interface external signals 32 pci1_ad[31:0] 4 pci1_par pci1_c/be [3:0] 1 1 pci1_trdy 1 pci1_irdy 1 pci1_stop 1 pci1_devsel 1 pci1_perr pci1_serr pci1_frame 1 pci1_idsel 1 pci 1 signals address interface error 1 pci1_req [0:4] pci1_gnt [0:4] arbitration pci 2 signals 32 pci1_c/be [7:4]/pci2_c/be [3:0] 1 pci1_par64/pci2_par pci1_ad[63:32]/pci2_ad[31:0] 4 5 5 and data command reporting 37 signals 6 signals 2 signals 10 signals address and data 37 signals 1 1 1 1 1 1 1 1 5 5 interface command 6 signals error reporting 2 signals arbitration 10 signals pci2_frame pci2_trdy pci2_irdy pci2_stop pci2_devsel pci2_idsel pci2_perr pci2_serr pci2_req [0:4] pci2_gnt [0:4] pci1_clk 1 pci2_clk 1 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 16-8 freescale semiconductor table 16-2 contains the detailed descriptions of the external pci interface signals. table 16-2. pci1 and pci2 interface signals?detailed signal descriptions signal i/o description pci1_ack64 i/o 64-bit transaction acknowledge. the 64-bit transaction acknowledge (pci1_ack64 ) signal is both an input and output signal. it indicates that the current target supports 64-bit trans fers during the data phase of the current transaction. o as an output for the bi-directional 64-bit transaction acknowledge, this signal operates as follows: state meaning asserted?indicates that this pc i controller, as the target of a pci transaction, may use the full 64-bit data bus for the data phase of the transaction. negated?indicates that this pci controller, as the target of a pci transaction, may use only 32 bits of the data bus in servicing a data transfer. timing assertion/negation?as specified by the pci local bus specification , rev 2.2 i as an input for the bi-directional 64-bit transaction acknowledge, this signal operates as follows: state meaning asserted?indicates that the targ et of a pci transaction may use the full 64-bit data bus for the data phase of the transaction. negated?indicates that t he target of a pci transaction may only use 32 bits of the data bus during the data phase of the transaction. timing assertion/negation?as specified by the pci local bus specification , rev 2.2 pci1_ad[31:0], pci1_ad[63:32]/ pci2_ad[31:0] i/o pci address/data bus. the pci addr ess/data bus (pci1_ad[63:0] or pci n _ad[31:0]) consists of 64 or 32 signals that are both input and out put signals on this pci controller. o as outputs for the bi-directional pci address/data bus, these signals operate as described below. state meaning asserted/negated?represents the physical addr ess during the address phase of a pci transaction. during the data phase(s) of a pci transaction, the pci address/data bus contain the data being written. the pci n _ad[7:0] signals define the lsb and pci n _ad[31:0] define the msb for the 32-bit interface; pci1_ad[63:56] defin e the msb for the 64-bit bus mode. timing assertion/negation?as specified by the pci local bus specification , rev 2.2 i as inputs for the bi-directional pci address/data bus, these signals operate as described below. state meaning asserted/negated?represents the address to be decoded as a check for device select during the address phase of a pci transaction or the data being received during the data phase(s) of a pci transaction. the pci n _ad[7:0] signals define the lsb and pci n _ad[31:0] define the msb for the 32-bit interface; pci1_ad[63:56] defin e the msb for the 64-bit bus mode. timing assertion/negation?as specified by the pci local bus specification , rev 2.2 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 16-9 pci1_c/be [3:0], pci1_c/be [7:4]/ pci2_c/be [3:0] i/o command/byte enable. the command/byte enable (pci1_c/be [7:0] or pci n _c/be [3:0]) signals are both input and output signals on this pci contro ller. the command encodings for pci bus mode are described in section 16.4.2.2, ?pci bus commands.? o as outputs for the bi-directional command/byte enable, these signals operate as described below. state meaning asserted/negated?during the address phase, pci1_c/be [7:0] or pci n _c/be [3:0] define the bus command. during the data phase, pci1_c/be [7:0] or pci n _c/be [3:0] function as byte enables to determine which byte lanes carry meaningful data. the pci n _c/be 0 signal applies to the lsb. timing assertion/negation?as specified by the pci local bus specification , rev 2.2 i as inputs for the bi-directional command/byte e nable, these signals operate as described below. state meaning asserted/negated?during the address phase, pci1_c/be [7:0] or pci n _c/be [3:0] indicate the command that another master is s ending. during the pci bus data phase, pci1_c/be [7:0] or pci n _c/be [3:0] indicate which byte lanes are valid. timing assertion/negation?as specified by the pci local bus specification , rev 2.2 pci n _devsel i/o device select. the device select (pci n _ devsel ) signal is both an input and output signal on this pci controller. o as outputs for the bi-directional device select, these signals operate as described below. state meaning asserted?indicates that this pci controller has decoded the address and is the target of the current access. negated?indicates that this pci controller has decoded the address and is not the target of the current access. timing assertion/negation?as specified by the pci local bus specification , rev 2.2 i as inputs for the bi-directional device sele ct, these signals operate as described below. state meaning asserted?indicates that some pci agent (other than this pci controller) has decoded its address as the target of the current access. negated?indicates that no pci agent has been selected. timing assertion/negation?as specified by the pci local bus specification , rev 2.2 pci n _frame i/o frame. the frame (pci n _frame ) signal is both an input and output signal on this pci controller. o as outputs for the bi-directional frame, these signals operate as described below. state meaning asserted?indicates that this pc i controller, acting as a pci master, is initiating a bus transaction. while pci n _frame is asserted, data transfers may continue. negated?if pci n _irdy is asserted, indicates that the pci transaction is in the final data phase; if pci n _irdy is negated, indicates that the pci bus is idle. timing assertion/negation?as specified by the pci local bus specification , rev 2.2 i as inputs for the bi-directional frame, these signals operate as described below. state meaning asserted?indicates that another pci master is initiating a bus transaction. negated?indicates that the transaction is in th e final data phase or that the bus is idle. timing assertion/negation?as specified by the pci local bus specification , rev 2.2 table 16-2. pci1 and pci2 interface signal s?detailed signal descriptions (continued) signal i/o description 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 16-10 freescale semiconductor pci n _ gnt [4:0] o pci bus grant. output signals on this pci contro ller when the arbiter is ena bled. when the arbiter is disabled pci n _gnt0 is an input signal. note that pci n _ gnt[ n] is a point-to-point signal. every master has its own bus grant signal. also, note that these signals are also used as reset configuration signals in the MPC8555E as described in section 4.4.3, ?power-on reset configuration." state meaning asserted?indicates that this pc i controller has granted control of the pci bus to agent n . negated?indicates that this pci controller has not granted control of the pci bus to agent n . timing assertion/negation?as specified by the pci local bus specification , rev 2.2 pci n _idsel i initialization device select. the initialization device select (pci n _idsel) signal is an input signal on this pci controller. it is used as a chip select during configuration read and write transactions. state meaning asserted?indicates this pci controller is being se lected as a target of a configuration read or write transactions. negated?indicates this pci controller is not being selected as a target of configuration read or write transactions. timing assertion/negation?as specified by the pci local bus specification , rev 2.2 pci n _irdy i/o initiator ready. the initiator ready (pci n _ irdy ) signal is both an input and output signal on this pci controller. o as outputs for the bi-directional initiator ready, these signals operate as described below. state meaning asserted?indicates that this pci controller, ac ting as a pci master, can complete the current data phase of a pci transaction. during a write, this pci controller asserts pci n _ irdy to indicate that valid data is present on the address/data bus. during a read, this pci controller asserts pci n _ irdy to indicate that it is prepared to accept data. negated?indicates that the pci target needs to wait before this pci controller, acting as a pci master, can complete the cu rrent data phase. during a write, this pci controller negates pci n _ irdy to insert a wait cycle when it cannot provide valid data to the target. during a read, this pci controller negates pci n _ irdy to insert a wait cycle when it cannot accept data from the target. timing assertion/negation?as specified by the pci local bus specification , rev 2.2 i as inputs for the bi-directional initiator ready, these signals operate as described below. state meaning asserted?indicates another pci master is able to complete the current data phase of a transaction. negated?if pci n _frame is asserted, indicates a wait cycle from another master. if pci n _frame is negated, indicates the pci bus is idle. timing assertion/negation?as specified by the pci local bus specification , rev 2.2 table 16-2. pci1 and pci2 interface signal s?detailed signal descriptions (continued) signal i/o description 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 16-11 pci n _par i/o pci parity. the pci parity (pci n _par) signal is both an input and output signal on this pci controller. o as outputs for the bi-directional pci parity, these signals operate as described below. state meaning asserted?indicates odd parity across the pci n _ad[31:0] and pci n _c/be [3:0] signals during address and data phases. negated?indicates even parity across the pci n _ad[31:0] and pci n _c/be [3:0] signals during address and data phases. timing assertion/negation?as specified by pci local bus specification, rev 2.2 i as inputs for the bi-directional pci parity, these signals operate as described below. state meaning asserted?indicates odd parity driven by another pci master or the pci target during read data phases. negated?indicates even parity driven by another pci master or the pci target during read data phases. timing assertion/negation?as specified by pci local bus specification, rev 2.2 pci1_par64 i/o upper dword parity. the pci parity (pci1_par64) signal is both an input and output signal on this pci controller. pci1_par64 is the even parity bit that protects the upper 32 bits of data and upper 4 bits of command/byte enable. o as outputs for the bi-directional upper dword pa rity, these signals operate as described below. state meaning asserted?indicates odd parity acro ss the pci1_ad[63: 32] and pci1_c/be [7:4] signals during address and data phases. negated?indicates even parity across the pci1_ad[63:32] and pci1_c/be [7:4] signals during address and data phases. timing assertion/negation?as specified by pci local bus specification , rev 2.2 i as inputs for the bi-directional upper dword parity, these signals operate as described below. state meaning asserted?indicates odd parity driven by another pci master or the pci target during read data phases. negated?indicates even parity driven by another pci master or the pci target during read data phases. timing assertion/negation?as specified by pci local bus specification , rev 2.2 table 16-2. pci1 and pci2 interface signal s?detailed signal descriptions (continued) signal i/o description 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 16-12 freescale semiconductor pci n _perr i/o pci parity error. the pci parity error (pci n _perr ) signal is both an input and output signal on this pci controller. o as outputs for the bi-directional pci parity error, these signals operate as described below. state meaning asserted?indicates that this pc i controller, acting as a pci ag ent, detected a data parity error. (the pci initiator drives pci n _perr on read operations; the pci target drives pci n _perr on write operations.) negated?indicates no error. timing assertion/negation?as specified by the pci local bus specification , rev 2.2 i as inputs for the bi-directional pci parity error, these signals operate as described below. state meaning asserted?indicates that another pci agent detected a data parity error while this pci controller was sourcing data (this pci controlle r was acting as the pci initiator during a write, or was acting as the pci target during a read). negated?indicates no error. timing assertion/negation?as specified by the pci local bus specification , rev 2.2 pci n _req [4:0] i pci bus request . input signals on this pci controller when the arbiter is enabled. when the arbiter is disabled, pci n _req [0] is an output. note that pci n _req[n] is a point-to-point signal. every master has its own bus request signal. following is the state meaning for the pci n _req [n] input. state meaning asserted?indicates that agent n is requesting control of the pci bus to perform a transaction. negated?indicates that agent n does not require use of the pci bus. timing assertion/negation?as specified by the pci local bus specification , rev 2.2 pci1_req64 i/o 64-bit transaction request. both an input and output si gnal on this pci controller. it indicates that the current master desires to tr ansfer data using 64-bit transfers. also, note that this signal is used as a reset configuration signal in the MPC8555E as described in section 4.4.3, ?power-o n reset configuration ." o as an output for the bi-directional 64-bit transaction request, this signal operates as follows: state meaning asserted?indicates that this pc i controller, as the master of a pci transaction, desires to use all 64 bits. negated? indicates that this pci controller, as the master of a pci transaction, uses only 32 bits of the data bus in servicing a data transfer. timing assertion/negation?as specified by the pci local bus specification, rev 2.2 i as an input for the bi-directional 64-bit transaction request, this signal operates as described below. state meaning asserted?indicates that the master of a pci transaction is reque sting to use the full 64-bit data bus for the data phase of the transaction. negated?indicates that the master of a pci tr ansaction uses only 32 bits of the data bus during the data phase of the transaction. timing assertion/negation?as specified by the pci local bus specification, rev 2.2 table 16-2. pci1 and pci2 interface signal s?detailed signal descriptions (continued) signal i/o description 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 16-13 pci n _serr i/o pci system error.the pci system error (pci n _serr ) signal is both an input and output signal on this pci controller. o as outputs for the bi-directional pci system erro r, these signals operate as described below. state meaning asserted?indicates that an address parity error, a target-abort (when this pci controller is acting as the initiator), or some other syst em error (where the resu lt is a catastrophic error) was detected. negated?indicates no error. timing assertion/negation?as specified by the pci local bus specification , rev 2.2 i as inputs for the bi-directiona l pci system error, these sign als operate as described below. state meaning asserted?indicates that a target (other than th is pci controller) has detected a catastrophic error. negated?indicates no error. timing assertion/negation?as specified by the pci local bus specification , rev 2.2 pci n _stop i/o stop.the stop (pci n _stop ) signal is both an input and output signal on this pci controller. o as outputs for the bi-directional stop, these signals operate as described below. state meaning asserted?indicates that this pc i controller, acting as a pci target, is requesting that the initiator stop the current transaction. negated?indicates that the curr ent transaction can continue. timing assertion/negation?as specified by the pci local bus specification , rev 2.2 i as inputs for the bi-directional stop, th ese signals operate as described below. state meaning asserted?indicates that a targ et is requesting that the pci initiator stop the current transaction. negated?indicates that the curr ent transaction can continue. timing assertion/negation?as specified by the pci local bus specification , rev 2.2 pci n _trdy i/o target ready. both an input and output signal on this pci controller. o as outputs for the bi-directional target ready, these signals operate as described below. state meaning asserted?indicates that this pci controller, acting as a pci target, can complete the current data phase of a pci transaction. during a read, this pci controller asserts pci n _trdy to indicate that valid data is present on pci n _ad[31:0]. during a write, this pci controller asserts pci n _trdy to indicate that it is prepared to accept data. negated?indicates that the pci initiator needs to wait before this pci controller, acting as a pci target, can complete the current data phase. during a read, this pci controller negates pci n _trdy to insert a wait cycle when it cannot provide va lid data to the initiator. during a write, this pci controller negates pci n _trdy to insert a wait cycle when it cannot accept data from the initiator. timing assertion/negation?as specified by the pci local bus specification , rev 2.2 i as inputs for the bi-directional target ready, these signals operate as described below. state meaning asserted?another pci target is able to comp lete the current data phase of a transaction. negated?indicates a wait cycl e from another target. timing assertion/negation?as specified by the pci local bus specification , rev 2.2 table 16-2. pci1 and pci2 interface signal s?detailed signal descriptions (continued) signal i/o description 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 16-14 freescale semiconductor 16.3 memory map/register definitions the pci interface unit of the MPC8555E supports the followi ng two types of registers: ? memory-mapped registers?these registers c ontrol pci address tr anslation, pci error management, and pci configuration register access on the MPC8555E. these registers are described in section 16.3.1, ?pci memory mapped registers,? and its subsections. ? pci configuration registers contained within th e pci configuration header?these registers are specified by the pci bus specifi cation for every pci device. thes e registers are described in section 16.3.2, ?pci configuration header,? and its subsections. 16.3.1 pci memory mapped registers the pci memory mapped registers are accessed by reading and wr iting to an address co mprised of the base address (specified in the ccsrbar on the local side or the pcsrbar on the pci side) plus the offset of the specific register to be accesse d. note that all memory-mapped regi sters (except the pci configuration data register, pci cfg_data) must only be accessed as 32-bit quantities. table 16-3 lists the memory-mapped registers. note th at the memory-mapped registers for the pci1 interface begin at offset 0x0_8000 and the memory-mappe d registers for the pci2 interface begin at offset 0x0_9000. undefined 4-byte ad dress spaces within offset 0x000?0xfff are reserved. table 16-3. pci memory-mapped register map offset register access reset section/page pci1 configuration access registers 0x0_8000 cfg_addr?pci1 configur ation address r/w 0x0000_0000 16.3.1.1.1/16-17 0x0_8004 cfg_data?pci1 configuration data r/w 0x0000_0000 16.3.1.1.1/16-17 0x0_8008 int_ack?pci1 interrupt acknowledge r 0x0000_0000 16.3.1.1.3/16-19 0x0_800c? 0x0_8bfc reserved ? ? ? pci1 atmu registers?outbound and inbound 0x0_8c00?0x0_8c3c?outbound window 0 (default) 0x0_8c00 potar0?pci1 outbound window 0 (default) translation address register r/w 0x0000_0000 16.3.1.2.1/16-20 0x0_8c04 potear0?pci1 outbound window 0 (default) translation extended address register r/w 0x0000_0000 16.3.1.2.2/16-20 0x0_8c08 reserved ? ? 0x0_8c0c reserved ? ? 0x0_8c10 powar0?pci1 outbound window 0 (default) attributes register r/w 0x8004_401f 16.3.1.2.4/16-22 0x0_8c14? 0x0_8c1c reserved ? ? 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 16-15 0x0_8c20?0x0_8c3c?outbound window 1 0x0_8c20 potar1?pci1 outbound window 1 translation address register r/w 0x0000_0000 16.3.1.2.1/16-20 0x0_8c24 potear1?pci1 outbound window 1 translation extended address register r/w 0x0000_0000 16.3.1.2.2/16-20 0x0_8c28 powbar1?pci1 outbound window 1 base address register r/w 0x0000_0000 16.3.1.2.3/16-21 0x0_8c2c reserved ? ? 0x0_8c30 powar1?pci1 outbound window 1 attributes register r/w 0x0000_0000 16.3.1.2.4/16-22 0x0_8c34? 0x0_8c3c reserved ? ? 0x0_8c40?0x0_8c5c?outbound window 2 0x0_8c40 potar2?pci1 outbound window 2 translation address register r/w 0x0000_0000 16.3.1.2.1/16-20 0x0_8c44 potear2?pci1 outbound window 2 translation extended address register r/w 0x0000_0000 16.3.1.2.2/16-20 0x0_8c48 powbar2?pci1 outbound window 2 base address register r/w 0x0000_0000 16.3.1.2.3/16-21 0x0_8c4c reserved ? ? 0x0_8c50 powar2?pci1 outbound window 2 attributes register r/w 0x0000_0000 16.3.1.2.4/16-22 0x0_8c54? 0x0_8c5c reserved ? ? 0x0_8c60?0x0_8c7c?outbound window 3 0x0_8c60 potar3?pci1 outbound window 3 translation address register r/w 0x0000_0000 16.3.1.2.1/16-20 0x0_8c64 potear3?pci1 outbound window 3 translation extended address register r/w 0x0000_0000 16.3.1.2.2/16-20 0x0_8c68 powbar3?pci1 outbound window 3 base address register r/w 0x0000_0000 16.3.1.2.3/16-21 0x0_8c6c reserved ? ? 0x0_8c70 powar3?pci1 outbound window 3 attributes register r/w 0x0000_0000 16.3.1.2.4/16-22 0x0_8c74? 0x0_8c7c reserved ? ? 0x0_8c80?0x0_8c9c?outbound window 4 0x0_8c80 potar4?pci1 outbound window 4 translation address register r/w 0x0000_0000 16.3.1.2.1/16-20 0x0_8c84 potear4?pci1 outbound window 4 translation extended address register r/w 0x0000_0000 16.3.1.2.2/16-20 0x0_8c88 powbar4?pci1 outbound window 4 base address register r/w 0x0000_0000 16.3.1.2.3/16-21 0x0_8c8c reserved ? ? 0x0_8c90 powar4?pci1 outbound window 4 attributes register r/w 0x0000_0000 16.3.1.2.4/16-22 0x0_8c94? 0x0_8d9c reserved ? ? table 16-3. pci memory-mapped register map (continued) offset register access reset section/page 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 16-16 freescale semiconductor 0x0_8da0?0x0_8dbc?inbound window 3 0x0_8da0 pitar3?pci1 inbound window 3 translation address register r/w 0x0000_0000 16.3.1.3.1/16-24 0x0_8da4 reserved ? ? 0x0_8da8 piwbar3?pci1 inbound window 3 base address register r/w 0x0000_0000 16.3.1.3.2/16-25 0x0_8dac piwbear3?pci1 inbound window 3 base extended address register r/w 0x0000_0000 16.3.1.3.3/16-26 0x0_8db0 piwar3?pci1 inbound window 3 attributes register r/w 0x0000_0000 16.3.1.3.4/16-26 0x0_8db4? 0x0_8dbc reserved ? ? 0x0_8dc0?0x0_8ddc?inbound window 2 0x0_8dc0 pitar2?pci1 inbound window 2 translation address register r/w 0x0000_0000 16.3.1.3.1/16-24 0x0_8dc4 reserved ? ? 0x0_8dc8 piwbar2?pci1 inbound window 2 base address register r/w 0x0000_0000 16.3.1.3.2/16-25 0x0_8dcc piwbear2?pci1 inbound window 2 base extended address register r/w 0x0000_0000 16.3.1.3.3/16-26 0x0_8dd0 piwar2?pci1 inbound window 2 attributes register r/w 0x0000_0000 16.3.1.3.4/16-26 0x0_8dd4? 0x0_8ddc reserved ? ? 0x0_8de0?0x0_8dfc?inbound window 1 0x0_8de0 pitar1?pci1 inbound window 1 translation address register r/w 0x0000_0000 16.3.1.3.1/16-24 0x0_8de4 reserved ? ? 0x0_8de8 piwbar1?pci1 inbound window 1 base address register r/w 0x0000_0000 16.3.1.3.2/16-25 0x0_8dec reserved ? ? 0x0_8df0 piwar1?pci1 inbound window 1 attributes register r/w 0x0000_0000 16.3.1.3.4/16-26 0x0_8df4? 0x0_8dfc reserved ? ? pci1 error management registers 0x0_8e00 err_dr?pci1 error detect register special 0x0000_0000 16.3.1.4.1/16-29 0x0_8e04 err_cap_dr?pci1 error capture disabled register r/w 0x0000_0000 16.3.1.4.2/16-30 0x0_8e08 err_en?pci1 error enable register r/w 0x0000_0000 16.3.1.4.3/16-31 0x0_8e0c err_attrib?pci1 error attrib utes capture register r/w 0x0000_0000 16.3.1.4.4/16-32 0x0_8e10 err_addr?pci1 error address capture register r/w 0x0000_0000 16.3.1.4.5/16-33 0x0_8e14 err_ext_addr?pci1 error extended address capture register r/w 0x0000_0000 16.3.1.4.6/16-33 0x0_8e18 err_dl?pci1 error data lo w capture register r/w 0x0000_0000 16.3.1.4.7/16-33 table 16-3. pci memory-mapped register map (continued) offset register access reset section/page 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 16-17 16.3.1.1 pci configurat ion access registers the pci configuration header, shown in figure 16-24 and figure 16-58 , is accessed through an indirect method utilizing a pair of 32-bit memory-mapped access registers. fo r pci1, cfg_addr is at offset 0x0_8000 and cfg_data is at offset 0x0_8004. fo r pci2, cfg_addr is at offset 0x0_9000 and cfg_data is at offset 0x0_9004. 16.3.1.1.1 pci configuration address register (cfg_addr) the cfg_addr register is shown in figure 16-3 . figure 16-3. pci cfg_addr register table 16-4 describes the bit settings for the cfg_addr register. 0x0_8e1c err_dh?pci1 error data high capture register r/w 0x0000_0000 16.3.1.4.8/16-34 0x0_8e20 gas_timr?pci1 gasket timer register r/w 0x0000_0000 16.3.1.4.9/16-35 0x0_8e24? 0x0_8efc reserved ? ? 0x0_8f00? 0x0_8ffc reserved for debug ? ? 0x0_9000? 0x0_9ffc pci2 registers note: the pci2 interface has the same memory-mapped regi sters that are described for pci1 from 0x0_8000 to 0x0_8fff except the offsets ar e from 0x0_9000 to 0x0_9fff. 07815 r en 00 00000 bus number w reset 0000_0000_0000_0000 16 20 21 23 24 29 30 31 r device number function number register number 00 w reset 0000_0000_0000_0000 offset pci1: 0x0_8000, pci2: 0x0_9000 table 16-4. pci cfg_addr field descriptions bits name description 0 en enable. allow a pci configuration access when pci cfg_data is accessed 1?7 ? reserved 8?15 bus number pci bus number to access table 16-3. pci memory-mapped register map (continued) offset register access reset section/page 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 16-18 freescale semiconductor bus number 0xb00 and device number 0b0_0000 are used to configure the internal pci configuration header of the MPC8555E itself. see section 16.4.2.11.2, ?accessing th e pci configuration sp ace in host mode,? and section 16.4.2.11.3, ?pci configuration in agent and agent lock modes,? for usage of pci cfg_addr. 16.3.1.1.2 pci configuration data register (cfg_data) the cfg_data register is shown in figure 16-3 . figure 16-4. pci cfg_data register table 16-5 describes the bit settings for the cfg_data register. the cfg_data register is a 4-byte wi ndow into the little-endian pci conf iguration header data structure; therefore byte addressing within th e cfg_data register uses little-endian c onvention. note that cfg_data may contain 1, 2, 3, or 4 bytes depend ing on the size of the register being accessed. see section 16.4.2.11.2, ?accessing th e pci configuration sp ace in host mode,? and section 16.4.2.11.3, ?pci configuration in agent and agent lock modes,? for usage of cfg_data. 16?20 device number device number to access on specified bus 21?23 function number function to access within specified device 24?29 register number 32-bit register to access within specified device 30?31 ? reserved, hardwired to logic 00 0 15 r data w reset 0000_0000_0000_0000 16 31 r data w reset 0000_0000_0000_0000 offset pci1: 0x0_8004, pci2: 0x0_9004 table 16-5. pci cfg_data field descriptions bits name description 0?31 data a read or write to this regist er starts a pci configuration cycle if the pci cfg_addr enable bit is set. if the enable bit is not set, a pci i/o transaction is generated. table 16-4. pci cfg_addr field descriptions (continued) bits name description 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 16-19 16.3.1.1.3 pci interrupt ac knowledge register (int_ack) an external pci interrupt acknowledge transaction is generated by reading the int_ack register. for pci1, int_ack is at offset 0x0_8008. for pci2, int_ack is at offset 0x0_9000. pci int_ack is read-only and a write to that address results in nothing. the int_ack register is shown in figure 16-5 . figure 16-5. pci int_ack register table 16-6 describes the bit settings for the int_ack register. 16.3.1.2 pci atmu outbound registers the outbound address translat ion and mapping unit contro ls the mapping of transac tions from the internal 32-bit address space of the MPC8555E to the extern al pci address space. the outbound atmu consists of four translation windows plus a default translation for transacti ons that do not hit in one of the four windows. each window contains a base address that points to the beginning of the window in the local address map, a translation address that sp ecifies the high-order bits of the transact ion in the external pci address space, and a set of attributes including window size and external transaction type. each window must be aligned ba sed on the granularity specified by the window size. if two outbound atmu windows overlap in the local address space, the mapping of the lo wer numbered window has precedence over the higher numbered window. note that outbound translation windows must not overlap the configuration access registers. window 0 is the default window a nd is the only window enabled upon re set. the default outbound register set is used when a transaction mi sses in all of the other outbound windows. 0 15 rdata w reset 0000_0000_0000_0000 16 31 rdata w reset 0000_0000_0000_0000 offset pci1: 0x0_8008, pci2: 0x0_9008 table 16-6. pci int_ack field descriptions bits name description 0?31 data a read to this register generates a pci interrupt acknowledge cycle. 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 16-20 freescale semiconductor 16.3.1.2.1 pci outbound translat ion address registers (potar n ) the pci outbound translation address registers (potar n ) select the starting addr esses in the pci address space for hits in the pci outbound windows. the transl ated address is created by concatenating the transaction offset to this translati on address. the format of the potar n is shown in figure 16-6 . figure 16-6. pci outbound translation address registers table 16-7 describes the fields of the potar n registers. 16.3.1.2.2 pci outbound translation extended address registers (potear n ) the pci outbound translation extende d address registers (potear n ) contain the most si gnificant bits of a 64-bit translation address. the format of the potear n is shown in figure 16-7 . figure 16-7. pci outbound translat ion extended address registers 0 11 12 15 r tea ta w reset 0000_0000_0000_0000 16 31 r ta w reset 0000_0000_0000_0000 offset pci1: 0x0_8c00, 0x0_8c20, 0x0_8c40, 0x0_8c60, 0x0_8c80 pci2: 0x0_9c00, 0x0_9c20, 0x0_9c40, 0x0_9c60, 0x0_9c80 table 16-7. potar n field descriptions bits name description 0?11 tea translation extended address. represents bi ts 43?32 of a 64-bit pci address (bit 0 is lsb) 12?31 ta translation address. represents bits 31?12 of the pci address. based on the size of the window specified in powar n [ows], the low-order bits of this field may be ignored. 0 11 12 15 r0 0 0 0 00000 0 0 0 tea w reset 0000_0000_0000_0000 16 31 r tea w reset 0000_0000_0000_0000 offset pci1: 0x0_8c04, 0x0_8c24, 0x0_8c44, 0x0_8c64, 0x0_8c84 pci2: 0x0_9c04, 0x0_9c24, 0x0_9c44, 0x0_9c64, 0x0_9c84 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 16-21 table 16-8 describes the fields of the potear n . 16.3.1.2.3 pci outbound window base address registers (powbar n ) the pci outbound window base address registers (powbar n ) point to the beginning of each translation window in the local 32-bit addres s space. addresses for outbound tran sactions are compared to the appropriate bits in these registers, according to the sizes of the windows. if a transaction does not fall within one of these windows, the default translation and mapping is used. the default window is always enabled and used when the other windows miss. note that powbar0 (for outbound atmutwindow 0) is not used, because window 0 is the default window used when no other windows match. powbar0 may be read from and written to, but the value is ignored. the format of the powbar n is shown in figure 16-8 . figure 16-8. pci outbound window base address registers table 16-9 describes the field of the powbar n . table 16-8. potear n field descriptions bits name description 0?11 ? reserved 12?31 tea translation extended address. comprises bi ts [44?63] of the translation address register 0 11 12 15 r ?wba w reset 0000_0000_0000_0000 16 31 r wba w reset 0000_0000_0000_0000 offset pci1: 0x0_8c08, 0x0_8c28, 0x0_8c48, 0x0_8c68, 0x0_8c88 pci2: 0x0_9c08, 0x0_9c28, 0x0_9c48, 0x0_9c68, 0x0_9c88 table 16-9. powbar n field descriptions bits name description 0?11 ? reserved, should be cleared. 12?31 wba window base address. source address which is the starting point for the outbound translation window. the window must be aligned based on the size selected in the window size bits. 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 16-22 freescale semiconductor 16.3.1.2.4 pci outbound window attributes registers (powar n ) the pci outbound window attr ibutes registers (powar n ) define the window size s to translate and other attributes for the translations. the minimum window size is 4 kbytes. the maximum window size is 4 gbytes. the default window attribute re gister, powar0, is shown in figure 16-9 . note that the fiel ds for all of the powar n registers are the same, only th e reset values are different. figure 16-9. pci outbound window attributes register 0 (default) powar1?powar4 are shown in figure 16-10 . figure 16-10. pci outbound window attributes registers 1?4 table 16-10 describes the fields for the powar n registers. 01 11 12 15 r en 1 1 for powar0, translation is always enabled. the enable field (en) may be read and written, but the value is ignored. 0 0 0 00000 0 0 0 rtt w reset 1000_0000_0000_0100 2 2 the default window is enabled, configured for memory read and memory write, and set to an ows size of 4 gbytes. 16 19 20 25 26 31 r wtt 00000 0 ows w reset 0100_0000_0001_1111 offset pci1: 0x0_8c10, pci2: 0x0_9c10 01 11 12 15 r en 0 0 0 00000 0 0 0 rtt w reset 0000_0000_0000_0000 16 19 20 25 26 31 r wtt 00000 0 ows w reset 0000_0000_0000_0000 offset pci1: 0x0_8c30, 0x0_8c50, 0x0_8c70, 0x0_8c90 pci2: 0x0_9c30, 0x0_9c50, 0x0_9c70, 0x0_9c90 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 16-23 16.3.1.3 pci atmu inbound registers the inbound address translation and mapping unit controls the mapping of transacti ons from the external pci address space to the local address space of th e MPC8555E. the inbound atmu is comprised of four windows?a configuration window and three general translation windows . the configuration window has table 16-10. powar n field descriptions bits name description 0 en enable. enables this address translation. note that for powar0,translation is always enabled. the enable field (en) may be read and written, but the value is ignored. 1?11 ? reserved 12?15 rtt read transaction type to run on pci 0000 reserved ... 0011 reserved 0100 memory read 0101 reserved ... 0111 reserved 1000 i/o read 1001 reserved ... 1111 reserved 16?19 wtt write transaction type to run on pci 0000 reserved ... 0011 reserved 0100 memory write 0101 reserved ... 0111 reserved 1000 i/o write 1001 reserved ... 1111 reserved 20?25 ? reserved 26?31 ows outbound window size. outbound translation window size n which is the encoded 2^(n+1) bytes window size. the smallest window size is 4 kbytes. 000000: reserved ... 001011: 4-kbyte window size 001100: 8-kbyte window size ... 011111: 4-gbyte window size 100000:reserved ... 111111: reserved the default powar register (0x0_8c10) has an ows val ue of 011111. also note that for powar0, setting ows to less than 4 gbytes causes addresses that miss in the other outbound windows to be aliased to the smaller address range defined by powar0[ows] and potar0. 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 16-24 freescale semiconductor higher priority than all other inbound atmu window s and takes precedence over them if there is an overlap. note pci1 and pci2 can also be used as possible target interfaces for pci inbound atmus, mapping from one pci to th e other. however, it is illegal for pci1 to use pci1 as a target, or for pci2 to use pci2 for a target. each window contains the following: ? a base address, which points to the beginning of the window in th e external pci address map. the base address of each window is also accessible by pci c onfiguration transactions as base address registers within the pci confi guration header, as shown in figure 16-24 . the registers may be read or updated equivalently thro ugh the atmu memory map or through pci configuration transactions to the pci configuration header. ? a translation address, which specifies the upper or der bits of the transact ion in the local address space ? a set of attributes including window size and internal tr ansaction attributes each window?s base address and tran slation address must be aligned to the size of the window. if two general inbound atmu windows overlap in the external pci address space, th e mappings of the lower numbered window are applied; however, it is ille gal for an inbound window to overlap the pcsrbar window. in addition, if inbound atmu windows are ove rlapped, the atmu windows must not map to the same address with differ ent sets of attributes. note that pcsrbar in the pci configuration header acts as a fourth inbound window that translates a 1-mbyte region of pci space to the local confi guration space pointed to by ccsrbar. pcsrbar can be accessed by pci configuration cy cles or by accessing the pci conf iguration header through the pci cfg_addr and pci cfg_data registers. see section 16.3.1.1.1, ?pci configur ation address register (cfg_addr),? section 16.3.1.1.2, ?pci configuration data register (cfg_data),? and section 16.3.2.11, ?pci base address registers.? all accesses to pcsrbar have an automatic internal byte lane redirection from the li ttle-endian pci bus to the big-e ndian ccsrbar configuration space. 16.3.1.3.1 pci inbound translat ion address registers (pitar n ) the pci inbound translation address registers (pitar n ) points to the beginning of the local address space for the inbound window. the translated address is created by concatenating the transaction offset to this translation address. the format of the pitar n is shown in figure 16-11 . 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 16-25 figure 16-11. pci inbound tran slation address registers table 16-11 describes the fields of the pitar n registers. 16.3.1.3.2 pci inbound window b ase address registers (piwbar n ) the pci inbound window base address registers (piwbar n ) select the pci base address for the windows that are translated to the local address space of MPC8555E. addresses fo r inbound transactions are compared to these wi ndows. if a pci transaction does not fall wi thin one of these spaces, then the pci interface does not assert devsel. the piwbar n is shown in figure 16-12 . figure 16-12. pci inbound window base address registers 0 11 12 15 r ?ta w reset 0000_0000_0000_0000 16 31 r ta w reset 0000_0000_0000_0000 offset pci1: 0x0_8da0, 0x0_8dc0, 0x0_8de0 pci2: 0x0_9da0, 0x0_9dc0, 0x0_9de0 table 16-11. pitar n field descriptions bits name description 0?11 ? reserved, should be cleared. 12?31 ta translation address. indicates t he starting point of the inbound transl ated address. the translation address must be aligned based on the size field. ta correspond s to the high-order 20 bits of a 32-bit local address. 0 11 12 15 r bea ba w reset 0000_0000_0000_0000 16 31 r ba w reset 0000_0000_0000_0000 offset pci1: 0x0_8da8, 0x0_8dc8, 0x0_8de8 pci2: 0x0_9da8, 0x0_9dc8, 0x0_9de8 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 16-26 freescale semiconductor table 16-12 describes the fields of the piwbar n registers. 16.3.1.3.3 pci inbound wi ndow base extended addre ss registers (piwbear n ) the pci inbound window base extended a ddress registers (piwbear n ) contain the most significant bits of a 64-bit base address. note that inbound window 1 supports only a 32-bit base address and does not define an inbound window base extended address register. the piwbear n are shown in figure 16-13 . figure 16-13. pci inbound window ba se extended address registers table 16-13 describes the fiel ds of the piwbear n registers. 16.3.1.3.4 pci inbound window attributes registers (piwar n ) the pci inbound window attributes registers (piwar n ) define the window sizes to translate and other attributes for the translations. 16 gbytes is the largest window size allowed. the format of the piwbar n is shown in figure 16-14 . table 16-12. piwbar field descriptions bits name description 0?11 bea base extended address. corresponds to bits 43?32 of a 64-bit pci base address 12?31 ba base address. corresponds to bits 31?12 of a pci base address 0 11 12 15 r0 0 0 0 00000 0 0 0 bea w reset 0000_0000_0000_0000 16 31 r bea w reset 0000_0000_0000_0000 offset pci1: 0x0_8dac, 0x0_8dcc pci2: 0x0_9dac, 0x0_9dcc table 16-13. piwbear field descriptions bits name description 0?11 ? reserved 12?31 bea base extended address. corresponds to bits 63?44 of a 64-bit pci base address 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 16-27 figure 16-14. pci inbound window attributes registers table 16-14 describes the fields of the piwar n registers. 0 1 2 3 7 8 11 12 15 r en 0 pf 0 0000 tgi rtt w reset 0000_0000_0000_0000 16 19 20 25 26 31 r wtt 00000 0 iws w reset 0000_0000_0000_0000 offset pci1: 0x0_8db0, 0x0_8dd0, 0x0_8df0 pci2: 0x0_9db0, 0x0_9dd0, 0x0_9df0 table 16-14. piwar n field descriptions bits name description 0 en enable. enables this address translation 1?reserved 2 pf prefetchable. indicates that the address space is prefetchable so that pref etching and streaming are attempted. 0 not prefetchable 1prefetchable 3?7 ? reserved 8?11 tgi target interface 0000 pci1 0001 pci2 ... 1011 reserved 1100?1110 reserved 1111 local memory (ddr sdram, local bus, sram) note: if this field is set to an i/o port rather than loca l memory space, attributes for the external i/o transaction are assigned in an outbound atmu of that i/o controller. 12?15 rtt read transaction type. transaction type to run if acce ss is a read. the field description differs subject to the transaction being targeted to i/o interface or to local memory. following are the transaction type settings for reads to an i/o interface: 0000?0011 reserved 0100 read 0101?1111 reserved following are the transaction type settings for reads to local memory: 0000?0011 reserved 0100 read, do not snoop local processor 0101 read, snoop local processor 0110 reserved 0111 read, unlock l2 cache line 1000?1111 reserved 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 16-28 freescale semiconductor 16.3.1.4 pci error management registers when a pci error is detected, the appropriate error bit is set in the pci error de tect register. subsequent errors set the appropriate error bits in the error det ection registers, but releva nt information (attributes, address, and data) is captured only for the fi rst error. the pci error detect re gister is a write -1-to-clear type register. that is, reading from this register occurs normally; however, wr ite operations are different in that the bits can be cleared but not set. a bit is cleared whenever the register is written, and the data in the corresponding bit location is a 1. for ex ample, to clear bit 25 and not affect any other bits in the register, the value 0x0000_0040 is written to the register. the error bit is set regardless of the state of the corresponding error enable bit in the pci error enable register. the error enable bi ts are used to send or bl ock the error reporting to the interrupt mechanism. the interrupt can be cleared by writing 0xffff_ ffff to the pci error detect register. note that some errors are reported in two bits?one in the pci error detect regi ster (err_dr) and another in the pci bus status register in th e pci configuration header. these bits must be cleared separately; that is, clearing one does not clear the other. for exampl e, clearing the err_dr[m str abort error] does not clear the received master abort bit in the pci bus status register. in these cases, both bits must be cleared before further error repor ting can occur. refer to table 16-52 for pci mode error act ions. likewise, some errors are enabled by programming two bits?one in the pci error enable register and another in the pci bus command register in th e pci configuration header. 16?19 wtt write transaction type. transaction type to run if acce ss is a write. the field description differs subject to the transaction being targeted to an i/ o interface or to local memory. following are the transaction type settings for writes to an i/o interface: 0000?0011 reserved 0100 write 0101?1111 reserved following are the transaction type settings for writes to local memory: 0000?0011 reserved 0100 write, don?t snoop local processor 0101 write, snoop local processor 0110 write, allocate l2 cache line 0111 write, allocate and lock l2 cache line 1000?1111 reserved 20?25 ? reserved 26?31 iws inbound window size. inbound translation window size n which is the encoded 2^(n+1) bytes window size. the smallest window is 4 kbytes. 000000?001010 reserved 001011 4-kbyte window size 001100 8-kbyte window size ... 011111 4-gbyte window size 100000?111111 reserved for configuration and run-time registers, the window size is fixed at 010011 1-mbyte window size for register set 0, the window size is limited to 4 gbytes or smaller. table 16-14. piwar n field descriptions (continued) bits name description 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 16-29 a master-abort condition during a configur ation cycle is not necessarily an e rror. in this case, if relevant, the master abort error enable can be disabled to prevent the repor ting of master-aborts during outbound configuration cycles. master-aborts during configuration reads return 0xffff_ffff. if a data parity error occurs during an inbound conf iguration write access, the error is reported and captured. however, the errone ous data is written to the register spec ified in the transaction. therefore, pci data parity error recovery routines must include reinit ialization of the pci configur ation register if the error occurred during a configuration write. for an inbound configuration write transaction with a parity error, the MPC8555E always updates the register access and generates the error interr upt if the interrupt enabled bit is set. see section 16.4.2.13, ?pci error functions,? for more detail on error handling. 16.3.1.4.1 pci error det ect register (err_dr) figure 16-15. pci error detect register (err_dr) table 16-15 describes err_dr fields. note that uncorrect able read errors may cause the assertion of core_fault_in , which causes the core to generate a machin e check interrupt, unless it is disabled (by clearing hid1[rfxe]). if rfxe is ze ro and an error occurs, the appropria te parity detect and master-abort bits in err_dr must be cl eared and the appropriate enab le bits in err_en must be set to ensure that an interrupt is generated. see section 6.10.2, ?hardware implementati on-dependent register 1 (hid1).? 01 15 r multiple pci errors w reset 0000_0000_0000_0000 16 21 22 23 24 25 26 27 28 29 31 r addr parity error rcvd serr error mstr perr error tr g t perr error mstr abort error tr g t abort error owmsv error ormsv error w reset 0000_0000_0000_0000 offset pci1: 0x0_8e00, pci2: 0x0_9e00 table 16-15. err_dr field descriptions bits name description 0 multiple pci errors 0 multiple pci errors of th e same type were not detected (write-1-to-clear) 1 multiple pci errors of the same type were detected 1?20 ? reserved 21 addr parity error address parity error (write-1-to-clear) 22 rcvd serr error received serr error (write-1-to-clear) 23 mstr perr error master perr error (write-1-to-clear) 24 trgt perr error target perr error (write-1-to-clear) 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 16-30 freescale semiconductor 16.3.1.4.2 pci error capture disable regist er (err_cap_dr) figure 16-16. pci error capture disable register (err_cap_dr) 25 mstr abort error master abort error (write-1-to-clear) 26 trgt abort error target abort error (write-1-to-clear) 27 owmsv error outbound write memory space violation error (write-1-to-clear) 28 ormsv error outbound read memory space violation error (write-1-to-clear) 29?31 ? reserved 0 15 r w reset 0000_0000_0000_0000 16 21 22 23 24 25 26 27 28 29 31 r addr parity error capture disable rcvd serr error capture disable mstr perr error capture disable tr g t perr error capture disable mstr abort error capture disable tr g t abort error capture disable owmsv error capture disable ormsv error capture disable w reset 0000_0000_0000_0000 offset pci1: 0x0_8e 04, pci2: 0x0_9e04 table 16-16. err_cap_dr field descriptions bits name description 0?20 ? reserved 21 addr parity error capture disable disable capture for address parity errors 22 rcvd serr error capture disable disable capture for received serr errors 23 mstr perr error capture disable disable capture for master perr errors 24 trgt perr error capture disable disable capture for target perr errors 25 mstr abort error capture disable disable capture for master abort errors 26 trgt abort error capture disable disable capture for target abort errors 27 owmsv error capture disable disable capture fo r outbound write memory space violation errors 28 ormsv error capture disable disable capture for outbound read memory space violation errors 29?31 ? reserved table 16-15. err_dr field descriptions (continued) bits name description 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 16-31 16.3.1.4.3 pci error enable register (err_en) figure 16-17. pci error enable register (err_en) table 16-17 describes err_dr fields. note that uncorrect able read errors may cause the assertion of core_fault_in , which causes the core to generate a machin e check interrupt, unless it is disabled (by clearing hid1[rfxe]). if rfxe is zero and this error occurs, the appropria te parity detect and master-abort bits in err_dr must be cleared and the appropriate enable bits in err_en must be set to ensure that an interrupt is ge nerated. for more information, see section 6.10.2, ?hardware implementation-dependent register 1 (hid1).? 0 15 r w reset 0000_0000_0000_0000 16 21 22 23 24 25 26 27 28 29 31 r addr parity error enable rcvd serr error enable mstr perr error enable tr g t perr error enable mstr abort error enable tr g t abort error enable owmsv error enable ormsv error enable w reset 0000_0000_0000_0000 offset pci1: 0x0_8e08, pci2: 0x0_9e08 table 16-17. err_en field descriptions bits name description 0?20 ? reserved 21 addr parity error enable enable reporting address parity errors 22 rcvd serr error enable enable reporting received serr errors 23 mstr perr error enable enable reporting master perr errors 24 trgt perr error enable enable reporting target perr errors 25 mstr abort error enable enable reporting master abort errors 26 trgt abort error enable enable reporting target abort errors 27 owmsv error enable enable reporting outbound write memory space violation errors 28 ormsv error enable enable reporting outbound read memory space violation errors 29?31 ? reserved 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 16-32 freescale semiconductor 16.3.1.4.4 pci error attributes capture register (err_attrib) figure 16-18. pci error attributes capture register (err_attrib) 0 3 4 7 8 9 10 11 15 r high word byte enables low word byte enables high parity bit low parity bit error source w reset 0000_0000_0000_0000 16 19 20 30 31 r command valid w reset 0000_0000_0000_0000 offset pci1: 0x0_8e0c, pci2: 0x0_9e0c table 16-18. err_attrib field descriptions bits name description 0?3 high word byte enables pci byte enables for most significant word of the double word 4?7 low word byte enables pci byte enables for least significant word of the double word 8 high parity bit parity bit for most significant pci bus data word (only valid for 64-bit pci bus) 9 low parity bit parity bit for least significant pci bus data word 10 ? reserved 11?15 error source the source of the pci transaction 00000 pci interface 1 00001 pci interface 2 00010 reserved 00011 reserved 00100 local bus controller 00101 reserved 00110 reserved 00111 security 01000 reserved 01001 reserved 01010 reserved 01011 reserved 01100 reserved 01101 reserved 01110 reserved 01111 reserved 10000 e500 core (instruction) 10001 e500 core (data) 10010 reserved 10011 reserved 10100 cpm 10101 dma 10110 rdc 10111 sap 11000 tsec1 11001 tsec2 11010 reserved 11011 reserved 11100 reserved 11101 reserved 11110 reserved 11111 reserved 16?19 command pci command 20?30 ? reserved 31 valid info the pci bus capture registers contain valid information 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 16-33 16.3.1.4.5 pci error address capture register (err_addr) figure 16-19. pci error address capture register (err_addr) 16.3.1.4.6 pci error extended addr ess capture regist er (err_ext_addr) figure 16-20. pci error extended addr ess capture register (err_ext_addr) 16.3.1.4.7 pci error data lo w capture regi ster (err_dl) note that for inbound reads that have data pa rity errors, only the address (err_addr and err_ext_addr) and attributes (err_attrib) are captured. the data is not captured. 0 15 r memory address w reset 0000_0000_0000_0000 16 31 r memory address w reset 0000_0000_0000_0000 offset pci1: 0x0_8e10, pci2: 0x0_9e10 table 16-19. err_addr field descriptions bits name description 0?31 memory address memory transaction address 0 15 r memory extended address w reset 0000_0000_0000_0000 16 31 r memory extended address w reset 0000_0000_0000_0000 offset pci1: 0x0_8e14, pci2: 0x0_9e14 table 16-20. err_ext_addr field descriptions bits name description 0?31 memory extended address memory transaction extended address 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 16-34 freescale semiconductor figure 16-21. pci error data low capture register (err_dl) 16.3.1.4.8 pci error data hi gh capture register (err_dh) note that for inbound reads that have data pa rity errors, only the address (err_addr and err_ext_addr) and attributes (err_attrib) are captured. the data is not captured. figure 16-22. pci error data high capture register (err_dh) 0 15 r data low w reset 0000_0000_0000_0000 16 31 r data low w reset 0000_0000_0000_0000 offset pci1: 0x0_8e18, pci2: 0x0_9e18 table 16-21. err_dl field descriptions bits name description 0?31 data low least significant pci bus data 0 15 r data high w reset 0000_0000_0000_0000 16 31 r data high w reset 0000_0000_0000_0000 offset pci1: 0x0_8e1c, pci2: 0x0_9e1c table 16-22. err_dh field descriptions bits name description 0?31 data high most significant pci bus data word (only valid with 64-bit pci bus) 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 16-35 16.3.1.4.9 pci gasket ti mer register (gas_timr) figure 16-23. pci gasket timer register (gas_timr) 16.3.2 pci configuration header the pci local bus specification defines the configuration regi sters contained within the pci configuration header from 0x00 through 0x3f. 07815 r0 0 0 0 0 0 0 en tcnt w reset 0000_0001_0000_0000 16 31 r tcnt w reset 0011_1111_1111_1111 offset pci1: 0x0_8e20, pci2: 0x0_9e20 table 16-23. gas_timr field descriptions bits name description 0?6 ? reserved 7 en gasket timer enable pci default: gasket timer is enabled 8?24 tcnt number of system clocks to purge a non-prefetchable inbound read buffer 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 16-36 freescale semiconductor figure 16-24 lists the common pci configuration h eader as implemented by the MPC8555E. figure 16-24. MPC8555E pci configuration header table 16-49 in section 16.4.2.11.1, ?pci confi guration space header,? provides a summary of the pci configuration header registers. detailed descriptions of thes e registers are provided in the pci local bus specification . 16.3.2.1 pci vendor id register?offset 0 x 00 the pci vendor id register, shown in figure 16-25 , is used to identify the manufacturer of the part. figure 16-25. pci vendor id register table 16-24 describes pci vendor id register fields. 15 0 r vendor id w reset 0001_0000_0101_0111 offset 0x00 table 16-24. pci vendor id register field descriptions bits name description 15?0 vendor id 0x1057 (freescale) reserved device id vendor id pci bus status pci bus command bus base class code bus programming interface subclass code revision id bist control bus latency timer header type bus cache line size pci bus max lat pci bus interrupt pin pci bus max gnt pci bus interrupt line 00 04 08 0c 3c address offset (hex ) pci configuration and status register base address register (pcsrbar) 10 24 40 44 / / / / / / / / pci bus arbiter configuration 64-bit high memory base address register 34 38 / / / / / / / / 2c subsystem id subsystem vendor id 14 32-bit memory base address register 18 64-bit low memory base address register 1c 64-bit high memory base address register 20 / / / / / / / / pci bus function pci bus capability pointer 28 64-bit high memory base address register 64-bit low memory base address register 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 16-37 16.3.2.2 pci device id register?offset 0 x 02 the pci device id register, shown in figure 16-26 , is used to identify the device. figure 16-26. pci device id register 16.3.2.3 pci bus command register?offset 0 x 04 the 2-byte pci bus command register provides control over the ability to generate and respond to pci cycles. table 16-26 describes the bits of the pci bus command register. figure 16-27. pci bus command register 15 0 rdevice id w reset 0000_0000_0000_1010 offset 0x02 table 16-25. pci device id register field descriptions bits name description 15?0 device id 0x000a: MPC8555E 0x000c: mpc8541 15 10 9 8 7 6 5 4 3 2 1 0 r fast back-to-b ack serr parity error response memory-write- and-invalidate special cycles bus master memory space i/o space w reset 0000_0000_0000_0*00 pci1: *0 = agent, 1 = host, pci2: *= 1 offset 0x04 table 16-26. pci bus command register field descriptions bits name description 15?10 ? reserved 9fast back-to-back hard-wired to 0, indicating that this pci controller (as a master) does not run fast back-to-back transactions 8 serr controls the pci n _serr driver of this pci controller. this bit (and bit 6) must be set to report address parity errors. 0 disables the pci n _serr driver 1 enables the pci n _serr driver 7?reserved 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 16-38 freescale semiconductor 16.3.2.4 pci bus status register?offset 0 x 06 the 2-byte pci bus status regi ster is used to record status inform ation for pci bus bus-related events. the definition of each bit is given in table 16-27 . only 2-byte accesses to address offset 0x06 are allowed. note that some errors are reported in two bits?one in the pci bus stat us register and another in the pci error detect register (err _dr). these bits must be cleared separately; that is , clearing one does not clear the other. for example, clearing the err_dr[mstr a bort error] does not clear th e received master abort bit in the pci bus status register. in these cases, both bits must be cleared before further error reporting can occur. refer to table 16-52 for pci mode error actions. like wise, some errors are enabled by programming two bits?one in the pci bus command regist er and another in the pc i error enable register (err_en). reads to this register behave norma lly. writes are slightly different in that bits can be cleared, but not set. a bit is cleared whenever the register is written, an d the data in the corresponding bit location is a 1. for example, to clear bit 14 and not affect any other bits in the register, write the value 0b0100_0000_0000_0000 to the register. 6 parity error response controls whether this pci controller responds to parity errors 0 parity errors are ignored and normal operation continues. 1 parity errors cause the appropriate bit in the pci st atus register to be set. however, note that errors are reported based on the values set in the pci error enable and detection registers. 5?reserved 4 memory-write- and-invalidate hard-wired to 0, indicating that this pci cont roller, acting as a master, can not generate the memory-write-and-i nvalidate command. 3 special-cycles hard-wired to 0, indicating that this pci controller (as a targ et) ignores all special-cycle commands. 2 bus master indicates whether this pci c ontroller is configured as a master. for pci1, the reset state of this bit depends on whether pci1 is configured in host mode (b us master = 1) or agent mode (bus master = 0). 0 disables the ability to generate pci accesses 1 enables this pci controller to behave as a pci bus master note that the bus master bit in the pci bus comm and register should be set before attempting an outbound configuration access. 1 memory space controls whether this pci controller (as a target) responds to memory accesses 0 this pci controller does not respond to pci memory space accesses. 1 this pci controller (as a target) responds to pci memory space accesses. 0 i/o space hard-wired to 0, indicating that this pci co ntroller (as a target) does not respond to pci i/o space accesses table 16-26. pci bus command regist er field descriptions (continued) bits name description 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 16-39 figure 16-28. pci bus status register . 15 14 13 12 11 10 9 8 7 6 5 4 3 0 r detected parity error signaled system error received master abort received target abort signaled target abort devsel timing master data parity error detected fast back-to- back capable 66-mhz capable capabilities list w reset 0000_0000_1010_0000 offset 0x06 table 16-27. pci bus status register field descriptions bits name description 15 detected parity error set whenever this pci controller detects a pci parity error, even if parity error handling is disabled (as controlled by bit 6 in the pci bus command register 14 signaled system error set whenever this pci controller asserts pci n _serr 13 received master-abort set whenever this pci controller, acting as the pci master, terminates a transaction (except for a special-cycle) using master-abort 12 received target-abort set whenever a pci transaction initiated by this pci controller (excluding a special-cycle) is terminated by a target-abort 11 signaled target-abort set whenever this pci controller, acting as the pci target, issues a target-abort to a pci master 10?9 devsel timing hard-wired to 0b00, indicating that this pci controller uses fast device select timing 8 master data parity error detected set upon detecting a data parity error. three co nditions must be met for this bit to be set: ? this pci controller detected a parity error. ? this pci controller was acting as the bus master for the operation in which the error occurred. ? bit 6 in the pci bus command register was set. 7 fast back-to-back capable hard-wired to 1, indicating that this pci contro ller (as a target) is capable of accepting fast back-to-back transactions 6?reserved 5 66-mhz capable read-only bit indicates that this pc i controller is capable of 66 mhz pci bus operation 4 capabilities list hard-wired to 0 3?0 ? reserved 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 16-40 freescale semiconductor 16.3.2.5 pci revision id register?offset 0 x 08 the pci revision id regist er is used to identify the revision of the part. figure 16-29. pci revision id register 16.3.2.6 pci bus programming in terface register?offset 0 x 09 table 16-29 describes the pci bus program ming interface register (pir). figure 16-30. pci bus programming interface register 7 0 r revision id w reset revision specific offset 0x08 table 16-28. pci revision id register field descriptions bits name description 7?0 revision id revision specific 7 0 r programming interface w reset 0000_000* pci1: *0 = host, 1 = agent, pci2: *0 = host offset 0x09 table 16-29. pci bus programming interface register field descriptions bits name description 7?0 programming interface 0x00 when the pci controller is configured as host bridge 0x01 when the pci controller is configured as an agent device 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 16-41 16.3.2.7 pci subclass co de register?offset 0x0a table 16-31 describes the pci subcla ss code register (pscr). figure 16-31. pci subclass code register 16.3.2.8 pci bus base class code register?offset 0 x0b table 16-31 describes the pci bus base class code register (pbccr). figure 16-32. pci bus base class code register 16.3.2.9 pci bus cache line size register?offset 0x0c table 16-32 describes the pci bus cache line size register (pclsr). figure 16-33. pci bus cache line size register 7 0 r subclass code w reset 0010_0000 offset 0x0a table 16-30. pci subclass code register field descriptions bits name description 7?0 subclass code powerpc?0x20 7 0 r base class code w reset 0000_1011 offset 0x0b table 16-31. pci bus base class code register field descriptions bits name description 7?0 base class code processor?0x0b 7 0 r cache line size w reset 0000_0000 offset 0x0c 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 16-42 freescale semiconductor 16.3.2.10 pci bus latenc y timer register?0x0d table 16-33 describes the pci latenc y timer register (pltr). figure 16-34. pci bus latency timer register 16.3.2.11 pci base address registers a pci base address register points to the beginnings of e ach address range to which the device responds by asserting pci n _devsel . the base address regist er (bar) at offset 0x10 is a fixed 1-mbyte window that is automatically translated to the local confi guration, control, and status registers address space. the other base address registers are aliases (with differing format ) of the pci inbound atmu windows; see section 16.3.1.3, ?pci atmu inbound registers.? the 32-bit base address register at offset 0x14 corresponds to inbound atmu window 1; the 64-bit base address re gisters at offsets 0x18 and 0x20 correspond to inbound atmu windows 2 and 3. if one of these registers is wr itten, the corresponding atmu register is also updated; if a pci inbound atmu regist er is written, the corr esponding bar is also updated. if one of these registers is read, the co rresponding size of atmu is returned on the pci bus providing valid window size in the inbound atmu window attributes register. note that pcsrbar cannot be update d through the inbound atmu registers. table 16-32. pci bus cache line size register field descriptions bits name description 7?0 cache line size represents the cache line size of the processor in term s of 32-bit words (8 32-bit words = 32 bytes). pclsr is read-write, however for pci operation an attempt to program this register to any value other than 0x8 results in clearing it. 7 32 0 r latency timer latency timer w reset 0000_0000 offset 0x0d table 16-33. pci bus latency timer register field descriptions bits name description 7?3 latency timer the maximum number of pci clocks that the de vice, when mastering a transa ction, holds the bus after pci bus grant has been negated the value is in pci clocks. the pci 2.2 specification gives rules by which the pci bus interface unit completes transactions when the timer has expired. 2?0 latency timer read-only bits. the minimum latency timer value when set is 8 pci clocks. 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 16-43 figure 16-35. pci configuration and status register base address register (pcsrbar) figure 16-36. 32?bit memory base address register 31 20 19 16 r address w reset 0000_0000_0000_0000 15 43 2 10 r pref type msi w reset 0000_0000_0000_0000 offset 0x10 table 16-34. pcsrbar field descriptions bits name description 31?20 address indicates the base address that the inbound configur ation/run-time window resides at. this window is fixed at 1 mbyte. 19?4 ? reserved 3prefprefetchable 2?1 type type. 00?locate anywhere in 32-bit address space 0 msi memory space indicator 31 16 r address w reset 0000_0000_0000_0000 15 12 11 4 3 2 1 0 r address pref type msi w reset 0000_0000_0000_0000 offset 0x14 table 16-35. 32-bit memory base address register field descriptions bits name description 31?12 address indicates the base address that the inbound memory window resides at. the number of upper bits that the device allows to be writable is selected through the inbound translation windows. 11?4 ? reserved. the device allows a 4-kbyte window minimum. 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 16-44 freescale semiconductor figure 16-37. 64-bit low memory base address register figure 16-38. 64-bit high memory base address register 3prefprefetchable 2?1 type type. 00 - locate anywhere in 32-bit address space 0 msi memory space indicator 31 16 r address w reset 0000_0000_0000_0000 15 12 11 4 3 2 1 0 r address pre type msi w reset 0000_0000_0000_0100 offset 0x18, 0x20 table 16-36. 64-bit low memory base address register field descriptions bits name description 31?12 address indicates the base address that the inbound memory window resides at. the number of upper bits that the device allows to be writable is selected through the inbound translation windows. 11?4 ? reserved. the device allows a 4-kbyte window minimum. 3prefprefetchable 2?1 type type. 10 - locate anywhere in 64-bit address space 0 msi memory space indicator 31 16 r address w reset 0000_0000_0000_0000 15 0 r address w reset 0000_0000_0000_0000 offset 0x1c, 0x24 table 16-35. 32-bit memory base address register field descriptions (continued) bits name description 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 16-45 16.3.2.12 pci subsystem vendor id register the pci subsystem vendor id register is used to identify the subsystem. figure 16-39. pci subsystem vendor id register 16.3.2.13 pci subsystem id register the pci subsystem id register is used to identify the subsystem. figure 16-40. pci subsystem id register table 16-37. bit setting for 64-bit high memory base address register bits name description 31?0 address indicates the base address that the inbound memory window resides at. the number of upper bits that the device allows to be writable is selected through the inbound translation windows. if no access to local memory is to be permitted by external masters then all bits are programmed. 15 0 r subsystem vendor id w reset 0000_0000_0000_0000 offset 0x2c table 16-38. pci subsystem vendor id register field descriptions bits name description 15?0 subsystem vendor id 0x0000 15 0 r subsystem id w reset 0000_0000_0000_0000 offset 0x2e table 16-39. pci subsystem id register field descriptions bits name description 15?0 subsystem id 0x0000 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 16-46 freescale semiconductor 16.3.2.14 pci bus capabilities pointer register the pci bus capabilities pointer identifies a dditional functionality supported by the device. figure 16-41. pci bus capabilities pointer register 16.3.2.15 pci bus interrupt line register figure 16-42. pci bus interrupt line register 16.3.2.16 pci bus interrupt pin register the MPC8555E has 12 general purpose interrupt reque st lines (irq[0:11]) and an interrupt output, irq_out (active low, level sensitive), to which all extern al and most internal in terrupt sources (including pci) can be routed. irq_out is mapped to pci_inta as a default. note that th is device does not respond to intack or special cycle commands on the pci interfaces. 7 0 r capabilities pointer w reset 0000_0000 offset 0x34 table 16-40. pci bus capabilities po inter register field descriptions bits name description 7?0 capabilities pointer no additional capabilities 7 0 r interrupt line w reset 0000_0000 offset 0x3c table 16-41. pci bus interrupt line register field descriptions bits name description 7?0 interrupt line this register is used to communicate interrupt line routing information. 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 16-47 figure 16-43. pci bus interrupt pin register 16.3.2.17 pci bus minimum grant (min gnt) register figure 16-44. pci bus minimum grant register 16.3.2.18 pci bus maximum latency (max lat) register figure 16-45. pci bus maximum latency register 7 0 r interrupt pin w reset 0000_0001 offset 0x3d table 16-42. pci bus interrupt pin register field descriptions bits name description 7?0 interrupt pin pci_inta pin selected 7 0 rmingnt w reset 0000_0000 offset 0x3e table 16-43. pci bus minimum grant register field descriptions bits name description 7?0 mingnt specifies the length of the device?s burst peri od (0x00 indicates that this pci controller has no major requirements for the settings of latency timers) 7 0 r maxlat w reset 0000_0000 offset 0x3f table 16-44. pci bus maximum latency register field descriptions bits name description 7?0 maxlat specifies how often the device needs to gain access to the pci bus (0x00 indica tes that this pci controller has no major requirements for the settings of latency timers) 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 16-48 freescale semiconductor 16.3.2.19 pci bus function register (pbfr) the 2-byte pci bus function register is used to determine different fe atures how the pci interface in bus 0 is configured. this register is at pci configuration space at offset 0x44. figure 16-46. pci bus function register 16.3.2.20 pci bus arbiter configuration register (pbacr) the pci bus arbiter configur ation register is used to determine the configurati on of the pci bus arbiter. figure 16-47. pci bus arbiter configuration register 15 6 5 4 3 2 1 0 r0 0 0 0 00000 0 acl 0p640 0pah w reset pci1: 0000_0000_00*0_*00*, pci2: 0000_0000_0000_0000 *depends on the state of the rese t configuration signals at reset offset 0x44 table 16-45. pci bus function register fiel d descriptions bits name description 15?6 ? reserved 5 acl agent configuration lock. indicates to an external host whether the local processor is doing internal configuration and must be explicitly set and cleared by t he local processor during this time. acl is set during reset if the la27 (cfg_cpu_boot) input selects the cpu as the configuration owner. this bit is only meaningful in agent mode. 0 pci interface allows incoming pci configuration cycles 1 pci interface retries all incoming pci configuration cycles 4?reserved 3 p64 pci 64-bit configuration. read-on ly. indicates the reset value of t he pci 64-bit configuration signal, pci1_req64 . 0 64-bit interface functions as a 32-bit interface 1 64-bit interface functions as a 64-bit interface 2?1 ? reserved 0 pah pci agent/host. read-only. indicates the reset val ue of the pci host/agent configuration signal, lwe2 . 0 pci interface is in host mode 1 pci interface is in agent mode 15 14 13 12 11 10 9 8 7 6 2 1 0 rpad pm 0 pbmd 00000 pbmp 0 dp w reset 0000_0000_0000_0000 offset 0x46 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 16-49 16.4 functional description this section describes the func tionality of the pci interface. 16.4.1 pci bus arbitration pci bus arbitration is access-based. bus masters must arbitrate for each acces s performed on the bus. the pci bus uses a central arbitr ation scheme where each master has its own unique request (r eq ) output and grant (g nt ) input signal. a simple request/g rant handshake is used to gain access to the bus. arbitration for the bus occurs during the previous access so that no pci bus cycles are consumed due to arbitration (except when the bus is idle). the MPC8555E provides bus arbitration logic for its master interface and up to five other external pci bus masters. the on-chip pci arbiter is independent of host or agent mode . the on-chip pci arbiter functions in both host and agent modes, or it can be di sabled to allow for an external pci arbiter. a configuration signal (pci n _gnt2 ) sampled at the negation of hreset determines if the on-chip pci arbiter is enabled (high) or disabled (low). the state of the reset signal is reflected in bi t 15 (read-only) of table 16-46. pci bus arbiter configuration register field descriptions bits name description 15 pad pci arbiter disable. determines if the device is th e pci arbiter on the pci bus or not. the reset state is determined by the inverse of the pci n _gnt2 configuration input signal when reset is released. 0 device is the pci arbiter 1 device is not the pci arbiter. device presents its request on pci n _ req0 to the external arbiter and receives its grant on pci n _ gnt0 14 pm parking mode. controls which device receives the bus grant when there are no outstanding bus requests and the bus is idle. 0 the bus is parked on the last device to use the bus. 1 the bus is parked on the device. 13 ? reserved 12 pbmd pci broken master disable. determines if the device ignores the bus requests of an initiator that requests the bus for an excessive period without using the bus 0 an initiator that requests the bus and receives the grant must begin using the bus within 16 pci clock periods after the bus becomes idle or else its request is subsequently ignored. 1 no requests are ignored. 11?7 ? reserved 6?2 pbmp pci bus master priorities. determines arbitration priority given to different masters on the pci bus. bit 6 corresponds to the priority of the master sourcing pci n _ req0 ; bit 2 corresponds to the priority of the master sourcing pci n _ req4 . 0master n is low priority 1master n is high priority 1?reserved 0 dp device priority. determines this device?s arbitration priority 0 device is low priority 1 device is high priority 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 16-50 freescale semiconductor the pci bus arbitration control regi ster (pbacr[pad]). note that pa d is the inverse of the arbiter configuration signal; that is, when pad = 0 the ar biter is enabled, and when pad = 1 the arbiter is disabled. see chapter 4, ?reset, clocking, and initialization,? for more information on the reset configuration signals. if the on-chip pci arbiter is enabled, a request-grant pair of signals is provided for each external master (pci n _req [0:4] and pci n _gnt [0:4]). in addition, there is an internal request/grant pair for the internal master state machine of the MPC8555E that governs in ternal accesses to the pci interface. if the on-chip pci arbiter is disabled, the MPC8555E uses the pci n _ req0 signal as an output to issue its request to the external arbiter and uses the pci n _ gnt0 signal as an input to receive its grant from the external arbiter. the following sections describe the operation of the on-chip pci arbiter that arbitrates between external pci masters and the internal pci bus master of the MPC8555E. 16.4.1.1 pci bus arbiter operation the on-chip pci arbiter uses a pr ogrammable two-level, round-robin ar bitration algorithm. each of the five external masters, pl us the MPC8555E, can be programmed for tw o priority levels, high or low, using the appropriate bits in the pbacr. within each prio rity group, the pci bus grant is asserted to the next requesting device in numerical order, with the MPC8555E positioned before device 0. conceptually, the lowest priority de vice is the master that is curr ently using the bus, and the highest priority device is the devi ce that follows the current master in numerical order and group priority. this is considered to be a fair algorithm, since a single device cannot prevent other de vices from having access to the bus; it automatically becomes the lowest priority de vice as soon as it begins to use the bus. if a master is not requesting the bus, then its transaction slot is given to the ne xt requesting device within its priority group. a grant is awarded to the highest priority request ing device as soon as the current master begins a transaction; however, the granted de vice must wait until the bus is relinquished by the current master before initiati ng a transaction. the grant given to a particular device may be rem oved and awarded to anothe r higher priority device, whenever the higher priority device asserts its reque st. if the bus is idle when a device requests the bus, then the arbiter withholds the grant for one clock cycl e. the arbiter re-evaluates the priorities of all requesting devices and grants the bus to the highest priority device in the following clock cycle. this allows a turnaround clock when a highe r priority device is using address stepping or when the bus is parked. the low-priority group collectively has one bus transaction request slot in the high-priority group. for n high-priority device s and m low-priority devices, each high-priori ty device is guaranteed at least 1 of n+1 bus transactions and each low-priority devi ce is guaranteed at least 1 of (n+1) m bus transactions, with one low-priority device receiving the grant in 1 of n+1 bus transactions. if a ll devices are programmed to the same priority level, or if the low-priority group ha s only one device, th e algorithm defaults to give each device an equal number of bus grants in round-robin sequence. for the example in figure 16-48 , assume that several devices are re questing the bus. if two masters are in the high-priority group and three are in the low-priority group, each high-pr iority master is guaranteed at 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 16-51 least one out of three transaction slots and each lo w-priority master is guaranteed one out of nine transaction slots. in figure 16-48 , the grant sequence (with al l devices, except device 4 reque sting the bus and device 3 being the current master) is 0, 2, MPC8555E, 0, 2, 1, 0, 2, 3, ?, and re peating. if device 2 is not requesting the bus, the grant sequence is 0, mp c8555e, 0, 1, 0, 3, ?, and repeating. if device 2 requests the bus when device 0 is conducting a tran saction and the MPC8555E has the next grant, the MPC8555E has its grant removed and device 2 is awarded the grant since devi ce 2 is higher priority than the MPC8555E when device 0 has the bus. figure 16-48. pci arbitration example 16.4.1.2 pci bus parking when no device is using or requesting the bus, the pci ar biter grants the bus to a selected device. this is known as parking the bus on the selected device. the selected device is required to drive the pci n _ad[31:0], pci n _c/be [3:0], and the pci parity signals to a stable value, preventing these signals from floating. the parking mode parameter (pbacr [pm]) determines which device the arbiter selects for parking the pci bus. if pbacr[pm] = 0 (or if the bus is not idle), then the bus is parked on the last master to use the bus. if the bus is idle and pbacr[pm] = 1, the bus is parked on the MPC8555E. 16.4.1.3 broken master lock-out the pci bus arbiter on the MPC8555E ha s a feature that allows it to lo ck out any masters that are broken or ill-behaved. the broken master fe ature is controlled by programming bit 12 of the pci bus arbitration control register (0 = enabled, 1 = disabled). when the broken master feature is enabled, a granted device that does not assert pci n _frame within 16 pci clock cycles after the bus is idle, has its gr ant removed and subsequent requests are ignored until its req is negated for at least one cl ock cycle. this prevents ill-be haved masters from monopolizing the bus. when the broken master feature is disabled, a device that requests the bus and receiv es a grant never loses its grant until and unless it begi ns a transaction or negates its req signal. note that disabling the broken master feature is not recommended. device 2 device 0 low- high-priority group device 1 device 3 low-priority group (1/3) (1/3) (1/3) (1/9) (1/9) (1/9) priority slot MPC8555E 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 16-52 freescale semiconductor 16.4.1.4 power-saving modes and the pci arbiter in the sleep power-saving mode, the cl ock signal driving sysclk can be disabled. if the clock is disabled, the arbitration logic is not able to perform its f unction. system programmers must park the bus with a device that can sustain the pci n _ad[31:0], pci n _c/be [3:0], and parity signals prior to disabling the sysclk signal. if the bus is parked on the mp c8555e when its clocks are stopped, the MPC8555E sustains the pci n _ad[31:0], pci n _c/be [3:0], and parity signals in their prior states. in this situation, the only way for another agent to use the pci bus is by waking the mpc 8555e. in nap and doze power-saving modes, the arbiter continues to operate allo wing other pci devices to run transactions. 16.4.2 pci bus protocol this section provides a general description of the pc i bus protocol. specific pci bus transactions are described in section 16.4.2.7, ?pci bus transactions.? refer to figure 16-49 , figure 16-50 , figure 16-51 , and figure 16-52 for examples of the transfer-control mechanisms describe d in this section. all signals are sampled on the rising edge of the pc i bus clock (sysclk). each signal has a setup and hold aperture with respect to the rising clock edge in which transitions are not allowed. outside this aperture, signal values or transi tions have no significance. see the MPC8555E powerquicc? iii integrated processor hardware specifications for specific setup and hold times. 16.4.2.1 basic transfer control the basic pci bus transfer mechanism is a burst. a burst is composed of an address phase followed by one or more data phases. fundamentally, all pci da ta transfers are contro lled by three signals?pci n _frame (frame), pci n _irdy (initiator ready), and pci n _trdy (target ready). an initiator asserts pci n _frame to indicate the beginning of a pci bus transaction and negates pci n _frame to indicate the end of a pci bus transaction. an initiator negates pci n _irdy to force wait cycles. a target negates pci n _trdy to force wait cycles. the pci bus is consider ed idle when both pci n _frame and pci n _irdy are negated. the first clock cycle in which pci n _frame is asserted indicates the beginning of the address phase. the address and bus command code are transferred in th at first cycle. the next cycle begi ns the first of one or more data phases. data is transferred between initiato r and target in each cycle that both pci n _irdy and pci n _trdy are asserted. wait cycles may be inserted in a data phase by the initiator (by negating pci n _irdy ) or by the target (by negating pci n _trdy ). once an initiator has asserted pci n _irdy , it cannot change pci n _irdy or pci n _frame until the current data phase completes regardless of the state of pci n _trdy . once a target has asserted pci n _trdy or pci n _stop , it cannot change pci n _devsel , pci n _trdy , or pci n _stop until the current data phase completes. in simpler terms, once an initiator or target has committed to the data transfer, it cannot change its mind. when the initiator intends to complete only one more data transfer (which coul d be immediately after the address phase), pci n _frame is negated and pci n _irdy is asserted (or kept asserted), indicating the initiator is ready. after the target indicates the final data transfer (by asserting pci n _trdy ), the pci bus may return to the idle state (both pci n _frame and pci n _irdy are negated) unless a fast back-to-back 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 16-53 transaction is in progress. in the case of a fast back-to-back transaction, an address phase immediately follows the last data phase. 16.4.2.2 pci bus commands a pci bus command is encoded in the pci n _c/be [3:0] signals during the address phase of a pci transaction. the bus command indicates to the target the type of transaction the initi ator is requesting. table 16-47 describes the pci bus commands implemented by the MPC8555E. table 16-47. pci bus commands pci n _c/ be [3:0] pci bus command MPC8555E supports as an initiator MPC8555E supports as a target definition 0000 interrupt- acknowledge yes no a read (implicitly addressing th e system interrupt controller). only one device on the pci bus should respond to this command; others ignore it. see section 16.4.2.12.1, ?interrupt-acknowledge transactions,? for more information. 0001 special cycle yes no provides a way to broa dcast select messages to all devices on the pci bus. see section 16.4.2.12.2, ?speci al-cycle transactions,? for more information. 0010 i/o-read yes no accesses agents mapped into the pci i/o space 0011 i/o-write yes no accesses agents mapped into the pci i/o space 0100 reserved 1 no no ? 0101 reserved 1 no no ? 0110 memory-read yes yes accesses either local memory or agents mapped into pci memory space, depending on the address. when a pci master issues this command to local memory, the MPC8555E (the target) fetches data from the requested address to the end of the cache line (32 bytes) from local memory, even though all of the data may not be requested by (or sent to) the initiator. 0111 memory-write yes yes accesses either local memory or agents mapped into pci memory space, depending on the address 1000 reserved 1 no no ? 1001 reserved 1 no no ? 1010 configuration- read yes agent mode only accesses the 256-byte configuration space of a pci agent. a specific agent is selected when its idsel signal is asserted during the address phase. see section 16.4.2.11, ?c onfiguration cycles,? for details. 1011 configuration- write yes agent mode only 1100 memory-read- multiple yes yes similar to the memo ry-read command, but also causes a prefetch of the next cache line (32 bytes) 1101 dual-address- cycle yes yes used to transfer a 64-bit address (in two 32-bit address cycles) to 64-bit addressable devices 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 16-54 freescale semiconductor 16.4.2.3 addressing pci defines three physical addres s spaces?pci memory space, pci i/o space, and pci configuration space. access to the pci memory and i/o space is st raightforward, although one must take into account the local memory acces s window and address tr anslation being used. the addr ess translation registers are described in section 16.3.1, ?pci memory mapped registers.? access to the pci configuration space is described in section 16.4.2.11, ?configuration cycles.? address decoding on the pci bus is performed by every device for every pci transaction. each agent is responsible for decoding its own a ddress. pci supports tw o types of address de coding?positive decoding and subtractive decoding. fo r positive decoding, each device looks fo r accesses in the address range that the device has been assigned. for s ubtractive decoding, one device on the bus looks for accesses that no other device has claimed. see section 16.4.2.4, ?device selection,? for information about claiming transactions. the information contained in the two low-order a ddress bits (pci n _ad[1:0]) varies by the address space (memory, i/o, or configuration). regardless of the encoding scheme, the two low-order address bits are always included in parity calculations. 16.4.2.3.1 memory space addressing for memory accesses, pci defines two types of burst ordering controlled by the two low-order bits of the address?linear incrementing (pci n _ad[1:0] = 0b00) and cache wrap mode (pci n _ad[1:0] = 0b10), as shown in table 16-48 . the other two pci n _ad[1:0] possibilities (0b01 a nd 0b11) are reserved. as an initiator, the MPC8555E always encodes pci n _ad[1:0] = 00 for pci memory space accesses. as a target, the MPC8555E executes a target disconnect after the first da ta phase completes if pci n _ad[1:0] = 01 or pci n _ad[1:0] = 0b11 during the address phase of a local memory access. see section 16.4.2.8.2, ?target-initiated termination,? for more information on ta rget disconnect conditions. 1110 memory-read- line yes yes indicates that an initiator is re questing the transfer of an entire cache line. this occurs only when the processor is performing a burst read. note that these processors perform burst reads only when the appropriate cache is enabled and the transaction is not cache-inhibited. 1111 memory-write- and-invalidate no yes indicates that an initiator is transf erring an entire cache line; if this data is in any cacheable memory, that cache line needs to be invalidated. 1 reserved command encodings are reserved for future us e. the MPC8555E does not respond to these commands. table 16-47. pci bus commands (continued) pci n _c/ be [3:0] pci bus command MPC8555E supports as an initiator MPC8555E supports as a target definition 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 16-55 for linear incrementing mode, the memory address is encoded/decoded using pci n _ad[31:2] or pci1_ad[63:2] in 64-bit mode. thereafter, the addres s is incremented by 4 bytes after each data phase completes until the transaction is te rminated or completed (a 4-byte data width per data pha se is implied). note that the two low-order bits on the addre ss bus are included in al l parity calculations. for cache wrap mode (pci n _ad[1:0] = 0b10) reads, the critical memory address is decoded using pci n _ad[31:2] or pci1_ad[63:2 ] in 64-bit mode. the address is incr emented by 4 bytes after each data phase completes until the end of the cache line is reac hed. for cache-wrap reads, the address wraps to the beginning of the current cache line and continues incrementing until th e entire cache line (32 bytes) is read. the MPC8555E does not support cache-w rap write operations and executes a target disconnect after the data phase for the end of the cache line completes for writes with pci n _ad[1:0] = 0b10. that is, the MPC8555E does not wrap back to the beginning of the cache line. note th at the two low-order bits on the address bus are included in all parity calculations. 16.4.2.3.2 i/o space addressing for pci i/o accesses, 32 address signals (pci n _ad[31:0]) are used to provi de a byte address. after a target has claimed an i/o access, it must determine if it can complete the entire access as indicated by the byte enable signals. if all the select ed bytes are not in the address range of the target, the entire access cannot complete. in this case, the ta rget does not transfer any data a nd terminates the transaction with a target-abort error. see section 16.4.2.8.2, ?target-initiated termination,? for more information. 16.4.2.3.3 configurat ion space addressing pci supports two types of conf iguration accesses that use di fferent formats for the pci n _ad[31:0] signals during the address phase. the two low-order bits of the address indicate the format used for the configuration address phase?type 0 (pci n _ad[1:0] = 0b00) or type 1 (pci n _ad[1:0] = 0b01). both address formats identify a specific device and a spec ific configuration regist er for that device. see section 16.4.2.11, ?configuration cycles,? for descriptions of the two formats. 16.4.2.4 device selection the pci n _ devsel signal is driven by the target of the current transaction. pci n _ devsel indicates to the other devices on the pci bus that the target ha s decoded the address and claimed the transaction. pci n _ devsel may be driven one, two, or thr ee clock cycles (fast, medium, or slow device select timing) following the address phase. device select timing is encoded into the device?s pci bus status register. if table 16-48. supported combinations of pci n _ad[1:0] pci n _ad[1:0] MPC8555E as target MPC8555E as initiator read write read write 00 linear ??? 01 reserved td td ? ? 10 cache wrap td ? ? 11 reserved td td ? ? 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 16-56 freescale semiconductor no agent asserts pci n _ devsel within three clock cycles of pci n _ frame , the agent responsible for subtractive decoding may claim th e transaction by asserting pci n _ devsel . a target must assert pci n _ devsel (claim the transaction) before or coincident with any other target response (assert pci n _ trdy , pci n _ stop , or data signals). in all cases except target-abort, once a target asserts pci n _ devsel , it must not negate pci n _ devsel until pci n _ frame is negated (with pci n _ irdy asserted) and the last data phase has co mpleted. for normal term ination, negation of pci n _ devsel coincides with the negation of pci n _ trdy or pci n _ stop . if the first access maps into a target?s address range, that target asserts pci n _ devsel to claim the access. however, if the initiator attempts to continue the burst access across the resour ce boundary, then the target must issue a target disconnect. the MPC8555E is hardwired for fast device select timing (pci bus status re gister [10?9] = 0b00). therefore, when the MPC8555E is the target of a transaction (local memory access or configuration register access), it asserts pci n _ devsel one clock cycle follow ing the address phase. as an initiator, if the MPC8555E doe s not detect the assertion of pci n _ devsel within four clock cycles after the address phase (that is, five clock cycles afte r it asserts pci n _ frame ), it terminates the transaction with a master-abort termination; see section 16.4.2.8.1, ?master-in itiated termination.? 16.4.2.5 byte alignment the byte enable signals of the pci bus (pci n _c/be , during a data phase) are us ed to determine which byte lanes carry meaningful data. the byte enable signals may enable different bytes for each of the data phases. the byte enables are valid on the edge of the clock that starts each data phase and stay valid for the entire data phase. note that parity is calculated for all bytes regardless of the state of the byte enable signals. see section 16.4.2.13.1, ?pci parity,? for more information. if the MPC8555E, as a target, detects no byte enables asserted, it comple tes the current data phase with no permanent change. this implies that on a read transa ction, the MPC8555E expects that the data is not changed, and on a write transact ion, the data is not stored. 16.4.2.6 bus drivi ng and turnaround to avoid contention, a turnaround cycle is required on al l signals that may be driven by more than one agent. the turnaround cycle occurs at diff erent times for different signals. the pci n _ irdy , pci n _ trdy , pci n _ devsel , and pci n _ stop signals use the address phase as their turnaround cycle. pci n _ frame , pci n _c/be [3:0], and pci n _ad[31:0] (or pci1_c/be [7:0] and pci1_ad[63:2] in 64-bit mode) signals use the idle cycle between tr ansactions (when both pci n _ frame and pci n _ irdy are negated) as their turnaround cycle. pci n _ perr has a turnaround cycle on the fourth cl ock cycle after the last data phase. the pci address/data signals, pci n _ad[31:0] or pci1_ad[63:2] in 64-bi t mode, are driven to a stable condition during every address/data phase. even when the byte enables indicate that byte lanes carry meaningless data, the signals carry st able values. parity is calculated on all bytes regardless of the byte enables. see section 16.4.2.13.1, ?pci parity,? for more information. 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 16-57 16.4.2.7 pci bus transactions this section provides descriptions of the pci bus transactions . all bus transactions follow the protocol as described in section 16.4.2, ?pci bus protocol.? read and write transactions are similar for the memory and i/o spaces, so they are described as generic read transactions and generic write transactions. the timing diagrams in this section show the re lationship of significant signals involved in bus transactions. when a signal is drawn as a solid line, it is actively being driven by the current master or target. when a signal is drawn as a dashed line, no agent is actively dr iving it. high-impedance signals are indicated to have indeterminate values when the dashed line is between the two rails. the terms ?edge? and ?clock edge? always refer to th e rising edge of the clock. the terms ?asserted? and ?negated? always refer to the globally visible state of the signal on the clock edge, and not to signal transitions. ? ? represents a turnaround cycle in the timing diagrams. 16.4.2.7.1 pci read transactions this section describes pci single-beat read tr ansactions and pci burst read transactions. a read transaction starts with the address phase, occurring when an initiator asserts pci n _ frame . during the address phase, pci n _ad contains a valid address and pci n _c/be contains a valid bus command. the first data phase of a read tran saction requires a turnaround cycle. th is allows the transition from the initiator driving pci n _ad as address signals to the target driving pci n _ad as data signals. the turnaround cycle is enforced by the target with the trdy signal. the target provi des valid data at the earliest one cycle after the turnaround cycle. the target must drive the pci n _ad signals when pci n _ devsel is asserted. during the data phase, the pci n _c/be signals indicate which byte lanes are involved in the current data phase. a data phase may consist of a da ta transfer and wait cycles. the pci n _c/be signals remain actively driven for both reads and writes fr om the first clock of the data phase through the end of the transaction. a data phase completes when data is transferred, which oc curs when both pci n _ irdy and pci n _ trdy are asserted on the same clock edge. when either pci n _ irdy or pci n _ trdy is negated, a wait cycle is inserted and no data is transfe rred. the initiator indicates the last data phase by negating pci n _ frame when pci n _ irdy is asserted. the transaction is considered complete when data is transferred in the last data phase. 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 16-58 freescale semiconductor figure 16-49 illustrates a pci single-beat read transaction. figure 16-49. pci single-beat read transaction figure 16-50 illustrates a pci burst read transaction. figure 16-50. pci burst read transaction 16.4.2.7.2 pci write transactions this section describes pci single-b eat write transactions, and pci burst write transactions. a pci write transaction starts with the address phase, occurring when an initiator asserts pci n _ frame . a write transaction is similar to a read transaction except no turnaround cycle is need ed following the address phase because the initiator provides both address and data. th e data phases are the sa me for both read and write transactions. although not shown in the figures, the initiator must drive the pci n _c/be signals, even if the initiator is not rea dy to provide valid data (pci n _ irdy negated). sysclk pci_ frame pci_ irdy pci_ad addr pci_ devsel pci_ trdy pci_c/be byte enables cmd data sysclk pci_ frame pci_ irdy pci_ad addr pci_ devsel pci_ trdy pci_c/be byte enables 1 data2 data1 cmd byte enables 2 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 16-59 figure 16-51 illustrates a pci single- beat write transaction. figure 16-51. pci single-beat write transaction figure 16-52 illustrates a pci burst write transaction. figure 16-52. pci burst write transaction 16.4.2.8 transaction termination a pci transaction may be terminated by either the initiator or the ta rget. the initiator is ultimately responsible for concluding al l transactions, regardless of the cause of the termin ation. all transactions are concluded when pci n _ frame and pci n _ irdy are both negated, indicating the bus is idle. 16.4.2.8.1 master-in itiated termination normally, a master initiates termination by negating pci n _ frame and asserting pci n _ irdy . this indicates to the target that the final data phase is in progress. the final data transfer occurs when both pci n _ trdy and pci n _ irdy are asserted. the transaction is considered complete when data is sysclk pci_ frame pci_ irdy pci_ad addr pci_ evsel pci_ trdy pci_c/be data cmd byte enables sysclk pci_ frame pci_ irdy pci_ad addr pci_ devsel pci_ trdy pci_c/be data4 data1 data2 data3 byte enables 1 byte enables 2 cmd bes 4 byte enables 3 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 16-60 freescale semiconductor transferred in the last data phase. after the final data phase, both pci n _ frame and pci n _ irdy are negated (the bus becomes idle). there are three types of ma ster-initiated termination: ? completion?refers to termination when the initiator has conclude d its intended transaction. this is the most common r eason for termination. ? timeout?refers to termination when the initiator loses its bus grant (gnt n is negated), and its internal latency timer has expired. the intende d transaction is not necessarily concluded. ? master-abort?an abnormal case of master-initiated terminati on. if no device (including the subtractive decoding agent) asserts pci n _ devsel to claim a transaction, the initiator terminates the transaction with a master-abort. for a ma ster-abort termination, the initiator negates pci n _ frame and then negates pci n _ irdy on the next clock. if a tran saction is terminated by master-abort (except for a special-c ycle command), the received mast er-abort bit (bit 13) of the pci bus status register is set. as an initiator, if the MPC8555E doe s not detect the assertion of pci n _ devsel within four clock cycles following the address phase (five clock cycles after asserting pci n _ frame ), it terminates the transaction with a master-abort. 16.4.2.8.2 target-initiated termination by asserting the pci n _ stop signal, a target may request that the initiator terminate the current transaction. once asserted, the target holds pci n _ stop asserted until the initiator negates pci n _ frame . data may or may not be transferred dur ing the request for termination. if pci n _ trdy and pci n _ irdy are asserted during the assertion of pci n _ stop , data is transferred. however, if pci n _ trdy is negated when pci n _ stop is asserted, it indicates that the target wi ll not transfer any more data; therefore, the initiator does not wait for a final data transf er as it would in a completion termination. when a transaction is terminated by pci n _ stop , the initiator must negate its req n signal for a minimum of two pci clock cycles, (one corresponding to when the bus goes to the idle state (pci n _ frame and pci n _ irdy negated)). if the initiator intends to comp lete the transaction, it can reassert its req n immediately following the two clock cy cles. if the initiator does not intend to complete the transaction, it can assert req n whenever it needs to use the pci bus again. there are three types of ta rget-initiated termination: ? disconnect?disconnect refers to termination requested because th e target is temporarily unable to continue bursting. disconnect im plies that some data has been transferred. the initiator may restart the transaction at a later time starting with the address of the next untransferred data. (that is, data transfer may resume where it left off.) ? retry?retry refers to terminati on requested because the target is currently in a state where it is unable to process the transaction. retry implies that no data was tr ansferred. the init iator may start the entire transaction over again at a later time. note that the pci local bus specification , rev. 2.2 requires that all retried tran sactions must be completed. ? target-abort?target-abort is an abnormal case of target-initiated termination. target-abort is used when a fatal error has occurred or when a target can never respond. 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 16-61 as a target, the MPC8555E terminates a transacti on with a target disconnect due to the following: ? it is unable to respond within eight pci clock cycles (not including the first data phase). ? the transaction is attempti ng to cross a 4-kbyte boundary. ? a single beat of data has be en transferred and the inbound atmu is marked non-prefetchable. ? the end of a cache line has been transferred for a cache-wrap mode write transaction. see section 16.4.2.3.1, ?memory space addressing,? for more information. as a target, the MPC8555E responds to a tran saction with a retry due to the following: ? the 32-clock latency time r has expired, and the first data phase has not begun. ? there is no more internal buffer sp ace available for an inbound transaction. target-abort is indicated by asserting pci n _ stop and negating pci n _ devsel . this indicates that the target requires termination of the tr ansaction and does not want the transaction retried. if a transaction is terminated by target-abort, the receive d target-abort bit (bit 12) of the initi ator?s bus status register and the signaled target-abort bit (bit 11) of the target?s bus status regist er are set. note that any data transferred in a target-aborted transaction may be corrupt. for pci writes to local memory, if an address parity error or data par ity error occurs, the MPC8555E aborts the transaction internally, but con tinues the transaction on the pci bus. 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 16-62 freescale semiconductor figure 16-53 shows several target-i nitiated terminations. figure 16-53. pci target -initiated terminations the three disconnect terminations are unique in the da ta transferred at the en d of the transaction. for disconnect a, the initiator is negating pci n _ irdy when the target asserts pci n _ stop and data is transferred only at the end of th e current data phase. for disconn ect b, the target negates pci n _ trdy one sysclk pci_ frame pci_ irdy pci_ devsel pci_ trdy pci_ stop sysclk pci_ frame pci_ irdy pci_ devsel pci_ trdy pci_ stop sysclk pci_ frame pci_ irdy pci_ devsel pci_ trdy pci_ stop sysclk pci_ frame pci_ irdy pci_ devsel pci_ trdy pci_ stop sysclk pci_ frame pci_ irdy pci_ devsel pci_ trdy pci_ stop disconnect a d isconnect b retry disconnect without data target abort 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 16-63 clock after it asserts pci n _ stop , indicating that the target can accept the current data, but no more data can be transferred. for disconnect-wit hout-data, the target asserts pci n _ stop when pci n _ trdy is negated indicating that the targ et cannot accept any more data. 16.4.2.9 fast back-to-back transactions the pci bus allows fast back-to- back transactions by the same ma ster. during a fast back-to-back transaction, the initiator starts the ne xt transaction immediately without an idle state. the last data phase completes when pci n _ frame is negated, and pci n _ irdy and pci n _ trdy are asserted. the current master starts another transaction in the clock cycle immediately followi ng the last data transfer for the previous transaction. fast back-to-back transactions must avoid contention on the pci n _ trdy , pci n _ devsel , pci n _ perr , and pci n _ stop signals. there are two types of fast back-t o-back transactions?thos e that access the same target and those that access multiple targets sequen tially. the first type places the burden of avoiding contention on the initiator; the sec ond type places the burden of a voiding contention on all potential targets. as an initiator, the MPC8555E does not perform any fast back-to-back transactions. as a target, the MPC8555E supports both types of fa st back-to-back transactions. during fast back-to-back tran sactions, the MPC8555E monitors the bus stat es to determine if it is the target of a transaction. if the previous tr ansaction was not directed to the MPC8555E and the current transaction is directed at the MPC8555E, it delays the assertion of pci n _ devsel (as well as pci n _ trdy , pci n _ stop , and pci n _ perr ) for one clock cycle to allow the ot her target to stop driving the bus. 16.4.2.10 dual address cycles the MPC8555E supports dual addre ss cycle (dac) commands (64-bit addressing on pci bus) as both an initiator and a target. dacs are differ ent from single address cycles (sac s) in that the address phase takes two pci beats instead of one pci beat to transfer (64-bit vs. 32-bit addressing). only pci memory commands can use dac cycl es; i/o, configuration, interrupt acknowledge, and special cycle command cannot use dac cycles. the mpc8 555e block supports single-beat and burst dac transactions. for the case of the local processor, dac genera tion depends on the setting of the potearx. if the potearx are programmed with nonzero values and a tran saction from the local pr ocessor core hits in one of the outbound windows, a dac tr ansaction is generated on the pci bus with the translated lower 32-bit addresses. refer to section 16.3.1.2, ?pci atmu outbound registers,? for more information. the timing sequence of the pci signals fo r single-beat dac reads is shown in figure 16-54 . the timing for a dac burst read is shown in figure 16-55 . figure 16-56 and figure 16-57 show timing examples for single-beat dac writes and bur st dac writes, respectively. 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 16-64 freescale semiconductor figure 16-54. dac single-beat read example figure 16-55. dac burst read example figure 16-56. dac single-beat write example lo-addr pci_clk pci_ad[31:0] pci_c/be [3:0] pci_frame pci_irdy pci_devsel pci_trdy data t/a hi-addr t/a x?d? t/a cmd byte enables lo-addr pci_clk pci_ad[31:0] pci_c/be [3:0] pci_frame pci_irdy pci_devsel pci_trdy t/a hi-addr t/a x?d? t/a cmd byte enables1 data1 data2 byte enables2 lo-addr pci_clk pci_ad[31:0] pci_c/be [3:0] pci_frame pci_irdy pci_devsel pci_trdy t/a hi-addr data x?d? t/a cmd byte enables 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 16-65 figure 16-57. dac burst write example 16.4.2.11 configuration cycles this section describes pci configur ation cycles used for configuri ng standard pci devices. the pci configuration space of any devi ce is intended for configuration, initialization, a nd catastrophic error-handling functions only. access to the pci configur ation space should be limi ted to initialization and error-handling software. 16.4.2.11.1 pci config uration space header the first 64 bytes of the 256-byte configuration space cons ists of a predefined head er that every pci device must support. the predefined header for all pci devices is shown in figure 16-58 . the first 16 bytes of the predefined header are defined the sa me for all pci devices; the remaini ng 48 bytes of the header may have differing layouts depending on the func tion of the device. most pci devices use the configuration header layout shown in figure 16-58 . the rest of the 256-byte configurati on space is device-specific. the pci header specific to the mp c8555e is described in section 16.3.2, ?pci configuration header.? lo-addr pci_clk pci_ad[31:0] pci_c/be [3:0] pci_frame pci_irdy pci_devsel pci_trdy t/a hi-addr data4 data1 data2 data3 x?d? t/a cmd be?s1 be?s2 be?s3 be?s4 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 16-66 freescale semiconductor figure 16-58. standard pci configuration header table 16-49 summarizes the configuration header registers. detailed descriptions of these registers are provided in the pci local bus specification, rev. 2.2. table 16-49. pci configuration space header summary address offset (hex) register name description 0x00 vendor id identifies the manufacturer of the de vice (assigned by the pci sig (special-interest group) to ensure uniqueness). 0x02 device id identifies the particular device (assigned by the vendor). 0x04 command provides coarse control over a device?s ability to generate and respond to pci bus cycles 0x06 status records status inform ation for pci bus-related events 0x08 revision id specifies a device-speci fic revision code (assigned by vendor) 0x09 class code identifies the generic f unction of the device and (in some cases) a specific register-level programming interface 0x0c cache line size specifie s the system cache line size in 32-bit units 0x0d latency timer specifies the value of the latency time r in pci bus clock units for the device when acting as an initiator 0x0e header type bits 0?6 identify the layout of bytes 0x10?0x3f; bit 7 indicates a multifunction device. the most common header type (0x00) is shown in figure 16-58 and in this table. device id vendor id status command class code revision id bist latency timer header type cache line size max_lat interrupt pin min_gnt interrupt line 0x00 0x04 0x08 0x3c address offset 0x2c 0x14 0x18 0x1c 0x20 0x24 0x28 0x30 0x34 0x38 0x10 0x0c expansion rom base address reserved reserved reserved base address registers subsystem id subsystem vendor id 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 16-67 16.4.2.11.2 accessing the pci conf iguration space in host mode to access the configuration space, a 32-bit value must be written to the pci cfg_addr register that specifies the target pci bus, the target device on that bus, and the configuration register to be accessed within that device. note that the bus master bit in the MPC8555E pci bus command regist er must be set before an outbound configurat ion access is attempted. device 0 on pci bus 0 is th e MPC8555E itself; thus, device 0, bus 0 is used to access the internal pci configuration header. when the MPC8555E detects an access to pci cfg_da ta, it checks the enable flag and the device number in the pci cfg_addr register. if the enable bit is set, and the device number is not 0b1_1111, the MPC8555E performs a configuration cycle transl ation function and runs a configuration-read or configuration-write transa ction on the pci bus. if the bus number corresponds to the local pci bus (bus number = 0x00), the MPC8555E performs a type 0 configuration cycle translation. if the bus number indicates a remote pci bus (that is, nonlocal), the MPC8555E perfor ms a type 1 configuration cycle translation. the device numbe r 0b1_1111 is used for performing in terrupt-acknowledge and special-cycle transactions. see section 16.4.2.12, ?other bus transactions,? for more information. see section 16.3.1.1.1, ?pci configuration address register (cfg_addr),? for details on pci cfg_addr and section 16.3.1.1.2, ?pci configuration data register (cfg_data),? for details on pci cfg_data. note that because all pci re gisters are intrinsically littl e-endian, in the following examples, the data in the configuration register is shown in little-endian order. core accesses to the pci cfg_data register should use the load/store with byte-reversed instructions. external pci masters that use the local address map to access configuration space do not need to reverse bytes since byte lane redirection from the little-endian pci bus is performed internally. 0x0f bist optional register for control and status of built-in self test (bist) 0x10?0x27 base address registers address mapping information for memory and i/o space 0x28 ? reserved for future use 0x2c subsystem vendor id identifies the subsystem vendor id (read-only for MPC8555E) 0x2e subsystem id identifies the sub system id (read-only for MPC8555E) 0x30 expansion rom base address base address and size information for expansion rom contained in an add-on board 0x34, 0x38 ? reserved for future use 0x3c interrupt line contains interrupt line routing information 0x3d interrupt pin indicates which interrupt pin the device (or function) uses 0x3e min_gnt specifies the length of the de vice?s burst period in 0.25 s units 0x3f max_lat specifies how often the device needs access to the bus in 0.25 s units table 16-49. pci configuration space header summary (continued) address offset (hex) register name description 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 16-68 freescale semiconductor example: configuration sequence, 4-byte data read from the revision id/standard programming interface/subclass code/class code re gisters at address offset 0x08 of th e pci configuration header (device 0 on the pci bus 0 is the MPC8555E itself). initial values: r0 contains 0x8000_0008 r1 contains ccsrbar + 0x0_8000 (address of pci cfg_addr register) r2 contains ccsrbar + 0x0_8004 (address of pci cfg_data register) r3 contains 0xffff_ffff register at 0x08 contains 0x0b20_0002 (0x0b to 0x08) code sequence: stw r0, 0 (r1) lwbrx r3, 0 (r2) results: address ccsrbar + 0x0_8000 contains 0x8000_0008 register r3 contains 0x0b20_0002 example: configuration sequence, 4-byte data write to pci register at address offs et 0x14 of device 1 on pci bus 0. initial values: r0 contains 0x8000_0814 r1 contains ccsrbar + 0x0_8000 (address of pci cfg_addr register) r2 contains ccsrbar + 0x0_8004 (address of pci cfg_data register) r3 contains 0x1122_3344 register at 0x14 contains 0xffff_ffff (0x17 to 0x14) code sequence: stw r0, 0 (r1) // update pci cfg_addr register to point to //register offset 0x14 of device 1. stwbrx r3, 0 (r2) results: address ccsrbar + 0x0_8000 contains 0x8000_0814 register at 0x14 contains 0x1122_3344 (0x17 to 0x14) example: configuration sequence, 2-byte data write to pc i register at address of fset 0x1c of device 1 on pci bus 0. initial values: r0 contains 0x8000_081c r1 contains ccsrbar + 0x0_8000 r2 contains ccsrbar + 0x0_8004 r3 contains 0xddcc_bbaa register at 0x1c contains 0xffff_ffff (0x1f to 0x1c) code sequence: stw r0, 0 (r1) sthbrx r3, 0 (r2) results: address ccsrbar + 0x0_8000 contains 0x8000_081c register at 0x1c contains 0xffff_bbaa (0x1f to 0x1c) 16.4.2.11.3 pci configuration in agent and agent lock modes in general, agents should not access the configuration space of other external pci devices. configuration of agents is a function usually rese rved for the host. when the MPC8555E is in agent mode, it responds to remote host-generated pci configuration cycles. this occurs when a configur ation command is decoded along with the idsel input signal being asserted. when the MPC8555E is in agent lock mode, it retries 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 16-69 all externally-generated pci configur ation cycles until the acl bit in the pci bus functi on register (0x44) is cleared. see section 16.5.1, ?power-on reset configuration modes,? for more information. in either agent or agent lock mode, access to the in ternal pci configuration header by the processor core is handled as described in section 16.4.2.11.2, ?accessing the pci co nfiguration space in host mode,? using device = 0 and bus = 0 in pci cfg_a ddr to indicate the internal pci header. 16.4.2.11.4 pci type 0 conf iguration translation figure 16-59 shows the pci type 0 transla tion function performed on the c ontents of the pci cfg_addr register to the pci n _ad[31:0] signals on the pci bus during the address phase of the configuration cycle. figure 16-59. pci type 0 configuration translation for pci type 0 configuration cycles, the MPC8555E translates the device number field of the pci cfg_addr register into a unique id sel signal for up to 21 different de vices. each device connects its idsel input to one of the pci n _ad[31:11] signals. for pci type 0 configuration cycles, the MPC8555E translates the device number to ad n as shown in table 16-50 . table 16-50. pci type 0 configuration?device number to ad n translation device number ad n used for idsel binary decimal 0b0_0000 0 ? 1 0b0_0001?0b0_1001 1?9 ? 2 0b0_1010 10 ad31 0b0_1011 11 ad11 0b0_1100 12 ad12 0b0_1101 13 ad13 0b0_1110 14 ad14 0 1 7 8 15 16 20 21 2324 29 30 31 bus number 000_0000 reserved device number function number register number e 00 31 11 10 2 1 0 idsel?only one signal high function/register number 00 contents of pci cfg_addr register pci_ad[31:0] signals during address phase see table 16-50 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 16-70 freescale semiconductor for pci type 0 translations, th e function number and register num ber fields are copied without modification onto the pci n _ad[10:2] signals during th e address phase. the pci n _ad[1:0] signals are driven to 0b00 during the address phase for type 0 configuration cycles. the MPC8555E implements address stepping on configurati on cycles so that the target?s idsel, which is connected directly to one of the pci_ad lines, reaches a stable value. this means that a valid address and command are driven on pci n _ad[31:0] and pci n _c/be [3:0] one clock cycle before the assertion of pci n _frame . 16.4.2.11.5 pci type 1 conf iguration translation for type 1 translations, the mpc 8555e copies the 30 high-order bits of the pci cfg_addr register (without modification) onto the pci n _ad[31:2] signals during the address phase. the MPC8555E 0b0_1111 15 ad15 0b1_0000 16 ad16 0b1_0001 17 ad17 0b1_0010 18 ad18 0b1_0011 19 ad19 0b1_0100 20 ad20 0b1_0101 21 ad21 0b1_0110 22 ad22 0b1_0111 23 ad23 0b1_1000 24 ad24 0b1_1001 25 ad25 0b1_1010 26 ad26 0b1_1011 27 ad27 0b1_1100 28 ad28 0b1_1101 29 ad29 0b1_1110 30 ad30 0b1_1111 3 31 ? 1 no external configuration transaction takes place; rather, internal registers are accessed. 2 no idsel line asserted. type0 configuration transaction is run, but ends with a master abort since no device responds. 3 a device number of all ones indicates a pci special-cycle or interrupt-acknowledge transaction. table 16-50. pci type 0 configuration?device number to ad n translation (continued) device number ad n used for idsel binary decimal 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 16-71 automatically translates pci n _ad[1:0] into 0b01 during the addr ess phase to indicate a type 1 configuration cycle. 16.4.2.12 other bus transactions there are two other pci transact ions that the MPC8555E supports?i nterrupt acknowledge and special cycles. as an initiator, the MPC8555E may init iate both interrupt acknowledge and special-cycle transactions; however, as a target, the MPC8555E ignores interrupt-acknow ledge and special-cycle transactions. both transactions ma ke use of the pci cfg_addr and pci cfg_data registers described in section 16.4.2.11.3, ?pci configuration in agent and agent lock modes.? 16.4.2.12.1 interrupt-acknowledge transactions the pci bus supports an interrupt -acknowledge transacti on. the interrupt-acknowledge command is a read operation implicitly addressed to the syst em interrupt controller. note that the pci interrupt-acknowledge command does not address the MPC8555E pic processor interrupt-acknowledge register and does not return the interrupt vector addr ess from the pic unit. see chapter 10, ?programmable interrupt controller,? for more information about the pic unit. when the MPC8555E detects a read to the pci cfg_da ta register, it checks the enable flag and the device number in the pci cfg_addr re gister. if the enable bit is set, the bus number corresponds to the local pci bus (bus number = 0x00), th e device number is all ones (0b1_1 111), the function number is all ones (0b111), and the register number is zero (0b00_0000), then the MPC8555E performs an interrupt-acknowledge transaction. if the bus numb er indicates a nonlocal pci bus, the MPC8555E performs a type 1 configuration cycl e translation, similar to any other configuration cycle for which the bus number does not match. the address phase contains no valid informati on other than the interrupt-acknowledge command (pci n _c/be [3:0] = 0b0000). although there is no explicit address, pci_ad are driven to a stable state, and parity is generated. only one device (the syst em interrupt controller) on the pci bus should respond to the interrupt-acknowledge command by asserting pci n _ devsel . all other devices on the bus should ignore the interrupt-acknowledge command. as stated previously, the MPC8555E pic unit does not respond to pci interrupt-acknowledge commands. during the data phase, the respon ding device returns the interrupt vector on pci_ad when pci n _ trdy is asserted. the size of the interrupt vector retu rned is indicated by the value driven on the pci n _c/be signals. the MPC8555E also provides a direct way to genera te pci interrupt-acknowle dge transactions. reads from pci int_ack at offset 0x0_8008 generate pci interrupt-acknowledge transactions. note that processor writes to these addresses do nothing. 16.4.2.12.2 special-cycle transactions the special-cycle command provides a mechanism to br oadcast select messages to all devices on the pci bus. the special-cycle comma nd contains no explicit de stination address but is broadcast to all pci agents. 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 16-72 freescale semiconductor when the MPC8555E detects a write to pci cfg_data, it checks the enable flag and the device number in pci cfg_addr. if the enable bi t is set, the bus numbe r corresponds to the lo cal pci bus (bus number = 0x00), the device number is all ones (0b1_1111), the function number is all ones (0b111), and the register number is zero (0b00_0000), then the MPC8555E performs a special-cycle transaction on the local pci bus. if the bus number indicates a nonlocal pci bus, th e MPC8555E performs a type 1 configuration cycle translation, similar to any othe r configuration cycle for whic h the bus number does not match. aside from the special-cycle command (pci n _c/be [3:0] = 0b0001) the address phase contains no other valid information. although there is no explicit address, pc i_ad are driven to a stab le state, and parity is generated. during the data phase, pci n _ad contain the special-cycle messa ge and an optional data field. the special-cycle message is encoded on the 16 least-significant bits (pci n _ad[15:0]); the optional data field is encoded on the most -significant 16 lines (pci n _ad[31:16]). the special-cycle message encodings are assigned by the pci sig steering committee. the current list of defined encodings are provided in table 16-51 . note that the MPC8555E does not automatically issue a special-cycle message when it enters any of its power-saving modes. it is the respons ibility of software to issue the a ppropriate special-cycle message, if needed. each receiving agent must determine whether the special -cycle message is applicab le to itself. assertion of pci n _ devsel in response to a special-cycle command is not necessary. the initiator of the special-cycle transaction can insert wait states but since there is no specific target, the special-cycle message and optional data field are valid on the first clock pci n _ irdy is asserted. all special-cycle transactions are terminated by master-abort; however, the master-abort bit in the initiator?s bus status register is not set for sp ecial-cycle terminations. 16.4.2.13 pci error functions pci provides for parity and other sy stem errors to be detected and reported. this section describes generation and detection of parity and error reporting for the pci bus. 16.4.2.13.1 pci parity generating parity is not opt ional; it must be performed by all pci- compliant devices. all pci transactions, regardless of type, calculate even pari ty; that is, the number of ones on the pci n _ad[31:0], pci n _c/be [3:0], and pci n _par signals all sum to an even number and the number of ones on the pci1_ad[63:33], pci1_c/be [7:4], and pci1_par64 signals all sum to an even number. table 16-51. special-cycle message encodings pci n _ad[15:0] message 0x0000 shutdown 0x0001 halt 0x0002 x86 architecture-specific 0x0003?0xffff ? 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 16-73 parity provides a way to determine, on each transaction, if the initiator successfully addressed the target and transferred valid data. the pci1_c/be [7:4] and pci n _c/be [3:0] signals are included in the parity calculation to ensure that the correct bus command is performed (during the address phase) and correct data is transferred (during the data phase). the agent responsible for dr iving the bus must also drive even parity on the par and pci1_par64 si gnals one clock cycle after a vali d address phase or valid data transfer, as shown in figure 16-60 . during the address and data phases, parity covers all 32 or 64 a ddress/data signals and 4 or 8 command/byte enable signa ls, regardless of whether al l lines carry meaningful in formation. byte lanes not actually transferring data must c ontain stable (albeit meaningless) data and are included in parity calculation. during configur ation, special-cycle, or interrupt-ac knowledge commands; some address lines are not defined, but are driven to stable values and are included in parity calculation. figure 16-60. pci parity operation 16.4.2.13.2 error reporting pci provides for the de tection and signaling of both parity and other system er rors. two signals are used to report these errors?pci n _ perr and pci n _ serr . the pci n _ perr signal is used exclusively to report data parity errors on all transact ions except special cycles. the pci n _ serr signal is used for other error signaling including address parity errors and data parity errors on special-cycle transactions; it may also be used to signal other system errors. note that some errors are enab led by programming two bits?one in th e pci bus command register and another in the pci error enable register (err_en). likewise, some errors are reported in two bits?one in the pci bus status register and another in the pci error detect register (err_dr). these bits must be cleared separately; that is , clearing one does not clear the other. for example, clearing the err_dr[mstr sysclk pci_par pci_ frame pci_ad addr pci_ irdy pci_ devsel pci_c/be data byte enables byte enables pci_ trdy pci_ perr pci_ serr cmd data addr cmd 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 16-74 freescale semiconductor abort error] does not clear the received master abort bit in the pci bus status register. in these cases, both bits must be cleared before further error reporting can occur. table 16-52 shows the actions taken for each kind of error. table 16-52. pci mode error actions pci error type error detect register bit pci status register bit comment pci outbound read received serr at any phase rcvd serr ? no data transferred received parity error for data phase mstr perr detected parity error, master data parity error detected no data transferred master abort mstr abort received master abort no data transferred target abort trgt abort received target abort no data transferred memory space violation ormsv ? no data transferred. only 8 bytes are requested in pci bus. pci outbound write received serr related to address phase rcvd serr ? may float ad bus to avoid contention received serr related to data phase rcvd serr ? received perr (data phase) mstr perr master data parity error master abort mstr abort received master abort target abort trgt abort received target abort memory space violation owmsv ? only 8 bytes transferred. pci inbound read detected parity error for address phase addr parity error detected parity error, signaled system error float ad bus detected parity error on upper address bus for address phase (sac or dac) ? ? no par64 check during address phase received serr at any phase received serr ? received perr (data phase) target perr ? internal error target abort signaled target abort 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 16-75 16.5 initialization/application information this section describes some tips for use of the pci controllers. 16.5.1 power-on reset configuration modes the pci1 interface can power-on in three modes: host mode, agent mode and agent configuration lock mode. certain bits in the configurat ion registers are set differently acc ording to the por (power-on reset) mode. also, certain configuration bi ts have different implications wh en compared with past freescale parts and pci implementations. note that after reset, the device cannot be switched from one mode to another. also note that the pci2 interface only supports host mode. the affected configuration bits are defined in table 16-53 pci inbound write detected parity error for address phase addr parity error detected parity error, signaled system error cache line purged detected parity error on upper address bus for address phase (sac or dac) ? ? no par64 check during address phase received serr at any phase rcvd serr ? detected parity error for data phase trgt perr detected parity error cache line purged table 16-53. affected configuration register bits for por register (offset) bit name register description pci command register (0x04) 2bus master controls whether the device can master a transa ction on the pci bus. if cleared, the device can not master a transaction. this bit is independent of host or agent mode. 1 memory space controls the acknowledgement of inbound memory transactions. if cleared, all inbound memory accesses (including accesses to pcsrbar space) end in a master abort. this bit is independent of host or agent mode. pci bus function register (0x44) 5 acl valid only in agent mode. controls acknowledgement of inbound configuration accesses. if set, all inbound configuration accesses are re tried. if cleared, inbound configuration accesses are acknowledged. in host mode all inbound configuration accesses end in master aborts. 0 pah determines whether the device is in age nt or host mode. zero indicates host mode. table 16-52. pci mode error actions (continued) pci error type error detect register bit pci status register bit comment 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 16-76 freescale semiconductor the por reset values for the affected configuration bits are described in table 16-54 . 16.5.1.1 host mode when the device powers up in host mode, all inbound conf iguration accesses are ignored (and thus master aborted). the acl bit is a do not care. the device powers up with the ab ility to master transactions on the pci bus, however in order to acknowledge memory tr ansactions, the memory space bit must be set. 16.5.1.2 agent mode when the device powers up in agen t mode, it acknowledges inbound configuration accesses. however the device cannot master transactions or acknowledge inbound memory accesses on the pci bus until the appropriate configuration bits (bus master and memory space, respectively) have been set. 16.5.1.3 agent config uration lock mode agent configuration lock mode is similar to agent m ode with the added restriction that when the device powers up in agent configuration lock mode, it retries all inbound conf iguration accesses until the acl bit is cleared. the purpose of this mode is to allow in itial configuration on the port by the local processor before opening the port to be further configured by the external host. as in agent mode, the device in agent configuration lock mode cannot ma ster transactions or acknowledge inbound memory accesses on the pci bus until the appropriate configurat ion bits (bus master and memory space, respectively) have been set. 16.5.2 extended 64-bit pc i1 signal connections the device can be configured as one pci-64 interfac e or two independent pci- 32 interfaces at power-on reset. see section 16.1.3.2, ?pci-64 or two pc i-32 interface configuration for more details. table 16-54. power-on reset values for affected configuration bits mode configuration bit bus master memory space acl pah host pci1: 1, pci2: 1 pci1: 0, pci2: 0 pci1: x, pci2: 0 pci1: 0, pci2: 0 agent pci1: 0, pci2: 0 pci1: 0, pci2: 0 pci1: 0, pci2: 0 pci1: 1, pci2: 0 agent configuration lock pci1: 0, pci2: 0 pci1: 0, pci2: 0 pci1: 1, pci2: 0 pci1: 1, pci2: 0 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 16-77 when this device is confi gured as one pci-64 interfac e, pci2 pins are used fo r the extended 64-bit pci1 signals. table 16-55 shows the extended 64-bit pci1 signa l connections using the pci2 pins. table 16-55. extended 64-bit pci1 signal connections pci1 pin names pci2 pin names pci1_ad[63:32] pci2_ad[31:0] pci1_c/be [7:4] pci2_c/be [3:0] pci1_req64 pci2_frame pci1_ack64 pci2_devsel pci1_par64 pci2_par 4 datasheet u .com
pci bus interface MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 16-78 freescale semiconductor 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 17-1 chapter 17 security engine (sec) 2.0 this chapter describes the functionality of the mp c8555e integrated security engine (sec 2.0). it addresses the following topics: ? section 17.1, ?architecture overview? ? section 17.2, ?configuration of internal memory space? ? section 17.3, ?descriptor overview? ? section 17.4, ?execution units? ? section 17.5, ?crypto-channels? ? section 17.6, ?sec controller? ? section 17.7, ?bus interface? ? section 17.8, ?power-saving mode? the sec 2.0 is designed to offload co mputationally intensive security functions, su ch as key generation and exchange, authentication, and bulk encryption, from the processo r core of the MPC8555E. it is optimized to process all algorithms associated with ipsec, ike, ssl/tls, iscsi, srtp, and ieee 802.11i standard. the sec 2.0 is derived from integrated security cores found in other members of the powerquicc family, including sec 1.0, th e version implemented in the mpc8272. the security engine?s executi on units (eus) and primary feat ures include the following: ? pkeu?public key execution uni t that supports the following: ? rsa and diffie-hellman ? programmable field size up to 2048 bits ? elliptic curve cryptography ?f 2 m and f(p) modes ? programmable field size up to 511 bits ? deu?data encryption standard execution unit ? des, 3des ? two key (k1, k2, k1) or three key (k1, k2, k3) ? ecb and cbc modes for both des and 3des ? aesu?advanced encryption standard execution unit ? implements the rijndael symmetric-key cipher ? ecb, cbc, ccm, and counter modes ? 128-, 192-, 256-bit key lengths 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 17-2 freescale semiconductor ? afeu?arc four execution unit ? implements a stream cipher comp atible with the rc4 algorithm ? 40- to 128-bit programmable key ? mdeu?message digest execution unit ? sha with 160- or 256-bit message digest ? md5 with 128-bit message digest ? hmac with either algorithm ? rng?random number generator ? master/slave logic, with dma ? 32-bit address/64-bit data ? up to 166-mhz operation ? dma blocks can be on any byte boundary ? four channels, each supporting a queue of commands (descriptor pointers) ? dynamic assignment of crypto execution units through an integrated controller ? 256-byte buffer fifos on data input and output paths of each execut ion unit, with flow control for large data sizes ? scatter/gather capability ? gather capability enables the sec 2.0 to concat enate multiple segments of memory when reading input data ? similarly, scatter capability enables sec 2.0 to write to multiple segments of memory when writing output data 17.1 architecture overview the sec 2.0 (henceforth referred to as sec) can act as a mast er on the internal bus. this allows the sec to alleviate the data movement bottl eneck normally associated with slav e-only cores. the host processor accesses the sec through its device drivers, using syst em memory for data storage. the sec resides in the peripheral memory map of the processor; ther efore, when an applica tion requires cryptographic functions, it simply creates descriptors for the sec th at define the cryptographic function to be performed and the location of the data. the sec?s bus-mastering capability permits the host processor to set up a crypto-channel with a few short regi ster writes, leaving the sec to pe rform reads and writes on system memory to complete the required task. figure 17-1 shows that the sec communi cates with other modules through the internal bus. 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 17-3 figure 17-1. sec connected to MPC8555E internal bus a block diagram of the sec inte rnal architecture is shown in figure 17-2 . the bus interface module is designed to transfer 64-bit words between the bus and any register inside the sec. figure 17-2. sec functional modules an operation begins when the host writes a descriptor pointer to the fetch fifo in one of the four sec channels. from this point on, the channel directs the sequence of operations. the channel uses the descriptor pointer to read the descriptor, then decodes the first wo rd of the descriptor to determine the operation to be performed and the crypto-execution units needed to perform it. the channel requests the controller to assign the needed cryp to-execution units. next the channel requests that the controller fetch the keys, initialization vector s (ivs), and data from locations specif ied in the rest of the descriptor. the controller satisfies the requests by making requests to the master inte rface per the programmable priority scheme. data is fed into the execu tion units through their registers and input fifos. the execution units read from their input fi fos and write processed data to their output fifos. the channel requests the controller to write data from the output fifos and registers back to system memory through the master/slave interface. e500 core e500 security engine (sec) coherency module communications processor module (cpm) ddr memory controller tsec tsec fifo crypto- channel crypto- channel crypto- channel crypto- channel bus control pkeu deu fifo fifo fifo fifo afeu interface aesu fifo fifo fifo rng mdeu execution units (eus) 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 17-4 freescale semiconductor for most packets, the entire payload is too long to fi t in an execution unit?s input or output fifo. the sec then uses a flow control scheme for reading and writ ing data. the channel direct s the controller to read bursts of input as necessary to keep refilling the input fifo, until the entire payload has been fetched. similarly, the channel directs the controller to write bur sts of output whenever enough accumulates in the execution unit?s output fifo. 17.1.1 data packet descriptors as a crypto-acceleration block, the se c controller has been designed for easy use and integration with existing systems and software. all cr yptographic functions are accessible through descri ptors. a descriptor specifies a cryptographic func tion to be performed and co ntains pointers to all ne cessary input data and to the places where output data is to be written. some descriptor types perf orm multiple functions to facilitate particular protocols. a data pack et descriptor is diagrammed in table 17-1 . each descriptor contains eight long-words ( 64 bits each), consisting of the following: ? one long-word of header?the h eader describes the required se rvices and encodes information indicating which eus to use and whic h modes to set. it also indicate s if notification should be sent to the host when the descriptor operation is complete. ? seven long-words containing pointers and lengt hs used to locate input or output data. upon completion of the current descript or, the channel checks the next entry in its fetch fifo , and, if it is nonzero, the channel is instructed to request a burst read of th e next descriptor. processing of the next descriptor (and whether or not a done signal is generated) is determined by the programming of the crypto-channel? s configuration register. two modes of operation are supported: ? signal done at end of every descriptor ? signal done at end of a selected descriptor table 17-1. example data packet descriptor field name value/type description dpd_des_ctx_crypt tbd representative header for des using context to encrypt len_ctxin ptr_ctxin length pointer number of bytes to be written pointer to context (iv) to be written into des engine len_key ptr_key length pointer number of bytes in key pointer to block cipher key len_datain ptr_datain length pointer number of bytes of data to be ciphered pointer to data to perform cipher upon len_dataout ptr_dataout length pointer number of bytes of data after ciphering pointer to location where cipher output is to be written len_ctxout ptr_ctxout length pointer length of output context (iv) pointer to location where alte red context is to be written null length null pointer length pointer zeros for fixed length descriptor filter zeros for fixed length descriptor filter null length null pointer length pointer zeros for fixed length descriptor filter zeros for fixed length descriptor filter 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 17-5 the crypto-channel can signal done thr ough an interrupt or by a write-back of the descriptor header after processing a data packet descriptor. the value written back is identical to that of the header, with the exception that a done field is set. occasionally, a descriptor fi eld may not be applicable to the requested service. for example, if using des in ecb mode, the contents of the iv field do not aff ect the result of the des computation. therefore, when processing data packet descriptors, the crypto-channel skips any pointer that has an associated length of zero. for more information, refer to section 17.1.1, ?data packet descriptors.? 17.1.2 execution units (eus) execution unit (eu) is the generic te rm for a functional block that perfor ms the mathematical permutations required by protocols used in cryptographic proces sing. the eus are compatible with ipsec, ike, ssl/tls, iscsi, srtp, and 802.11i standard processi ng, and can work together to perform high-level cryptographic tasks. the sec?s execution units are as follows: ? pkeu?for computing asymmetric-key operati ons, including modular ex ponentiation (and other modular arithmetic functions ) or ecc point arithmetic ? deu?for performing block cipher, symmet ric-key cryptography using des and 3des ? afeu?for performing rc4 compatible st ream cipher symmet ric-key cryptography ? aesu?for performing the advanced encryption standard algorithm ? mdeu?for performing security hash ing using md-5, sha-1, or sha-256 ? rng?for random number generation each eu is described in detail in section 17.4, ?execution units.? 17.1.2.1 public key execution unit (pkeu) the pkeu is capable of performing many advanced mathematical functions to support both rsa and ecc public key cryptogr aphic algorithms. ecc is supported in both f 2 m (polynomial-basis) and f(p) modes. this eu supports all levels of functions to assist the host microproce ssor to perform its desired cryptographic task. for example, at the highest level, the accelerator performs m odular exponentiations to support rsa and performs point mul tiplies to support ecc. at the lo wer levels, the pkeu can perform simple operations such as modular multiplies. for mo re information, refer to section 17.4.1, ?public key execution unit (pkeu).? 17.1.2.1.1 elliptic curve operations the pkeu has its own data and control units, in cluding a general-purpose register file in the programmable-size arit hmetic unit. the field or modulus size can be programmed to any value between 160 and 512 bits in increments of 8, with each value i supporting all actual fi eld sizes from 8 i ? 7 to 8 i . the result is hardware supporting a wi de range of cryptographi c security. larger field/modulus sizes result in greater security but lower performance; processi ng time is determined by field or modulus size. for example, a field size of 160 is roughl y equivalent to the security pr ovided by 1024 bit rsa. a field size set to 208 roughly equates to 2048 bits of rsa security. 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 17-6 freescale semiconductor the pkeu contains routines implementing the atom ic functions for ellipt ic curve processing?point arithmetic and finite fiel d arithmetic. the point ope rations (multiplication, a ddition, and doubling) involve one or more finite field operations, which ar e addition, multiplication, invers e, and squaring. point add and double each use all four finite field operations. similarly , point multiplication uses all ec point operations as well as the finite field operations. all thes e functions are supported both in modular arithmetic and polynomial basis finite fields. 17.1.2.1.2 modular expo nentiation operations the pkeu is also capable of perfor ming ordinary integer modul o arithmetic. this arithm etic is an integral part of the rsa public key algorithm ; however, it can also play a role in the generatio n of ecc digital signatures and diffie-hellman key exchanges. modular arithmetic functi ons supported by the sec?s pkeu include the following: ? r 2 mod n ?a e mod n ?(a b) r ?1 mod n ?(a b) r ?2 mod n ? (a + b) mod n ? (a ? b) mod n where the following variable definitions: a = ar mod n, n is the modulus vector, a and b are input vectors, e is the exponent vector, r is 2 s , where s is the bit length of the n vector rounded up to the nearest multiple of 32. the pkeu can perform modular arit hmetic on operands up to 2048 bits in length. the modulus must be larger than or equal to 105 bits. the pkeu uses the montgomery modular mul tiplication algorithm to perform core functions. the addition and subtraction functions exist to help support known methods of the chinese remainder theorem (crt) for efficient exponentiation. 17.1.2.2 data encryption standard execution unit (deu) the des execution unit (deu) performs bulk data en cryption/decryption, in compliance with the data encryption standard algorithm (ans i x3.92). the deu can also compute 3des, an extension of the des algorithm in which each 64-bit input block is processed three times. the sec supports 2-key (k1 = k3) or 3-key 3des. the deu operates by permuting 64-bit da ta blocks with a shared 56-bit key and an initialization vector (iv). the sec supports two modes of operation: el ectronic code book (ecb) a nd cipher clock chaining (cbc). for more information, refer to section 17.4.2, ?data encryption sta ndard execution unit (deu).? 17.1.2.3 arc four exec ution unit (afeu) the afeu accelerates a bulk encrypt ion algorithm compatible with the rc4 stream cipher from rsa security, inc. the algorithm is byte-oriented, meani ng a byte of plain text is encrypted with a key to 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 17-7 produce a byte of ciphertext. the ke y is variable length and the afeu supports key lengths from 8 to 128 bits (in byte increments), providing a wide range of security strengths . arc4 is a symmetric algorithm, meaning each of the two communicati ng parties share the same key. for more information, refer to section 17.4.3, ?arc four execution unit (afeu).? 17.1.2.4 advanced encryption standard execution unit (aesu) the aesu is used to accelerate bulk data encrypt ion/decryption in compliance with the advanced encryption standard (rijndael) algor ithm. the aesu executes on 128-bit blocks with a choice of key sizes: 128, 192, or 256 bits. aesa is a symmetric-key algorithm; the sender and receiver use the same key for both encryption and decryption. the session key and iv ar e supplied to the aesu module pr ior to encryption. the processor supplies data to the module that is processed as a 128-bit input. th e aesu operates in ecb, cbc, ctr, and ccm modes. for more information, refer to section 17.4.6, ?advanced encryption st andard execution unit (aesu).? 17.1.2.5 message digest execution unit (mdeu) the mdeu computes a single message digest (or hash or integrity check) value of all the data presented on the input bus, using either th e md5, sha-1 or sha-256 algorithms for bulk data hashing. with any hash algorithm, the larger message is mapped onto a smaller output space; th erefore, collisions are possible, albeit not probable. the 160-bit hash value is a sufficiently large space that collisions are extremely rare. the security of the hash function is ba sed on the difficulty of lo cating collisions. that is, it is computationally infeasible to construct two distinct but similar messages that produce the same hash output. ? the md5 generates a 128-bit hash; th e algorithm is specified in rfc 1321. ? sha-1 is a 160-bit hash function, specified by the ansi x9.30-2 and fips 180-1 standards. ? sha-256 is a 256-bit hash function that provides 256 bits of security against collision attacks. ? the mdeu also supports hmac com putations, as specified in rfc 2104. for more information, refer to section 17.4.4, ?message digest execution unit (mdeu).? 17.1.2.6 random number generator (rng) the rng is a digital integrated ci rcuit capable of generating 64-bit random numbers. it is designed to comply with fips 140-1 standards fo r randomness and non-determinism. because many cryptographic algorithm s use random numbers as a source fo r generating a se cret value (a nonce), it is desirable to have a private rng for use by the sec. the anonymity of each random number must be maintained, as well as the unpredictabili ty of the next random number. the fips-140 common criteria compliant private rng allows the system to develop random challenges or random secret keys. the secret key can thus remain hidden from even the high-level a pplication code, providing an added measure of physical security. for more information, refer to section 17.4.5, ?random numb er generator (rng).? 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 17-8 freescale semiconductor 17.1.3 crypto-channels the sec includes four crypto-channels that manage data and eu functi on. each channel consists of the following: ? a fetch fifo, which holds a queue of point ers to descriptors waiting to be serviced ? a configuration register, which allows the us er a number of options for sec event signaling. ? control registers containing informati on about the transaction in process ? a status register containing an indica tion of the last unfulfilled bus request ? a descriptor buffer memory used to store the active descriptor whenever a channel is idle and its fetch fifo is non- empty, the channel reads th e next descriptor pointer from the fetch fifo. using this point er, the channel fetches th e descriptor and places it in its descriptor buffer. to service this descriptor, the chan nel directs execution of the following steps: 1. analyze the descriptor header to determine the cryptographic serv ices required and request use of the appropriate eu(s) from the controller. 2. wait for the controller to grant access to the required eu(s). 3. set the appropriate mode bits in the eu(s) for the required service. 4. fetch data parcels using pointers from the descriptor buf fer, and place them in either an eu input fifo or eu registers (as appropriate ). the term data parcel refers here to any input or output of a cryptographic process, such as a key, hash result, input cont ext, output context, or text-data. context refers to either an iv or other internal eu state that can be read out or loaded in. ?text-data? refers to plaintext or ciphertext to be operated on. 5. if the data size is greater than eu fifo size, conti nue fetching input data, and writing output data to memory. 6. wait for eu(s) to complete processing. 7. upon completion, unload results from output fifo s and context registers and write them to external memory using pointers in the descriptor buffer. 8. if multiple services are requested, go back to step 3. 9. release the eus. (note that in previous freescale securi ty co-processors, it was possible to reserve an eu for use on multiple descriptors. with the added capabilities in sec2.0, such static assignments are no longer necessary and are not supported. eus are alwa ys released at the completion of a descriptor.) 10. if done notification is enabled in the de scriptor header, perform this notification. the channel can generate two types of done notif ication signals when it completes operation on a descriptor. it can signal done through an interrupt or by a writeback of the descriptor header after processing a descriptor. the va lue written back is identical to that of the header, with the exception that a done field is set. many security protocols involve both encryption and hashing of packet payloads. to accomplish this without requiring two passes through the data, channels can configure data flows through more than one eu. in such cases, one eu is de signated the primary eu, and the othe r as the secondary eu. the primary eu receives its data from memory through the cont roller, and the secondary eu receives its data by snooping the sec buses. 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 17-9 there are two types of snooping. ? input data can be fed to the primary eu and the same input data snooped by the secondary eu. this is called in-snooping. ? output data from the primary eu can be snoope d by the secondary eu. this is called out-snooping. in the sec, the secondary eu is always the mdeu. for more information, refer to section 17.5, ?crypto-channels.? 17.1.4 sec controller the sec controller manages on-chip resources, includi ng the individual execution units (eus), fifos, the master/slave interface, and the inte rnal buses that connect all the vari ous modules. the cont roller receives service requests from the master/sla ve interface and various crypto-ch annels, and schedules the required activities. the controller ca n configure each of the on-ch ip resources in two modes: ? host-controlled access?the host is directly responsible for all data movement into and out of the resource. this mode is typically only used in debug. ? dynamic eu access?a crypto-channel can reques t a particular service from any available execution unit. 17.1.4.1 host-controlled access all execution units (eu) can be used entirely through register read/write access. the sec operates as a slave, and the host must target write the informati on typically provided through the descriptor into the appropriate registers and fifos of th e sec. this mode is more cpu in tensive, and requires a great deal of familiarity with the sec registers. it is recomm ended that host-controlled access be used only for operations using a single eu, and for debug purposes. 17.1.4.2 dynamic eu access processing begins when a data packet descriptor po inter is written to the fetch fifo of one of the crypto-channels. prior to fetching the data referred to by the descriptor and based on the services requested by the descriptor header in the desc riptor buffer, the controller dynamically reserves usage of an eu to the crypto-channel. if all appropriate eus are already dynamically rese rved by other crypto-channels, the crypto-channel stalls and waits to fetch data until an appropriate eu is available. if multiple crypto-channels simultane ously request the same eu, the eu is assigned on a we ighted priority or round-robin basis. once the required eu has been reserved, the crypto-channel fetches and loads the appropriate data packets, operates the eu, unloads data to system memory, and releases the eu for use by another crypto-channel. for more information, refer to section 17.6, ?sec controller.? 17.1.5 bus interface the master/slave interface manages communication be tween the sec?s internal execution units and the MPC8555E internal bus. all on-chi p resources are memory mapped, and the slave accesses to the sec 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 17-10 freescale semiconductor may be addressed on byte boundaries. the sec performs init iator reads on byte boundari es and internally adjusts the data to place on word boundaries as appropriate. access to sy stem memory is a critical factor in performance, and the 64-bit master/slave interf ace of the sec allows it to achieve performance unattainable on secondary buses. for more information, refer to section 17.7, ?bus interface.? 17.2 configuration of internal memory space table 17-2 shows the base address map, while table 17-3 provides the address ma p, including all registers in the execution units. the 18-bit sec address bus va lue is shown. these address values are offsets from ccsrbar. refer to section 2.3, ?configuration, contro l, and status register map,? for more information. note that these tables show modulo- 8 addresses; the three le ast significant address bits that are used to select bytes within 64-bit-words are not shown. table 17-3 shows the system address map showing all functional register s. undefined 4-byte address spaces within offset 0x000?0xfff are reserved. table 17-2. sec base address map offset (ad 17?0) module description type reference 0x3_0000?0x3_0fff ? reserved ? ? 0x3_1000?0x3_10ff controller arbiter/contro ller control register space resource control 17.6/17-92 0x3_1100?0x3_11ff channel_1 crypto-channel 1 data control 17.5/17-80 0x3_1200?0x3_12ff channel_2 crypto-channel 2 0x3_1300?0x3_13ff channel_3 crypto-channel 3 0x3_1400?0x3_14ff channel_4 crypto-channel 4 0x3_2000?0x3_2fff deu des/3des execution unit crypto eu 17.4.2/17-33 0x3_4000?0x3_4fff aesu aes execution unit 17.4.6/17-67 0x3_6000?0x3_6fff mdeu message digest execution unit 17.4.4/17-51 0x3_8000?0x3_8fff afeu arc four execution unit 17.4.3/17-42 0x3_a000?0x3_afff rng random number generator 17.4.5/17-61 0x3_c000?0x3_cfff pkeu public key execution unit 17.4.1/17-24 table 17-3. sec address map offset register acce ss reset section/page controller registers 0x3_1008 imr?interrupt mask register r/w 0x0000_0000_0000_0000 17.6.2.1/17-93 0x3_1010 isr?interrupt status register r 0x0000_0000_0000_0000 17.6.2.2/17-94 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 17-11 0x3_1018 icr?interrupt clear register w 0x0000_0000_0000_0000 17.6.2.3/17-95 0x3_1020 id?identification register r 0x0000_0000_0000_0040 17.6.2.4/17-97 0x3_1028 euasr?eu assignment status register r 0xf0f0_f0f0_00ff_f0f0 17.6.2/17-92 0x3_1030 mcr?master control register r/w 0000_0000_0000_0000 17.6.2.5/17-98 channel 1 0x3_1108 cccr1?crypto-channel 1 configuration register r/w 0x0000_0000_0000_0000 17.5.1.1/17-81 0x3_1110 ccpsr1?crypto-channel 1 pointer status register r 0x0000_0000_0000_0007 17.5.1.2/17-83 0x3_1140 cdpr1?crypto-channel 1 current descriptor pointer register r 0x0000_0000_0000_0000 17.5.1.3/17-89 0x3_1148 ff1?crypto-channel 1 fetch fi fo address register w 0x0000_0000_0000_0000 17.5.1.4/17-90 0x3_1180? 0x3_11bf dbn?crypto-channel 1descriptor buffers[0-7] r 0x0000_0000_0000_0000 17.5.1.5/17-90 channel 2 0x3_1208 cccr2?crypto-channel 2 configuration register r/w 0x0000_0000_0000_0000 17.5.1.1/17-81 0x3_1210 ccpsr2?crypto-channel 2 pointer status register r 0x0000_0000_0000_0007 17.5.1.2/17-83 0x3_1240 cdpr2?crypto-channel 2 current descriptor pointer register r 0x0000_0000_0000_0000 17.5.1.3/17-89 0x3_1248 ff2?crypto-channel 2 fetch fi fo address register w 0x0000_0000_0000_0000 17.5.1.4/17-90 0x3_1280? 0x3_12bf dbn?crypto-channel 2 descriptor buffers[0-7] r 0x0000_0000_0000_0000 17.5.1.5/17-90 channel 3 0x3_1308 cccr3?crypto-channel 3 configuration register r/w 0x0000_0000_0000_0000 17.5.1.1/17-81 0x3_1310 ccpsr3?crypto-channel 3 pointer status register r 0x0000_0000_0000_0007 17.5.1.2/17-83 0x3_1340 cdpr3?crypto-channel 3 current descriptor pointer register r 0x0000_0000_0000_0000 17.5.1.3/17-89 0x3_1348 ff3?crypto-channel 3 fetch fi fo address register w 0x0000_0000_0000_0000 17.5.1.4/17-90 0x3_1380? 0x3_13bf dbn?crypto-channel 3 descriptor buffers[0-7] r 0x0000_0000_0000_0000 17.5.1.5/17-90 channel 4 0x3_1408 cccr4?crypto-channel 4 configuration register r/w 0x0000_0000_0000_0000 17.5.1.1/17-81 0x3_1410 ccpsr4?crypto-channel 4 pointer status register r 0x0000_0000_0000_0007 17.5.1.2/17-83 0x3_1440 cdpr4?crypto-channel 4 current descriptor pointer register r 0x0000_0000_0000_0000 17.5.1.3/17-89 0x3_1448 ff4?crypto-channel 4 fetch fi fo address register w 0x0000_0000_0000_0000 17.5.1.4/17-90 0x3_1480? 0x3_14bf dbn?crypto-channel 4 descriptor buffers[0-7] r 0x0000_0000_0000_0000 17.5.1.5/17-90 data encryption standard execution unit (deu) 0x3_2000 deumr?deu mode register r/w 0x0000_0000_0000_0000 17.4.2.1/17-33 table 17-3. sec address map (continued) offset register acce ss reset section/page 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 17-12 freescale semiconductor 0x3_2008 deuksr?deu key size register r/w 0x0000_0000_0000_0000 17.4.2.2/17-34 0x3_2010 deudsr?deu data size register r/w 0x0000_0000_0000_0000 17.4.2.3/17-35 0x3_2018 deurcr?deu reset control register r/w 0x0000_0000_0000_0000 17.4.2.4/17-36 0x3_2028 deusr?deu status register r 0x0000_0000_0000_0000 17.4.2.5/17-37 0x3_2030 deuisr?deu interrupt status register r 0x0000_0000_0000_0000 17.4.2.6/17-38 0x3_2038 deuicr?deu interrupt control register r/w 0x0000_0000_0000_3000 17.4.2.7/17-39 0x3_2050 deueug?deu eu-go register w 0x0000_0000_0000_0000 17.4.2.8/17-41 0x3_2100 deuiv?deu initialization ve ctor register r/w 0x0000_0000_0000_0000 17.4.2.9/17-41 0x3_2400 deuk1?deu key register 1 w ? 17.4.2.10/17-41 0x3_2408 deuk2?deu key register 2 w ? 17.4.2.10/17-41 0x3_2410 deuk3?deu key register 3 w ? 17.4.2.10/17-41 0x3_2800? 0x3_2fff deu fifo r/w 0x0000_0000_0000_0000 17.4.2.11/17-42 advanced encryption standa rd execution unit (aesu) 0x3_4000 aesumr?aesu mode register r/w 0x0000_0000_0000_0000 17.4.6.1/17-67 0x3_4008 aesuksr?aesu key size register r/w 0x0000_0000_0000_0000 17.4.6.2/17-69 0x3_4010 aesudsr?aesu data size register r/w 0x0000_0000_0000_0000 17.4.6.3/17-70 0x3_4018 aesurcr?aesu reset control register r/w 0x0000_0000_0000_0000 17.4.6.4/17-70 0x3_4028 aesusr?aesu status register r 0x0000_0000_0000_0000 17.4.6.5/17-71 0x3_4030 aesuisr?aesu interrupt status register r 0x0000_0000_0000_0000 17.4.6.6/17-72 0x3_4038 aesuicr?aesu interrupt control register r/w 0x0000_0000_0000_1000 17.4.6.7/17-73 0x3_4050 aesuemr?aesu end of message register w 0x0000_0000_0000_0000 17.4.6.8/17-75 0x3_4100 aesu context memory registers r/w 0x0000_0000_0000_0000 17.4.6.9/17-75 0x3_4400? 0x3_4408 aesu key memory r/w 0x0000_0000_0000_0000 17.4.6.9.5/17-79 0x3_4800? 0x3_4fff aesu fifo r/w 0x0000_0000_0000_0000 17.4.6.9.6/17-80 message digest execution unit (mdeu) 0x3_6000 mdeumr?mdeu mode register r/w 0x0000_0000_0000_0000 17.4.4.1/17-51 0x3_6008 mdeuksr?mdeu key size register r/w 0x0000_0000_0000_0000 17.4.4.3/17-53 0x3_6010 mdeudsr?mdeu data size register r/w 0x0000_0000_0000_0000 17.4.4.4/17-54 0x3_6018 mdeurcr?mdeu reset control register r/w 0x0000_0000_0000_0000 17.4.4.5/17-54 0x3_6028 mdeusr?mdeu status register r 0x0000_0000_0000_0000 17.4.4.6/17-55 0x3_6030 mdeuisr?mdeu interrupt status register r 0x0000_0000_0000_0000 17.4.4.7/17-56 0x3_6038 mdeuicr?mdeu interrupt co ntrol register r/w 0x0000_0000_0000_1000 17.4.4.8/17-57 0x3_6050 mdeueug?mdeu eu-go register w 0x0000_0000_0000_0000 17.4.4.9/17-58 table 17-3. sec address map (continued) offset register acce ss reset section/page 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 17-13 0x3_6100? 0x3_6120 mdeu context memory registers r/w 0x0000_0000_0000_0000 17.4.4.10/17-59 0x3_6400? 0x3_647f mdeu key memory w 0x0000_0000_0000_0000 17.4.4.11/17-60 0x3_6800? 0x3_6fff mdeu fifo w 0x0000_0000_0000_0000 17.4.4.12/17-60 arc four execution unit (afeu) 0x3_8000 afeumr?afeu mode register r/w 0x0000_0000_0000_0000 17.4.3.1/17-42 0x3_8008 afeuksr?afeu key size register r/w 0x0000_0000_0000_0000 17.4.3.3/17-43 0x3_8010 afeudsr?afeu data size register r/w 0x0000_0000_0000_0000 17.4.3.4/17-44 0x3_8018 afeurcr?afeu reset control register r/w 0x0000_0000_0000_0000 17.4.3.5/17-45 0x3_8028 afeusr?afeu status register r 0x0000_0000_0000_0000 17.4.3.6/17-46 0x3_8030 afeuisr?afeu interrupt status register r 0x0000_0000_0000_0000 17.4.3.7/17-47 0x3_8038 afeuicr?afeu interrupt co ntrol register r/w 0x0000_0000_0000_1000 17.4.3.8/17-48 0x3_8050 afeuemr?afeu end of message register w 0x0000_0000_0000_0000 17.4.3.9/17-50 0x3_8100? 0x3_81ff afeu context memory registers r/w 0x0000_0000_0000_0000 17.4.3.10.1/17-5 0 0x3_8200 afeu context memory pointers r/w 0x0000_0000_0000_0000 17.4.3.10.2/17-5 1 0x3_8400 afeuk0?afeu key register 0 w ? 17.4.3.11/17-51 0x3_8408 afeuk1?afeu key register 1 w ? 17.4.3.11/17-51 0x3_8800? 0x3_8fff afeu fifo r/w 0x0000_0000_0000_0000 17.4.3.11.1/17-5 1 random number generator (rng) 0x3_a000 rngmr?rng mode register r/w 0x0000_0000_0000_0000 17.4.5.1/17-61 0x3_a010 rngdsr?rng data size register r/w 0x0000_0000_0000_0000 17.4.5.2/17-62 0x3_a018 rngrcr?rng reset contro l register r/w 0x0000_0000_0000_0000 17.4.5.3/17-63 0x3_a028 rngsr?rng status register r 0x0000_0000_0000_0000 17.4.5.4/17-63 0x3_a030 rngisr?rng interrupt st atus register r 0x0000_0000_0000_0000 17.4.5.5/17-64 0x3_a038 rngicr?rng interrupt control register r/w 0x0000_0000_0000_1000 17.4.5.6/17-65 0x3_a050 rngeug?rng eu-go register w 0x0000_0000_0000_0000 17.4.5.7/17-66 0x3_a800? 0x3_afff rng fifo r 0x0000_0000_0000_0000 17.4.5.8/17-66 public key execution unit (pkeu) 0x3_c000 pkeumr?pkeu mode register r/w 0x0000_0000_0000_0000 17.4.1.1/17-25 0x3_c008 pkeuksr?pkeu key size register r/w 0x0000_0000_0000_0000 17.4.1.2/17-26 0x3_c010 pkeudsr?pkeu data size register r/w 0x0000_0000_0000_0000 17.4.1.3/17-26 table 17-3. sec address map (continued) offset register acce ss reset section/page 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 17-14 freescale semiconductor 17.3 descriptor overview the host processor maintains a record of current secure sessions and the corresponding keys and contexts of those sessions. after the host has determined that a security opera tion is required, it cr eates a descriptor containing all the information the sec needs to pe rform the security operation. the host creates the descriptor in main memory, then writes a pointer to the descriptor into the fetc h fifo of one of the sec channels. the channel uses th is pointer to read the descriptor into it s descriptor buffer. after it obtains the descriptor, the sec uses its bus ma stering capability to obtain inputs a nd write results, thus off-loading data movement and encryption ope rations from the host processor. for test purposes, it is also possible for the host to wr ite keys, context, and text-data directly to the sec, using sec?s host-controlled mode. this method avoids use of descriptors. 0x3_c018 pkeurcr?pkeu reset control register r/w 0x0000_0000_0000_0000 17.4.1.5/17-28 0x3_c028 pkeusr?pkeu status register r 0x0000_0000_0000_0000 17.4.1.6/17-29 0x3_c030 pkeuisr?pkeu interrupt status register r 0x0000_0000_0000_0000 17.4.1.7/17-30 0x3_c038 pkeuicr?pkeu interrupt control register r/w 0x0000_0000_0000_1000 17.4.1.8/17-31 0x3_c040 pkeuabs?pkeu ab size register r/w 0x0000_0000_0000_0000 17.4.1.3/17-26 0x3_c050 pkeueug?pkeu eu-go w 0x0000_0000_0000_0000 17.4.1.9/17-32 0x3_c200? 0x3_c23f pkeu parameter memory a0 r/w 0x0000_0000_0000_0000 17.4.1.10/17-32 0x3_c240? 0x3_c27f pkeu parameter memory a1 r/w 0x0000_0000_0000_0000 0x3_c280? 0x3_c2bf pkeu parameter memory a2 r/w 0x0000_0000_0000_0000 0x3_c2c0? 0x3_c2ff pkeu parameter memory a3 r/w 0x0000_0000_0000_0000 0x3_c300? 0x3_c33f pkeu parameter memory b0 r/w 0x0000_0000_0000_0000 0x3_c340? 0x3_c37f pkeu parameter memory b1 r/w 0x0000_0000_0000_0000 0x3_c380? 0x3_c3bf pkeu parameter memory b2 r/w 0x0000_0000_0000_0000 0x3_c3c0? 0x3_c3ff pkeu parameter memory b3 r/w 0x0000_0000_0000_0000 0x3_c400? 0x3_c4ff pkeu parameter memory e w 0x0000_0000_0000_0000 0x3_c800? 0x3_c8ff pkeu parameter memory n r/w 0x0000_0000_0000_0000 table 17-3. sec address map (continued) offset register acce ss reset section/page 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 17-15 17.3.1 descriptor structure sec descriptors are conceptually similar to descri ptors used by most devices with dma capability. the descriptors have a fixed le ngth of 64 bytes, that is, eight long word s, consisting of one header dword and seven pointer dwords. see figure 17-3 for the descriptor format. the header dword specifies the secu rity operation to be pe rformed, the execution uni t(s) needed, and the modes for each execution unit. the poi nter dwords, all of which have th e same format, contain pointer and length information for locating input or output data par cels (such as keys, context, or text-data). the large number of pointers provided in the descriptor allows for multi-algor ithm operations that require fetching of multiple keys, as well as fetch and return of contexts. any pointer dw ord that is not needed can be given a length of zero, and the channel will skip over the corresponding operations. sec descriptors include scatter/gath er capability, which means that eac h pointer in a descriptor can be either a direct pointer to a contiguous parcel of data, or can be a pointer to a ?link table? which is a list of pointers and lengths used to assemble the data parcel. when a link table is used to read input data, this is referred to as a gather operation; when used to write output data, it is referred to as a scatter operation. 17.3.2 descriptor format?header dword descriptors are created by the ho st to guide the sec through requi red cryptographic operations. the descriptor header defines the ope rations to be performed, the mode for each operation, and internal addressing used by the cont roller and channel for in ternal data movement. th e sec device drivers allow the host to create proper header s for each cryptographic operation. 015161723243132 63 header dword header reserved pointer dword 0 length0 j0 extent0 ? pointer0 pointer dword 1 length1 j1 extent1 ? pointer1 pointer dword 2 length2 j2 extent2 ? pointer2 pointer dword 3 length3 j3 extent3 ? pointer3 pointer dword 4 length4 j4 extent4 ? pointer4 pointer dword 5 length5 j5 extent5 ? pointer5 pointer dword 6 length6 j6 extent6 ? pointer6 figure 17-3. descriptor format 0 3 4 11121516 2324 28293031 field op_0 op_1 desc_type ? dir dn eu_sel0 mode0 eu_sel1 mode1 32 63 field ? figure 17-4. header dword 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 17-16 freescale semiconductor 17.3.2.1 selecting execution un its?eu_sel0 and eu_sel1 table 17-5 shows the values for eu_sel0 and eu_sel1 in the descriptor header. the following rules govern the choices for these fields: 1. eu_sel0 values of 0000 (no eu selected) or 0111?1111 (reserved) result in an unrecognized header error condition during proces sing of the descriptor header. 2. the only valid choices for eu_sel1 are 0000 ( no eu selected) or 0011 (mdeu). any other choice results in an unrecognized header error condition. 3. if eu_sel1 is 0011 (mdeu), then eu_sel0 must be 0010 (deu), 0110 (aesu), or 0001 (afeu). all other values of eu_sel0 result in an unrecognized header error condition. table 17-4. header dword bit definitions bits name description op_0: 0?3 eu_sel0 primary eu select. see section 17.3.2.1, ?selecting execution units?eu_sel0 and eu_sel1,? for possible values. 4?11 mode0 primary mode: mode data used to program the primary eu. the mode data is to the chosen eu. this field is passed directly to bits 56?63 of the mode register in the selected eu. op_1: 12?15 eu_sel1 secondary eu select. see section 17.3.2.1, ?selecting exec ution units?eu_sel0 and eu_sel1,? for possible values. 16?23 mode1 secondary mode: mode data used to program th e primary eu. the mode data is to the chosen eu. this field is passed directly to bits 56?63 of the mode register in the selected eu. 24?28 desc_type descriptor type. this field, along with the di r field, determines the sequence of actions to be performed by the channel and selected eus using the bloc ks of data listed in the rest of the descriptor. the attributes determined include the direction of data flow for each data block, which eu (primary or secondary) is accessed, what snooping options are used, and which internal eu addresses are accessed. see section 17.3.2.2, ?selecting descriptor type?desc_type,? for possible values. 29 ? reserved. 30 dir direction?direction of overall data flow 0 outbound 1 inbound this field, along with th e desc_type field, helps determine the s equence of actions to be performed by the channel and selected eus. 31 dn done notification 0 no done notification 1 signal done to the host on completion of this descriptor. the done notification can take the form of an interrupt, or a modified header writeback, or both, depending upon the states of the cdie (channel done interrupt enable) and cdwe (channel done writeback enable) bits in the channel configuration register. when writeback is used, the value written back is 0xff in bits 0?7 of this long word. 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 17-17 17.3.2.2 selecting descriptor type?desc_type table 17-6 shows the permissible values for the desc_typ e field in the descriptor header. descriptor types from the sec 1.0, which have zer o in the last bit (xxxx_0), are list ed first, follow ed by new sec 2.0 types, which have one in the last bit (xxxx_1). table 17-5. eu_sel1 and eu_sel2 values value (binary) selected eu 0000 no eu selected 0001 afeu 0010 deu 0011 mdeu 0100 rng 0101 pkeu 0110 aesu 0111?1110 reserved 1111 reserved for header writeback table 17-6. descriptor types value (binary) descriptor type notes 0000_0 aesu_ctr_nonsnoop aesu ctr nonsnooping 1 0001_0 common_nonsnoop_no_afeu common, nonsnooping, non-pkeu, non-afeu 1 0010_0 hmac_snoop_no_afeu snooping, hmac, non-afeu 2 0011_0 ? reserved 0100_0 ? reserved 0101_0 common_nonsnoop_afeu common, nonsnooping, afeu 0110_0 ? reserved 0000_0 aesu_ctr_nonsnoop aesu ctr nonsnooping 0001_0 common_nonsnoop common, nonsnooping, non-pkeu, non-afeu 0010_0 hmac_snoop_no_afeu snooping, hmac, non-afeu 0011_0 ? reserved 0100_0 ? reserved 0101_0 common_nonsnoop_afeu common, nonsnooping, afeu 0110_0 ? reserved 0111_0 ? reserved 1000_0 pkeu_mm pkeu-montgomery multiplication 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 17-18 freescale semiconductor 1 type 0000_0 is for aes-ctr operations. type 0001_0 also supports aes-ctr; however, to use aes-ctr with 0001_0, the user must prepend zeros to the aes ct x before loading the aes context registers. 2 type 1100_0 is for aes-ctr operati ons with hmac. type 0010_ 0 also supports aes-ctr with hmac; however, to use aes-ctr with 0010_0, the user must prepend zeros to the aes ctx before loading the aes context registers. for more information about descriptor type s and the data used for each type, see section 17.3.5, ?descriptor types.? 17.3.3 descriptor format?pointer dwords the descriptor contains seven pointer dwords that define where in memory the sec should access its input and output data parcels. th e channel determines how it will use ea ch of the pointer dwords based on the descriptor type and direction fields in the header. the channel accesses the first data parcel by starting at a location given by a pointer valu e, and accessing a number of byt es given by a length or extent value. subsequent data parcels may be accessed by staring where a pr evious data parcel ended, or by starting at a different pointer. the length or extent used with any pointer may be from the same pointer dword or from a diff erent pointer dword in the same descriptor. although the extent field exists in each pointer dword of the sec descriptor, current usage is limited to pointer dwords 4-6. 1001_0 ? reserved 1010_0 ? reserved 1011_0 ? reserved 1100_0 hmac_snoop_aesu_ctr aesu ctr hmac snooping 2 1101_0 ? reserved 1110_0 ? reserved 1111_0 ? reserved 0000_1 ipsec_esp ipsec esp mode encryption and hashing 0001_1 802.11i standard aes ccmp ccmp encryption and hashing, suitable for 802.11i standard 0010_1 srtp srtp encryption and hashing 0011_1 pkeu_assemble pkeu_assemble elliptic curve cryptography 0100_1 pkeu_ptmul pkeu_ptmul elliptic curve cryptography 0101_1 pkeu_ptadd_dbl pkeu_ptadd_dbl elliptic curve cryptography others ? reserved 0 151617 2324 3132 63 field length j extent ? pointer figure 17-5. pointer dword table 17-6. descriptor types (continued) value (binary) descriptor type notes 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 17-19 on occasion, a descriptor field may not be applicable to the requested service. with seven length/pointer pairs, it is possible that not all descriptor fields are required to lo ad the required keys, context, and text-data. (some operations, for example, do not require context.) therefore, wh en processing descriptors the sec skips entirely any pointer that has an associated length of zero. if the channel procedure calls fo r reading a parcel using a nonzero length field, but the pointer field is zero, the length value is written to the eu but no data parcel is fetched from the bus. the j bit in each pointer dword is used to enable the s catter/gather feature. if a da ta parcel to be read or written by sec is in one contiguous block of memory locations, then th e scatter/gather feature is not needed. in this case the pointer should be set to point directly at the first byte of the parcel, and the j bit should be 0. on the other hand, if th e data parcel is stored in several separate segments of memory, then the scatter/gather capability is needed to assemble or distribute the complete parcel. in this case the pointer should be set to point to a link table, an d the j bit should be 1. for link table format, see section 17.3.4, ?link table format.? 17.3.4 link table format link tables implement scatter/gather capability. fo r gather operations, a link table specifies a list of memory segments that are to be concatenated in the process of assembling data parcels. for scatter operations, a link table specifi es a list of memory segm ents into which the output data should be written. scatter or gather of a data parcel may be specified by a single link ta ble or by a chain of link tables that are linked together with pointers (see figure 17-7 ). the link table or chain of link ta bles accessed through some descript or pointer must specify enough memory segments to hold all the data that will be accessed through that poi nter. in most cases, only a single data parcel is accessed th rough a given pointer, and the chain of link tables specif ies just that parcel. in other cases, the descriptor pointer is used multiple times to access a sequence of data parcels, and the chain of link tables must su pply data for the entire seque nce. if a link table is used to access a sequence of data parcels, the end of e ach parcel must also be at the end of a memory segment. in other words, a single memory segment must not st raddle two data parcels. an example of proper construction of link tables is illustrated in figure 17-7 . table 17-7. pointer dword field definitions bits name description 0?15 length a number of bytes in the range 0 to 65535. the use of this field depends on the descriptor type and direction in the header dword. a value of ze ro causes the channel to skip this dword. 16 j jump. determines whether to jump to a link table w henever the pointer field in this same lword is used. 0 the pointer field points to data. 1 the pointer field points to a link table, and scatter/gather is enabled. 17?23 extent a number of bytes in the range 0 to 127. the use of this field depends on the descriptor type and direction in the header dword. 24?27 ? reserved 32?63 pointer a memory address. 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 17-20 freescale semiconductor a link table may contain any number of long word entries. there are two kinds of en tries, ?regular? entries and ?next? entries. each ?regular ? entry specifies a memory segment by means of a 32-bi t starting address (segadr) and a 16-bit length (s eglen). a ?next? entry is used at the end of a link table to specify that the list of memory segments is continued in another link tabl e. in a ?next? entry, the n bit is set and the segadr field gives the address of the next link table, and the seglen field must be 0. a chain of link tables may contain any number of link tables. whether the list of memory segments is in a single link table or split into several link tables, the last entry in the last link table is a ?regular? entry with the r (return) bit set. th e r bit signifies th e end of link table operations so that the channel returns to the descri ptor for its next pointer (if any). link tables are illustrated in figure 17-7 . for any sequence of data parcels ac cessed by a link table or chain of li nk tables, the combined lengths of the parcels (the sum of their lengt h and/or extent fields) must equa l the combined lengths of the link table memory segments (seglen fiel ds). otherwise the channel sets the appropriate error bit in the channel pointer status register?ger for ga ther error or ser for scatter error (see section 17.5.1.1, ?crypto-channel configur ation register (cccr)? ). 0 1516 21222324 3132 63 seglen ? r n ? segadr figure 17-6. link table entry format table 17-8. link table field definitions bits name description 0?15 seglen length. when n = 0, a number in the range 1 to 65535, specifying the number of bytes in the memory segment. pointed to by segadr. a value of 0 will cause an error bit to be set in the channel pointer status register?ger for a gather operation or ser for a scatter operation (see section 17.5.1.1, ?crypto-channel configuration register (cccr)? ). when n = 1, must be zero. 16?21 ? reserved 22 r return when n = 0: 0 no special action 1 this is the last entry in the chain of link tables. if this entry does no t specify the right number of bytes to complete the last data parcel, a ger or ser erro r will be set in the channel pointer status register (see section 17.5.1.1, ?crypto-channel configuration register (cccr)? ). note: when n = 1, this field is ignored. 23 n next 0 no special action 1 this is the last long word in the current link table. the segadr field is the address of the next link table in the chain. 24?31 ? reserved 32?63 segadr segment address. a memory address. 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 17-21 17.3.4.1 link table example figure 17-7 illustrates various ways that a de scriptor may specify data parcels: ? the first pointer dword in the de scriptor specifies parcel a using the simplest method: the parcel is specified directly through pointer0 and length0. ? the next pointer dword uses a chai n of link tables to specify parcel b. since j = 1, pointer1 is used as the address of a link table. the link table sp ecifies several ?regular? entries specifying data segments to be concatenated. the last word of the link table is a ?next? entr y indicating that the list continues in the next link table. the last entry in the last link table of the chain has the r bit set. ? the last cases illustrate how one pointer in a desc riptor can be used to specify multiple parcels. pointer2 and length2 specify parcel c, then parcel d follows imme diately afterwards, with length specified by extent2. pointer3 is used for three da ta parcels (e, f, and g), this time using link tables. to demonstrate use of a link table, a ssume that the current descriptor type calls for the channel to access a data parcel using pointer3 and extent 3 fields, and assume that j3 = 1. due to the j3 value, pointer3 is not used as a data address but instead used as the address of a link table. the channel begins by reading the first four long words starting at pointe r3 into an internal link table buffer. 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 17-22 freescale semiconductor figure 17-7. descriptors, link tables, and data parcels using the first entry of the link tabl e, the channel starts accessing the data parcel by reading seglen bytes beginning at segadr. if the required data parcel size (extent3) is grea ter than this first seglen, the channel moves on to the next entry of the link table, and reads seglen bytes starting at segadr. while there are more bytes to be read in the data parcel, this process c ontinues. if the chan nel?s link table buffer is exhausted, the channel reads the ne xt four long words of the link table into its link table buffer. if a link table entry is encountered in which the n bit is set, the channel uses the segadr field in that word to find the next link table in the chain. the last byte of the re quired parcel size (extent3) must coincide with the last byte of a memory segment, or unpredictable results may occur. now assume that the channel accesses its next data parcel using pointer3 again, this time with length given by length3. in this case the channel continues to the ne xt line of the link table, and begins reading the descriptor link tables n = 1 n = 1 r = 1 r = 1 n = 1 data segments parcel a length0 parcel b length1 parcel c length2 parcel d extent2 parcel e extent3 parcel f length3 parcel g extent4 data parcels length0 j = 0 pointer0 header dword length1 j = 1 pointer1 length2 j = 0 extent2 pointer2 length3 j = 1 extent3 pointer3 extent4 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 17-23 memory segment specified there. as before, the ch annel concatenates memory segments from as many link table entries as necessary to obtain the required number of bytes (length3). similarly, the next data parcel is obtained by using pointer3 yet agai n, this time with length given by extent4. assume that for the current descript or type, the extent4 data parcel is the last one to be accessed through pointer3. then the link table entry that supplies the last memory segment for extent4 has the r bit set, signifying that this is the last entry in the chain of link tables. 17.3.5 descriptor types table 17-9 shows how the pointer dwords s hould be used with the various descriptor types to load keys, context, and text data into the execution uni ts, and how the required outputs should be unloaded. additional explanation of the use of certain descriptor types and the meaning of the pointer dwords can be found in the sec 2.0 descriptor programmer?s guide . table 17-9. descriptor pointer dword usage descriptor type pointer dword1 pointer dword2 pointer dword3 pointer dword4 extent4 pointer dword5 extent5 pointer dword6 extent6 pointer dword7 0000_0 nil cipher iv cipher key in fifo nil out fifo nil cipher iv out nil nil 0001_0 nil cipher iv cipher key in fifo nil out fifo nil cipher iv out nil nil 0010_0 hmac key hmac data cipher key cipher iv nil in fifo nil out fifo nil hmac out 0011_0 reserved 0100_0 reserved 0101_0 nil arc4 context (in fifo) arc4 key in fifo nil out fifo nil arc4 context (out fifo) nil nil 0110_0 reserved 0111_0 reserved 1000_0 n b a e nil b out nil nil nil nil 1001_0 reserved 1010_0 reserved 1011_0 reserved 1100_0 hmac key hmac data aes key aes ctx nil in fifo nil out fifo nil hmac out 1101_0 reserved 1110_0 reserved 1111_0 reserved 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 17-24 freescale semiconductor 17.4 execution units execution unit (eu) is the term used for a functional block that perfor ms the mathematical permutations required by protocols used in cryptographic proces sing. the eus are compatible with ipsec, ike, ssl/tls, iscsi, srtp, and 802.11i standard processi ng, and can work together to perform high level cryptographic tasks. the following execution units are used in the sec: ? public key execution unit (pkeu) ? data encryption standard execution unit (deu) ? advanced encryption standard execution unit (aesu) implementi ng the rijndael symmetric-key cipher. ? arc four execution unit (afeu) ? message digest execution unit (mdeu) ? one private on-chip random number generator (rng) working together, the eus can perf orm high-level cryptographic tasks, such as ipsec encapsulating security protocol (esp) and digital signature. the re mainder of this chapter pr ovides details about the execution units themselves. 17.4.1 public key execution unit (pkeu) this section contains details about the public key execut ion unit (pkeu), including detailed register map, modes of operation, status and contro l registers, and the parameter rams. the following sections describe pkeu registers and parameter memories. 0000_1 hmac key hmac data cipher iv cipher key nil in fifo nil out fifo hmac out cipher iv out 0001_1 nil aes ctx aes key in fifo nil in fifo nil out fifo nil aes ctx out 0010_1 hmac key aes ctx aes key in fifo in fi fo out fifo in fifo hmac out nil aes ctx out 0011_1 a0 a1 a2 a3 nil b0 nil b1 nil ?build? 0100_1 n e ?build? b1 out nil b2 out nil b3 out nil nil 0101_1 n ?build? b2 b3 nil b1 out nil b2 out nil b3 out others reserved table 17-9. descriptor pointer dword usage (continued) descriptor type pointer dword1 pointer dword2 pointer dword3 pointer dword4 extent4 pointer dword5 extent5 pointer dword6 extent6 pointer dword7 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 17-25 17.4.1.1 pkeu mode register (pkeumr) this register specifies the internal pkeu routine to be ex ecuted. pkeumr is clea red when the pkeu is reset or re-initialized. setting the mo de field to a reserved value will generate a data error. if pkeumr is modified during processing, a c ontext error will be generated. figure 17-8 shows pkeumr, and table 17-10 lists the possible mode field values. table 17-10 lists the possible mode field values. de pending on the value written to pkeumr[mode] will depend on the routine used. para meter memories are referred to for the base address, as shown. 0 55 56 63 field ?mode reset 0 r/w r/w addr pkeu 0x3_c000 figure 17-8. pkeu mode register (pkeumr) table 17-10. pkeumr mode field descriptions routine name routine description mode reserved reserved 0x00 clearmemory clear memory 0x01 mod_exp fp: exponentiate mod n and deconvert from montgomery format 0x02 mod_r2modn fp: compute montgome ry converter (r2 mod n) 0x03 mod_rrmodp fp: compute montgomery converter for chinese remainder theorem (rnrp mod n) 0x04 ec_fp_aff_ptmult fp ec: multiply key times point in affine coordinates 0x05 ec_f2m_aff_ptmult f 2 m ec: multiply key times point in affine coordinates 0x06 ec_fp_proj_ptmult fp ec: multiply key times point in projective coordinates 0x07 ec_f2m_proj_ptmult f 2 m ec: multiply key times point in projective coordinates 0x08 ec_fp_add fp ec: add two points in projective coordinates 0x09 ec_fp_double fp ec: double a point in projective coordinates 0x0a ec_f2m_add f 2 m ec: add two points in projective coordinates 0x0b ec_f2m_double f 2 m ec: double a point in projective coordinates 0x0c f2m_r2 f 2 m: compute montgomery converter (r2 mod n) 0x0d f2m_inv 1 f 2 m: invert mod n 0x0e mod_inv 2 fp: invert mod n 0x0f mod_add fp: add mod n 0x10 mod_sub fp: subtract mod n 0x20 mod_mult1_mont fp: multiply mod n in montgomery format 0x30 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 17-26 freescale semiconductor 17.4.1.2 pkeu key size register (pkeuksr) the pkeu key size register, shown in figure 17-9 , reflects the number of signi ficant bytes to be used from pkeu parameter memory e in performing modular expone ntiation or ellipt ic curve point multiplication. note that leading zeros are note si gnificant and are not considered pa rt of the key (m odulus) size. the range of values for this register, when performing either modular expon entiation or elliptic curve point multiplication, is from 1 to 256. specifying a key size out side of this range will cause a key size error in the pkeu interrupt status regi ster (pkeuisr[kse] is set). note writing to this register while in debug mode generates an illegal size error. disable the illegal size error in the asso ciated interrupt cont rol register prior to performing debug operations. 17.4.1.3 pkeu ab size register (pkeuabs) the pkeu ab size register ( figure 17-10 ) represents the operand size for the specific operands whenever it is required. the unit of the value written into pk euabs[ab size] is in bits, even though internally the pkeu imposes a 32-bit alignment. any data beyond th e number of bits in pkeuabs, either in a- and b-ram (operands) will be ignored. no error checking is performed whether the operand sizes are greater than the prime modulus or the field size and this ma y cause a wrong result. in ot her words, it is assumed that operands are modulo reduced be fore being written into the pkeu . hence, pkeuabs[ab size] must mod_mult2_deconv fp: multiply mod n and deconvert from montgomery format 0x40 f2m_add f 2 m: add mod n 0x50 f2m_mult1_mont f 2 m: multiply mod n in montgomery format 0x60 f2m_mult2_deconv f 2 m: multiply mod n and deconve rt from montgomery format 0x70 rsa_sstep fp: exponentiate mod n (combi nes mod_r2modn, f2m_mult1_mont, and mod_exp) 0x80 spk_build build pk data structure 0xff 1 f2m_inv returns incorrect results for modulus sizes greater than 480 bits. 2 mod_inv returns incorrect results for modulus sizes greater than 480 bits. 0 51 52 63 field ?key size reset 0 r/w r/w addr pkeu 0x3_c008 figure 17-9. pkeu key size register (pkeuksr) table 17-10. pkeumr mode field descriptions (continued) routine name routine description mode 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 17-27 be less than or equal to data si ze for a correct result. if pkeuabs is modified during processing, an error will be generated. an illegal data size error will be generated as follows: ? for all non-ecc routines, a data size >256 wi ll generate an illegal data size error. ? for all ecc routines, a data size >64 wi ll generate an illegal data size error. setting pkeuabs[ab size] = 0 (either intentionally or by ignoring it a nd not writing it at all) will generate an illegal size error, except for routines that do not require an a or b operand, such as the clear_mem routine. note writing to this register while in debug mode generates an illegal size error. disable the illegal size error in the asso ciated interrupt cont rol register prior to performing debug operations. figure 17-10. pkeu ab size register (pkeuabs) 17.4.1.4 pkeu data size register (pkeudsr) the pkeu data size register, shown in figure 17-11 , specifies the size in bits of the significant portion of the modulus or irreducible pol ynomial. any value written to this register that is a multiple of 32 bits (for example, 128 bits or 160 bits) will be represented intern ally as the same value (1 28 bits or 160 bits). any value written that is not a multiple of 32 bits (for example, 132 bits or 161 bits) will be represented internally as the next larger 32 bit multiple (160 bits or 196 bits). this intern al rounding up to the next 32-bit multiple is described for in formation only. the minimum size va lid for all routines to operate properly is 97 bits (interna lly 128 bits). the maximum si ze to operate properly is 2048 bits. a value in bits larger than 2048 will result in a data size error. note writing to this register while in debug mode generates an illegal size error. disable the illegal size error in the associated interrupt control register prior to performing debug operations. 0 51 52 63 field ? ab size reset 0 r/w r/w addr pkeu 0x3_c040 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 17-28 freescale semiconductor figure 17-11. pkeu data size register (pkeudsr) 17.4.1.5 pkeu reset cont rol register (pkeurcr) this register, shown in figure 17-12 , contains three reset opti ons specific to the pkeu. table 17-11 describes pkeurcr fields. 0 51 52 63 field ? data size reset 0 r/w r/w addr pkeu 0x3_c010 0 60 61 62 63 field ?rimisr reset 0 r/w r/w addr pkeu 0x3_c018 figure 17-12. pkeu reset control register (pkeurcr) table 17-11. pkeurcr field descriptions bits name description 0?60 ? reserved 61 ri reset interrupt. writing this bit active high causes pkeu interrupts signaling do ne and error to be reset. it further resets the state of th e pkeu interrupt status register. 0 do not reset interrupt logic. 1 reset interrupt logic. 62 mi module initialization. module init ialization is nearly the same as software reset, except that the interrupt control register remains unchanged. this module initiali zation includes execution of an initialization routine, completion of wh ich is indicated by the rd (reset done) bit in th e pkeu status register ( section 17.4.1.6, ?pkeu status register (pkeusr)? ). 0 don?t reset. 1 reset most of pkeu. 63 sr sw reset. software reset is func tionally equivalent to hardware reset (the reset# pin), but only for the pkeu. all registers and internal state are returned to their defined reset state. upon negation of sw_reset, the pkeu will enter a routine to perform proper initia lization of the parameter memories. the rd (reset done) bit in the pkeu status register will indicate when this initialization routine is complete. (see section 17.4.1.6, ?pkeu status register (pkeusr).? ) 0 don?t reset. 1 full pkeu reset. 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 17-29 17.4.1.6 pkeu status register (pkeusr) this status register contains fields which reflect the stat e of pkeu internal fields. pkeusr is read only. writing to this register will result in an addres s error being reflected in the pkeu interrupt status register (pkeuisr[ae] is set). figure 17-13. pkeu status register (pkeusr) table 17-12 describes pkeusr fields. 0 56 57 58 59 60 61 62 63 field ? z halt ? ie id rd reset 0 r/w read only addr pkeu 0x3_c028 table 17-12. pkeusr field descriptions bits name description 0?56 ? reserved 57 z zero. reflects the state of the pkeu zero detect bi t when last sampled. only particular instructions within routines cause z to be modified, so this bit should be used with great care. 58 halt halt indicates that the pkeu has halted due to an error. 0 pkeu not halted 1 pkeu halted note: because the error causing the pkeu to stop oper ating may be masked to the interrupt status register, the status register is used to provide a second sour ce of information regarding errors preventing normal operation. 59?60 ? reserved 61 ie interrupt error. this status bit reflects the state of the error interrupt signal, as sampled by the controller interrupt status register (see section 17.6.2.2, ?interrupt status register (isr)? ). 0 pkeu is not signaling error 1 pkeu is signaling error 62 id interrupt done. this status bit reflects the state of the done interrupt signal, as sampled by the controller interrupt status register (see section 17.6.2.2, ?interrupt status register (isr)? ). 0 pkeu is not signaling done 1 keu is signaling done 63 rd reset done. this status bit, when high, indicates t hat pkeu has completed its internal reset sequence. 0 reset in progress 1 reset done 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 17-30 freescale semiconductor 17.4.1.7 pkeu interrupt status register (pkeuisr) the pkeu interrupt status regist er tracks the state of possible errors?if those errors are not masked?through the pkeu interrupt control register (pkeuicr). the definition of each bit in the pkeuisr is shown in figure 17-14 . figure 17-14. pkeu interrupt status register (pkeuisr) table 17-13 describes pkeuisr fields. 0 49505152535455565758 63 field ? inv ie ? ce kse dse me ae ? reset 0 r/w read only addr pkeu 0x3_c030 table 17-13. pkeuisr field descriptions bits name description 0 ? 49 ? reserved 50 inv inversion error. indicates that the inversion routine has a zero operand. 0 no inversion error detected 1 inversion error detected 51 ie internal error. an internal processing error was detected while the pkeu was operating. 0 no error detected 1 internal error note: this bit will be asserted any time an enabled error condition occurs and can only be cleared by setting the corresponding bit in the interrupt control register or by resetting the pkeu. 52 ? reserved 53 ce context error. pkeukr n , pkeuksr, pkeudsr, or pkeumr was modi fied while the pkeu was operating. 0 no error detected 1 context error 54 kse key size error. value outside the bounds of 1?256 bytes was written to pkeuksr 0 no error detected 1 key size error detected 55 dse data size error. value outside the bounds 97?2048 bits was written to pkeudsr 0 no error detected 1 data size error detected 56 me mode error. an illegal value was detected in pkeumr. 0 no error detected 1 mode error note: writing to reserved bits in a mode register is a likely source of error. 57 ae address error. illegal read or write address was detected within the pkeu address space. 0 no error detected 1 address error 58 ? 63 ? reserved 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 17-31 17.4.1.8 pkeu interrupt co ntrol register (pkeuicr) the pkeu interrupt control register c ontrols the result of detected erro rs. for a given error (as defined in section 17.4.1.7, ?pkeu interrupt st atus register (pkeuisr)? ), if the corresponding bit in this register is set, then the error is disabled; no error interrupt occurs and the interrupt status regi ster is not updated to reflect the error. if the corresponding bit is not set, then upon detection of an error, pkeuisr is updated to reflect the error, causing assertion of the erro r interrupt signal, and cau sing the module to halt processing. figure 17-15. pkeu interrupt control register (pkeuicr) table 17-14 describes pkeuicr fields. 0 49505152535455565758 63 field ? inv ie ? ce kse dse me ae ? reset 0x0000_0000_0000_1000 r/w read only addr pkeu 0x3_c038 table 17-14. pkeuicr field descriptions bits name description 0 ? 49 ? reserved 50 inv inversion error 0 inversion error enabled 1 inversion error disabled 51 ie internal error 0 internal error enabled 1 internal error disabled 52 ? reserved 53 ce context error 0 context error enabled 1 context error disabled 54 kse key size error 0 key size error enabled 1 key size error disabled 55 dse data size error 0 data size error enabled 1 data size error disabled 56 me mode error 0 mode error enabled 1 mode error disabled 57 ae address error 0 address error enabled 1 address error disabled 58 ? 63 ? reserved 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 17-32 freescale semiconductor 17.4.1.9 pkeu eu-go register (pkeueug) the eu-go register in the pkeu is us ed to indicate the start of a new co mputation. writing to this register causes the pkeu to execut e the function requested by the mode regist er, per the contents of the parameter memories listed below. note that this register has no data size, and during the writ e operation, the host data bus is not read. hence, any data value is accepted. normally, a write operation wi th a zero data value is performed. moreover, no read operation from this register is meaningful , but no error is generated, and a zero value is always returned. pkeu eug is only used when the is operate d as a slave. the descriptors and crypto-channel activate the pkeu (t hrough an internally generated writ e to pkeueug) when the acts as an initiator. figure 17-16. pkeu eu-go register (pkeueug) 17.4.1.10 pkeu parameter memories the pkeu uses four 2048-bit memories to receive a nd store operands for the arithmetic operations the pkeu will be asked to perform. in addition, results are stored in one particular parameter memory. all these memories store data in the same format: least significant data byte in the least significantly addressed byte, both data significance and addr essing significance increasing identically and simultaneously. 17.4.1.10.1 pkeu parameter memory a this 2048-bit memory is typically used as an input parameter memory space. for modular arithmetic routines, this memory operates as one of the operands of the desired function. for elliptic curve routines, this memory is segmented into four 512-bit memories, and is used to sp ecify particular curve parameters and input values. 17.4.1.10.2 pkeu parameter memory b this 2048-bit memory is typically us ed as an input paramete r memory space, as well as the result memory space. for modular arithmetic routines, this memory se rves as one of the operands of the desired function, as well as the result memory space. for elliptic curv e routines, this memory is segmented in to four 512-bit memories, and is used to specify particular curve para meters and input values, as well as to store result values. 0 63 field pkeu eu-go reset 0 r/w w addr pkeu 0x3_c050 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 17-33 17.4.1.10.3 pkeu parameter memory e this 2048-bit memory is non-segmentable, and stor es the exponent for modul ar exponentiation, or the multiplier k for elliptic curve point multipli cation. this memory space is writ e only; a read of this memory space will cause address error to be reflected in the pkeuisr. 17.4.1.10.4 pkeu parameter memory n this 2048-bit memory is non-segmentable, and stor es the modulus for modular arithmetic and f p elliptic curve routines. for f 2 m elliptic curve routines, this memo ry stores the irreducible polynomial. 17.4.2 data encryption stan dard execution unit (deu) this section contains details about the data encryption standard exec ution unit (deu), including detailed register map, modes of operation, stat us and control registers, and fifos. the registers used in the deu ar e documented primarily for debug a nd slave mode operations. if the sec requires the use of the deu when acting as an initiato r, accessing these registers directly is unnecessary. the device drivers and on-chip controller will abstract register-level access from the user. 17.4.2.1 deu mode register (deumr) the deu mode register contains 3 bi ts which are used to program the de u. it also reflects the value of burst size, which is loaded by the crypto-channel dur ing normal operation with the sec as an initiator. burst size is not relevant to slave mode operations, where an external host pushes and pulls data from the execution units. deumr is cleared when the deu is rese t or re-initialized. sett ing a reserved mode bit will generate a data error. if the mode register is modified during processing, a co ntext error will be generated. figure 17-17. deu mode register (deumr) table 17-15 describes deumr fields. 0 5253 55 56 60616263 field ? burst size ?cetsed reset 0 r/w r/w addr deu 0x3_2000 table 17-15. deumr field descriptions bits name description 0?52 ? reserved 53?55 burst size implements flow control to allow larger than fifo-sized blocks of data to be processed with a single key/iv. the deu signals to the channel that a burst size amount of data is available to be pushed to or pulled from the fifo. note: the inclusion of this field in deumr is to avoi d confusing a user who may read this register in debug mode. burst size should not be written directly to the deu. 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 17-34 freescale semiconductor 17.4.2.2 deu key size register (deuksr) this value indicates the number of bytes of key memory that should be used in encrypting or decrypting. if deumr is set for single des, any value other than 8 bytes will automatically generate a key size error in the deuisr. if the mode bit is set for triple des, any value other than 16 bytes (112 bits for 2-key triple des (k1 = k3) or 24 bytes (168 bits for 3-key triple des) will generate an error. triple des always uses k1 to encrypt, k2 to decrypt, k3 to encrypt. note writing to this register while in debug mode generates an illegal size error. disable the illegal size error in the asso ciated interrupt cont rol register prior to performing debug operations. figure 17-18. deu key size register (deuksr) 56?60 ? reserved 61 ce cbc/ecb. if set, deu operates in cipher-block-chaining mode. if not set, deu operates in electronic codebook mode. 0ecb mode 1 cbc mode 62 ts triple/single des. if set, deu performs the triple des algorithm; if not set, deu performs the single des algorithm. 0 perform single des. 1 perform triple des. 63 ed encrypt/decrypt. if set, deu performs the encr yption algorithm; if no t set, deu performs the decryption algorithm. 0 perform decryption. 1 perform encryption. 0 51 52 63 field ?key size reset 0 r/w r/w addr deu 0x3_2008 table 17-15. deumr field descriptions (continued) bits name description 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 17-35 table 17-16 shows the legal values for deuksr[key size]. 17.4.2.3 deu data size register (deudsr) this register, shown in figure 17-19 , is used to verify that the data to be processed by the deu is divisible by the des algorithm block size of 64 bits. the deu does not auto matically pad messages out to 64-bit blocks; therefore, any message proce ssed by the deu must be di visible by 64 bits or a data size error will occur. in normal operation, the full message length (data size) to be encrypted or decrypted by the deu is copied from the descriptor to de udsr; however, only bits 58?63 are checked to determin e if there is a data size error. if bits 58?63 are all zeros, the message is evenly divisible into 64-bit blocks. in ta rget mode, the user must write the data size to de udsr. if the data size written is not divisible by 64-bits (bits 58?63 nonzero), a data size error will occur. note writing to this register while in debug mode generates an illegal size error. disable the illegal size error in the asso ciated interrupt cont rol register prior to performing debug operations. figure 17-19. deu data size register (deudsr) table 17-16. deuksr field descriptions bits name description 0?51 ? reserved 52?63 key size 8 bytes = 0x08 (only legal value if mode is single des) 16 bytes = 0x10 (for 2 key 3des, k1 = k3) 24 bytes = 0x18 (for 3 key 3des) 0 51 52 63 field ? data size reset 0 r/w r/w addr deu 0x3_2010 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 17-36 freescale semiconductor 17.4.2.4 deu reset cont rol register (deurcr) this register, shown in figure 17-20 , allows three levels of reset of just the deu, as defined by the three self-clearing bits: figure 17-20. deu reset control register (deurcr) table 17-17 describes deurcr fields. 0 60 61 62 63 field ? ri mi sr reset 0 r/w r/w addr deu 0x3_2018 table 17-17. deurcr field descriptions bits names description 0?60 ? reserved 61 ri reset interrupt. writing this bit active high causes deu interrupts signaling done and error to be reset. it further resets the state of deuisr. 0 don?t reset. 1 reset interrupt logic. 62 mi module initialization is nearly the same as software reset, except that the interrupt control register remains unchanged. this module initialization includes execution of an initialization routine, completion of which is indicated by the reset_done bit in deusr. 0 don?t reset. 1 reset most of deu. 63 sr software reset is functionally equ ivalent to hardware reset (the reset# pi n), but only for deu. all registers and internal state are returned to their defined reset state. upon negation of sw _reset, the deu will enter a routine to perform proper initia lization of the paramet er memories. the reset_d one bit in deusr will indicate when this initialization routine is complete 0 don?t reset. 1 full deu reset 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 17-37 17.4.2.5 deu status register (deusr) the deu status register, displayed in figure 17-21 , contains six fields whic h reflect the state of deu internal signals. deusr is read only; writing to deusr will result in an addres s error being reflected in deuisr. figure 17-21. deu status register (deusr) table 17-12 describes deusr fields. 0 3940 4748 555657585960616263 field ? ofl ifl ? halt ? ie id rd reset 0 r/w read only addr deu 0x3_2028 table 17-18. deusr field descriptions bits name description 0?39 ? reserved 40?47 ofl the number of dwords currently in the output fifo 48?55 ifl the number of dwords currently in the input fifo 56?57 ? reserved 58 halt halt. indicates that the deu has halted due to an error. 0 deu not halted 1 deu halted note: because the error causing the deu to stop operating may be masked to the interrupt status register, the status register is used to prov ide a second source of information regarding errors preventing normal operation. 59?60 ? reserved 61 ie interrupt error. this status bit reflects the state of the error interrupt signal, as sampled by the controller interrupt status register ( section 17.6.2.2, ?interrupt status register (isr)? ). 0 deu is not signaling error. 1 deu is signaling error. 62 id interrupt done. this status bit reflects the state of the done interrupt signal, as sampled by the controller interrupt status register ( section 17.6.2.2, ?interrupt status register (isr)? ). 0 deu is not signaling done. 1 deu is signaling done. 63 rd reset done. this status bit, when high, indicates that deu has completed its internal reset sequence. 0 reset in progress 1 reset done 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 17-38 freescale semiconductor 17.4.2.6 deu interrupt status register (deuisr) the deu interrupt status register, shown in figure 17-22 , tracks the state of possibl e errors, if those errors are not masked through deuicr. figure 17-22. deu interrupt status register (deuisr) table 17-19 describes deuisr fields. 0 495051525354 55 565758 59606162 63 field ? kpe ie ere ce kse dse me ae ofe ife ifu ifo ofu ofo reset 0 r/w read only addr deu 0x3_2030 table 17-19. deuisr field descriptions bits name description 0?49 ? reserved 50 kpe key parity error. defined parity bits in the keys written to the key registers did not reflect odd parity correctly. (note that deuk2 and deuk3 are checked for parity only if the appropriate deumr bit indicates triple des. also, key register 3 is checked only if deuksr[key size] = 24. deuk2 is checked only if deuksr[key size] = 16 or 24.) 0 no error detected 1 key parity error detected 51 ie internal error. an internal processing error was detected while performing encryption. 0 no error detected 1 internal error detected note: this bit will be asserted any time an enabled error condition occurs and can only be cleared by setting the corresponding bit in the interrupt control register or by resetting the deu. 52 ere early read error. the deu iv register wa s read while the deu was performing encryption. 0 no error detected 1 early read error detected 53 ce context error. deukr, deuksr, deudsr, deumr, or deuiv was modified while the deu was performing encryption. 0 no error detected 1 context error 54 kse key size error. an inappropriate value (8 being appropriate for single des, and 16 and 24 being appropriate for triple des) was written to deuksr. 0 no error detected 1 key size error detected 55 dse data size error (dse). a value was written to deudsr that is not a multiple of 64 bits. 0 no error detected 1 data size error detected 56 me mode error. an illegal value was detected in deumr. note: writing to reserved bits in deumr is the likely source of error. 0 no error detected 1 mode error 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 17-39 17.4.2.7 deu interrupt control register (deuicr) the deu interrupt control register controls the result of detected errors. for a given error (as defined in section 17.4.2.6, ?deu interrupt st atus register (deuisr)? ), if the corresponding bit in this register is set, then the error is ignored, no erro r interrupt occurs and deuisr is not updated to reflect the error.if the corresponding bit is not set, then upon detection of an er ror, deuisr is updated to reflect the error, causing assertion of the error inte rrupt signal, and causing the module to halt processing. figure 17-23. deu interrupt control register (deuicr) 57 ae address error. an illegal read or write addr ess was detected within the deu address space. 0 no error detected 1 address error 58 ofe output fifo error. the deu output fifo was detected non-empty upon write of deudsr. 0 no error detected 1 output fifo non-empty error 59 ife input fifo error. the deu in put fifo was detected non-empty upon generation of done interrupt. 0 no error detected 1 input fifo non-empty error 60 ifu input fifo underflow. the deu input fifo has been read while empty. 0 no error detected 1 input fifo had underflow error 61 ifo input fifo overflow. the deu input fifo has been pushed while full. 0 no error detected 1 input fifo has overflowed note: when operating as a master, the deu implements flow -control, and fifo size is not a limit to data input. when operated as a target, the deu cannot accept fifo inputs larger than 512 bytes without overflowing. 62 ofu output fifo underflow. the deu ou tput fifo has been read while empty. 0 no error detected 1 output fifo has underflow error 63 ofo output fifo overflow. the deu output fifo has been pushed while full. 0 no error detected 1 output fifo has overflowed 0 4950 51 525354 55 56 57 58 59 606162 63 field ? kpe ie ere ce kse dse me ae ofe ife ifu ifo ofu ofo reset 0x0000_0000_0000_3000 r/w r/w addr deu 0x3_2038 table 17-19. deuisr field descriptions (continued) bits name description 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 17-40 freescale semiconductor table 17-20. deuicr field descriptions bits name description 0?49 ? reserved 50 kpe key parity error. the defined parity bits in the keys written to the key registers did not reflect odd parity correctly. (note that deuk2 and deuk3 are only checked for parity if the appropriate deumr bit indicates triple des. 0 key parity error enabled 1 key parity error disabled 51 ie internal error. an internal processing error was detected while performing encryption. 0 internal error enabled 1 internal error disabled 52 ere early read error. the deu iv register wa s read while the deu was performing encryption. 0 early read error enabled 1 early read error disabled 53 ce context error. deukr, deuksr, deudsr, deumr, or deuiv was modified while the deu was performing encryption. 0 context error enabled 1 context error disabled 54 kse key size error. an inappropriate value (8 being appropriate for single des, and 16 and 24 being appropriate for triple des) was written to deuksr. 0 key size error enabled 1 key size error disabled 55 dse data size error (dse): a value was written to deudsr that is not a multiple of 8 bytes. 0 data size error enabled 1 data size error disabled 56 me mode error. an illegal value was detected in deumr. 0 mode error enabled 1 mode error disabled 57 ae address error. an illegal read or write addr ess was detected within the deu address space. 0 address error enabled 1 address error disabled 58 ofe output fifo error. the deu output fifo was dete cted non-empty upon write of deu data size register 0 output fifo non-empty error enabled 1 output fifo non-empty error disabled 59 ife input fifo error. the deu in put fifo was detected non-empty upon generation of done interrupt 0 input fifo non-empty error enabled 1 input fifo non-empty error disabled 60 ifu input fifo underflow error. the deu input fifo has been read while empty. 0 input fifo underflow error enabled 1 input fifo underflow error disabled 61 ifo input fifo overflow error. the de u input fifo has been pushed while full. 0 input fifo overflow error enabled 1 input fifo overflow error disabled note: when operating as a master, the deu implements flow -control, and fifo size is not a limit to data input. when operated as a target, the deu cannot accept fifo inputs larger than 512 bytes without overflowing. 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 17-41 17.4.2.8 deu eu-go register (deueug) the eu-go register in the deu is used to indicat e a des operation may be completed. after the final message block is written to the input fifo, deueug must be written. the value in the data size register will be used to determine how many bits of the fi nal message block (always 64) will be processed. note that this register has no data si ze, and during the write operation, the hos t data bus is not read. hence, any data value is accepted. norm ally, a write operation with a zero data value is pe rformed. moreover, no read operation from this register is mean ingful, but no error is generated, and a zero value is always returned. writing to deueug is merely a trigger causing the de u to process the final bl ock of a message, allowing it to signal done. deueug is only used when the sec is operated as a slave. the descri ptors and crypto-ch annel activate the deu (through an internally generated write to deueug) when the sec acts as an initiator. figure 17-24. deu eu-go register (deueug) 17.4.2.9 deu iv register (deuiv) for cbc mode, the initialization vector is written to and read from deuiv. the value of this register changes as a result of the encrypt ion process and reflects the context of deu. reading deuiv while the module is processing data ge nerates an er ror interrupt. 17.4.2.10 deu key registers (deuk1?deuk3) the deu uses three write-only key registers to perf orm encryption and decryption. in single des mode, only deuk1 may be written. the value written to deuk1 is simultaneously written to deuk3, auto-enabling the deu for 1 12-bit triple des if deuksr indicates 2-key 3des is to be performed (key size = 16 bytes). to operate in 168-bi t triple des, deuk1 must be wri tten first, followed by deuk2, then deuk3. reading any of these memory locations generates an address error interrupt. 62 ofu output fifo underflow error. the de u output fifo has been read while empty. 0 output fifo underflow error enabled 1 output fifo underflow error disabled 63 ofo output fifo overflow. the deu output fifo has been pushed while full. 0 output fifo overflow error enabled 1 output fifo overflow error disabled 0 63 field deu eu-go reset 0 r/w w addr deu 0x3_2050 table 17-20. deuicr field descriptions (continued) bits name description 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 17-42 freescale semiconductor 17.4.2.11 deu fifos deu uses an input fifo/output fifo pair to hold data before and after the encryption process. these fifos are multiply addressable, but those multiple addresses point only to th e appropriate end of the appropriate fifo. a write to anywhere in the deu fifo address space causes the 64-bit word to be pushed onto the deu input fifo, and a read from anywhere in the de u fifo address space causes a 64-bit-word to be popped off the deu output fifo. overflows and underflows caused by reading or writing the deu fifos are reflected in the deu interrupt status register. 17.4.3 arc four execution unit (afeu) this section contains deta ils about the arc four ex ecution unit (afeu), includi ng detailed register map, modes of operation, status and contro l registers, s-box memory, and fifos. the registers used in the afeu are documented prim arily for debug and slave mode operations. if the sec requires the use of the afeu when acting as an initia tor, accessing these registers directly is unnecessary. the device drivers and the on-chip controller will abstract register level access from the user. 17.4.3.1 afeu mode register (afeumr) shown in figure 17-25 , the afeu mode register c ontains three bits which are used to program the afeu. it also reflects the value of burst size, which is loaded by the crypto- channel during norm al operation with the sec as an initiator. burst size is not relevant to slave mode operations, where an external host pushes and pulls data from the execution units. afeumr is cleared when the afeu is reset or re-initialized. setting a reserved mode bit generates a data error. if afeumr is modified during processing, a context error is generated. 17.4.3.2 host-provided context through prevent permute in the default mode of operation, the host provides the key and key size to the afeu. the initial memory values in the s-box are permuted w ith the key to create ne w s-box values, which ar e used to encrypt the plaintext. if afeumr[pp] is set (prevent pe rmute mode is enabled), the afeu will not require a key. rather, the host will write the context to the afeu, and message processing will occur using the provided context. this mode is used to resume pr ocessing of a message using the alr eady permuted s-box. the context may be written through the fifo if afeumr[cs] is set. 17.4.3.2.1 dump context this mode may be independently specified (using afeumr[dc]) in addition to host-provided context mode. in this mode, once me ssage processing is complete and the output data is read, the afeu will make the current context data available for reads through the output fifo. 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 17-43 note after the initial key permute to generate a context for an afeu encrypted session, all subsequent messag es will re-use that cont ext, such that it is loaded, modified during the encryption, and unloaded, similar to the use of a cbc initialization vector in des ope rations. a new context is generated (through key permute) according to a re -keying interval specified by the security protocol. context should never be loaded to encrypt a message if a key is loaded and permuted at the same time. table 17-21 describes afeu mode register fields. 17.4.3.3 afeu key size register (afeuksr) as displayed in figure 17-26 , this value indicates the number of byt es of key memory that should be used in performing s-box permutation. any key data beyond the number of bytes in afeuksr will be ignored. 0 5253 55 56 60616263 field ? burst size ? cs dc pp reset 0 r/w r/w addr afeu 0x3_8000 figure 17-25. afeu mode register (afeumr ) table 17-21. afeumr field descriptions bits name description 0?52 ? reserved 53?55 burst size the afeu implements flow control to allow la rger than fifo-sized blocks of data to be processed with a single key/context. the afeu si gnals to the channel that burst size amount of data is available to be pushed to or pulled from the fifo. note: the inclusion of this field in the afeumr is to avoid confusing a user who may read this register in debug mode. burst size should not be written directly to the afeu. 56?60 ? reserved 61 cs context source. if set, cs caus es the context to be moved from the input fifo into the s-box prior to starting encryption/decryption. other wise, context should be directly written to the context registers. cs is only checked if pp is set. 0 context not from fifo 1 context from input fifo 62 dc dump context. if set, this causes the context to be moved from the s-box to the output fifo following assertion afeu?s done interrupt. 0 do not dump context 1 after cipher, dump context 63 pp prevent permute. normally, afeu receives a ke y and uses that information to randomize the s-box. if reusing a context from a previous descriptor, pp should be set to prevent afeu from reperforming this permutation step. 0 perform s-box permutation 1 do not permute 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 17-44 freescale semiconductor afeuksr is cleared when the afeu is reset or re-initialized. if the key size specified is less than 1 or greater than 16, a key size error wi ll be generated. if afeuksr is m odified during processing, a context error will be generated. note that although the afeu supports key lengths as short as 1 byte, a 1-byte key offers little security. most uses of arc4 specify keys of 5?16 bytes. note writing to this register while in debug mode generates an illegal size error. disable the illegal size error in the asso ciated interrupt cont rol register prior to performing debug operations. figure 17-26. afeu key size register (afeuksr) note the device driver will create properly formatted descriptors for situations requiring a key permute prior to ciphering. when operating the sec as a slave (typically while in debug mode), the user must set the afeu mode register (afeumr) to perform ?permute with key?, then write the key data to the afeu key registers, then write the key size to the key size register (afeuksr[key size]). the afeu will start permuting the memory with the contents of the afeu key regi sters immediately after afeuksr[key size] is written. 17.4.3.4 afeu context/data size register (afeudsr) the afeu context/data size register, shown in figure 17-27 , stores the number of bi ts in the final message block. afeudsr is cleared when the afeu is reset or re-i nitialized. the last message block can be between 8 to 64 bits. if a data size that is not a mult iple of 8 bits is written, a data size error will be generated. a data size of 0 is illegal and results in the associated crypto-channel locking, requiring a crypto-channel and afeu reset. afeudsr is also used to specify the context size. th e context size is fixed at 2072 bits (259 bytes). when loading context through the fifo, all context data must be written prior to writing the context data size. the message data size must be written separately. 0 51 52 63 field ? key size reset 0 r/w r/w addr afeu 0x3_8008 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 17-45 note in slave mode, when reloading an exis ting context, the user must write the context to the input fifo, then writ e the context size (always 2072 bits). the write of the context si ze indicates to the that al l context has been loaded. the user then writes the message data size to afeudsr. after this write, the user may begin writing message data to the fifo. writing to afeudsr signals the afeu to start pro cessing data from the input fifo as soon as it is available. if the value of data si ze is modified during processing, a context error will be generated. note writing to this register while in debug mode generates an illegal size error. disable the illegal size error in the asso ciated interrupt cont rol register prior to performing debug operations. 17.4.3.5 afeu reset control register (afeurcr) this register, shown in figure 17-28 , allows 3 levels reset that affe ct the afeu only, as defined by 3 self-clearing bits. it should be noted that the afeu executes an internal reset sequence for hardware reset, software reset, or module initiali zation, which performs proper initiali zation of the s-box. to determine when this is complete, observe the reset_done bit in afeusr. 0 51 52 63 field ? data size reset 0 r/w r/w addr afeu 0x3_8010 figure 17-27. afeu data size register (afeudsr) 0 60 61 62 63 field ? ri mi sr reset 0 r/w r/w addr afeu 0x3_8018 figure 17-28. afeu reset control register (afeurcr ) 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 17-46 freescale semiconductor table 17-22 describes afeurcr fields. note the afeu must be reset prior to fi rst use following a power on reset. failure to do so results in undefined behavior. set the sr bit to perform afeu reset. 17.4.3.6 afeu status register (afeusr) this status register, shown in figure 17-29 , contains 6 bits which reflect the state of the afeu internal signals. the afeusr is read-only. writing to this location will result in addres s error being reflected in afeuisr. figure 17-29. afeu status register (afeusr) table 17-23 describes afeusr fields. table 17-22. afeurcr field descriptions bits name description 0?60 ? reserved 61 ri reset interrupt. writing this bit causes afeu interr upts signaling done and error to be reset. it further resets the state of afeuisr. 0 do not reset 1 reset interrupt logic 62 mi module initialization is nearly the same as software reset, except that the interrupt control register remains unchanged. 0 do not reset 1 reset most of afeu 63 sr software reset is functionally eq uivalent to hardware re set (the reset# pin), but only for afeu. all registers and internal state are returned to their defined reset state. on negation of sw_reset, the afeu will enter a routine to perform proper in itialization of the s-box. 0 do not reset 1 full afeu reset 0 3940 4748 555657 58 596061 62 63 field ? ofl ifl ? halt ? ie id rd reset 0 r/w read only addr afeu 0x3_8028 table 17-23. afeusr field descriptions bits name description 0?39 ? reserved 40?47 ofl the number of dwords currently in the output fifo 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 17-47 17.4.3.7 afeu interrupt stat us register (afeuisr) the afeu interrupt stat us register, seen in figure 17-30 , tracks the state of possibl e errors, if those errors are not masked through afeuicr. figure 17-30. afeu interrupt status register (afeuisr) table 17-24 describes afeuisr fields. 48?55 ifl the number of dwords currently in the input fifo 56?57 ? reserved 58 halt halt. indicates that the afeu has halted due to an error. 0 afeu not halted 1 afeu halted note: because the error causing the afeu to stop operati ng may be masked to the interrupt status register, the status register is used to prov ide a second source of information regarding errors preventing normal operation. 59?60 ? reserved 61 ie interrupt error. this status bit reflects the state of the error interrupt signal, as sampled by the controller interrupt status register ( section 17.6.2.2, ?interrupt status register (isr)? ). 0 afeu is not signaling error. 1 afeu is signaling error. 62 id interrupt done. this status bit re flects the state of the done interrupt signal, as sampled by the controller interrupt status register ( section 17.6.2.2, ?interrupt status register (isr)? ). 0 afeu is not signaling done. 1 afeu is signaling done. 63 rd reset done. this status bit, when high, indicates t hat afeu has completed its internal reset sequence. 0 reset in progress 1 reset done 0 505152 53 54 55 5657 58 596061 6263 field ? ieereceksedsemeaeofeife?ifoofu? reset 0 r/w read only addr afeu 0x3_8030 table 17-24. afeuisr field descriptions bits names description 0?50 ? reserved 51 ie internal error. an internal processing error was detected while performing encryption. 0 no error detected 1 internal error table 17-23. afeusr field descriptions (continued) bits name description 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 17-48 freescale semiconductor 17.4.3.8 afeu interrupt co ntrol register (afeuicr) the interrupt control register, shown in figure 17-31 , controls the result of detected errors. for a given error (as defined in section 17.4.3.7, ?afeu interrupt st atus register (afeuisr)? ), if the corresponding bit in afeuicr is set, the error is disabled; no error interrupt o ccurs, and afeuisr is not updated to reflect the error. if the corresponding bit is not set, then upon detection of an error, afeuisr is updated 52 ere early read error. the afeu context memory or control was read while the afeu was performing encryption. 0 no error detected 1 early read error 53 ce context error. afeumr, afeukr n , afeuksr, afeudsr, or context memory was modified while afeu processes data. 0 no error detected 1 context error 54 kse key size error. a value outside the bounds 1?16 bytes was written to afeuksr. 0 no error detected 1 key size error 55 dse data size error. an inconsistent va lue (not a multiple of 8 bits, or larger than 64 bits) was written to afeudsr. 0 no error detected 1 data size error 56 me mode error. an illegal value was detected in afeumr. no te: writing to reserved bits in mode register is likely source of error. 0 no error detected 1 mode error 57 ae address error. an illegal read or write addr ess was detected within the afeu address space. 0 no error detected 1 address error 58 ofe output fifo error. the afeu output fifo was detected non-empty upon write of afeudsr. 0 no output fifo error detected 1 output fifo error detected 59 ife input fifo error. the afeu input fifo was detected non-empty upon generation of done interrupt. 0 no input fifo error detected 1 input fifo error detected 60 ? reserved 61 ifo input fifo overflow. the afeu in put fifo has been pushed while full. 0 no error detected 1 input fifo has overflowed. note: when operating as a master, the afeu implements flow -control, and fifo size is not a limit to data input. when operated as a target, the afeu cannot accept fifo in puts larger than 512 bytes without overflowing. 62 ofu output fifo underflow. the afeu ou tput fifo has been read while empty. 0 no error detected 1 output fifo has underflow error. 63 ? reserved table 17-24. afeuisr field descriptions (continued) bits names description 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 17-49 to reflect the error, causing assertion of the erro r interrupt signal, and cau sing the module to halt processing. figure 17-31. afeu interrupt control register (afeuicr) table 17-25 describes afeuicr fields. 0 5051525354 555657585960616263 field ? ie ere ce kse dse me ae ofe ife ? ifo ofu ? reset 0x0000_0000_0000_1000 r/w r/w addr afeu 0x3_8038 table 17-25. afeuicr field descriptions bits names description 0?50 ? reserved 51 ie internal error. an internal processing error was detected while performing encryption. 0 internal error enabled 1 internal error disabled 52 ere early read error. the af eu register was read while th e afeu was performing encryption. 0 early read error enabled 1 early read error disabled 53 ce context error. afeukr n , afeuksr, afeudsr, afeumr, or contex t memory was modified while afeu was performing encryption. 0 context error enabled 1 context error disabled 54 kse key size error. a value outside the bounds 1?16 bytes was written to afeuksr. 0 key size error enabled 1 key size error disabled 55 dse data size error. an inconsiste nt value was written to the afeudsr. 0 data size error enabled 1 data size error disabled 56 me mode error. an illegal value was detected in afeumr. 0 mode error enabled 1 mode error disabled 57 ae address error. an illegal read or write addr ess was detected within the afeu address space. 0 address error enabled 1 address error disabled 58 ofe output fifo error. the afeu output fifo was detected non-empty upon write of afeudsr. 0 output fifo non-empty error enabled 1 output fifo non-empty error disabled 59 ife input fifo error. the afeu input fifo was detected non-empty upon generation of done interrupt. 0 input fifo non-empty error enabled 1 input fifo non-empty error disabled 60 ? reserved 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 17-50 freescale semiconductor 17.4.3.9 afeu end of message register (afeuemr) the end of message register in the afeu, displayed in figure 17-32 , is used to indicate an arc4 operation may be completed. after th e final message block is written to the input fifo, afeuemr must be written. the value in afeudsr wi ll be used to determine how many bits of the final message block (8-64, in multiples of 8) will be processed. writing to this register causes the afeu to process the final block of a message, allowing it to signal done. if afeumr[dc] is set (dump context mode is enabled), the context will be written to the output fifo following the last mess age word. a read of afeuemr will always return a zero value. afeuemr is only used when the afeu is operated as a slave. the descriptors and crypto-channel activate the afeu (by mean s of an internally generated write to afeuemr) when the sec acts as an initiator. figure 17-32. afeu end of message register (afeuemr) 17.4.3.10 afeu context this section provides additional information about the afeu context memory and its related pointer register. 17.4.3.10.1 afeu context memory the s-box memory consists of 32 64-bit words, each readable and wr itable. the s-box contents should not be written with data unless it was previously read from th e s-box. context data may only be written if afeumr[pp] is set (prevent permutation mode is enabled, see figure 17-25 ), and the context data must be written prior to the message da ta. if the context registers are wr itten during message processing or afeumr[pp] is not set, a context error will be generate d. reading this memory while the module is not done will generate an error interrupt. 61 ifo input fifo overflow. the afeu in put fifo has been pushed while full. 0 input fifo overflow error enabled 1 input fifo overflow error disabled 62 ofu output fifo underflow. the afeu output fifo has been read while empty. 0 output fifo underflow error enabled 1 output fifo underflow error disabled 63 ? reserved 0 63 field afeu end of message reset 0 r/w w addr afeu 0x3_8050 table 17-25. afeuicr field descriptions (continued) bits names description 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 17-51 17.4.3.10.2 afeu context me mory pointer registers the context memory pointer registers hold the internal context pointers that are u pdated with each byte of message processed. these pointers corr espond to the values of i, j, a nd sbox[i+1] in the arc4 algorithm. if this register is written during message processing, a context error will be generated. when performing arc4 operations, the user has the option of performing a ne w s-box permutation per packet, or unloading the contents of the s-box (context) and reloading th is context prior to processing the next packet. the s-box contents ( 256 bytes) plus the 3 bytes of the context memory pointers are unloaded and reloaded through the afeu fifos. afeu context consists of the contents of the s-box, as well as three counter va lues, which indicate the next values to be used from the s- box. context must be loaded in the same order in which it was unloaded. 17.4.3.11 afeu key registers (afeuk0, afeuk1) afeu uses two write-only key regist ers to guide initial permutation of the afeu s-box, in conjunction with the afeu key size register. afeu performs permutation starting with the first byte of afeuk0, and uses as many bytes from the two ke y registers as necessary to complete the permutat ion. reading either of these memory locations will genera te an address error interrupt. 17.4.3.11.1 afeu fifos afeu uses an input fifo/output fi fo pair to hold data before and after the encryption process. these fifos are multiply addressable, but those multiple addresses point only to th e appropriate end of the appropriate fifo. a write to anywhere in the afeu fifo addres s space causes the 64-bit-word to be pushed onto the afeu input fifo, and a read from a nywhere in the afeu fifo address space causes a 64-bit-word to be popped off the afeu output fifo. overflows and underflows caused by reading or writing the afeu fifos are reflected in the afeu interrupt status register. 17.4.4 message digest execution unit (mdeu) this section contains details about the message digest execution unit (m deu), including detailed register map, modes of operation, status a nd control registers, and fifos. the registers used in the mdeu are documented pr imarily for debug and slav e mode operations. if the sec requires the use of the mdeu when acting as an initiator, accessing thes e registers directly is unnecessary. the device drivers and th e on-chip controller will abstract register le vel access from the user. 17.4.4.1 mdeu mode register (mdeumr) the mdeu mode register, shown in figure 17-33 , contains 8 bits which are used to program the mdeu. it also reflects the value of burst size, which is loaded by the crypto- channel during norm al operation with the sec 2.0 as an initiator. burst size is not releva nt to slave mode operations, where an external host pushes and pulls data fr om the execution units. mdeumr is cleared when the mdeu is reset or re-ini tialized. setting a reserved mode bit will generate a data error. if mdeumr is modified during processing, a context e rror will be generated. 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 17-52 freescale semiconductor figure 17-33. mdeu mode register (mdeumr) table 17-26 describes mdeumr fields. 17.4.4.2 recommended settings for mdeumr the most common task likely to be executed th rough the mdeu is hmac generation. hmacs are used to provide message integrity within a number of security protocols, including ipsec, and ssl/tls. when the hmac is being generated by a si ngle descriptor (the mdeu acting as sole or secondary eu), the following mdeumr bit se ttings should be used: 0 5253 55 56575859 60 616263 field ? burst size cont ? init hmac pd alg reset 0 r/w r/w addr mdeu 0x3_6000 table 17-26. mdeumr field descriptions bits name description 0?52 ? reserved 53?55 burst size the mdeu implements flow control to allow la rger than fifo-sized blocks of data to be processed with a single key/context. the mdeu signals to t he channel that a burst size amount of data is available to be pushed to the fifo. note: the inclusion of this field in the mdeumr is to avoid confusing a user who may read this register in debug mode. burst size should not be written directly to the mdeu. 56 cont continue?used during hmac/hash processing when the data to be hashed is spread across multiple descriptors. 0 don?t continue?operate the md eu in auto completion mode 1 preserve context to operate the mdeu in continuation mode 57?58 ? reserved, set to zero. 59 init initialization bit?cause an algorithm-specific initia lization of the digest registers. most operations will require this bit to be set. only operations that load context from a known intermediate hash value would not initialize the registers. 0 do not initialize. 1 initialize the selected algorithm?s starting registers. 60 hmac identifies the hash operation to execute 0 perform standard hash. 1 perform hmac operation. this requires a key and key length information. 61 pd if set, configures the mdeu to automatically pad partial message blocks. 0 do not autopad. 1 perform automatic message padding whenever an incomplete message block is detected. 62?63 alg message digest algorithm selection 00 sha-160 algorithm (full name for sha-1) 01 sha-256 algorithm 10 md5 algorithm 11 reserved 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 17-53 the sec cannot calculate an hmac ac ross multiple descriptors. howeve r, it is capable of calculating a simple hash across multiple descriptors. when the ha sh is being generated for a message that is spread across a chain of descriptors, the follow ing mdeumr bit setti ngs should be used: all descriptors other than the fina l descriptor must output the inte rmediate message digest for the following descriptor to reload as mdeu context. additional information on de scriptors can be found in section 17.1.1, ?data packet descriptors.? 17.4.4.3 mdeu key size register (mdeuksr) displayed in figure 17-34 , mdeuksr indicates the num ber of bytes of key memo ry that should be used in hmac generation. the mdeu supports at most 64 bytes of key. the mdeu will generate a key size error if the value written to mdeuksr exceeds 64 bytes. note writing to this register while in debug mode generates an illegal size error. disable the illegal size error in the asso ciated interrupt cont rol register prior to performing debug operations. figure 17-34. mdeu key size register (mdeuksr) table 17-27. mdeumr?hmac generated by single descriptor bits field value 56 cont 0 (off) 59 init 1 (on) 60 hmac 1 (on) 61 pd 1 (on) table 17-28. mdeumr?hmac generated for a message across a chain of descriptors bits field value first descriptor middle descriptor(s) final descriptor 56 cont 1 (on) 1 (on) 0 (off) 59 init 1 (on) 0 (off) 0 (off) 60 hmac 0 (off) 0 (off) 0 (off) 61 pd 0 (off) 0 (off) 1 (on) 0 56 57 63 field ? key size reset 0 r/w r/w addr mdeu 0x3_6008 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 17-54 freescale semiconductor 17.4.4.4 mdeu data size register (mdeudsr) the mdeu data size register, shown in figure 17-35 , stores the size of the last block of data (in bits) to be processed. because the mdeu does not support bit of fsets, any value other than 0 in bits 61?63 will cause a data size error. bits 58?60 are used to iden tify the ending byte location in the last 8-byte dword. this is used to add the data paddi ng when auto padding is selected. mdeudsr is cleared when the mdeu is reset, re-initialized, and at the e nd of processing the complete message. note writing to mdeudsr will allow the mdeu to enter auto-start mode. therefore, the required context data s hould be written prior to writing the data size. note writing to this register while in debug mode generates an illegal size error. disable the illegal size error in the asso ciated interrupt cont rol register prior to performing debug operations. figure 17-35. mdeu data size register (mdeudsr) 17.4.4.5 mdeu reset control register (mdeurcr) this register, shown in figure 17-36 , allows three levels of reset of ju st the mdeu, as de fined by the three self-clearing bits. figure 17-36. mdeu reset control register (mdeurcr) 0 56 57 63 field ? data size reset 0 r/w r/w addr mdeu 0x3_6010 0 60 61 62 63 field ? ri mi sr reset 0 r/w r/w addr mdeu 0x3_6018 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 17-55 table 17-29 describes mdeurcr fields. 17.4.4.6 mdeu status register (mdeusr) the mdeu status register, as seen in figure 17-37 , reflects the state of the mdeu internal signals. the majority of these internal signals reflect the state of low-level mdeu functions , such as data padding and key padding, and are not important to the user; however, the user should be aware that reads of this register, especially during processing, are li kely to return non-zero values for many bits between 0?57. the four signals shown are those which are most li kely to be of interest to the user. mdeusr is read only. figure 17-37. mdeu status register (mdeusr) table 17-23 describes mdeusr fields. table 17-29. mdeurcr field descriptions bits name description 0?60 ? reserved 61 ri reset interrupt. writing this bit active high causes mdeu interrupts signaling done and error to be reset. it further resets the state of the mdeuisr. 0 no reset 1 reset interrupt logic 62 mi module initialization is nearly the same as soft ware reset, except that the mdeuicr remains unchanged. 0 no reset 1 reset most of mdeu 63 sr software reset is functionally equivalent to hardware reset (the reset pin), but only for the mdeu. all registers and internal state are returned to their defined reset state. 0 no reset 1 full mdeu reset 0 57 58 59 60 61 62 63 field ? halt ? ie id rd reset 0 r/w read only addr mdeu 0x3_6028 table 17-30. mdeusr field descriptions bits name description 0?57 ? reserved 58 halt halt. indicates that the mdeu has halted due to an error. 0 mdeu not halted 1 mdeu halted note: because the error causing the mdeu to stop operating may be masked to mdeuisr, mdeusr is used to provide a second source of informat ion regarding errors preventing normal operation. 59?60 ? reserved 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 17-56 freescale semiconductor 17.4.4.7 mdeu interrupt st atus register (mdeuisr) the interrupt status register tracks the state of possible errors, if t hose errors are not masked through the mdeuisr. the definition of each field in mdeuisr is shown in figure 17-38 . figure 17-38. mdeu interrupt status register (mdeuisr) table 17-31 describes mdeuisr fields. 61 ie interrupt error. this status bit reflects the state of the error interrupt signal, as sampled by the controller isr ( section 17.6.2.2, ?interrupt status register (isr)? ). 0 mdeu is not signaling error. 1 mdeu is signaling error. 62 id interrupt done. this status bit re flects the state of the done interrupt signal, as sampled by the controller isr ( section 17.6.2.2, ?interrupt status register (isr)? ). 0 mdeu is not signaling done 1 mdeu is signaling done 63 rd reset done. this status bit, when high, indicates t hat mdeu has completed its internal reset sequence. 0 reset in progress 1 reset done 0 50515253545556575860616263 field ? ie ere ce kse dse me ae ? ifo ? reset 0 r/w read only addr mdeu 0x3_6030 table 17-31. mdeuisr field descriptions bits name description 0?50 ? reserved 51 ie internal error. indicates the mdeu has been locked up and requires a reset before use. 0 no internal error detected 1 internal error detected note: this bit will be asserted any time an enabled error condition occurs and can only be cleared by resetting the mdeu. 52 ere early read error. the mdeu context was re ad before the mdeu completed the hashing operation. 0 no error detected 1 early read error 53 ce context error. the mdeu key register, mdeuksr, or mdeudsr was modified while mdeu was hashing. 0 no error detected 1 context error 54 kse key size error. a value greater than 64 bytes was written to mdeuksr. 0 no error detected 1 key size error table 17-30. mdeusr field descriptions (continued) bits name description 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 17-57 17.4.4.8 mdeu interrupt co ntrol register (mdeuicr) the mdeu interrupt cont rol register, shown in figure 17-39 , controls the result of detected errors. for a given error (as defined in section 17.4.4.7, ?mdeu interrupt st atus register (mdeuisr)? ), if the corresponding bit in mdeuicr is set, the error is disabled; no error in terrupt occurs and mdeuisr is not updated to reflect the error. if the corresponding bit is not set, then upon detection of an error, mdeuisr is updated to reflect the error, causing assertion of the error interrupt signal, and causing the module to halt processing. figure 17-39. mdeu interrupt control register (mdeuicr) table 17-31 describes mdeuicr fields. 55 dse data size error. a value not a multiple of 512 bits while the mdeu mode register autopad bit is negated. 0 no error detected 1 data size error 56 me mode error. an illegal value for alg was detected in mdeumr. 0 no error detected 1 mode error 57 ae address error. an illegal read or write addr ess was detected within the mdeu address space. 0 no error detected 1 address error 58?60 ? reserved 61 ifo input fifo overflow. the mdeu in put fifo has been pushed while full. 0 no overflow detected 1 input fifo has overflowed. note: when operating as a master, the implements flow contro l, and fifo size is not a limit to data input. when operated as a target, the can not accept fifo inputs larger t han 512 bytes without overflowing. 62?63 ? reserved 0 50515253545556575860616263 field ? ie ere ce kse dse me ae ? ifo ? reset 0x0000_0000_0000_1000 r/w r/w addr mdeu 0x3_6038 table 17-32. mdeuicr field descriptions bits name description 0?50 ? reserved 51 ie internal error. an internal processing error was detected while performing hashing. 0 internal error enabled 1 internal error disabled table 17-31. mdeuisr field descriptions (continued) bits name description 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 17-58 freescale semiconductor 17.4.4.9 mdeu eu-go register (mdeueug) the eu-go register in the mdeu (see figure 17-40 ) is used to indicate that an authentication operation may be completed. after the final me ssage block is written to the input fifo, mdeueug must be written. the value in mdeudsr will be used to determine how many bits of th e final message block (always 512) will be processed. note that mdeu eug has no data size, and during th e write operation, the host data bus is not read. hence, any data value is accepted. norm ally, a write operation with a zero data value is performed. moreover, no read operation from mdeueug is meaningful, but no er ror is generated, and a zero value is always re turned. writing to mdeueug is merely a trigger causing the mdeu to process the final block of a message, allowing it to signal done. mdeueug is only used when the sec is operated as a slave. the descriptors and cr ypto-channel activate the mdeu (by means of an internally generated writ e to mdeueug) when the sec acts as an initiator. 52 ere early read error. the mdeu register was read while the mdeu was performing hashing. 0 early read error enabled 1 early read error disabled 53 ce context error. the mdeu key re gister, mdeuksr, mdeudsr, or mdeu mr was modified while the mdeu was performing hashing. 0 context error enabled 1 context error disabled 54 kse key size error. a value outside the bounds of 64 bytes was written to the mdeu key size register 0 key size error enabled 1 key size error disabled 55 dse data size error. an inconsistent value was written to mdeudsr: 0 data size error enabled 1 data size error disabled 56 me mode error. an illegal value was detected in mdeumr. 0 mode error enabled 1 mode error disabled 57 ae address error. an illegal read or write addr ess was detected within the mdeu address space. 0 address error enabled 1 address error disabled 58?60 ? reserved 61 ifo input fifo overflow. the mdeu input fifo has been pushed while full. 0 input fifo overflow error enabled 1 input fifo overflow error disabled 62?63 ? reserved table 17-32. mdeuicr field descriptions (continued) bits name description 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 17-59 figure 17-40. mdeu eu-go register (mdeueug) 17.4.4.10 mdeu context registers for mdeu, context consists of the hash plus the messa ge length count. write access to this register block allows continuation of a previous hash. reading these regi sters provides the result ing message digest or hmac, along with an aggregate bit count. note sha-1and sha-256 are big endian. md 5 is little endian. the mdeu module internally reverses the endianness of the five registers a, b, c, d, and e upon writing to or reading fr om the mdeu context if the mdeu mode register indicates md5 is the hash of choi ce. most other endian considerations are performed as 8- byte swaps. in this case, 4-byte endianness swapping is performed within the a, b, c, d, and e fields as individual registers. reading this me mory location while the module is not done will generate an error interrupt. after a power-on reset, all the mdeu context register values are cleared. figure 17-41 shows how the mdeu context registers are initialized if the init bit is set in mdeumr. all registers are initialized, regardless of mode selected; however , only the appropriate mdeu context register values are used in hash generation according to the mode selected. the user typically does not care about the mdeu context register initialization values; however, they are docum ented for completeness in the event the user reads these registers during a debug operati on. mdeu reset through mdeurcr (see figure 17-36 ) or sec global software reset (see figure 17-68 ) does not clear these registers. 0 63 field mdeu eu-go reset 0 r/w w addr mdeu 0x3_6050 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 17-60 freescale semiconductor 17.4.4.11 mdeu key registers the mdeu maintains eight 64-bit registers for writ ing an hmac key. the ip ad and opad operations are performed automatically on the key data when required. note sha-1 and sha-256 are big endian. md 5 is little endian. the mdeu module internally reverses the endi anness of the key upon writing to or reading from the mdeu key register s if mdeumr indicates md5 is the hash of choice. 17.4.4.12 mdeu fifos mdeu uses an input fifo to hold data to be hashe d. the input fifo is multip ly addressable, but those multiple addresses point only to th e write (push) end of the fifo. a wr ite to anywhere in the mdeu fifo address space causes the 64-bit-word s to be pushed onto the mdeu input fifo, and a read from anywhere in the mdeu fifo address space returns all zeros. 0313263 name a b context offset 0x3_6100 md-5 0x01234567 0x89abcdef sha-1 0x67452301 0xefcdab89 sha-256 0x6a09e667 0xbb67ae85 name c d context offset 0x3_6108 md-5 0xfedcba98 0x76543210 sha-1 0x98badcfe 0x10325476 sha-256 0x3c6ef372 0xa54ff53a name e f context offset 0x3_6110 md-5 0xf0e1d2c3 0x8c68059b sha-1 0xc3d2e1f0 0x9b05688c sha-256 0x510e527f 0x9b05688c name g h context offset 0x3_6118 md-5 0xabd9831f 0x19cde05b sha-1 0x1f83d9ab 0x5be0cd19 sha-256 0x1f83d9ab 0x5be0cd19 name message length count context offset 0x3_6120 reset 0 figure 17-41. mdeu context registers 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 17-61 note sha-1 and sha-256 are big endian. md 5 is little endian. the mdeu module internally reverses the endi anness of the key upon writing to or reading from the mdeu key register s if the mdeumr indicates md5 is the hash of choice. 17.4.5 random number generator (rng) this section contains deta ils about the random number generator (rng), including detailed register map, modes of operation, status and control registers, and fifos. the rng is an execution unit capable of generating 64-bit random numbers. it is designed to comply with the fips-140 standard for randomness and non-determinism. a linear feedback shif t register (lfsr) and cellular automata shift register (casr) are operated in parallel to generate pseudo-random data. the rng consists of six major functional blocks: ? bus interface unit (biu) ? linear feedback shift register (lfsr) ? cellular automata shift register (casr) ? clock controller ? six ring oscillators the states of the lfsr and ca sr are advanced at unknown freque ncies determined by the two ring oscillator clocks and the clock cont rol. when a read is performed, the oscillator clocks are halted and a collection of bits from the lfsr and casr are xored together to obtain the 64-bit random output. the registers used in th e rng are documented primarily for debug and slave mode operations. if the sec requires the use of the rng when acting as an initia tor, accessing these register s directly is unnecessary. the device drivers and the on-chip controller will abstract register level access from the user. 17.4.5.1 rng mode register (rngmr) the rng mode register is used to control the rng. one operational mode , randomizing, is defined. writing any other value than 0 to bits 56?63 results in a data error interrupt that is reflected in the rngisr. rngmr also reflects the value of burst size, which is loaded by the crypto-channel during normal operation with the rng as an initiator. burst size is not relevant to slave mode operations, where an external host pushes a nd pulls data from the execution units. 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 17-62 freescale semiconductor rngmr is cleared when the rng is rese t or re-initialized. rngmr is shown in figure 17-42 . 17.4.5.2 rng data size register (rngdsr) the rng data size register is used to tell the rng to begin generati ng random data. the actual contents of rngdsr do not affect the operation of the rng. afte r a reset and prior to the first write of data size, the rng builds entropy without pushing data onto th e fifo. once rngdsr is written, the rng will begin pushing data onto the fifo. data will be pushe d onto the fifo every 256 cycles until the fifo is full. the rng then attempts to keep the fifo full. note writing to this register while in debug mode generates an illegal size error. disable the illegal size error in the asso ciated interrupt cont rol register prior to performing debug operations. figure 17-43. rng data size register (rngdsr) 0 52 53 55 56 63 field ? burst size ? reset 0 r/w r/w addr 0x3_a000 figure 17-42. rng mode register (rngmr) table 17-33. rngmr field definitions bits name description 0?52 ? reserved, must be set to zero. 53?55 burst size the rng implements flow control to allow larger than fifo-sized blocks of data to be processed with a single key/context. the rng signals to the cryp to-channel that a burst size amount of data is available to be pulled from the fifo. note: the inclusion of this field in the rngmr is to av oid confusing a user who may read this register in debug mode. burst size should not be written directly to the rng. 56?63 ? reserved 0 63 field rng data size reset 0 r/w r/w addr 0x3_a010 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 17-63 17.4.5.3 rng reset cont rol register (rngrcr) this register, shown in figure 17-44 , contains three reset opti ons specific to the rng. figure 17-44. rng reset control register (rngrcr) table 17-34 describes rngrcr fields. 17.4.5.4 rng status register (rngsr) this rng status register, figure 17-45 , contains six fields which reflec t the state of the rng internal signals. rngsr is read only. writing to this location will re sult in an address error being reflected in rngisr. figure 17-45. rng status register (rngsr) 0 60 61 62 63 field ? ri mi sr reset 0 r/w r/w addr 0x3_a018 table 17-34. rngrcr field descriptions bits name description 0-60 ? reserved 61 ri reset interrupt. writing this bit causes rng inte rrupts signaling done and error to be reset. it further resets the state of the rngisr. 0 no reset 1 reset interrupt logic 62 mi module initialization. this reset value performs enoug h of a reset to prepare the rng for another request, without forcing the internal control machines and the output fifo to be reset, thereby invalidating stored random numbers or requiring reinvocation of a warm-up per iod. module initialization is nearly the same as software reset, except t hat rngicr remains unchanged. 0 no reset 1 reset most of the rng 63 sr software reset is functionally equivalent to hardware reset (the reset # pin), but only for the rng. all registers and internal state are returned to their defined reset state. 0 no reset 1 full rng reset 8?63 ? reserved 0 3940 4748 57585960616263 field ? ofl ? halt ? ie id rd reset 0 r/w read only addr rng 0x3_a028 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 17-64 freescale semiconductor table 17-23 describes rng status register fields. 17.4.5.5 rng interrupt status register (rngisr) the rng interrupt status register tr acks the state of possible errors, if those errors are not masked, through the rngicr. the definition of each bit in rngisr is shown in figure 17-46 . figure 17-46. rng interrupt status register (rngisr) table 17-35. rngsr field descriptions bits name description 0?39 ? reserved 40-47 ofl the number of dwords currently in the output fifo 48-57 ? reserved. internal status bits may be observed as nonzero. 58 halt halt. indicates that the rng has halted due to an error. 0 rng not halted 1 rng halted note: because the error causing the rng to stop operating may be masked to the interrupt status register, the status register is used to prov ide a second source of information regarding errors preventing normal operation. 59-60 ? reserved 61 ie interrupt error. this status bit reflects the state of the error interrupt signal, as sampled by the controller isr ( section 17.6.2.2, ?interrupt status register (isr)? ). 0 rng is not signaling error. 1 rng is signaling error. 62 id interrupt done. this status bit reflects the state of the done interrupt signal, as sampled by the controller interrupt status register ( section 17.6.2.2, ?interrupt status register (isr)? ). 0 rng is not signaling done. 1 rng is signaling done. 63 rd reset done. this status bit, when set, indicates that the rng has completed its internal reset sequence. 0 reset in progress 1 reset done 0 505152 55565758 616263 field ? ie ? me ae ? ofu ? reset 0 r/w read only addr rng 0x3_a030 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 17-65 table 17-36 describes rngisr fields. 17.4.5.6 rng interrupt control register (rngicr) the rng interrupt control register c ontrols the result of detected erro rs. for a given error (as defined in section 17.4.5.5, ?rng interrupt st atus register (rngisr)? ), if the corresponding b it in rngicr is set, then the error is disabled; no error interrupt occurs a nd rngisr is not updated to reflect the error. if the corresponding bit is not set, then upon detection of an error, rngisr is updated to reflect the error, causing assertion of the error interrupt signa l, and causing the module to halt processing. figure 17-47. rng interrupt control register (rngicr) table 17-36. rngisr field descriptions bits name description 0?50 ? reserved 51 ie internal error 0 no internal error detected 1 internal error 52?55 ? reserved 56 me mode error. indicates that the host has attempted to write an illegal value to rngmr. 0 valid data 1 invalid data error 57 ae address error. an illegal read or write address was detected within the rng address space. 0 no error detected 1 address error 58?61 ? reserved 62 ofu output fifo underflow. the rng output fifo has bee n read while empty. 0 no overflow detected 1 output fifo has underflowed 63 ? reserved 0 505152 55565758 616263 field ? ie ? me ae ? ofu ? reset 0x0000_0000_0000_1000 r/w read only addr rng 0x3_a038 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 17-66 freescale semiconductor table 17-37 describes rngicr fields. 17.4.5.7 rng eu-go register (rngeug) the rng eu-go is a writable location but serves no f unction in the rng. it is documented for the sake of consistency with the other eus. figure 17-48. rng eu-go register (rngeug) 17.4.5.8 rng fifo rng uses an output fifo to collect periodically sa mpled random 64-bit-words, with the intent that random data always be available fo r reading. the fifo is multiply ad dressed, but those multiple addresses point only to the appropriate end of the output fifo. a read from a nywhere in the rng fifo address space causes a 64-bit-word to be popped off the r ng output fifo. underflows caused by reading or writing the rng output fifo are reflected in rngisr . also, a write to the rn g output fifo space will be reflected as an addressing error in rngisr. table 17-37. rngicr field descriptions bits name description 0?50 ? reserved 51 ie internal error. an internal processing error was detected while generating random numbers. 0 internal error enabled 1 internal error disabled 52?55 ? reserved 56 me mode error. an illegal value was detected in rngmr. 0 mode error enabled 1 mode error disabled 57 ae address error. an illegal read or write addr ess was detected within the mdeu address space. 0 address error enabled 1 address error disabled 58?61 ? reserved 62 ofu output fifo underflow. rng output fifo has been read while empty. 0 output fifo underflow error enabled 1 output fifo underflow error disabled 63 ? reserved 0 63 field rng eu-go reset 0 r/w w addr rng 0x3_a050 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 17-67 17.4.6 advanced encryption st andard execution unit (aesu) this section contains details about the advanced encryption standard execution unit (aesu), including detailed register map, mode s of operation, status and control register s, and fifos. the registers used in the aesu are documented primarily for debug and slave mode operations. if the sec requires the use of the aesu when acting as an initiato r, accessing these registers directly is unnecessary. the device drivers and the on-chip controller will abstract register level access from the user. 17.4.6.1 aesu mode register (aesumr) the aesu mode register, shown in figure 17-49 , contains 7 bits which are us ed to program the aesu. it also reflects the value of burst size, which is lo aded by the crypto-channel during normal operation with the sec as an initiator. burst size is not relevant to slave mode operations, where an external host pushes and pulls data from the execution units. aesumr is cleared when the aesu is reset or re-ini tialized. setting a reserved mode bit will generate a data error. if aesumr is modified during processing, a context error will be generated. figure 17-49. aesu mode register (aesumr) table 17-15 describes aesumr fields. 0 52 53 55 56 57 58 59606162 63 field ? burst size ecm fm im rdk cm ed reset 0 r/w r/w addr aesu 0x3_4000 table 17-38. aesumr field descriptions bits name description 0?52 ? reserved 53?55 burst size implements flow control to allow larger than fifo-sized blocks of data to be processed with a single key/context. the aesu signals to t he channel that a burst size amount of data is available to be pushed to the fifo. the inclusion of this field in the aesumr is to av oid confusing a user who may read this register in debug mode. burst size should not be written directly to the aesu. 56?57 ecm extend cipher mode: used in combination with cm to define the mode of aes operation. see ta b l e 1 7 - 3 9 for mode bit combinations. 58 fm final mac: processes final message block and generates final mac tag at end of message processing (ccm mode only) 0 do not generate final mac tag. 1 generate final mac tag after ccm processing is complete. 59 im initialize mac: initializes aesu for new message (ccm mode only) 0 do not initialize (context will be loaded by host). 1 initialize new message with nonce. 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 17-68 freescale semiconductor srt is not a new aes mode, it is an aesu method of performing ae s-ctr mode with reduced context loading overhead specifically for pe rforming srtp. it should be used with descriptor type 0010_0 ?srtp?. see figure 17-57 for more information on how srt mo de reduces context loading overhead. 1 srt is not a new aes mode, it is an aesu method of performing aes-ctr mode with reduced context loading overhead specifically for performing srtp. it should be used with descriptor type 0010_0 ?srtp?. see section 17.4.6.9.3, ?context for srt mode? for more information on how srt mode reduces context loading overhead. 60 rdk restore decrypt key: specifies that key data wr ite will contain pre-expanded key (decrypt mode only). see note on use of rdk bit. 0 expand the user key prior to decrypting the first block 1 do not expand the key. the expanded decryption key will be written following the context switch. 61?62 cm cipher mode: used in combination with ec m to define the mode of aesu operation. see table 17-39 for mode bit combinations. 63 ed encrypt/decrypt. if set, aesu operates the encryption algor ithm; if not set, aesu operates the decryption algorithm. 0 perform decryption. 1 perform encryption. note: this bit is ignored if cm is set to ?11??ctr mode. table 17-39. aes cipher modes mode ecm cm ecb 00 00 cbc 00 01 res xx 10 ctr 00 11 srt 1 01 11 ccm 10 00 table 17-38. aesumr field descriptions (continued) bits name description 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 17-69 note restore decrypt key (rdk)?in most networking applications, the decryption of an aes protected pack et will be performed as a single operation. however, if ci rcumstances dictate that the decryption of a message should be split across multiple descriptors, the aesu allows the user to save the decrypt key and the active aes context to memory for later re-use. this saves the internal aesu processing overhead associated with regenerating the decryption key schedul e (~12 aesu clock cycles for the first block of data to be decrypted). the use of rdk is completely optional, as the input time of the preserved decrypt key may exceed the ~12 cycles required to restore the decrypt key for processing the first block. to use rdk, the following procedure is recommended: the descriptor type used in decryption of the first portion of the message is 0100_0- aesu key expand output. the ae su mode must be decrypt. see table 17-6 for more information. the descript or will cause the sec to write the contents of the context register s and the key registers (containing the expanded decrypt key) to memory. to process the remainder of the me ssage, use a common descriptor type (0001_0), and set the restore decrypt key mode bit. load the context registers and the expanded decrypt ke y with previously saved key and context data from the first message. th e key size is written as before (16, 24, or 32 bytes). 17.4.6.2 aesu key size register (aesuksr) the aesu key size register stores the number of bytes in the key (16,24,32). any key data beyond the number of bytes in the key size regist er will be ignored. this register is cleared when the aesu is reset or re-initialized. if a key size other than 16, 24, or 32 bytes is specified, an illegal key size error will be generated. if aesuksr is modified during pr ocessing, a context erro r will be generated. note writing to this register while in debug mode generates an illegal size error. disable the illegal size error in the asso ciated interrupt cont rol register prior to performing debug operations. figure 17-50. aesu key size register (aesuksr) 0 51 52 63 field ? key size reset 0 r/w r/w addr aesu 0x3_4008 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 17-70 freescale semiconductor 17.4.6.3 aesu data size register (aesudsr) this aesu data size register is used to advise the aesu of the size of the data to be processed. depending on the aes mode selected, data size must be divisible by a specific bl ock size or a data size error will occur. in ecb, cbc, and ctr mode, the aesu do es not automatically pad messages out to 128-bit blocks; therefore, when operating in ecb, cbc, or ctr mode, the me ssage processed by the aesu must be divisible by 128 bits or a data si ze error will occur. when operating in ccm mode, data size must be divisible by 8-bits or a da ta size error will occur. in normal operation, the full message length to be encr ypted or decrypted with th e aesu is copied from the descriptor to the aesudsr; how ever only bits 56?63 are checked to de termine if there is a data size error. if bits 57?63 are all ze ros, the message is evenly divisible into 128-bit blocks. this register is cleared when the ae su is reset or re-initi alized. if a data size other than 128 bits is specified, an illegal data size error will be generated. writing to this register signals the aesu to start processing data from the input fifo as soon as it is av ailable. if the value of da ta size is modified during processing, a context error will be generated. note writing to this register while in debug mode generates an illegal size error. disable the illegal size error in the asso ciated interrupt cont rol register prior to performing debug operations. figure 17-51. aesu data size register (aesudsr) 17.4.6.4 aesu reset control register (aesurcr) this register allows three levels of reset of just the aesu, as defi ned by the three self-clearing bits: 0 51 52 63 field ? data size reset 0 r/w r/w addr aesu 0x3_4010 0 60 61 62 63 field ? ri mi sr reset 0 r/w r/w addr aesu 0x3_4018 figure 17-52. aesu reset control register (aesurcr) 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 17-71 table 17-17 describes aesu reset c ontrol register fields. 17.4.6.5 aesu status register (aesusr) the aesu status register is a read -only register that reflects the stat e of six status outputs. writing to aesusr will result in an address error being reflected in the aesuisr. table 17-23 describes aesusr fields. table 17-40. aesurcr field descriptions bits names description 0?60 ? reserved 61 ri reset interrupt. writing this bit active high causes aesu interrupts signaling do ne and error to be reset. it further resets the state of th e aesu interrupt status register. 0 do not reset. 1 reset interrupt logic. 62 mi module initialization. mi is nearly the same as software reset, except that the interrupt control register remains unchanged. this module initialization includes execution of an initialization routine, completion of which is indicated by the reset_done bit in the aesu st atus register 0 do not reset. 1 reset most of aesu. 63 sr software reset is functionally equivalent to hardware reset (the r eset# pin), but only for the aesu. all registers and internal state are re turned to their defined reset state. upon negation of sw_reset, the aesu will enter a routine to perform prop er initialization of t he parameter memories. th e reset_done bit in the aesu status register will indicate when th is initialization routine is complete. 0 do not reset. 1 full aesu reset. 0 3940 4748 555657585960616263 field ? ofl ifl ? halt ? ie id rd reset 0 r/w read only addr aesu 0x3_4028 figure 17-53. aesu status register (aesusr ) table 17-41. aesusr field descriptions bits name description 0?39 ? reserved 40?47 ofl the number of dwords currently in the output fifo 48?55 ifl the number of dwords currently in the input fifo 56?57 ? reserved 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 17-72 freescale semiconductor 17.4.6.6 aesu interrupt status register (aesuisr) the aesu interrupt status register, figure 17-54 , tracks the state of possible er rors, if those errors are not masked, through the aesuicr. table 17-19 describes aesu interr upt register fields. 58 halt indicates that the aesu has halted due to an error. 0 aesu not halted 1 aesu halted note: because the error causing the aesu to stop operating may be mask ed to the interrupt status register, the status register is used to prov ide a second source of information regarding errors preventing normal operation. 59?60 ? reserved 61 ie interrupt error.this status bit re flects the state of the error interrupt signal, as sampled by the controller interrupt status register ( section 17.6.2.2, ?interrupt status register (isr)? ). 0 aesu is not signaling error 1 aesu is signaling error 62 id interrupt done. this status bit re flects the state of the done interrupt signal, as sampled by the controller interrupt status register ( section 17.6.2.2, ?interrupt status register (isr)? ). 0 aesu is not signaling done 1 aesu is signaling done 63 rd reset done. this status bit, when high, indicates t hat aesu has completed its internal reset sequence. 0 reset in progress 1 reset done 0 50 51 525354555657585960616263 field ? ie ere ce kse dse me ae ofe ife ? ifo ofu ? reset 0 r/w read only addr aesu 0x3_4030 figure 17-54. aesu interrupt status register (aesuisr ) table 17-42. aesuisr field descriptions bits name description 0?50 ? reserved 51 ie internal error. an internal processing error was detected while the aesu was processing. 0 no error detected 1 internal error note: this bit will be asserted any time an enabled error condition occurs and can only be cleared by setting the corresponding bit in the interrupt co ntrol register or by resetting the aesu. table 17-41. aesusr field descriptions (continued) bits name description 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 17-73 17.4.6.7 aesu interrupt control register (aesuicr) the aesu interrupt control register, shown in figure 17-55 , controls the result of detected errors. for a given error, as defined in section 17.4.6.6, ?aesu interrupt st atus register (aesuisr),? if the corresponding bit in this register is set, the error is ignored; no error interrupt occurs and aesuisr is not updated to reflect the error. if the corresponding bit is not set, then upon detection of an error, aesuisr 52 ere early read error. the aesu iv regi ster was read while the aesu was processing. 0 no error detected 1 early read error 53 ce context error. an aesu key regi ster, the key size regist er, data size register, mode register, or iv register was modified while aesu was processing 0 no error detected 1 context error 54 kse key size error. an inapp ropriate value (not 16, 24 or 32 bytes) was written to the aesu key size register 0 no error detected 1key size error 55 dse data size error. a value was written to the aesu data size register that is no t a multiple of 128 bits. 0 no error detected 1 data size error 56 me mode error. indicates that invalid data was writ ten to a register or a reserved mode bit was set. 0 valid data 1 reserved or invalid mode selected 57 ae address error. an illegal read or write address was detected within the aesu address space. 0 no error detected 1 address error 58 ofe output fifo error. the aesu output fifo was dete cted non-empty upon write of aesu data size register. 0 no error detected 1 output fifo non-empty error 59 ife input fifo error. the aesu input fifo was detected non-empty upon generation of done interrupt. 0 no error detected 1 input fifo non-empty error 60 ? reserved 61 ifo input fifo overflow. the aesu input fifo has be en pushed while full. 0 no error detected 1 input fifo has overflowed note: when operating as a master, the aesu implements flow-control, and fifo size is not a limit to data input. when operated as a target, the aesu cannot accept fifo inputs larger than 512 bytes without overflowing. 62 ofu output fifo underfl ow. the aesu output fifo has been read while empty. 0 no error detected 1 output fifo has underflow error 63 ? reserved table 17-42. aesuisr field descriptions (continued) bits name description 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 17-74 freescale semiconductor is updated to reflect the error, causing assertion of the error interrupt signal, and causing the module to halt processing. table 17-43 describes the fiel ds of the aesuicr. 0 50 51 525354555657585960616263 field ? ie ere ce kse dse me ae ofe ife ? ifo ofu ? reset 0x0000_0000_0000_1000 r/w r/w addr aesu 0x3_4038 figure 17-55. aesu interrupt control register (aesuicr) table 17-43. aesuicr field descriptions bits name description 0?50 ? reserved 51 ie internal error. an internal processing error was detected while the aesu was processing. 0 internal error enabled 1 internal error disabled 52 ere early read error. the aesu iv regi ster was read while the aesu was processing. 0 early read error enabled 1 early read error disabled 53 ce context error. one of aesukr, the aesuksr, aesudsr, aesumr, or aesu iv register was modified while the aesu was processing. 0 context error enabled 1 context error disabled 54 kse key size error. an inapp ropriate value (non 16, 24 or 32 bytes) was written to the aesu key size register 0 key size error enabled 1 key size error disabled 55 dse data size error. indicates that the nu mber of bits to process is out of range. 0 data size error enabled 1 data size error disabled 56 me mode error. indicates that invalid data was writ ten to a register or a reserved mode bit was set. 0 mode error enabled 1 mode error disabled 57 ae address error. an illegal read or write address was detected within the aesu address space. 1 address error disabled 0 address error enabled 58 ofe output fifo error. the aesu output fifo was de tected non-empty upon write of aesu data size register 0 output fifo non-empty error enabled 1 output fifo non-empty error disabled 59 ife input fifo error. the aesu input fifo was detected non-empty upon generation of done interrupt 0 input fifo non-empty error enabled 1 input fifo non-empty error disabled 60 ? reserved 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 17-75 17.4.6.8 aesu end of message register (aesuemr) the aesu end of messag e register, shown in figure 17-56 , is used to indicate an aes operation may be completed. after the final message block is written to the input fi fo, aesuemr must be written. the value in aesudsr will be used to determine how many bits of th e final message bloc k (always 128) will be processed. writing to aesuemr causes the aesu to process the final block of a message, allowing it to signal done. a read of this register will alwa ys return a zero value. aesuemr is only used when the is operated as a slave. the descriptors and crypt o-channel activate the aesu (through an internally generated write to the end of message register) when the sec acts as an initiator. 17.4.6.9 aesu context registers there are three 64-bit context data registers that allow the host to read /write the contents of the context used to process the message. the cont ext must be written prior to the ke y data. if the context registers are written during message processing, a context error will be generated. all context registers are cleared when a hard/soft reset or initialization is performed. the context registers must be read when changing context and restored to their original values to resume processing an interrupted message (cbc, ctr a nd ccm modes). for ctr and ccm mode, all seven 64-bit context registers must be read to retrieve cont ext, and all seven must be written back to restore context. effectively, the user must read the four empty plac e holder context registers in addition to the three context registers holding the counter and counter modulus when in ctr mode. the contents of the empty context registers need not be pres erved, but when restoring the ctr mo de context, the empty registers must be filled with 32 bytes of zeros before writing th e saved counter and counter modulus. context should be loaded with the lower bytes in th e lowest 64-bit context register. the context registers are summarized in figure 17-57 . 61 ifo input fifo overflow. the aesu input fifo has be en pushed while full. 0 input fifo overflow error enabled 1 input fifo overflow error disabled 62 ofu output fifo underflow the aesu output fifo has been read while empty. 0 output fifo underflow error enabled 1 output fifo underflow error disabled 63 ? reserved 0 63 field aesu end of message reset 0 r/w w addr aesu 0x3_4050 figure 17-56. aesu end of message register table 17-43. aesuicr field descriptions (continued) bits name description 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 17-76 freescale semiconductor 1 must be written at the start of a new message. 2 must be written at start of new ccm decryption. 3 header size/mac size is only used if aes-ccm processing is suspended and resumed. figure 17-57. aesu context registers 17.4.6.9.1 context for cbc mode within the context register, for use in cbc mode, are two 64-bit context data registers th at allow the host to read/write the contents of the initialization vector (iv): ? iv1 holds the least significant bytes of the initialization vector (bytes 1?8). ? iv2 holds the most significant bytes of the initialization vector (bytes 9?16). the iv must be written prior to th e message data. if the iv registers are written du ring message processing, or the cbc mode bit is not set, a context error will be generated. the iv registers may only be read af ter processing has completed, as indi cated by the assertion of interrupt done done in the aesu stat us register as shown in section 17.4.6.5, ?aesu status register (aesusr).? if the iv registers are read pr ior to assertion of interrupt done , an early read error will be generated. the iv registers must be read when changing contex t and restored to resume processing an interrupted message (cbc mode only). 17.4.6.9.2 context for counter mode in counter mode, a random 128-bit initial counter value is incremented modulo 2 n with each block processed. the modulus si ze can be set between 2 8 through 2 128 , by powers of 8. th e running counter is encrypted and xored with the plaintext to derive the ciphertext, or with the ci phertext to recover the plaintext. in ctr mode, the block count er is incremented modulo 2 m . the value of m is specified by writing to context register 3 as described in table 17-44 context register (64 bits each) cipher mode 12 3 456 7 ecb?? ? ??? ? cbc iv1 1 iv2 1 ? ??? ? ctr????counter 1 counter modulus 1 srt counter 1 counter modulus 1 ??? ? ccm iv 1 / mac tag encrypted mac 2 /decrypted mac/encrypted counter counter 1 counter modulus 1,3 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 17-77 17.4.6.9.3 context for srt mode as was noted in the aesu mode register, srt is not a new aes mode, it is an aesu method of performing aes-ctr mode with redu ced context loading overhead speci fically for performing srtp. it should be used with descriptor type 0010_0 srtp. as with counter mode, a random 128-bit initial counter value is incremented modulo 2 n with each block processed. the m odulus size can be set between 2 8 through 2 128 , by powers of 8. the running counter is encrypted and exclusive-ored wi th the plaintext to derive the ciphertext, or with the ciphertext to recover the plaintext. the block counter is incremented modulo 2 m . the value of m is specified by writing to context register 3 as described in table 17-44 . the only difference between srt mode and ctr mode is in srt mode, the aes context is loaded and read through context registers 1?3, with no requireme nt to access context registers 4?7. in ctr mode, context registers 1?4 must be loaded with zeros, with the counter and mo dulus being loaded into and read from context registers 5?7. 17.4.6.9.4 context for ccm mode the sec aesu is capable of perf orming single pass encryption and ma c generation. the host is required to order the ccm context is such a way that the c ontext can be fetched as a contiguous string into the context registers, prior to en cryption/mac generation or decrypt ion/mac validation. a complete explanation of the cont ext and ordering follows. table 17-44. counter modulus value written modulus 82 8 16 2 16 24 2 24 32 2 32 40 2 40 48 2 48 56 2 56 64 2 64 72 2 72 80 2 80 88 2 88 96 2 96 104 2 104 112 2 112 120 2 120 128 2 128 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 17-78 freescale semiconductor the context for ccm encr yption/mac generation is: ? reg 1?2 session specific128 bit init ialization vector (from memory) ? reg 3?4 128 bits of zero padding ? reg 5?6 session specific counter (ini tial counter value) (from memory) ? reg 7 counter modulus should be fixed at 0x0000_0080. note the counter modulus for ccm mode is currently defined as 2 128 . this value has been made programmable in the se c in case the final version of the 802.11i standard uses a different c ounter modulus. because this is a programmable field, it must be gene rated and stored along with other session specific information for loadi ng into the aesu context register prior to ccm encryption. ccm encryption processing with the session specific key and context, th e aesu will perform the following operations. 1. initialize the iv, and encrypt with the symmetric key. 2. in cbc fashion, take the output of step 1, hash wi th the first block of plaintext, and encrypt with the symmetric key. 3. continue as in step 2 until th e final block of plaintext has be en processed. the result of the encryption of the final block of plaintext with the symmetric key is the mac tag. the full 128bits of mac data is written to c ontext registers 1?2, for use in th e next phase of ccm processing. once the mac tag has been genera ted (step 3), the mac tag, along wi th the plaintext is encrypted with the aesu operating in counter mode. 4. the first item to be encrypted in counter mode is the counter (initial count er value) from context registers 5?6. the counter is encrypted with the symm etric key, and the result is hashed with the mac tag (retrieved from context reg 1?2) to produce the encrypted ma c, which is then stored in context registers 3?4. at the completion of ccm en crypt processing, this en crypted mac is output to memory (per the descriptor pointer) for the hos t to append to the 802.11i standard frame. note that the encrypted mac written out to memory by the aesu is the full 128-bits. the host must only append the most significant 64-bits to the frame as the encrypted mac. 5. the counter value is incremented, and is then encr ypted with the symmetric key. the result is then hashed with the first block of plaintext to produce the first block of cipher text. the ciphertext is placed in the aesu output fifo. 6. the counter continues to be incremented, and encr ypted with the symmetric key, with the result hashed with each successive block of plaintext, until al l plaintext has been co nverted to ciphertext. the sec controller will manage fifo reads and writes, fetching plaintext and writing ciphertext per the pointers provided in the de scriptor. when all ciphertext a nd the encrypted mac have been output, the ccm encrypt operation is complete. the context for ccm decr yption/mac generation is: ? reg 1?2 session specific128 bit init ialization vector (from memory) ? reg 3?4 encrypted mac (from received frame) + 64 bits of zero padding 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 17-79 ? reg 5?6 session specific counter (ini tial counter value) (from memory) ? reg 7 counter modulus should be fixed at 0x0000_0080. note the counter modulus for ccm mode is currently defined as 2 128 . this value has been made programmable in the sec to in case the final version of the 802.11i standard uses a different c ounter modulus. because this is a programmable field, it must be gene rated and stored along with other session specific information for loadi ng into the aesu context register prior to ccm decryption. ccm decryption processing the reverse of encryption. with the session specific ke y and context, the aesu wi ll perform the following operations. 1. initialize the iv, and encrypt wi th the symmetric key. simultaneous ly, the counter (initial counter value) from context registers 5?6 is encrypted with the symmetric key. the result is hashed with the encrypted mac (from context register 3-4), and the resulting original mac is written to context reg 3?4, overwriti ng the encrypted mac. note strictly speaking, the counter is en crypted with the symmetric key; however, the aesu should be set for decrypt to perform the counter and cbc processes in the correct order. 2. the 802.11 standard frame header is hashed wi th the encrypted iv. (the aesu automatically determines the header length.) simultaneously, th e counter is incremented, and is then encrypted with the symmetric key. the result is then hashed with the first block of ciphertext to produce the first block of plaintext. the plai ntext is placed in the aesu output fifo, while simultaneously, in cbc fashion, a copy of the first block of plaintext is hashed with the output of encryption of the 802.11 standard frame header. the output is encrypted with the symmetric key. 3. as each ciphertext block is convert ed to plaintext, the plaintext is cbc encrypted. when the final plaintext block has been processe d, the cbc mac (mac tag) is written to context registers 1?2. the first 64 bits of the mac tag are compar ed to the mac tag recovered in step 1. note for both encrypt and decrypt operations , if the 802.11 standard frame is being processed as a whole (not spli t across multiple descriptors), the initialize and final mac bits should be set in the aesu mode register. 17.4.6.9.5 aesu key registers the aesu key registers hold from 16, 24, or 32 bytes of ke y data, with the first 8 byt es of key data written to key 1. any key data written to bytes beyond the valu e written to the key size register will be ignored. the key data registers are cleared wh en the aesu is reset or re-initiali zed. if these registers are modified during message processing, a cont ext error will be generated. 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 17-80 freescale semiconductor the key data registers may be read when changing context in decrypt mode. to resume processing, the value read must be written back to the key registers and the restore decrypt key bit must be set in the mode register. this eliminates the overh ead of expanding the key prior to starting decr yption when switching context. 17.4.6.9.6 aesu fifos the aesu fetches data 128 bits at a time from the input fifo. during pro cessing, the input data is encrypted or decrypted with the key and initialization vector (cbc mode only) and the results are placed in the output fifo. the output size is the same as the input size. writing to the fifo address space pl aces 64 bits of message data into the input fifo. the input fifo may be written any time the ifw signal is asserted (as indicated in the aesu st atus register). th is will indicate that the number of bytes of available space is at or above th e threshold specified in the mode register. there is no limit on the total num ber of bytes in a message. the number of bits in the final message block must be set in the data size register. reading from the fifo address spac e will pop 64 bits of message data from the output fifo. the output fifo may be read any time the ofr si gnal is asserted (as indicated in th e aesu status regi ster). this will indicate that the number of bytes in the output fifo is at or above the threshold specified in the mode register. 17.5 crypto-channels a channel in the sec manages the execution of each cryptographic task, making use of one or more of the sec?s execution units (eus). control information and da ta pointers for a given task are stored in the form of a descriptor (see section 17.3.1, ?descriptor structure? ) in system memory or in the channel itself. a descriptor determines what eus will be used, how they will be configured, where to fetch needed data, and where to store the results. to invoke cryptographic task s, the host constructs a desc riptor, selects a channel, and writes a pointer to th e descriptor into the selected channel? s fetch fifo. operat ions performed by channels include the following (not necessarily in this order): ? if the channel is idle an d its fetch fifo is non-empt y, read the next descript or pointer from the fetch fifo, and use this pointer to read the desc riptor into the channel?s descriptor buffer. ? request from the controller the assignment of one or more eus for the exclusive use of the channel. where necessary, configure the secondary eu to snoop input or output data intended for the primary eu. ? upon notification of completion of the eu reset sequence, initialize mode registers in the assigned eu. ? initialize eus and write to eu registers such as ke y size and text-data size. ? transfer data parcels ( up to 32 kbytes) from system memory into assigned eu i nput registers and fifos. this may involve using link tables to gather input data that has been split into multiple segments which are stored in vari ous locations of system memory. ? transfer data parcels (up to 32 kbytes) from assigned eu output registers and fifos to system memory space. this may involve using link tables to s catter output data into multiple segments which are stored in various locations of system memory. 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 17-81 ? initialize the eu-go register (w here applicable) in the assigne d eu upon completion of last eu write indicated by the descriptor. th e channel will wait for a indica tion from the eu that processing of input text-data is complete before procee ding with further acti vity after writing eu-go. ? reset assigned eu(s). ? release assigned eu(s). ? when a descriptor has been completely processed, provide feedback to the host, in the form of interrupt and/or descriptor header write-back to system memory. ? when descriptor processing is halted due to an error, provi de feedback to the host through interrupt. the channel will wait indefi nitely for the controller to complete a requested activity before continuing to the next step of descriptor processing. 17.5.1 crypto-channel registers crypto-channel registers are descri bed in the following sections. 17.5.1.1 crypto-channel conf iguration register (cccr) this register contains five opera tional bits permitting co nfiguration of the crypto-channel as shown in figure 17-58 . table 17-45 describes the cccr. 0 29 30 31 field ? con r reset 0 r/w r/w addr channel_1 0x1108, channel_2 0x1208, channel_3 0x1308, channel_4 0x1408 32 54 55 56 58 59 60 61 62 63 field ? bs ? cdwe nt cdie reset 0 r/w r/w addr channel_1 0x3_110c, channel_2 0x3_120c, channel_3 0x3_130c, channel_4 0x3_140c figure 17-58. crypto -channel config uration register (cccr) table 17-45. cccr field descriptions bits name description 0?29 ? reserved, set to zero 30 con continue bit 0 no special action. 1 causes the same channel reset actions as bit r, exc ept that the fetch fifo and the lower half of the ccr register are not cleared. after the reset sequence is complete, this bit automatically returns to 0 and the channel resumes normal operation, servicing the next descriptor pointer in the fetch fifo, if any. 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 17-82 freescale semiconductor 31 r reset channel 0 no special action. 1 causes a software reset of the channel, clearing all its internal state. the details of the software reset actions depend upon what the channel is doing when the bit is set: if the r bit is set while the channel is requesting an eu assignment from the c ontroller, the channel cancels its request by asserting the release output signals. t he channel then resets all its registers, clears the r bit, and return the channel state machine to the idle state. if the r bit is set after the channel has been assigned an eu, the channel requests a write from the controller to set the software reset bit of the eu. if a secondary eu has been reserved, the channel requests a write to reset that eu as well. the channel next asserts the appr opriate release signal to notify the controller that the channel has finished with the reserved eu(s). the channel then resets all the registers, clears the reset bit and returns the channel state machine to the idle state. 32?54 ? reserved, set to zero 55 bs burst size. the sec accesses long text-data parcels in main memory through bursts of programmable size: 0 burst size is 64 bytes 1 burst size is 128 bytes 56-58 ? reserved, set to zero 59 cdwe channel done writeback enable: 0 channel done writeback disabled. 1 channel done writeback enabled. upon completion of descr iptor processing, if the nt bit is set for global, or if the dn (done notification) bit is set in the head er word of the descriptor, then notify the host by writing back the descriptor header with 0xff in bits 0-7. this enables the host to poll the memory location of the original descriptor header to determine if that descriptor has been completed. 60 ? reserved, set to zero 61 nt notification type. channel done notification type. th is bit controls when the crypto-channel will generate channel done notification. channel do ne notification can take the form of an interrupt or modified header writeback or both, depending on the st ate of the cdie and we control bits. 0 global: the crypto-channel will generate channel done notification (if enabled) at the end of each descriptor. 1 done bit: the crypto-channel will generate channel done notification (if enabled) at the end of every descriptor with the done bit set in the descriptor header. 62 cdie channel done interrupt enable 0 channel done interrupt disabled 1 channel done interrupt enabled. upon completion of descriptor processing, if the nt bit is set for global, or if the dn (done notif ication) bit is set in the header word of the descriptor, then notify the host by asserting an interrupt. refer to section 17.5.2, ?interrupts,? for complete description of channel interrupt operation. 63 ? reserved, set to zero table 17-45. cccr field descriptions (continued) bits name description 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 17-83 17.5.1.2 crypto-channel pointer status register (ccpsr) this register contains stat us fields and counters whic h provide the user with st atus information regarding the channel?s actual processing of a given descriptor. table 17-46 describes the crypto-channel poi nter status register fields. 0 2 3 7 8 1112 15 1619 20 2324 31 field ? ff_counter ? g_state ? s_state chn_state reset 0 r/w read only addr channel_1 0x3_01110, channel_2 0x3_01210, channel_3 0x3_01310, channel_4 0x3_01410 32 37 38 39 40 41 42 43 44 45 46 47 48 59 60 63 field mi mo pr sr pg sg prd srd pd sd error pair_ptr reset 0x0000 _0007 r/w read only addr channel_1 0x3_01114, channel_2 0x3_01214, channel_3 0x3_01314, channel_4 0x3_01414 figure 17-59. crypto-channel pointer status register (ccpsr ) table 17-46. ccpsr field descriptions bits name description 0?2 ? reserved. 3?7 ff_counter fetch fifo counter . the fetch fifo can store up to 24 pointers to de scriptors in system memory. this 5-bit counter indicates how many fetch pointers are currently stored in the fifo. 8?11 ? reserved. 12?15 g_state gather state machin e state. reflects the state of the cryp to-channel gather control state machine. the value of this field indicates which stage the crypto-channel is in while performing gather function. ta b l e 1 7 - 4 7 lists all possible values of the g_state field. note: g_state is documented for information only. th e user will not typically care about the gather state machine. 16?19 ? reserved. 20?23 s_state scatter state machi ne state. reflects the stat e of the crypto-channel scatter control state machine. the value of this field indicates which stage the cr ypto-channel is while performing scatter function. ta b l e 1 7 - 4 8 lists all possible values of the s_state field. note: s_state is documented for information only. the user will not typically care about the scatter state machine. 24?32 chn_state crypto-channel state machine state. reflects the state of the crypto-chan nel control state machine. the value of this field indicates exactly which stage the crypto-channel is in the sequence of fetching and processing data descriptors. table 17-49 lists all possible values of the chn_state field. note: chn_state is documented for information only. the user will not typically care about the crypto-channel state machine. 31?37 ? reserved, set to zero 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 17-84 freescale semiconductor 38 mi multi_eu_in. the multi_eu_in bit reflects t he type of snooping the channel will perform, as programmed by the ?snoop type? bit in the descriptor header. 0 data input snooping by secondary eu disabled 1 data input snooping by secondary eu enabled 39 mo multi_eu_out. the multi_eu_out bit reflects t he type of snooping the channel will perform, as programmed by the ?snoop type? bit in the descriptor header. 0 data output snooping by secondary eu disabled 1 data output snooping by secondary eu enabled 40 pr pri_req. request primary eu assignment. 0 primary eu assignment request is inactive. 1 the crypto-channel is requesting assignment of primary eu to the channel. the channel will assert the eu request signal indicated by the op_0 field in the descriptor header register as long as this bit remains set. the pri_req bit is set when descriptor processing is initiated in dynamic mode and the op_0 field in the descriptor header cont ains a valid eu identifier. this bit is cleared when the request is granted, which will be reflected in the status register by the setting the pri_grant bit. 41 sr sec_req. request secondary eu assignment. 0 secondary eu assignment request is inactive. 1 the crypto-channel is requesting assignment of secondary eu to the channel. the channel will assert the eu request signal indicated by the op_1 field in the descriptor header register as long as this bit remains set. the sec_req bit is set when descriptor processing is initiated in dynamic mode and the op_1 field in the descriptor header cont ains a valid eu identifier. this bit is cleared when the request is granted, which will be reflected in the status r egister by the setting the sec_grant bit. 42 pg primary eu granted. reflects t he state of the eu grant signal for the requested primary eu from the controller. 0 the primary eu grant signal is inactive. 1 the eu grant signal is active, indicating the controller has assigned the requested primary eu to the channel. 43 sg secondary eu granted. reflects the state of th e eu grant signal for the requested secondary eu from the controller. 0 the secondary eu grant signal is inactive. 1 the eu grant signal is active, indicating the controller has assigned the requested secondary eu to the channel. 44 prd primary eu reset done. reflects the state of the reset done signal from the assigned primary eu. 0 the assigned primary eu reset done signal is inactive. 1 the assigned primary eu reset done signal is active, indicating its reset sequence has completed and it is ready to accept data. 45 srd secondary eu reset done. reflects the state of the reset done signal from the assigned secondary eu. 0 the assigned secondary eu reset done signal is inactive. 1 the assigned secondary eu reset done signal is active, indicating its reset sequence has completed and it is ready to accept data. 46 pd primary eu done. the pri_done bit reflects the state of the done interrupt from the assigned primary eu. 0 the assigned primary eu done interrupt is inactive. 1 the assigned primary eu done interrupt is active indicating the eu has completed processing and is ready to provide output data. table 17-46. ccpsr field descriptions (continued) bits name description 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 17-85 table 17-49 shows the values of the gather state machine. 47 sd secondary eu done. reflects the state of th e done interrupt from the assigned secondary eu. 0 the assigned secondary eu done interrupt is inactive. 1 the assigned secondary eu done interrupt is active indicating the eu has completed processing and is ready to provide output data. 48?59 error crypto-channel error status. reflects the error status of the crypto-channel. when a channel error interrupt is generated, this field w ill reflect the source of the error. the bits in the error field are registered at specific stages in the descriptor processing flow. once registered, an error can only be cleared only by resetting the crypto-channel or writing the appropriate registers to initiate the processing of a new descriptor. ta b l e 1 7 - 5 0 lists the conditions which can cause a crypto-channel error and how they are represented in the error field. 60?63 pair_ptr descriptor buffer register length/pointer pair. this field indicates which of the length/pointer pairs are currently being processed by the channel. table 17-51 shows the meaning of all possible values of the pair_ptr field. table 17-47. g_state field values value gather state machine 0x0 idle 0x1 load_4pointers_frm_gather_table 0x2 load_4pointers_frm_gather_table_done 0x3 next_bit_set_load_next_gather_table 0x4 process_gather_pointer 0x5 request_block_data_trans 0x6 request_block_data_trans_done 0x7 request_bytes_data_trans 0x8 request_bytes_data_trans_done 0x9 increase_table_pointer 0xa update_gather_pointer 0xb gather_table_done 0xc gather_error 0xd load_next_4pointers_frm_gather_table 0xe-f reserved table 17-46. ccpsr field descriptions (continued) bits name description 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 17-86 freescale semiconductor table 17-49 shows the values of the scatter state machine. table 17-49 shows the values of crypto-channel states. table 17-48. s_state field values value scatter state machine 0x0 idle 0x1 load_4pointers_frm_scatter_table 0x2 load_4pointers_frm_scatter_table_done 0x3 next_bit_set_load_next_scatter_table 0x4 process_scatter_pointer 0x5 request_block_data_trans 0x6 request_block_data_trans_done 0x7 request_bytes_data_trans 0x8 request_bytes_data_trans_done 0x9 increase_table_pointer 0xa update_scatter_pointer 0xb scatter_table_done 0xc scatter_error 0xd load_next_4pointers_frm_scatter_table 0xe-f reserved table 17-49. chn_state field values value crypto-channel state 0x00 idle 0x01 process_header 0x02 fetch_descriptor 0x03 channel_done 0x04 channel_done_irq 0x05 channel_done_writeback 0x06 channel_done_notification 0x07 channel_error 0x08 request_pri_eu 0x09 inc_data_pair_pointer 0x0a delay_data_pair_update 0x0b evaluate_data_pairs 0x0c write_reset_pri 0x0d release_pri_eu 0x0e write_reset_sec 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 17-87 0x0f release_sec_eu 0x10 process_data_pairs 0x11 write_mode_pri 0x12 write_mode_sec 0x13 write_datasize_pri 0x14 delay_rng_done 0x15 write_datasize_sec_multi_eu_in 0x16 trans_request_read_multi_eu_in 0x17 delay_pri_sec_done 0x18 trans_request_read 0x19 write_key_size 0x1a write_eu-go 0x1b delay_pri_done 0x1c write_reset_irq_pri 0x1d write_reset_irq_sec 0x1e write_datasize_sec_snoopout 0x1f trans_request_write_snoopout 0x20 delay_sec_done 0x21 trans_request_write 0x22 evaluate_reset 0x23 reset_write_reset_pri 0x24 reset_release_pri_eu 0x25 reset_write_reset_sec 0x26 reset_release_sec_eu 0x27 reset_channel 0x28 write_datasize_pri_post 0x29 reset_release_all 0x2a reset_release_all_delay 0x2b request_sec_eu 0x2c write_datasize_sec 0x2d write_pri_eu-go_multi_eu_out 0x2e write_sec_eu-go_multi_eu_out 0x2f write_pri_eu-go_multi_eu_in 0x30 write_sec_eu-go_multi_eu_in 0x31 write_datasize_pri_delay 0x32 wait_afeu_done 0x33 trans_extend_write table 17-49. chn_state field values (continued) value crypto-channel state 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 17-88 freescale semiconductor table 17-50 shows the bit positions of each potenti al error. multiple errors are possible. note eu error bit (error[0]) can only be cleared by first clearing the error source in the assigned eu which caused it to be set. 0x34 trans_extend_a 0x35 trans_extend_b 0x36- 0xff reserved table 17-50. ccpsr error field definitions value error 48 dof. double fetch fifo write overflow error.this bit is se t when the crypto-channel fetch fifo is full, sof is set, and another write has been made to the fetch fifo. when this bit is set the crypto-channel will stop, and an error interrupt will be activated. the channel will not start again until a continue or reset is given through the cccr register. this bit can be cleared by writing ?1? to this bit in the ccpsr register. 49 sof. single fetch fifo write overflow error. this bit is set when the channel fetch fifo is full and another write has been made to the fetch fifo. the crypto-channel will set this bit and activate an error interrupt. the crypto-channel continues processing, but the descriptor point er is lost. the host must clear this bit by writing ?1? to this bit in the ccpsr register. 50 mdte. a master data transfer error was received from the master bus interface. when the sec, while acting as a bus master, detects an error, the controller passes the error to the channel in use. the channel halts and activates an interrupt. the channel can only be restarted by writing a ?1? to the continue or reset bit in the crypto-channel configuration register, or resetting the whole sec. 51 scatter/gather data length zero error. a zero length scatter/gather da ta pointer was detected. 52 fetch pointer zero error. an all zero fetch pointer was detected. 53 illegal descriptor header. possible causes of an illegal descriptor header are: ? invalid primary eu indicated by op_0 field in descriptor header. ? invalid secondary eu indicated by op_1 field in descriptor header. ? descriptor type field in descriptor header indicates secondary eu transaction when not in snoop mode 54 invalid eu assignment request. indicates the channel has been assigned one or more eus not requested by the descriptor header. 55 eu error detected. an eu assigned to this channel has generated an error interrupt. this error may also be reflected in the controller's interrupt status register. 56 gather boundary error. indicates a gather pointer straddles both a primary and secondary eu?s data transfer. 57 gather return/length error. indicates the total data size cove red by a gather link table did not match the total data size from the main descriptor. 58 scatter boundary error. indicates a scatter pointer stra ddles both a primary and secondary eu?s data transfer. 59 scatter return/length error. indicates the total data size co vered by a scatter link table did not match the total data size from the main descriptor. table 17-49. chn_state field values (continued) value crypto-channel state 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 17-89 table 17-51 shows the possible values of the ptr_dw field in the ccpsr. 17.5.1.3 crypto-channel current de scriptor pointer register (cdpr) the cdpr, shown in figure 17-60 , contains the address of the desc riptor which the crypto-channel is currently processing. this register, along with the pair_ptr in the ccpsr , can be used to determine if a new descriptor can be safely inse rted into a chain of descriptors. figure 17-60. crypto-channel current descriptor pointer register (cdpr ) the fields in cdpr perform the functions described in table 17-52 . table 17-51. channel pointer status register ptr_dw field values value error 0x00 processing header or pointer dword 0 0x01 processing pointer dword 1 0x02 processing pointer dword 2 0x03 processing pointer dword 3 0x04 processing pointer dword 4 0x05 processing pointer dword 5 0x06 processing pointer dword 6 0x07 complete (or not yet begun) processing of header dword and pointer dwords 0x08-ff reserved 0313263 field ? cur_des_ptr_adrs reset 0x0000_0000 r/w read only addr channel_1 0x3_1140, channel_2 0x3_1240, channel_3 0x3_1340, channel_4 0x3_1440 table 17-52. cdpr field descriptions bits name description 0?31 ? reserved ? set to zero. 32?63 cur_des_ptr_adrs current descriptor pointer address. pointer to system memory location of the current descriptor. reflects the star ting location in system memory of the descriptor currently loaded into the db. this value is updated whenever the channel requests a fetch of a descriptor from the controller. the value from the fetch fifo is transferr ed to the current descriptor pointer register immediately after the fetch is completed. this address will be used as the destination of the writeback of the modified header dword, if header writeback not ification is enabled. 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 17-90 freescale semiconductor 17.5.1.4 fetch fifo (ff) each channel contains a fetch fifo to store a queu e of pointers to descriptor s which the channel will process. the fetch fifo, displayed in figure 17-61 , contains the addresses of the first byte of descriptors to be processed. in typical operation, the host cpu will create a descriptor in memory containing all relevant mode and location information for the sec, then ?launch? th e sec by writing the addr ess of the descriptor to the fetch fifo. the fetch address is written into th e fifo only if the write includes the least significa nt byte (bits 56?63). writing a fetch address of zero to the fetch fifo causes the channel to generate an error and to stop. the fetch fifo can hold up to 24 descriptor pointers at a time. when the end of the current descriptor is reached, the descriptor pointed to by the next location in the fetch fifo will be read to launch the next descriptor. writing a descript or pointer to the fetch fifo while the fifo is full will result in a single overflow interrupt to advise the user that the descript or pointer was not successfully written to the fetch fifo. the channel will continue processing and software can check the fetch fifo counter in the crypto-channel pointer status register before attempting to re-enqueue th e descriptor pointer. if a second descriptor pointer is written to th e fetch fifo before the single the si ngle overflow error is cleared, the channel will generate a double overf low error interrupt and stop proces sing descriptors. the channel can be restarted by setting the continue bit in the crypto- channel configuration regist er, or completely reset by writing the reset bit in the same register. figure 17-61. fetch fifo table 17-53 describes the fetch fifo fields. 17.5.1.5 descriptor buffer (db) the descriptor buffer (db) consists of 8 dword registers (db0?db7), a nd contains the current descriptor being processed by the channe l. these registers are read-only, since the descriptor is always fetched from system memory. for more information about the fields in a descriptor, see section 17.3.1, ?descriptor structure.? 0313263 field ? fetch_adrs reset 0x0000_0000 r/w w addr channel_1 0x3_01148, channel_2 0x3_01248, channel_3 0x3_01348, channel_4 0x3_01448 table 17-53. fetch fifo field descriptions bits name description 0?31 ? reserved. set to zero. 32?63 fetch adrs fetch address. pointer to system memory location of a descriptor the host wants the sec to fetch. 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 17-91 figure 17-62. data packet descriptor buffer 17.5.2 interrupts the crypto-channel can assert both done and error in terrupts to the controller. when the interrupt generation conditions have be en met, the crypto-channel will assert the appropriate interrupt. the status of the registered crypto-channel inte rrupts are available in the controll er interrupt status register. the registered interrupts can cleared by writing to the controller interrupt clear register. the crypto-channel does not have an internal interrupt mask bit and error interrupts are alwa ys asserted to th e controller. the controller can be programmed to ma sk channel interrupts to the host through its interrupt mask register (imr). see section 17.6.2.1, ?interrupt mask register (imr).? 17.5.2.1 channel done interrupt whether and when a channel done interrupt is gene rated depends on the setting of the crypto-channel configuration register nt and cdie bits in the cccr (see figure 17-58 ). assuming cdie (channel done interrupt enable) is set, the channel will generate an interrupt after every successf ully completed descriptor (notification type set to global), or after each successfully comple ted descriptor with the dn (done notification) bit set in the header word of the descriptor. the controller will queue multiple channel done interrupts if an interrupt is not cleared before the next channel done interrupt is issued. if th ere are multiple interrupts, the cont roller will re-assert the channel done interrupt one cycle after the previ ous channel done interrupt is cleared. 17.5.2.2 channel error interrupt the channel error interrupt is gene rated when an error condition occurs during descriptor processing. the channel error interrupt will be as serted as soon as the error conditi on is detected. the type of error condition is reflected the error fi eld of the channel pointer stat us register (cpsr). refer to table 17-50 for a complete listing of error types. 0 15 16 17 2324 3132 63 db0 header reserved db1 length0 j1 extent0 - pointer0 db2 length1 j2 extent1 - pointer1 db3 length2 j3 extent2 - pointer2 db4 length3 j4 extent3 - pointer3 db5 length4 j5 extent4 - pointer4 db6 length5 j6 extent5 - pointer5 db7 length6 j7 extent6 - pointer6 address channel_1 0x3_1180-0x3_11bf, channel_2 0x3_1280-0x3_12bf, channel_3 0x3_1380-0x3_13bf, channel_4 0x3_1480-0x3_14bf 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 17-92 freescale semiconductor 17.5.2.3 channel reset channel reset is asserted when the host sets the r (r eset) bit in the crypto-cha nnel configuration register (cccr). the effect of software reset on the channel varies according to what the channel is doing when the bit is set: ? if the r bit is set while the crypto-channel is re questing a eu assignment fr om the controller, the crypto-channel will cancel its request by asserting the release output signals. the crypto-channel will then reset all the re gisters, clear the r bit and return the control state machine to the idle state. ? if the r bit is set after the crypto-channel has been dynamically assigned a eu, the channel will request a write from the controller to set the so ftware reset bit of the eu. a write to reset the secondary (mdeu) eu will also be requested if one has been reserved for snooping. the crypto-channel will then assert th e appropriate release output signal to notify the controller that the channel has finished with the reserved eu(s). the crypto-channel will then reset all the registers, clear the r bit and return the contro l state machine to the idle state. 17.6 sec controller the sec controller is responsible for overseeing the operations of the execution units (eus), the interface to the host processor, and the management of the cr ypto-channels. the controller interfaces to the host through the master/slave bus interface and to the ch annels and eus through inte rnal buses. all transfers between the host and the eus are moderated by the controll er. some of the main functions of the controller are as follows: ? arbitrate and control accesses to the bus ? control the internal bus accesses to the eus ? arbitrate and assign eus to the crypto-channels ? monitor interrupts from channels and pass to host ? realign read and write data to the proper byte alignment 17.6.1 controller registers the controller registers are described in detail in the following sections. 17.6.2 eu assignment status register (euasr) the euasr, displayed in figure 17-63 , is used to check the assignment st atus of an eu to a particular channel. when an eu is already assigned, it is inaccessible to any other channel. 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 17-93 a four-bit field (see table 17-54 ) indicates the channel to which an eu is assigned. table 17-54 shows the eu channel assignments. 17.6.2.1 interrupt mask register (imr) the sec controller generates the single interrupt output from all possi ble interrupt source s. these sources can be masked by the interrupt ma sk register. if unmasked, the interr upt source value, when active, is captured into the inte rrupt status register. figure 17-64 shows the bit positions of each potential interrupt source. each interrupt source is i ndividually unmasked by setting its corr esponding bit. at reset, all bits are masked. the bit fields are described in table 17-55 . 034781112151619202324272831 field ? afeu ? mdeu ? aesu ? deu reset 0xf 0x0 0xf 0x0 0xf 0x0 0xf 0x0 r/w read only addr 0x3_1028 32 35 36 39 40 43 44 47 48 51 52 55 56 59 60 63 field ? ? pkeu ? rng reset 0x00ff 0xf 0x0 0xf 0x0 r/w read only addr 0x3_102c figure 17-63. eu assignment status register (euasr) table 17-54. channel assignment value value channel 0x0 no channel assigned 0x1 channel 1 0x2 channel 2 0x3 channel 3 0x4 channel 4 0xa?0xe undefined 0xf unavailable 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 17-94 freescale semiconductor 17.6.2.2 interrupt status register (isr) the isr contains fields re presenting all possible sources of interrupts. the interrupt status register is cleared either by a reset, or by wr iting the appropriate bits active in the interrupt clear register. figure 17-65 shows the bit positions of each potential inte rrupt source. the bit fi elds are described in table 17-55 . 0 14 15 field ? ito definition reset 0x0000 r/w r/w addr 0x3_1008 16 19 20 21 22 23 24 25 26 27 28 29 30 31 field ? done overflow chn_4 chn_3 chn_2 chn_1 definition 4 3 2 1 err dn err dn err dn err dn reset 0x0000 r/w r/w addr 0x3_1008 32 39 40 41 42 43 44 45 46 47 field ? pkeu ? rng ? definition err dn err reset 0x0000 r/w r/w addr 0x3_100c 48 49 50 51 52 53 54 55 56 57 58 63 field ? afeu ? mdeu ? aesu ? deu definition err dn err dn err dn err dn reset 0x0000 r/w r/w addr 0x3_100c figure 17-64. interrupt mask register (imr) 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 17-95 17.6.2.3 interrupt clear register (icr) the interrupt control register provide s a means of clearing the interrupt st atus register. when a bit in the icr is written with a 1, the corresponding bit in the isr is cleared, clearing th e interrupt output pin irq (assuming the cleared bit in the isr is the only interr upt source). if the input source to the isr is a steady-state signal that remains active, the appropriate isr bit, and subsequently irq , will be reasserted shortly thereafter. figure 17-66 shows the bit positions of each interr upt source that can be cleared by this register. the complete bit defini tions for the icr can be found in figure 17-66 . the bit fields are described in table 17-55 . when an icr bit is written, it will automatically clear itself one cycle later. that is, it is not necessary to write a 0 to a bit position whic h has been written with a 1. 0 14 15 field ? ito definition reset 0x0000 r/w read only addr 0x3_1010 16 19 20 21 22 23 24 25 26 27 28 29 30 31 field ? done overflow chn_4 chn_3 chn_2 chn_1 definition 4 3 2 1 err dn err dn err dn err dn reset 0x0000 r/w read only addr 0x3_1010 32 39 40 41 42 43 44 45 46 47 field ? pkeu ? rng ? definition err dn err reset 0x0000 r/w read only addr 0x3_1014 48 49 50 51 52 53 54 55 56 57 58 63 field ? afeu ? mdeu ? aesu ? deu definition err dn err dn err dn err dn reset 0 r/w read only addr 0x3_1014 figure 17-65. interrupt status register (isr) 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 17-96 freescale semiconductor note interrupts are registered and sent based upon the conditions which cause them. if the cause of an interrupt is not removed, the interrupt will return a few cycles after it has been cleared using the icr. 0 14 15 field ? ito definition reset 0x0000 r/w w addr 0x3_1018 16 19 20 21 22 23 24 25 26 27 28 29 30 31 field ? done overflow chn_4 chn_3 chn_2 chn_1 definition 4 3 2 1 err dn err dn err dn err dn reset 0x0000 r/w w addr 0x3_1018 32 39 40 41 42 43 44 45 46 47 field ? ? pkeu ? rng ? definition err dn err reset 0x0000 r/w w addr 0x3_101c 48 49 50 51 52 53 54 55 56 57 58 63 field ? afeu ? mdeu ? aesu ? deu definition err dn err dn err dn err dn reset 0x0000 r/w w addr 0x3_101c figure 17-66. interrupt clear register (icr) 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 17-97 table 17-55 describes the interrupt mask, st atus, and clear register fields. i 17.6.2.4 id register the read-only id register, displayed in figure 17-67 , contains a 64-bit value that uniquely identifies the version of the sec 2.0. the valu e of this register is alwa ys 0x0000_0000_0000_0040, indicating that this is the first version of the sec 2.0. figure 17-67. id register table 17-55. interrupt mask, status, and clear register field descriptions bits name description 15 ito internal time out 0 no internal time out 1 an internal time out was detected the internal time out interrupt is triggered by the controller if a slave access to an sec register does not result in successful data trans fer within 16 clock cycles. with ito enabled the sec controller terminates the transaction and signals and interrupt. 20?23 done overflow done overflow 0 no done overflow 1 done overflow error. indicates that more than 15 done interrupts were queued from the interrupting channel without an interrupt clear. multiple chn_err_dn each of the 4 channels has error and done bits. 0 no error detected 1 error detected. indicates that execution unit status register must be read to determine exact cause of the error. 0 not done 1 done bit indicates that the interrupting channel or eu has completed its operation. multiple eu_err_dn each of the execution units has error and done bits. 0 no error detected 1 error detected. indicates that execution unit status register must be read to determine exact cause of the error. 0 not done 1 done bit indicates that the interrupting channel or eu has completed its operation. 0?14, 16?19, 32?41, 44?45, 47?49, 52?53, 56?57, 60?61 ? reserved, set to zero 0565763 field ? version reset 0x0000_0000_0000_0040 r/w read only addr 0x3_1020 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 17-98 freescale semiconductor 17.6.2.5 master control register (mcr) the mcr, shown in figure 17-68 , controls certain functi ons in the controller a nd provides a means for software to reset the sec. figure 17-68. master control register (mcr) table 17-56 describes the master c ontrol register signals. 0 21 22 23 24 30 31 field ? priority ? swr reset 0x0000_0000 r/w r/w addr 0x3_1030 32 39 40 47 48 55 56 63 field chn3_eu_pr_cnt chn4_eu_pr_cnt chn3_bus_pr_cnt chn4_bus_pr_cnt reset 0x0000_0000 r/w r/w addr 0x3_1034 table 17-56. mcr field descriptions bits name description 0?21 ? reserved 22?23 priority priority on master bus. th e setting of these bits determines the transaction priority level the sec asserts to the MPC8555E internal arbiter. the sec does not dynamically alter its priority level based on system congestion or sec utilization; however, software may change the sec priority level in real time. 00 lowest priority (default) 01 next lowest priority 10 next highest priority 11 highest priority 24?30 ? reserved 31 swr software reset. writing 1 to this bit will caus e a global software reset. upon completion of the reset, this bit will be automatically cleared. 0 don?t reset 1 global reset warning: certain sec interrupts are not fully cleared by writing this bit. if sec interrupts are pending, it is recommended that the us er set this bit twice (two consecutive writes) to completely reset the sec. 32?39 chn3_eu_pr_cnt channel 3 eu priority counter. this counter is used by the controller to determine when channel 3 has been denied access to a requested eu long enough to warrant immediate elevation to top priority. note: if set to zero, the chn4_eu_pr_ctr must also be set to zero, and the controller will assign eus on a purely round robin basis. if set to nonzero, chn4_eu_pr_ctr must also be set to a different, nonzero value. 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 17-99 17.6.2.6 eu access assignment of an eu function to a channel is done dynamically. with dynamic assignment, the channel requests an eu function, the controller checks to see if the requested eu function is available, and if it is, the controller grants the channel assignment of the eu. if an eu is available for a channel when requested, the controller will assert the grant si gnal pertaining to the request from the channe l. the grant signal will re main asserted until the ch annel is done and releases the eu. 17.6.2.7 multiple eu assignment in some cases, a channel may request two eus. the channel will do this by first requesting the primary eu, then requesting the secondary eu . once the controller ha s granted both eus, this channel is then capable of requesting that the secondary eu snoop the bus. snooping is described in section 17.7.3, ?snooping by caches.? in all cases, the controller assigns the primary eu to a requesting channel as the eus become available. the controller does not wait until bot h eus are available before issuing any grants to a channel which is requesting two eu functions. 17.6.2.8 multiple channels since there are multiple channels in the sec, the controller must arbitr ate for access to the execution units. to accomplish this, the controller im plements an arbite r for each channel. each arbiter acts on either a weig hted priority-based or on a round-r obin scheme, depending on the values of chn3_eu_pr_cnt and chn4_eu_pr _cnt. if both chn3_eu_pr_cnt and 40?47 chn4_eu_pr_cnt channel 4 eu priority counter. this counter is used by the controller to determine when channel 4 has been denied access to a requested eu long enough to warrant immediate elevation to top priority. note: if set to zero, the chn3_eu_pr_ctr must also be set to zero, and the controller will assign eus on a purely round robin basis. if set to nonzero, chn3_eu_pr_ctr must also be set to a different, nonzero value. 48?55 chn3_bus_pr_cnt channel 3 bus priority counter.this counter is used by the controller to determine when channel 3 has been denied access to the bus long enough to warrant immediate elevation to top priority. note: if set to zero, the chn4_bus_pr_ctr must also be set to zero, and the controller will assign access to the bus on a purely round robin basis. if set to nonzero, chn4_bus_pr_ctr must also be set to a different, nonzero value. 56?63 chn4_bus_pr_cnt channel 4 bus priority counter. this c ounter is used by the controller to determine when channel 4 has been denied access to a needed on-chip resource long enough to warrant immediate elevation to top priority. note: if set to zero, the chn3_bus_pr_ctr must also be set to zero, and the controller will assign access to the bus on a purely round robin basis. if set to nonzero, chn3_bus_pr_ctr must also be set to a different, nonzero value. table 17-56. mcr field descriptions (continued) bits name description 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 17-100 freescale semiconductor chn4_eu_pr_cnt are set to a nonzero value, the arbi ter will implement the we ighted priority scheme. otherwise, the arbitration will be ro und-robin. setting only one of the chn n _eu_pr_cnt fields to a nonzero value will result in unpredictable operation. 17.6.2.9 priority arbitration when arbitrating on the priority scheme , the priority will be as follows: ? channel 1?highest priority ? channel 2?second-highest priority, unless chn3_eu_pr_cnt or chn4_eu_pr_cnt expired ? channel 3?third priority, unless chn4_eu_pr_cnt expired ? channel 4?lowest priority, unt il chn4_eu_pr_cnt expires for channels 1?4, the priority is channel 1, channel 2, channel 3, and channel 4, in that order. in order to prevent channels 3 and 4 from be ing locked out, the chn3_eu_pr_c nt and chn4_eu_pr_cnt fields are implemented in the master control register. th e value of these fields determines how many times channel 3 or channel 4 can be refused access to an eu in favor of a higher priori ty channel. a counter is implemented in the arbiter for each of these entities. when the channel has lost arbitration the number of times specified in its chn_eu_pr_cnt field, then th at channel has the 2nd highest priority when the requested eu becomes available. chn1 always has th e highest priority, but it cannot make back-to-back requests, so the 2nd highest priority channel will be serviced upon completion of the current chn1 operation. it is permissible for the chn_eu _pr_cnt values to be different from the chn_bus_pr_cnt values; that is, eu access may be prioritized, while bus access is purely round robin, and vice-versa. 17.6.2.10 round-robin snapshot arbiters the controller implements seven snapshot arbiters, one for each eu function, and one for the bus. each arbiter takes a snapshot of the reque sts for its function. if there are re quests, the arbiter satisfies those requests through a round-robin scheme as the resource becomes available. when all requests have been satisfied, the arbiter ta kes another snapshot. 17.7 bus interface the controller in the sec (refer to section 17.6, ?sec controller? ) has the ability to be a bus master or a slave. this means that the controlle r can issue read and write commands to the bus, and it can also be written to and read from by the host. the controller is the sole bus mast er in the sec. all othe r modules are slave-only devices. a channel may request access to system resources including the bus. in these cases, the channel must provide the starting address of the transfer for the bus(es) requested. all subsequent addresses are ge nerated by the controller. all addresses will be sequential. 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 17-101 17.7.1 bus access the controller attempts to maximize bus util ization by grouping outstandi ng bus requests from the channels by request type. the controller will push al l write requests to the bus interface, followed by all read requests, then repeat. within a request type, the controller will grant bus access through the same scheme that is used for granting eus. when the chn_bus_pr_cnt va lues of both channel 3 and 4 are set to zero, round robin operation is in effect. in this case, the snapshot arbiter samples the requests for the bus, then grants those requests as the bus becomes available. for exam ple, if channels 1, 2, and 4 are requesting bus access at a gi ven time, the snapshot arbiter will regi ster the three requests and ignore further requests. the buses will be granted to channel 1 until its transfer is completely satisfied. then the buses will be granted to channel 2 until ch annel 2?s transfer is completely sa tisfied. finally, the buses will be granted to channel 4 until that transfer is completely satisfied. then another snap shot of requests will be taken. refer to section 17.6.2.9, ?prior ity arbitration,? for more information. 17.7.1.1 master read the sequence for master re ad access is as follows: 1. channel asserts its bus read request. 2. channel furnishes address and transfer length. 3. controller acknowledges request to channel. 4. controller asserts reque st to master interface. 5. controller waits for bus read to begin. 6. when bus read begins, controlle r receives data from the master interface and perfor ms a write to the appropriate internal address using the address supplied by the ch annel. data ma y be realigned byte-wise by the controller if either: ? the read did not begin on a 32-bit word boundary, or ? the previous write to an execution unit?s input fifo did not end on a 32-bit word boundary 7. transfer continues until the bus read is complete d and the controller has written all data to the appropriate internal address. the master interface will continue making bus requests until the full data length has been read. 17.7.1.1.1 slave aborts it is possible for the intended slave of an sec master-initiated transacti on to terminate the transfer due to an error. the sec?s transaction requests are poste d to the MPC8555E target queue, after which the MPC8555E takes responsibility for completing the tr ansaction or signaling error. an error in an sec-initiated transaction will also be reported by the sec through the ch annel interrupt st atus register. the host will be able to determine which channel generated the interrupt by checking the isr for the channel error bit. 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 17-102 freescale semiconductor 17.7.1.2 master write master writes are performe d by transferring data from one of the eus to the output fifo in the controller, then transferring the data from the fifo to the bus when the bus is gr anted to the controller. the sequence for a master bus write access is as follows: 1. channel requests the bus from controller. 2. channel furnishes address and transfer length. 3. controller acknowledges request to channel. 4. controller loads the write data into its fi fo, and waits for the bus to become available. 5. when the bus becomes available, controller writ es data from its fifo to the master interface. 6. transfer continues until the bus write is complete d and the controller has read all data from the appropriate internal address. the master interface will continue making bus requests until the full data length has been written. it is probable that multiple bus bur sts will be required to complete a ny given request. when a channel has been granted access to the bus, no other internal sec requests to the bus will be acknowledged until that transfer has been fully satisfied; that is, all bytes have been transferred. 17.7.1.2.1 slave access the controller also acts as a bus slave. as a slave, the controller simply responds to read and write commands from the bus. when a write command is recei ved from the bus, the controller takes the data from the slave interface and sends it to whichever internal location is in dicated by the address. for a read, the controller goes to the internal location and fetches the requested data from the specified address. the sec internal memory space must be accessed modulo-4 boundaries to avoi d invalid data or unpredictable operation. 17.7.2 bus arbitration priority transaction priority is configured for all channels in the sec master control register (mcr[priority]) as seen in figure 17-68 . the sec does not dynamically adjust its transaction priority; however, system software can adjust sec transaction priority in real time, with the change in priority taking effect immediately. 17.7.3 snooping by caches all sec transactions are snooped by th e MPC8555E coherency module. this is part of the wiring of the sec interface and requires no user intervention. 17.7.4 interrupts the sec generates a single interrupt to the mpc85 55e programmable interrupt controller. (refer to section 10.1.5.2, ?internal interrupt sources,? for additional information.) th e user allows interrupts from the sec to be reported to the cpu by clearing the mask bit in the associat ed vector/priority register of the pic. 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 17-103 the user can control which events cause an interrupt by configuring the sec interr upt mask register. these events are: ? done (of a channel or an execution unit) ? error (of a channel or an execution unit) when the user detects an interrupt request from the sec, it should further read the sec interrupt status register (isr) to determine the source of that interru pt. to clear an interrupt, the user should first write 1 to the bits in the sec interrupt clear register (i cr) corresponding to the pending isr bits, and then write zeros to the end of interrupt register in the pic to enable additional sec interrupts. events may be further masked per channel by setting or clearing the related fields in the crypto-channel configuration registers. it is suggested that the us er leave channel interrupts unmasked, while masking the interrupts from the eus. errors or done signals co ming from the eus eventually cause the channel to signal an error or done interrupt. cl earing an interrupt before elimin ating the condition which caused the interrupt will cause the interrupt to be asserted again a few cycles later. 17.8 power-saving mode the sec may be disabled by setting devdisr[sec]. (refer to section 18.4.1.11, ?device disable register (devdisr).? ) the clocks to the sec are active by default. the sec should not be enabled/disabled dur ing normal operation. 4 datasheet u .com
security engine (sec) 2.0 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 17-104 freescale semiconductor 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor iv-1 part iv global functions and debug this part defines other global blocks of the MPC8555E. the following chapters are included: ? chapter 18, ?global utilities,? defines the global utilities of the MPC8555E. these include power management, i/o device enabling, power- on reset (por) configuration monitoring, general-purpose i/o signal use, a nd multiplexing for the interrupt and local bus chip select signals ? chapter 19, ?performance monitor,? describes the performance monitor of the MPC8555E. ? chapter 20, ?debug features and watchpoint facility,? describes the debug features and watchpoint monitor of the MPC8555E. 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 iv-2 freescale semiconductor 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 18-1 chapter 18 global utilities this chapter describes the global ut ilities of the MPC8555E. it provid es signal descript ions, register descriptions, and a functional de scription of these utilities. 18.1 overview the global utilities block controls power mana gement, i/o device enabli ng, power-on-reset (por) configuration monitoring, general- purpose i/o signal configuration, al ternate function selection for multiplexed signals, and clock control. 18.2 global utilities features this section provides an overview of global utilities features. 18.2.1 power management and block disables the following features affect the device?s overall power consumption: ? dynamic power management mode ? software-controlled power ma nagement (doze, nap, sleep) ? externally controlled power management (doze, sleep) ? static power management (i/o block disables) 18.2.2 accessing current po r configuration settings the por configuration values of all device parameters sampled from pi ns at reset are available through memory-mapped registers in the global utilities block. 18.2.3 general-purpose i/o the pci and tsec2 data bus signals can be used as general-purpose i/o signals when not used for their primary function. memory-mapped regist ers in the global utilities block pr ovide control and status for the use of these signals . a general purpose input register is loaded with the valu es of the local bus address/data pins at the negation of hreset . 18.2.4 interrupt and local bus signal multiplexing irq[9:11] and lcs [5:7] serve multiple functions that can be selected by configuration registers in the global utilities block. 4 datasheet u .com
global utilities MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 18-2 freescale semiconductor the multiplexing of the cp m signals occurs through the cpm programming model. see chapter 45, ?parallel i/o ports,? for details on cpm signal multiplexing. 18.2.5 clock control the global utilities block also selects th e internal clock signal driven on clk_out. 18.3 external signal description the following sections provide information a bout signals that serve as global utilities. 18.3.1 signals overview table 18-1 summarizes the external signals used by the global utilities block. 18.3.2 detailed signal descriptions table 18-2 describes signals in the gl obal utilities block in detail. table 18-1. external signal summary signal name i/o description reference (section/page) asleep o signals that the device has reached a sleep state. 18.5.1.5.3/18-24 ckstp_ in i checkstop input ? ckstp_out o checkstop output. ? clk_out o clock out. selected by clkocr values. 18.4.1.16/18-19 table 18-2. detailed signal descriptions signal i/o description asleep o asleep. see section 18.5.1.5.3, ?sleep mode.? after negation of hreset , asleep is asserted until the device completes its power-on reset sequence and reaches its ready state. state meaning asserted?indicates that the device is either still in its power-on reset sequence or it has reached a sleep state after a power-down command is issued by software. negated?the device is not in sleep mode. (it has either awakened from a power-down state, or has completed the por sequence.) timing assertion?may occur at any time; may be asse rted asynchronously to the input clocks. negation?negates synchro nously with sysclk when leaving power-on sequence; otherwise negation is asynchronous. ckstp_in i checkstop in state meaning asserted?indicates that the e500 core must ente r a hard stop condition. all e500 clocks are turned off. ckstp_out is asserted. the rest of MPC8555E device logic, including memory controllers, internal memories an d registers, and i/o interfaces, remains functional. negated?indicates that normal operation should proceed. timing assertion?may occur at any time; may be asse rted asynchronously to the input clocks. negation?must remain asserted until the MPC8555E is reset with assertion of hreset . 4 datasheet u .com
global utilities MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 18-3 18.4 memory map/register definition table 18-3 summarizes the global utilities registers and their addresses. undefined 4-byte address spaces within offset 0x000?0xfff are reserved. ckstp_out o checkstop out state meaning asserted?indicates that the e500 co re of the MPC8555E is in a checkstop state. the rest of the MPC8555E logic remains functional. negated?indicates normal operation. after ckstp_out has been asserted, it is negated after the next negation (low -to-high transition) of hreset . timing assertion?may occur at any time; may be asse rted asynchronously to the input clocks. negation?must remain asserted until the device has been reset with a hard reset. clk_out o clock out. reflects clock signal selected by clkocr (see section 18.4.1.16, ?clock out control register (clkocr)? ). state meaning asserted?if clkocr[enb] = 1, clock signal selected by clkocr[clk_sel] is driven. high impedance?if clkocr[enb] = 0. timing assertion/negation?depends on the value of clkocr[clk_sel]. table 18-3. global utilities block register summary offset register access reset section/page power-on reset configuration values 0xe_0000 porpllsr?por pll ratio status register r 0x00 nn _ n 1 nn 18.4.1.1/18-4 0xe_0004 porbmsr?por boot mode status register r 0x nnnn _0000 18.4.1.2/18-5 0xe_0008 porimpscr?por i/o impedance stat us and control register r/w 0x000 n _007f 18.4.1.3/18-6 0xe_000c pordevsr?por i/o device status register r see ref. 18.4.1.4/18-7 0xe_0010 pordbgmsr?por debug mode status register r see ref. 18.4.1.5/18-8 0xe_0020 gpporcr?general-purpose por configuration register r see ref. 18.4.1.6/18-9 signal multiplexing and gpio controls 0xe_0030 gpiocr?gpio control register r/w 0x0000_0000 18.4.1.7/18-10 0xe_0040 gpoutdr?general-purpose ou tput data register r/w 0x0000_0000 18.4.1.8/18-11 0xe_0050 gpindr?general-purpose input data register r 0x nnnn _0000 18.4.1.9/18-12 0xe_0060 pmuxcr?alternate function sig nal multiplex control r/w 0x0000_0000 18.4.1.9/18-12 device disables 0xe_0070 devdisr?device disable control r/w 0x0000_0000 18.4.1.11/18-14 power management registers 0xe_0080 powmgtcsr?power ma nagement status and control register r/w 0x0000_0000 18.4.1.12/18-16 table 18-2. detailed signal descriptions (continued) signal i/o description 4 datasheet u .com
global utilities MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 18-4 freescale semiconductor 18.4.1 register descriptions this section describes the global utilities registers in detail. 18.4.1.1 por pll status register (porpllsr) porpllsr, shown in figure 18-1 , contains the settings for the pll ra tios as set by th e cfg_sys_pll[0:3], cfg_core_pll[0:1], tsec2_txd[1], and ts ec2_txd[0] por confi guration pins. see section 4.4.3.1, ?system pll ratio,? section 4.4.3.10, ?pci clock selection,? and section 4.4.3.2, ?e500 core pll ratio,? for more information. figure 18-1. por pll status register (porpllsr) interrupt reporting 0xe_0090 mcpsumr?machine check summary register read/clear 0x0000_0000 18.4.1.13/18-17 version registers 0xe_00a0 pvr?processor version register r e500 processor version 18.4.1.14/18-18 0xe_00a4 svr?system version register r MPC8555E / mpc8541e system version 18.4.1.15/18-19 debug control 0xe_0e00 clkocr?clock out select register r/w 0x0000_0000 18.4.1.16/18-19 0xe_0e20 lbdllcr?lbc dll control register r/w 0x0000_0000 18.4.1.17/18-20 0 9 10 15 16 17 25 26 31 r0000000001e500_ratiopci1_clk_selpci2_clk_sel00000101plat_ratio0 w reset 0000_0000_01 nn _ nnnn_nn 00_0001_01 nn _ nnnn offset 0xe_0000 table 18-3. global utilities block register summary (continued) offset register access reset section/page 4 datasheet u .com
global utilities MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 18-5 table 18-4 describes the bit settings of porpllsr. 1 ccb to sysclk clock ratio of 2:1 must not be selected when tsec2_txd[1] or tsec2_txd[0] are configured to be clocked by sysclk. 18.4.1.2 por boot mode status register (porbmsr) the porbmsr, shown in figure 18-2 , reports setting of th e por configuration pins that control the boot mode settings (described in section 4.4.3.3, ?boot rom location,? section 4.4.3.5, ?cpu boot configuration,? and section 4.4.3.6, ?boot sequ encer configuration,? ) and the default settings of pci host/agent mode (described in section 4.4.3.4, ?host/ag ent configuration? ). table 18-4. porpllsr field descriptions bits name description 0?9 ? reserved 10?15 e500_ratio clock ratio between the e500 core and the ccb cloc k. the 2 lsbs of this field correspond to the values on cfg_core_pll[0:1] at the negation of hreset . patterns not shown are reserved. 000100 2:1 000101 5:2 000110 3:1 000111 7:2 16 pci1_clk_sel clock used for pci1. this bit corresponds to the value on tsec2_txd[1] at the negation of hreset : 0 pci1 is clocked by pci1_clk 1 pci1 is clocked by sysclk 1 17 pci2_clk_sel clock used for pci2. this bit corresponds to the value on tsec2_txd[0] at the negation of hreset : 0 pci2 is clocked by pci2_clk 1 pci2 is clocked by sysclk 1 18?25 ? reserved 26?30 plat_ratio clock ratio between the ccb (platform) cloc k and sysclk. the 4 lsbs correspond to the values on cfg_sys_pll[0:3] at the negation of hreset . patterns not shown are reserved. 00010 2:1 1 00011 3:1 00100 4:1 00101 5:1 00110 6:1 01000 8:1 01001 9:1 01010 10:1 01100 12:1 10000 16:1 31 ? reserved 0 1 45 789101112 141516 31 r bcfg0000rom_loc00bscfg000 pci1_ha 0000000000000000 w reset n 000_0 nn n_00 nn _000 n_ 0000_0000_0000_0000 offset 0xe_0004 figure 18-2. por boot mode status register (porbmsr) 4 datasheet u .com
global utilities MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 18-6 freescale semiconductor for more information about the pci configurations, see section 16.3.2.19, ?pci bus function register (pbfr).? figure 18-5 describes the bit settings of the porbmsr. 18.4.1.3 por i/o impedance status and control register (porimpscr) porimpscr, shown in figure 18-3 , defines the current i/ o driver impedances for local bus signals and reports the i/o impedance setting for the pci interface. the i/o impedance of the local bus si gnal (including the local bus clock) is controlled through this register. the i/o impedance of pci sign als is controlled by por config uration pins (described in section 4.4.3.12, table 18-5. porbmsr field descriptions bits name description 0 bcfg cpu boot configuration 0 the cpu is prevented from booting until confi guration by an external master is complete. 1 the cpu is allowed to start fetching boot code. 1?4 ? reserved 5?7 rom_loc location of boot rom 000 pci1 001 ddr sdram 010 pci2 011?100 reserved 101 local bus gpcm: 8-bit 110 local bus gpcm:16-bit 111 local bus gpcm: 32-bit 8?9 ? reserved 10?11 bscfg boot sequencer configuration 00 reserved 01 boot sequencer enabled with normal i 2 c addressing 10 boot sequencer enabled with extended i 2 c addressing 11 boot sequencer disabled 12?14 ? reserved 15 pci1_ha pci1 host/agent mode configur ation. when the MPC8555E is an agent on an interface, it is prevented from mastering transactions on that interface until the external host configures the interface appropriately. note that pci2 is always in host mode. 0 pci1 agent mode 1 pci1 host mode 16?31 ? reserved 0 13 14 15 16 2425262728293031 r 00000000000000 pci2_z pci1_z 00000000 0 lale_z ladp_z la_cke_z lcs12_z lwe_z lgpl_z lclk_z w reset 0000_0000_0000_00 nn_ 0000_0000_0111_1111 offset 0xe_0008 figure 18-3. por i/o impedance status and control register (porimpscr) 4 datasheet u .com
global utilities MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 18-7 ?pci i/o impedance? ). MPC8555E powerquicc? iii integrated processor hardware specifications provides exact i/o impedances. table 18-6 describes porimpscr fields. 18.4.1.4 por device status register (pordevsr) shown in figure 18-4 , pordevsr reports other por settings for i/o devices as described in section 4.4.3.7, ?tsec width ,? section 4.4.3.8, ?tsec1 protocol,? section 4.4.3.9, ?tsec2 protocol,? section 4.4.3.13, ?pci arbiter configuration,? and section 4.4.3.11, ?pci width configuration.? table 18-6. porimpscr field descriptions bits name description 0?13 ? reserved 14 pci2_z pci2 i/o impedance 0 low impedance 1 high impedance 15 pci1_z pci1 i/o impedance (lower 32 bits wh en in 64-bit mode) as set by por signals (see section 4.4.3.12, ?pci i/o impedance? ). 0 low impedance 1 high impedance 16?24 ? reserved 25 lale_z i/o impedance for local bus address latch enable 0 low impedance 1 high impedance 26 ladp_z i/o impedance for local bus address/dat a and data parity (lad[0:31] and ldp[0:7]) 0 low impedance 1 high impedance 27 la_cke_z i/o impedance for local bus address and clock enable (la[27:31] and lcke) 0 low impedance 1 high impedance 28 lcs12_z i/o impedance for two local bus chip selects (lcs 1 and lcs 2 only) other chip selects use a fixed high i/o impedance 0 low impedance 1 high impedance 29 lwe_z i/o impedance for local bus write enables (lwe [0:3]) 0 low impedance 1 high impedance 30 lgpl_z i/o impedance for local bus general-purpose lines (lgpl[0:5]) 0 low impedance 1 high impedance 31 lclk_z i/o impedance for local bus clocks (lclk[0:2]) 0 low impedance 1 high impedance 4 datasheet u .com
global utilities MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 18-8 freescale semiconductor table 18-7 describes the bit settings of pordevsr. 18.4.1.5 por debug mode stat us register (pordbgmsr) pordbgmsr, shown in figure 18-5 , holds debug mode settings from the por configuration pins as described in section 4.4.3.15, ?memory debug configur ation,? section 4.4.3.16, ?ddr debug configuration,? and section 4.4.3.14, ?pci debug configuration.? 0 1 5 6 7 8 12 13 14 15 16 31 r ecw 0 0 0 0 0 ecp 0 0 0 0 0 pci2_arb pci1_arb pci32 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset n 000_00 nn _0000_0 nnn_ 0000_0000_0000_0000 offset 0xe_000c figure 18-4. por device stat us register (pordevsr) table 18-7. pordevsr field descriptions bits name description 0 ecw gigabit ethernet controller width 0 reduced (rgmii, rtbi) 1 full (mii, gmii, tbi) 1?5 ? reserved 6?7 ecp gigabit ethernet controller protocol 00 both tsec blocks use a media indepe ndent interface protocols (mii/gmii/rgmii) 01 tsec1 uses mii, tsec2 uses tbi 10 tsec1 uses tbi, tsec2 uses mii 11 both tsec blocks use a ten bit interface protocol (tbi or rtbi) 8?12 ? reserved 13 pci2_arb pci2 arbiter enable 0 pci2 arbiter is disabled 1 pci2 arbiter is enabled 14 pci1_arb pci1 arbiter enable 0 pci1 arbiter is disabled 1 pci1 arbiter is enabled 15 pci32 pci1 interface width 0 64-bit 1 32-bit. pci2 may be enabled. 16?31 ? reserved 4 datasheet u .com
global utilities MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 18-9 table 18-8 describes the bit settings of pordbgmsr. 18.4.1.6 general-purpose por co nfiguration register (gpporcr) shown in figure 18-6 , gpporcr stores the value sampled from the local bus address/data signals, lad[0:31], during por, as described in section 4.4.3.19, ?general-pur pose por configuration.? software can use this value to inform the operating system about initial syst em configuration. typical interpretations include circuit board type, board id number, or a list of available peripherals. 045 6 78 31 r 0 0 0 0 0 mem_sel ddr_dbg pci1_dbg 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset 0000_0 nnn _0000_0000_0000_0000_0000_0000 offset 0xe_0010 figure 18-5. por debug mode status register (pordbgmsr) table 18-8. pordbgmsr field descriptions bits name description 0?4 ? reserved 5 mem_sel memory select. indicates which co ntroller is driving msrcid[0:4] and mdval 0 local bus controller is driving debug information 1 ddr sdram controller is driving debug information 6 ddr_dbg ddr debug configuration 0 source id and data valid information is being driven on ecc pins of ddr sdram interface 1 normal mode. ecc information is being driven on ecc pins of ddr sdram interface 7 pci1_dbg pci1 debug configuration 0 pci1 drives source id onto address signals pci1_ad[ 62:58]. note that pci1 must be configured for 64-bit mode to see source id debug information. 1 pci1 drives address onto address signals pci1_ad[62:58]. (see section 20.4.2, ?pci interface debug,? for additional details.) 8?31 ? reserved 0 31 r por_cfg_vec w reset 0x nnnn _ nnnn offset 0xe_0020 figure 18-6. por configuration register (gpporcr) 4 datasheet u .com
global utilities MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 18-10 freescale semiconductor table 18-9 describes the bit se ttings of gpporcr. 18.4.1.7 general-purpose i/o control register (gpiocr) shown in figure 18-7 , gpiocr contains the enable bits for ea ch group of pins that may be used for general-purpose i/o. these bits have meaning only if the pins are not being used fo r their primary function. note that when these signals are enabled as general-purpose i/o signals , they are read and written through gpindr and gpoutdr described in section 18.4.1.9, ?general-purpos e input data register (gpindr),? and section 18.4.1.8, ?general-purpose out put data register (gpoutdr).? section 18.5.2, ?general-purpose i/o signals,? describes the use of ge neral-purpose i/o signals. table 18-10 describes the bit settings of gpiocr. table 18-9. gpporcr field descriptions bits name description 0?31 por_cfg_vec general-purpose por c onfiguration vector sampled from local bus address/data signals at the negation of hreset . note that if nothing is driven on these signals during reset, the value of this register is indeterminate. 0567813141516 31 r0 0 00 0 0 tx2out rx2in 000000 pciout pciin 00 00000000000000 w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0xe_0030 figure 18-7. general-purpose i/o control register (gpiocr) table 18-10. gpiocr field descriptions bits name description 0?5 ? reserved 6 tx2out enables tsec2_tx[0:7] for use as general-purpo se outputs if the tsec2 interface is disabled. (see section 18.4.1.11, ?device disable register (devdisr).? ) 0 tsec2_tx[0:7] function as described in the tsec chapter. 1 tsec2_tx[0:7] function as general-purpose outputs. 7 rx2in enables tsec2_rx[0:7] for use as general-purpos e inputs if the tsec2 interface is disabled. (see section 18.4.1.11, ?device disable register (devdisr).? ) 0 tsec2_rx[0:7] function as described in the tsec chapter. 1 tsec2_rx[0:7] function as general-purpose inputs. 8?13 ? reserved 14 pciout enables pci2_ad[15:8] for us e as general-purpose outputs. note that the pci1 interface must be configured for 32-bit mode and the pci2 interface must be disabled. (see section 18.4.1.11, ?device disable register (devdisr).? ) 0 pci2_ad[15:8] function as de scribed in the pci chapter. 1 pci2_ad[15:8] function as general-purpose outputs. 4 datasheet u .com
global utilities MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 18-11 18.4.1.8 general-purpose output data register (gpoutdr) gpoutdr, shown in figure 18-8 , contains the data driven as general-purpose output on tsec2_txd[0:7] and/or pc i2_ad[15:8] when either of these buses is configured as a general-purpose i/o bus, as described in section 18.4.1.7, ?general-purpose i/o control register (gpiocr).? writes to gpoutdr affect only pins enabled as general-purpos e outputs. reads return valid data only for bits corresponding to pins enabled as general-purpose outputs. gpoutdr may be accessed using single byte writes (using big-endian addressing) so that writes to one byte do not affect outputs controlled by others. 15 pciin enables pci2_ad[7:0] for use as general-purpose input s. note that the pci1 interface must be configured for 32-bit mode and the pci2 interface must be disabled. (see section 18.4.1.11, ?device disable register (devdisr).? ) 0 pci2_ad[7:0] function as described in the pci chapter. 1 pci2_ad[7:0] function as general-purpose inputs. 16?31 ? reserved 01516 31 r gpoutdr 0000000000000000 w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0xe_0040 figure 18-8. general-purpose output data register (gpoutdr) table 18-10. gpiocr field descriptions (continued) bits name description 4 datasheet u .com
global utilities MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 18-12 freescale semiconductor table 18-11 describes the fields of gpoutdr. 18.4.1.9 general-purpose input data register (gpindr) gpindr, shown in figure 18-9 , contains the data currently sa mpled as general-purpose input on tsec2_rxd[0:7] and/or pc i2_ad[7:0] when either of these buses is configured as a general-purpose i/o bus in gpiocr. (see section 18.4.1.7, ?general-purpose i/o control register (gpiocr).? ) gpindr bits are updated only if the associated bits are confi gured as general-purpose input pins rather than their primary functions. table 18-11. gpoutdr field descriptions bits name description 0?15 gpoutdr general-purpose output data. when the corre sponding signals are configured to be general-purpose output signals, the values of the bits of gpoutdr are driven onto those pins. gpoutdr[0:7] corresponds to t sec2_txd[0:7] and gpoutdr[8:15 ] corresponds to pci2_ad[15:8] as follows: gpoutdr[0] ? tsec2_txd[0] gpoutdr[1] ? tsec2_txd[1] gpoutdr[2] ? tsec2_txd[2] gpoutdr[3] ? tsec2_txd[3] gpoutdr[4] ? tsec2_txd[4] gpoutdr[5] ? tsec2_txd[5] gpoutdr[6] ? tsec2_txd[6] gpoutdr[7] ? tsec2_txd[7] gpoutdr[8] ? pci2_ad[15] gpoutdr[9] ? pci2_ad[14] gpoutdr[10] ? pci2_ad[13] gpoutdr[11] ? pci2_ad[12] gpoutdr[12] ? pci2_ad[11] gpoutdr[13] ? pci2_ad[10] gpoutdr[14] ? pci2_ad[9] gpoutdr[15] ? pci2_ad[8] 16?31 ? reserved, should be cleared 01516 31 r gpindr 0000000000000000 w reset nnnn _ nnnn_nnnn_nnnn _0000_0000_0000_0000 offset 0xe_0050 figure 18-9. general-purpose input data register (gpindr) 4 datasheet u .com
global utilities MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 18-13 table 18-12 describes the fields of gpindr. 18.4.1.10 alternate function signal mu ltiplex control register (pmuxcr) shown in figure 18-10 , pmuxcr contains bits that enable dma channels 2 and 3, which exist as alternate functions on local bus chip select pins lcs [5:7], and interrupt input pi ns irq[9:11], respectively. specifically, dma request, acknowle dge, and done signals comprise th e secondary functions for the associated irq and local bus chip se lect signals. note that cpm signal mu ltiplexing is handled separately through the cpm programming model described in chapter 45, ?parallel i/o ports.? table 18-12. gpindr field descriptions bits name description 0?15 gpindr general-purpose input data. when th e corresponding signals are configured to be general-purpose input signals, the values sampl ed on these signals are reflected in gpindr. gpindr[0:7] corresponds to tsec2_rxd[0: 7] and gpindr[8:15] corresponds to pci2_ad[7:0] as follows: gpindr[0] ? tsec2_rxd[0] gpindr[1] ? tsec2_rxd[1] gpindr[2] ? tsec2_rxd[2] gpindr[3] ? tsec2_rxd[3] gpindr[4] ? tsec2_rxd[4] gpindr[5] ? tsec2_rxd[5] gpindr[6] ? tsec2_rxd[6] gpindr[7] ? tsec2_rxd[7] gpindr[8] ? pci2_ad[7] gpindr[9] ? pci2_ad[6] gpindr[10] ? pci2_ad[5] gpindr[11] ? pci2_ad[4] gpindr[12] ? pci2_ad[3] gpindr[13] ? pci2_ad[2] gpindr[14] ? pci2_ad[1] gpindr[15] ? pci2_ad[0] 16?31 ? reserved 0 141516 3031 r0 0000000000000 0 dma2 0 0000000000000 0 dma3 w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0xe_0060 figure 18-10. alternate function pin multiplex control register (pmuxcr) 4 datasheet u .com
global utilities MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 18-14 freescale semiconductor table 18-13 describes the bit settings of pmuxcr. 18.4.1.11 device disable register (devdisr) devdisr, shown in figure 18-11 , contains disable bits for va rious MPC8555E functional blocks. all functional blocks are enabled after reset; unneeded blocks can be disabled to reduce power consumption or allow their signals to be used as ge neral-purpose i/o signals. see section 18.4.1.7, ?general-purpose i/o cont rol register (gpiocr).? blocks disabled by devdisr must not be re-enabled without a hard reset. section 18.5.1.4, ?shutting down unused blocks,? has more information on the use of devdisr. table 18-14 describes devdisr fields. table 18-13. pmuxcr field descriptions bits name description 0?14 ? reserved 15 dma2 enables dma channel 2 signals 0 dma channel 2 is not exposed to pins; the pins retain their primary function as local bus chip selects. 1 dma channel 2 is exposed to pins as follows: lcs5 functions as dma_dreq2 lcs6 functions as dma_dack2 lcs7 functions as dma_ddone2 16?30 ? reserved 31 dma3 enables dma channel 3 signals 0 dma channel 3 is not exposed to pins; the pins retain their primary function as interrupt requests. 1 dma channel 3 is exposed to pins as follows: irq9 functions as dma_dreq3 irq10 functions as dma_dack3 irq11 functions as dma_ddone3 01234567 8 1112 1415 r pci1 pci2 00 lbc 00 sec 0000000 ddr w reset 0000_0000_0000_0000 16 17 18 19 20 21 22 23 24 25 26 28 29 30 31 r e500 tb 0 0 cpm dma 00 tsec1 tsec2 000 i2c duart 0 w reset 0000_0000_0000_0000 offset 0xe_0070 figure 18-11. device disable register (devdisr) 4 datasheet u .com
global utilities MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 18-15 . table 18-14. devdisr field descriptions bits name description 0 pci1 pci1 controller disable 0 pci1 controller enabled 1 pci1 controller disabled 1 pci2 pci2 controller disable 0 pci2 controller enabled 1 pci2 controller disabled. pci2_ad[15:0] may be used as general-purpose i/o provided pci1 is in 32-bit mode. 2?3 ? reserved 4 lbc local bus controller disable 0 local bus controller enabled 1 local bus controller disabled 5?6 ? reserved 7 sec security disable 0 security enabled 1 security disabled 8?11 ? reserved 12?14 ? reserved 15 ddr ddr sdram controller disable 0 ddr sdram controller enabled 1 ddr sdram controller disabled 16 e500 e500 core disable 0 e500 core enabled 1 e500 core disabled. places the core in the core_sto pped state in which it does not respond to interrupts. equivalent to nap mode. instruction fetching is stopped, snooping is disabled, and clocks are shut down to all functional units of the core including the timer facilities. for more information, see section 18.5.1.4, ?shutting down unused blocks.? 17 tb time base (timer facilities) of the e500 core disable 0 timer facilities enabled 1 timer facilities disabled 18?19 ? reserved 20 cpm communications processor module disable 0 cpm enabled 1cpm disabled 21 dma dma controller disable 0 dma controller enabled 1 dma controller disabled 22?23 ? reserved 24 tsec1 three-speed ethernet controller 1 disable 0 tsec1 enabled 1 tsec1 disabled 25 tsec2 three-speed ethernet controller 2 disable 0 tsec2 enabled 1 tsec2 disabled. rxd and txd pins may be used for general-purpose i/o. 4 datasheet u .com
global utilities MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 18-16 freescale semiconductor 18.4.1.12 power management control and status register (powmgtcsr) shown in figure 18-12 , powmgtcsr contains bits for placing the MPC8555E in to low power states and for controlling when it wakes up. it also c ontains power manageme nt status bits. see section 18.5.1.8.2, ?interrupts and power manageme nt controlled by powmgtcsr,? for more information. table 18-15 describes the bit settings of powmgtcsr. 26?28 ? reserved 29 i2c i 2 c controller disable 0i 2 c controller enabled 1i 2 c controller disabled 30 duar t dual uart controller disable 0 duart enabled 1 duart disabled 31 ? reserved 012 1 1 12 13 14 1 5 2 7 28 29 30 31 r irq_msk ci_msk 0000000000 doz 0 slp 0000000000000dozingn apping slping 0 w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0xe_0080 figure 18-12. power management control and status register (powmgtcsr) table 18-15. powmgtcsr field descriptions bits name description 0 irq_msk interrupt input mask 0 interrupts cause the device to wake up from a low-power state. 1 interrupts are masked as a wake-up condition. th e device remains in a low-power state despite the presence of an interrupt request. 1 ci_msk critical in terrupt input mask 0 critical interrupts cause the device to wake up from a low power state. 1 critical interrupts are masked as a wake-up condition. the device remains in a low-power state despite the presence of a critical interrupt. 2?11 ? reserved 12 doz doze mode 0 no request to put device in doze mode. note that this bit is automatically cleared on mcp, ude, sreset , core_tbint (from the core) and also int and cint if not masked. 1 device is to be placed in doze mode. instruction fe tching is halted in the e500 core. note that this bit is logically ored with hid0[doze]. 13 ? reserved table 18-14. devdisr field descriptions (continued) bits name description 4 datasheet u .com
global utilities MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 18-17 18.4.1.13 machine check summary register (mcpsumr) shown in figure 18-13 , mcpsumr contains bits summarizing so me of the sources of a pending machine check interrupt. all mcpsumr bits function as write-1-to-clear. note register fields designated as write-1- to-clear are cleared only by writing ones to them. writing zeros to them has no effect. note that other conditions can cause a machine check condition no t summarized in mcpsumr. for example, uncorrectable read er rors cause the assertion of core_fault_in , which may directly cause a machine check (if hid1[rfxe] = 1) . if rfxe = 0, the assertion of core_fault_in does not directly cause a machine check interrupt, but must be handled by the block that generate d the error. for more information about rfxe, see section 6.10.2, ?hardware implementati on-dependent register 1 (hid1).? figure 18-13. machine check summary register (mcpsumr) 14 slp sleep mode 0 no request to put device in sleep mode 1 device is to be placed in sleep mode. instruction fe tching is halted, snooping of l1 caches is disabled, and most functional blocks are shut down in both the e500 core and the system logic. 15?27 ? reserved 28 dozing doze status 0 device is not in doze mode 1 the MPC8555E is in doze mode because powmgt csr[doz] is set or because hid0[doze] and msr[we] (in the e500 core) are set. the core has halted instruction fetching, but all other functional blocks in the core and device are fully operational. 29 napping nap status 0 device is not in nap mode. 1 the MPC8555E is in nap mode because hid0[nap] and msr[we] are set. the core has halted instruction fetching, snooping of the l1 caches is disabled, and all of t he core?s functional units except the timer facilities are shut down. all functional blocks in the device are fully operational. 30 slping sleep status 0 device is not attempting to reach sleep mode 1 the device is attempting to sleep because powm gtcsr[slp] is set or because hid0[sleep] and msr[we] (in the e500 core) are set. most functional blocks in the core and device are shut down or are attempting to shut down. 31 ? reserved. should be cleared. 0 28 29 30 31 r000000000000000000 00000000000 wrs sreset mcp_in w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0xe_0090 table 18-15. powmgtcsr field descriptions (continued) bits name description 4 datasheet u .com
global utilities MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 18-18 freescale semiconductor table 18-16 describes the bit settings of mcpsumr. 18.4.1.14 processor vers ion register (pvr) shown in figure 18-14 , the pvr contains the e500 processor version number. it is a memory-mapped copy of the pvr in the e500 core (and is theref ore accessible to external devices). see section 6.5.3, ?processor version register (pvr).? section 5.2, ?e500 processor and system version numbers,? lists the complete values for the MPC8555E table 18-17 describes the fields of pvr. table 18-16. mcpsumr field descriptions bits name description 0?28 ? reserved 29 wrs watchdog timer machine check 0 machine check exception was not caused by watchdog timer 1 machine check was caused by a soft reset condition from the e500 watchdog timer as configured in the core?s tsr. specifically, tsr[wrs] = 01 and a watchdog reset condition occurred. 30 sreset soft reset machine check 0 machine check exception was not caused by sreset assertion 1 machine check exception was caused by the assertion of the sreset input signal 31 mcp_in mcp signal asserted 0 machine check exception was not caused by mcp assertion 1 machine check exception was caused by the assertion of the mcp input signal 0151631 r version revision w reset 0x8020_ nnnn offset 0xe_00a0 figure 18-14. processor version register (pvr) table 18-17. pvr field descriptions bits name description 0?15 version a 16-bit number that ident ifies the version of the processor. di fferent version numbers indicate major differences between processors, such as which opti onal facilities and inst ructions are supported. 16?31 revision a 16-bit number that dist inguishes between implementat ions of the version. different revision numbers indicate minor differences between processors having the same version number, such as clock rate and engineering change level. 4 datasheet u .com
global utilities MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 18-19 18.4.1.15 system version register (svr) shown in figure 18-15 , the svr contains the system ve rsion number for the MPC8555E/mpc8541e implementation. this value can also be read though the svr spr of the e500 core. see section 6.5.4, ?system version register (svr).? section 5.2, ?e500 processor an d system version numbers ,? lists the complete values for the MPC8555E. table 18-18 describes the fields of svr. 18.4.1.16 clock out control register (clkocr) shown in figure 18-16 , the clkocr contains contro l bits that select the clock sources to be placed on the clock out (clk_out) signal. table 18-19 describes the bit settings of clkocr. 0 31 rsv w reset 0x8079_0011 (for MPC8555E) / 0x807a_0011 (for mpc8541e) 0x8071_0011 (for mpc8555) / 0x8072_0011 (for mpc8541) offset 0xe_00a4 figure 18-15. system version register (svr) table 18-18. svr field descriptions bits name description 0?31 sv system version: 0x8079_0011 (for MPC8555E) / 0x807a_0011 (for mpc8541e) 0x8071_0011 (for mpc8555) / 0x8072_0011 (for mpc8541) 01 25 26 31 r enb 0000000000000000000000000 clk_sel w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0xe_0e00 figure 18-16. clock out control register (clkocr) table 18-19. clkocr field descriptions bits name description 0 enb clock out enable 0 clk_out signal is three-stated 1 clk_out signal is driven according to clkocr[clk_sel] 4 datasheet u .com
global utilities MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 18-20 freescale semiconductor 18.4.1.17 local bus dll control register (lbdllcr) shown in figure 18-17 , the lbdllcr contains contro l bits that allow debug of the local bus controller?s dll. the delay chain of the dll is made up of 128 tap points. 1?25 ? reserved 26?31 clk_sel clock out select 000000 ccb (platform) clock 000001 ccb (platform) clock divided by 2 000010 sysclk (echoes sysclk input) 000011 sysclk divided by 2 (demonstrates platform pll lock) 000100 reserved 000101 reserved 000110 reserved 000111 reserved 001000 reserved 001001 reserved 001010 reserved 001011 reserved 001100 reserved 001101 reserved 001110 reserved 001111 reserved 01xx0x reserved 01xx1x reserved 10x000 reserved 10x001 reserved 10x010 pci1 bus clock 10x011 pci1 bus clock divided by 2 10x100 reserved 10x101 reserved 10x110 reserved 10x111 logic 0 11x000 reserved 11x001 reserved 11x010 pci2 bus clock 11x011 pci2 bus clock divided by 2 11x100 reserved 11x101 reserved 11x110 reserved 11x111 logic 1 0 1 4 5 7 8 15 16 20 21 23 24 31 r ovrd 0000 course_adj tap_sel 0 0 0 0 0 course_set tap w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0xe_0e20 figure 18-17. local bus dll control register (lbdllcr) table 18-19. clkocr field descriptions (continued) bits name description 4 datasheet u .com
global utilities MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 18-21 table 18-20 describes the bit settings of lbdllcr. 18.5 functional description this section describes th e global utilities from a functional perspective. 18.5.1 power management the MPC8555E has features to minimize power consumption at several levels. dynamic power management locally minimizes power consumption when a block is id le. software can also shut down clocks to individual blocks when they are not needed through a memory-ma pped register (devdisr). additionally, software executing on the e500 core can access the core?s sprs to put th e device into doze, nap, or sleep power down state. finally, software can access a memory-mapped register (powmgtcr) in the global utilities block to put th e device in the doze or sleep states. note that the software that writes to either devdisr or powmgtcr can be executing either on the e500 core or on an external master th at can write to the MPC8555E memo ry-mapped register s through the pci interfaces. these features are described in further detail in this section. 18.5.1.1 relationship between core an d device power management states the MPC8555E has three low-power st ates: doze, nap, and sleep. the ma pping of core and device power management states is shown in figure 18-18 showing state transitions from the perspective of the e500 core. table 18-20. lbdllcr field descriptions bits name description 0 ovrd override mode 0 override mode disabled 1 override of current delay chain tap point with the tapsel tap point enabled 1?4 ? reserved 5?7 course_adj course adjustment value to be used by the dll when in override mode (ovrd = 1). the course adjustment is the number of ccb clock cycles of del ay to inject before the delay chain. when leaving override mode (ovrd cleared) this course adjust poi nt serves as the starting point for a dynamic search for a lock point. 8?15 tap_sel tap select value to be used by the dll when in override mode (ovrd = 1). selects the tap point within the delay chain. when leaving override mode (ovrd cleared) this tap point serves as the starting point for a dynamic search for a lock point. 16?20 ? reserved 21?23 course_set reports the current course delay setting fo und by the dynamic search algorithm that produced a lock. measured in ccb clock cycles 24?31 tap reports the tap value found by the dynamic search algorithm that produced a lock. measured in tap points 4 datasheet u .com
global utilities MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 18-22 freescale semiconductor figure 18-18. e500 core power management state diagram for each operating state repres ented in the diagram, the core?s state is listed fi rst, with the corresponding state of the MPC8555E shown beneath it in parenthesi s. note that there are many other variables that control the state transitions betw een MPC8555E power management stat es. these additional variables are described in more detail in section 18.5.1.7, ?power-down sequence coordination.? table 18-21 lists basic characteristics of the low-power modes and the full on mode. 18.5.1.2 ckstp_in is not power management ckstp_in is not described here because it is not considered a power management signal, although asserting it does stop the core and a stopped core is technically in a low-power mode. ckstp_in is described in section 18.3.2, ?detailed signal descriptions.? table 18-21. MPC8555E power management modes?basic descriptions mode description core responds to signal states snoop interrupts ready asleep full on all units operating normally yes yes asserted negated doze core stops dispatching new instructio ns (core is halted) yes yes negated negated nap core is stopped with clocks off except to time base should flush data cache before entering no yes negated negated sleep core is stopped with clocks off. clocks powered down to all blocks (including core time base) except to the interrupt controller (pic) unit no yes negated asserted core-halted core-stopped core_halt & ? core_stop core_stop ? core_halt core_halt ? core_stop core_stop & core_halt full on ? core_halt (doze) (nap) core-stopped ? core_tben (sleep) ? core_tben core_tben 4 datasheet u .com
global utilities MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 18-23 18.5.1.3 dynamic power management many blocks in the MPC8555E can dynamically turn off clocks within the block when sections of the block are idle. this feature is alwa ys enabled and occurs automatically. 18.5.1.4 shutting down unused blocks as described in section 18.4.1.11, ?device disa ble register (devdisr),? devdisr provides a way to shut down certain functional blocks within the MPC8555E when they are not needed in a particular system. devdisr can be written by the e500 core or by an external master. powering down a block in this way turns off all clocks to that block. devdisr was designed with the expectation that, once initialized by software, it would be modified only by a hard system reset (hreset ). it is recommended that this re gister be written only during system initialization. blocks disabled by devdisr must not be re-enabled without a hard reset. (setting devdisr[tb] disables the core?s timer facilities, and setting devdi sr[e500] places the core in the core_stopped state in which it does not respond to in terrupts.) the results of re-enabling previously disabled blocks (by clearing the corresponding de vdisr field) without a hard reset are boundedly undefined. note functional blocks disabled us ing devdisr cannot respond to configuration accesses. any access to configuration, control, and status registers of a disabled bl ock is a programming error. 18.5.1.5 software-controlled power-down states the e500 software can place the device in doze, nap, or sleep power- down states by writing to hid0 in the core. in addition, external mast ers can write to the memory-ma pped powmgtcr in the MPC8555E to cause the device to enter doze or sleep modes. 18.5.1.5.1 doze mode in doze mode, the e500 core suspe nds instruction execution, significant ly reducing the power consumption of the core. snooping of the l1 data cache is still supported and thus the data in the data cache is kept coherent. interrupts directed to the core as described in section 10.1.3, ?interrupts to the processor core,? are monitored by the device and ca use the MPC8555E to use the defined handshake mechanism to exit the core from doze mode to al low the core to recognize and process th e interrupt; however, unless the interrupt subroutine turns off (or masks) th e control bits that enabled doze mode (msr[we], and hid0[doze]), the device re-enters doze mode after th e interrupt has been serviced. see section 18.5.1.8, ?interrupts and power management,? for more information. the e500 core?s timer facilities ar e still enabled during doze mode, and core time base interrupts can be generated. all device logic external to the core remains fully operational in doze mode. 4 datasheet u .com
global utilities MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 18-24 freescale semiconductor 18.5.1.5.2 nap mode in nap mode all clocks internal to th e e500 core are turned off except for its timer facilities clock (the core time base). the l1 caches do not respond to snoops in nap mode, so if coherency with external i/o transactions is required, the l1 cache must be flushed before entering nap mode. similar to doze mode, interrupts occu rring in nap mode cause the device to wake up the e500 core in order to service the interrupt. however, unless the interrupt service routine changes the control bits that caused the device to enter nap mode (msr[we], and hid0[n ap]), the MPC8555E returns to nap mode after the interrupt is serviced. see section 18.5.1.8, ?interrupts and power management,? for more information. all device logic external to the e500 core remains fully operational in nap mode. 18.5.1.5.3 sleep mode in sleep mode, all clocks internal to the e500 core ar e turned off, including the timer facilities clock. all i/o interfaces in the device logic are also shut down. only the cloc ks to the MPC8555E pic are still operational so that an external interrupt can wake up the device. note that the ddr controller does not shut down unless ddr_sdram_ interval[refint] is set to a non-zero value. see section 9.4.1.7, ?ddr sdram interval configur ation (ddr_sdram_interval),? for details.note that external interrupts from port c of the cpm are a special case and do not reach the pic when the device is asleep. therefore, they do not cause the device to wake up. after the core and i/o interfaces have shut down, asleep is asserted and ready is negated. note only external interrupts can wake th e MPC8555E from sleep mode. internal interrupt sources like the core inte rval timer or watchdog timer depend on an active clock for their operation a nd these are disabled in sleep mode. 18.5.1.6 power management control fields the e500 core provides the followi ng fields to signal power manage ment requests to the MPC8555E device logic. ? msr[we]?used to qualify the va lues of hid0[doze,nap,sleep] in the generation of the internal doze , nap , and sleep signals ? hid0[doze]?signals the mpc 8555e to initiate doze mode ? hid0[nap]?signals the mpc 8555e to initiate nap mode ? hid0[sleep]?signals the MPC8555E to initiate sleep mode these register fields and their f unctional relationship are shown in section 6.10.1, ?hardware implementation-dependent register 0 (hid0),? and section 6.5.1, ?machine st ate register (msr).? the e500 core family reference manual has details on accessing these pow er management control bits. an external master can also initia te power management requests by se tting the doz or slp bits in the memory-mapped power management control and status register (powmgtcsr). because the core responds to snoops while dozing but not while napping, maintaining cache coherency requi res significant 4 datasheet u .com
global utilities MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 18-25 preparation by the core before entering nap mode. for this reason only the core can initiate a nap during normal operation while other ma sters can initiate a doze. 18.5.1.7 power-down sequence coordination to preserve cache coherency and othe rwise avoid loss of system state, the core?s transition to low-power modes is coordinated by a set of handshaking signals, shown in figure 18-19 , and protocols with all other MPC8555E functional blocks that respond to power- down requests. the mode-transition protocol is executes automatically under thes e conditions and is shown in figure 18-18 and described in table 18-22 . the column in table 18-22 showing the global utiliti es block as initiating a low-power mode corresponds to the external masters that can write to the powm gtcsr that resides in the global utilities block. for the MPC8555E, these are the pci inte rfaces. however, note that the co re can also write to powmgtcsr and, in this case, can initiate power ma nagement through the gl obal utilities block. as shown in figure 18-19 , the e500 core enters low-power modes only in response to the core_halt , core_stop , or core_tben inputs from the MPC8555E power mana gement logic. these inputs may be prompted by the core (by setting the nap, doze, or sleep bits in the hid0 when enabled by setting msr[we]) or by an external master (by setting powmgtcsr[doz,slp]). figure 18-19 shows how all the clocking to the core timer facilities is disabled by clearing hid0[tben]. when enabled, (hid0[tben] = 1), the cl ock source is either the ccb cloc k divided by eight (the default) or a synchronized version of the rtc input. for more details, see section 6.10.1, ?hardware implementation-dependent register 0 (hid0).? table 18-22. power management entry protocol and initiating functional units low-power mode entry protocol initiating functional unit global utilities core doze 1. assert core_halt input to core. 2. wait for core_halted handshake from core. ? nap 1. follow doze protocol 2. assert core_stop input to core. 3. wait for core_stopped handshake from core. ? sleep 1. follow doze protocol; send stop requests to rest of device. 2. follow nap protocol. 3. wait for all interfaces to acknowledge stop requests. 4. assert asleep, negate ready, power down all clocks except to pic unit. ? 4 datasheet u .com
global utilities MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 18-26 freescale semiconductor figure 18-19. MPC8555E power management handshaking signals msr[we] hid0[nap] hid0[doze] hid0[sleep] sleep nap doze e500 core complex device logic core_halted core_stop core_halt core_tben stop fetching instructions instruction execution stopped? ye s no core_stopped stop clock distribution clock distribution stopped? ye s no hid0[sel_tbclk] 8 ccb clock rtc (sampled and synchronized) snoopable traffic stopped? ye s no powmgtcsr[doz] powmgtcsr[slp] note: all signals shown are internal to the device. ckstp_i hreset core_tbint core timer facilities core timer clock (time base) hid0[tben] processor interrupt sources (see ta b l e 1 0 - 1 and table 10-2 ) devdisr[tb]or[e500] devdisr[e500] all transactions that could have snooped are complete 4 datasheet u .com
global utilities MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 18-27 18.5.1.8 interrupts and power management whether low-power modes are automati cally re-enabled after an interrupt is processed di ffers depending on whether the low power mode was entered due to a write to the co re msr[we] bit or the low power mode was entered due to a write to powmgtcsr. 18.5.1.8.1 interrupts and power mana gement controlled by msr[we] when an interrupt is asserted to the cpu, the core complex saves portions of the msr to mcsrr1, csrr1, or srr1 (depending on the type of interrupt), a nd restores those values on return from the routine. msr[we], which gates the doze , nap , and sleep power management outputs (i nternal device signals) from the core complex, is always among the bits saved and restored; hence these outputs negate to the MPC8555E power management logic when the interrupt begins processing in the core. they return to their previous state when the core executes an rfi , rfci , or rfmci instruction. section 10.1.3, ?interrupts to the processor core,? lists interrupts that cause the MPC8555E to wake up. note returning doze , nap , and sleep signals to their original state when msr[we] is restored differs from how power management is implemented on earlier devices where msr[pow], which enables power-down requests, is cleared when the processor ex its a low-power state and is not automatically restored, as it is in book e implementations. 18.5.1.8.2 interrupts and power mana gement controlled by powmgtcsr the irq_msk and ci_msk fields of the powmgtcsr register prevent int interrupts or cint critical interrupts from waking the device from a low power stat e. this is true regardless of the method used to enter the low power state. any unmasked interrupt (n ot masked by the mask bits in the powmgtcsr register) causes the powmgtcsr[doz,slp] fields to be cleared when it occurs. when such an interrupt occurs, the device returns to the normal operating mode and does not auto matically attempt to return to a low power state after the interrupt is handled. note that interrupts caused by the unconditional debug event (ude ) and machine check (mcp ) signals are not masked by the irq_msk and ci_msk fields; therefore, when these signals assert, the powmgtcsr[doz,slp] fields are cleared and the device will return to full power operation. see section 18.4.1.12, ?power manageme nt control and status register (powmgtcsr),? for detailed information about the bits of powmgtcsr. note also that unmasked interrupts that occur while the device is in the process of going into the sleep state (before sleep is completely attained) can also cau se the device to clear the powmgtcsr[doz,slp] fields and return the device to full power operation. 18.5.1.9 snooping in power-down modes when the MPC8555E is in doze mode, th e e500 core is in the core-halted state and it snoops its l1 caches and full coherency is maintaine d. in deeper power-down modes, how ever, the e500 core does not respond to snoops. 4 datasheet u .com
global utilities MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 18-28 freescale semiconductor the MPC8555E does not perform dynamic bus snooping as described in the e500 reference manual . that is, when the e500 core is in the core-stopped state (w hich is the state of the core when the MPC8555E is in either the nap or sleep state), the core is not awakened to perform s noops on global transactions. therefore, before entering nap or sleep modes, the l1 caches should be flushed if coherency is required during these power-down modes. 18.5.1.10 software considerations for power management setting msr[we] generates a request to the MPC8555E logic (external to the core complex) to enter a power saving state. it is assumed that the desired power-saving state (doze, nap, or sleep) was set up by setting the appropriate hid0 bit, typically at system start-up time. setting we has no direct effect on instruction execution, but is reflected on the internal doze , nap , and sleep signals, depending on the hid0 settings. to ensure a clean transi tion into and out of a power-saving mode, the following program sequence is recommended: sync mtmsr (we) isync loop: br loop 18.5.1.11 requirements for reaching and recovering from sleep state in order to successfully reach the sl eep state, i/o traffic to the devi ce must be stopped. the logic that controls the power down sequence waits for all i/o interfaces to become idle. in some applications this may happen eventually without activel y shutting down interfaces, but most likely, software will have to take steps to shut down the tsecs, cpm, and pci in terfaces before issuing the command (either the write to the core msr[we] as described above or writing to powmgtcsr) to put the device into sleep state. the pci interfaces will begin retrying inbound transact ions before entering a pow er down state. the pci interfaces, however, could potentially be in an unknown state when they exit sleep if they were in the middle of a retry sequence when inte rnal clocks were shut down. theref ore it is strongly recommended that system software clear the memory space bit in the pci bus command re gister before putting the device in sleep mode. software may also need to set the agent config lock bit of the pci bus function register so that the device will not respond to c onfiguration transactions. upon exiting sleep mode, software should return these configuration bits to their normal state. 18.5.2 general-purpose i/o signals certain groups of signals can optiona lly be used as general-purpose i/o signals when not being used for their primary function. the general-purpose i/o functio nality of these signals can be enabled through configuration registers in th e global utilities block. thes e signals are the following: ? pci2_ad[15:8] and pci2_ad[7:0]. when confi gured as general-purpos e i/o, pci2_ad[15:8] function as outputs and pci2_ ad[7:0] function as inputs. pci2_ad[15:0] can be used as gene ral-purpose i/o if the pci2 interface is disabled or if the pci1 controller is disabled or in 32-bit mode. ? tsec2_rxd[0:7] and tsec2_txd[0:7]. tsec2 pins are fixed as either inputs or outputs based on the direction of the signal?s primary functi on. the tsec2_txd pins are always outputs, so 4 datasheet u .com
global utilities MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 18-29 these signals may only be used as outputs when configured as gene ral-purpose i/o. similarly, the tsec2_rxd pins are used as inputs wh en configured as general-purpose i/o. the tsec2 txd and rxd pins are available when the tsec2 block is disabled. the txd signals can then be enabled as general-purpose out puts and the rxd pins can be enabled as general-purpose inputs. when configured as general-purpose i/o signals, softwa re can read inputs by reading the associated gpio data register. output values can be set by writing th e to the associated gpio data register. for details regarding the control a nd status of the genera l-purpose i/o signals, see section 18.4.1.7, ?general-purpose i/o control register (gpiocr).? 18.5.3 interrupt and local bus signal multiplexing except for the cpm, the MPC8555E has very littl e signal multiplexing. two sets of dma channel triggering signals can alte rnately be placed on ot her signals as follows: ?lcs [5:7] are multiplexed with dma channel 2 dma_dreq2 , dma_dack2 , and dma_done2 . ? irq[9:11] are multiplexed with dma channel 3 dma_dreq3 , dma_dack3 , and dma_ddone3 . for details regarding the selection of the alternate function dma trigger, see section 18.4.1.10, ?alternate function signal multiplex c ontrol register (pmuxcr).? the multiplexing of the cp m signals occurs through the cpm programming model. see chapter 45, ?parallel i/o ports,? for details on cpm signal multiplexing. 4 datasheet u .com
global utilities MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 18-30 freescale semiconductor 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 19-1 chapter 19 performance monitor this chapter describes the MPC8555E performance moni tor facility, which can be used to monitor and optimize performance. the e500 core implements a separate performance monitor for strictly core-related behavior, such as instruction timing and l1 cache operations. this is described in the powerpc? e500 core family reference manual (freescale document e500corerm). section 19.4.7, ?performance monitor events,? briefly describes the events that can be monitored. refer to the individual chapters for a better understanding of these events. 19.1 introduction the MPC8555E includes a performance monitor facility that can be used to monitor and record selected behaviors of the integrated device. although the performance monitor de scribed here is similar in many respects to the performance monito r facility implemented on the e500 core, it differs in that it is implemented using memory-mapped re gisters and it counts events outside the e500 core, for example, pci, ddr, and l2 cache events. performance monitor counters (pmc 0?pmc8) are used to count even ts selected by the performance monitor local control registers. pmc0 is a 64-bit counter specifically desi gnated to count cycles. pmc1?pmc8 are 32-bit counters that can monitor 64 c ounter-specific events in addition to counting 64 reference events. the benefits of the on-chip performance monitor are numerous , and include the following: ? because some systems or software environments are not easily ch aracterized by signal traces or benchmarks, the performance mon itor can be used to understand th e MPC8555E behavior in any system or software environment. ? the performance monitor facilit y can be used to aid system developers when bringing up and debugging systems. ? system performance can be increased by monitoring memory hierarchy behavior. this can help to optimize algorithms used to schedul e or partition tasks and to re fine the data structures and distribution used by each task. 19.1.1 overview figure 19-1 is a high-level block di agram of the performance monitor, which consists of a global control register (pmgc0), one 64-bit counter (pmc0), eight 32-bit counters, and two control regist ers per counter 4 datasheet u .com
performance monitor MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 19-2 freescale semiconductor (18 total control registers) . the global control regist er pmgc0 affects all counter s and takes priority over local control registers. the local control regi sters are divided into two groups, as follows: ? local control a registers control counter freezi ng, overflow condition enable , event selection, and burstiness. local control regist er pmlca0, which controls count er pmc0, does not contain event selection because pmc0 counts only cycles. ? local control b registers control the start a nd stop triggering, contain the counters? threshold values, and the value of the threshold multiplier . local control register pmlcb0, which controls pmc0, does not contain threshold inform ation because pmc0 only counts cycles. figure 19-1. performance monitor block diagram performance monitor events are si gnaled by the functional blocks in the integrated device and are selectively recorded in the pmcs. sixt y-four of these events are referred to as reference events, which can be counted on any of the eight count ers. counter-specific events can be counted only on the counter where the event is defined. the performance monitor can generate an interrupt on overflow. several contro l registers specify how a performance monitor interrupt is signaled. the pmcs can al so be programmed to freeze when an interrupt is signaled. counters global control register pmgc0 pmlca3 pmlcb3 pmlca2 pmlcb2 pmlca1 pmlcb1 pmlca0 pmlcb0 pmc1 pmc2 pmc3 ... control logic counters and registers performance monitor event 1 event 2 event 8 event 3 event 4 ... event signals interrupt ( int ) read data output signals pmc8 pmlca8 pmlcb8 event 0 pmc0 (upper) pmc0 (lower) 32-bit local control registers ... ... 4 datasheet u .com
performance monitor MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 19-3 19.1.2 features the MPC8555E performance monitor offe rs a rich set of features that permits a complete performance characterization of the implemen tation. these features include: ? one 64-bit counter exclusively dedicated to counting cycles ? eight 32-bit counters that count the occurrence of selected events ? one global control register (affects all counte rs) and two local control registers per counter ? ability to count up to 64 reference events that may be counted on any of the eight 32-bit counters ? ability to count up to 512 counter-specific events ? triggering and chaining capability ? duration threshold counting ? burstiness feature that permits counting of burst events with a programmable ti me between bursts ? ability to generate an interrupt on overflow 19.2 signal descriptions the performance monitor does not have any signals that are driven extern ally (off-chip) but it does assert the internal interrupt ( int ) signal on a performance m onitor interrupt condition. 19.3 memory map and register definition performance monitor registers reside in the run-time register block starting at offset 0xe_1000. undefined 4-byte address spaces within offset 0x000?0xfff are re served. this section describes the registers implemented to support the perf ormance monitor facilities. table 19-1 lists the performance monitor registers. these registers can be read or written only with 32-bit accesses. 19.3.1 register summary the performance monitor uses nine c ounter registers and a group of local c ontrol registers that are used to specify the method of counting. two local control registers are associated with each counter in addition to a global control register th at applies to all counters. table 19-1. control register memory map address offset (in hex) register access reset section/page 0xe_1000 pmgc0?performance monitor gl obal control register r/w 0x0000_0000 19.3.2.1/19-5 0xe_1010 pmlca0?performance monitor local control register a0 r/w 0x0000_0000 19.3.2.2/19-5 0xe_1014 pmlcb0?performance monitor local control register b0 r/w 0x0000_0000 19.3.2.2/19-5 0xe_1018 pmc0 (upper)?performance monitor counter 0 upper r/w 0x0000_0000 19.3.3.1/19-9 0xe_101c pmc0 (lower)?performance monitor counter 0 lower r/w 0x0000_0000 19.3.3.1/19-9 0xe_1020 pmlca1?performance monitor local control register a1 r/w 0x0000_0000 19.3.2.2/19-5 4 datasheet u .com
performance monitor MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 19-4 freescale semiconductor in addition to these registers, the in terrupt control provides four pairs of mask register s that can be used to monitor message, interprocessor, tim er, and external interrupts. see section 10.3.4, ?performance monitor mask registers (pmmrs).? 0xe_1024 pmlcb1?performance monitor local control register b1 r/w 0x0000_0000 19.3.2.2/19-5 0xe_1028 pmc1?performance monitor counter 1 r/w 0x0000_0000 19.3.3.1/19-9 0xe_1030 pmlca2?performance monitor local control register a2 r/w 0x0000_0000 19.3.2.2/19-5 0xe_1034 pmlcb2?performance monitor local control register b 2 r/w 0x0000_0000 19.3.2.2/19-5 0xe_1038 pmc2?performance monitor counter 2 r/w 0x0000_0000 19.3.3.1/19-9 0xe_1040 pmlca3?performance monitor local control register a3 r/w 0x0000_0000 19.3.2.2/19-5 0xe_1044 pmlcb3?performance monitor local control register b3 r/w 0x0000_0000 19.3.2.2/19-5 0xe_1048 pmc3?performance monitor counter 3 r/w 0x0000_0000 19.3.3.1/19-9 0xe_1050 pmlca4?performance monitor local control register a4 r/w 0x0000_0000 19.3.2.2/19-5 0xe_1054 pmlcb4?performance monitor local control register b4 r/w 0x0000_0000 19.3.2.2/19-5 0xe_1058 pmc4?performance monitor counter 4 r/w 0x0000_0000 19.3.3.1/19-9 0xe_1060 pmlca5?performance monitor local control register a5 r/w 0x0000_0000 19.3.2.2/19-5 0xe_1064 pmlcb5?performance monitor local control register b 5 r/w 0x0000_0000 19.3.2.2/19-5 0xe_1068 pmc5?performance monitor counter 5 r/w 0x0000_0000 19.3.3.1/19-9 0xe_1070 pmlca6?performance monitor local control register a6 r/w 0x0000_0000 19.3.3.1/19-9 0xe_1074 pmlcb6?performance monitor local control register b6 r/w 0x0000_0000 19.3.2.2/19-5 0xe_1078 pmc6?performance monitor counter 6 r/w 0x0000_0000 19.3.3.1/19-9 0xe_1080 pmlca7?performance monitor local control register a7 r/w 0x0000_0000 19.3.2.2/19-5 0xe_1084 pmlcb7?performance monitor local control register b7 r/w 0x0000_0000 19.3.2.2/19-5 0xe_1088 pmc7?performance monitor counter 7 r/w 0x0000_0000 19.3.3.1/19-9 0xe_1090 pmlca8?performance monitor local control register a8 r/w 0x0000_0000 19.3.2.2/19-5 0xe_1094 pmlcb8?performance monitor local control register b8 r/w 0x0000_0000 19.3.2.2/19-5 0xe_1098 pmc8?performance monitor counter 8 r/w 0x0000_0000 19.3.3.1/19-9 table 19-1. control register memory map (continued) address offset (in hex) register access reset section/page 4 datasheet u .com
performance monitor MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 19-5 19.3.2 control registers this section describes the performance monitor control registers in detail. 19.3.2.1 performance monitor glo bal control register (pmgc0) the performance monitor global cont rol register (pmgc0), shown in figure 19-2 , is a 32-bit register used to control all pmcs. figure 19-2. performance monitor global control register (pmgc0) table 19-2 describes pmgc0 fields. 19.3.2.2 performance monitor loc al control registers (pmlca n , pmlcb n ) the performance monitor local control registers (pmlca n and pmlcb n ) are used to control the operation of the pmcs. the performanc e monitor local control a and b re gisters are paired 32-bit control registers that are associated with an individual counter to specify how the counter is used and what event is monitored on that counter. 01 23 31 r fac pmie fcece 00000000000000000000000000000 w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0xe_1000 table 19-2. pmgc0 field descriptions bits name description 0 fac freeze all counters. 0 pmcs are incremented (if permitt ed by other pmgc0/pmlc bits). 1 pmcs are not incremented. set by hardware when an interrupt is signaled and fcece = 1. 1 pmie performance monitor interrupt enable. interrupts are caused by pmc overflows. 0 interrupts are disabled. 1 interrupts are enabled and occur when an enabled condition or event occurs. 2 fcece (discount) freeze counters on enabled condition or event. an enabled condition or event is defined as: the msb = 1 in pmc n and pmlca n [ce] = 1. the use of the trigger and freeze counter c onditions depends on the enabled condition. 0 pmcs can be incremented (if permitted by other control bits). 1 pmcs can be incremented (if permitted by other control bits) only until an enabled condition or event occurs, at which time pmgc0[fac] is set. it is up to software to clear fac. 3?31 ? reserved 4 datasheet u .com
performance monitor MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 19-6 freescale semiconductor figure 19-3 shows the performance monitor loca l control a0 regi ster (pmlca0). figure 19-3. performance monitor local control register a0 (pmlca0) table 19-3 describes pmlca0 fields. figure 19-4 shows the performance monitor local control registers a1?a8. figure 19-4. performance monitor local control a registers (pmlca1?pmlca8) table 19-4 describes pmlca n fields. 01 456 31 r fc 0000 ce 00000000000000000000000000 w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0xe_1010 table 19-3. pmlca0 field descriptions bits name description 0 fc freeze counter. basic counter enable. 0 the pmcs are enabled and incremented (if permitted by other spm control bits). 1 the pmcs are disabled?they do not increment. 1?4 ? reserved 5 ce condition enable. controls counter overflow condition. should be cleared when pmc0 is used as a trigger or is selected for chaining. 0 overflow conditions for pmc0 cannot occur (pmc0 cannot cause interrupts or freeze counters) 1 overflow conditions occur when pmc0[msb] is set. 6?31 ? reserved 0 1 4 5 6 8 9 15 16 20 21 25 26 31 r fc 0000 ce 000 event bsize bgran bdist w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0xe_1020, 0xe_1030, 0xe_1040, 0xe_1050, 0xe_1060, 0xe_1070, 0xe_1080, 0xe_1090 table 19-4. pmlca1?pmlca8 field descriptions bits name description 0 fc freeze counter 0 the pmcs are incremented (if permitted by other pmc control bits). 1 the pmcs are not incremented (if permitted by other pmc control bits). 1?4 ? reserved 4 datasheet u .com
performance monitor MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 19-7 figure 19-5 shows the performance monitor loca l control b0 regi ster (pmlcb0). figure 19-5. performance monitor local control register b0 (pmlcb0) table 19-5 describes pmlcb0 fields. 5 ce condition enable 0 overflow conditions for pmc n cannot occur (pmc n cannot cause interrupts or freeze counters). should be cleared when pmc n is used as a trigger or is selected for chaining. 1 overflow conditions occur when pmc n [msb] is set. 6?8 ? reserved 9?15 event event selector. up to 128 events selectable. see table 19-10 for definition of events. 16?20 bsize burst size. fewest event occurrenc es that constitute a burst, that is , a rapid sequence of events followed by a relatively long pause. a value less than two implie s regular event counting. any non-threshold, regular event may be counted in a bursty fashion. see section 19.4.6, ?burstiness counting,? for more information. 21?25 bgran burst granularity. the maximum number of clock cycles between events that are considered part of a single burst. see section 19.4.6, ?burstiness counting.? 26?31 bdist burst distance (used with tbmu lt). the number of clock cycles between bursts. must be set to a value greater than bsize for proper burstiness counting behavior. 00_0000 regular counting 01 2 5 67 8 11 12 13 14 15 16 31 r00 trigonsel 00 trigoffsel trigo ncntl trigoffcntl 0 00000000000000 0 w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0xe_1014 table 19-5. pmlcb0 field descriptions bits name description 0?1 ? reserved 2?5 trigonsel trigger-on select. the number of the count er that starts event count ing. when the specified counter?s trigoncntl event overflows, the current counter begins counting. no triggering occurs if the value is self-referential, that is , when set to the current counter number. 6?7 ? reserved 8?11 trigoffsel trigger-off select. the number of the counter that stops event co unting. when the specified counter?s trigoncntl event overflows, the current counter stops counting. no triggering occurs if the value is self-referential, that is , when set to the current counter number. 12?13 trigoncntl trigger-on control. indicates the conditi on under which triggering to start counting occurs 00 trigger off (no triggering to start) 01 trigger on change 10 trigger on overflow 11 reserved table 19-4. pmlca1?pmlca8 field descriptions (continued) bits name description 4 datasheet u .com
performance monitor MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 19-8 freescale semiconductor figure 19-6 shows performance monitor local control registers 1?8. figure 19-6. performance monitor loca l control register b (pmlcb1?pmlcb8) table 19-5 describes pmlcb n fields. 14?15 trigoffcntl trigger-off control. indicates the condition under which triggering to stop occurs 00 trigger off (no triggering to stop) 01 trigger on change 10 trigger on overflow 11 reserved 16?31 ? reserved 01 2 5 67 8 11 12 13 14 15 16 20 21 23 242526 31 r00 trigonsel 00 trigoffsel trigon cntl trigoffcntl 0 000 0 tbmult 00 threshold w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0xe_1024, 0xe_1034, 0xe_1044, 0xe_1054 , 0xe_1064, 0xe_1074, 0xe_1084, 0xe_1094 table 19-6. pmlcb1?pmlcb8 field descriptions bits name description 0?1 ? reserved 2?5 trigonsel trigger-on select. set this field equal to the number of the counter that should trigger event counting to start. when the specified co unter?s trigoncntl event overflow s, the current counter begins counting. no triggering occurs when trigonsel = current counter. 6?7 ? reserved 8?11 trigoffsel trigger-off select. set this field equal to the number of the c ounter that should trigger event counting to stop. when the specified counter?s trigoncntl event overflows, the current counter stops counting. no triggering occurs when trigoffsel = current counter. 12?13 trigoncntl trigger-on control. indicates the conditi on under which triggering to start counting occurs 00 trigger off (no triggering to start) 01 trigger on change 10 trigger on overflow 11 reserved 14?15 trigoffcntl trigger-off control. indicates the condition under which triggering to stop occurs 00 trigger off (no triggering to stop) 01 trigger on change 10 trigger on overflow 11 reserved 16?20 ? reserved table 19-5. pmlcb0 field descriptions (continued) bits name description 4 datasheet u .com
performance monitor MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 19-9 19.3.3 counter registers this section describes the pmcs in detail. note because accessing a pmc ma nually has priority over incrementing it due to event counting, reading or writing a pmc while it is counting may affect the count. likewise, accessing a performanc e monitor control register while its target counter is counting may also affect the count. 19.3.3.1 performance monitor counters (pmc0?pmc8) pmc0?pmc8 are used to count events selected by the performance monito r local control re gisters. pmc0, shown in figure 19-7 , is associated with two 32-bit registers th at form a 64-bit counter designated to count clock cycles. pmc0 upper represents the upper 32 bits of counter 0, and pmc0 lower represents the lower 32 bits. figure 19-7. performance monitor counter register 0 (pmc0) table 19-7 describes pmc0 fields. 21?23 tbmult threshold and burstiness multiplier. threshol d events are counted when the event duration exceeds a specified threshold value. the threshold is scaled based on the tbmult settings. the burst distance for burstiness counting is also scaled usin g the tbmult settings. fo r all events that scale the threshold, the threshold field is multiplied by the factors shown below (ranging from 1 to 128). 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 24?25 ? reserved 26?31 threshold threshold. only events whose (number of) o ccurrences exceed this value are counted. by varying the threshold value, software can characterize the events subject to the threshold. for example, if pmc2 countstsec bd read latencies for which the duration exceeds the threshold, software can obtain the distribution oftsec bd read latencies for a given program by monitoring the program repeatedly using a different threshold value each time. 0313263 r pmc0 upper pmc0 lower w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0xe_1018 0xe_101c table 19-6. pmlcb1?pmlcb8 field descriptions (continued) bits name description 4 datasheet u .com
performance monitor MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 19-10 freescale semiconductor . pmc1?pmc8, shown in figure 19-8 , are 32-bit counters that can monitor 64 unique ev ents in addition to the 64 reference events that can be counted on all of these registers. figure 19-8. performance monitor counter register (pmc1?pmc8) table 19-8 describes pmc n fields. 19.4 functional description this section describes the use of some features of the performance monitor. 19.4.1 performance monitor interrupt pmcs can generate an interrupt on an overflow when the msb of a counter changes from 0 to 1. for the interrupt to be signaled, the condition enable bit (pmlca n [ce]) and performance monitor interrupt enable bit (pmgc0[pmie]) must be set. when an interrupt is signaled and the freeze-counters-on-enabled-condition- or-event bit (pmgc0[fcece]) is set, pmgc0[fac] is set by hardware and all of the registers are frozen. software can clear th e interrupt condition by resetting the performance monitor and clearing the most significan t bit of the counter that generated the overflow. 19.4.2 event counting using the control registers described in section 19.3.2, ?control registers,? the nine pmcs can count the occurrences of specific events. the 64-bit pmc0 is designated to count only clock cycles. however, to provide flexibility, a total of 64 reference even ts can be counted on any of the 32-bit pmcs (pmc1?pmc8). additionally, up to 64 unique ev ents can be counted on each 32-bit counter. the performance monitor must be reset before event counting seque nces. the performance monitor can be reset by first freezing one or more counters and then clearing th e freeze condition to allow the counters to count according to the settings in the perfor mance monitor registers.tc ounters can be frozen table 19-7. pmc0 field descriptions bits name description 0?63 pmc0 event count. counts only clock cycles 0 31 r pmc n w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0xe_1028, 0xe_1038, 0xe_1048, 0xe_10 58, 0xe_1068, 0xe_1078, 0xe_1088, 0xe_1098 table 19-8. pmc1?pmc8 field descriptions bits name description 0?31 pmc n event count. an overflow is indicated when the msb = 1. manually setting the msb can cause an immediate interrupt. 4 datasheet u .com
performance monitor MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 19-11 individually by setting pmlcan[fc] bits, or simultaneously by setti ng pmgc0[fac]. simply clearing these freeze bits wi ll then allow the performance monitor to be gin counting based on the register settings. note that using pmlcan[fc] to reset the perfor mance monitor resets only the specified counter. performance monitor registers can be configured through reads or writes while the counters are frozen as long as freeze bits are not cl eared by the register accesses. 19.4.3 threshold events the threshold feature allows characterization of events that can take a variable number of clock cycles to occur. threshold events are counted only if the latency is greater than the threshold value specified in pmlcb n [threshold]. for duration threshold event sequences, the pmc increm ents only when the duration of the event is equal to or greater than the threshold value. the thre shold value is scaled by a multiple specified in pmlcb n [tbmult]. a threshold event requires two signa ls: the first indicates when a th reshold event sequence begins, and the second indicates when it ends. an internal counter determines when the threshold count is exceeded and when the pmc can increment. this internal counter decrements during a threshold event sequence until it reaches the value of one. a new sequence cannot begin until the current one completes. additional threshold start signals are ignored during a sequence until a threshold stop signal occurs. if both a start and stop signal are asserted during the same cycle in a current sequence, the stop terminates the current sequence and the start signals the beginning of a new one. however, if both signals are asserted during the same cycle while not in a current even t sequence, both signals are ignored. figure 19-9 is a timing diagram for duration threshold event counting. an illegal condition exists if the threshold value obt ained from pmlcb n [threshold] and pmlcb n [tbmult] is less than two. under these condi tions the intent of threshold counting is ambiguous. 4 datasheet u .com
performance monitor MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 19-12 freescale semiconductor figure 19-9. duration threshold event sequence timing diagram 19.4.4 chaining by configuring one counter to incr ement each time anothe r counter overflows, several counters can be chained together to provide event c ounts larger than 32 bits. each counter in a chain adds 32 bits to the maximum count. the register chaining sequence is not arbitrary and is sp ecified indirectly by selecting the register overflow event to be counte d. selecting an event has the effect of selecting a source register because all available chaining events, as shown in table 19-10 , are dedicated to specific registers. note that the chaining overflow ev ent occurs when the c ounter reaches it s maximum value and wraps, not when the register?s msb is set. for this overflow to occur, pmlca n [ce] should be cleared to avoid signaling an interrupt when the count er?s most significant bit is set. note that several cycles may be required for the chained counters to reflect the true c ount because of the internal delay between when an overflow occurs and a counter increments. 19.4.5 triggering triggering allows one counter to st art or stop counting on the change of another counter or on the overflow of another counter. more specifically, if pmc1 is set to start or stop counting as a result of a change or overflow in counter pmc2, th en counter pmc2 must be identified in the local c ontrol register of counter pmc1. this is done by appropriate ly setting the trigger-on select bit or trigger-off select bit (pmlcb1[trigoffsel] or pmlcb1 [trigonsel]). additionally, th e condition that triggers the counter must be selected by configuring the corresponding control bits (pmlcb1[trigoncntl] or pmlcb1[trigoffcntl]). assuming the counter is en abled by other control re gister settings, the counter increments (or freezes) when its specified ev ent occurs after the trigger-on (or off) condition occurs. thresh_value thresh_start thresh_stop thresh_counter thresh_exceeded 32 1 3 32 1 2 3 1 0 3 pmlcb n [threshold] pmlcb n [tbmult] perfmon_counter 0 1 2 123456789101112 1 for this example a threshold value of three indicates that the user wishes to count the number of times a particular event lasts three cycles or longer. 4 datasheet u .com
performance monitor MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 19-13 when trigger on and trigger off are both selected, the trigger-off condition is ignored until the trigger-on condition has occurred. furtherm ore, when a trigger-off condition occurs , the counter state is preserved; it is not restarted by subse quent trigger-on conditions. triggering is disabled when the counter?s trigger-select bits specify itself as th e trigger source. similarly, triggering is disabled when the trigger control bits are cleared. 19.4.6 burstiness counting the burstiness counting feature make s it easier to characterize events that occur in rapid succession followed by a relatively long pause. as shown in table 19-9 , event bursts are defined by size, granularity, and distance. figure 19-10 shows the relationships between size, granularity, and distan ce. burstiness counting can be performed for all events except threshold events. figure 19-10. burst size, distance, granularity, and burstiness counting the burstiness size field (pmlca n [bsize]) specifies the minimum num ber of event occurrences that constitute a burst. a burst is id entified when the number of even t occurrences equals or exceeds pmlca n [bsize]. furthermore, these individual event o ccurrences must be separated by no more clock cycles than the value in the burstiness granularity field (pmlca n [bgran]). note that, although a burst is identified when the minimum number of events oc curs, it is not counted unt il the burst sequence has ended. a burst sequence ends when the specified burstiness gra nularity is exceeded, at which point the last valid event has occurred for that sequence. pmlca n [bgran] specifies the maximum number of cycl es between individual events for them to qualify as members of the same burst sequence. the burstiness distance field (pmlca n [bdist]) and threshold/bur stiness multiplier field (pmlcb n [tbmult]) specify the acceptable number of cycl es between the end of a burst sequence and the beginning of a new sequence for a group of event occurrences to be c ounted as an individual burst. the product of the burstiness distance field and the threshold/burstines s multiplier field determine the table 19-9. burst definition parameter description register field size the minimum number of events constituting a burst pmlca n [bsize] granularity the maximum time between individual events counted as members of the same burst pmlca n [bgran] distance the minimum time between bursts pmlca n [bdist] x pmlcb n [tbmult] burst size burst granularity event occurrence time burst size burst distance (cycles) 4 datasheet u .com
performance monitor MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 19-14 freescale semiconductor burstiness distance value used to determine when a nother burst sequence can begin. note that the burst distance count begins when a new burst sequence ends and the pmc is incremented. no new burst sequence may begin until th e burst distance count has reached zero. after the burst distance count reaches zero, it holds the zero value indica ting that a new burst sequence can be counted. the burst distance count begins again when a new burst sequence is identified and counted. burstiness counting is disabl ed when the definition of a burst is am biguous, that is, when the burst size field is less than two, or the burst distance is zero. when burstiness c ounting is disabled, regular counting is allowed. figure 19-10 shows that the burst distance is measured from the end of on e burst sequence and that a new burst sequence may not begin until the burst distan ce count expires. three internal counters track the differen t values required for burstiness counting. ? burstiness size is monitored by a c ounter. it is loaded with the valu e specified in the local control register when the burst granular ity counter and the burst distan ce counters reach zero, and no new event is occurring. it always decrements when th e following conditions o ccur: its value is not already zero, an event occurs, and the burst distance count equals zero. ? burstiness granularity is monitored by a counter that is loaded with the specified value in the local control register on the rising edge of an event occurrence whenever the burst distance count equals zero. the granularity counter is de cremented (if it has not already reached zero) when an event is not occurring and burst distance count equals zero. ? burstiness distance is measured by a counter that is loaded with the product of pmlcb n [bdist] and pmlcb n [tbmult] when a burst sequence has been identified and counted . this counter is decremented when burstiness counting is enabled (and the counter has not already reached zero). a burst is counted at the end of a burst sequence when the three burst parameter counters are all equal to zero. figure 19-11 shows a burstiness counting example. figure 19-11. burstiness counting timing diagram burst size counter burst granularity counter burst distance counter pmlcb n [bgran] pmlcb n [bsize] 123456789101112 pmlcb n [bdist] pmlcb n [tbmult] burst count 14 15 16 17 18 19 20 21 22 23 24 25 13 26 1 0 1 01 4 53210 5 0 4 32 1 0 1 54 1 5 4 1 (multiply by 2) 1 0 0 4321 0 1 for this example: count bursts of 5 event occurrences, burst granularity of 1, and acceptable distance between bursts of 8 (product of tbmult and bdist). 8 7 6 5 4 datasheet u .com
performance monitor MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 19-15 19.4.7 performance monitor events table 19-10 lists performance monitor even ts specified in pmlca1?pmlc8. the event assignment column indicates the event? s type and number, using the following formats: ? ref:#?reference events are shared across counters pmc1?pmc8. the number indicates the event. for example, ref:6 means that pmc1?pmc8 share reference event 6. ? c[0?8]:#?counter-specific events. c8 indicates an event assigned to pmc8. thus c8:62 means pmc8 is assigned event 62 (pic interrupt wait cycles). note that with counter-specific events, an offset of 64 must be used wh en programming the field, because counter-specific events occupy the bottom 64 values of the 7-bit event field where events are numbered. for example, to specify counter- specific event 0, the event field must be programmed to 64. counter events not specified in table 19-10 are reserved. table 19-10. performance monitor events event counted number descrip tion of event counted general events nothing ref:0 register counter holds current value system cycles c0 ccb (platform) clock cycles ddr memory controller events cycles a read is returning data from ddr sdram ref:10 each data beat returned to the memory controller on the ddr sdram interface cycles a read or write transfers data from (or to) ddr sdram ref:11 each data beat transferred to or from the ddr sdram pipelined read misses in the row open table c1:57 row open table read misses issued while a read is outstanding pipelined read or write misses in the row open table c2:0 row open table read or write misses issued while a read or write is outstanding non-pipelined read misses in the row open table c3:60 row open table read misses issued when no reads are outstanding non-pipelined read or write misses in the row open table c4:0 row open table read or write misses issued when no reads or writes are outstanding pipelined read hits in the row open table c5:56 row open table read hits issued when a read is outstanding pipelined read or write hits in the row open table c6:0 row open table read or write hits issued when a read or write is outstanding non-pipelined read hits in the row open table c7:57 row open table read hits issued when no reads are outstanding non-pipelined read or write hits in the row open table c8:0 row open table read or write hits issued when no reads or writes are outstanding 4 datasheet u .com
performance monitor MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 19-16 freescale semiconductor forced page closings not caused by a refresh c1:0 precharges issued to the ddr sdram for any reason except refresh. the possibilities are as follows: ? a new transaction must be issued to an already active bank and sub-bank that has a different row open. ? a new transaction must be issued, but the row open table is full and there is no bank/sub- bank match between the current transaction and the row open table. ? the bstopre interval expired for an open row. row open table misses c2:1 transactions that miss in the row open table row open table hits c3:0 transaction that hit in the row open table force page closings c4:1 forced page closings including those due to refreshes read-modify-write transactions due to ecc c5:0 if ecc is enabled and a transaction requires byte enables, a read-modify-write sequence is issued on the ddr sdram interface. forced page closings due to collision with bank and sub-bank ref:12 increments if a new transaction must be issued to an active bank and sub-bank that has a different row open reads or writes from core ref:13 ? reads or writes from tsec 1 c3:1 ? reads or writes from tsec 2 c4:2 ? reads or writes from cpm c5:1 ? reads or writes from pci c4:3 ? reads or writes from dma c5:2 ? row open table hits for reads or writes from core ref:14 ? row open table hits for reads or writes from tsec 1 c6:1 ? row open table hits for reads or writes from tsec 2 c7:0 ? row open table hits for reads or writes from cpm c8:1 ? row open table hits for reads or writes from pci c7:1 ? row open table hits for reads or writes from dma c8:2 ? memory target queue events mem tq read/write address collision c5:5 ? misaligned engine priority 2 occupied c5:12 misaligned engine for priority 2 transactions busy misaligned engine priority 1 occupied c6:12 ? misaligned engine priority 0 occupied c7:10 misaligned engine for priority 0 transactions busy table 19-10. performance monitor events (continued) event counted number descrip tion of event counted 4 datasheet u .com
performance monitor MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 19-17 ack history queue full c4:61 unacked packets are outstanding. dma controller events channel 0 read request c1:2 dma channel 0 read request active in the system channel 1 read request c2:5 dma channel 1 read request active in the system channel 2 read request c3:4 dma channel 2 read request active in the system channel 3 read request c4:6 dma channel 3 read request active in the system channel 0 write request c1:3 dma channel 0 write request active in the system channel 1 write request c2:6 dma channel 1 write request active in the system channel 2 write request c3:5 dma channel 2 write request active in the system channel 3 write request c4:7 dma channel 3 write request active in the system channel 0 descriptor request c5:41 dma channel 0 descriptor request active in the system channel 1 descriptor request c6:44 dma channel 1 descriptor request active in the system channel 2 descriptor request c7:41 dma channel 2 descriptor request active in the system channel 3 descriptor request c8:41 dma channel 3 descriptor request active in the system channel 0 read dw or less c1:4 and c5:53 dma channel 0 read double word valid channel 1 read dw or less c2:7 and c6:58 dma channel 1 read double word valid channel 2 read dw or less c3:6 and c7:54 dma channel 2 read double word valid channel 3 read dw or less c4:8 and c8:52 dma channel 3 read double word valid channel 0 write dw or less c1:5 dma channel 0 write double word valid channel 1 write dw or less c2:8 dma channel 1 write double word valid channel 2 write dw or less c3:7 dma channel 2 write double word valid channel 3 write dw or less c4:9 dma channel 3 write double word valid e500 coherency module (ecm) events ecm request wait core c8:13 asserted for every cycle core request occurs ecm request wait cpm/sap/boot sequencer c7:13 asserted for every cycle cpm request occurs ecm request wait tsec1 c5:16 asserted for every cycle tsec1 request occurs ecm request wait tsec2 c6:16 asserted for every cycle tsec2 request occurs ecm request wait pci/dma c4:20 asserted for every cycle pci request occurs ecm dispatch ref:15 ecm dispatch (includes address only?s) note: all ecm dispatch events are for committed dispatches ecm dispatch from core c1:16 ecm dispat ch from core (includes address only?s) ecm dispatch from cpm c2:20 ? table 19-10. performance monitor events (continued) event counted number descrip tion of event counted 4 datasheet u .com
performance monitor MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 19-18 freescale semiconductor ecm dispatch from tsec1 c3:19 ? ecm dispatch from tsec2 c4:21 ? ecm dispatch from pci c6:17 ? ecm dispatch from dma c7:14 ? ecm dispatch from other c8:14 ? ecm dispatch to ddr c4:22 ? ecm dispatch to l2/sram c5:18 ? ecm dispatch to lbc c6:18 ? ecm dispatch to pci c8:15 ? ecm dispatch snoopable c3:20 ? ecm dispatch write c1:17 ? ecm dispatch write allocate c2:21 ? ecm dispatch write allocate lock c3:21 ? ecm dispatch read c4:23 ? ecm dispatch read unlock c5:19 ? ecm dispatch read clear atomic c6:19 ? ecm dispatch read set atomic c7:16 ? ecm dispatch read decrement atomic c8:16 ? ecm dispatch read increment atomic c7:17 ? ecm data bus grant ddr c1:18 ? ecm data bus grant lbc c2:22 ? ecm data bus grant pic c1:19 ? ecm data bus grant cpm c2:23 ? ecm data bus grant tsec1 c3:23 ? ecm data bus grant tsec2 c4:25 ? ecm data bus wait ddr c5:20 ? ecm data bus wait lbc c6:20 ? ecm data bus wait pic c5:21 ? ecm data bus wait cpm c6:21 ? ecm data bus wait tsec1 c7:19 ? ecm data bus wait tsec2 c8:18 ? ecm global data bus beat ref:16 ? ecm e500 direct read bus beat ref:17 ? table 19-10. performance monitor events (continued) event counted number descrip tion of event counted 4 datasheet u .com
performance monitor MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 19-19 ecm e500 direct read bus beat forwarded c2:24 ecm direct read bus beat forwarded directly to e500 r1 data bus ecm cancel ref:18 ? interrupt controller (pic) events pic total interrupt count ref:26 tot al number of interrupts serviced pic interrupt wait cycl es c8:62 counts cycles when an inte rrupt waits to be acknowledge pic interrupt service cycles c2:19 number of cycles there is an interrupt currently being serviced. pic interrupt select 0 (duration threshold) c1:56 threshold: select 0?3: interrupt count over threshold. (note: only unmasked, nonzero priority requests are acknowledged). the four interrupts are selected through register pairs, pm0mr n ?pm3mr n . see section 10.3.4, ?performance monitor mask registers (pmmrs).? pic interrupt select 1 (duration threshold) c3:59 pic interrupt select 2 (duration threshold) c5:55 pic interrupt select 3 (duration threshold) c6:60 pci common events pci clock cycles ref:28 ? pci inbound memory reads c1:62 includes all read types. pci inbound memory writes c2:37 ? pci inbound config reads c3:63 ? pci inbound config writes c4:37 ? pci outbound memory reads c5:30 includes all read types. pci outbound memory writes c6:32 number of pci outbound memory writes. pci outbound i/o reads c3:37 ? pci outbound i/o writes c4:38 ? pci outbound config reads c7:26 number of pci outbound config reads. pci outbound config writes c8:26 ? pci inbound total read data beats c5:32 in cludes 32- and 64-bit transactions. pci inbound total write data beats c6:34 includes 32- and 64-bit transactions. pci outbound total read data beats c7:28 includes 32- and 64-bit transactions. pci outbound total write data beats c8:28 includes 32- and 64-bit transactions. pci inbound 32-bit read data beats c1:30 ? pci inbound 32-bit write data beats c2:38 ? pci outbound 32-bit read data beats c3:38 ? pci outbound 32-bit write data beats c4:39 ? pci inbound 64-bit read data beats c5:31 ? pci inbound 64-bit write data beats c6:33 ? pci outbound 64-bit read data beats c7:27 ? table 19-10. performance monitor events (continued) event counted number descrip tion of event counted 4 datasheet u .com
performance monitor MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 19-20 freescale semiconductor pci outbound 64-bit write data beats c8:27 ? pci total transactions c7:29 includes 32- and 64-bit transactions. pci 64-bit transactions c8:29 ? pci inbound purgeable reads c2:2 ? pci inbound (speculative reads) purgeable reads discarded c8:63 pci idle cycles c1:31 ? pci dual address cycles c2:40 ? pci internal cycles c3:39 ? pci inbound memory read c1:34 ? pci inbound memory readline c2:44 ? pci inbound memory read multiple c3:42 ? pci outbound memory reads c4:43 number of pci outbound memory reads. pci outbound memory read lines c5:36 number of pci outbound memory read lines. pci wait c1:35 pci n _irdy , pci n _trdy not both asserted pci specific events pci cycles pci n _irdy is asserted c6:36 ? pci cycles pci n _trdy is asserted c7:31 ? pci cycles pci n _frame is asserted c8:31 ? pci snoopable c1:32 ? pci write stash c2:42 ? pci write stash with lock c3:41 ? pci read unlock c4:42 ? pci byte enable transactions c1:33 ? pci non-byte enable transactions c2:43 ? three-speed ethernet controller (tsec) tsec1 address data filtering (adf) events accepted frames ref:36 ? individual hash table accepted frame c7:35 ? group hash table accepted frame c8:35 ? rejected frames ref:39 ? dropped frames ref:38 dropped frames that co uld have been accepted (data overflow, status overflow and lack of bds) table 19-10. performance monitor events (continued) event counted number descrip tion of event counted 4 datasheet u .com
performance monitor MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 19-21 dropped frames due to data overflow c1:41 frames dropped because of overflow in the fifo and 256-byte buffer dropped frames due to status overflow c2:50 frames dropped because of inability to write status for one frame and a new frame starts tsec1 fifo events receive fifo data valid c1:45 ? transmit frames without threshold c7:44 transmit frames that don?t hit tx fifo threshold receive fifo above 1/4 ref:47 ? receive fifo above 1/2 ref:48 ? receive fifo above 3/4 ref:49 ? tsec1 dma events dma reads c1:47 descriptor and data reads bd reads c2:54 txbd and rxbd reads rxbd reads c3:51 rxbd reads (transmit nu mber can be calculated by subtracting this number from total) dma writes c4:52 writes (descriptor and data) bd writes c5:46 txbds and rxbds closed rxbd writes c6:49 rxbds closed (transmit nu mber can be calculated by subtracting this number from total) rxbd read latency (duration threshold) ref:41 times rxbd read latency exceeds threshold (threshold event) start: request asserted stop: data acknowledge received txbd read latency (duration threshold) ref:42 times txbd read latency exceeds threshold (threshold event). start: request asserted stop: data acknowledge received rxbd write latency (duration threshold) ref:43 times rxbd write latency exceeds threshold (threshold event). only for writes that require a response. start: request asserted stop: end of transaction received txbd write latency (duration threshold) ref:44 times txbd write respon se latency exceeds threshold (threshold event). only for writes that require a response. start: request asserted stop: end of transaction received tx data read latency (duration threshold) ref:45 times data read response lat ency exceeds threshold (threshold event). start: request asserted stop: data acknowledge received data beats c7:48 ? read data beats c8:46 ? table 19-10. performance monitor events (continued) event counted number descrip tion of event counted 4 datasheet u .com
performance monitor MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 19-22 freescale semiconductor rx frame interrupts c1:49 times receive frame interrupt is set. event occurs when the bd receive interrupt is set on a last bd. tx frame interrupts c3:53 times a transmit frame interrupt is set. event occurs when the bd transmit interrupt is set on a bd with l = 1. rx frame processing (duration threshold) ref:46 times frame processing exceeds threshold (threshold event). start: open first bd stop: close last bd tsec2 address data filtering (adf) events accepted frames ref:50 ? individual hash table accepted frame c7:36 ? group hash table accepted frame c8:36 ? rejected frames ref:53 ? dropped frames ref:52 dropped frames that co uld have been accepted (data overflow, status overflow and acknowledgement of bds) dropped frames due to data overflow c1:42 frames dropped because of overflow in the fifo and 256-byte buffer dropped frames due to status overflow c2:51 frames dropped because of inability to write status for one frame and a new frame starts tsec2 fifo events receive fifo data valid c1:46 rece ive fifo contains receive data transmit frames without threshold c7:45 transmit frames that don?t hit tx fifo threshold receive fifo above 1/4 ref:61 ? receive fifo above 1/2 ref:62 ? receive fifo above 3/4 ref:63 ? tsec2 dma events dma reads c1:48 descriptor and data reads bd reads c2:55 transmit and rxbd reads rxbd reads c3:52 times that rxbd reads (transmit number can be calculated by subtracting this number from total) dma writes c4:53 descriptor and data writes bd writes c5:47 times that txbds and rxbds closed rxbd writes c6:50 times rxbds closed (transmit number can be calculated by subtracting this number from total) rxbd read latency (duration threshold) ref:55 times rxbd read latency exceeds threshold (threshold event) start: request asserted stop: data acknowledge received table 19-10. performance monitor events (continued) event counted number descrip tion of event counted 4 datasheet u .com
performance monitor MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 19-23 txbd read latency (duration threshold) ref:56 times txbd read latency exceeds threshold (threshold event). start: request asserted stop: data acknowledge received rxbd write latency (duration threshold) ref:57 times rxbd write respons e latency exceeds threshold (threshold event). only for writes that require a response. start: request asserted stop: end of transaction received txbd write latency (duration threshold) ref:58 times that txbd write response latency exceeds threshold (threshold event). only for writes that require a response. start: request asserted stop: end of transaction received tx data read latency (duration threshold) ref:59 data read response latency ex ceeds threshold (threshold event). start: request asserted stop: data acknowledge received data beats c7:49 ? read data beats c8:47 ? rx frame interrupts c1:50 bd receive interrupt is set on a last bd. tx frame interrupts c3:54 bd transmit interrupt is set on a bd with l = 1. rx frame processing ref:60 receive frame proc essing exceeds threshold (threshold event). start: open first bd stop: close last bd local bus events bank 1 hits (chip-select) c1:51 ? bank 2 hits (chip-select) c2:56 ? bank 3 hits (chip-select) c3:55 ? bank 4 hits (chip-select) c4:54 ? bank 5 hits (chip-select) c5:48 ? bank 6 hits (chip-select) c6:53 ? bank 7 hits (chip-select) c7:50 ? bank 8 hits (chip-select) c8:50 ? requests granted to cpm port c1:52 ? requests granted to ecm port c2:57 ? cycles atomic lock for cpm port is enabled c3:56 ? cycles atomic reservation for ecm port is enabled c4:55 atomic reservation time -outs for cpm port c5:49 ? atomic reservation time -outs for ecm port c6:54 ? cycles a read is taking in gpcm c1:53 ? table 19-10. performance monitor events (continued) event counted number descrip tion of event counted 4 datasheet u .com
performance monitor MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 19-24 freescale semiconductor cycles a read is taking in upm c2:58 ? cycles a read is taking in sdram c3:57 ? cycles a write is taking in gpcm c4:56 ? cycles a write is taking in upm c5:50 ? cycles a write is taking in sdram c6:55 ? sdram bank misses c7:51 ? sdram page misses c8:51 ? l2 cache/sram events core instruction accesses to l2 that hit ref:22 ? core instruction accesses to l2 that miss c2:59 ? core data accesses to l2 that hit ref:23 ? core data accesses to l2 that miss c4:57 ? non-core burst write to l2 (cache external write or sram) c5:51 ? non-core non-burst write to l2 c6:56 ? noncore write misses cache external write window and sram memory range c7:52 ? non-core read hit in l2 ref:24 ? non-core read miss in l2 c1:54 ? l2 allocates, from any source ref:25 ? l2 retries due to full write queue c2:60 ? l2 retries due to address collision c3:58 ? l2 failed lock attempts due to full set c4:58 ? l2 victimizations of valid lines c5:52 ? l2 invalidations of lines c6:57 ? l2 clearing of locks c7:53 ? debug events external event c3:61 number of cycles trig_in pin is asserted watchpoint monitor hits c2:61 ? trace buffer hits c1:58 ? duart events uart0 baud rate c1:63 ? uart1 baud rate c5:63 ? table 19-10. performance monitor events (continued) event counted number descrip tion of event counted 4 datasheet u .com
performance monitor MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 19-25 19.4.8 performance monitor examples table 19-12 contains sample register sett ings for the four supported modes. ? simple event performance monitoring example ? triggering event perform ance monitoring example ? threshold event performance monitoring example ? burstiness event perform ance monitoring example the settings in table 19-11 are identical for all four examples. for simple event counting, a non-thres hold event is selected in pmlca n [event] and all other features are disabled by clearing all regi ster fields except for ce. for the triggering example any ev ent can be selected in pmlca n [event]. all other features are disabled by clearing these register fi elds except for ce to allow interrupt signaling. if pmlcb n [trigonsel] is 3 and pmlcb n [trigoffsel] is 5, the counter begins and ends counting based on the conditions in counters three and five. furthermore, if pmlcb n [trigoncntl] is 1, the counter begins counting when pmc3 changes value. according to the setting in pmlcb n [trigoffcntl], the c ounter ends counting when pmc5 overflows. also, al though the register settings fo r pmc5 is not shown, pmlca n [ce] for this chaining events pmc0 carry-out ref:1 pmc0[0 ] 1-to-0 transitions. pmc1 carry-out ref:2 pmc1[0] 1-to-0 transitions. reserved for pmc1. pmc2 carry-out ref:3 pmc2[0] 1-to-0 transitions. reserved for pmc2. pmc3 carry-out ref:4 pmc3[0] 1-to-0 transitions. reserved for pmc3. pmc4 carry-out ref:5 pmc4[0] 1-to-0 transitions. reserved for pmc4. pmc5 carry-out ref:6 pmc5[0] 1-to-0 transitions. reserved for pmc5. pmc6 carry-out ref:7 pmc6[0] 1-to-0 transitions. reserved for pmc6. pmc7 carry-out ref:8 pmc7[0] 1-to-0 transitions. reserved for pmc7. pmc8 carry-out ref:9 pmc8[0] 1-to-0 transitions. reserved for pmc8. table 19-11. pmgc0 and pmlca n settings field setting reason pmgc0[fac] 0 counters must not be frozen. pmgc0[pmie] 1 performance monitor interrupts are enabled pmgc0[fcece] 1 counters should be frozen when an interrupt is signaled. pmlca n [fc] 0 counters cannot be frozen for counting. pmlca n [ce] 1 overflow condition enable is required to allow interrupt signaling. table 19-10. performance monitor events (continued) event counted number descrip tion of event counted 4 datasheet u .com
performance monitor MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 19-26 freescale semiconductor counter must be cleared so that in terrupt signaling is not enabled and the counter does not freeze when it overflows. for threshold counting, a threshold ev ent must be spec ified in pmlca n [event]. for this example, the duration threshold value is scaled by two because pmlcb n [tbmult] is one. all other features are disabled by clearing th e appropriate fields. any non-threshold event can use the burstiness fe ature. for burstiness counting, values for pmlca n [bsize,bgran,bdist] and pmlcb n [tbmult] must be specified. table 19-12. register settings for counting examples register register field simple ev ent triggering threshold burstiness pmgc0fac 0 000 pmie 1 111 fcece 1 111 pmlca n fc 0 000 ce 1 111 event 89 68 39 2 bsize 0 0 0 5 bgran 0 001 bdist 0 008 pmlcb n trigonsel 0 3 0 0 trigoffsel 0 5 0 0 trigoncntl 0 1 0 0 trigoffcntl 0 2 0 0 tbmult 0 000 threshold 0 0 3 0 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 20-1 chapter 20 debug features and watchpoint facility this chapter describes all custom er-visible debug modes of the MPC8555E integrated device. the debug features on the MPC8555E pertain to these three interfaces: the pci in terface (only when in 64-bit pci mode), the local bus controller (lbc), and the dd r sdram interface. in addition to the external interfaces, the MPC8555E provides triggering capabi lities based on user-p rogrammable events. the watchpoint and trace buffer also provi de some visibility to internal buses. this chapter also describes context id registers useful for software debug and desc ribes the jtag access port si gnals that comply with the ieee 1149.1 boundary-scan specification. 20.1 introduction as shown in the block diagram of figure 20-1 , the MPC8555E device provides the following debug features (listed with references to secti ons of this chapter that describe them): ? pci interface debug ( section 20.4.2, ?pci interface debug? ) ? ddr sdram interface debug ( section 20.4.3, ?ddr sdram interface debug? ) ? local bus controller (lbc) debug ( section 20.4.4, ?local bus interface debug? ) ? watchpoint monitor and trace buffer debug ( section 20.4.5, ?watchpoint monitor,? and section 20.4.6, ?trace buffer? ) 20.1.1 overview as shown in figure 20-1 , debug information is provided through th e following interfaces: pci, lbc, and ddr sdram. limited vi sibility, through a 256 64 trace buffer, is also provi ded for the processor core interface. this visibility into internal device ope ration is useful for debugging application software through inverse assembly and reconstr uction of the fetch stream. the combination of a source id (msrcid[0:4]) and a data-valid signal (mdval) indicates that meaningful debug information is visible on either the local bus or ddr sdram interfaces. a logic analyzer can be programmed to capture data based on the values of msrcid[0:4] and mdval. 4 datasheet u .com
debug features and watchpoint facility MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 20-2 freescale semiconductor figure 20-1. debug and watchpoint monitor block diagram other system debugging is supported by the programmable triggering of the watchpoint monitor and trace buffer. both can be triggered from one of the follo wing three sources: ? each other ? a performance monitor event ? an external source (through trig_in) the watchpoint monitor can be configured to asse rt trig_out when a programmed event occurs. the two context id registers, described in section 20.3.3, ?context id registers,? are useful for software debug. 20.1.2 features the principal features of the debug modes and the watchpoint monitor are as follows: ? pci1 interface: transaction source id driven onto pci1_ad[62:58] (only when in 64-bit pci mode) e500 coherency pci controller ddr controller lbc mecc[0:5] msrcid[0:4], mdval trig_in trig_out pci1_ad[62:58] trace buffer (256 64) watchpoint and trace buffer control module sdram performance monitor signal name lbc protocol signals all other ddr signals 6 6 6 5 6 all other pci signals pordbgmsr[mem_sel] = por value of msrcid0 srcid[0:4] srcid[0:4] dval srcid[0:4] dval (local bus) core e500 processor 4 datasheet u .com
debug features and watchpoint facility MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 20-3 ? lbc and ddr interface source id and data-valid indicators ? lbc or ddr sdram source id can be se lected to be driven onto msrcid[0:4] ? source id and data-valid indicator s can be selected to be driven onto the error correcting code (ecc) pins of the ddr interface ? watchpoint monitor that supports: ? two-level triggering ? programmable external trigger (trig_out) ? interlocked with performance monito r to use its large number of counters ? trace buffer features that supports: ? two-level triggering ? programmable external trigger (trig_out) ? interlocked with performance monito r to use its large number of counters ? 256-entry trace buffer, 64 bits each ? programmable trace start and stop ? can function as a second watchpoint monitor ? context id registers that can be programmed to trigger events 20.1.3 modes of operation the pci, lbc, and ddr sdram interfaces all have debug modes, which are controlled by values on configuration inputs during the power- on reset (por) sequence, as shown in table 20-1 .the ddr controller can also drive debug information on either msrcid[0:4] or mecc[0:5]. see section 20.4.1, ?source and target id,? for additional information about the s ource id information driven on the debug signals in these modes. note that both the watchpoint monitor and trac e buffer also operate in a variety of modes. table 20-1. por configuration settings and debug modes configuration signal por value effect reference msrcid0 0 local bus sdram information appears on msrcid[0:4] and mdval. 20.1.3.1/20-4 1 default value (internal pull-up resistor). ddr sdram information appears on msrcid[0:4] and mdval. msrcid1 0 mecc[0:4] operate in debug mode and provide memory debug source id and mecc5 provides data-valid information. 20.1.3.2/20-4 1 default value (internal pull-up resistor). mecc[0:4] operate in normal mode and provide ddr sdram error correcting code information. pci1_gnt3 0 the pci interface operates in debug mode. the source id information appears on the high-order address bits (pci1_ad[62:58]) during the bus command phase. 20.1.3.3/20-4 1 default value (internal pull-up resistor). the pci interface operates in normal mode. 4 datasheet u .com
debug features and watchpoint facility MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 20-4 freescale semiconductor 20.1.3.1 local bus (lbc) debug mode the lbc and the ddr sdram controller can driv e debug information (source id and data-valid indicator) onto msrcid[0:4] and mdval as shown in table 20-1 , the msrcid0 value during por controls multiplexing. if msrcid 0 is low when sampled during por, the local bus sdram information appears on msrcid[0:4] and mdva l; otherwise, the ddr sdram debug information is presented. 20.1.3.2 ddr sdram interface debug modes msrcid1 is sampled during por to multiplex either ecc or debug info rmation on the ecc pins of the ddr sdram interface. as shown in table 20-1 , if msrcid1 is low during por, the ecc pins operate in debug mode and provide memory debug source id and data-valid informa tion. msrcid1 must be pulled low during por to use the ecc pins in de bug mode. if msrcid1 is unconnected, an internal pull-up resistor ensures the ecc pi ns always source ddr sdram erro r correcting code information as their default power-on reset configuration. note if the ddr ecc pins are in debug mode (configured for debug during por), ecc checking is disabled in the memory controller. in this case, mecc[0:4] do not provide ecc informat ion and must not be connected to sdram devices. 20.1.3.3 pci interf ace debug modes if pci1_gnt3 is low when sampled during por, the pci interface operates in debug mode. pci debug mode is only possible when the pci1 is configured for a 64-bit interface. in th is mode, the source id information appears on the high-or der address bits (pci 1_ad[62:58]) during the bus command phase. see section 20.4.2, ?pci interface debug,? for more information. 20.1.3.4 watchpoint monitor modes the watchpoint monitor supports the following operating modes: ? immediate trigger arming (one-level triggering)?the watchpoint monitor triggers as soon as the first trigger event occurs. ? wait for trigger arming (two-level triggering)?the watc hpoint monitor waits fo r a specific event before enabling (arming) the trigger logic. the monitor does not respond to trigger events until after the arming event occurs. this function is si milar to two-level trigge ring on a logic analyzer. ? assert trig_out on hit?the debug block can be programmed to assert the trig_out signal when a programmed watchpoint monitor event occurs . this signal can be used to trigger a logic analyzer. 20.1.3.5 trace buffer modes the trace buffer supports the following operating modes: ? immediate trigger arming (one-lev el triggering)?the trace buffer triggers as soon as the first trigger event occurs. 4 datasheet u .com
debug features and watchpoint facility MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 20-5 ? wait for trigger arming (two-level triggering)?the trace buffer wa its for a specific event before enabling (arming) the trigger logic. the trace buf fer does not respond to trigger events until after the arming event occurs. this function is simila r to two-level triggering on a logic analyzer. ? specific interface selection?the trace buffer can be programmed to trace on e of several internal interfaces. ? specific event selection?the trace buffer can be programmed to tr ace on the occurrence of one or several concurrent events. ? specific trace selection?to facilit ate trace data filtering, the trace buffer can be configured to capture data under the following conditions: ? on every cycle in which a valid transac tion is present on the selected interface ? only when a watchpoint monitor event occurs ? only when the programmed trace event is detected ? programmable trace stop?the trace buffer ma y be programmed to stop tracing when a programmed stop-tracing event occurs or when the 256-entry buffer is full. 20.2 external signal description this section provides information about all the exte rnal signals associated with the various MPC8555E debug functions. as shown in table 20-1 , the MPC8555E has several signals that are sampled during por to determine the configuration of the phase-locked loop clock m ode and the rom, flash, and dynamic memory. see chapter 4, ?reset, clocking, and initialization.? to facilitate system testing, th e MPC8555E provides a jtag test access port (tap) th at complies with the ieee 1149.1 boundary-scan specification. this section also describes jtag tap signals. 20.2.1 overview all the signals associated with devi ce debug features are summarized in table 20-2 , listed with a reference to the page number of the section with more info rmation. the detailed descri ptions are contained in table 20-2 . some signals (the mecc bus, for example) are additionally described in other chapters, but are described here also for completeness, with emphasis on their debugging utility. table 20-2. debug, watchpoint, and test signal summary name description functional block function reset value i/o page # mdval memory data-valid debug selectable data-valid signal from either ddr sdram controller or lbc. 1o 20-7 mecc[0:7] ddr error correcting code ddr sdram in debug mode, the high-order 6 bits carry debug information (transaction source id and data-valid indication). 0x08 o 1 20-7 msrcid[0:1] memory source id debug selectable transaction source id from either ddr sdram controller or local bus controller. reset_cfg o 20-7 msrcid[2:4] 111 o 20-7 4 datasheet u .com
debug features and watchpoint facility MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 20-6 freescale semiconductor trig_in trigger in debug trigger for various function in the watchpoint monitor and trace buffer. 1i 20-8 trig_out trigger out debug can be used externally for triggering a logic analyzer. additionally, it can be used for observing system ready indication. functions are multiplexed onto this signal depending on tosr[sel] (see ta b l e 2 0 - 2 5 ). 1o 20-8 pci1_ad [62:58] pci address debug in debug mode these pins carry the source id of the transaction. 0000_0 o 20-7 tck test clock debug clock for jtag testing. internal ly pulled up. 1 i 20-8 tdi test data input debug serial input for instructions and data to the jtag test subsystem. internally pulled up. 1i 20-8 tdo test data output debug serial data output for the jtag test subsystem. high impedance except when scanning out data. hi z o 20-8 tms test mode select debug carries commands to the tap controller for boundary scan operations. internally pulled up. 1i 20-8 trst test reset debug resets the tap controller asynchronously. ? i 20-8 therm[0:1] thermal resistor access test these pins tie directly to an internal resistor whose value varies linearly with temperature. ?i 20-8 test_s el0 (MPC8555E) test_sel0 (mpc8541e) test select 0 test factory test. must be negated (pulled high on an MPC8555E; pulled low on an mpc8541e) for normal operation. ?i 20-8 test_sel1 test select 1 test factory test. must be negated for normal operation. ? i 20-8 lssd_ mode test test factory test. refer to the MPC8555E powerquicc? iii integrated processor hardware specifications for proper treatment. i 20-8 l1_tstclk test test factory test. refer to the MPC8555E powerquicc? iii integrated processor hardware specifications for proper treatment. i 20-8 l2_tstclk test test factory test. refer to the MPC8555E powerquicc? iii integrated processor hardware specifications for proper treatment. i 20-8 1 while these signals are normally bidirectional, when sourcing debug information they are output only. table 20-2. debug, watchpoint, and test signal summary (continued) name description functional block function reset value i/o page # 4 datasheet u .com
debug features and watchpoint facility MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 20-7 20.2.2 detailed signal descriptions this section describes the details of the de bug, watchpoint monitor, and jtag test signals. 20.2.2.1 debug signals?details table 20-3 describes all signals associ ated with device debug modes. table 20-3. debug signals?detailed signal descriptions signal i/o description mdval o memory data-valid. indicates when valid data is available. may be used by a logic analyzer to capture the data on the data bus. state meaning asserted?indicates that data is valid on the da ta bus during the current clock cycle. when the ddr sdram interface is selected to sour ce information on mdval, this signal is valid for every cycle that data is driven or received on the ddr sdram interface. when the lbc is sele cted, this signal is valid for ev ery cycle that data is driven or received on the local bus interface. the assertion of this signal may be used by a logic analyzer to capture data. timing asserted/negated?referenced to the selected interface, (ddr or local bus). asserts when data is valid. assertions are held fo r the duration of the transfer. read data timing is similar to ma. write data timing is similar to the output mdq. mecc[0:7] o memory ecc. ddr error checking and correcting. the normally bidirectional operation of the memory ecc (mecc) bus is described in section 9.5.12, ?error checking and correcting (ecc).? this bus is used for debug functions when msrcid1 is sampled low during por. in debug mode, the high-order 5 bits (mecc[0:4]) ma y be used to provide the transaction source id and mecc5 can be used as the data-valid indicator. in debug mode, mecc[0:5] is constantly driven with debug information and must be disconnected from the ddr memory?s ecc pins. state meaning asserted/negated?in debug mode, mecc[0:5] is always driven. the source id values appear during ras and cas cycles. a value of 0x1f (all ones) is driven during cycles other than ras and cas . the data-valid indicator appears when data is being received or driven on the pins. timing driven every cycle in debug mode. msrcid[0:4] o memory source id. attribute signals associated with the memory interface that indicate the source id for a transaction on an sdram interface. the sdram interface, ddr or local bus, to which the debug information applies is specified during por with msrcid0 as shown in ta bl e 2 0 - 1 . two of these signals serve as reset configuration input signals. state meaning asserted/negated?in debug mode, always dr iven with the value of the source id. the source id has a value of 0x 1f for cycles other than ras and cas . the encodings shown in table 20-26 provide detailed information about a memory transaction. timing driven every cycle in debug mode. similar timing to ma. pci1_ad[62:58] o pci address. provides transacti on source id for the current pci bus transaction. state meaning asserted/negation?in debug mode, always driven with the value of the transaction source id. timing driven every cycle in debug mode. 4 datasheet u .com
debug features and watchpoint facility MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 20-8 freescale semiconductor 20.2.2.2 watchpoint monitor trigger signals?details table 20-4 shows detailed descriptions of the wa tchpoint monitor and trace buffer signals. 20.2.2.3 test signals?details table 20-5 shows detailed descriptions of the jtag test signals. table 20-4. watchpoint and trigger signals?detailed signal descriptions signal i/o description trig_in i trigger in. can be used to trigger the watchpoint and trace buffers. note this is an active-high (rising-edge triggered) signal. state meaning asserted?indicates that a prog rammed/armed external event has been detected. assertion may be used internally to trigger trace buffers and watchpoint mechanisms. timing assertion/negation?the MPC8555E interprets trig_in as asserted on detection of the rising edge. it may occur at any time. must re main asserted for at least 3 system clocks to be recognized internally. trig_out o trigger out. function determined by tosr[sel]. when tosr[sel] is non-zero, it can be used for triggering external devices, like a logic analyzer, with either the watchpoint monitor, the trace buffer, or the performance monitor as trigger sources. when tosr[sel] is cleared, trig_out is multiplexed with ready, which indicates the operational readiness of the device (running or in low-power or debug modes). see chapter 4, ?reset, clocking, and initialization,? and chapter 18, ?global utilities,? for more details about reset, low-power, and debug states. state meaning asserted?when tosr[sel] is all zeros, serves as the ready signal, indicating that the device is not in a low-power or debug mode and that it has emerged from reset. sel 0 indicates that a programmed trigger event has occurred. negation?no final watchpoint match condition timing assertion may occur at any time. remain s asserted for at least 3 system clocks table 20-5. jtag test and other signals?detailed signal descriptions signal i/o description tck i jtag test clock. state meaning asserted/negated?should be driven by a fr ee-running clock signal with a 30?70% duty cycle. input signals to the tap are clocked in on the rising edge. changes to the tap output signals occur on the falling edge. the test logic allows tck to be stopped. an unterminated input appears as a high signal level to the test logic due to an internal pull-up resistor. timing see ieee 1149.1 standard for more details. tdi i jtag test data input. state meaning asserted/negated?the value present on the rising edge of tck is clocked into the selected jtag test instruction or data register. an unterminated input appears as a high signal level to the test logic due to an internal pull-up resistor. timing see ieee 1149.1 standard for more details. 4 datasheet u .com
debug features and watchpoint facility MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 20-9 tdo o jtag test data output. state meaning asserted/negated?the cont ents of the selected internal in struction or data register are shifted out on this signal on the falling edge of tck. remains in a high-impedance state except when scanning data. timing see ieee 1149.1 standard for more details. tms i jtag test mode select. state meaning asserted/negated?decoded by the internal jtag tap controller to distinguish the primary operation of the test support circuitry. an unterminated input appears as a high signal level to the test logic due to an internal pull-up resistor. timing see ieee 1149.1 standard for more details. trst i jtag test reset. state meaning asserted?causes asynchronous initialization of the internal jtag tap controller. must be asserted during power-on reset in order to properly initialize the jtag tap and for normal operation of the MPC8555E. an unterminated input appears as a high signal level to the test logic due to an internal pull-up resistor. negated? normal operation. timing see ieee 1149.1 standard for more details. lssd_mode i used for factory test. refer to the MPC8555E powerquicc? iii inte grated processor hardware specifications for proper treatment. l1_tstclk i used for factory test. refer to the MPC8555E powerquicc? iii inte grated processor hardware specifications for proper treatment. l2_tstclk i used for factory test. refer to the MPC8555E powerquicc? iii inte grated processor hardware specifications for proper treatment. therm[0:1] i these signals provide access to an internal resist or that has a value that vari es linearly with temperature. the actual value for the resistor varies from device to device, but the linear relationship between temperature and resistance is consistent. see the MPC8555E powerquicc? iii integrated processor hardware specifications for more information on how to accura tely measure the junction temperature of a device. note that this thermal resistor is intended for engineering development only. test_s el0 (MPC8555E) test_sel0 (mpc8541e) i used for factory test. this test signal is active-l ow on the MPC8555E device but active-high on the mpc8541e device. for normal operation, it should be negated (pulled high on an MPC8555E; pulled low on an mpc8541e). test_sel1 i used for factory test. should be negated for normal operation table 20-5. jtag test and other signals?detailed signal descriptions signal i/o description 4 datasheet u .com
debug features and watchpoint facility MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 20-10 freescale semiconductor 20.3 memory map/register definition table 20-6 shows the memory-mapped debug and watchpoi nt registers of the MPC8555E. undefined 4-byte address spaces within offset 0x000?0xfff are reserved. 20.3.1 watchpoint monitor register descriptions the following sections describe the control re gisters for the watchpoi nt monitor facility. 20.3.1.1 watchpoint monitor control registers 0?1 (wmcr0, wmcr1) the watchpoint monitor control regi sters (wmcr0, wm cr1), shown in figure 20-2 and figure 20-3 , control the specification of watchpoint monitor events. table 20-6. debug and watchpoint monitor memory map local memory offset register access reset section/page watchpoint monitor registers 0xe_2000 wmcr0?watchpoint monitor control register 0 r/w 0x0000_0000 20.3.1.1/20-10 0xe_2004 wmcr1?watchpoint monitor control register 1 r/w 0x0000_0000 20.3.1.1/20-10 0xe_200c wmar?watchpoint monitor address register r/w 0x0000_0000 20.3.1.2/20-12 0xe_2014 wmamr?watchpoint monitor address mask register r/w 0x0000_0000 20.3.1.3/20-13 0xe_2018 wmtmr?watchpoint monitor transaction mask register r/w 0x0000_0000 20.3.1.4/20-13 0xe_201c wmsr?watchpoint monitor status register r/w 0x0000_0000 20.3.1.5/20-15 trace buffer registers 0xe_2040 tbcr0?trace buffer control register 0 r/w 0x0000_0000 20.3.2.1/20-15 0xe_2044 tbcr1?trace buffer control register 1 r/w 0x0000_0000 20.3.2.1/20-15 0xe_204c tbar?trace buffer address register r/w 0x0000_0000 20.3.2.2/20-18 0xe_2054 tbamr?trace buffer address mask register r/w 0x0000_0000 20.3.2.3/20-18 0xe_2058 tbtmr?trace buffer transaction mask register r/w 0x0000_0000 20.3.2.4/20-18 0xe_205c tbsr?trace buffer status register r/w 0x0000_0000 20.3.2.5/20-19 0xe_2060 tbacr?trace buffer access control register r/w 0x0000_0000 20.3.2.6/20-20 0xe_2064 tbadhr?trace buffer access data high register r/w 0x0000_0000 20.3.2.7/20-21 0xe_2068 tbadr?trace buffer access data register r/w 0x0000_0000 20.3.2.8/20-21 context id registers 0xe_20a0 pcidr?programmed context id register r/w 0x0000_0000 20.3.3.1/20-22 0xe_20a4 ccidr?current context id register r/w 0x0000_0000 20.3.3.2/20-22 other registers 0xe_20b0 tosr?trigger output source register r/w 0x0000_0000 20.3.4.1/20-23 4 datasheet u .com
debug features and watchpoint facility MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 20-11 table 20-7 describes wmcr0 fields. 0 1 2 3 4 5 6 7 20 21 23 24 31 r en amd tmd ecen necen siden tiden 0 0 0 0 0 0 0 0 0 0 0 0 0 0 strt 0 0 0 0 0 0 0 0 w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x000 figure 20-2. watchpoint monitor control register 0 (wmcr0) table 20-7. wmcr0 field descriptions bits name description 0 en enable 0 watchpoint monitor events are not flagged. 1 a watchpoint monitor event is flagged. 1 amd address match disable. qualifies address match as a watchpoint event criterion. 0 address matching is used to recognize a watchpoint event. 1 address matching does not affect watchpoint event detection. 2 tmd transaction match disable. qual ifies transaction type match (as defined in wmcr1[ifsel] and wmtmr) as a watchpoint event criterion. 0 a transaction type match is used to recognize watchpoint events. 1 a transaction type match does not affect watchpoint event detection. 3 ecen equal context enable. qualifies the matching of cu rrent context with programmed context as a watchpoint event criterion, as written in the context registers described in section 20.3.3, ?context id registers.? 0 current context match does not affect watchpoint event detection. 1 watchpoint events are qualified by comparing current context with the programmed context event value. note: ecen and necen must not be enabled in the same run. if both are set, watchpoint events are inhibited (never occur). 4 necen not equal context enable. qualifies the matching of current context with programmed context as a watchpoint event criterion, as written in the context registers described in section 20.3.3, ?context id registers.? 0 the failure of a current context match doe s not affect watchpoint event detection 1 watchpoint events are qualified with not getting a current context compare wit h the programmed context event value. note: ecen and necen must not be enabled in the same run. if both are set, watchpoint events are inhibited (never occur). 5 siden source id enable 0 source id does not affect watchpoint event detection. 1 watchpoint events are qualified by compar ison with the programmed wmcr1(sid) value. 6 tiden target id enable 0 target id does not affect watchpoint event detection. 1 watchpoint events are qualified by compar ison with the programmed wmcr1(tid) value. 7?20 ? reserved 4 datasheet u .com
debug features and watchpoint facility MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 20-12 freescale semiconductor figure 20-3 shows the wmcr1. table 20-8 describes the wmcr1 fields. 20.3.1.2 watchpoint monitor address register (wmar) the watchpoint monitor address register (wmar), shown in figure 20-4 , contains the address to match against if wmcr[amd] is clear. note that the transact ion address is qualified with the bits described in 21?23 strt start condition. specifies the event that arms th e watchpoint monitor to start looking for the programmed event. 000 no event. armed immediately 001 trace buffer event is detected 010 performance monitor signals overflow 011 trig_in transitions from 0 to 1 100 trig_in transitions from 1 to 0 101 current context id equals programmed context id 110 current context id is not equal to programmed context id 111 reserved 24?31 ? reserved 0 1 2 3 4 5 7 8 9 10 11 15 16 26 27 31 r 0 0 0 0 0 ifsel 0 0 0 sid 0 0 0 0 0 0 0 0 0 0 0 tid w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x004 figure 20-3. watchpoint monitor control register 1 (wmcr1) table 20-8. wmcr1 field descriptions bits name description 0?4 ? reserved 5?7 ifsel interface selection. selects the address, transacti on type (as defined in wmtmr), and other attributes to be used for comparison 000 select e500 coherency module (ecm) dispatch interface 001 select internal ddr sdram interface 010 select internal pci outbound interface 011?111 reserved 8?10 ? reserved 11?15 sid source id. specifies the source id associated wit h wmcr0[siden]. for a definit ion of the source id, see table 20-26 . 16?26 ? reserved 27?31 tid target id. specifies the target id associated wi th wmcr0[tiden]. for a definition of the target id see table 20-26 . table 20-7. wmcr0 field descriptions (continued) bits name description 4 datasheet u .com
debug features and watchpoint facility MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 20-13 section 20.3.1.3, ?watchpoint monitor a ddress mask register (wmamr),? before being compared with wmar. note also that the contents of wmar are not qualified with wmamr. table 20-9 describes the wmar fields. 20.3.1.3 watchpoint monitor address mask register (wmamr) the watchpoint monitor address ma sk register (wmamr) shown in figure 20-5 contains the mask that is applied to a transaction a ddress before the address is compared with wmar. table 20-10 describes the wmamr fields. 20.3.1.4 watchpoint monitor transaction mask register (wmtmr) the watchpoint monitor transaction ma sk register (wmtmr), shown in figure 20-6 , specifies which transaction types to monitor. wmtmr allows users to qualify watchpoint even ts specifically with any combination of transacti on types. as shown in table 20-12 , each bit represents as many as four separate transaction types; one for each in terface. setting a bit enables watchpoi nt monitoring for the corresponding transaction types. 0 31 r wma w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x00c figure 20-4. watchpoint monitor address register (wmar) table 20-9. wmar field descriptions bits name description 0?31 wma watchpoint monitor address. 0 31 r wmam w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x014 figure 20-5. watchpoint monitor address mask register (wmamr) table 20-10. wmamr field descriptions bits name description 0?31 wmam watchpoint monitor address mask. a value of zero masks the address comparison for the corresponding address bit. 4 datasheet u .com
debug features and watchpoint facility MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 20-14 freescale semiconductor because the supported transaction types vary by inte rface, the type designated by a wmtmr field also depends on the interface specified by wmcr1[ifsel]. table 20-12 lists transaction types associated with each wmtmr bit by interface. table 20-11 describes the wmtmr fields. the following table, table 20-12 , defines the transactions associated w ith each transaction mask bit for the different interfaces supporte d by the watchpoint monitor. 0 31 r wmtm w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x018 figure 20-6. watchpoint monitor tran saction mask register (wmtmr) table 20-11. wmtmr field descriptions bits name description 0?31 wmtm watchpoint monitor transaction mask. each bi t corresponds to a transaction type as defined in ta b l e 2 0 - 1 2 . the transaction associated with any particular bit may be different depending on the interface being monitored. a value of 1 for a given mask bit enables the matching of the transaction associated with that bit. these bits are meaningful on ly when wmcr0[tmd] = 0. table 20-12. transaction types by interface bits e500 coherency module dispatch ddr controller pci outbound request 0 write with local processor snoop write memory write 1 write with no local processor snoop ? i/o write 2 write with allocate(l2 stashing) write with allocate ? 3 write with allocate and lock (l2 stashing with locking) write with allocate and lock ? 4?7 reserved 8 read with local processor snoop read memory read 9 read with no local processor snoop ? i/o read 10 read with unlock read with unlock ? 11?15 reserved 16 atomic clear atomic clear ? 17 atomic set atomic set ? 18 atomic decrement atomic decrement ? 19 atomic increment atomic increment ? 20?31 reserved 4 datasheet u .com
debug features and watchpoint facility MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 20-15 20.3.1.5 watchpoint monitor status register (wmsr) the watchpoint monitor status register (wmsr), shown in figure 20-7 , indicates the state of the watchpoint monitor. table 20-13 describes the wmsr fields. 20.3.2 trace buffer re gister descriptions the following sections descri bes the trace buffer registers. 20.3.2.1 trace buffer control registers (tbcr0, tbcr1) the trace buffer control regist ers (tbcr0, tbcr1), shown in figure 20-8 and figure 20-9 , specify trace buffer events. 012 31 r act trig 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x01c figure 20-7. watchpoint monitor status register (wmsr) table 20-13. wmsr field descriptions bits name description 0actactive 0 the start triggering event has not occu rred; watchpoint moni tor is not armed. 1 the start triggering event has occurred; watchpoint monitor is armed. 1 trig triggered 0 the programmed event in wmcr0 has not yet been triggered. 1 the programmed event in wmcr0 has been triggered at least once. 2?31 ? reserved 0 1 2 3 4 5 6 7 8 1314 1516 2021 2324 2829 31 r en amd tmd ecen necen siden tiden halt 0 0 0 0 0 0 mode 0 0 0 0 0 strt 0 0 0 0 0 stop w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x040 figure 20-8. trace buffer control register 0 (tbcr0) 4 datasheet u .com
debug features and watchpoint facility MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 20-16 freescale semiconductor table 20-14 describes the tbcr0 fields. table 20-14. tbcr0 field descriptions bits name description 0enenable 0 the trace buffer facility is disabled. 1 the trace buffer facility is enabled. 1 amd address match disable 0 the address match is used to qualify a trace buffer event. 1 the address match is ignored when detecting a trace buffer event. 2 tmd transaction match disable 0 the transaction type match is used to qualify a trace buffer event. 1 the transaction type match is ignored when detecting a trace buffer event. 3 ecen equal context enable. qualifies the matching of curr ent context with programmed context as a trace buffer event criterion, as written in the context registers described in section 20.3.3, ?context id registers.? 0 current context match does not af fect trace buffer event detection 1 trace buffer events are qualified by comparing curr ent context with t he programmed context event value. note: ecen and necen must not be enabled in the same run. if both are set, watchpoint events are inhibited (never occur). 4 necen not equal context enable. qualifies the matching of current context with programmed context as a trace buffer event criterion, as written in the context registers described in section 20.3.3, ?context id registers.? 0 the failure of a current context match does not affect trace buffer event detection 1 trace buffer events are qualified with not getting a cu rrent context compare with the programmed context event value. note: ecen and necen must not be enabled in the same run. if both are set, watchpoint events are inhibited (never occur). 5 siden source id enable 0 trace buffer events ignore the programmed source id value. 1 trace buffer events are qualified by comparison with the programmed sid event value. 6 tiden target id enable 0 trace buffer events ignore the programmed tid event value. 1 trace buffer events are qualified by comparison wit h the programmed tid event value. this comparison only applies when the ecm is selected for tracing (tbcr1[ifsel] is all zeros). 7 halt halt causes the trace buffer to stop tracing immediately. 8?13 ? reserved 14?15 mode trace mode. specifies one of two trace modes. 00 trace every valid transaction 01 reserved 10 trace only cycles in which a trace event is detect ed. note that if en and other tbcr0 fields are not properly programmed to specify a traceable event, tracing occurs for every valid address. 11 reserved 16?20 ? reserved 4 datasheet u .com
debug features and watchpoint facility MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 20-17 table 20-15 describes the tbcr1 fields. 21?23 strt start condition. specifies the event that arms th e trace buffer to start looking for the programmed event 000 no event. armed immediately 001 watchpoint monitor event is detected 010 trace buffer event is detected 011 performance monitor signals overflow 100 trig_in transitions from 0 to 1 101 trig_in transitions from 1 to 0 110 current context id equals programmed context id 111 current context id does not equal programed context id 24?28 ? reserved 29?31 stop trace stop mode. specifies the ev ent that stops the updati ng of the trace buffer after it has been started. trace buffer only stops after it has been triggered at least once. 000 buffer is full 001 watchpoint monitor event is detected 010 trace buffer event is detected 011 performance monitor signals overflow 100 trig_in transitions from 0 to 1 101 trig_in transitions from 1 to 0 110 current context id equals programmed context id 111 current context id does not equal programed context id 0 4 5 7 8 9 10 11 15 16 26 27 31 r 0 0 0 0 0 ifsel 0 0 0 sid 0 0 0 0 0 0 0 0 0 0 0 tid w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x044 figure 20-9. trace buffer control register 1 (tbcr1) table 20-15. tbcr1 field descriptions bits name description 0?4 ? reserved 5?7 ifsel interface selection. specifies the interface that sources information for both comparison/buffer control and buffer data capture. 000 selects e500 coherency module (ecm) dispatch interface 001 selects internal ddr sdram interface 010 selects internal pci outbound interface 011?111 reserved 8?10 ? reserved 11?15 sid source id. specifies the source id associat ed with tbcr0[siden]. the source id is defined in ta b l e 2 0 - 2 6 . 16?26 ? reserved 27?31 tid target id. specifies the target id associated with tbcr0[tiden]. the target id is defined in table 20-26 . table 20-14. tbcr0 field descriptions (continued) bits name description 4 datasheet u .com
debug features and watchpoint facility MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 20-18 freescale semiconductor 20.3.2.2 trace buffer address register (tbar) the trace buffer address re gister (tbar), shown in figure 20-10 , contains the address to match against (if tbcr0[amd] is zero). the tr ansaction address is qualified with the bits described in section 20.3.2.3, ?trace buffer address ma sk register (tbamr),? before being compared with tbar. note that the contents of tbar are not qualified with tbamr. table 20-16 describes the tbar field. 20.3.2.3 trace buffer address mask register (tbamr) the trace buffer address mask register (tbamr), shown in figure 20-11 , contains the mask that is applied to a transaction address before th e address is compared with tbar. table 20-17 describes the tbamr field. 20.3.2.4 trace buffer transaction mask register (tbtmr) the trace buffer transaction mask register (tbtmr), shown in figure 20-12 , specifies which transaction types to monitor. each bit in the tbtmr represents a transaction type on the selected interface. the transaction associated with any pa rticular bit depends on the interf ace being monitored as specified by tbcr1[ifsel]. note that the transactions used fo r defining trace buffer events are the same as those 0 31 r tba w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x04c figure 20-10. trace buffer address register (tbar) table 20-16. tbar field descriptions bits name description 0?31 tba trace buffer address. 0 31 r tbam w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x054 figure 20-11. trace buffer address mask register (tbamr) table 20-17. tbamr field descriptions bits name description 0?31 tbam trace buffer address mask.a value of zero masks the address comparison for the corresponding address bit. 4 datasheet u .com
debug features and watchpoint facility MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 20-19 defined for watchpoint monitor events. thus, table 20-12 defines the transaction types associated with each interface. setting a bit enables a hit when this tr ansaction is matched (provide d all other match criteria are met and tbcr0[tmd] is clear). different interfaces support different transaction types, and the same bit may represent different transaction types depe nding on the interface. table 20-18 describes the tbtmr field. 20.3.2.5 trace buffer status register (tbsr) the trace buffer status re gister (tbsr), shown in figure 20-13 , indicates the operational state of the trace buffer. table 20-19 describes the tbsr fields. 0 31 r tbtm w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x058 figure 20-12. trace buffer transaction mask register (tbtmr) table 20-18. tbtmr field descriptions bits name description 0?31 tbtm trace buffer transaction mask. each bit corresponds to a transaction type as defined in table 20-12 . the transaction associated with a bit depends on the interface being monitored. a value of 1 for a given mask bit enables the matching of the transaction associated with that bit. these bits are meaningful only when tbcr0[tmd] = 0. 0 1 2 3 4 15 16 23 24 31 r act trig stp wrap 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c_indx w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x05c figure 20-13. trace buffer status register (tbsr) table 20-19. tbsr field descriptions bits name description 0 act active. indicates trace buffer activity 0 the start triggering event has not yet occurred. trace buffer is not armed 1 the start triggering event has occurred. trace buffer is armed 1 trig triggered. indicates whether or not a programmed event has been triggered 0 the programmed event in tbcr0 has not yet been triggered. 1 the programmed event in tbcr0 has been triggered at least once. 4 datasheet u .com
debug features and watchpoint facility MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 20-20 freescale semiconductor 20.3.2.6 trace buffer access control register (tbacr) the trace buffer access control register (tbacr) enables software to read or write the trace buffer. each entry is 64 bits; therefore, it take s one write of tbacr a nd two reads of the access data register (tbadr and tbadhr) to read one 256-entry array entry. simil arly, it takes one write of tbacr and two writes of tbadr and tbadhr to write one array entry. software can access any entry by writing the appropriate index into tbacr[indx]. to read or write the buffer seque ntially, starting with entry 0, the index must start with a value of 0 and in crement every time a new entry is accessed. tbacr is shown in figure 20-14 . table 20-20 describes the tbacr fields. 2 stp stopped. indicates whether or not a tr ace buffer stop condition has been detected 0 no stop condition yet detected 1 the trace buffer has detected a stop condition and is no longer capturing events. 3 wrap wrapped. indicates that the trace buffer write point er has wrapped to the beginning of the buffer at least once. set when the last entry of the trace buffer is written 0 pointer has not yet wrapped 1 pointer has wrapped to the beginning at least once 4?23 ? reserved 24?31 c_indx current index. represents the current value of t he write pointer at the time tbsr was read. this value may be written by software to initialize the write pointer; however, software is not allowed to write the write pointer while the trace buffer is active. writes are ignored while the trace buffer is active. it is recommended to write the status register before enabling t he trace buffer in order to zero out any bits that might have been set during a prior run and to initialize the write pointer to zero. 012 23 24 31 r r d w r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 indx w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x060 figure 20-14. trace buffer access control register (tbacr) table 20-20. tbacr field descriptions bits name description 0 rd read command. when set, a trace buffer read is pe rformed using the value of tbacr[indx]. this bit is automatically cleared when the read is performed. 1 wr write command. when set, a trace buffer write is performed using the value of tbacr[indx]. this bit is automatically cleared when the write is performed. a writ e occurs only if the trace buffer is not active: write requests are ignored while the buffer is active. 2?23 ? reserved 24?31 indx buffer index to read from or write into (0?255). used in conjunction with tbacr[rd] and tbacr[wr]. table 20-19. tbsr field descriptions (continued) bits name description 4 datasheet u .com
debug features and watchpoint facility MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 20-21 20.3.2.7 trace buffer access data high register (tbadhr) the trace buffer access data high register (tbadhr), shown in figure 20-15 , contains the high-order 32 bits of the data read from the trace buffer duri ng a software-initiated read command (tbacr[rd]), or the write data to be written into the trace buffer during a software-initiated write command (tbacr[wr]). tbacr must be confi gured to perform a read before th is register contains valid data. this register must be initialized by software before configuring th e tbacr to perform a write command. table 20-21 describes tbadhr. 20.3.2.8 trace buffer acce ss data register (tbadr) the trace buffer access data register (tbadr), shown in figure 20-16 , contains the low- order 32 bits of the data read from the trace buffe r during a software-initiated read command (tbacr[rd]) or the write data to be written into the tra ce buffer during a software-initiated write command (tbacr[wr]). tbacr must be configured to perform a re ad before this register contains valid data. this register must be initialized by software before configuri ng the tbacr to perform a write command. table 20-22 describes the tbadr field. 0 31 r tbadh w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x064 figure 20-15. trace buffer read hi gh register (tbadhr) table 20-21. tbadhr field descriptions bits name description 0?31 tbadh trace buffer access data high. the higher 32 bits of the data read from or to be written into the trace buffer, depending on whether the array is accessed with a read or a write. 0 31 r tbad w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x068 figure 20-16. trace buffer access data register (tbadr) table 20-22. tbadr field descriptions bits name description 0?31 tbad trace buffer access data. corresponds to the lower 32 bits of the data read from the trace buffer or to be written into the trace buffer, depending on whether software is accessing the array with a read or a write. 4 datasheet u .com
debug features and watchpoint facility MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 20-22 freescale semiconductor 20.3.3 context id registers this section describes the context i d registers. the current context i d register (ccidr) and programmed context id registers (pcidr) are set by softwa re and facilitate debugging complex software. 20.3.3.1 programmed context id register (pcidr) the programmed context id regi ster (pcidr), shown in figure 20-17 , contains the user-programmed context id. this register can be c onfigured to trigger watchpoint events when its value ma tches the current context id register (ccidr ), as controlled by wmcr0[ ecen] and wmcr0[necen]. see section 20.3.1.1, ?watchpoint monitor cont rol registers 0?1 (wmcr0, wmcr1),? for more information. table 20-23 describes the pcidr field. 20.3.3.2 current context id register (ccidr) the current context id regi ster (ccidr), shown in figure 20-18 , contains the current context id. this register is written by software after a context switch and can be used to trigger events when compared with the programmed context id register (pcidr). 0 31 r pcid w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x0a0 figure 20-17. programmed context id register (pcidr) table 20-23. pcidr field descriptions bits name description 0?31 pcid programmed context id. contains the user-progr ammed context id. compared with current context id for context-sensitive event triggering 0 31 r ccid w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x0a4 figure 20-18. current contex t id regist er (ccidr) 4 datasheet u .com
debug features and watchpoint facility MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 20-23 table 20-24 describes the ccidr field. 20.3.4 trigger out function trig_out provides a convenient mechanism for tri ggering external system monitors and diagnostic equipment such as logic analyzers. note that re ady is multiplexed with trig_out. see the last paragraph of section 4.4.2, ?power-on reset sequence,? for more information about ready functionality. when the trace buffer hit is selected by tosr[sel], trig_out is only meaningf ul if the trace buffer control register 0 (tbcr0) is properl y configured to hit on a traceable event. the same holds true for the watchpoint monitor when the watchpoint monitor is selected by tosr[sel]. 20.3.4.1 trigger out source register (tosr) the trigger out source register (tosr) shown in figure 20-19 specifies the source for trig_out. the three event-trigger sources are the following: ? the watchpoint monitor ? the trace buffer ? the performance monitor table 20-24. ccidr field descriptions bits name description 0?31 ccid current context id. set by user software. typica lly loaded immediately following a context switch. compared with user-programmed context id for context-sensitive event triggering 04578 31 r 0 0 0 0 0 sel 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x0b0 figure 20-19. trigger out source register (tosr) 4 datasheet u .com
debug features and watchpoint facility MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 20-24 freescale semiconductor table 20-25 describes the tosr fields. 20.4 functional description the debug features on the MPC8555E use the pci inte rface, the lbc interfaces, and the ddr sdram interface. 20.4.1 source and target id debug information that is common to a ll the interfaces is the source id (sid). the transaction source id provides enough information to determine which bloc k or port originated a transaction including the distinction between instruction and da ta fetches from the processor core. table 20-26 shows the values and interpretation for the 5-bit sid field. note that the ta ble also includes ports that are only slaves, such as local memory. these ports are always targets. as suc h, the value shown represents a target id (tid) and not a source id. for ports that can function in both capacities, the value indi cates source id when mastering transactions, and target id when responding as slave. the ti d field is only meaningful when one of the following participates in the transaction: ? the e500 coherency module (ecm) dispatch bus ? the watchpoint monitor (wmcr1[ifsel] = 000) ? the trace buffer (tbcr1[ifsel] = 000) table 20-25. tosr field descriptions bits name description 0?4 ? reserved 5?7 sel select. selects th e source for trig_out 000 ready signal. multiplexed with trig_out. basic de vice state indicator. r eady asserts whenever the device is not in reset or not asleep. see chapter 4, ?reset, clocking, and initialization,? for more details about the reset sequence, and chapter 18, ?global utilities,? for more information about power management states. 001 selects the watchpoint monitor hit indication 010 selects the trace buffer hit indication 011 selects the performance monitor overflow indication 8?31 ? reserved table 20-26. source and target id values value (hex) source (or target) port value (hex) source (or target) port 00 pci1 10 local processor (instruction fetch) 01 pci2 11 local processor (data fetch) 02 reserved 12 reserved 03 reserved 13 reserved 04 local bus controller 14 cpm 05 reserved 15 dma 4 datasheet u .com
debug features and watchpoint facility MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 20-25 20.4.2 pci interface debug if pci1_gnt3 is low when sampled during por, the pci interface operates in debug mode. pci debug mode is only possible when pci1 is configured as a 64-bit interface. in debug mode the s ource id appears on the high-order address bits (pci 1_ad[62:58]) during the bus command phase of a pci transaction. the bus command phase occurs either dur ing the first cycle that pci1_frame is asserted, or, in the case of addresses greater than 32 bits, after a dual-address cycle phase. in either ca se, the debug information appears on the highest order a ddress bits while pci1_frame is asserted and both pci1_irdy and pci1_trdy are negated. when accessing the low 4 gbytes of pci address sp ace for which no dual-address cycle is needed, the debug information appears during the first (and onl y) address phase on pci1 _ad[62:58]. whenever a dual-address cycle must be r un, (addresses above 4 gbytes) th e debug information appears on pci1_ad[62:58] during the sec ond address cycle. in either case a l ogic analyzer should be configured to sample information on the first cycl e of the assertion of pci1_frame and the cycle following a dual-address cycle command. note because they share the same pins, an entire 64-bit address and the debug information cannot be captured in a single cycle. 20.4.3 ddr sdram interface debug the ddr interface has two debug mode s distinguished by which pins dr ive the debug information. in one mode, debug information (source id, da ta valid) is multiplexed onto the ecc pins; the other mode uses the debug pins. 06 reserved 16 reserved 07 security 17 system access port (sap) 08 configuration space 18 tsec1 09 reserved 19 tsec2 0a boot sequencer 1a reserved 0b reserved 1b reserved 0c reserved 1c reserved 0d reserved 1d reserved 0e reserved 1e reserved 0f local space (ddr) 1f non valid port indicator (reserved for debug info) table 20-26. source and target id values (continued) value (hex) source (or target) port value (hex) source (or target) port 4 datasheet u .com
debug features and watchpoint facility MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 20-26 freescale semiconductor 20.4.3.1 debug information on debug pins if msrcid0 is high when sampled during por, the debug informati on from the ddr sdram interface is driven on msrcid[0:4] and mdval. this por value is captured in pordbgmsr[mem_sel] as described in section 18.4.1.5, ?por debug mode stat us register (pordbgmsr).? in this mode, the source id appears on msrcid[0:4] during a ras or cas cycle. during any other cycle, the value of msrcid[0:4] is all ones, which indicates idle cy cles on the address/command interface. similarly, mdval is asserted during valid da ta cycles on the ddr interface. 20.4.3.2 debug information on ecc pins if msrcid1 is low when sampled during por, de bug information from the ddr sdram interface is selected to appear on mecc[0:5] as shown in figure 20-1 . in this mode, the id va lue of the source port, (the source id), appears on mecc[0:4] during a ras or cas cycle. during any othe r cycle the value of mecc[0:4] is all ones. a data-val id signal (dval) is driven on mecc5 during valid ddr sdram data cycles. note in this mode, mecc[0:5] must be disconnected from al l sdram devices to prevent contention on those lines. 20.4.4 local bus interface debug if msrcid0 is low when sampled during por, the lbc is selected as the source for the debug information appearing on msrcid[0:4] and mdva l. for more information on this mode, see section 13.1.3.2, ?source id debug mode.? 20.4.5 watchpoint monitor the watchpoint monitor (wm) can be programmed to arm and trigger on many different events including any of the following: ? external event (through trig_in) ? a trace buffer event ? a performance monitor overflow event ? a comparison of the current and programmed context id registers. a watchpoint event can be used in the following ways: ? trigger a logic analyzer (using trig_out) ? arm or trigger the trace buffer ? trigger a performance monitor event. the large counters available in the performance m onitor block and the interlock between it and the watchpoint monitor support sophisticated debug scenarios. a wm trigger event may be composed of several ev ents programmed in the watchpoint monitor control registers (wmcr0?wmcr1). because the watchpoint monitor is disabl ed by default during por, these 4 datasheet u .com
debug features and watchpoint facility MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 20-27 registers must be init ialized to make use of this debug feature. note that th e wm address mask register (wmamr) and the type mask register (wmtmr) are cleared during por. this means that the watchpoint monitor?s default behavior following a po wer-on reset is to trigge r on any address and no transaction type. the reset value of wmcr0[tmd] is 0 which means tr ansaction matching is enabled but since no transaction is sel ected (wmtmr = 0), a match will never occur. either the transaction matching must be disabled by settin g wmcr0[tmd] to a value of 1, or vali d transactions must be selected by setting one or more of the wmtmr bits to a value of 1. 20.4.5.1 watchpoint monitor performance monitor events the wm can produce a performance monitor (pm) even t with every trigger. this is accomplished by configuring the performance monitor to count wm even ts. for more information on this configuration see the events named ?number of wa tchpoint monitor hits? and ?num ber of trace buffer hits? in table 19-10 . multi-level triggers can be created using the watchpoint monitor, the performance monitor, and the trace buffer combined. for example, the wm can be programme d to trigger on events that also increment a pm counter (the performance m onitor must also be programmed to res pond to this event), the output of which (perfmon_overflow) could trigger the st art of tracing in the trace buffer. 20.4.6 trace buffer the trace buffer is a 256 64 array that can capture informati on about the internal processing of transactions to selected interfaces. the trace buffer controls are a s uperset of those for the watchpoint monitor. close inspection of the tr ace buffer control registers (tbcr n ) and the wm control registers (wmcr n ) shows that trace buffer cont rols not needed for the wm are marked reserved in wmcr n . this permits using the trace buffer as a second watchpoint monitor by si mply ignoring the trace options. the trace buffer provides great flexibility about when to start tracing, when to stop tracing, and what to trace. the trace mode field, tbcr 0[mode], indicates when to tra ce: on every valid cycle, on a watchpoint monitor event, or when all the programmed events in the t bcr are met. this permits a user to program the trace condition in th e watchpoint monitor and to program a start or stop condition in the trace buffer control register. the us er can also program the tbcr with the conditions in which to stop tracing: on an event, or when the buffer is full. tbcr0[ifsel] specif ies which interface transactions are being captured. the trace buffer can be programmed to trace th e dispatch bus from any of the following: ? e500 coherency module (ecm) ? outbound host interface to the pci controller ? host interface to the ddr controller transactions come into the ecm, arbitrate for common resources, and get dispatched to the target port. information such as transaction types, source id, and other at tributes can be captured in any of the selected interfaces. 4 datasheet u .com
debug features and watchpoint facility MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 20-28 freescale semiconductor 20.4.6.1 traced data formats ( as a function of tbcr1[ifsel]) figure 20-20 shows the trace buffer entry form at for an ecm dispatch (cmd) transaction that is specified when tbcr1[ifsel] = 000. table 20-27 describes the fields of cmd trace buffer entries. figure 20-21 shows the trace buffer entry format for the ddr sdram interf ace, tbcr1[ifsel] = 001. 0 4 5 9 10 13 14 18 19 31 32 63 r cmdtt cmdsid cmdtid cmdbc ? cmdaddr w reset 0000_0000_0000_0000_0000_0000_0000_0000 figure 20-20. e500 coherency module dispatch (cmd) trace buffer entry table 20-27. cmd trace buffer entry field descriptions (tbcr1[ifsel] = 000) bits name function 0?4 cmdtt transaction type. specifies the transaction type as shown in table 20-12 . for example, a value of zero indicates a write with local processor snoop condition. 5?9 cmdsid source id. identifies the source of the transaction as shown in table 20-26 . for example, a value of 010101 indicates that dma is the transaction source. 10?13 cmdtid target id. identifies the targ et of the transaction as shown in table 20-26 . for example, a value of 010101 indicates that dma is the transaction target. 14?18 cmdbc byte count. range: 32 to 1 where a value of 0 indicates 32 bytes. 00000 = 32 bytes 00001 = 1 byte 00010 = 2 bytes 11110 = 30 bytes 11111 = 31 bytes 19?31 ? reserved 32?63 cmdaddr address bits 0?31 0 4 5 9 10 13 14 18 19 31 32 63 r ddrtt ddrsid ? ddrbc ? ddraddr w reset 0000_0000_0000_0000_0000_0000_0000_0000 figure 20-21. ddr trace buffer entry 4 datasheet u .com
debug features and watchpoint facility MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 20-29 table 20-28 describes the fields of ddr sdram tr ace buffer entries when tbcr1[ifsel] = 001. figure 20-22 shows the pci trace buffer entr y format when tbcr1[ifsel] = 010. table 20-29 describes the fields of pci trace buffer entries when tbcr1[ifsel] = 010. 20.5 initialization configuring the appropriate control re gister must be the last step in the initialization sequence for either the watchpoint or trace buffer. that is, all required register s except the corresponding control register must be configured before any control register bits that enable watc hpoint or trace events are set. table 20-28. ddr trace buffer entry field descriptions (tbcr1[ifsel] = 001) bits name function 0?4 ddrtt transaction type. specifies the transaction type as shown in table 20-12 . for example, a value of all zeros maps to write. 5?9 ddrsid source id. specifies the source of the transaction as shown in table 20-26 . for example, a value of 010101 indicates that dma is the transaction source, and so on. 10?13 ?reserved 14?18 ddrbc byte count 19?31 ?reserved 32?63 ddraddr address bits 0?31 0 4 5 9 10 11 12 31 32 63 r pcitt pcisid pcibc ? pciaddr w reset 0000_0000_0000_0000_0000_0000_0000_0000 figure 20-22. pci trace buffer entry table 20-29. pci trace buffer entry field descriptions (tbcr1[ifsel] = 010) bits name function 0?4 pcitt transaction type. specifies the transaction type as shown in table 20-12 . for example, a value of all zeros maps to write. 5?9 pcisid source id. identifie s the source of the transaction as shown in table 20-26 . for example, a value of 010101 identifies dma as the transaction source. 10?11 pcibc byte count. the size of the transaction. 00 32 bytes 01 8 bytes 10 16 bytes 11 24 bytes 12?31 ?reserved 32?63 pciaddr address bits 0?31 4 datasheet u .com
debug features and watchpoint facility MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 20-30 freescale semiconductor 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor v-1 part v cpm features the MPC8555E communications proce ssor module (cpm) is a superset of the mpc8260 powerquicc ii cpm, with enhancements in perf ormance and the addition of hardwa re and microcode routines for supporting high bit-rate protocols like atm and fast ethernet. th e support for multiple high-level data link control (hdlc) channels is enhanced to support up to 256 hdlc channels. this part defines the cpm blocks of the MPC8555E. it c ontains the following chapters: ? chapter 21, ?communications processor module overview,? provides a high-level summary of the MPC8555E features and memory map. ? chapter 22, ?cpm interrupt controller,? describes the cpm interrupt controller of the MPC8555E. ? chapter 23, ?serial interface with time-slot assigner,? describes the serial interface and tsa of the MPC8555E. ? chapter 24, ?cpm multiplexing,? describes how the cpm multip lexing logic (cmx) connects the physical layer (utopia, mii, mode m lines, tdm lines, and proprietary serial lines) to the fccs and sccs. ? chapter 25, ?baud-rate generators (brgs),? describes the eight indepe ndent, identical baud-rate generators (brgs) that can be used with the fccs and sccs. ? chapter 26, ?cpm timers,? describes the four identical 16-bi t general-purpose cpm timers that can alternately be used as two 32-bit timers. ? chapter 27, ?sdma channels,? describes the two phys ical serial dma (sdm a) channels of the MPC8555E. ? chapter 28, ?serial communica tions controllers (sccs),? describes the MPC8555E?s four sccs, which can be configured indepe ndently to implement different protocols for bridging functions, routers, and gateways, and to interface with a wide variety of standard wans, lans, and proprietary networks. ? chapter 29, ?scc uart mode,? describes how the general scc m ode register (gsmr) is used to configure an scc channel to function in uart mode, which prov ides standard serial i/o using asynchronous character-based (start-stop) protocols with rs-232c-type lines. ? chapter 30, ?scc hdlc mode,? describes how hdlc mode is selected for an scc. in hdlc mode, an scc becomes an hdlc c ontroller, and consists of separate transmit and receive sections whose operations are async hronous with the core and can eith er be synchronous or asynchronous with respect to other sccs. ? chapter 31, ?scc bisync mode,? describes how transparent bisy nc mode allows full binary data to be sent with a ny possible character pattern. ? chapter 32, ?scc transparent mode,? describes how an scc in tran sparent mode functions as a high-speed serial-to-parallel a nd parallel-to-se rial converter. 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 v-2 freescale semiconductor ? chapter 33, ?scc appletalk mode,? describes how the MPC8555E provides localtalk protocol support. the appletalk contro ller provides required frame synchronization, bit sequence, preamble, and postamble onto standard hdlc frames. ? chapter 34, ?quicc multi-channel controller (qmc),? describes the qm c protocol, which emulates up to 64 logical channels within one scc using the same time-division-multiplexed (tdm) physical interface. ? chapter 35, ?universal serial bus controller,? describes the MPC8555E usb controller, including basic operation, the pa rameter ram, and registers. ? chapter 36, ?serial manageme nt controllers (smcs),? describes two serial management controllers, full-duplex ports that can be co nfigured independently to support one of three protocols?uart, transparent, or general-circuit interface (gci). ? chapter 37, ?fast communications controllers (fccs),? describes how the fccs can be configured independently to implement differen t protocols. together, they can be used to implement bridging functions, rout ers, and gateways, and to inte rface with a wide variety of standard wans, lans, and proprietary networks. ? chapter 38, ?fcc hdlc controller,? describes the fcc hdlc c ontroller of the MPC8555E. ? chapter 39, ?fcc transparent controller,? describes how the fcc transparent controller functions as a high-speed serial-to-parallel and para llel-to-serial converter. ? chapter 40, ?cpm fast ethernet controller,? describes the fast ethernet controller in the cpm. ? chapter 41, ?atm controller,? describes the atm controller that provides the atm and aal layers of the atm protocol usi ng the universal test and operations physical layer (phy) interface for atm (utopia level ii) for both master and slave modes. ? chapter 42, ?atm aal2,? describes the aal2 microcode package. ? chapter 43, ?serial peri pheral interface (spi),? describes the serial peripheral interface (spi) of the MPC8555E cpm. ? chapter 44, ?i 2 c controller,? describes the i 2 c controller of the cpm. ? chapter 45, ?parallel i/o ports,? describes the four general-purpose i/o ports of the cpm. convention this part uses the following additional notational convention: in figures and tables show ing registers and parameter ram, bold entr ies indicate fields that should be initialized by the user. bold 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 21-1 chapter 21 communications processor module overview the MPC8555E communications processor module (c pm) is a modified version of the mpc8260 powerquicc ii cpm, with enhancements in performa nce and the addition of hardware and microcode routines for supporting high bit-ra te protocols like atm and fast ethernet. the support for multiple high-level data link control (hdlc) channels is enhanced to support up to 64 hdlc channels. 21.1 features the cpm includes various blocks to provide the system with an efficient way to handle data communication tasks. the following is a list of the cpm?s important features. ? communications processor (cp) ? one instruction per clock ? executes code from intern al rom or instruction ram ? 32-bit risc architecture ? tuned for communication environments: instru ction set supports crc computation and bit manipulation. ? internal timer ? interfaces with the embedded e500 core pro cessor through dual-port ram and virtual dma channels for each peripheral controller. (dual- port ram size is 16 kbytes plus 4 kbytes of dedicated instruction ram.) ? handles serial protocols and virtual dma ? two full-duplex fast serial communications c ontrollers (fccs) support the following protocols: ? atm protocol through utopia interface ? ieee 802.3 standard/fast ethernet ? high level data link control (hdlc) ? totally transparent operation ? three full-duplex serial communi cations controllers (sccs) support the following protocols: ? high level/synchronous data link control (hdlc/sdlc) ? localtalk (hdlc-based local area network protocol) ? universal asynchronous receiver transmitter (uart) ? synchronous uart (1 clock mode) ? binary synchronous communication (bisync) ? totally transparent operation ? qmc support, providing 64 channe ls with only one tdm interface 4 datasheet u .com
communications processor module overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 21-2 freescale semiconductor ? two full-duplex serial management contro llers (smcs) support the following protocols: ? gci (isdn interface) monitor and c/i channels ? uart ? totally transparent operation ? serial peripheral interface (spi ) support for master or slave ?i 2 c bus controller ? time-slot assigner supports multiplexing of data from any of the sccs, fccs, and smcs. the time-slot assigner supports the following tdm formats: ? t1/cept lines ?t3/e3 ? pulse code modulation (pcm) highway interface ? isdn primary rate ? freescale interchi p digital link (idl) ? general circuit interface (gci) ? user-defined interfaces ? universal serial bus (usb 2.0) ? eight independent baud rate generators (brgs) ? four general-purpose 16-bit ti mers or two 32-bit timers ? general-purpose parallel ports?sixteen pa rallel i/o lines with interrupt capability 4 datasheet u .com
communications processor module overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 21-3 figure 21-1 shows the MPC8555E cpm block diagram. figure 21-1. MPC8555E cpm block diagram note the cpm clock frequency is the same as the ccb clock frequency and is determined by the configur ation of the platform p ll during power-on reset. baud rate generators system bus 1 usb 2 fccs 3 sccs spi i 2 c 4 timers parallel i/o ports bus interface sdma dual-port ram communications rom internal bus peripheral bus serial interface (si) and time-slot assigners (tsas) cpm interrupt controller local bus cpm int 2 smcs processor 4 datasheet u .com
communications processor module overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 21-4 freescale semiconductor 21.1.1 cpm memory map table 21-1 shows the cpm portion of the internal memory map. table 21-1. MPC8555E internal memory map address (offset) register access reset section/page cpm dual-port ram 0x8_0000? 0x8_1fff dpram1?dual-port ram r/w ? 21.4/21-28 0x8_2000? 0x8_7fff reserved ? ? ? 0x8_8000? 0x8_9fff dpram2?dual-port ram r/w ? 21.4/21-28 0x8_a000? 0x8_ffff reserved ? ? ? e500 core interface 0x9_0000 cear?cpm error address register r 0x0000_0000 21.2.3.1.1/21-18 0x9_0004 ceer?cpm error event register r/w 0x0000 21.2.3.1.2/21-19 0x9_0006 cemr?cpm error mask register r/w 0x0000 21.2.3.1.3/21-20 sdma 0x9_0050 smaer?system bus address error register r 0x0000_0000 27.1.1/27-2 0x9_0054 reserved ? ? ? 0x9_0058 smevr?system bus event register r/w 0x0000_0000 27.1.2/27-2 0x9_005c smctr?system bus c ontrol register r/w 0x3800_0000 27.1.3/27-3 0x9_0060 lmaer?local bus address error register r 0x0000_0000 27.1.1/27-2 0x9_0064 reserved ? ? ? 0x9_0068 lmevr?local bus event register r/w 0x0000_0000 27.1.2/27-2 0x9_006c lmctr?local bus control register r/w 0x3800_0000 27.1.3/27-3 interrupt controller 0x9_0c00 sicr?cpm interrupt config uration register r/w 0x0000_0000 22.5.1.1/22-9 0x9_0c02 reserved ? ? ? 0x9_0c04 sivec?cpm interrupt vector register r/w 0x0000_0000 22.5.1.5/22-14 0x9_0c08 sipnr_h?cpm interrupt pending register (high) r/w 0x0000_0000 22.5.1.3/22-11 0x9_0c0c sipnr_l?cpm interrupt pending register (low) r/w 0x0000_0000 22.5.1.3/22-11 0x9_0c10 reserved ? ? ? 0x9_0c14 scprr_h?cpm interrupt priority register (high) r/w 0x0530_9770 22.5.1.2/22-10 4 datasheet u .com
communications processor module overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 21-5 0x9_0c18 scprr_l?cpm interrupt priority register (low) r/w 0x0530_9770 22.5.1.2/22-10 0x9_0c1c simr_h?cpm interrupt mask register (high) r/w 0x0000_0000 22.5.1.4/22-12 0x9_0c20 simr_l?cpm interrupt mask register (low) r/w 0x0000_0000 22.5.1.4/22-12 0x9_0c24 siexr?cpm external interrupt control register r/w 0x0000_0000 22.5.1.6/22-15 0x9_0c28? 0x9_0c7f reserved ? ? ? clock 0x9_0c80 sccr?system clock control register r/w 0x0000_0000 25.1/25-2 input/output port 0x9_0d00 pdira?port a data direction register r/w 0x0000_0000 45.2.2.2/45-5 0x9_0d04 ppara?port a pin assignment register r/w 0x0000_0000 45.2.4/45-10 0x9_0d08 psora?port a special options register r/w 0x0000_0000 45.2.5/45-13 0x9_0d0c podra?port a open drain register r/w 0x0000_0000 45.2.1/45-1 0x9_0d10 pdata?port a data register r/w 0x0000_0000 45.2.2/45-4 0x9_0d14? 0x9_0d1f reserved ? ? ? 0x9_0d20 pdirb?port b data direction register r/w 0x0000_0000 45.2.2.2/45-5 0x9_0d24 pparb?port b pin assignment register r/w 0x0000_0000 45.2.4/45-10 0x9_0d28 psorb?port b special options register r/w 0x0000_0000 45.2.5/45-13 0x9_0d2c podrb?port b open drain register r/w 0x0000_0000 45.2.1/45-1 0x9_0d30 pdatb?port b data register r/w 0x0000_0000 45.2.2/45-4 0x9_0d34? 0x9_0d3f reserved ? ? ? 0x9_0d40 pdirc?port c data direction register r/w 0x0000_0000 45.2.2.2/45-5 0x9_0d44 pparc?port c pin assignment register r/w 0x0000_0000 45.2.4/45-10 0x9_0d48 psorc?port c special options register r/w 0x0000_0000 45.2.5/45-13 0x9_0d4c podrc?port c open drain register r/w 0x0000_0000 45.2.1/45-1 0x9_0d50 pdatc?port c data register r/w 0x0000_0000 45.2.2/45-4 0x9_0d54? 0x9_0d5f reserved ? ? ? 0x9_0d60 pdird?port d data direction register r/w 0x0000_0000 45.2.2.2/45-5 0x9_0d64 ppard?port d pin assignment register r/w 0x0000_0000 45.2.4/45-10 0x9_0d68 psord?port d special options register r/w 0x0000_0000 45.2.5/45-13 table 21-1. MPC8555E internal memory map (continued) address (offset) register access reset section/page 4 datasheet u .com
communications processor module overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 21-6 freescale semiconductor 0x9_0d6c podrd?port d open drain register r/w 0x0000_0000 45.2.1/45-1 0x9_0d70 pdatd?port d data register r/w 0x0000_0000 45.2.2/45-4 cpm timers 0x9_0d80 tgcr1?timer 1 and timer 2 global configuration register r/w 0x00 26.2.2/26-3 0x9_0d81 reserved ? ? ? 0x9_0d84 tgcr2?timer 3 and timer 4 global configuration register r/w 0x00 26.2.2/26-3 0x9_0d85? 0x9_0d8f reserved ? ? ? 0x9_0d90 tmr1?timer 1 mode register r/w 0x0000 26.2.3/26-5 0x9_0d92 tmr2?timer 2 mode register r/w 0x0000 26.2.3/26-5 0x9_0d94 trr1?timer 1 reference register r/w 0x0000 26.2.4/26-7 0x9_0d96 trr2?timer 2 reference register r/w 0x0000 26.2.4/26-7 0x9_0d98 tcr1?timer 1 capt ure register r/w 0x0000 26.2.5/26-7 0x9_0d9a tcr2?timer 2 ca pture register r/w 0x0000 26.2.5/26-7 0x9_0d9c tcn1?timer 1 counter r/w 0x0000 26.2.6/26-7 0x9_0d9e tcn2?timer 2 counter r/w 0x0000 26.2.6/26-7 0x9_0da0 tmr3?timer 3 mode register r/w 0x0000 26.2.3/26-5 0x9_0da2 tmr4?timer 4 mode register r/w 0x0000 26.2.3/26-5 0x9_0da4 trr3?timer 3 reference register r/w 0x0000 26.2.4/26-7 0x9_0da6 trr4?timer 4 reference register r/w 0x0000 26.2.4/26-7 0x9_0da8 tcr3?timer 3 ca pture register r/w 0x0000 26.2.5/26-7 0x9_0daa tcr4?timer 4 ca pture register r/w 0x0000 26.2.5/26-7 0x9_0dac tcn3?timer 3 counter r/w 0x0000 26.2.6/26-7 0x9_0dae tcn4?timer 4 counter r/w 0x0000 26.2.6/26-7 0x9_0db0 ter1?timer 1 event register r/w 0x0000 26.2.7/26-8 0x9_0db2 ter2?timer 2 event register r/w 0x0000 26.2.7/26-8 0x9_0db4 ter3?timer 3 event register r/w 0x0000 26.2.7/26-8 0x9_0db6 ter4?timer 4 event register r/w 0x0000 26.2.7/26-8 0x9_0db8? 0x9_12ff reserved ? ? ? table 21-1. MPC8555E internal memory map (continued) address (offset) register access reset section/page 4 datasheet u .com
communications processor module overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 21-7 fcc1 0x9_1300 gfmr1?fcc1 general mode register r/w 0x0000_0000 37.2/37-3 0x9_1304 fpsmr1?fcc1 protocol-specific mode register r/w 0x0000_0000 (atm) 41.13.3/41-84 (ethernet) 40.18.2/40-20 (hdlc) 38.6/38-8 0x9_1308 ftodr1?fcc1 transmit on demand register r/w 0x0000 37.6/37-8 0x9_130a reserved ? ? ? 0x9_130c fdsr1?fcc1 data synchronization register r/w 0x7e7e 37.5/37-7 0x9_130e reserved ? ? ? 0x9_1310 fcce1?fcc1 event re gister r/w 0x0000_0000 (atm) 41.13.4/41-86 (ethernet) 40.18.3/40-22 (hdlc) 38.9/38-14 0x9_1314 fccm1?fcc1 mask register r/w 0x0000_0000 (atm) 41.13.4/41-86 (ethernet) 40.18.3/40-22 (hdlc) 38.9/38-14 0x9_1316 reserved ? ? ? 0x9_1318 fccs1?fcc1 status register r 0x00 38.10/38-16 (hdlc) 0x9_1319 reserved ? ? ? 0x9_131c ftirr1_phy0?fcc1 transmit internal rate registers for phy0 r/w 0x00 41.13.5/41-87 (atm) 0x9_131d ftirr1_phy1?fcc1 transmit internal rate registers for phy1 r/w 0x00 41.13.5/41-87 (atm) 0x9_131e ftirr1_phy2?fcc1 transmit internal rate registers for phy2 r/w 0x00 41.13.5/41-87 (atm) 0x9_131f ftirr1_phy3?fcc1 transmit internal rate registers for phy3 r/w 0x00 41.13.5/41-87 (atm) table 21-1. MPC8555E internal memory map (continued) address (offset) register access reset section/page 4 datasheet u .com
communications processor module overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 21-8 freescale semiconductor fcc2 0x9_1320 gfmr2?fcc2 general mode register r/w 0x0000_0000 37.2/37-3 0x9_1324 fpsmr2?fcc2 protocol-specific mode register r/w 0x0000_0000 (atm) 41.13.3/41-84 (ethernet) 40.18.2/40-20 (hdlc) 38.6/38-8 0x9_1328 ftodr2?fcc2 transmit on-demand register r/w 0x0000 37.6/37-8 0x9_132a reserved ? ? ? 0x9_132c fdsr2?fcc2 data synchronization register r/w 0x7e7e 37.5/37-7 0x9_132e reserved ? ? ? 0x9_1330 fcce2?fcc2 event re gister r/w 0x0000_0000 (atm) 41.13.4/41-86 (ethernet) 40.18.3/40-22 (hdlc) 38.9/38-14 0x9_1334 fccm2?fcc2 mask register r/w 0x0000_0000 (atm) 41.13.4/41-86 (ethernet) 40.18.3/40-22 (hdlc) 38.9/38-14 0x9_1336 reserved ? ? ? 0x9_1338 fccs2?fcc2 status register r 0x00 38.10/38-16 (hdlc) 0x9_1339? 0x9_137f reserved ? 0x00 ? 0x9_133c ftirr2_phy0?fcc2 transmit internal rate registers for phy0 r/w 0x00 41.13.5/41-87 (atm) 0x9_133d ftirr2_phy1?fcc2 transmit internal rate registers for phy1 r/w 0x00 41.13.5/41-87 (atm) 0x9_133e ftirr2_phy2?fcc2 transmit internal rate registers for phy2 r/w 0x00 41.13.5/41-87 (atm) 0x9_133f ftirr2_phy3?fcc2 transmit internal rate registers for phy3 r/w 0x00 41.13.5/41-87 (atm) 0x9_1340? 0x9_137f reserved ? ? ? table 21-1. MPC8555E internal memory map (continued) address (offset) register access reset section/page 4 datasheet u .com
communications processor module overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 21-9 fcc1 (continued) 0x9_1380 firper1?fcc1 internal rate port enable register r/w 0x0000_0000 41.15.3/41-90 0x9_1384 firer1?fcc1 internal rate event register r/w 0x0000_0000 41.15.4/41-91 0x9_1388 firsr1_hi?fcc1 internal rate selection register:hi r/w 0x0000_0000 41.15.5/41-92 0x9_138c firsr1_lo? fcc1 internal rate selection register:lo r/w 0x0000_0000 41.15.5/41-92 0x9_1390 gfemr1?general fcc1 expansion mode register r/w 0x00 37.3/37-7 0x9_1391? 0x9_139f reserved ? ? ? fcc2 (continued) 0x9_13a0 firper2?fcc2 internal rate port enable register r/w 0x0000_0000 41.15.3/41-90 0x9_13a4 firer2?fcc2 internal ra te event register r/w 0x0000_0000 41.15.4/41-91 0x9_13a8 firsr2_hi?fcc2 internal rate selection register:hi r/w 0x0000_0000 41.15.5/41-92 0x9_13ac firsr2_lo?fcc2 internal rate selection register:lo r/w 0x0000_0000 41.15.5/41-92 0x9_13b0 gfemr2?general fcc2 expansion mode register r/w 0x00 37.3/37-7 0x9_13b1? 0x9_15ef reserved ? ? ? brgs 5?8 0x9_15f0 brgc5?brg5 configurat ion register r/w 0x0000_0000 25.2/25-3 0x9_15f4 brgc6?brg6 configurat ion register r/w 0x0000_0000 25.2/25-3 0x9_15f8 brgc7?brg7 configurat ion register r/w 0x0000_0000 25.2/25-3 0x9_15fc brgc8?brg8 configuration register r/w 0x0000_0000 25.2/25-3 0x9_1600? 0x9_185f reserved ? ? ? i 2 c 0x9_1860 i2mod?i 2 c mode register r/w 0x00 44.4.1/44-6 0x9_1861 reserved ? ? ? 0x9_1864 i2add?i 2 c address register r/w 0x00 44.4.2/44-7 0x9_1865 reserved ? ? ? 0x9_1868 ii2brg?i 2 c brg register r/w 0x00 44.4.3/44-7 0x9_1869 reserved ? ? ? 0x9_186c i2com?i 2 c command register r/w 0x00 44.4.5/44-8 0x9_186d reserved ? ? ? table 21-1. MPC8555E internal memory map (continued) address (offset) register access reset section/page 4 datasheet u .com
communications processor module overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 21-10 freescale semiconductor 0x9_1870 i2cer?i 2 c event register r/w 0x00 44.4.4/44-7 0x9_1871 reserved ? ? ? 0x9_1874 i2cmr?i 2 c mask register r/w 0x00 44.4.4/44-7 0x9_1875? 0x9_19bf reserved ? ? ? communications processor 0x9_19c0 cpcr?communications processor command register r/w 0x0000_0000 21.3.1/21-24 0x9_19c4 rccr?cp configuration register r/w 0x0000_0000 21.2.6/21-22 0x9_19c8? 0x9_19d5 reserved ? ? ? 0x9_19d6 rter?cp timers event register r/w 0x0000 21.5.4/21-35 0x9_19da rtmr?cp timers mask register r/w 0x0000 21.5.4/21-35 0x9_19dc rtscr?cp time-stamp timer control register r/w 0x0000 21.2.7/21-23 0x9_19de reserved ? ? ? 0x9_19e0 rtsr?cp time-stamp register r/w 0x0000_0000 21.2.8/21-24 brgs 1?4 0x9_19f0 brgc1?brg1 configurat ion register r/w 0x0000_0000 25.2/25-3 0x9_19f4 brgc2?brg2 configurat ion register r/w 0x0000_0000 25.2/25-3 0x9_19f8 brgc3?brg3 configurat ion register r/w 0x0000_0000 25.2/25-3 0x9_19fc brgc4?brg4 configuration register r/w 0x0000_0000 25.2/25-3 scc1 0x9_1a00 gsmr_l1?scc1 general mode register r/w 0x0000_0000 28.2/28-3 0x9_1a04 gsmr_h1?scc1 general mode register r/w 0x0000_0000 28.2/28-3 0x9_1a08 psmr1?scc1 protocol-spec ific mode register r/w 0x0000 28.2/28-3 29.16/29-12 (uart) 30.8/30-7 (hdlc) 31.11/31-9 (bisync) 32.9/32-8 (transparent) 0x9_1a0a reserved ? ? ? 0x9_1a0c todr1?scc1 transmit-on-demand register r/w 0x0000 28.2.3/28-9 0x9_1a0e dsr1?scc1 data synchronization register r/w 0x7e7e 28.2.2/28-8 table 21-1. MPC8555E internal memory map (continued) address (offset) register access reset section/page 4 datasheet u .com
communications processor module overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 21-11 0x9_1a10 scce1?scc1 event register r/w 0x0000 29.19/29-18 (uart) 30.11/30-12 (hdlc) 31.14/31-14 (bisync) 32.12/32-11 (transparent) 0x9_1a12? 0x9_1a13 reserved ? ? ? 0x9_1a14 sccm1?scc1 mask register r/w 0x0000 29.19/29-18 (uart) 30.11/30-12 (hdlc) 31.14/31-14 (bisync) 32.12/32-11 (transparent) 0x9_1a16 reserved ? ? ? 0x9_1a17 sccs1?scc1 stat us register r/w 0x00 29.20/29-20 (uart) 30.12/30-13 (hdlc) 31.15/31-15 (bisync) 32.13/32-12 (transparent) 0x9_1a18? 0x9_1a3f reserved ? ? ? scc3 0x9_1a40 gsmr_l3?scc3 general mode register r/w 0x0000_0000 28.2/28-3 0x9_1a44 gsmr_h3?scc3 general mode register r/w 0x0000_0000 0x9_1a48 psmr3?scc3 protocol-spec ific mode register r/w 0x0000 28.2.1/28-8 29.16/29-12 (uart) 30.8/30-7 (hdlc) 31.11/31-9 (bisync) 32.9/32-8 (transparent) 0x9_1a4a reserved ? ? ? 0x9_1a4c todr3?scc3 transmit on demand register r/w 0x0000 28.2.2/28-8 0x9_1a4e dsr3?scc3 data synchronization register r/w 0x7e7e 28.2.2/28-8 table 21-1. MPC8555E internal memory map (continued) address (offset) register access reset section/page 4 datasheet u .com
communications processor module overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 21-12 freescale semiconductor 0x9_1a50 scce3?scc3 event register r/w 29.19/29-18 (uart) 30.11/30-12 (hdlc) 31.14/31-14 (bisync) 32.12/32-11 (transparent) 0x9_1a52? 0x0x9_1a53 reserved ? ? ? 0x9_1a54 sccm3?scc3 mask register r/w 0x0000 29.19/29-18 (uart) 30.11/30-12 (hdlc) 31.14/31-14 (bisync) 32.12/32-11 (transparent) 0x9_1a56 reserved ? ? ? 0x9_1a57 sccs3?scc3 stat us register r/w 0x00 29.20/29-20 (uart) 30.12/30-13 (hdlc) 31.15/31-15 (bisync) 32.13/32-12 (transparent) 0x9_1a58? 0x9_1a5f reserved ? ? ? scc4 0x9_1a60 gsmr_l4?scc4 general mode register r/w 0x0000_0000 28.2/28-3 0x9_1a64 gsmr_h4?scc4 general mode register r/w 0x0000_0000 28.2/28-3 0x9_1a68 psmr4?scc4 protocol-spec ific mode register r/w 0x0000 28.2.1/28-8 29.16/29-12 (uart) 30.8/30-7 (hdlc) 31.11/31-9 (bisync) 32.9/32-8 (transparent) 0x9_1a6a reserved ? ? ? 0x9_1a6c todr4?scc4 transmit on-demand register r/w 0x0000 28.2.3/28-9 table 21-1. MPC8555E internal memory map (continued) address (offset) register access reset section/page 4 datasheet u .com
communications processor module overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 21-13 0x9_1a6e dsr4?scc4 data synchronization register r/w 0x7e7e 28.2.2/28-8 0x9_1a70 scce4?scc4 event register r/w 29.19/29-18 (uart) 30.11/30-12 (hdlc) 31.14/31-14 (bisync) 32.12/32-11 (transparent) 0x9_1a72? 0x9_1a73 reserved ? ? ? 0x9_1a74 sccm4?scc4 mask register r/w 0x0000 29.19/29-18 (uart) 30.11/30-12 (hdlc) 31.14/31-14 (bisync) 32.12/32-11 (transparent) 0x9_1a76 reserved ? ? ? 0x9_1a77 sccs4?scc4 st atus register ? ? 29.20/29-20 (uart) 30.12/30-13 (hdlc) 31.15/31-15 (bisync) 32.13/32-12 (transparent) 0x9_1a78? 0x9_1a7f reserved ? ? ? smc1 0x9_1a82 smcmr1?smc1 mode register r/w 0x0000 36.2.1/36-2 0x9_1a84 reserved ? 16 bits ? 0x9_1a86 smce1?smc1 event register r/w 0x00 36.3.11/36-18 0x9_1a87 reserved ? 24 bits ? 0x9_1a8a smcm1?smc1 mask register r/w 0x00 36.3.11/36-18 0x9_1a8b? 0x9_1a91 reserved ? 7 bytes ? smc2 0x9_1a92 smcmr2?smc2 mode register r/w 0x0000 36.2.1/36-2 0x9_1a94 reserved ? 16 bits ? table 21-1. MPC8555E internal memory map (continued) address (offset) register access reset section/page 4 datasheet u .com
communications processor module overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 21-14 freescale semiconductor 0x9_1a96 smce2?smc2 event register r/w 0x00 36.3.11/36-18 0x9_1a97 reserved ? 24 bits ? 0x9_1a9a smcm2?smc2 mask register r/w 0x00 36.3.11/36-18 0x9_1a9b? 0x9_1a9f reserved ? 5 bytes ? spi 0x9_1aa0 spmode?spi mode register r/w 0x0000 43.4.1/43-6 0x9_1aa2 reserved ? ? ? 0x9_1aa6 spie?spi event register r/w 0x00 43.4.2/43-9 0x9_1aa7 reserved ? ? ? 0x9_1aaa spim?spi mask register r/w 0x00 43.4.2/43-9 0x9_1aab reserved ? ? ? 0x9_1aad spcom?spi command register w 0x00 43.4.3/43-10 0x9_1aa7? 0x9_1b00 reserved ? ? ? cpm mux 0x9_1b02 cmxsi2cr?cpm mux si2 cl ock route register r/w 0x00 24.4.2/24-8 0x9_1b03 reserved ? ? ? 0x9_1b04 cmxfcr?cpm mux fcc cloc k route register r/w 0x0000_0000 24.4.3/24-8 0x9_1b08 cmxscr?cpm mux scc clock route register r/w 0x0000_0000 24.4.4/24-10 0x9_1b0c cmxsmr?cpm mux smc clock route register r/w 0x00 24.4.5/24-13 0x9_1b0e cmxuar?cpm mux utopia address register r/w 0x0000 24.4.1/24-5 0x9_1b10? 0x9_1b3f reserved ? ? ? si2 registers 0x9_1b40 si2amr?si2 tdma2 mode register r/w 0x0000 23.6.2/23-14 0x9_1b42 si2bmr?si2 tdmb2 mode register r/w 0x0000 23.6.2/23-14 0x9_1b44 si2cmr?si2 tdmc2 mode register r/w 0x0000 23.6.2/23-14 0x9_1b46 reserved r/w 16 bits 23.6.2/23-14 0x9_1b48 si2gmr?si2 global mode register r/w 0x00 23.6.1/23-14 0x9_1b49 reserved ? ? ? 0x9_1b4a si2cmdr?si2 comm and register r/w 0x00 23.6.4/23-20 0x9_1b4b reserved ? ? ? table 21-1. MPC8555E internal memory map (continued) address (offset) register access reset section/page 4 datasheet u .com
communications processor module overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 21-15 0x9_1b4c si2str?si2 status register r/w 0x00 23.6.5/23-21 0x9_1b4d reserved ? ? ? 0x9_1b4e si2rsr?si2 ram shadow address register r/w 0x0000 23.6.3/23-20 0x9_1b50? 0x9_1b5f reserved ? ? ? usb 0x9_1b60 usmod?usb mode register r/w 0x00 35.5.7.1/35-17 0x9_1b61 usadr?usb address register r/w 0x00 35.5.7.2/35-18 0x9_1b62 uscom?usb command register r/w 0x00 35.5.7.4/35-19 0x9_1b64 usep1?usb endpoint 1 register r/w 0x0000 35.5.7.3/35-18 0x9_1b66 usep2?usb endpoint 2 register r/w 0x0000 35.5.7.3/35-18 0x9_1b68 usep3?usb endpoint 3 register r/w 0x0000 35.5.7.3/35-18 0x9_1b6a usep4?usb endpoint 4 register r/w 0x0000 35.5.7.3/35-18 0x9_1b6c? 0x9_1b6f reserved ? 32 bits ? 0x9_1b70 usber?usb event register r/w 0x0000 35.5.7.5/35-20 0x9_1b72 reserved ? 16 bits ? 0x9_1b74 usbmr?usb mask register r/w 0x0000 35.5.7.6/35-21 0x9_1b77 usbs?usb status register r/w 0x00 35.5.7.7/35-21 0x9_1b79? 0x9_1fff reserved ? 1174 bytes ? si2 ram 0x9_2800? 0x9_29ff si2txram?si 2 transmit routing ram ? ? 23.5.3/23-9 0x9_2a00? 0x9_2bff reserved ? ? ? 0x9_2c00? 0x9_2dff si2rxram?si 2 receive routing ram ? ? 23.5.3/23-9 0x9_2e00? 0x9_3fff reserved ? ? ? instruction ram 0xa_0000? 0xa_0fff dual-port ram (instruction ram only) ? ? 21.4/21-28 table 21-1. MPC8555E internal memory map (continued) address (offset) register access reset section/page 4 datasheet u .com
communications processor module overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 21-16 freescale semiconductor 21.2 communications processor (cp) the communications processor (cp), also called the risc microcontroller, is a 32-bit controller for the cpm that resides on a separate bus from the core and, therefore, can pe rform tasks independent of the e500 core. the cp handles lower-layer communications tasks and dma cont rol, freeing the core to handle higher-layer activities. the cp works with the peri pheral controllers and parallel port to implement user-programmable protocols and mana ge the serial dma (sdma) channe ls that transfer data between the i/o channels and memory. it also contains an internal timer used to implement up to 16 additional software timers. the cp?s architecture and instruct ion set are optimized for data co mmunications and data processing required by many wire-line and wire less communications standards. 21.2.1 features the following is a list of the cp?s primary features. ? one system clock cycle per instruction ? 32-bit instruction object code ? executes code from intern al rom or instruction ram ? 32-bit alu data path ? 64-bit internal ram access ? optimized for commun ications processing ? performs dma bursting of serial data from/to internal ram/external memory ? tuned for communications environments?instr uction set supports crc computation and bit manipulation ? internal timer ? interfaces with the cpu through 16 kbytes of internal dual-port ram and virtual dma channels for each serial channel ? handles serial protocols 21.2.2 cp block diagram the cp contains the fo llowing functional units: ? scheduler and sequencer ? instruction decoder ? execution unit ? load/store unit (lsu) ? block transfer module (btm)?moves data between serial fifo and ram ? eight general purpose registers (gprs) ? special registers, crc machine, hdlc framer 4 datasheet u .com
communications processor module overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 21-17 the cp also gives sdma commands to the sdma. the cp interfaces with the dual-port ram for loading and storing data. figure 21-2 shows the cp block diagram. figure 21-2. communications pr ocessor (cp) block diagram general- load/store unit block transfer dual-port ram microcode dma execution source buses destination bus address data address data address data peripheral bus scheduler decoder instruction to all units bus communications processor (cp) timer special sequencer registers unit data address data data rom/i-ram instruction address address data interface local bus system bus module (btm) purpose registers 4 datasheet u .com
communications processor module overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 21-18 freescale semiconductor 21.2.3 e500 core interface the cp communicates with the e500 core in several ways: ? many parameters are exchanged through the dual-port ram. ? the cp can execute special commands issued by the core. these commands should only be issued in special situations like exceptions or error recovery. ? the cp generates interrupts to the cpm inte rrupt controller, which is connected to the programmable interrupt contro ller (pic) of the MPC8555E. ? the e500 core can read the cpm st atus/event regist ers at any time. 21.2.3.1 error reporting and capture when the e500 core (or any other master) tries to read from or write to the cp m registers or internal memories and an erroneous condition is recogni zed, the cpm reports the event and captures the information in the cpm error registers. the following sections desc ribe these registers. 21.2.3.1.1 cpm error ad dress register (cear) the cpm error address regi ster (cear), shown in figure 21-3 , is a read-only regist er that contains the address and attributes of the first er roneous transaction that occurred af ter the last time that the cpm error event register (ceer) was entirely cleared. note that th is register contains inva lid data if the cpm error event register has all of its bits cleared. the ceer is cleared by hreset or as a result of a write transaction. cear is not affected by write transactions. figure 21-3. cpm error address register (cear) 0 78910 15 field byte_en rw ? addr r/w r reset: 0000_0000_0000_0000 1 1 cear is unaffected by soft rese t. it is cleared by hard reset. offset 0x90000 16 31 field addr r/w r reset 0000_0000_0000_0000 1 offset 0x90002 4 datasheet u .com
communications processor module overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 21-19 21.2.3.1.2 cpm error ev ent register (ceer) the cpm error event register contains the type of erro r if an error event has occurred. when an erroneous transaction is recognized, the cpm sets the corres ponding bit in ceer. an interrupt is generated if enabled by the cpm error mask register. note that ceer reflects one or more erroneous events. ceer bits are cleared by hreset or by writing 1 to the appropria te bit; writing 0 has no effect. figure 21-4. cpm error event register (ceer) table 21-2. cear field descriptions bits name description 0?7 byte_en byte enables. contains the byte enab le pattern of the erroneous transaction 8 rw read/write. the read/write attrib ute of the erroneous transaction 1 erroneous transaction type is read 0 erroneous transaction type is write 9 ? reserved. 10?31 addr address. the address of the erroneous transaction . addr[29?31] are always read as zeros. this field contains the internal cpm offset, while the full ad dress is a combination of this field and the base address of the cpm as indicated by the ccsrbar setting. 01234 15 field abort be size nomap ? reset 0000_0000_0000_0000 1 1 ceer is unaffected by soft reset. it is cleared by hard reset. r/w r/w offset 0x90004 table 21-3. ceer field descriptions bits name description 0 abort abort error. asserted if a transaction that was targeted to the cpm was aborted before completion due to an internal error condition in the MPC8555E 1 be byte enable error. set when a transaction with a non-contiguous or all-zeros byte enable pattern is targeted to the cpm 2 size size error. set when an access is attempted to cpm registers, with a byte enable pattern that crosses an aligned 4-byte boundary 3 nomap not mapped. set when an access is targeted into a non-implemented address space. none implemented space is defined by: cpm base + 0x14000 <= address <= cpm base + 0x1ffff, or cpm base + 0x30000 <= address <= cpm base + 0x3ffff 4?15 ? reserved, should be cleared. 4 datasheet u .com
communications processor module overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 21-20 freescale semiconductor 21.2.3.1.3 cpm error mask register (cemr) the cpm error mask register (cemr) is used to mask corresponding even t bits in ceer. setting a mask bit enables the corresponding ceer interrupt. 21.2.4 peripheral interface the cp uses the peripheral bus to communicate with all of its periphe rals. each fcc and each scc has separate receive and tr ansmit fifos. the fcc fifos are 192 byt es. the scc fifos are 32 bytes. the smcs, spi, and i 2 c are all double-buffered, creating effective fifo sizes of two characters. table 21-5 shows the order in which the cp handles reque sts from peripherals from highest to lowest priority. note elevation to emergency stat us (priority 4) is determined on a per peripheral basis and may depend on a periphera l?s mode of operation. emergency prioritization among peripherals mainta ins relative normal prioritization. for example, simultaneous emergency requests from fcc1 transmit and scc1 transmit would be handled in the same order as normal requests (fcc1 transmit). 01234 15 field abort be size nomap ? reset 0000_0000_0000_0000 r/w r/w offset 0x90006 figure 21-5. cpm error mask register (cemr) table 21-4. cemr field descriptions bits name description 0 abort mask interrupt for abort event 0 interrupt is disabled 1 interrupt is enabled 1 be mask interrupt for be error event 0 interrupt is disabled 1 interrupt is enabled 2 size mask interrupt for size error event 0 interrupt is disabled 1 interrupt is enabled 3 nomap mask interrupt for nomap error event 0 interrupt is disabled 1 interrupt is enabled 4?15 ? reserved, should be cleared. 4 datasheet u .com
communications processor module overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 21-21 21.2.5 execution from ram the cp has an option to execute microcode from a portion of user ram located in the instruction ram (iram). in this mode, the cp fetc hes instructions from both the iram and its own private rom. this mode allows freescale to add new protocols or e nhancements to the MPC8555E in the form of ram microcode packages. if pref erred, the user can obt ain binary microcode from freescale and load it into the iram. table 21-5. peripheral prioritization priority request 1 reset in the cpcr or sreset 2 sdma bus error 3 commands issued to the cpcr 4 emergency (from fccs and sccs) 5usb 6 fcc1 receive 7 fcc1 transmit 8 fcc2 receive 9 fcc2 transmit 10 scc1 receive 11 scc1 transmit 12 scc3 receive 13 scc3 transmit 14 scc4 receive 15 scc4 transmit 16 reserved 17 smc1 receive 18 smc1 transmit 19 smc2 receive 20 smc2 transmit 21 spi receive 22 spi transmit 23 i 2 c receive 24 i 2 c transmit 25 risc timer table 26 reserved 4 datasheet u .com
communications processor module overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 21-22 freescale semiconductor 21.2.6 risc controller conf iguration register (rccr) the risc controller configurat ion register (rccr), shown in figure 21-6 , configures the cp to run microcode from rom or instruction ram and controls the cp?s intern al timer. the rccr register is cleared at reset. rccr bit fields are described in table 21-6. 0 1 2 7 8 111213 15 field time ? timep ? eie ? ? reset 0000_0000_0000_0000 r/w r/w offset 0x9_19c4 16 19 20 21 22 23 24 31 field eram edm1 edm2 edm3 edm4 ? reset 0000_0000_0000_0000 r/w r/w offset 0x9_19c6 figure 21-6. risc c ontroller configuration register (rccr) table 21-6. risc controller configur ation register field descriptions bits name description 0 time timer enable. enables the cp internal timer that generates a tick to the cp based on the value programmed into the timep field. time can be modified at any time to start or stop the scanning of the risc timer tables. 1 ? reserved, should be cleared. 2?7 timep timer period controls the cp timer tick. the risc timer tables are scanned on each timer tick and the input to the timer tick generator is the general system clock (133/166 mhz) divided by 1024. the formula is (timep + 1) 1024 = (general system clock period). thus, a va lue of 0 stored in these bits gives a timer tick of 1 (1024) = 1024 general syst em clocks and a value of 63 (dec imal) gives a timer tick of 64 (1024) = 65,536 general system clocks. 8?11 ? reserved, should be cleared. 12 eie external interrupt enable. when eie is set, dreq1 ac ts as an external interrupt to the cp. configure as instructed in the download process of a freescale-supplied ram microcode package. 0 dreq1 cannot interrupt the cp. 1 dreq1 will interrupt the cp. 13?15 ? reserved, should be cleared. 16?19 eram enable ram microcode. configure as instructed in the download process of a freescale-supplied ram microcode package. otherwise, it should not be used. 0000 disable microcode program execution from the internal ram. 0100 microcode is executed from the instruction ram. other combinations of these bits are not valid and must not be used. 4 datasheet u .com
communications processor module overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 21-23 21.2.7 risc time-stamp control register (rtscr) the risc time-stamp control register (rtscr), shown in figure 21-7 , configures the risc time-stamp register (rtsr). the time-stamp timer is used by the atm and the hdlc controllers. for application examples, see section 41.5.3, ?abr flow control setup,? and section 38.6, ?hdlc mode register (fpsmr).? ? table 21-7 describes rtscr fields. 20?23 edm x edge detect mode. dreq x asserts as follows: 0 low-to-high change 1 high-to-low change 24?31 ? reserved, should be cleared. 0 456 15 field ? rte rtps (timer prescale) reset 0000_0000_0000_0000 r/w r/w offset 0x9_19dc figure 21-7. risc time-stamp control register (rtscr) table 21-7. rtscr field descriptions bits name description 0?4 ? reserved 5 rte time stamp enable 0 disable time-stamp timer 1 enable time-stamp timer 6?15 rtps time-stamp timer pre-scale. must be programmed to generate a 1-s period input clock to the time-stamp timer. time-stamp frequency = (cpm frequency)/(rtps + 2) table 21-6. risc controller configuration register field descriptions (continued) bits name description 4 datasheet u .com
communications processor module overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 21-24 freescale semiconductor 21.2.8 risc time-stamp register (rtsr) the risc time-stamp register (rtsr), shown in figure 21-8 , contains the time stamp. after reset, setting rtscr[rte] causes the time stamp to start counti ng microseconds from zero. 21.2.9 risc microcode revision number the cp writes a revision number stored in its ro m to a dual-port ram location called rev_num that resides in the miscellaneous parameter ram. the other locations are rese rved for future use. table 21-8 describes the risc microcode revision number. 21.3 command set the core issues commands to the cp by writing to the cp command register (cpcr). the cpcr rarely needs to be accessed. for example, to terminate the transmission of an scc?s frame without waiting until the end, a stop tx command must be issued through the cpcr. 21.3.1 cp command register (cpcr) the core sets cpcr[flg], shown in figure 21-9 , when it issues a command. the cp clears flg after completing the command to indicate to the core that it is ready for the next command. subsequent commands to the cpcr can be given only after flg is clear. however, the software reset command, issued by setting rst, does not de pend on the state of flg, although the core should still set flg when setting rst. 0 15 field time stamp reset ? r/w r offset 0x9_19e0 16 31 field time stamp reset ? r/w r offset 0x9_19e2 figure 21-8. risc time-stamp register (rtsr) table 21-8. risc microcode revision number address name width description ram base + 0x8af0 rev_num hword microcode revision number. 0x00e8 ram base + 0x8af2 ? hword reserved 4 datasheet u .com
communications processor module overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 21-25 table 21-9 describes cpcr fields. 0 1 5 6 10 11 14 15 field rst page sub-block code (sbc) ? flg reset 0000_0000_0000_0000 r/w r/w offset 0x9_19c0 16 17 18 25 26 27 28 31 field ? mcn ep opcode reset 0000_0000_0000_0000 r/w r/w offset 0x9_19c2 figure 21-9. cp command register (cpcr) table 21-9. cp command register field descriptions bits name description 0 rst software reset command. set by the core and cleared by the cp. when this command is executed, rst and flg bit are cleared within two general system clocks. the cpm reset rout ine is approximately 60 clocks long, but the user can begin initialization of the cpm immediately after this command is issued. rst is useful when the core wants to reset the regi sters and parameters for all the channels (fccs, sccs, spi, i 2 c) as well as the cp and risc timer tables. ho wever, this command does not affect the serial interface (si x ) or parallel i/o registers. 1?5 page indicates the parameter ram page number asso ciated with the sub-block being served. see the sbc description for page numbers. 6?10 sbc sub-block code. set by the core to specify the sub-block on which the command is to operate. set according to opcode (bits 28?31). sub-block code page sub-block code page fcc1 1 01110: atm transmit (opcode = 1010) 10000: all other commands 00100 spi 01010 01001 fcc2 1 01110: atm transmit (opcode = 1010) 10001: all other commands 00101 i 2 c 01011 01010 scc1 00100 00000 timer 01111 01010 scc3 00110 00010 reserved 10100 00111 scc4 00111 00011 reserved 10101 01000 smc1 01000 00111 reserved 10110 01001 smc2 01001 01000 reserved 10111 01010 rand 01110 01010 usb 10011 01011 11?14 ? reserved 4 datasheet u .com
communications processor module overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 21-26 freescale semiconductor 21.3.1.1 cp commands the cp command opcodes are shown in table 21-10 . 15 flg command semaphore flag. set by the core and cleared by the cp 0 the cp is ready to receive a new command. 1 the cpcr contains a command that the cp is currently processing. t he cp clears this bit at the end of command execution or after reset. 16?17 ? reserved 18?25 mcn in fcc protocols, this field contains the protocol code as follows: 0x00 hdlc 0x0a atm 0x0c ethernet 0x0f transparent 26?27 ep endpoint: logical pipe number (only in usb) 00 endpoint 0 01 endpoint 1 10 endpoint 2 11 endpoint 3 28?31 opcode operation code. settings are listed in table 21-10 . 1 set according to opcode[28?31]. if opcode is 1010, sbc must be 01110. refer to table 21-10 . table 21-10. cp command opcodes opcode channel fcc usb scc smc (uart/ transparent) smc (gci) spi i 2 c timer special 0000 init rx and tx params ? init rx and tx params init rx and tx params init rx and tx params init rx and tx params init rx and tx params ?? 0001 init rx params ? init rx params init rx params ? init rx params init rx params ?? 0010 init tx params ? init tx params init tx params ? init tx params init tx params ?? 0011 enter hunt mode ? enter hunt mode enter hunt mode ?? ??? 0100 stop tx ? stop tx stop tx ?? ??? 0101 graceful stop tx ? graceful stop tx ??? ??? 0110 restart tx ? restart tx restart tx ?? ??? 0111 ? ? c lose rx bd c lose rx bd ?c lose rx bd c lose rx bd ?? table 21-9. cp command register field descriptions (continued) bits name description 4 datasheet u .com
communications processor module overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 21-27 note if a reserved command is issued, the cpm enters an unknown state that requires an external reset to recover. the commands in table 21-10 are described in table 21-11 . 1000 set group address ? set group address ??? ? set timer ? 1001 ? ? ? ? gci timeout ???? 1010 atm transmit command 1 usb stop tx endpoint reset bcs ? gci abort request ???? 1011 ? usb restart tx endpoint ? ??? ??? 1100 ? ? ? ? ? ? ? ? random number 11 xx undefined. reserved for use by freescale-supplied ram microcodes. 1 see sbc for fcc1 and fcc2, ta bl e 2 1 - 9 . table 21-11. command descriptions command description init tx and rx params initialize transmit and receive parameters. initializes the transmit and receive parameters in the parameter ram to the values that they had af ter the last reset of the cp. this command is especially useful when switching protocols on a given peripheral controller. init rx params initialize receive parameters. initializes the receive parameters of the peripheral controller. init tx params initialize transmit parameters. initializes the tr ansmit parameters of the peripheral controller. enter hunt mode enter hunt mode. causes the receiver to stop receiv ing and begin looking for a new frame. the exact operation of this command may vary depending on the protocol used. stop tx stop transmission. aborts the transmission from th is channel as soon as the transmit fifo has been emptied. it should be used in cases where transmission needs to be stopped as quickly as possible. transmission proceeds when the restart command is issued. graceful stop tx graceful stop transmission. stops the transmission fr om this channel as soon as the current frame has been fully transmitted from the transmit fifo. tr ansmission proceeds when the restart command is issued and the r-bit is set in the next txbd. restart tx restart transmission. once the stop tx command has been issued, this command is used to restart transmission at the current bd. table 21-10. cp command opcodes (continued) opcode channel fcc usb scc smc (uart/ transparent) smc (gci) spi i 2 c timer special 4 datasheet u .com
communications processor module overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 21-28 freescale semiconductor note the cpm accesses bds by initiating a dm a cycle on either the system or local bus. if bds are located in dpram, the cpm initiates a cycle on the system bus because dpram is a slave device on the system bus. therefore, a system design should not plan to acc ess the system bus simultaneously with dpram bd fetches. 21.3.2 command register example to perform a complete reset of the cp, the value 0x8001_0000 should be written to the cpcr. following this command, the cpcr returns th e value 0x0000_0000 after two clocks. 21.3.3 command execution latency the worst-case command execution latency is 200 cloc ks and the typical command execution latency is about 40 clocks. 21.4 internal ram the cpm has 20 kbytes of static ram. this ram is split into two blocks. ? 4 kbytes of instruction ram to store a microcode package of up to 1k instructions ? 16 kbytes of dual-port data ram to store cpm-risc pa rameter ram and data structures usb stop tx endpoint see section 35.7, ?usb cp commands.? usb restart tx endpoint see section 35.7, ?usb cp commands.? close rxbd close rxbd. causes the receiver to close the current rxbd, making the receive buffer immediately available for manipulation by the user. reception continues using the next available bd. can be used to access the buffer without waiting until the buffer is completely filled by the scc. set timer set timer. activates, deactivates, or reconfigures one of the 16 timers in the risc timer table. set group address set group address. sets a bit in the hash table for the ethernet logical group address recognition function. gci abort request gci abort request. the gci receiver sends an abort request on the e bit. gci timeout gci time-out. the gci performs the timeout function. reset bcs reset block check sequence. used in bisync mode to reset the block check sequence calculation. atm transmit see section 41.14, ?atm transmit command.? random number generate a random number and put it in dual-port ram; see rand in table 21-13. table 21-11. command descriptions (continued) command description 4 datasheet u .com
communications processor module overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 21-29 figure 21-10 is a block diagram of the internal ram. figure 21-10. internal ram block diagram the internal instruction ram ca n be accessed by the following: ? cp instruction fetcher (in case of microcode from ram) ? other masters connected through the ecm (including the processor core) the internal dual-port data ram can be accessed by the following: ? cp load/store unit ? cp block transfer module (btm) ? other masters connected through the ecm (including the processor core) ? sdma system bus ? sdma local bus figure 21-11 shows the memory map of the internal instruction ram. figure 21-11. internal instruction ram memory map slave address risc instruction address instruction ram (microcode) slave data risc instruction 4 kbytes slave address risc data address dual-port data ram (bds, buffers) dma (system) address dma (local) address btm address slave data risc data dma (system) data dma (local) data btm data 16 kbytes cpm instruction 2 kbytes bank #1 0xa_0000 cpm instruction 2 kbytes bank #2 0xa_0800 0xa_1000 4 datasheet u .com
communications processor module overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 21-30 freescale semiconductor figure 21-12 shows a memory map of the internal dual-port data ram. figure 21-12. internal dual-port data ram memory map the dual-port data ram data bus is 64 bits wide. the ram is us ed for the following tasks: ? to store parameters associated with the fccs, sccs, smcs, spi, and i 2 c in the parameter ram ? to store buffer descriptors (bds) ? to hold data buffers (optiona l because data can also be stored in external memory) ? to temporarily store fcc data moving to/from an fcc fifo (usi ng the btm) from/to external memory (using sdma) ? as an additional scratch-pad ram space for user software the dual-port data ram is designed to serve multiple re quests at the same cycle, as long as they are not in the same bank. only the parameters in the parameter ram and the microcode ram option requir e fixed addresses to be used. the bds, buffer data, and scratchpad ram can be located in the internal system ram or in any bd/data 2 kbytes bank #1 0x0000 bd/data 2 kbytes bank #2 0x0800 bd/data 2 kbytes bank #3 0x1000 bd/data 2 kbytes bank #4 0x1800 0x4000 reserved reserved parameter ram 2 kbytes bank #5 0x8000 parameter ram 2 kbytes bank #6 0x8800 bd/data 2 kbytes bank #7 0x9000 bd/data 2 kbytes bank #8 0x9800 reserved 0x2000 0xa000 4 datasheet u .com
communications processor module overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 21-31 unused parameter ram, for ex ample, in the area made av ailable when a peripheral controller or sub-block is not being used. microcode can be executed from the instru ction ram (separate from the data ram). 21.4.1 buffer descriptors (bds) the peripheral controllers (f ccs, sccs, smcs, spi, and i 2 c) always use bds for controlling buffers and their bd formats, shown in table 21-12 , are all the same. 21.4.2 parameter ram the cpm maintains a section of ra m called the parameter ram, whic h contains many parameters for the operation of the fccs, sccs, smcs, spi, and i 2 c channels. an overview of the parameter ram structure is shown in table 21-13 . the exact definition of the parameter ram is contai ned in each protocol s ubsection describing a device that uses a parameter ram. for example, the ethern et parameter ram is defined differently in some locations from the hdlc -specific parameter ram. table 21-12. buffer descriptor format address descriptor offset + 0 status and control offset + 2 data length offset + 4 high-order buffer pointer offset + 6 low-order buffer pointer table 21-13. parameter ram page address 1 peripheral size (bytes) 1 0x8000 scc1 256 2 0x8100 reserved 256 3 0x8200 scc3 256 4 0x8300 scc4 256 5 0x8400 fcc1 256 6 0x8500 fcc2 256 7 0x8600 reserved 256 4 datasheet u .com
communications processor module overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 21-32 freescale semiconductor 21.5 risc timer tables the cp can control up to 16 software timers that ar e separate from the 4 gene ral-purpose timers and the brgs in the cpm. these timers are best used in pr otocols that do not require extreme precision, but in which it is preferable to free the core from scanning the software?s tim er tables. these t imers are clocked from an internal timer that only the cp uses. the follow ing is a list of the importa nt features of the risc timer tables. ? up to 16 timers supported ? two timer modes: one-shot and restart ? maskable interrupt on timer expiration ? programmable timer resolution as fine as 3.85 s at 266 mhz (3.09 s at 333 mhz) 8 0x8700 reserved 128 0x8780 reserved 124 0x87fc smc1_base 2 0x87fe reserved 2 9 0x8800 reserved 128 0x8880 reserved 124 0x88fc smc2_base 2 0x88fe reserved 2 10 0x8900 reserved 252 0x89fc spi_base 2 0x89fe reserved 2 11 0x8a00 reserved 224 0x8ae0 risc timers 16 0x8af0 rev_num 2 2 0x8af2 reserved 2 0x8af4 reserved 4 0x8af8 rand 4 0x8afc i 2 c_base 2 0x8afe reserved 2 12 0x8b00 usb 256 13-16 0x8c00 reserved 1024 1 offset from ram_base. 2 refer to ta b l e 2 1 - 8 . table 21-13. parameter ram (continued) page address 1 peripheral size (bytes) 4 datasheet u .com
communications processor module overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 21-33 ? maximum timeout period of 15.9 seconds at 266 mhz (12.8 s econds at 333 mhz) ? continuously updated reference counter all operations on the risc ti mer tables are based on a f undamental tick of the cp?s internal timer that is programmed in the rccr. the tick is a mu ltiple of 1024 general system clocks; see section 21.2.6, ?risc controller configurat ion register (rccr).? the risc timer tables have the lowest priority of all cp operations. ther efore, if the cp is so busy with other tasks that it does not have time to service the timer during a tick in terval, one or more timers may not be updated accurately. this behavior can be used to estimate the worst-case loading of the cp; see section 21.5.10, ?using the risc timers to track cp loading.? the timer table is configured using the rccr, the ti mer table parameter ram, and the risc controller timer event/mask registers (rter/rtmr), and by issuing set timer to the cpcr. 21.5.1 risc timer table parameter ram two areas of dual-port ram, shown in figure 21-13 , are used for the risc timer tables: ? the risc timer table parameter ram ? the risc timer table entries figure 21-13. risc timer table ram usage the risc timer table parameter ram area begins at the risc timer base address and is used for the general timer parameters; see table 21-14 . table 21-14. risc timer table parameter ram offset 1 name description 0x00 tm_base risc timer table base addres s. the actual timers are a small bloc k of memory in the dual-port ram. tm_base is the offset from the beg inning of the dual-port ram where that block resides. four bytes must be reserved at the tm_base fo r each timer used (64 bytes if all 16 timers are used). if fewer than 16 timers are used, timers should be allocated in ascending order to save space. for example, only 8 bytes are required if two timers are needed and risc timers 0 and 1 are enabled. tm_base should be word-aligned. tm_base 16 risc timer table entries (up to 64 bytes) risc timer table parameter ram 0x8ae0 timer table base pointer 4 datasheet u .com
communications processor module overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 21-34 freescale semiconductor 21.5.2 risc timer command register (tm_cmd) figure 21-14 shows the risc timer command register (tm_cmd). tm_cmd fields are described in table 21-15 . 0x02 tm_ptr risc timer table pointer. this value is used excl usively by the cp to point to the next timer accessed in the timer table. it should not be modified by the user. 0x04 r_tmr risc timer mode register. this value is used exclusively by the cp to store the mode of the timer?one-shot (bit is 0) or restart (bit is 1). r_tmr should not be modified by the user. the set timer command should be used instead. 0x06 r_tmv risc timer valid register. used exclusively by the cp to determine if a timer is currently enabled. if the corresponding timer is enabled, a bit is 1. r_tmv should not be modified by the user. the set timer command should be used instead. 0x08 tm_cmd risc timer command register. used as a parameter location when the set timer command is issued. the user should write this location before issuing the set timer command. this register is defined in section 21.5.2, ?risc timer command register (tm_cmd).? 0x0c tm_cnt risc timer internal count. a tick counter th at the cp updates after each tick. the update occurs after the cp complete scanning the timer table.all 16 timers are scanned every tick interval regardless of whether any of them is enabled.it is updated if the cp?s internal timer is enabled, regardless of whether any of the 16 timers are enabled and it can be used to track the number of ticks the cp receives and responds to.tm_cnt is updated only after the last ti mer (timer 15) has been serviced. if the cp is so busy with other tasks that it does not have time to service all the timers during a tick interval, and timer 15 has not been serviced, then tm_cnt would not be updated in that tick interval. 1 offset from timer base address (0x8ae0). 0123456789101112131415 field v r ? tn 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field timer period (tp) figure 21-14. risc timer command register (tm_cmd) table 21-15. tm_cmd field descriptions bits name description 0 v valid. this bit should be set to enable the timer and cleared to disable it. 1 r restart. should be set for an automatic restart or cleared for a one-shot operation of the timer. 2?11 ? reserved. these bits s hould be written with zeros. 12?15 tn timer number. a value from 0?15 signifying which timer to use?an offset into the timer table entries. 16?31 tp timer period. the 16-bit timeout value of the timer is zero-based. the minimum value is 1 and is programmed by writing 0x0000 to the timer period.the maximum value of the timer is 65,536 and is programmed by writing 0xffff. table 21-14. risc timer tabl e parameter ram (continued) 4 datasheet u .com
communications processor module overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 21-35 21.5.3 risc timer table entries the 16 timers are located in the bl ock of memory following the tm_bas e location; each timer occupies 4 bytes. the first half word forms the initial valu e of the timer written during the execution of the set timer command and the next half word is the current valu e of the timer that is de cremented until it reaches zero. these locations should not be modified by the user. they are documented only as a debugging aid for user code. use the set timer command to initialize table values. 21.5.4 risc timer event register (rter)/mask register (rtmr) the rter register is used to repo rt events recognized by th e 16 timers and to gene rate interrupts. rter can be read at any time. bits ar e cleared by writing ones; writing zeros does not affect bit values. the risc timer mask register (rtmr) is used to en able interrupts that can be generated in the rter. setting an rtmr bit enables the corresponding in terrupt in the rter; cl earing a bit masks the corresponding interrupt. an interrupt is generated only if th e risc timer table bi t is set in the cpm interrupt mask register. see section 22.5.1.4, ?cpm interrupt mask registers (simr_h, simr_l).? 21.5.5 set timer command the set timer command is used to enable, disable, and c onfigure the 16 timers in the risc timer table and is issued to the cpcr. this means the value 0x29e1_0008 should be written to cpcr. however, before writing this value, the user should program the tm_cmd fields. see section 21.5.2, ?risc timer command register (tm_cmd).? 21.5.6 risc timer initialization sequence the following sequence init ializes the risc timers: 1. configure rccr to determine the preferred tick interval for the en tire timer table. the time bit is normally set at this time but can be set late r if all risc timers need to be synchronized. 2. determine the maximum number of timers to be located in the timer table. configure the tm_base in the risc timer table parameter ra m to point to a location in the dual-port ram with 4 n bytes available, where n is the number of ti mers. if n is less th an 16, use timer 0 through timer n?1 to save space. 3. clear the tm_cnt field in the risc timer table parameter ram to show how many ticks elapsed since the risc internal timer was enabled. this step is optional. 0 1 2 3456789101112131415 field tmr 15 tmr 14 tmr 13 tmr 12 tmr 11 tmr 10 tmr 9 tmr 8 tmr 7 tmr 6 tmr 5 tmr 4 tmr 3 tmr 2 tmr 1 tmr 0 reset 0000_0000_0000_0000 r/w r/w offset 0x9_19d6 (rter)/0x9_19da (rtmr) figure 21-15. risc timer event register (rter)/mask register (rtmr) 4 datasheet u .com
communications processor module overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 21-36 freescale semiconductor 4. clear rter, if it is not already clear ed. write ones to clear this register. 5. configure rtmr to enable the timers that shou ld generate interrupts. ones enable interrupts. 6. set the risc timer table bit in the cpm interr upt mask register (simr_l[rtt]) to generate interrupts to the system. the cpm interrupt c ontroller may require other initialization not mentioned here. 7. configure the tm_cmd field of the risc timer table parameter ram. at this point, determine whether a timer is to be enabled or disabled, one-shot or restart, and what its timeout period should be. if the timer is being disabled, the paramete rs (other than the timer number) are ignored. 8. issue the set timer command by writing 0x29e1_0008 to the cpcr. 9. repeat the preceding two steps for ea ch timer to be enabled or disabled. 21.5.7 risc timer initialization example the following sequence initia lizes risc timer 0 to generate an in terrupt approximately every second using a 133-mhz genera l system clock: 1. write 111111 to rccr[timep] to generate the slowest clock. this value generates a tick every 65,536 clocks, which is every 485 s at 133 mhz. 2. configure the tm_base in the risc timer tabl e parameter ram to point to a location in the dual-port ram with 4 bytes available. assuming the beginning of dual-port ram is available, write 0x0000 to tm_base. 3. (optional) write 0x0000 to the tm _cnt field in the risc timer table parameter ram to see how many ticks elapsed since the risc internal timer was enabled. 4. write 0xffff to the rter to clear any previous events. 5. write 0x0001 to the rtmr to enable risc timer 0 to generate an interrupt. 6. write 0x0002_0000 to the cpm interrupt mask regist er (simr_l) to allow the risc timers to generate a system interrupt. initialize th e cpm interrupt configuration register. 7. write 0xc000_080d to the tm_cmd field of the ri sc timer table parameter ram. this enables risc timer 0 to timeout after 2,061(decimal) ticks of the timer. the timer automatically restarts after it times out. 8. write 0x29e1_0008 to the cpcr to issue the set timer command. 9. set rccr[time] to enable the risc timer to begin operation. 21.5.8 risc timer interrupt handling the following sequence describes what normally would occur within an interrupt handler for the risc timer tables: 1. once an interrupt occurs, read rter to see which timers have caused interrupts. the risc timer event bits are usually cleared by this time. 2. issue additional set timer commands at this time or later, as preferred. nothing needs to be done if the timer is being automatically restarted for a repetitive interrupt. 4 datasheet u .com
communications processor module overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 21-37 3. clear the rtt bit in the cpm interrupt pending register (sipnr_l). 4. execute the rte instruction. 21.5.9 risc timer table scan algorithm the cp scans the timer table once every tick. it handles each of the 16 timers at its turn and checks for other requests with higher priority to service before ha ndling the next one. for each valid timer in the table, the cp decrements the count and chec ks for a timeout. if none occurs, the cp moves to the next timer. if a timeout occurs, the cp se ts the corresponding event bit in rter. then the cp ch ecks to see if the timer is to be restarted and if it is, the cp leaves the ti mer?s valid bit set in the r_tmv location and resets the current count to the initial count . otherwise, it clear s r_tmv. once the timer table scanning has completed, the cp updates the tm_cnt value in the risc timer table paramete r ram and stops working on the timer tables until the next tick. if a set timer command is issued, the cp makes the appropr iate modifications to the timer table and parameter ram, but does not scan the ti mer table until the next tick of th e internal timer. it is important to use the set timer command to properly synchronize timer tabl e modifications to the execution of the cp. 21.5.10 using the risc timers to track cp loading the risc timers can be used to track cp loadi ng. the following sequence provides a way to use the 16 risc timers to determine if the cp ever exceeds the 96% utilization level during any tick interval. removing the timers adds a 4% margin to the cp utilization level, but the aggressive user can use this technique to push cp performance to its limit. the user s hould use the standard in itialization sequence and incorporate the following differences: 1. program the tick of the ri sc timers to be every 1024 16 = 16,384 system clocks. 2. disable risc timer inte rrupts, if preferred. 3. using the set timer command, initialize all 16 risc timers to have a timer period of 0xffff, which is equal to 65,536. 4. program one of the four genera l-purpose timers to increment onc e every tick. the general-purpose timer should be free-running and should have a timeout of 65,536. 5. after a few hours of operation, compare the gene ral-purpose timer to the current count of risc timer 15. if it is more than two ticks different from the general-purpose timer, the cp has, during some tick interval, exceeded the 96% utilization level. note general-purpose timers are up counters, but risc timers are down counters. the user should take this into consid eration when comparing timer counts. 4 datasheet u .com
communications processor module overview MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 21-38 freescale semiconductor 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 22-1 chapter 22 cpm interrupt controller key features of the cpm interrupt controller include the following: ? communications processor module (cpm) interr upt sources (fccs, sc cs, smcs, timers, i 2 c, sdma, usb, and spi) ? 16 external interrupt pins (port c) ? programmable priority between sccs and fccs ? two priority schemes for the sccs: grouped, spread ? programmable highest priority request ? unique vector number for each interrupt source 22.1 interrupt configuration figure 22-1 shows the MPC8555E interrupt structure. the interrupt controller receives interrupts from internal sources from the cpm and from external pins (port c parall el i/o pins). the cpm interrupt controller combines all of these in terrupt inputs into a single interrupt signal to the programmable interrupt controller (pic), which treats it as an internal interrupt. 4 datasheet u .com
cpm interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 22-2 freescale semiconductor figure 22-1. MPC8555E cpm interrupt structure the cpm interrupt controller allows masking of eac h interrupt source. multiple events within a cpm sub-block event are also maskable. all interrupt sources are prioritized and bits are set in the interrupt pending register (sipnr). on the MPC8555E, the prioritization of the interrupt sour ces is flexible in th e following two aspects: ? the relative priority of the fccs and sccs can be modified. ? one interrupt source can be assigned the highest priority. when an unmasked interrupt source is pending in the sipnr, the interrupt cont roller sends an interrupt request to the pic. the cpm interrupt vector register (sivec) is updated with a 6-bi t vector corresponding to the requesting sub-block with the highest current priority. 22.2 cpm interrupt source priorities the cpm interrupt controller has 34 interrupt sources that assert one interrupt request to the pic. table 22-1 shows the prioritization of the interrupt sour ces. as described in the following sections, flexibility exists in the relative ordering of the interr upts, but, in general, relati ve priorities are as shown. a single interrupt priority number is associated with each table entry. int pic port c[0:1, 4:15, 23, 29] timer1 timer2 timer3 timer4 smc1 smc2 reserved spi i 2 c reserved cpm interrupt controller reserved reserved risc timers scc4 scc1 fcc2 fcc1 edge/ fall e500 core interface system bus sdma local bus sdma scc3 16 usb 4 datasheet u .com
cpm interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 22-3 note that the group and spread opt ions, shown with ycc entries in table 22-1 , are described in section 22.2.1, ?scc and fcc relative priority.? table 22-1. interrupt source priority levels priority level interrupt source description multiple events 1 highest ? 2 xcc1 yes 3 xcc2 yes 4 xcc3 yes 5 xcc4 yes 6 xcc5 yes 7 xcc6 yes 8 xcc7 yes 9 xcc8 yes 10 ycc1 (grouped) yes 11 ycc2 (grouped) yes 12 ycc3 (grouped) yes 13 ycc4 (grouped) yes 14 ycc5 (grouped) yes 15 ycc6 (grouped) yes 16 ycc7 (grouped) yes 17 ycc8 (grouped) yes 18 parallel i/o?pc29 yes 19 timer 1 yes 20 parallel i/o?pc23 yes 21 ycc1 (spread) yes 22 parallel i/o?pc15 yes 23 sdma bus error yes 24 usb yes 25 ycc2 (spread) yes 26 parallel i/o?pc14 no 27 parallel i/o?pc13 no 28 reserved ? 29 timer 2 yes 30 parallel i/o?pc12 no 31 ycc3 (spread) yes 4 datasheet u .com
cpm interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 22-4 freescale semiconductor notice the lack of sdma interrupt sources, which are re ported through each indivi dual fcc, scc, smc, spi, or i 2 c channel. the only true sdma in terrupt source is the sdma ch annel bus error entry that is reported when a bus error occurs during an sdma access. there are two ways to a dd flexibility to the table of cpm interrupt priorities?t he fcc and scc relative pr iority option, described in section 22.2.1, ?scc and fcc relative priority,? and the highest prior ity option, described in section 22.2.2, ?highest priority interrupt.? 32 risc timer table yes 33 i 2 cyes 34 ycc4 (spread) yes 35 parallel i/o?pc11 no 36 parallel i/o?pc10 no 37 reserved ? 38 timer 3 yes 39 ycc5 (spread) yes 40 parallel i/o?pc9 no 41 parallel i/o?pc8 no 42 parallel i/o?pc7 no 43 timer 4 yes 44 ycc6 (spread) yes 45 parallel i/o?pc6 no 46 reserved ? 47 spi yes 48 parallel i/o?pc5 no 49 parallel i/o?pc4 no 50 smc1 yes 51 ycc7 (spread) yes 52 smc2 yes 53 parallel i/o?pc1 no 54 parallel i/o?pc0 no 55 ycc8 (spread) yes 56 reserved ? table 22-1. interrupt source priority levels (continued) priority level interrupt source description multiple events 4 datasheet u .com
cpm interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 22-5 22.2.1 scc and fcc relative priority the relative priority between the three sccs a nd two fccs is programmable and can be changed dynamically. in table 22-1 there is no entry for scc1?scc4, fcc 1?fcc2, but rather there are entries for xcc1?xcc8 and ycc1?ycc8. each scc can be ma pped to any ycc location and each fcc can be mapped to any xcc location. the scc and fcc prioritie s are programmed in the cpm interrupt priority registers (scprr_h and scprr_l) and can be cha nged dynamically to implement a rotating priority. in addition, grouping of ycc entr y locations can occur in one of the following two ways: ? group. in the group scheme, all sccs are grouped toge ther at the top of the priority table, ahead of most other cpm interrupt sour ces. this scheme is ideal for applications wher e all sccs and fccs function at a very high data rate and interrupt latency is very important. ? spread. in the spread sche me, priorities are spread over the table so ot her sources can have lower interrupt latencies. this scheme is also programmed in the sicr but cannot be changed dynamically. 22.2.2 highest priority interrupt in addition to the fcc/scc relative priority option, sicr[hp] can be used to specify one interrupt source as having highest priority. this interrupt remains wi thin the same interrupt level as the other interrupt controller interrupts, but is serviced be fore any other interrupt in the table. if the highest priority feature is not used, select the interrupt request with the highest priority. sicr[hp] can be updated dynamically to allow the user to cha nge a normally low priority source into a high priority-source for a certain period. 22.3 masking interrupt sources by programming the cpm interrupt mask registers, simr_h and simr _l, the user can mask interrupt requests to the core. each simr bit corresponds to an interrupt source. to enable an interrupt, set the corresponding simr bit. when a masked interrupt source has a pending interrupt request, the corresponding sipnr bit is se t, even though the interrupt is not gene rated to the core. the user can mask all interrupt sources to implement a polling interrupt servicing scheme. when an interrupt source has multip le interrupting events, the user ca n individually mask these events by programming a mask register within that block. table 22-1 shows which interrupt sources have multiple interrupting events. figure 22-2 shows an example of how the mask ing occurs, using an scc as an example. 4 datasheet u .com
cpm interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 22-6 freescale semiconductor figure 22-2. interrupt request masking 22.4 cpm interrupt vector generation and calculation pending unmasked interrupts are presented to the core in order of prio rity. the interrupt vector that allows the core to locate the interrupt service routine is made available to the core by reading sivec. the interrupt controller passes an in terrupt vector corresponding to the highest-priority, unmasked, pending interrupt. table 22-2 lists encodings for the 6 low-orde r bits of the interrupt vector. table 22-2. encoding the interrupt vector interrupt number interrupt source description interrupt vector 0 error (no interrupt) 0b00_0000 1i 2 c 0b00_0001 2 spi 0b00_0010 3 risc timers 0b00_0011 4 smc1 0b00_0100 5 smc2 0b00_0101 6 reserved 0b00_0110 scce sccm 13 input (or sipnr mask bit simr request to the pic mask bit event bit 13 event bits) cpm interrupt controller 4 datasheet u .com
cpm interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 22-7 7 reserved 0b00_0111 8 reserved 0b00_1000 9 reserved 0b00_1001 10 reserved 0b00_1010 11 usb 0b00_1011 12 timer1 0b00_1100 13 timer2 0b00_1101 14 timer3 0b00_1110 15 timer4 0b00_1111 16?31 reserved 0b01_0000?01_1111 32 fcc1 0b10_0000 33 fcc2 0b10_0001 34 reserved 0b10_0010 35 reserved 0b10_0011 36 reserved 0b10_0100 37 reserved 0b10_0101 38 reserved 0b10_0110 39 reserved 0b10_0111 40 scc1 0b10_1000 41 reserved 0b10_1001 42 scc3 0b10_1010 43 scc4 0b10_1011 44 reserved 0b10_1100 45 core interface 0b10_1101 46 sdma system 0b10_1110 47 sdma local 0b10_1111 48 pc29 0b11_0000 49 pc23 0b11_0001 50 pc15 0b11_0010 51 pc14 0b11_0011 52 pc13 0b11_0100 table 22-2. encoding the interrupt vector (continued) interrupt number interrupt source description interrupt vector 4 datasheet u .com
cpm interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 22-8 freescale semiconductor note that the interrupt vector table differs from the interrupt priority table in only two ways: ? fcc and scc vectors are fixed; they are not affected by the scc group mode, spread mode, or the relative priority order of the fccs and sccs. ? an error vector exists as the last entry in table 22-2 . the error vector is issued when no interrupt is requesting service. 22.4.1 port c external interrupts there are 16 external interrupts, co ming from the parallel i/o port c pins, pc[0:1, 4:15, 23, 29]. when one of these pins is configured as an input, a change according to the cpm external interrupt control register (siexr) causes an interrupt request si gnal to be sent to the interrupt controller. pc[0: 1, 4:15, 23, 29] lines can be programmed to assert an interrupt request upon any change. ea ch port c line asserts a unique interrupt request to the interrupt pending register and ha s a different internal interr upt priority level within the interrupt controller. requests can be masked independently in the interrupt mask register (s imr). notice that the global simr is cleared on system reset so pins le ft floating do not cau se false interrupts. 22.5 cpm interrupt programming model the interrupt controller registers c ontrol configuration, prioritization, and masking of interrupts. they also include registers for determining the interrupt sources. these registers are described in section 22.5.1, ?interrupt controller registers.? 53 pc12 0b11_0101 54 pc11 0b11_0110 55 pc10 0b11_0111 56 pc9 0b11_1000 57 pc8 0b11_1001 58 pc7 0b11_1010 59 pc6 0b11_1011 60 pc5 0b11_1100 61 pc4 0b11_1101 62 pc1 0b11_1110 63 pc0 0b11_1111 table 22-2. encoding the interrupt vector (continued) interrupt number interrupt source description interrupt vector 4 datasheet u .com
cpm interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 22-9 22.5.1 interrupt controller registers there are seven interrupt controller regist ers, described in the following sections: ? section 22.5.1.1, ?cpm interrupt conf iguration register (sicr)? ? section 22.5.1.2, ?cpm interrupt priority registers (scprr_h, scprr_l)? ? section 22.5.1.3, ?cpm interrupt pending registers (sipnr_h, sipnr_l)? ? section 22.5.1.4, ?cpm interrupt mask registers (simr_h, simr_l)? ? section 22.5.1.5, ?cpm interrupt vector register (sivec)? ? section 22.5.1.6, ?cpm external interr upt control register (siexr)? 22.5.1.1 cpm interrupt configuration register (sicr) the cpm interrupt configurati on register (sicr), shown in figure 22-3 , defines the highest priority interrupt and whether interrupts are groupe d or spread in the priority table, table 22-1 . the sicr register b its are described in table 22-3 . 012 78 1415 field ? hp ? sps reset 0000_0000_0000_0000 r/w r/w offset 0x9_0c00 figure 22-3. cpm interrupt configuration register (sicr) table 22-3. sicr field descriptions bits name description 0?1 ? reserved, should be cleared. 2?7 hp highest priority. specifies the 6-bit in terrupt number of the single interrupt controller interrupt source that is advanced to the highest priority in the table. hp can be modified dynamically. to retain the original priority, program hp to the interrupt number assigned to the interrupt request with the highest priority. 8?14 ? reserved, should be cleared. 15 sps spread priority scheme. selects the relative ycc priority scheme. it cannot be changed dynamically. 0 grouped. the yccs are grouped by pr iority at the top of the table. 1 spread. the yccs are spread by priority in the table. 4 datasheet u .com
cpm interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 22-10 freescale semiconductor 22.5.1.2 cpm interrupt priority registers (scprr_h, scprr_l) the cpm high interrupt priority register (scprr_h), shown in figure 22-4 , defines priorities between the fccs. table 22-4 describes scprr_h fields. the cpm low interrupt priority register (scprr_l), shown in figure 22-5 , defines the prioritization of the sccs. 02356891112 15 field xc1p xc2p xc3p xc4p ? reset 000 001 010 011 000 r/w r/w offset 0x9_0c14 16 18 19 21 22 24 25 27 28 31 field xc5p xc6p xc7p xc8p ? reset 100 101 110 111 000 r/w r/w offset 0x9_0c16 figure 22-4. cpm high interrupt priority register (scprr_h) table 22-4. scprr_h field descriptions bits name description 0?2 xc1p priority order. defines which fcc asserts its request in the xcc1 priority position. the user should not program the same fcc to more than one prio rity position (1?8). these bits can be changed dynamically. 000 fcc1 asserts its request in the xcc1 position. 001 fcc2 asserts its request in the xcc1 position. 010 reserved 011 xcc1 position not active 100 reserved 101 reserved 110 xcc1 position not active 111 xcc1 position not active 3?11, 16?27 xc2p?xc8p same as xc1p, but for xcc2?xcc8 13?15, 28?31 ? reserved, should be cleared. 4 datasheet u .com
cpm interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 22-11 table 22-5 describes scprr_l fields. 22.5.1.3 cpm interrupt pending re gisters (sipnr_h, sipnr_l) each bit in the cpm interrupt pending regi sters (sipnr_h and sipnr_l), shown in figure 22-6 and figure 22-7 , corresponds to an interrupt source. when an inte rrupt is received, the in terrupt controller sets the corresponding sipnr bit. 02356891112 15 field yc1p yc2p yc3p yc4p ? reset 000 001 010 011 0000 r/w r/w offset 0x9_0c18 16 18 19 21 22 24 25 27 28 31 field yc5p yc6p yc7p yc8p ? reset 100 101 110 111 0000 r/w r/w offset 0x9_0c20 figure 22-5. cpm low interrupt priority register (scprr_l) table 22-5. scprr_l field descriptions bits name description 0?2 yc1p priority order. defines which scc asserts its reques t in the ycc1 priority po sition. do not program the same scc to multiple priority positions. this field can be changed dynamically. 000 scc1 asserts its request in the ycc1 position. 001 reserved 010 scc3 asserts its request in the ycc1 position. 011 scc4 asserts its request in the ycc1 position. 100 reserved 101 core interface asserts its request in the ycc1 position 110 system sdma asserts its re quest in the ycc1 position 111 local sdma asserts its request in the ycc1 position 3?11, 16?27 yc2p?yc8p same as yc1p, but for ycc2?ycc8 12?15, 28?31 ? reserved, should be cleared. 4 datasheet u .com
cpm interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 22-12 freescale semiconductor figure 22-7 shows sipnr_l fields. when a pending interrupt is handled, the user clear s the corresponding sipnr bit. however, if an event register exists, the unmasked event register bits s hould be cleared instead, caus ing the sipnr bit to be cleared. sipnr bits are cleared by writing ones to them. because the user can only cl ear bits in this register, writing zeros to this register has no effect. note that the scc/fcc sipnr bit positions are not changed accord ing to their relative priority. 22.5.1.4 cpm interrupt mask registers (simr_h, simr_l) each bit in the cpm interrupt mask register (simr) corresponds to a in terrupt source. th e user masks an interrupt by clearing and enables an interrupt by se tting the corresponding simr bit. when a masked 0123456789101112131415 field pc0 pc1 pc4 pc5 pc6 pc7 pc8 pc9 pc10 pc11 pc12 pc13 pc14 pc15 pc23 pc29 reset undefined (the user should write 1s to clear these bits before using.) r/w r/w offset 0x9_0c08 16 31 field ? reset undefined (the user should write 1s to clear these bits before using.) r/w r/w offset 0x9_0c10 figure 22-6. sipnr_h fields 0 1 2 7 8 9 10 11 12 13 14 15 field fcc1 fcc2 ? scc1 ? scc3 scc4 ? core i/f sdma sys sdma lcl reset 0000_0000_0000_0000 1 r/w r/w offset 0x9_0c0c 16 17 18 19 20 21 25 26 27 28 29 30 31 field i 2 c spi rtt smc1smc2 ? usb tim er1timer2timer3timer4 ? reset 0000_0000_0000_0000 1 r/w r/w offset 0x9_0c0e 1 these fields are zero after reset because their corr esponding mask register bits are cleared (disabled). figure 22-7. sipnr_l fields 4 datasheet u .com
cpm interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 22-13 interrupt occurs, the corresponding sipnr bit is set, regardless of the simr bit although no interrupt request is passed to the core. if an interrupt source reque sts interrupt service when th e user clears its simr bit, the request stops. if the user sets the simr bit later, a pr eviously pending interrupt request is processed by the core, according to its assigned priority. the simr can be read by the user at any time. figure 22-8 shows the simr_h register. figure 22-9 shows simr_l. note the following: ? scc/fcc simr bit positions are not af fected by their relative priority. ? the user can clear pending regist er bits that were set by multipl e interrupt events only by clearing all unmasked events in the corresponding event register. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field pc0 pc1 pc4 pc5 pc6 pc7 pc8 pc9 pc10 pc11 pc12 pc13 pc14 pc15 pc23 pc29 reset 0000_0000_0000_0000 r/w r/w offset 0x9_0c1c 16 31 field ? reset 0000_0000_0000_0000 r/w r/w offset 0x9_0c1e figure 22-8. simr_h register 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field fcc1 fcc2 ? scc1 ? scc3 scc4 ? core i/f sdma sys sdma lcl reset 0000_0000_0000_0000 r/w r/w offset 0x9_0c20 16 17 18 19 20 21 25 26 27 28 29 30 31 field i 2 c spi rtt smc1 smc2 ? usb timer1timer2timer3timer4 ? reset 0000_0000_0000_0000 r/w r/w offset 0x9_0c22 figure 22-9. simr_l register 4 datasheet u .com
cpm interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 22-14 freescale semiconductor ? if an simr bit is masked at the same time that the corresponding sipnr bit causes an interrupt request to the core, the error vect or is issued (if no other interrupt s pending). thus, the user should always include an error vector rout ine, even if it contains only an rfi instruction. the error vector cannot be masked. 22.5.1.5 cpm interrupt ve ctor register (sivec) the cpm interrupt vector register (sivec), shown in figure 22-10 , contains an 8-bit code representing the unmasked interrupt source of the highest priority level. the sivec can be read as either a byte, half word, or word. when read as a byte, a branch table can be used in which each entry contains one instruction (b ranch). when read as a half word, each entry can contain a full routine of up to 256 instructions. the interrupt code is defined such that it s two lsbs are zeros, allowing indexing into the table, as shown in figure 22-11 . 0 56789101112131415 field interrupt code 0000000000 reset 0000_0000_0000_0000 r/w r offset 0x9_0c04 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field0000000000000000 reset 0000_0000_0000_0000 r/w r offset 0x9_0c06 figure 22-10. cpm interrupt vector register (sivec) 4 datasheet u .com
cpm interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 22-15 figure 22-11. interrupt table handling example 22.5.1.6 cpm external interrupt control register (siexr) each defined bit in the cpm external inte rrupt control register (siexr), shown in figure 22-12 , determines whether the corresponding port c line asse rts an interrupt request upon either a high-to-low change or any change on the pin. external interrupts can come from port c (pc[0:15]). base b routine1 b routine2 b routine3 b routine4 ? ? base + n base + 4 base + 8 base + c base +10 base 1st instruction of routine1 1st instruction of routine2 1st instruction of routine3 1st instruction of routine4 ? ? base + n base + 400 base + 800 base + c00 base +1000 ? ? ? ? ? ? intr: ? ? ? save state r3 <- @ sivec r4 <-- base of branch table ? ? ? lbz add mtspr bctr rx, r3 (0) # load as byte rx, rx, r4 ctr, rx intr: ? ? ? save state r3 <- @ sivec r4 <-- base of branch table ? ? ? lhz add mtspr bctr rx, r3 (0) # load as half word rx, rx, r4 ctr, rx 4 datasheet u .com
cpm interrupt controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 22-16 freescale semiconductor table 22-6 describes siexr fields. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field edpc 0 edpc 1 edpc 4 edpc 5 edpc 6 edpc 7 edpc 8 edpc 9 edpc 10 edpc 11 edpc 12 edpc 13 edpc 14 edpc 15 edpc 23 edpc 29 reset 0000_0000_0000_0000 r/w r/w offset 0x9_0c24 16 31 field ? reset 0000_0000_0000_0000 r/w r/w r offset 0x9_0c26 figure 22-12. cpm external interrupt control register (siexr) table 22-6. siexr field descriptions bits name description 0?15 edpcx edge detect mode for port cx. the corresponding port c line (pcx) asserts an interrupt request according to the following: 0 any change on pcx generates an interrupt request. 1 high-to-low change on pcx generates an interrupt request 16?31 ? reserved 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 23-1 chapter 23 serial interface with time-slot assigner 23.1 overview figure 23-1 shows a block diagram of the ti me-slot assigner (tsa). one serial interface (si) block in the MPC8555E (si2) can be programmed to handle three tdm lines concu rrently. the tdm channels on si2 are referred to as tdma2, tdmb2, and tdmc2. figure 23-1. si block diagram time-slot assigner (tsa) r clocks t clocks r clocks t clocks r sync t sync tdm a, b, c pins strobes route si ram tx/rx ram control mode register tdm a, b, c tx tx command register status register smc1 smc2 scc1 scc3 scc4 mii1 or mii2 or nonmultiplexed serial interface (nmsi) pins shadow register clock route address rx rx cpm mux note: the cpm mux is not part of the si. (see chapter 24, ?cpm multiplexing.? ) rmii2/ utopia8 to: smc1 smc2 scc1 scc3 scc4 fcc1 rmii1/ utopia8 fcc2 mux mux mux mux mux mux mux 4 datasheet u .com
serial interface with time-slot assigner MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 23-2 freescale semiconductor if the tsa is not used as intended, it can be used to generate complex wave forms on dedicated output pins. for instance, it can program these pins to implem ent stepper motor control or variable-duty cycle and period control on-the-fly. 23.2 features si has the following features: ? can connect to three indepe ndent tdm channels. each tdm can be one of the following: ? t1 or e1 line ? integrated services digital network primary rate (pri) ? an isdn basic rate?interchip digital link (idl) channel in up to three tdm channels?each idl channel requires suppor t from a separate scc ? isdn basic rate?general circuit interface (g ci) in up to two tdm channels?each gci channel requires support from a separate smc ? e3 or ds3 clear channel ? user-defined interfaces ? independent, programmable transm it and receive routing paths ? independent transmit and r eceive frame syncs allowed ? independent transmit and receive clocks allowed ? selection of rising/falling clock edge s for the frame sync and data bits ? supports 1 and 2 input clocks (1 or 2 clocks per data bit) ? selectable delay (0?3 bits) betw een frame sync and frame start ? four programmable strobe out puts and two clock output pins ? 1- or 8-bit resolution in routi ng, masking, and strobe selection ? supports frames up to 16,384 bits long ? internal routing and strobe sel ection can be dynamically programmed ? supports automatic echo and lo opback mode for each tdm ? maximum tdm frequency is serial-dependent: note this clock ratio is based on the hardwa re architecture and does not ensure that an application will r un at that speed. it is the responsibility of the system designer to check ac specifications of the i/o pins and determine the maximum frequency. ? for fccs transparent ? for all other serials cpm clock 3 ? for fccs hdlc cpm clock 4 4 datasheet u .com
serial interface with time-slot assigner MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 23-3 23.3 overview the tsa implements both internal route selection and time-division multiplexing (tdm) for multiplexed serial channels. the tsa supports th e serial bus rate and format for most standard tdm buses, including t1 and e1 highways, pulse-code modulation (pcm ) highway, and the isdn buses in both basic and primary rates. the two popular isdn basic rate buses (interchip digi tal link (idl) and general-circuit interface (gci), also know n as iom-2) are supported. because the si supports three tdms, it is possible to simultaneously suppo rt a combination of three t1 or e1 lines, and basic rate or primary rate isdn channels. the tdm channel can support e3 or ds-3 rates as a cl ear channel in a serial in terface (clock ratio 1/4). tsa programming is independe nt of the protocol used. the serial controllers can be programmed for any synchronous protocol without affe cting tsa programming. the tsa simp ly routes programmed portions of the received data frame from the tdm pins to the target controller, while the target controller handles the received data in the actual protocol. in its simplest mode, the tsa identifies the frame using one sync pulse and one clock signal provided externally by the user. this can be enhanced to allow independent routing of the receive and transmit data on the tdm. additionally, the definition of a time-slot need not be limited to 8 bits or even to a single contiguous position within the frame. finally, the user can provide separate rece ive and transmit syncs as well as clocks. figure 23-2 shows example tsa configurations ra nging from the simplest to the most complex. 4 datasheet u .com
serial interface with time-slot assigner MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 23-4 freescale semiconductor figure 23-2. various configurations of a single tdm channel tsa MPC8555E tdm tsa tsa tsa slot slot 3 3 slot slot n n tdm tdm tdm scc3 smc1 scc3 smc1 tdm tx tdm rx simplest tdm example slot 2 slot n 1 tdm sync 1 tdm clock smc1 scc3 smc1 tdm tx tdm rx slot 1 slot 3 scc3 more complex tdm example?unique routing scc3 smc1 scc3 scc3 smc1 scc3 tdm tx tdm rx even more complex tdm exampl e?multiple time slots per scc3 smc1 scc3 tdm tx scc3 tdm rx smc1 most complex tdm example ?totally independent rx and tx note: the two shaded areas off scc3 rx are receiv ed as one high-speed data stream by scc3 rx stored together in the same data buffers channel with varying sizes of time slots MPC8555E MPC8555E MPC8555E 1 tdm sync 1 tdm clock 1 tdm sync 1 tdm clock 1 tdm sync 1 tdm clock 1 tdm sync 1 tdm clock 4 datasheet u .com
serial interface with time-slot assigner MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 23-5 at its most flexible, the tsa can pr ovide three separate tdm channels, each with independent receive and transmit routing assignments and i ndependent sync pulse a nd clock inputs. thus, the tsa can support six, independent, half-duplex tdm sources, three in reception and three in tr ansmission, using six sync inputs and six clock inputs. figure 23-3 shows a dual-channel example. figure 23-3. dual tdm channel example in addition to channel programming, the tsa supports up to four strobe outputs that may be asserted on a bit or byte basis. these strobes are completely independent from the ch annel routing used by the sccs and smcs. the strobe outputs are useful for interfacing to other devices that do not support the multiplexed interface or for enabling/disabling three-state i/o buffers in a multiple-transmitter architecture. notice that open-drain programming on the txdx pins that supports a multiple-transmitter architecture occurs in the parallel i/o block. these strobes can also be used for generating output wave forms to support such applications as st epper-motor control. most tsa programming is done in the two 256 16-bit si2 rams. these si2 rams are directly accessible by the core in the internal register sec tion of the MPC8555E and are not associated with the dual-port ram. one si2 ram is always used to program the transmit rou ting; the other is always used to scc3 smc1 tdma rx tsa tdma tdmc tdma tx sync tdma tx clock scc4 smc1 scc4 tdma rx sync tdma rx clock tdma rx scc3 scc4 tdmc tx tdmc tx sync tdmc tx clock tdmc rx sync tdmc rx clock scc1 smc1 tdmc rx note: sccs can receive on one tdm and transmit on another (scc1 and scc3). 4 datasheet u .com
serial interface with time-slot assigner MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 23-6 freescale semiconductor program the receive routing. si 2 rams can be used to define the numbe r of bits/bytes to be routed to the fcc, scc, or smc and determine when extern al strobes are to be asserted and negated. the size of the si2 ram available for time-slot programming depends on the user?s configuration. the user defines how many of the 256 en tries are related to each tdm. th e resolution of the division is by fractions of 32. if on-the-fly change s are allowed, the si2 ram entries ar e reduced according to the user?s programming. the maximum frame length that can be supported in any configuration is 16,384 bits. the maximum external serial clock that ma y be an input to the tsa is cpm clk/3. the si supports two testi ng modes?echo and loopback. ? the echo mode provides a return signal from the physical interface by retransmitting the signal it has received. the physical interface echo mode differs from the i ndividual fcc or scc echo mode in that it can operate on the entire tdm signal ra ther than just on a particular serial channel. ? loopback mode causes the physical interface to re ceive the same signal it is sending. the si loopback mode checks more than the individual se rial loopback; it checks both the si and the internal channel routes. note the flexibility described in the preced ing section can be applied to each of the three tdm channels and to al l serial interfaces independently. 23.4 enabling connections to tsa each serial interface can be indepe ndently enabled to connect to one of the following: tsa, utopia, mii, or dedicated external pins. note the following: ? each fcc can be connected to a de dicated mii to or one of the thre e tdms, or to an 8-bit utopia level ii interface. ? each scc or smc can be connected to one of the three tdms or to its own set of pins. the three tdms are connected to three independent tdm interfaces. figure 23-4 illustrates the connection between the tsa and the serial interfa ces. the connection is ma de by programming the cpm mux. see chapter 24, ?cpm multiplexing.? after the connections are made , the exact routing decisions are made in the si2 ram. 4 datasheet u .com
serial interface with time-slot assigner MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 23-7 figure 23-4. enabling connections to the tsa 23.5 serial interface ram the si has a transmit ram and a recei ve ram, each with four banks of 64 half-word entries that enable it to control tdm channel routing to all serial devices. the si2 ra ms are uninitializ ed after power-on reset; unwanted results can occur if the user does not program them before enabling the multiplexed channels. each 16-bit si ram entry defi nes the routing of 1?8 bits or bytes at a time. in addition to the routing, up to four strobe pins (logic or of four strobes in the transmit ram and four in r eceive ram) can be asserted according to the programming of the rams. the four si2 ram banks can be configured in many different ways to support various tdm channels. the user can defi ne the size of each si2 ram that is related to a certain tdm channel by programming the starting bank of that tdm. programming the starting shadow bank address, described in section 23.6.3, ?si2 ram shadow address registers (si2rsr),? determines whether this ram has a shadow for changing si2 ra m entries while the tdm channel is active. this reduces the number of availabl e si2 ram entries for that tdm. 23.5.1 one multiplexed channel with static frames the example in figure 23-5 shows one of many possible settings. w ith this configuration, the si2 ram has 256 entries for transmit data and strobe routing and 256 entries for recei ve data and strobe routing. this configuration should be chosen only when one tdm is required and the routing on that tdm does not en en si2 ram time-slot assigner tdm a,b, c enable = 1 tdm a pins tdm b pins fcc1 fcc2 scc1 scc3 scc4 smc1 smc2 mii1 or rmii1/utopia8 fc1 = 0 mii2 or rmii2/utopia8 fc2 = 0 scc3 pins sc3 = 0 scc4 pins sc4 = 0 smc1 pins smc1 = 0 smc2 pins smc2 = 0 nmsi mode in the cpm mux scc1 pins sc1 = 0 en tdm c pins 4 datasheet u .com
serial interface with time-slot assigner MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 23-8 freescale semiconductor need to be dynamically changed. the number of entrie s available in the si2 ra m is determined by the user. figure 23-5. one tdm channel with static frames and independent rx and tx routes 23.5.2 one multiplexed channel with dynamic frames in the configuration shown in figure 23-5 , one multiplexed channel has 256 entries for transmit data and strobe routing and 256 entries for receive data and strobe routing. each ram has two sections, the current-route ram and a shadow ram fo r changing serial routing dynamically. after programming the shadow ram, the user sets si2cmdr[csr xn ] for the associated channel. when the next frame sync arrives, the si automatically exchanges the current-route ram for the shadow ram. see section 23.5.5, ?static and dynamic routing.? figure 23-6. one tdm channel with shadow ram for dynamic route change 256 entries txa route framing signals l1tclka x l1tsynca x si2 ram address: 256 entries rxa route 511 1535 1024 l1rclka x l1rsynca x (each entry is 16 bits wide) 0 128 entries txa route framing signals l1tclka x l1tsynca x si2 ram address: 128 entries rxa route 255 1279 1024 l1rclka x l1rsynca x 1280 256 511 1535 (each entry is16 bits wide) 0 4 datasheet u .com
serial interface with time-slot assigner MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 23-9 this configuration should be chosen when only one tdm is needed, but dynamic rerouting may be needed on that tdm. similarly, for three tdm channels, th e number of si2 ram entrie s are reduced for every tdm channel programmed for shadow mode. 23.5.3 programming si2 ram entries the programming of each entry in the si2 ram determin es the routing of the serial bits (or bit groups) and the assertion of strobe outputs. figure 23-7 shows the entry fields. the si2 ram entry fields function as described in table 23-1 . 0 1 2 3 4 5 6 7 10 11 13 14 15 field ? swtr ssel1 ssel2 ssel3 ssel4 ? csel cnt byt lst r/w r/w offset see chapter 21, ?communications processor module overview.? figure 23-7. si2 ram entry fields table 23-1. si2 ram entry bits name description 0 ? reserved, should be cleared. 1 swtr switch tx and rx. valid only in the receive route ram and ignored in the transmit route ram. swtr affects the operation of both l1rxd and l1txd. swtr is set on ly in special situations where the user prefers to receive data from a transmit pin and transmit data on a receive pin. for instance, where devices a and b are connected to the same tdm, each with different time-s lots. normally, there is no opportunity for stations a and b to communicate with each other directly over the tdm, because they both receive the same tdm receive data and transmit on the same tdm transmit signal. 0 normal operation of l1txd and l1rxd 1 data for this entry is sent on l1rxd and received from l1txd see figure 23-8 for details. 2?5 sselx strobe select. there are four strobes available that can be assigned to the receive ram and asserted/negated with the received clock of this tdm channel (l1rclkx). they can also be assigned to the transmit ram and asserted/negated with the transmit clock of this tdm ch annel (l1tclkx). each bit corresponds to the value the strobe should have during this bit/byte group. there are four strobe pins for all ei ght strobe bits in the si2 ram entries, so the value on a strobe pin is the logical or of the rx and tx ram entry strobe bits. multiple strobes can be asserted simultaneously. a strobe config ured to be asserted in consecutive si2 ram entries remains continuously asserted for both entries. a strobe asserted on the last entry in a table is negated after the last entry is processed. note: each strobe is changed with the corresponding ra m clock and is output only if the corresponding parallel i/o is configured as a dedicated pin. if a st robe is programmed to be asserted in more than one set of entries (the si route entries for more t hen one tdm channel select the same strobe), the assertion of the strobe corresponds to the logical or of all possible sources. this use of strobes is not useful for most applications. a given strobe should be selected in only one set of si2 ram entries. 6 ? reserved, should be cleared. 4 datasheet u .com
serial interface with time-slot assigner MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 23-10 freescale semiconductor figure 23-8 shows how swtr can be used. figure 23-8. using the swtr feature the swtr option lets station b listen to transmissions from station a and send data to station a. to do this, station b would set swtr in its receive route ra m. for this entry, receive data is taken from the l1txd pin and data is sent on the l1 rxd pin. if the user wants to list en only to stati on a transmissions 7?10 csel channel select. determines the routing of the bit/byte group. 0000 the bit/byte group is not supported by the mpc 8555e. the transmit data pin is three-stated and the receive data pin is ignored. 0001 routed to scc1 0010 reserved 0011 routed to scc3 0100 routed to scc4 0101 routed to smc1 0110 routed to smc2 0111 the bit/byte group is not supported by the mpc855 5e. this code is also used in scit mode as the d channel grant. see section 23.8.2.2, ?scit programming.? 1000 reserved 1001 routed to fcc1 1010 routed to fcc2 1011 reserved 11xx reserved 11?13 cnt count. indicates the number of bits/bytes (according to the byt bit) that the routi ng and strobe select of this entry controls. 000 = 1 bit/byte; 111= 8 bits/bytes. 14 byt byte resolution 0 bit resolution. the cnt value indicate s the number of bits in this group. 1 byte resolution. the cnt value indicate s the number of bytes in this group. 15 lst last entry in the ram. whenever si2 ram is used, ls t must be set in one of t he tx or rx entries of each group. even if all entries of a group are used, this bit must still be set in the last entry. 0 not the last entry in this section of the route ram. 1 last entry in this ram. after this entry, the si waits for the sync signal to start the next frame. note: there must be only an even number of entries in an si2 ram frame, because lst is active only in odd-numbered entries (assuming the entry count starts with 0). therefore, to obtain an even number of entries, an entry may need to be split into two entries. also note that, to avoid errors in switching to and from shadow si ram, the last entry in si ram should not be programmed to 1-bit resolution (that is, cnt = 000 and byt = 0). table 23-1. si2 ram entry (continued) bits name description rx station a tx rx station b tx l1txd l1rxd rx station a tx tx station b rx l1txd l1rxd tx and rx si2 ram n [swtr] = 1 tx and rx si2 ram n [swtr] = 0 4 datasheet u .com
serial interface with time-slot assigner MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 23-11 and not send data on l1rxd, the csel bits in th e corresponding transmit route ram entry should be cleared to prevent tran smission on the l1rxd pin. station b can transmit data to stat ion a by setting the swtr bit of th e entry in its receive route ram. data is sent on l1rxd ra ther than l1txd, according to the transmit route ram. note that this configuration could cause collisions with other data on l1rxd unless an available (quiet) time slot is used. to transmit on l1rxd and not receive data on l1txd, clear the csel bits in the receive route ram. note if the transmit and receive sections of the tdm do not use a common clock source, the swtr feature ca n cause erratic behavior. 23.5.4 si2 ram programming example this example shows how to program th e ram to support the 10-bit idl bus. figure 23-23 shows the 10-bit idl bus format. in this exam ple, the tsa supports the b1 channe l with scc3, the d channel with scc1, the first 4 bits of the b2 channel with an ex ternal device (using a strobe to enable the external device), and the last 4 bits of b2 with smc1. additionally, the tsa marks the d channel with another strobe signal. first, divide the frame from the star t (the sync) to the end of the fram e according to the support that is required: ? 8 bits (b1)?scc3 ? 1 bit (d)?scc1 + strobe 1 ? 1 bit?no support ? 4 bits (b2)?strobe 2 ? 4 bits (b2)?smc1 ? 1 bit (d)?scc1 + strobe 1 each of these six divisions can be supported by a si ngle si2 ram entry. thus, six si2 ram entries are needed. see table 23-2 . table 23-2. si2 ram entry descriptions entry number si2 ram entry swtr ssel csel cnt byt lst description 0 0 0000 0011 000 1 0 8-bit scc3 1 0 1000 0001 000 0 0 1-bit scc1 strobe1 2 0 0000 0000 000 0 0 1-bit no support 3 0 0100 0000 011 0 0 4-bit strobe2 4 0 0000 0101 011 0 0 4-bit smc1 5 0 1000 0001 000 0 1 1-bit scc1 strobe1 4 datasheet u .com
serial interface with time-slot assigner MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 23-12 freescale semiconductor note idl requires the same rout ing for both receive and tr ansmit., therefore, an exact duplicate of the above entries shoul d be written to both the receive and transmit sections of the si2 ram. then si2mr[crtx] can be used to instruct the si2 ram to use the same clock and sync to simultaneously control both sets of si2 ram entries. 23.5.5 static and dynamic routing the si2 ram has two operating modes for the tdms: ? static routing. the number of si2 ram entries is determined by the banks the user relates to the corresponding tdm and is divided into two parts (rx and tx). the following sequence must be followed to program the routing entries. ? all serial devices connected to the tsa must be disabled. ? si routing can be modified. ? all appropriate serial devices connect ed to the tsa must be re-enabled. ? dynamic routing. a tdm?s routing definition can be modified while fccs, sccs, or smcs are connected to the tdm. the number of si2 ram entr ies is determined by the banks the user relates to the corresponding tdm channel and is divided into four parts (rx, rx shadow, tx, and tx shadow). dynamic changes divide portions of the si2 ram into current-route and shadow ram. once the current-route ram is programmed, th e tsa and si channels are enabled, and tsa operation begins. when a change in routing is required, the shadow ram must be programmed with the new route and si2cmdr[csr xn ] must be set. as a result, as soon as th e corresponding sync arrives the si exchanges the shadow ram with the curr ent-route ram a nd resets csr xn to indicate that the operation is complete. at this time, the user may change the routing again. notice that the or iginal current-route ram is now the shadow ram and vice versa. figure 23-9 shows an example of the sha dow ram exchange process for two tdm channels both with ha lf of the ram as a shadow. if for instance one tdm with dynamic changes is pr ogrammed to own all four banks, and the shadow is programmed to the last two banks, the initial current- route ram addresses in th e si2 ram are as follows. ? 0?255: txa route ? 1024?1279: rxa route the initial shadow rams are at addresses: ? 256?511: txa route ? 1280?1535: rxa route the user can read any ram at any ti me, but for proper si operation the us er must not attempt to write the current-route ram. the si2 st atus register (si2str) ca n be read to find out whic h part of the ram is the current-route ram. the user can also externally connect one of the st robes to an interrupt pin to generate an interrupt on a pa rticular si2 ram entry starti ng or ending execution by the tsa. 4 datasheet u .com
serial interface with time-slot assigner MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 23-13 note the current-route and shadow si rams of a given tdm x should be contiguous; that is, the current-rout e and shadow si rams of differing tdm x should not be interleaved. an example is shown in figure 23-9 . figure 23-9. example: si2 ram dynamic changes, tdma and tdmc, same si2 ram size l1tclkc l1tsyncc 64 txc shadow 64 txa 64 txc route route the tsa uses the first part of framing signals: l1tclka l1tsynca 1) initial state the ram, and the shadow is 64 txa shadow 0 127 128 255 256 383 384 511 csrra = 0 the user programs the 2) programming shadow ram for the new the si swaps between swap the shadow and the rx and tx route and sets the second part of the ram. csr xn = 0 current-route rams 1024 1151 1152 1279 1280 1407 1408 1535 ram address: csrta = 0 csrrc = 0 csrtc = 0 csrra = 1 csrta = 1 csrrc = 1 csrtc = 1 csrra = 0 csrta = 0 csrrc = 0 csrtc = 0 l1rclkc l1rsyncc 64 rxc shadow 64 rxa 64 rxc route route framing signals: l1rclka l1rsynca 64 rxa shadow ram address: csr xn . l1tclkc l1tsyncc 64 txc shadow 64 txa 64 txc route route framing signals: l1tclka l1tsynca 64 txa shadow 0 127 128 255 256 383 384 511 1024 1151 1152 1279 1280 1407 1408 1535 ram address: l1rclkc l1rsyncc 64 rxc shadow 64 rxa 64 rxc route route framing signals: l1rclka l1rsynca 64 rxa shadow ram address: and resets csr xn . l1tclkc l1tsyncc 64 txc shadow 64 txa 64 txc route route framing signals: l1tclka l1tsynca 64 txa shadow 0 127 128 255 256 383 384 511 1024 1151 1152 1279 1280 1407 1408 1535 ram address: l1rclkc l1rsyncc 64 rxc shadow 64 rxa 64 rxc route route framing signals: l1rclka l1rsynca 64 rxa shadow ram address: 3) 4 datasheet u .com
serial interface with time-slot assigner MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 23-14 freescale semiconductor 23.6 serial interface registers the serial interface registers are de scribed in the following sections. 23.6.1 si global mode registers (si2gmr) the si global mode regist ers (si2gmr), shown in figure 23-10 , defines the activati on state of the tdm channels for si2. table 23-3 describes si2gmr. 23.6.2 si mode registers (si2mr) there are three si mode re gisters (si2mr), shown in figure 23-11 , one for each tdm channel (si2amr, si2bmr, and si2cmr). they are used to define si operation modes and allow the user (with si2 ram) to support any or all of the isdn channels independently when in id l or gci mode. any extra serial channel can then be used for other purposes. 01234567 field ? stzc stzb stza ? enc enb ena reset 0000_0000 r/w r/w offset 0x0x9_1b48 (si2gmr) figure 23-10. si global mode registers (si2gmr) table 23-3. si2gmr field descriptions bit name description 0,4, ? reserved, should be cleared. 1, 2, 3 stzx program l1txdx to zero for tdm a, b, or c 0 normal operation 1 l1txdx = 0 until serial clocks are available, which is useful for gci activation. see section 23.8.1, ?si gci activation/deactivation procedure.? 5, 6, 7 enx enable tdmx. note that enabling a tdm is the last step in initialization. 0 tdm channel x is disabled. the si2 rams and routing for tdmx are in a state of reset, but all other si functions still operate. 1 all tdmx functions are enabled. 01 34567 8 9101112131415 field ? sadx sdmx rfsdx dscx crtx slx cex fex gmx tfsdx reset 0000_0000_0000_0000 r/w r/w offset 0x9_1b40 (si2amr), 0x9_1b 42 (si2bmr), 0x9_1b44 (si2cmr) figure 23-11. si mode registers (si2mr) 4 datasheet u .com
serial interface with time-slot assigner MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 23-15 table 23-4 describes si2mr fields. table 23-4. si2mr field descriptions bits name description 0 ? reserved, should be cleared. 1?3 sadx starting bank address for the ram of tdm a, b, or c. these three bits define t he starting bank address of the si2 ram section that belongs to tdmx channel. note: as noted previously, the si2 ram c ontains four banks of 64 entries for receive and four banks of 64 entries for transmit. the starting bank address of each tdm can be programmed with a granularity of 32 entries. the user can put the shadow ram section of the same tdm on the same bank, but the user cannot put two different tdms on the same bank. the last entry of a certain tdm is determined by the lst bit in the si2 ram entry. the user must set lst within the entries of si2 ram blocks for every tdm used, that is, before the starting address of the next tdm. 000 first bank, first 32 entries 001 first bank, second 32 entries 010 second bank, first 32 entries 011 second bank, second 32 entries 100 third bank, first 32 entries 101 third bank, second 32 entries 110 fourth bank, first 32 entries 111 fourth bank, second 32 entries 4?5 sdmx si diagnostic mode for tdm a, b, or c 00 normal operation. 01 automatic echo. in this mode, the tdm transmitter automatically retransmits the tdm received data on a bit-by-bit basis. the receive section operates norm ally, but the transmit se ction can only retransmit received data. in this mode, the l1grx line is ignored. 10 internal loopback. in this mode, the tdm transmitter output is internally connected to the tdm receiver input (l1txdx is connected to l1rxdx). the receiver and transmitter operate normally. the data appears on the l1txdx pin and in this mode, l1rq x is asserted normally. the l1grx line is ignored. 11 loopback control. in this mode, the tdm transmitter output is internally connected to the tdm receiver input (l1txdx is connected to l1rxdx). the transmitter output (l1txdx) and l1rq x are inactive. this mode is used to accomplish loopback testing of the ent ire tdm without affecting the external serial lines. note: in modes 01, 10, and 11, the receive and transmit clocks should be identical. 6?7 rfsdx receive frame sync delay for tdm a, b, or c. determ ines the number of clock delays between the receive sync and the first bit of the receive frame. even if crtx is set, these bits do not control the delay for the transmit frame. 00 no bit delay. the first bit of the frame is transmitt ed/received on the same clock as the sync; use for gci. 01 1-bit delay. use for idl 10 2-bit delay 11 3-bit delay figure 23-12 and figure 23-13 show how these bits are used. 8 dscx double speed clock for tdm a, b, or c. some tdms, such as gci, define the input clock to be twice as fast as the data rate and this bit controls this option. 0 the channel clock (l1rclkx and/or l1tclkx) is equal to the data clock. use for idl and most tdm formats. 1 the channel clock rate is twice the data rate. use for gci. note: when an si is in 2x mode (dsc = 1), the si does not ignore sync signals asserted in the last phase of the last clock cycle of the frame. 4 datasheet u .com
serial interface with time-slot assigner MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 23-16 freescale semiconductor figure 23-12 shows the one-clock delay from sync to data when x fsd = 01. figure 23-12. one-clock delay from sync to data ( x fsd = 01) 9 crtx common receive and transmit pins for tdm a, b, or c. useful when the transmit and receive sections of a given tdm use the same clock and sync signals. in this mode, l1tclkx and l1tsyncx can be used for their alternate functions. 0 separate pins. the receive section of this tdm us es l1rclkx and l1rsyncx pins for framing and the transmit section uses l1tclkx and l1tsyncx for framing. 1 common pins. the receive and transmit sections of this tdm use l1rclkx as clock pin of channel x and l1rsyncx as the receive and transmit sync pin. use for idl and gci. rfsd and tfsd are independent of one another in this mode. 10 slx sync level for tdm a, b, or c. 0 the l1rsyncx and l1tsyncx signals are active on logic 1. 1 the l1rsyncx and l1tsyncx signals are active on logic 0. 11 cex clock edge for tdm a, b, or c. the function depends on dscx. when dscx = 0: 0 the data is sent on the rising edge of the clock and received on the falling edge (use for idl). 1 the data is sent on the falling edge of the clock and received on the rising edge. when dscx = 1: 0 the data is sent on the rising edge of the clock and received on the rising edge. 1 the data is sent on the falling edge of the clock and received on the falling edge (use for gci). see figure 23-14 and figure 23-15 . 12 fex frame sync edge for tdm a, b, or c. determines whether l1rsyncx and l1tsyncx pulses are sampled with the falling/rising edge of the channel clock. see figure 23-13 , figure 23-14 , figure 23-15 , and figure 23-16 . 0 falling edge. use for idl and gci 1 rising edge 13 gmx grant mode for tdm a, b, or c. 0 gci/scit mode. the gci/scit d chann el grant mechanism for transmission is internally supported. the grant is one bit from the receive channel. this bit is marked by programming the channel select bits of the si2 ram with 0111 to assert an internal strobe on it. see section 23.8.2.2, ?scit programming.? 1 idl mode. a grant mechanism is supported if the corresponding cmxscr[gr x ] bit is set. the grant is a sample of l1grx while l1rsyncx is asserted. this grant mechanism implies the idl access controls for transmission on the d channel. see section 23.7.2, ?idl interface programming.? 14?15 tfsdx transmit frame sync delay for tdm a, b, or c. de termines the number of clock delays between the transmit sync and the first bit of the transmit frame. see figure 23-16 . 00 no bit delay. the first bit of the frame is transmitted/received on the same clock as the sync. 01 1-bit delay 10 2-bit delay 11 3-bit delay table 23-4. si2mr field descriptions (continued) bits name description l1clk data (ce = 0) l1sync (fe = 1) bit 0bit 1bit 2bit 3bit 4 bit 0 one-clock delay from sync latch to first bit of frame bit 5 end of frame 4 datasheet u .com
serial interface with time-slot assigner MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 23-17 figure 23-13 shows the elimination of th e single-clock delay shown in figure 23-12 by clearing x fsd. figure 23-13. no delay from sync to data ( x fsd = 00) figure 23-14 shows the effects of changing fe when ce = 1 with a 1-bit frame sync delay. figure 23-14. falling edge (fe) effect when ce = 1 and x fsd = 01 figure 23-15 shows the effects of changing fe when ce = 0 with a 1-bit frame sync delay. figure 23-15. fe effect when ce = 0 and x fsd = 01 l1clk data (ce = 0) l1sync (fe = 1) bit 0bit 1bit 2bit 3bit 4 no delay from sync latch to first bit of frame bit 2 bit 1 bit 0 l1txd rx sampled here l1st l1sync l1sync l1clk (bit 0) (on bit 0) l1st driven from clock high for xfsd = 01 (fe = 0) (fe = 1) ce = 1 both fe settings l1txd rx sampled here l1st l1sync l1sync l1clk (bit 0) (on bit 0) l1st is driven from clock low (fe = 0) (fe = 1) ce = 0 in both the fe settings xfsd = 01 4 datasheet u .com
serial interface with time-slot assigner MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 23-18 freescale semiconductor figure 23-16 shows the effects of changing fe wh en ce = 1 with no frame sync delay. figure 23-16. falling edge (fe) effect when ce = 1 and x fsd = 00 l1txd l1st l1sync l1clk (bit 0) (on bit 0) xfsd = 0 0 (fe = 0) ce = 1 the l1st is driven from sync data is driven from clock low l1txd l1st l1sync (bit 0) (on bit 0) (fe = 0) l1st is driven from clock high l1txd l1st l1sync (bit 0) (on bit 0) (fe = 1) both data bit-0 and l1st are driven from sync rx sampled here rx sampled here l1txd l1st l1sync (bit 0) (on bit 0) (fe = 1) l1st and data bit-0 is driven from clock low 4 datasheet u .com
serial interface with time-slot assigner MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 23-19 figure 23-17 shows the effects of changing fe wh en ce = 0 with no frame sync delay. figure 23-17. falling edge (fe) effect when ce = 0 and x fsd = 00 l1txd l1st l1sync l1clk (bit 0) (on bit 0) xfsd = 00 (fe = 1) ce = 0 the l1st is driven from sync data is driven from clock high l1txd l1st l1sync (bit 0) (on bit 0) (fe = 1) l1st is driven from clock low l1txd l1st l1sync (bit 0) (on bit 0) (fe = 0) both the data and l1st from sync when asserted during clock high rx sampled here l1txd l1st l1sync (bit 0) (on bit 0) (fe = 0) both the data and l1st from the clock when asserted during clock low 4 datasheet u .com
serial interface with time-slot assigner MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 23-20 freescale semiconductor 23.6.3 si2 ram shadow address registers (si2rsr) the si2 ram shadow address re gisters (si2rsr), shown in figure 23-18 , define the starting addresses of the shadow section in the si2 ram for each of the tdm channels. table 23-5 describes si2rsr fields. 23.6.4 si command register (si2cmdr) the si command registers (si2cmdr), shown in figure 23-19 , allow the user to dynamically program the si2 ram. when the user sets bits in the si2cmd r, the si2 switches to the shadow si2 ram at the end of the current-route ram pr ogramming frame. for more info rmation about dyna mic programming, see section 23.5.5, ?static and dynamic routing.? 01 345 789 1112 15 field ? ssada ? ssadb ? ssadc ? reset 0000_0000_0000_0000 r/w r/w offset 0x9_1b4e (si2rsr) figure 23-18. si2 ram shadow address registers (si2rsr) table 23-5. si2rsr field descriptions bits name description 0, 4, 8, 12?15 ? reserved, should be cleared. 1?3, 5?7, 9?11 ssad x starting bank address for the shadow ram of tdm a, b, or c. defines the starting bank address of the shadow si2 ram section that belongs to the corresponding tdm channel. note: as noted before, the si2 ram contain four banks of 64 entries for receive and four banks of 64 entries for transmit. in spite of the above, the starting bank address of each tdm can be programmed by the user in a granularity of 32 entries, but the user cannot put two different tdms on the same bank. the user can put the shadow ram secti on of the same tdm on the same bank. the last entry of a certain tdm frame is determined by the lst bit in the si2 ram entry. the user must set this bit within the entries of si2 ram shadow blocks for every tdm used. that means before the starting address of the next tdm. 01234567 field csrra csrta csrrb csrtb csrrc csrtc ? ? reset 0000_0000 r/w r/w offset 0x9_1b4a (si2cmdr) figure 23-19. si command register (si2cmdr) 4 datasheet u .com
serial interface with time-slot assigner MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 23-21 table 23-6 describes si2cmdr fields. 23.6.5 si status registers (si2str) the si status register (si2str), shown in figure 23-20 , identifies the current-r oute ram. si2str values are valid only when the co rresponding si2cmdr bit = 0. table 23-7 describes si2str fields. table 23-6. si2cmdr field descriptions bits name description 0, 2, 4 csrrx change shadow ram for tdm a, b, or c receiver. set csrrx causes the si receiver to replace the current route ram with the shadow ram. set by the user and cleared by the si. 0 the receiver shadow ram is not valid. the user can write into the shadow ram to program a new routing. 1 the receiver shadow ram is valid. the si exchange s between the rams and take the new receive routing from the receiver shadow ram. cleared as soon as the switch has completed. 1, 3, 5 csrtx change shadow ram for tdm a, b, or c transmitter. set csrtx causes the si transmitter to replace the current route ram with the shadow ram. set by the user and cleared by the si. 0 the transmitter shadow ram is not valid. the user can write into the shadow ram to program a new routing. 1 the transmitter shadow ram is valid. the si exchan ges between the rams and take the new transmitter routing from the receiver shadow ram. cleared as soon as the switch has completed. 6?7 ? reserved, should be cleared. 01234567 field crora crota crorb crotb crorc crotc ? ? reset 0000_0000 r/w r offset 0x9_1b4c (si2str) figure 23-20. si status registers (si2str) table 23-7. si2str field descriptions bits name description 0, 2, 4 crorx current-route original receiver. determines whet her the current-route receiver ram is the original or the shadow. 0 the current-route receiver ram is the lower address area. 1 the current-route receiver ram is the upper address area. 1, 3, 5 crotx current-route original transmitter. determines wh ether the current-route transmitter ram is the original or the shadow. 0 the current-route transmitter ra m is the lower address area. 1 the current-route transmitter ra m is the upper address area. 6?7 ? reserved, should be cleared. 4 datasheet u .com
serial interface with time-slot assigner MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 23-22 freescale semiconductor 23.7 MPC8555E serial interface idl interface support the idl interface is a full-duplex isdn interface used to connect a physical layer device to the MPC8555E. the MPC8555E supports both th e basic and primary ra te of the idl bus. in the basic rate of idl, data on three channels (b1, b2, and d) is transferred in a 20- bit frame, providing a full-duplex bandwidth of 160 kbps. the MPC8555E is an idl slav e device that is clocked by the idl bus master (physical layer device) and has separate receive a nd transmit sections. the MPC8555E has three tdms, and it can support only three indepe ndent idl buses (limited by the number of tdms) using separate clocks and sync pulses. figure 23-21 shows an application with two idl buses. figure 23-21. dual idl bu s application example 23.7.1 idl interface example an example of the idl application is the isdn terminal adaptor shown in figure 23-22 . in such an application, the idl interface is used to connect the 2b+d channels betw een the MPC8555E, codec, and s/t transceiver. one of the mp c8555e sccs is configured to hdlc mode to handle the d channel; another MPC8555E scc is used to rate adapt the terminal data stream over the firs t b channel. that scc is configured for hdlc mode if v.120 rate adoption is required. the second b cha nnel is then routed to the codec as a digital voice channel, if preferred. the spi is used to send in itialization commands and periodically check status from the s/ t transceiver. the smc connected to the terminal is configured for uart. s/t s/t u u s/t s/t idl1 s/t interfaces idl2 isdn te nt u interfaces MPC8555E 4 datasheet u .com
serial interface with time-slot assigner MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 23-23 figure 23-22. idl terminal adaptor the MPC8555E can identify and support each idl cha nnel or can output strobe lines for interfacing devices that do not support the idl bus. the idl si gnals for each transmit a nd receive channel are described in table 23-8 . table 23-8. idl signal descriptions signal description l1rclk x idl clock; input to the MPC8555E l1rsync x idl sync signal; input to the MPC8555E. this signal indi cates that the clock periods following the pulse designate the idl frame. l1rxd x idl receive data; input to the MPC8555E. valid only for the bits supported by the idl; ignored for any other signals present. l1txd x idl transmit data; output from the MPC8555E. valid only fo r the bits that are supported by the idl; otherwise, three-stated. l1rq x idl request permission to transmit on the d channel; output from the MPC8555E on the l1rqx pin. l1gr x idl grant permission to transmit on the d channel; input to the MPC8555E on the l1tsyncx pin. note: x = a, b, or c for tdma and tdmb, and tdmc. tsa fcc1 ethernet ethernet phy lan async pcm codec/filter monocircuit s/t transceiver spi icl (control) b1+b2+d idl (data) b2+d b1 system bus (rom and ram) smc1 pots 4 wire scc4 smc2 scc3 MPC8555E 4 datasheet u .com
serial interface with time-slot assigner MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 23-24 freescale semiconductor the basic rate idl bus has the three following channels: ? b1 is a 64-kbps bearer channel ? b2 is a 64-kbps bearer channel ? d is a 16-kbps signaling channel there are two definitions of the idl bus frame stru cture?8 and 10 bits. the onl y difference between them is the channel order within the frame. see figure 23-23 . figure 23-23. idl bus signals note previous versions of freescale idl- defined bit functions called auxiliary (a) and maintenance (m) were remove d from the idl definition when it was concluded that the idl control channel would be out-of-band. these functions were defined as a subset of the freescale spi format called serial control port (scp). to implement the a and m bits as originally defined, program the tsa to access these bits a nd route them transparently to an scc or smc. use the spi to perform out-of-b and signaling. the MPC8555E supports all channels of the idl bus in the basic rate. each bit in the idl frame can be routed to any scc and smc or can assert a str obe output for supporting an external device. the MPC8555E supports the request-grant method for contention de tection on the d cha nnel of the idl basic rate and when the MPC8555E ha s data to transmit on the d channel, it asserts l1rq x . the physical layer device monitors the physical layer bus for activity on the d channel and i ndicates that the channel is free by asserting l1gr x . the MPC8555E samples the l1grx signa l when the idl sync signal (l1rsync x ) is asserted. if l1grx is asserted, the MPC8555E sends the first zero of th e opening flag in the first bit of the d channel. if a collision is detected on th e d channel, the physical layer device negates l1gr x . the MPC8555E then stops sending and retransmits the frame when l1gr x is reasserted. this procedure is handled automatically for the first two buffers of a frame. l1clk l1sync l1rxd l1txd b1 d1 10-bit idl d2 b1 d1 b2 d2 l1rxd l1txd b1 d1 8-bit idl d2 b1 b2 d2 b2 d1 b2 notes: 1. clocks are not to scale. 2. l1rq x and l1gr x are not shown. 4 datasheet u .com
serial interface with time-slot assigner MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 23-25 for the primary rate idl, the MPC8555E supports up to four 8-bit channels in the frame, determined by the si2 ram programming. to support more channels, the user can route more than one channel to each scc and the scc treats it as one high-speed stream and store it in the same data buffers (appropriate only for transparent data). additionally, the MPC8555E can be used to assert strobes for support of additional external idl channels. the idl interface supports the ccitt i.460 recommendation for data-rate adaptation since it separately accesses each bit of the idl bus. the current-route ram specifies which bits are supported by the idl interface and by which serial controller. the receiver only receives bits that are enabled by the receiver route ram. otherwise, the transmit ter sends only bits that are enable d by the transmitter route ram and three-states l1txd x . 23.7.2 idl interface programming to program an idl interfac e, first program si2mr[gm x ] to the idl grant mode for that channel. if the receive and transmit sections interfac e to the same idl bus, set si2mr[crt x ] to internally connect the rx clock and sync signals to the transmit sect ion. then, program the si2 ram used for the idl channels to the preferred routing. see section 23.5.4, ?si2 ram programming example.? define the idl frame structure by programming si2mr[ x fsd x ] to have a 1-bit dela y from frame sync to data, si2mr[fe x ] to sample on the falling edge, and si2mr[ce x ] to transmit on the rising edge of the clock. program the parallel i/o open- drain register so that l1txd x is three-stated when inactive; see section 45.2.1, ?port open-dra in registers (podrx).? to support the d channel, program the appropriate cmxscr[gr x ] bit, as described in section 24.4.4, ?cmx scc clock route register (cmxscr),? and program the si2 ram entry to route data to the chosen serial contro ller. the two definitions of idl, 8 or 10 bits, are implemented by simply modifying the si2 ram programming. in both cases, l1gr x is sampled while l1tsync x is asserted and transferred to th e d-channel scc as a grant indication. for example, based on the same 10-bit format as in section 23.5.4, ?si2 ram programming example,? implement an idl bus using scc1, scc3, an d smc1 connected to tdma2 as follows: 1. program both the tx and rx sections of the si2 ram as in table 23-9 . 2. cmxsi2cr = 0x00. tdma re ceive clock is clk13. table 23-9. si2 ram entries for an idl interface entry number si2 ram entry swtr ssel csel cnt byt lst description 0 0 0000 0011 000 1 0 8-bit scc3 1 0 0000 0001 000 0 0 1-bit scc1 2 0 0000 0000 000 0 0 1-bit no support 3 0 0000 0101 011 0 0 4-bit smc1 4 0 0000 0101 011 0 0 4-bit smc1 5 0 1000 0001 000 0 1 1-bit scc1 strobe1 4 datasheet u .com
serial interface with time-slot assigner MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 23-26 freescale semiconductor 3. cmxsmr = 0x80. smc1 is connected to the tsa. 4. cmxscr = 0xc000_4000. scc1 and scc3 are connect ed to the tsa. scc1 supports the grant mechanism because it handles the d channel. 5. si2amr = 0x0145. tdma grant mode is used with 1-bit frame sync delay in tx and rx and common receive-transmit mode. 6. set ppard[20?22], pparc[9]. configures l1txda, l1rxda, l1tsynca, and l1rsynca. 7. set psord[20?22], psorc[9]. configures l1txda, l1rxda, l1tsynca, and l1rsynca. 8. clear pdird[22]. configures l1txda(inout). 9. set podrd[22]. configures l1 txda to an open-drain output. 10. set pparc[19]. configures l1rclka. 11. clear pdirc[19]. configures l1rclka. 12. clear psorc[19]. configures l1rclka. 13. set pparc[1]. configures l1rqa . 14. set psorc[1]. configures l1rqa . 15. set pdirc[1]. configures l1rqa . 16. set pparc[8]. configures l1st1. 17. set psorc[8]. configures l1st1. 18. set pdirc[8]. configures l1st1. 19. si2cmdr is not used. 20. si2str does not need to be read. 21. configure the scc1 for hdlc operation (to ha ndle the lapd protocol of the d channel), and configure scc3 and smc1 as preferred. 22. si2gmr = 0x01. enable tdm a (one static tdm). 23. enable scc1, scc3, and smc1. 23.8 serial interface gci support the MPC8555E fully supports the normal mode of th e gci, also known as the isdn-oriented modular revision 2.2 (iom-2), and the scit. the MPC8555E al so supports the d-channel access control in s/t interface terminals using the co mmand/indication (c/i) channel the gci bus consists of f our lines?two data lines, a clock, and a frame synchroni zation line. usually, an 8-khz frame structure defines the various channe ls within the 256-kbps data rate. the MPC8555E supports two (limited by the number of smcs and td ms) independent gci buses, each with independent receive and transmit sections. the in terface can also be used in a mult iplexed frame structure on which up to eight physical layer devices mul tiplex their gci channels. in this mode, the data rate would be 2,048 kbps. in the gci bus, the clock rate is twice the data rate . the si divides the input clock by two to produce the data clock. the MPC8555E also has data strobe lines and the 1 data rate clock l1clkox output pins. these signals are used for interfacing devi ces to gci that do not support the gci bus. table 23-10 describes gci signals for each transmit and receive channel. 4 datasheet u .com
serial interface with time-slot assigner MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 23-27 the gci bus signals are shown in figure 23-24 . figure 23-24. gci bus signals in addition to the 144-kbps isdn 2b+d channels, th e gci provides five channels for maintenance and control functions: ? b1 is a 64-kbps bearer channel ? b2 is a 64-kbps bearer channel ? m is a 64-kbps monitor channel ? d is a 16-kbps signaling channel ? c/i is a 48-kbps c/i channel (includes a and e bits) the m channel is used to transfer data between layer 1 devices and the control unit (the cpu); the c/i channel is used to control activati on/deactivation procedures or to switc h test loops by the control unit. the m and c/i channels of the gci bus should be routed to smc1 or smc2, which have modes to support the channel protocols. the MPC8555E can support any ch annel of the gci bus in the primary rate by modifying si2 ram programming. the gci supports the ccitt i.460 recommendation as a method for data rate adaptation since it can access each bit of the gci separate ly. the current-route ram specifies which bits are supported by the table 23-10. gci signals signal description l1rsync x used as a gci sync signal; input to the MPC8555E. this si gnal indicates that the clock periods following the pulse designate the gci frame. l1rclk x used as a gci clock; input to the MPC8555E. the l1rclk x signal frequency is twice the data clock. l1rxd x used as a gci receive data; input to the MPC8555E. l1txd x used as a gci transmit data; open-drain output. valid only for the bits that are supp orted by the idl; otherwise, three-stated. l1clko x optional signal; output from the MPC8555E. this 1 clock output is used to clock devices that do not interface directly to the gci. if the double-speed clock is used, (dsc x bit is set in the si2mr), this output is the l1rclk x divided by 2; otherwise, it is simply a 1 output of the l1rclk x signal. note: x = a, b, and c for tdma and tdmb and tdmc. l1clk l1sync l1rxd l1txd b1 b2 b1 b2 m (monitor) c/i a e m (monitor) c/i a e (2 the data rate) notes: clock is not to scale. l1clko is not shown. d2 d1 d1 d2 4 datasheet u .com
serial interface with time-slot assigner MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 23-28 freescale semiconductor interface and which serial controlle r support them. the receiv er only receives the bits that are enabled by the si2 ram and the transmitter only transmits the bits that are enabled by the si2 ram and does not drive l1txdx. otherwise, l1txdx is an open-dr ain output and should be pulled high externally. the MPC8555E supports contention detection on the d channel of the scit bus. when the MPC8555E has data to transmit on the d channel, it checks a sc it bus bit that is marked with a special route code (usually, bit 4 of c/i channel 2). the physical laye r device monitors the physical layer bus for activity on the d channel and indicates on this bit that the channel is free. if a collision is detected on the d channel, the physical layer device sets bit 4 of c/i channe l 2 to logic high. the MPC8555E then aborts its transmission and retransmits the fram e when this bit is set again. this procedure is automatically handled for the first two buffers of a frame. 23.8.1 si gci activation /deactivation procedure in the deactivated state, the clock pul se is disabled and the data line is at a logic one. the layer 1 device activates the MPC8555E by enabling the clock pulses and by an indication in the channel 0 c/i channel. the MPC8555E reports to the core (through a maskable interrupt) that a valid indication is in the smc rxbd. when the core activates the line, the data out put of l1txdn is progr ammed to zero by setting si2gmr[stzx]. code 0 (command timi ng tim) is transmitted on channe l 0 c/i channel to the layer 1 device until stzx is reset. the phys ical layer device resu mes the clock pulses and gives an indication in the channel 0 c/i channel. the core shoul d reset stzx to enable data output. 23.8.2 serial interface gci programming the following sections describe serial interface gci programming. 23.8.2.1 normal mode gci programming the user can program and configure th e channels used for the gci bus in terface. first, the si2mr register to the gci/scit mode for that channe l must be programm ed, using the dsc x , fe x , ce x , and rfsd x bits. this mode defines the sync pulse to gci sync for fr aming and data clock as one -half the input clock rate. the user can program more than one channel to interface to the gci bus. also, if the receive and transmit section are used for in terfacing the same gci bus, the user inte rnally connects the receive clock and sync signals to the si2 ram transm it section, using the crt x bits. the user should th en define the gci frame routing and strobe sele ct using the si2 ram. when the receive and transmit section uses the same clock and sync signals, th ese sections should be programmed to the same conf iguration. also, the l1txd x pin in the i/o register should be programmed to be an open-drain output. to support the monitor and the c/i channels in gci, those channels should be routed to one of the smcs. to support the d channel when there is no possibility of collision, the user should clear the si2mr[gr x ] bit corresponding to the scc that supports the d channel. 4 datasheet u .com
serial interface with time-slot assigner MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 23-29 23.8.2.2 scit programming for interfacing the gci/scit bus, si 2mr must be programmed to the gci/scit mode. the si2 ram is programmed to support a 96-bit frame length and the frame sync is pr ogrammed to the gci sync pulse. generally, the scit bus supports the d channel acces s collision mechanism. for this purpose, the user should program the crt x bits so the receive and tr ansmit sections use the same clock and sync signals and program the gr x bits to transfer the d channel grant to th e scc that supports this channel. the received (grant) bit should be marked by programming the channe l select bits of the si2 ram to 0b0111 for an internal assertion of a strobe on this bit. this bit is sampled by the si and transferred to the d-channel scc as the grant. the bit is generally bi t 4 of the c/i in channel 2 of the gc i, but any other bit can be selected using the si2 ram. for example, assuming that scc1 is connected to the d channel, scc3 to the b1 channel, and smc2 to the b2 channel, smc1 is used to handle the c/i channe ls, and the d-channel grant is on bit 4 of the c/i on scit channel 2, the initializa tion sequence is as follows: 1. program both the tx and rx s ections of the si2 ram as in table 23-11 beginning at addresses 0 and 1024, respectively. 2. si2amr = 0x00c0. tdma is used in double spee d clock and common rx/t x modes. scit mode is used in this example. note if scit mode is not used, delete th e last three entries of the si2 ram, divide one entry into two, and set the lst bit in the new last entry. 3. cmxsmr = 0x88. smc1 and smc2 are connected to the tsa. 4. cmxscr = 0xc000_4000. scc3 and scc1 are connect ed to the tsa. scc1 supports the grant mechanism since it is on the d channel. 5. cmxsi2cr = 0x00. tdma uses clk13. 6. set ppard[20?22], pparc[9]. configures l1txda, l1rxda, l1tsynca, and l1rsynca. 7. set psord[20?22], psorc[9]. configures l1txda, l1rxda, l1tsynca, and l1rsynca. table 23-11. si2 ram entries for a gci interface (scit mode) entry number si2 ram entry swtr ssel csel cnt byt lst description 0 0 0000 0011 000 1 0 8 bits scc3 1 0 0000 0110 000 1 0 8 bits smc2 2 0 0000 0101 000 1 0 8 bits smc1 3 0 0000 0001 001 0 0 2 bits scc1 4 0 0000 0101 101 0 0 6 bits smc1 5 0 0000 0000 110 1 0 skip 7 bytes 6 0 0000 0000 001 0 0 skip 2 bits 7 0 0000 0111 000 0 1 d grant bit 4 datasheet u .com
serial interface with time-slot assigner MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 23-30 freescale semiconductor 8. clear pdird[22]. configures l1txda(inout). 9. set podrd[22]. configures l1 txda to an open-drain output. 10. set pparc[19]. configures l1rclka. 11. clear pdirc[19]. configures l1rclka. 12. clear psorc[19]. configures l1rclka. 13. set pparc[1]. configures l1rqa . 14. set psorc[1]. configures l1rqa . 15. set pdirc[1]. configures l1rqa . 16. if the 1 gci data clock is required, set pparc bi t 0 and pdirc bit 0 and set psorc 0, which configures l1clkoa as an output. 17. configure scc1 for hdlc opera tion (to handle the lapd protocol of the d channel). configure smc1 for scit operation and config ure scc3 and smc2 as preferred. 18. si2gmr = 0x11. enable tdma ( one static tdm), stz for tdma. 19. si2cmdr is not used. 20. si2str does not need to be read. 21. enable scc1, scc3, smc1, and smc2. 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 24-1 chapter 24 cpm multiplexing the cpm multiplexing logic (cmx) connects the p hysical layer?utopia, mii/rmii, modem lines, tdm lines, and proprietary serial lines to the fccs, sccs, smcs, and usb. the cmx features the following two modes: ? in nmsi mode, the cmx allows a ll serial devices to be connected to their own set of individual pins. each serial device that connects to the exte rnal world in this way is said to connect to a nonmultiplexed serial interface (nmsi). in the nmsi configurat ion, the cmx provides a flexible clocking assignment for each fcc, s cc, smc, and usb from a bank of external clock pins and/or internal brgs. ? in tdm mode, the cmx performs the connection of the serial devices to the si for using the time-slot assigner (tsa). this allows any comb ination of fccs, sccs, and smcs to multiplex data on any of the tdm channels. the cmx connects the serial device only to the tsa in the si. the actual multiplexing of the td m is made by programming the si ram. in tdm mode, all other pins used in nmsi mode are available for other purposes. see chapter 23, ?serial interface with time-slot assigner . ? note the usb uses only the nmsi mode and is mutually exclusive with scc3 in nmsi mode; it is not legal to enab le both peripherals in nmsi mode at the same time. figure 24-1 shows a block diagram of the cmx. 4 datasheet u .com
cpm multiplexing MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 24-2 freescale semiconductor figure 24-1. cpm multiplexing logic (cmx) block diagram 24.1 features the nmsi mode supports the following: ? each fcc, scc, and smc can be programmed independently to work with a serial device?s own set of pins in a non-multiplexed manner. ? each fcc can be connected to its own mii/rmii (media-independent interface). ? fcc1 can also be connected to an 8-bit atm utopia level-2interface. ? fcc2 can also be connected to an 8-bit atm utopia level-2 interface. ? each scc can have its own set of modem control pins. ? each smc can have its own set of four pins. ? each fcc, scc, smc, and the usb can be driven from a bank of 14 clock pins or a bank of 8 brgs. time-slot assigner si x r clocks t clocks r sync t sync tdm a2, b2, c2 pins strobes register bus tdm a 2 , b2, c2 tx tx smc1 nonmultiplexed serial interface (nmsi) pins rx rx clocks cpm mux brgs to serials: atm register (cmxatmr) smc clock register (cmxsmr) scc/usb clock register (cmxscr) fcc clock register (cmxfcr) si 2 clock registers (cmxsi2cr) smc1 mux mii2/ fcc2 mux mii1/ fcc1 mux scc4 scc4 mux scc3/usb scc3 mux scc1 scc1 mux smc2 smc2 mux utopia8 mux usb mux rmii2/ rmii1/ utopia8 4 datasheet u .com
cpm multiplexing MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 24-3 note in fcc2 utopia master or slav e mode only, clk13, clk14, brg 5, brg6, and brg7 are available. 24.2 enabling connections to tsa or nmsi each serial device can be independently enabled to c onnect to the tsa or to dedicated external pins, as shown in figure 24-2 . each fcc can be connected to a dedicated mii/rmii, the three tdms, or to an 8-bit utopia level ii interface. each scc or smc can be connected to the three tdms or to its own set of pins. once connections are made to the tsa, the exact routing decisions ar e made in the si ram. figure 24-2. enabling connections to the tsa 24.3 nmsi configuration the cmx supports an nmsi mode for each of the fc cs, sccs, and smcs. each of these serial devices is connected independently either to the nmsi or to the tsa using th e clock route registers. the user should note, however, that nmsi pins are multiplexed with other functions at the parallel i/o lines. therefore, if a combination of tdm and nmsi channe ls are used, consult the pinout to determine which fcc, scc, and smc to connect and where to connect them. the clocks provided to the fccs, sc cs, smcs, and usb are derived from a bank of 8 internal brgs and 14 external clk pins; see figure 24-3 . there are two main advantages to the bank-of-clocks approach. first, a serial device is not forced to choose a serial device clock from a predefined pin or brg; this allows a flexible pinout-mapping strategy. se cond, a group of serial re ceivers and transmitters that needs the same clock rate can share the same pin. this configura tion leaves additional pins for other functions and minimizes potential skew betw een multiple clock sources. en en si ram time-slot assigners tdm a,b,c enable = 1 tdm b pins tdm c pins fcc1 fcc2 scc1 scc3 scc4 smc1 smc2 mii1/rmii1/utopia8/mphy fc1 = 0 mii2/rmii2/utopia8/mphy fc2 = 0 scc1 pins sc1 = 0 scc3 pins sc3 = 0 scc4 pins sc4 = 0 smc1 pins smc1 = 0 smc2 pins smc2 = 0 nmsi mode en tdm a pins 4 datasheet u .com
cpm multiplexing MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 24-4 freescale semiconductor figure 24-3. bank of clocks the eight brgs also make their clocks available to external logic, regardless of whether the brgs are being used by a serial device. noti ce that the brg outputs are multiple xed with other f unctions; thus, all brgo x pins may not always be available. chapter 45, ?parallel i/o ports,? shows the function multiplexing. there are two restrictions in the bank-of-clocks mapping: ? only 4 of the 14 sources can be co nnected to any given fcc, scc rece iver or transmitter or to the usb. ? the smc transmitter and receiv er share the same clock source when connected to the nmsi. tdma2 tx rx brg1 brg2 brg3 brg4 brgo1 brgo2 brgo3 brgo4 bank of clocks selection logic clk3 clk4 clk5 clk6 clk7 clk8 clk9 clk10 clk11 clk12 clk13 clk14 clk15 clk16 brg5 brg6 brg7 brg8 brgo5 brgo6 brgo7 brgo8 fcc1 tx (partially filled cross-switch logic programmed in the cmx registers.) rx fcc2 tx rx scc1 tx rx scc3 tx rx scc4 tx rx smc1 smc2 tdmb2 tx rx usb tdmc2 tx rx 4 datasheet u .com
cpm multiplexing MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 24-5 table 24-1 shows the clock source options for the serial controllers and tdm channels. note after a clock source is selected, the cloc k is given an inte rnal name. for the fccs and sccs, the names are rclk x and tclk x ; for smcs, the name is simply smclk x ; for usb the name is usbclk. these internal names specify the clocks sent to the fccs, sccs, smcs, or usb. the internal names for the fccs, sccs, or smcs are used only in nmsi. these names do not correspond to any MPC8555E pins. 24.4 cmx registers the following sections de scribe the cmx registers. 24.4.1 cmx utopia address register (cmxuar) the cmx utopia address regi ster (cmxuar), shown in figure 24-4 , defines the conne ction of fcc1 and fcc2 utopia multiple-phy addr esses to the 14 utopia address pi ns of the MPC8555E; it also defines the connection of a brg to the fccs when an in ternal rate feature is us ed. this enables the user to implement a multiple-phy utopia master or slave on both fcc1 and fcc2 using only 14 pins. the table 24-1. clock source options clock clk brg 34567891011121314151612345678 scc1 rx vv vv vvvv scc1 tx vv vv vvvv scc3 rx vvvv vvvv scc3 tx/usb vvvv vvvv scc4 rx vvvv vvvv scc4 tx vvvv vvvv fcc1 rx vvvv vvvv fcc1 tx vvvv vvvv fcc2 rx vvvv vvvv fcc2 tx vvvv vvvv tdma2 rx v v tdma2 tx v v tdmb2 rx v v tdmb2 tx v v tdmc2 rx v v tdmc2 tx v v smc1 rx v v v v smc1 tx v v v v smc2 rx v v v v smc2 tx v v v v 4 datasheet u .com
cpm multiplexing MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 24-6 freescale semiconductor user chooses the number of phys to use with each interface and the number of address lines needed for each fcc. table 24-2 describes cmxuar fields. figure 24-5 describes the interconnection be tween the receive external multi-phy bus and the internal fcc1 and fcc2 receive multi-phy a ddresses. the same diagram applie s to the transmit multi-phy bus using different dedicate d parallel i/o pins. 0 1 2 3 4 5 7 8 9 10 11 12 15 field sad0 sad1 sad2 sad3 sad4 ? f1irb f2irb ? reset 0000_0000_0000_0000 r/w r/w offset 0x9_1b0e figure 24-4. cmx utopia address register (cmxuar) table 24-2. cmxuar field descriptions bits name description 0?4 sad x slave address input pin x connection. see note that the address indexes are relative to fcc1; see figure 24-5 . 0 reserved. 1 this address input pin is used by fcc1 in slave mode. 5?7 ? reserved, should be cleared. 8?9 f1irb fcc1 internal rate brg selecti on. selects the brg to be connected to fcc1 for internal rate operation. used by the atm controller; see section 41.2.1.5, ?transmit external rate and internal rate modes.? 00 fcc1 internal rate clock is brg5 01 fcc1 internal rate clock is brg6 10 fcc1 internal rate clock is brg7 11 fcc1 internal rate clock is brg8 10?11 f2irb fcc2 internal rate brg selection. selects the br g to be connected to fcc2 for internal rate operation. used by the atm controller; see section 41.2.1.5, ?transmit external rate and internal rate modes.? 00 fcc2 internal rate clock is brg5 01 fcc2 internal rate clock is brg6 10 fcc2 internal rate clock is brg7 11 fcc2 internal rate clock is brg8 12?15 ? reserved, should be cleared. 4 datasheet u .com
cpm multiplexing MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 24-7 figure 24-5. multi-phy receive address multiplexing 1 0 sad0 1 0 sad1 1 0 sad2 1 0 sad3 1 0 sad4 fcc1 rx master address msb lsb fcc1 rx slave address msb lsb fcc2 rx slave address msb lsb fcc2 rx master address msb lsb fcc1-rxaddr[4] gnd gnd gnd gnd gnd fcc1 fcc2 pio pd18 pio pc14 fcc1-rxaddr[3] fcc1-rxaddr[2] fcc1-rxaddr[1] fcc1-rxaddr[0] fcc2-rxaddr[0] (master) pio pd29 pio pc6 pio pc12 fcc2-rxaddr[0] (slave) fcc2-rxaddr[ 4] (master) fcc2-rxaddr[ 3] (master) fcc2-rxaddr[ 2] (master) fcc2-rxaddr[ 1] (master) fcc2-rxaddr[1] (slave) pio pio pio pio pio pc26 pc20 pc10 pd23 pc16 pio pc12 4 datasheet u .com
cpm multiplexing MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 24-8 freescale semiconductor 24.4.2 cmx si2 clock route register (cmxsi2cr) the cmx si2 clock route regi ster (cmxsi2cr), seen in figure 24-6 , defines the connection of si2 to the clock sources that can be i nput from the bank of clocks. table 24-3 describes cmxsi2cr fields. 24.4.3 cmx fcc clock route register (cmxfcr) the cmx fcc clock route regi ster (cmxfcr), shown in figure 24-7 , defines the connect ion of the fccs to the tsa and to the clock s ources from the bank of clocks. 01234567 field rta2cs rtb2cs rtc2cs ? tta2cs ttb2cs ttc2cs ? reset 0000_0000 r/w r/w offset 0x9_1b02 figure 24-6. cmx si2 clock route register (cmxsi2cr) table 24-3. cmxsi2cr field descriptions bits name description 0 rta2cs receive tdm a2 clock source 0 tdm a2 receive clock is clk13 1 tdm a2 receive clock is clk5 1 rtb2cs receive tdm b2 clock source 0 tdm c2 receive clock is clk3 1 tdm c2 receive clock is clk9 2 rtc2cs receive tdm c2 clock source 0 tdm c2 receive clock is clk5 1 tdm c2 receive clock is clk13 3 ? reserved, should be cleared. 4 tta2cs transmit tdm a2 clock source 0 tdm a2 transmit clock is clk14 1 tdm a2 transmit clock is clk6 5 ttb2cs transmit tdm b2 clock source 0 tdm b2 transmit clock is clk4 1 tdm b2 transmit clock is clk10 6 ttc2cs transmit tdm c2 clock source 0 tdm c2 transmit clock is clk6 1 tdm c2 transmit clock is clk14 7 ? reserved, should be cleared. 4 datasheet u .com
cpm multiplexing MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 24-9 table 24-4 describes cmxfcr fields. 012 45 78910 1213 15 field ? fc1 rf1cs tf1cs ? fc2 rf2cs tf2cs reset 0000_0000_0000_0000 r/w r/w offset 0x9_1b04 16 31 field ? reset 0000_0000_0000_0000 r/w r/w offset 0x9_1b06 figure 24-7. cmx fcc clock route register (cmxfcr) table 24-4. cmxfcr field descriptions bits name description 0 ? reserved, should be cleared 1 fc1 defines the fcc1 connection 0 fcc1 is not connected to the tsa and is either connected directly to the nmsix pins or is not used. the choice of general-purpose i/o port pins versus fccn pins is made in the parallel i/o control register. 1 fcc1 is connected to the tsa of the sis. th e nmsix pins are available for other purposes. 2?4 rf1cs receive fcc1 clock source (nmsi mode). ignor ed if fcc1 is connected to the tsa (fc1 = 1). 000 fcc1 receive clock is brg5 001 fcc1 receive clock is brg6 010 fcc1 receive clock is brg7 011 fcc1 receive clock is brg8 100 fcc1 receive clock is clk9 101 fcc1 receive clock is clk10 110 fcc1 receive clock is clk11 111 fcc1 receive clock is clk12 5?7 tf1cs transmit fcc1 clock source (nmsi mode). ig nored if fcc1 is connected to the tsa (fc1 = 1). 000 fcc1 transmit clock is brg5 001 fcc1 transmit clock is brg6 010 fcc1 transmit clock is brg7 011 fcc1 transmit clock is brg8 100 fcc1 transmit clock is clk9 101 fcc1 transmit clock is clk10 110 fcc1 transmit clock is clk11 111 fcc1 transmit clock is clk12 8 ? reserved, should be cleared 9 fc2 defines the fcc2 connection 0 fcc2 is not connected to the tsa and is either connec ted directly to the nmsix pins or is not used. the choice of general-purpose i/o port pins versus fccn pins is made in the parallel i/o control register. 1 fcc2 is connected to the tsa of the sis. th e nmsix pins are available for other purposes. 4 datasheet u .com
cpm multiplexing MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 24-10 freescale semiconductor 24.4.4 cmx scc clock route register (cmxscr) the cmx scc clock route regi ster (cmxscr), seen in figure 24-8 , defines the connection of the sccs to the tsa and to the clock sources from the bank of clocks. this regi ster also enables the use of the external grant pin. 10?12 rf2cs receive fcc2 clock source (nmsi mode). ig nored if fcc2 is connected to the tsa (fc2 = 1) 000 fcc2 receive clock is brg5 001 fcc2 receive clock is brg6 010 fcc2 receive clock is brg7 011 fcc2 receive clock is brg8 100 fcc2 receive clock is clk13 101 fcc2 receive clock is clk14 110 fcc2 receive clock is clk15 111 fcc2 receive clock is clk16 13?15 tf2cs transmit fcc2 clock source (nmsi mode). ig nored if fcc2 is connected to the tsa (fc2 = 1) 000 fcc2 transmit clock is brg5 001 fcc2 transmit clock is brg6 010 fcc2 transmit clock is brg7 011 fcc2 transmit clock is brg8 100 fcc2 transmit clock is clk13 101 fcc2 transmit clock is clk14 110 fcc2 transmit clock is clk15 111 fcc2 transmit clock is clk16 16?31 ? reserved, should be cleared 0124578 15 field gr1 sc1 rs1cs ts1cs ? reset 0000_0000_0000_0000 r/w r/w offset 0x9_1b08 16 17 18 20 21 23 24 25 26 28 29 31 field gr3 sc3 rs3cs ts3cs gr4 sc4 rs4cs ts4cs reset 0000_0000_0000_0000 r/w r/w offset 0x9_1b0a figure 24-8. cmx scc clock route register (cmxscr) table 24-4. cmxfcr field descriptions (continued) bits name description 4 datasheet u .com
cpm multiplexing MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 24-11 table 24-5 describes cmxscr fields. table 24-5. cmxscr field descriptions bits name description 0 gr1 grant support of scc1 0 scc1 transmitter does not support the grant mechanism. the grant is always asserted internally. 1 scc1 transmitter supports the grant mechanism as det ermined by the gmx bit of a serial device channel. 1 sc1 scc1 connection 0 scc1 is not connected to the tsa and is either connec ted directly to the nmsix pins or is not used. the choice of general-purpose i/o port pins versus sccn pins is made in the parallel i/o control register. 1 scc1 is connected to tsa of the sis. the nmsix pins are available for other purposes. 2?4 rs1cs receive scc1 clock source (nmsi mode). i gnored if scc1 is connected to the tsa (sc1 = 1) 000 scc1 receive clock is brg1 001 scc1 receive clock is brg2 010 scc1 receive clock is brg3 011 scc1 receive clock is brg4 100 scc1 receive clock is clk11 101 scc1 receive clock is clk12 110 scc1 receive clock is clk3 111 scc1 receive clock is clk4 5?7 ts1cs transmit scc1 clock source (nmsi mode). i gnored if scc1 is connected to the tsa (sc1 = 1) 000 scc1 transmit clock is brg1 001 scc1 transmit clock is brg2 010 scc1 transmit clock is brg3 011 scc1 transmit clock is brg4 100 scc1 transmit clock is clk11 101 scc1 transmit clock is clk12 110 scc1 transmit clock is clk3 111 scc1 transmit clock is clk4 8?15 ? reserved, should be cleared 16 gr3 grant support of scc3 0 scc3 transmitter does not support the grant mechanism. the grant is always asserted internally. 1 scc3 transmitter supports the grant mechanism as det ermined by the gmx bit of a serial device channel. 17 sc3 scc3 connection 0 scc3 is not connected to the tsa and is either connec ted directly to the nmsix pins or is not used. the choice of general-purpose i/o port pins versus sccn pins is made in the parallel i/o control register. 1 scc3 is connected to tsa of the sis. the nmsix pins are available for other purposes. 18?20 rs3cs receive scc3 clock source (nmsi mode). igno red if scc3 is connected to the tsa (sc3 = 1). 000 scc3 receive clock is brg1 001 scc3 receive clock is brg2 010 scc3 receive clock is brg3 011 scc3 receive clock is brg4 100 scc3 receive clock is clk5 101 scc3 receive clock is clk6 110 scc3 receive clock is clk7 111 scc3 receive clock is clk8 4 datasheet u .com
cpm multiplexing MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 24-12 freescale semiconductor 21?23 ts3cs transmit scc3 clock source (nmsi mode). used as the usb clock when scc3 is disabled or connected to the tsa (sc3 = 1) 000 scc3 transmit/usb clock is brg1 001 scc3 transmit/usb clock is brg2 010 scc3 transmit/usb clock is brg3 011 scc3 transmit/usb clock is brg4 100 scc3 transmit/usb clock is clk5 101 scc3 transmit/usb clock is clk6 110 scc3 transmit/usb clock is clk7 111 scc3 transmit/usb clock is clk8 24 gr4 grant support of scc4 0 scc4 transmitter does not support the grant mechanism. the grant is always asserted internally. 1 scc4 transmitter supports the grant mechanism as det ermined by the gmx bit of a serial device channel. 25 sc4 scc4 connection 0 scc4 is not connected to the tsa and is either connec ted directly to the nmsix pins or is not used. the choice of general-purpose i/o port pins versus sccn pins is made in the parallel i/o control register. 1 scc4 is connected to tsa of the sis. the nmsix pins are available for other purposes. 26?28 rs4cs receive scc4 clock source (nmsi mode). i gnored if scc4 is connected to the tsa (sc4 = 1) 000 scc4 receive clock is brg1 001 scc4 receive clock is brg2 010 scc4 receive clock is brg3 011 scc4 receive clock is brg4 100 scc4 receive clock is clk5 101 scc4 receive clock is clk6 110 scc4 receive clock is clk7 111 scc4 receive clock is clk8 29?31 ts4cs transmit scc4 clock source (nmsi mode). ignored if scc4 is connected to the tsa (sc4 = 1) 000 scc4 transmit clock is brg1 001 scc4 transmit clock is brg2 010 scc4 transmit clock is brg3 011 scc4 transmit clock is brg4 100 scc4 transmit clock is clk5 101 scc4 transmit clock is clk6 110 scc4 transmit clock is clk7 111 scc4 transmit clock is clk8 table 24-5. cmxscr field descriptions (continued) bits name description 4 datasheet u .com
cpm multiplexing MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 24-13 24.4.5 cmx smc clock route register (cmxsmr) the cmx smc clock route register (cmxsmr), shown in figure 24-9 , defines the connection of the smcs to the tsa and to the clock sources from the bank of clocks. table 24-6 describes cmxsmr fields. 01234567 field smc1 ? smc1cs smc2 ? smc2cs reset 0000_0000 r/w r/w offset 0x9_1b0c figure 24-9. cmx smc clock route register (cmxsmr) table 24-6. cmxsmr field descriptions bits name description 0 smc1 smc1 connection 0 smc1 is not connected to the tsa and is either co nnected directly to the nmsix pins or is not used. the choice of general-purpose i/o port pins versus smcn pins is made in the parallel i/o control register. 1 smc1 is connected to the tsa of the sis. th e nmsix pins are available for other purposes. 1 ? reserved, should be cleared 2?3 smc1cs smc1 clock source (nmsi mode). smc1 can take it s clocks from one of the two brgs or one of two pins from the bank of clocks. however, the smc1 transmi t and receive clocks must be the same when it is connected to the nmsi. 00 smc1 transmit and receive clocks are brg1 01 smc1 transmit and receive clocks are brg7 10 smc1 transmit and receive clocks are clk7 11 smc1 transmit and receive clocks are clk9 4 smc2 smc2 connection 0 smc2 is not connected to the tsa and is either co nnected directly to the nmsix pins or is not used. the choice of general-purpose i/o port pins versus smcn pins is made in the parallel i/o control register. 1 smc2 is connected to the tsa of the sis. th e nmsix pins are available for other purposes. 5 ? reserved, should be cleared 6?7 smc2cs smc2 clock source (nmsi mode). smc2 can take its clocks from one of the eight brgs or one of eight pins from the bank of clocks. however, the smc2 tran smit and receive clocks must be the same when it is connected to the nmsi. 00 smc2 transmit and receive clocks are brg2 01 smc2 transmit and receive clocks are brg8 10 smc2 transmit and receive clocks are clk4 11 smc2 transmit and receive clocks are clk15 4 datasheet u .com
cpm multiplexing MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 24-14 freescale semiconductor 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 25-1 chapter 25 baud-rate generators (brgs) the cpm contains eight independent, identical baud-rate generators (brg s) that can be used with the fccs, sccs, and smcs. the clocks produced by the brgs are sent to the bank-of -clocks selection logic, where they can be routed to the controllers. in addi tion, the output of a brg can be routed to a pin to be used externally. the following is a list of the main features of the brgs in the cpm: ? eight independent and identical brgs ? on-the-fly changes allowed ? each brg can be routed to one or more fccs, sccs, or smcs. ? a 16 divider option allows slow baud rates at high system frequencies. ? each brg contains an autobaud support option. ? each brg output can be routed to a pin (brgo n ). figure 25-1 shows a brg. figure 25-1. baud-rate generator (brg) block diagram each brg clock source can be brgclk or a choice of two external clocks (selected in brgc n [extc]). the brgclk is an internal signal generated in th e MPC8555E clock synthesize r specifically for the brgs, the spi, and the i 2 c internal brg. alternatively, external clock pins can be configured as clock sources. the external source option allows flexible baud-rate frequency generation, independent of the system frequency. ad ditionally, the external source option allows a single external frequency to be the clk pin x clock source mux divide by 1 or 16 prescaler 12-bit counter 1?4,096 div 16 cd[0?11] brgo n clock brgclk extc at b autobaud control rxd n to pin and/or bank of clocks brg n clk pin y 4 datasheet u .com
baud-rate generators (brgs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 25-2 freescale semiconductor source for multiple brgs. the external source signals are not synchronized internally before being used by the brg. the brg provides a divi de-by-16 option (brgc n [div16]) and a 12-bit prescaler (brgc n [cd]) to divide the source clock frequency. the combined source-clock divide factor can be ch anged on-the-fly; however, two changes should not occu r within two source clock periods. the prescaler output is sent intern ally to the bank of clocks and ca n also be output externally on brgo n through the parallel i/o ports. if th e brg divides the clock by an even value, the transitions of brgo n always occur on the falling edge of the source clock. if the divide factor is odd, the transitions alternate between the falling and rising edges of the source cl ock. additionally, the output of the brg can be sent to the autobaud control block. 25.1 system clock control register (sccr) the system clock control re gister (sccr), shown in figure 25-2 , is memory-mapped into the MPC8555E internal space. the sccr defines the brgclk frequency to be supplied to the brgs. table 25-1 describes sccr fields. 0 15 field ? reset ? r/w r/w offset 0x9_0c80 16 29 30 31 field ? dfbrg reset ? 01 r/w r/w offset 0x9_0c82 figure 25-2. system clock control register (sccr) table 25-1. sccr field descriptions bits name defaults description por hard reset 0?29 ? reserved 30?31 dfbrg 01 unaffected division factor of brg_clk relative to vco_out (which is twice the cpm clock). defines the brg_clk frequency. changing the value does not result in a loss of lock condition. 00 divide by 4 01 divide by 16 (normal operation) 10 divide by 64 11 divide by 256 4 datasheet u .com
baud-rate generators (brgs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 25-3 25.2 brg configurati on registers 1?8 (brgc n ) the brg configuration registers (brgc n ) are shown in figure 25-3 . a reset disables the brg and drives the brgo output clock high. the brgc ca n be written at any time with no need to disable the sccs or external devices that are connected to brgo. configuration changes o ccur at the end of the next brg clock cycle (no spikes occur on the brgo output cloc k). brgc can be changed on-the-fly; however, two changes should not occur within a time equal to two source clock periods. note since the MPC8555E does not cont ain scc2, atb cannot function on brg2. table 25-2 describes the brgc n fields. 0 13 14 15 field ? rst en reset 0000_0000_0000_0000 r/w r/w offset 0x9_19f0 (brgc1), 0x9_19f4 (brgc2), 0x9_19f8 (brgc3), 0x9_19fc (brgc4), 0x9_15f0 (brgc5), 0x9_15f4 (brgc6), 0x9_15f8 (brgc7), 0x9_15fc (brgc8) 16 17 18 19 30 31 field extc atb cd div16 reset 0000_0000_0000_0000 r/w r/w offset 0x9_19f2 (brgc1), 0x9_19f6 (brgc2 ), 0x9_19fa (brgc3), 0x9_19fe (brgc4), 0x9_15f2 (brgc5), 0x9_15f6 (brgc6), 0x9_15fa (brgc7), 0x9_15fe (brgc8) figure 25-3. baud-rate generator configuration registers (brgc n ) table 25-2. brgc n field descriptions bits name description 0?13 ? reserved, should be cleared. 14 rst reset brg. performs a software reset of the brg identi cal to that of an external reset. a reset disables the brg and drives brgo high. this is externally visible only if brgo is connected to the corresponding parallel i/o pin. 0 enable the brg. 1 reset the brg (software reset). 15 en enable brg count. used to dynamically stop the brg from counting?useful for low-power modes. 0 stop all clocks to the brg. 1 enable clocks to the brg. 4 datasheet u .com
baud-rate generators (brgs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 25-4 freescale semiconductor table 25-3 shows the possible external clock sources for the brgs. 16?17 extc external clock source. selects the brg input clock. see table 25-3 . 00 the brg input clock comes from the brgclk (i nternal clock generated fr om the cpm clock); see section 25.1, ?system clock control register (sccr).? 01 if brg1, 2, 5, 6: the brg input clock comes from the clk3 pin. if brg3, 4, 7, 8: the brg input clock comes from the clk9 pin. 10 if brg1, 2, 5, 6: the brg input clock comes from the clk5 pin. if brg3, 4, 7, 8: the brg input clock comes from the clk15 pin. 11 reserved 18 atb autobaud. selects autobaud operation of the brg on the corresponding rxd. atb must remain zero until the scc receives the 3 rx clocks. then the user must set atb to obtain the correct baud rate. after the baud rate is obtained and locked, it is indicated by setting ab in the uart event register. 0 normal operation of the brg 1 when rxd goes low, the brg determines the length of the start bit and synchronizes the brg to the actual baud rate. 19?30 cd clock divider. cd presets an internal 12-bit counte r that is decremented at the div16 output rate. when the counter reaches zero, it is reloaded with cd. cd = 0x fff produces the minimum clock rate for bgro (divide by 4,096); cd = 0x000 produces the maximum rate (divide by 1). when dividing by an odd number, the counter ensures a 50% duty cycle by asserting the terminal count once on clock low and next on clock high. the terminal count signals counter expiration and toggles the clock. see section 25.4, ?uart baud rate examples.? 31 div16 divide-by-16. selects a divide-by-1 or divide-by-16 prescaler before reaching the clock divider. see section 25.4, ?uart baud rate examples.? 0 divide by 1 1 divide by 16 table 25-3. brg external clock source options brg clk 1234567891011121314151617181920 brg1 v v brg2 v v brg3 v v brg4 v v brg5 v v brg6 v v brg7 v v brg8 v v table 25-2. brgc n field descriptions (continued) bits name description 4 datasheet u .com
baud-rate generators (brgs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 25-5 25.3 autobaud operation on a uart during the autobaud process, a uart deduces the baud rate of its receiv ed character stream by examining the received pattern and its timing. a built-in autobaud control function automatically measures the length of a start bit and modifies the baud rate accordingly. if the autobaud bit brgc n [atb] is set, the autobaud control function starts searching for a low level on the corresponding rxd n input, which it assumes marks the beginni ng of a start bit, and begins counting the start bit length. during this time, the brg output clock toggles for 16 brg cl ock cycles at the brg source clock rate a nd stops with brgo n in the low state. when rxd n goes high again, the autobaud control block rewrites brgc n [cd, div16] to the divide ratio found, which at high baud rates may not be exactly the final rate desired (for example, 56,600 may result rather than 57,600). an interrupt can be enabled in the uart scc event register to report that the autobaud controller rewrote brgc n. the interrupt handler can then adjust brgc n [cd, div16] (see table 25-4 ) for accuracy before the first ch aracter is fully received, ensuri ng that the uart recognizes all characters. after a full character is received, the software can verify that the character matches a predefined value (such as ?a? or ?a?). software should then check for other characters (such as ?t ? or ?t?) and program the preferred parity mode in the uart?s pr otocol-specific mode register (psmr). note that the scc associated with this brg must be programmed to uart mode and select the 16 option for tdcr and rdcr in the ge neral scc mode register low. input frequencies such as 1.8432, 3.68, 7.36, and 14.72 mhz should be used. the scc performing the autobaud function must be connected to that scc?s brg; that is, scc3 mu st be clocked by brg3, and so on. also, to detect an autobaud lock and generate an inte rrupt, the scc must receive 3 full rx clocks from the brg before the autobaud process be gins. to do this, first clear brgc n [atb] and enable the brg rx clock to the highest frequency. th en, immediately before the autoba ud process starts (after device initialization), set brgc n [atb]. 25.4 uart baud rate examples for synchronous communication using the internal brg, the brgo must not exceed the brg input clock divided by 2. therefore, with a brg input clock of 66 mhz (generated using an external clock source, refer to brgc n [extc]), the maximum brgo rate is 33 mhz. program the uart to 16 oversampling when using the scc as a uart. rates of 8 and 32 are also available. assuming 16 oversampling is chosen in the uart, the maximum data rate is 66 mhz 16 = 4.125 mbps. keeping the above in mind, use the following formula to calcula te the bit rate based on a particul ar brg configuration for a uart: async baud rate brgclk or external clock source prescale divider () clock divider 1 + () sampling rate () ------------------------------------------------------------------------------------------------------------------------------- --------------------------- - = async baud rate brgcx[extc] brgcx[div16] () brgcx[cd] 1 + () gsmrx_l[xdcr] () ------------------------------------------------------------------------------------------------------------------------------- ----------------------------- = 4 datasheet u .com
baud-rate generators (brgs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 25-6 freescale semiconductor table 25-4 lists typical bit rates of asynchronous communication. note that here the internal clock rate is assumed to be 16 the baud rate; that is, gsmr x _l[tdcr] = gsmr x _l[rdcr] = 0b10. for synchronous communication, the inte rnal clock is identical to the ba ud-rate output. to get the preferred rate, select the system cl ock according to the following: for example, to get a rate of 64 kbps, the system clock can be 24.96 mhz, brgc n [div16] = 0, and brgc n [cd] = 389. table 25-4. typical baud rates for asynchronous communication baud rate using a 66-mhz brg input clock brgc n [div16] brgc n [cd] actual frequency (hz) 75 1 3436 75.01 150 1 1718 149.98 300 1 858 300.13 600 1 429 599.56 1200 0 3436 1200.2 2400 0 1718 2399.7 4800 0 858 4802.1 9600 0 429 9593.0 19,200 0 214 19,186 38,400 0 106 38,551 57,600 0 71 57,292 115,200 0 35 114,583 460,000 0 8 458,333 sync baud rate brgclk or external clock source (prescale divider) clock divider 1 + () ------------------------------------------------------------------------------------------------------- - = sync baud rate brgcx[extc] brgcx[div16] () brgcx[cd] 1 + () -------------------------------------------------------------------------------------------------- = 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 26-1 chapter 26 cpm timers the cpm includes four identical 16-bi t general-purpose timers or two 32- bit timers. each general-purpose timer consists of a timer mode register (tmr), a timer capture re gister (tcr), a timer counter (tcn), a timer reference register (trr), a timer event regist er (ter), and a timer globa l configuration register (tgcr). the tmrs contain the prescal ar values programmed by the user. figure 26-1 shows the timer block diagram. figure 26-1. time r block diagram pin assignments for tin x , tgate x , and tout x are described in section 45.5, ?port tables.? 26.1 features the key features of the cpm timers include the following: ? the maximum input clock is the internal cpm cl ock which is the core complex bus (ccb) clock divided by 3. timer capture detection timer event register timer mode register mode bits prescalar timer counter (tcn) timer capture register timer reference register divider clock ter1 tmr1 tcn1 trr1 tcr1 bus tin1 tout1 timer1 timer2 timer3 timer4 global configuration register tgate1 tgate2 tgcr tin2 tin3 tin4 tout2 tout3 tout4 clock clock generator 4 datasheet u .com
cpm timers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 26-2 freescale semiconductor ? maximum period of 2.6 seconds (at 100 mhz) ? 10-ns resolution (at 100 mhz) ? programmable sources for the clock input ? input capture capability ? output compare with programmable mode for the output pin ? two timers cascade internally or externally to form a 32-bit timer ? free run and restart modes ? functional compatibility with ti mers on the mc68360, mpc860, and mpc8260 26.2 general-purpose timer units the clock input to the prescaler can be se lected from the following three sources: ? internal cpm clock (ccb/3) ? internal cpm clock divided by 16 (ccb/48) ? corresponding tin x , programmed in the parallel port registers the internal cpm clock is generated in the cpm clock synthesizer and defa ults to the ccb clock frequency divided by 3. the user can either choose that frequency or the frequency divided by 16 as the input to the prescaler of each timer. alternatively, the user may prefer tin x to be the cl ock source. tin x is internally synchronized to the internal clock. if the user has chosen to in ternally cascade two 16-bit timers to a 32-bit timer, a timer can use the clock generated by the output of another timer. the clock input source is selected by the corres ponding tmr[iclk] bits. the prescalar is programmed to divide the clock input by values from 1 to 256 and the output of the prescalar is used as an input to the 16-bit counter. the best resolution of the timer is one clock cycle (10 ns at 100 mhz). the maximum period (when the reference value is all ones) is 268,435,456 cycles (2.6 seconds at 100 mhz). each timer can be configured to count until a referen ce is reached and then either begin a new time count immediately or continue to run. the frr bit of the corresponding tmr selects each mode. upon reaching the reference value, the corresponding ter bit is set and an interrupt is issued if tmr[ori] = 1. the timers can output a signal on the timer outputs (tout 1 ?tout 4 ) when the referenc e value is reached (selected by the corresponding tmr[om]). this signal can be an active-low pul se or a toggle of the current output. the output can also be connected internally to the input of another timer, resulting in a 32-bit timer. in addition, each timer has a 16-bit tc r used to latch the value of the counter when a defined transition of tin1, tin2, tin3, or tin4 is sensed by the corr esponding input capture edge detector. the type of transition triggering the capture is selected by the corresponding tm r[ce] bits. upon a capture or reference event, the corresponding ter bit is set and a maskable interrupt request is issued to the interrupt controller. the timers may be ga ted/restarted by an external ga te signal. there are two gate signals?tgate1 controls timer 1 and/or 2 and tgate2 controls timer 3 and/or 4. normal gate mode enables the count on a fa lling edge of tgate x and disables the count on the rising edge of tgate x . this mode allows the timer to count condi tionally, based on the state of tgate x . 4 datasheet u .com
cpm timers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 26-3 the restart gate mode performs the same function as normal mode, except it also resets the counter on the falling edge of tgate x . this mode has applications in pulse in terval measurement and bus monitoring as follows: ? pulse measurement?the restart gate mode can measure a low tgate x . the rising edge of tgate x completes the measur ement and if tgate x is connected externally to tin x , it causes the timer to capture the count value a nd generate a rising-edge interrupt. ? bus monitoring?the restart gate mode can detect a signal that is abnormally stuck low. the bus signal should be connected to tgate x . the timer count is reset on the falling edge of the bus signal and if the bus signal does not go high again within the number of user-defined clocks, an interrupt can be generated. the gate function is enabled in the tmr; the ga te operating mode is selected in the tgcr. note tgate x is internally synchronized to the internal cpm clock. after the falling edge of tgate x is recognized, the counter begins counting after one internal cpm clock cycle when wo rking with the internal clock. 26.2.1 cascaded mode in this mode, two 16-bit timers can be internally cascaded to form a 32-bit counter. timer 1 may be internally cascaded to timer 2, and timer 3 can be internally cascaded to timer 4. because the decision to cascade timers is made independent ly, the user can select two 16-bit timers or one 32- bit timer. tgcr is used to put the timers into cascaded mode, as shown in figure 26-2 . figure 26-2. timer cascaded mode block diagram if tgcr[cas] = 1, the two timers function as a 32-bit timer with a 32-bit trr, tcr, and tcn. in this case, tmr1 and/or tmr3 are igno red, and the modes are defined usi ng tmr2 and/or tmr4. the capture is controlled from tin2 or tin4 and the interrupts are generated fr om ter2 or ter4. in cascaded mode, the combined trr, tcr, and tcn must be referenced with 32-bit bus cycles. 26.2.2 timer global configurat ion registers (tgcr1, tgcr2) the timer global configuration regist ers (tgcr1 and tgcr2), shown in figure 26-3 and figure 26-4 , contain configuration parameters used by the timers. these register s allow simultaneous starting and stopping of a pair of timers (1 and 2 or 3 and 4) if one bus cycle is used. timer1 timer2 timer3 timer4 capture capture clock clock trr, tcr, tcn connect ed to port d[16:31] trr, tcr, tcn connected to port d[0:15] trr, tcr, tcn connected to port d[0:15] t rr, tcr, tcn connected to port d[16:31] 4 datasheet u .com
cpm timers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 26-4 freescale semiconductor table 26-1 describes tgcr1 fields. 01234 5 67 field cas2 ? stp2 rst2 gm1 ? stp1 rst1 reset 0000_0000 r/w r/w offset 0x9_0d80 figure 26-3. timer global config uration register 1 (tgcr1) table 26-1. tgcr1 field descriptions bits name description 0 cas2 cascade timers 0 normal operation 1 timers 1 and 2 cascade to form a 32-bit timer. 1 ? reserved, should be cleared. 2 stp 2 stop timer 0 normal operation 1 reduce power consumption of the timer. this bit stops all clocks to the timer, except the clock from the internal bus interface, which allows the user to read and write timer registers. the clocks to the timer remain stopped until the user clears this bit or a hardware reset occurs. 3 rst2 reset timer 0 reset the corresponding time r (a software reset is iden tical to an external reset). 1 enable the corresponding timer if the stp bit is cleared. 4 gm1 gate mode for tgate1 . this bit is valid only if the gate function is enabled in tmr1 or tmr2. 0 restart gate mode. tgate1 is used to enable/disable count. a falling tgate1 enables and restarts the count and a rising edge of tgate1 disables the count. 1 normal gate mode. this mode is the same as 0, except the falling edge of tgate1 does not restart the count value in tcn. 5 ? reserved, should be cleared. 6 stp1 stop timer 0 normal operation 1 reduce power consumption of the timer. this bit stops all clocks to the timer, except the clock from the internal bus interface, which allows the user to read and write timer registers. the clocks to the timer remain stopped until the user clears this bit or a hardware reset occurs. 7 rst1 reset timer 0 reset the corresponding time r (a software reset is iden tical to an external reset). 1 enable the corresponding timer if stp = 0. 4 datasheet u .com
cpm timers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 26-5 the tgcr2 register is shown in figure 26-4 . table 26-2 describes tgcr2 fields. 26.2.3 timer mode registers (tmr1?tmr4) the four timer mode register s (tmr1?tmr4) are shown in figure 26-5 . erratic behavior may occur if tg cr1 and tgcr2 are not initialized before the tmrs. only tgcr[rst] can be modified at any time. 01 234 567 field cas4 ? stp4 rst4 gm2 ? stp3 rst3 reset 0000_0000 r/w r/w offset 0x9_0d84 figure 26-4. timer global config uration register 2 (tgcr2) table 26-2. tgcr2 field descriptions bit name description 0 cas4 cascade timers 0 normal operation 1 timers 3 and 4 cascades to form a 32-bit timer. 1 ? reserved, should be cleared. 2 stp 4 stop timer 0 normal operation 1 reduce power consumption of the timer. this bit stops all clocks to the timer, except the clock from the internal bus interface, which allows the user to read and write timer registers. the clocks to the timer remain stopped until the user clears this bit or a hardware reset occurs. 3 rst4 reset timer 0 reset the corresponding time r (a software reset is iden tical to an external reset). 1 enable the corresponding timer if the stp bit is cleared. 4 gm2 gate mode for tgate2 . this bit is valid only if the gate function is enabled in tmr3 or tmr4. 0 restart gate mode. tgate2 is used to enable/disable the count. the falling edge of tgate2 enables and restarts the count and the rising edge of tgate2 disables the count. 1 normal gate mode. this mode is the same as 0, except the falling edge of tgate2 does not restart the count value in tcn. 5 ? reserved, should be cleared. 6 stp3 stop timer 0 normal operation 1 reduce power consumption of the timer. this bit stops all clocks to the timer, however it is possible to read the values while the clock is stopped. the clocks to the timer remain stopped until the user clears this bit or a hardware reset occurs. 7 rst3 reset timer 0 reset the corresponding time r (a software reset is iden tical to an external reset). 1 enable the corresponding timer if stp = 0. 4 datasheet u .com
cpm timers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 26-6 freescale semiconductor table 26-3 describes tmr1?tmr4 register fields. 0 7 8 9 10 11 12 13 14 15 field ps ce om ori frr iclk ge reset 0000_0000_0000_0000 r/w r/w offset 0x9_0d90 (tmr1); 0x9_0d92 (tmr 2); 0x9_0da0 (tmr3); 0x9_0da2 (tmr4) figure 26-5. timer mode registers (tmr1?tmr4) table 26-3. tmr1?tmr4 field descriptions bits name description 0?7 ps prescalar value. the prescalar is programmed to divide the clock input by values from 1 to 256. the value 00000000 divides the clock by 1 and 1111_1111 divides the clock by 256. 8?9 ce capture edge and enable interrupt 00 disable interrupt on capture even t; capture function is disabled. 01 capture on rising tin x edge only and enable interrupt on capture event. 10 capture on falling tin x edge only and enable interrupt on capture event. 11 capture on any tin x edge and enable interrupt on capture event. 10 om output mode 0 active-low pulse on tout x for one timer input clock cycle as defined by the iclk bits. thus, tout x may be low for one bus clock period, one bus clock/16 period, or one tin x clock cycle period. tout x changes occur on the rising edge of the system clock. 1 toggle tout x . tout x changes occur on the rising edge of the system clock. 11 ori output reference interrupt enable 0 disable interrupt for reference reached (does not affect interrupt on capture function). 1 enable interrupt upon reaching the reference value. 12 frr free run/restart 0 free run. the timer count continues to increment after the reference value is reached. 1 restart. the timer count is reset immediat ely after the reference value is reached. 13?14 iclk input clock source for the timer 00 internally cascaded input. for tmr1, the timer 1 input is the output of timer 2. for tmr3, the timer 3 input is the output of timer 4. for tmr2 and tmr4, this sele ction means no input clock is provided to the timer. 01 internal bus clock 10 internal bus clock divided by 16 11 corresponding tin x : tin1, tin2, tin3, or tin4 (falling edge). 15 ge gate enable 0tgate x is ignored. 1tgate x is used to control the timer. 4 datasheet u .com
cpm timers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 26-7 26.2.4 timer reference registers (trr1?trr4) each timer reference regist er (trr1?trr4), shown in figure 26-6 , contains the timeout?s reference value. the reference value is not reached until tcn x increments to equal the timeout reference value. 26.2.5 timer capture re gisters (tcr1?tcr4) each timer capture regist er (tcr1?tcr4), shown in figure 26-7 , is used to latch th e value of the counter according to tmr x [ce]. 26.2.6 timer counte rs (tcn1?tcn4) each timer counter regist er (tcn1?tcn4), shown in figure 26-8 , is an up-counter. a read cycle to tcn x yields the current value of the ti mer but does not affect the counti ng operation. a write cycle to tcn x sets the register to the written value, thus causing its corresponding prescalar, tmr x [ps], to be reset. note that the counter registers ma y not be updated correctly if a write is made while the timer is not running. use trr x to define the pr eferred count value. 0 15 field timeout reference value reset 0xffff r/w r/w offset 0x9_0d94 (trr1), 0x9_0d96 (trr2) , 0x9_0da4 (trr3), 0x9_0da6 (trr4) figure 26-6. timer reference registers (trr1?trr4) 0 15 field latched counter value reset 0x0000 r/w r/w offset 0x9_0d98 (tcr1), 0x9_0d9a (tcr2), 0x9_0da8 (tcr3), 0x9_0daa (tcr4) figure 26-7. timer capture registers (tcr1?tcr4) 0 15 field up counter reset 0x0000 r/w r/w offset 0x9_0d9c (tcn1), 0x9_0d9e (tcn2), 0x9_0dac (tcn3), 0x9_0dae (tcn4) figure 26-8. timer counter registers (tcn1?tcn4) 4 datasheet u .com
cpm timers MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 26-8 freescale semiconductor 26.2.7 timer event registers (ter1?ter4) each timer event register (ter x ), shown in figure 26-9 , reports events recognized by the timers. when an output reference event is recognized, the timer sets ter x [ref] regardless of the corresponding tmr x [ori]. the capture event is set only if it is enabled by tmr x [ce]. ter1?ter4 can be read at any time. writing ones clears event bits; writing zeros has no effect. both event bits must be cleared before the timer negates the interrupt. table 26-4 describes ter fields. 0 13 14 15 field ? ref cap reset 0x0000 offset 0x9_0db0 (ter1); 0x9_0db2 (ter 2); 0x9_0db4 (ter3); 0x9_0db6 (ter4) figure 26-9. timer event registers (ter1?ter4) table 26-4. ter field descriptions bits name description 0?13 ? reserved, should be cleared. 14 ref output reference event. the count er has reached the trr value. tmr[or i] is used to enable the interrupt request caused by this event. 15 cap capture event. the counter value has been latched in to the tcr. tmr[ce] is us ed to enable generation of this event. 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 27-1 chapter 27 sdma channels the MPC8555E has two physical seri al dma (sdma) channels. the cp implements two dedicated virtual sdma channels for each fc c, scc, smc, spi, usb, and i 2 c?one for each transmitter and receiver. table 27-1 shows data flow paths. data from the periphe ral controllers can be routed to external ddr sdram using the ddr bus (path 1) or the local bus (path 2). figure 27-1. sdma data paths on a path 1 access, the sdma channe l must acquire the external ddr sy stem bus. on a path 2 access, the local bus is acquired and th e access is not seen on the external ddr system bus. thus, the local bus transfer occurs at the same time as other ope rations on the external ddr system bus. the sdma channel always operates in bi g-endian format when accesses data. ddr sdram internal system bus core cp sdma dual-port ram 1 3 sccs external ram 2 ddr local 2 fccs 2 smcs spi i 2 c ecm ddr controller 1 usb 4 datasheet u .com
sdma channels MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 27-2 freescale semiconductor if a system or local bus error occurs on a cp-relat ed access by the sdma, the cp generates an interrupt which will set the sdma sys or sdma lcl bit in the sipnr_l register. section 22.5.1.3, ?cpm interrupt pending regist ers (sipnr_h, sipnr_l).? the interrupt service routine then reads the appropriate dma transfer e rror address register (smaer for the sy stem bus or lmaer for the local bus) to determine the address the bus er ror occurred on. the cha nnel that caused the bus error is determined by reading the channel numbe r from smevr or lmevr. 27.1 sdma registers 27.1.1 sdma address error registers (smaer, lmaer) these registers indicate the address of the error that oc curred at a read or write transaction initiated by the system or local channel sdma. the smaer holds the system address of the system sdma initiated error transaction, and the lmaer holds the local address of the local sdma init iated error transaction. smaer and lmaer are cleared by hard reset. they are not affected by soft reset. these registers are updated at the first occurrence of th e error detection; the next captur e is enabled only after the event register is cleared. 27.1.2 sdma event registers (smevr, lmevr) these registers indicate if the er ror information that is found in smaer/lmaer is valid. they are updated in the first sdma data error that is detecte d. bit 0 is cleared by writing 1 to it. writing 0 has no effect. msnum contains the se rial number of the channel that created the data error. the bit fields of these two registers are updated only when a read error oc curs. smevr and lmevr are cleared by hard reset. soft reset has no effect. 0 31 field smaer/lmaer r/w r reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x9_0050 (smaer); 0x9_0060 (lmaer) figure 27-2. sdma address erro r registers (smaer and lmaer) 012 78 31 field dataerr ? msnum ? r/w r/w r r/w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset 0x9_0058 (smevr); 0x9_0068 (lmevr) figure 27-3. sdma event registers (smevr and lmevr) 4 datasheet u .com
sdma channels MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 27-3 27.1.3 sdma control registers (smctr, lmctr) the sdma control registers (s mctr and lmctr), shown in figure 27-4 , contain control parameters and can be updated through sreg. table 27-1. smevr and lmevr field descriptions bits name description 0 dataerr indicates data error, error details are captured in smaer/lmaer registers, and in msnum field. bit is cleared by writing ?1? to it. writing ?0? has no effect. 0 no error occurred 1 error occurred while reading / writing data 1?reserved 2?7 msnum represent the serial number of the channel that cr eated the data error 8?31 ? reserved 01245 31 field err_ mask ?? ? r/w r/w reset 0011_1000_0000_0000_0000_0000_0000_0000 offset 0x9_005c (smctr); 0x9_006c (lmctr) figure 27-4. sdma control registers (smctr and lmctr) table 27-2. smctr/lmctr field descriptions bits name description 0 err_mask data error interrupt mask 0 disable error interrupt 1 enable error interrupt 1?reserved 2?4 ? reserved note: user must not change default value of bits 2?4 (?111?) when writing to smctr/lmctr 5?31 ? reserved 4 datasheet u .com
sdma channels MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 27-4 freescale semiconductor 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 28-1 chapter 28 serial communications controllers (sccs) the MPC8555E has three serial communications controllers (sccs ), which can be configured independently to implement differ ent protocols for bridging functions , routers, and gateways, and to interface with a wide variety of standard wans , lans, and proprietary networks. an scc has many physical interface options such as interfacing to td m buses, isdn buses, and st andard modem interfaces. the sccs are independent from the physical interface, but sc c logic formats and ma nipulates data from the physical interface. furthermore, th e choice of protocol is independent from the c hoice of interface. an scc is described in terms of the pr otocol it runs. when an scc is pr ogrammed to a certain protocol or mode, it implements functionality th at corresponds to parts of the protoc ol?s link layer (layer 2 of the osi reference model). many scc func tions are common to protocols of the following controllers: ? uart, described in chapter 29, ?scc uart mode? ? hdlc and hdlc bus, described in chapter 30, ?scc hdlc mode? ? appletalk/localtalk, described in chapter 33, ?scc appletalk mode? ? bisync, described in chapter 31, ?scc bisync mode? ? transparent, described in chapter 32, ?scc transparent mode? ? although the selected protocol usually applies both to the scc transmitter and receiver, one half of an scc can run transparent operations wh ile the other runs a standard protocol. each rx and tx internal clock can be programmed with either an external or internal source. internal clocks originate from one of ei ght baud rate generators (brgs) or an external clock pin; see section 24.3, ?nmsi configuration,? for each scc?s available clock sources. thes e clocks can be as fast as a 1:4 ratio of the system clock. (for example, an scc intern al clock can run at 12.5 mh z in a 50-mhz system.) however, an scc?s ability to support a sustained bit stream depends on the protocol as well as other factors. note this clock ratio is based on the hardwa re architecture and does not ensure that an application will r un at that speed. it is the responsibility of the system designer to check ac specifications of the i/o pins and determine the maximum frequency. associated with each scc is a di gital phase-locked loop (dpll) for external clock recovery, which supports nrz, nrzi, fm0, fm1, manche ster, and differential manchester . if the clock recovery function is not required (that is, synchronous communication), th en the dpll can be disa bled, in which case only nrz and nrzi are supported. an scc can be connected to its own set of pins on the MPC8555E. this configuration is called the non-multiplexed serial interface (nmsi) a nd is described in chapter 23, ?serial interface with time-slot 4 datasheet u .com
serial communications controllers (sccs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 28-2 freescale semiconductor assigner.? using nmsi, an scc can support sta ndard modem interface signals, rts , cts , and cd . if required, software and addi tional parallel i/o lines can be used to support additional handshake signals. figure 28-1 shows the scc block diagram. figure 28-1. scc block diagram 28.1 features the following is a list of the main scc features. (p erformance figures assume a 25-mhz system clock.) ? implements hdlc/sdlc, hdlc bus, synchronous start/stop, as ynchronous start/stop (uart), appletalk/localtalk, and tota lly transparent protocols ? additional protocols may be available through th e use of ram-based microcodes. please contact your freescale sales office. ? dpll circuitry for clock recovery with nrz, nrzi, fm0, fm1, manchester, and differential manchester (also known as differential bi-phase-l) ? clocks can be derived from a baud rate generator, an external pin, or dpll ? supports automatic control of the rts , cts , and cd modem signals ? multi-buffer data structure for receive and send (the number of buf fer descriptors (bds) is limited only by the size of the internal dual-port ram?8 bytes per bd) ? deep fifos (scc transmit and receive fifos are 32 bytes each.) ? transmit-on-demand feature d ecreases time to frame transmission (transmit latency) ? low fifo latency option for send and receive in character-oriented and totally transparent protocols ? frame preamble options ? full-duplex operation decoder delimiter shifter delimiter internal clocks encoder modem lines rx control unit rx data fifo tx data fifo tx control unit rxd modem lines clock generator dpll and clock recovery tclk txd control registers shifter system bus peripheral bus rclk 4 datasheet u .com
serial communications controllers (sccs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 28-3 ? fully transparent option for one half of an s cc (rx/tx) while another protocol executes on the other half (tx/rx) ? echo and local loopback modes for testing 28.2 general scc mode re gisters (gsmr1?gsmr4) each scc contains a general scc m ode register (gsmr) that define s options common to most of the protocols. gsmr_l contains the lo w-order 32 bits; gsmr_h, shown in figure 28-2 , contains the high-order 32 bits. some gsmr operati ons are described in later sections. table 28-1 describes gsmr_h fields. 0 14 15 field ? reset 0000_0000_0000_0000 r/w r/w offset 0x9_1a04 (gsmr1); 0x9_1a4 4 (gsmr3); 0x9_1a64 (gsmr4) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field tcrc revd trx ttx cdp ctsp cds ctss tfl rfw txsy synl rtsm rsyn reset 0000_0000_0000_0000 r/w r/w offset 0x9_1a06 (gsmr1); 0x9_1a4 6 (gsmr3); 0x9_1a66 (gsmr4) figure 28-2. gsmr_h?general scc mode register (high order) table 28-1. gsmr_h field descriptions bits name description 0?15 ? reserved, should be cleared. 16?17 tcrc transparent crc (valid for totally transparent channel only). selects the frame checking provided on transparent channels of the scc (either the receiver, transmitter, or both, as defined by ttx and trx). although this configuration selects a frame check type, the decision to send the frame check is made in the txbd. thus, frame checks are not needed in transpa rent mode and frame check errors generated on the receiver can be ignored. 00 16-bit ccitt crc (hdlc). (x16 + x12 + x5 + 1) 01 crc16 (bisync). (x16 + x15 + x2 + 1) 10 32-bit ccitt crc (hdlc) (x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x1 + 1) 11 reserved 18 revd reverse data (valid for a totally transparent channel only) 0 normal operation 1 reverses the bit order for totally transparent channels on this scc (either the receiver, transmitter, or both) and sends the msb of each byte first. section 31.11, ?bisync mode register (psmr),? describes reversing bit order in a bisync protocol. 4 datasheet u .com
serial communications controllers (sccs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 28-4 freescale semiconductor 19?20 trx, ttx transparent receiver/transmitter. the receiver, transmitte r, or both can use totally transparent operation, regardless of gsmr_l[mode]. for example, to config ure the transmitter as a uart and the receiver for totally transparent operations, set mode = 0b0100 (uart), ttx = 0, and trx = 1. 0 normal operation 1 the channel uses totally transparent mode, regar dless of the protocol chosen in gsmr_l[mode]. for full-duplex totally transparent operation, set both ttx and trx. 21, 22 cdp, ctsp cd /cts pulse. if this scc is used in the tsa and is programmed in transparent mode, set ctsp and refer to section 32.4.2, ?synchronization and the tsa,? for options on programming cdp. 0 normal operation (envelope mode). cd /cts should envelope the frame. negating cd /cts during reception causes a cd /cts lost error. 1 pulse mode. synchronization occurs when cd /cts is asserted; further cd /cts transitions do not affect reception. 23, 24 cds, ctss cd /cts sampling. determine synchroni zation characteristics of cd and cts . if the scc is in transparent mode and is used in the tsa, cds and ctss must be set. also, cds and ctss must be set for loopback testing in transparent mode. 0cd /cts is assumed to be asynchronous with data. it is internally synchronized by the scc, then data is received (cd ) or sent (cts ) after several clock delays. 1cd /cts is assumed to be synchronous with data, which speeds up operation. cd or cts must transition while the rx/tx clock is low, at which time, the transfer begins. useful for connecting MPC8555E in transparent mode since the rts of one MPC8555E can connect directly to the cd /cts of another. 25 tfl transmit fifo length 0 normal operation. the transmit fifo is 32 bytes. 1 the tx fifo is 1 byte. this option is used with character-oriented protocols, such as uart, to ensure a minimum fifo latency at th e expense of performance. 26 rfw rx fifo width 0 receive fifo is 32 bits wide for maximum performance; the rx fifo is 32 bytes. data is not normally written to receive buffers until at least 32 bits are re ceived. this configuration is required for hdlc-type protocols and is recommended for high-performance transparent protocols. 1 low-latency operation. the receive fifo is 8 bits wid e, reducing the rx fifo to a quarter its normal size. this allows data to be written to the buffer as soon as a character is received, instead of waiting to receive 32 bits. this configuration must be chosen for character-oriented protocols, such as uart. it can also be used for low-performance, low-latency, transparent op eration. however, it must not be used with hdlc, hdlc bus, or appletalk because it causes erratic behavior. 27 txsy transmitter synchronized to the receiver. intended for x.21 applications where the transmitted data must begin an exact multiple of 8-bit periods after the received data arrives. 0 no synchronization between receiver and transmitter (default). 1 the transmit bit stream is synchronized to the receiver. additionally, if rsyn = 1, transmission in totally transparent mode does not occur until the rece iver synchronizes with the bit stream and cts is asserted to the scc. assuming cts is asserted, transmission begins 8 cloc ks after the receiver starts receiving data. 28?29 synl sync length (bisync and transpar ent mode only). see the data synchroni zation register (dsr) definition in section 31.9, ?sending and receiv ing the synchronization sequence,? (bisync) and section 32.4.1.1, ?in-line synchronization pattern,? (transparent). 00 an external sync (cd ) is used instead of the sync pattern in the dsr. 01 4-bit sync. the receiver synchronizes on a 4-bit sync pattern stored in the dsr. this sync and additional syncs can be stripped by programming the scc?s parameter ram for character recognition. 10 8-bit sync. should be chosen along with the bisync protocol to implement mono-sync. the receiver synchronizes on an 8-bit sync pattern in the dsr. 11 16-bit sync. also called bisync. the receiver synchronizes on a 16-bit sync pattern stored in the dsr. table 28-1. gsmr_h field descriptions (continued) bits name description 4 datasheet u .com
serial communications controllers (sccs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 28-5 figure 28-3 shows gsmr_l. table 28-2 describes gsmr_l fields. 30 rtsm rts mode. determines whether flags or idles are to be sent. can be changed on-the-fly. 0 send idles between frames as defined by the protocol and the tend bit. rts is negated between frames (default). 1 send flags/syncs between frames according to the protocol. rts is always asserted whenever the scc is enabled. 31 rsyn receive synchronization timing (totally transparent mode only) 0 normal operation. 1 if cds = 1 , cd should be asserted on the second bit of the rx frame rather than on the first. 012345 6 7 8 101112131415 field ? edge tci tsnc rinv tinv tpl tpp tend tdcr reset 0000_0000_0000_0000 r/w r/w offset 0x9_1a00 (scc1); 0x9_1a40 (scc3); 0x9_1a60 (scc4) 16 17 18 20 21 23 24 25 26 27 28 31 field rdcr renc tenc diag enr ent mode reset 0000_0000_0000_0000 r/w r/w offset 0x9_1a02 (scc1); 0x9_1a42 (scc3); 0x9_1a62 (scc4) figure 28-3. gsmr_l?general scc mode register (low order) table 28-2. gsmr_l field descriptions bits name description 0 ? reserved, should be cleared. 1?2 edge clock edge. determines the clock edge the dpll uses to adjust the receive sample point due to jitter in the received signal. ignored in uart protocol or if the 1x clock mode is selected in rdcr. 00 both the positive and negative edges are used for changing the sample point (default). 01 positive edge. only the positive edge of the received signal is used to change the sample point. 10 negative edge. only the negative edge of the receiv ed signal is used to change the sample point. 11 no adjustment is made to the sample point. table 28-1. gsmr_h field descriptions (continued) bits name description 4 datasheet u .com
serial communications controllers (sccs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 28-6 freescale semiconductor 3 tci transmit clock invert 0 normal operation 1 before it is used, the internal tx clock (tclk) is in verted by the scc so it can clock data out one-half clock earlier (on the rising rather than the falling edge). in this case, the scc offers a minimum and maximum rising clock edge-to-data specif ication. data output by the scc after the rising edge of an external tx clock can be latched by the external receiver one clock cycle later on the next rising edge of the same tx clock. in hdlc and transparent mode, when tci = 0, data is sent on the falling edge; when tci = 1, on the rising edge. recommended for hdlc and transparent operation when clock rates exceed 8 mhz to improve data setup time for the external transceiver. 4?5 tsnc transmit sense. determines the amount of time the in ternal carrier sense signal stays active after the last transition on rxd, indicating that the line is free. fo r instance, appletalk can use tsnc to avoid a spurious cs-changed (scce[dcc]) interrupt that would otherwise occur during the frame sync sequence before the opening flags. if rdcr is configured to 1 clock mode, the delay is the greater of the two numbers listed. if rdcr is configured to 8 , 16 , or 32 mode, the delay is the smaller number. 00 infinite. carrier sense is always active (default) 01 14- or 6.5-bit times as determined by rdcr 10 4- or 1.5-bit times as determined by rdcr (normally for appletalk) 11 3- or 1-bit times as determined by rdcr 6 rinv dpll rx input invert data. must be zero in hdlc bus mode or asynchronous uart mode 0 do not invert. 1 invert data before sending it to the dpll for recept ion. used to produce fm1 fr om fm0 and nrzi space from nrzi mark or to invert the data stream in regular nrz mode. 7 tinv dpll tx input invert data. must be zero in hdlc bus mode 0 do not invert. 1 invert data before sending it to the dpll for trans mission. used to produce fm1 from fm0 and nrzi space from nrzi mark and to invert the data stream in regular nrz mode. in t1 applications, setting tinv and tend creates a continuously inverted hdlc data stream. 8?10 tpl tx preamble length. determines the leng th of the preamble configured by the tpp bits 000 no preamble (default) 001 8 bits (1 byte) 010 16 bits (2 bytes) 011 32 bits (4 bytes) 100 48 bits (6 bytes) 101 64 bits (8 bytes) 110 128 bits (16 bytes) 111 reserved 11?12 tpp tx preamble pattern. determines what, if any, bit pattern should precede each tx frame. the preamble pattern is sent before the first flag/sync of the frame. tpp is ignored in uart mode. the preamble length is programmed in tpl; the preamble pattern is typically s ent to a receiving station that uses a dpll for clock recovery. the receiving dpll uses the regular preamble pattern to help it lock onto the received signal in a short, predictable time period. 00 all zeros 01 repetitive 10s 10 repetitive 01s 11 all ones. select this setting for localtalk operation. table 28-2. gsmr_l field descriptions (continued) bits name description 4 datasheet u .com
serial communications controllers (sccs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 28-7 13 tend transmitter frame ending. intended for nrzi transm itter encoding of the dpll . tend determines whether txd should idle in a high state or in an encoded ones st ate (high or low). it can, however, be used with other encodings besides nrzi. 0 default operation. txd is encoded only when data is sent, including the preamble and opening and closing flags/syncs. when no data is available to send, the signal is driven high. 1 txd is always encoded, even when idles are sent. 14?15 tdcr transmitter/receiver dpll clock ra te. if the dpll is not used, choose 1 mode except in asynchronous uart mode where 8 , 16 , or 32 must be chosen. tdcr should match r dcr in most applications to allow the transmitter and receiver to use the same clock source. if an applicatio n uses the dpll, the selection of tdcr/rdcr depends on the encoding/decoding. if communication is synchronous, select 1 . fm0/fm1, manchester, and differential manchester require 8 , 16 , or 32 . if nrz- or nrzi-encoded communication is asynchronous (that is, clock recovery required), select 8 , 16 , or 32 . the 8 option allows highest speed, whereas the 32 option provides the greatest resolution. 00 1 clock mode. only nrz or nrzi encodings/decodings are allowed. 01 8 clock mode 10 16 clock mode. normally chosen for uart and appletalk 11 32 clock mode 16?17 rdcr 18?20 renc receiver decoding/transmitter encoding method. se lect nrz if dpll is not used. renc should equal tenc in most applications. 000 nrz (default setting if dpll is not used). required for uart (synchronous or asynchronous) 001 nrzi mark (set rinv/tinv also for nrzi space) 010 fm0 (set rinv/tinv also for fm1) 011 reserved 100 manchester 101 reserved 110 differential manchester (differential bi-phase-l) 111 reserved 21?23 tenc 24?25 diag diagnostic mode 00 normal operation, cts and cd are under automatic control. data is received through rxd and transmitted through txd. the scc uses modem signals to enable or disable transmission and reception. these timings are shown in section 28.4.5, ?controlling scc timing with rts, cts, and cd.? 01 local loopback mode. transmitter output is connected internally to the receiver input, while the receiver and the transmitter operate normally. the value on rx d is ignored. if enabled, data appears on txd, or the parallel i/o registers can be programmed to make txd high. rts can also be programmed to be disabled in the appropriate parallel i/o register. the transmitter and receiver must share the same clock source, but separate clk x pins can be used if connected to the same external clock source. if external loopback is preferred, program diag for normal operation and externally connect txd and rxd. then, physically connect the control signals (rts connected to cd , and cts grounded) or set the parallel i/o registers so cd and cts are permanently asserted to the scc by configuring the associated cts and cd pins as general-purpose i/o. 10 automatic echo mode. the transmitter automatically re sends received data bit-by-bit using the rx clock provided. the receiver operates normally and receives data if cd is asserted. cts is ignored. 11 loopback and echo mode. loopback and echo operation occur simultaneously. cd and cts are ignored. see the loopback bit description above for clocking requirements. for tdm operation, the diagnostic mode is selected by si x mr[sdm x ]; see section 23.6.2, ?si mode registers (si2mr).? table 28-2. gsmr_l field descriptions (continued) bits name description 4 datasheet u .com
serial communications controllers (sccs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 28-8 freescale semiconductor 28.2.1 protocol-specific mode register (psmr) the protocol implemented by an scc is selected by its gsmr_l[mode]. each scc has an additional protocol-specific mode regi ster (psmr) that configures it specifi cally for the chosen protocol. the psmr fields are described in the specific chapters that describe each protocol. psmrs are cleared at reset. psmrs reside at the following addresse s: 0x9_1a08 (psmr1), 0x9_1a28 (psmr2), 0x9_1a48 (psmr3), and 0x9_1a68 (psmr4). 28.2.2 data synchronization register (dsr) each scc has a data synchroniza tion register (dsr) that specifi es the pattern used for frame synchronization. the programmed value for dsr depends on the following protocols: ? uart?dsr is used to configure fractional stop bit transmission. ? bisync and transparent?dsr should be programmed with the sync pattern. ? hdlc?at reset, dsr defaults to 0x7e7e (two hdlc flags), so it does not need to be written. 26 enr enable receive. enables the receiver hardware state machine for this scc. 0 the receiver is disabled and data in the rx fifo is lost. if enr is cleared during reception, the receiver aborts the current character. 1 the receiver is enabled. enr can be set or cleared, regardless of whether serial clocks are present. section 28.4.7, ?reconfiguring the sccs,? describes how to disable/enable an scc. note that other tools, including the enter hunt mode and close rxbd commands and the e bit of the rxbd, data pr ovide the capability to control the receiver. 27 ent enable transmit. enables the transmitter hardware state machine for this scc. 0 the transmitter is disabled. if ent is cleared during transmission, the current character is aborted and txd returns to the idle state. data already in the tx shift register is not sent. 1 the transmitter is enabled. ent can be set or cleared, regardless of whether serial clocks are present. section 28.4.7, ?reconfiguring the sccs,? describes how to disable/enable an scc. note that other tools, such as the stop transmit , graceful stop transmit , and restart transmit commands, the freeze option and cts flow control option in uart mode, and the r bit of the txbd, also provide the capability to control the transmitter. 28?31 mode channel protocol mode. see also gsmr_h[ttx, trx]. 0000 hdlc 0001 reserved 0010 appletalk/localtalk 0011 ss7?reserved for ram microcode 0100 uart 0101 profibus?reserved for ram microcode 0110 reserved 0111 reserved 1000 bisync 1001 reserved 1010 qmc 1011 reserved 1100 reserved 11xx reserved table 28-2. gsmr_l field descriptions (continued) bits name description 4 datasheet u .com
serial communications controllers (sccs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 28-9 figure 28-4 shows the sync fields. 28.2.3 transmit-on-demand register (todr) in normal operation, if no frame is being sent by an s cc, the cp periodically polls the r bit of the next txbd to see if a new fr ame/buffer is requested. de pending on the scc configurat ion, this polling occurs every 8?32 serial tx clocks. the tr ansmit-on-demand option, selected in the transmit-on-demand register (todr) shown in figure 28-5 , shortens the latency of the tx buffe r/frame and is useful in lan-type protocols where maximum inter-frame gap time s are limited by the protocol specification. the cp can be configured to begin processing a ne w frame/buffer without wait ing the normal polling time by setting todr[tod] after txbd[r] is set. because this feature favors the specified txbd, it may affect servicing of other scc fifos. therefore, transmitting on demand should only be used when a high-priority txbd has be en prepared and enough time has pa ssed since the la st g transmission. table 28-3 describes todr fields. 07815 field syn2 syn1 reset 0111_1110 0111_1110 r/w r/w offset 0x9_1a0e (dsr1); 0x9_1a2e (dsr2); 0x9_1a4e (dsr3); 0x9_1a6e (dsr4) figure 28-4. data synchronization register (dsr) 01 15 field tod ? reset 0000_0000_0000_0000 r/w r/w offset 0x9_1a0c (todr1); 0x9_1a2c (to dr2); 0x9_1a4c (todr3); 0x9_1a6c (todr4) figure 28-5. transmit-on-demand register (todr) table 28-3. todr field descriptions bits name description 0 tod transmit on demand 0 normal operation 1 the cp gives high priority to the current txbd and begins sending the frame without waiting the normal polling time to check the txbd?s r bit. tod is cleared automatically after one serial clock, but transmitting on demand continues until an unprepared (r = 0) bd is reached. tod does not need to be set again if new txbds are added to the bd table as long as ol der txbds are still being processed. new txbds are processed in order. the first bit of the frame is ty pically clocked out 5-6 bit times after tod is set. 1?15 ? reserved, should be cleared. 4 datasheet u .com
serial communications controllers (sccs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 28-10 freescale semiconductor 28.3 scc buffer descriptors (bds) data associated with each scc channel is stored in buffers and each buffer is referenced by a buffer descriptor (bd) that can reside anywhere in dual-port ram. the tota l number of 8-byte bds is limited only by the size of the dual-port ram (128 bds/1 kbyte). these bds are sh ared among all serial controllers?sccs, smcs, spi, and i 2 c. the user defines how th e bds are allocated among the controllers. each 64-bit bd has the following structure: ? the half word at offset + 0x0 c ontains status and control bits th at control and report on the data transfer. these bits vary from pr otocol to protocol. the cpm updates the status bits after the buffer is sent or received. ? the half word at offset + 0x2 (data length) holds the number of bytes sent or received. ? for an rxbd, this is the numbe r of bytes the controller writes into the buffer. the cpm writes the length after received data is placed into the associated buffer and the buffer closed. in frame-based protocols (but not including scc transparent operati on), this field contains the total frame length, including crc bytes. also, if a received fr ame?s length, including crc, is an exact multiple of mrblr, th e last bd holds no act ual data but does contain the total frame length. ? for a txbd, this is the number of bytes the c ontroller should send from its buffer. normally, this value should be greater than zero. the cpm never modifies this field. ? the word at offset + 0x4 (buffe r pointer) points to the beginning of the buffer in memory (internal or external). ? for an rxbd, the value must be a multiple of four. (word-aligned) ? for a txbd, this pointer can be even or odd. shown in figure 28-6 , the format of tx and rxbds is the same in each scc mode. only the status and control bits differ for each protocol. for frame-oriented protocols, a messa ge can reside in as many buffers as necessary. each buffer has a maximum length of 65,535 bytes. the cpm does not assume that all buffers of a single fram e are currently linked to the bd table. the cpm does assume, however , that the unlinked buffers are provided by the core in time to be sent or received; otherwise, an error condition is reported?a n underrun error when sending and a busy error when receiving. figure 28-7 shows the scc bd table and buffer structure. 0 15 offset + 0 status and control offset + 2 data length offset + 4 high-order buffer pointer offset + 6 low-order buffer pointer figure 28-6. scc buffer descriptors (bds) 4 datasheet u .com
serial communications controllers (sccs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 28-11 figure 28-7. scc bd and buffer memory structure in all protocols, bd s can point to buffers in the internal dua l-port ram. however, because dual-port ram is used for descriptors, buffers are usually put in external ram, especially if they are large. the cpm processes txbds straightforwardly; when th e transmit side of an scc is enabled, the cpm starts with the first bd in that scc txbd table. on ce the cpm detects that the r bit is set in the txbd, it starts processing the buffer. the cpm detects that th e bd is ready when it polls the r bit or when the user writes to the todr. after data from the bd is put in the tx fifo, if necessary the cpm waits for the next descriptor?s r bit to be set before proc eeding. thus, the cpm does no look-ahead descriptor processing and does not skip bds that are not ready. wh en the cpm sees a bd?s w bit (wrap) set, it returns to the start of the bd table after th is last bd of the table is processe d. the cpm clears r (not ready) after using a txbd, which keeps it from being retransmitted before it is confirmed by the core. however, some protocols support a continuous mode (cm), for which r is not cleared (always ready). the cpm uses rxbds similarly. wh en data arrives, the cpm perfor ms required processing on the data and moves resultant data to the buffer pointed to by the first bd; it continues until the buf fer is full or an event, such as an error or end-of- frame detection, occu rs. the buffer is then clos ed; subsequent data uses the next bd. if e = 0, the current buffer is not empty and it reports a busy error. the cpm does not move from the current bd until e is set by the core (the buffer is empty). afte r using a descriptor , the cpm clears e (not empty) and does not reuse a bd until it has been processed by the core. however, in continuous mode (cm), e remains set. when the cpm discovers a descriptor?s w bit set (i ndicating it is the last bd in the circular bd table), it returns to the beginning of the table when it is time to move to the next buffer. status and control buffer length buffer pointer sccx txbd ta b l e po i n t e r sccx rxbd ta b l e po i n t e r sccx rxbd ta bl e sccx txbd ta bl e dual-port ram status and control buffer length buffer pointer tx buffer external memory rx buffer descriptors tx buffer descriptors rx buffer 4 datasheet u .com
serial communications controllers (sccs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 28-12 freescale semiconductor 28.4 scc parameter ram each scc parameter ram area begins at th e same offset from each scc base area. section 28.4.1, ?scc base addresses,? describes the scc?s base addresses. th e protocol-specific portions of the scc parameter ram are discussed in the sp ecific protocol descript ions and the part that is common to all scc protocols is shown in table 28-4 . some parameter ram values must be initialized before the scc can be enabled. other values are initialized or written by the cpm. once initialized, mo st parameter ram values do not need to be accessed because most activity cent ers around the descriptors rather than the parameter ram. however, if the parameter ram is accessed, note the following: ? parameter ram can be read at any time. ? tx parameter ram can be wr itten only when the transmitt er is disabled?after a stop transmit command and before a restart transmit command or after the buffer/frame finishes transmitting after a graceful stop transmit command and before a restart transmit command. ? rx parameter ram can be written only when the receiver is disabled. note the close rxbd command does not stop reception, but it does allow the user to extract data fro m a partially full rx buffer. ?see section 28.4.7, ?reconfiguring the sccs.? table 28-4 shows the parameter ram map fo r all scc protocols. boldfaced entries must be initialized by the user. table 28-4. scc parameter ram map for all protocols offset 1 name width description 0x00 rbase hword rx/txbd table base address?offset from th e beginning of dual-port ram. the bd tables can be placed in any unused portion of the dual-port ram. the cpm starts bd processing at the top of the table. (the user defines the end of the bd ta ble by setting the w bit in the last bd to be processed.) initialize these entries before enabling the corresponding channel. erratic operations occur if bd tables of active sccs overlap. values in rbase and tbase shou ld be multip les of eight. 0x02 tbase hword 0x04 rfcr byte rx function code. see section 28.4.2, ?function co de registers (rfcr, tfcr).? 0x05 tfcr byte tx function code. see section 28.4.2, ?function c ode registers (rfcr, tfcr).? 0x06 mrblr hword maximum receive buffer length. defines the maximum number of bytes the MPC8555E writes to a receive buffer before it goes to the next buffer. the MPC8555E can write fewer bytes than mrblr if a condition such as an error or end-of -frame occurs. it never writes more bytes than the mrblr value. therefore, user-supplied buffers should be no smaller than mrblr. mrblr should be greater than zero for all modes. it should be a multiple of 4 for hdlc mode, and in totally transparent mode unless the rx fi fo is 8-bits wide (gsmr_h[rfw] = 1). note that although mrblr is not intended to be changed while the scc is operating, it can be changed dynamically in a single-cycle, 16-bit move (not two 8-bit cycles). changing mrblr has no immediate effect. to guarantee the exact rx bd on which the change occurs, change mrblr only while the receiver is disabled. transmit buffer length is programmed in tx bd[data length] and is not affected by mrblr. 0x08 rstate word rx internal state 3 4 datasheet u .com
serial communications controllers (sccs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 28-13 28.4.1 scc base addresses the cpm maintains a section of ra m called the parameter ram, whic h contains many parameters for the operation of the fccs, sccs, spi, and i 2 c. scc base addresse s are described in table 28-5 . the exact definition of the parameter ram is contai ned in each protocol s ubsection describing a device that uses a parameter ram. 0x0c ? word rx internal buffer pointer 2 . the rx and tx internal buffer pointers are updated by the sdma channels to show the next address in the buffer to be accessed. 0x10 rbptr hword current rxbd pointer. po ints to the current bd being process ed or to the next bd the receiver uses when it is idling. after reset or when the end of the bd table is reached, the cpm initializes rbptr to the value in the rbase. although most applications do not need to writ e rbptr, it can be modified when the receiver is disabled or when no rx buffer is in use. 0x12 ? hword rx internal byte count 2 . the rx internal byte count is a do wn-count value initialized with mrblr and decremented with each byte written by the supporting sdma channel. 0x14 ? word rx temp 3 0x18 tstate word tx internal state 3 0x1c word tx internal buffer pointer 2 . the rx and tx internal buffer pointers are updated by the sdma channels to show the next address in the buffer to be accessed. 0x20 tbptr hword current txbd pointer. po ints to the current bd being processed or to the next bd the transmitter uses when it is idling. after reset or when the end of the bd table is reached, the cpm initializes tbptr to the value in the tbase. although most applications do not need to write tbptr, it can be modified when the transmitter is disabled or when no tx buffer is in use (after a stop transmit or graceful stop transmit command is issued and the frame completes its transmission). 0x22 ? hword tx internal byte count 2 . a down-count value initialized with txbd[data length] and decremented with each byte read by the supporting sdma channel. 0x24 ? word tx temp 3 0x28 rcrc word temp receive crc 2 0x2c tcrc word temp transmit crc 2 0x30 ?? protocol-specific area. (the size of th is area depends on the protocol chosen.) 1 from scc base. see section 28.4.1, ?scc base addresses.? 2 these parameters need not be accessed for normal operation but may be helpful for debugging. 3 for cp use only. table 28-4. scc parameter ram map for all protocols (continued) offset 1 name width description 4 datasheet u .com
serial communications controllers (sccs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 28-14 freescale semiconductor 28.4.2 function code registers (rfcr, tfcr) there are six separate function code registers for the three scc channe ls, three for rx buffers (rfcr1, rfcr3, and rfcr4) and three for tx buffers (tfcr1, tfcr3, and tfcr4 ). the function code registers contain the transaction specification associated wi th sdma channel accesses to external memory. figure 28-8 shows the register format. table 28-6 describes rfcr x /tfcr x fields. table 28-5. parameter ram?scc base addresses page address 1 1 offset from ram_base. peripheral size (bytes) 1 0x8000 scc1 256 2 0x8100 reserved 256 3 0x8200 scc3 256 4 0x8300 scc4 256 01234567 field ? gbl bo ? dtb ? reset 0000_0000_0000_0000 r/w r/w offset scc x base + 0x04 (rfcr x ); scc x base + 0x05 (tfcr x ) figure 28-8. function code registers (rfcr and tfcr) table 28-6. rfcr x /tfcr x field descriptions bits name description 0?1 ? reserved, should be cleared. 2 gbl global 0 snooping disabled 1 snooping enabled 3?4 bo byte ordering. set bo to select the required byte orderi ng for the buffer. if bo is changed on-the-fly, it takes effect at the beginning of the next frame (hdlc a nd transparent) or at the beginning of the next bd. 0x reserved 1x big endian 5 ? reserved, should be cleared 6 dtb data bus indicator 0 use system bus for sdma operation 1 use local bus for sdma operation 7 ? reserved, should be cleared. 4 datasheet u .com
serial communications controllers (sccs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 28-15 28.4.3 handling scc interrupts to allow interrupt handling for scc-specific events, ev ent, mask, and status regi sters are provided within each scc?s internal memory map area; see table 28-7 . because interrupt events are protocol-dependent, event descriptions are found in th e specific protocol chapters. follow these steps to handle an scc interrupt: 1. when an interrupt occurs, read scce to determin e the interrupt sources a nd clear those scce bits (in most cases). 2. process the txbds to reuse them if scce[tx] or scce[txe] = 1. if the transmit spee d is fast or the interrupt delay is l ong, the scc may have sent more than one tx buffer. thus, it is important to check more than one txbd during interrupt handling. a common practice is to process all txbds in the handler until one is found with its r bit set. 3. extract data from the rxbd if scce[rx], scce[rxb], or scce[r xf] is set. as with transmit buffers, if the receive speed is fa st or the interrupt delay is long, the scc may have received more than one buffer and the handler should check mo re than one rxbd. a common practice is to process all rxbds in the interrupt handler until one is found with rxbd[e] set. 4. execute the rfi instruction. for additional information abou t interrupt handling refer to chapter 22, ?cpm interrupt controller.? 28.4.4 initializing the sccs the sccs require that a number of registers and paramete rs be configured after a power-on reset. regardless of the protocol used, foll ow these steps to initialize sccs: 1. write the parallel i/o ports to configur e and connect the i/o pins to the sccs. 2. configure the parallel i/o registers to enable rts , cts , and cd if these signals are required. 3. if the time-slot assi gner (tsa) is used, the serial interface (si x ) must be configur ed. if the scc is used in nmsi mode, cmxscr must still be initialized. table 28-7. scc x event, mask, and status registers register offset description scce x 0x9_1a10 (scce1); 0x9_1a50 (scce3); 0x9_1a70 (scce4) scc event register. this 16-bit register reports ev ents recognized by any of the sccs. when an event is recognized, the scc sets its corresponding bit in scce, regardless of the corresponding mask bit. when the corresponding event occurs, an interrupt is si gnaled to the sivec register. bits are cleared by writing ones (writing zeros has no effect). scce is cleared at reset and can be read at any time. sccm x 0x9_1a14 (sccm1); 0x9_1a54 (sccm3); 0x9_1a74 (sccm4) scc mask register. the 16-bit, read/write register allo ws interrupts to be enabled or disabled using the cpm for specific events in each scc channel. an interr upt is generated only if scc interrupts in this channel are enabled in the cpm interrupt mask register (simr). if an sccm bit is zero, the cpm does not proceed with interrupt handling when that even t occurs. the sccm and scce bit positions are identical. sccs x 0x9_1a17 (sccs1); 0x9_1a57 (sccs3); 0x9_1a77 (sccs4) scc status register. this 8-bit, r ead-only register allows monitoring of the real-time status of rxd. 4 datasheet u .com
serial communications controllers (sccs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 28-16 freescale semiconductor 4. write all gsmr bits except ent or enr. 5. write the psmr. 6. write the dsr. 7. initialize the required values for this scc?s parameter ram. 8. initialize the transmit/receive parameters through the cp command register (cpcr). 9. clear out any current events in scce (optional). 10. write ones to sccm register to enable interrupts. 11. set gsmr_l[ent] and gsmr_l[enr]. descriptors can have their r or e bits set at any time. notice that the cpcr does not need to be accessed after a hardware reset. an scc shoul d be disabled and re-e nabled after any dynamic change to its parallel i/o ports or serial channel physical interface configuration. a full rese t can also be implemented using cpcr[rst]. 28.4.5 controlling scc timing with rts , cts , and cd when gsmr_l[diag] is progr ammed to normal operation, cd and cts are controlled by the scc. in the following subsections, it is assumed that gsmr_l[tci] is zer o, implying normal transmit clock operation. 28.4.5.1 synchronous protocols rts is asserted when the scc data is loaded into the tx fifo and a fal ling tx clock occurs. at this point, the scc starts sending data once a ppropriate conditi ons occur on cts . in all cases, the first data bit is the start of the opening flag, sync pattern, or preamble. figure 28-9 shows that the delay between rts and data is 0 bit times, re gardless of gsmr_h[ctss]. this operation assumes that cts is already asserted to the scc or that cts is reprogrammed to be a parallel i/o line, in which case cts to the scc is always asserted. rts is negated one clock after the last bit in the frame. figure 28-9. output delay from rts asserted for synchronous protocols 1. a frame includes opening and closing fl ags and syncs, if present in the protocol. tclk txd last bit of frame data first bit of frame data note : (output) rts (output) cts (input) 4 datasheet u .com
serial communications controllers (sccs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 28-17 when rts is asserted, if cts is not already asserted, delays to the first data bit depend on when cts is asserted. figure 28-10 shows that the delay between cts and the data can be approximately 0.5 to 1 bit times or no delay, depending on gsmr_h[ctss]. figure 28-10. output delay from cts asserted for synchronous protocols if cts is programmed to envelope data, negating it during fram e transmission causes a cts lost error. negating cts forces rts high and tx data to become idle. if gsmr_h[ctss] is zero, the scc must sample cts before a cts lost is recognized; otherw ise, the negation of cts immediately causes the cts lost condition. see figure 28-11 . 1. gsmr_h[ctss] = 0. ctsp is a do not care. tclk txd last bit of frame data first bit of frame data note: cts sampled low here 1. gsmr_h[ctss] = 1. ctsp is a do not care. tclk txd last bit of frame data first bit of frame data note: (output) rts (output) cts (input) (output) rts (output) cts (input) 4 datasheet u .com
serial communications controllers (sccs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 28-18 freescale semiconductor figure 28-11. cts lost in synchronous protocols note that if gsmr_h[ctss] = 1, cts transitions must occur wh ile the tx clock is low. reception delays ar e determined by cd as shown in figure 28-12 . if gsmr_h[cds] is zero, cd is sampled on the rising rx clock edge before data is re ceived. if gsmr_h[cds] is 1, cd transitions cause data to be immediately gated into the receiver. 1. gsmr_h[ctss] = 0. ctsp = 0 or no cts lost can occur. tclk txd first bit of frame data note: cts sampled low here 1. gsmr_h[ctss] = 1. ctsp = 0 or no cts lost can occur. tclk first bit of frame data note: cts sampled high here data forced high rts forced high data forced high rts forced high cts lost signaled in frame b cts lost signaled in frame b (output) rts (output) cts (input) cts (input) rts (output) txd (output) 4 datasheet u .com
serial communications controllers (sccs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 28-19 figure 28-12. using cd to control synchronous protocol reception if cd is programmed to envelope the data, it must remain asserted during frame tran smission or a cd lost error occurs. negation of cd terminates reception. if gsmr_h[cds] is zero, cd must be sampled by the scc before a cd lost error is recognized; otherwise, the negation of cd immediately causes the cd lost condition. if gsmr_h[cds] is set, all cd transitions must occur while the rx clock is low. 28.4.5.2 asynchro nous protocols in asynchronous protocols, rts is asserted when scc da ta is loaded into the tx fifo and a falling tx clock occurs. cd and cts can be used to control reception and transmission in the same manner as the synchronous protocols. the firs t bit sent in an as ynchronous protocol is the star t bit of the first character. in addition, the uart protocol has an option for cts flow control as described in chapter 29, ?scc uart mode . ? ?if cts is already asserted when rts is asserted, transmission begins in two additional bit times. ?if cts is not already asserted when rts is asserted and gsmr_h[ct ss] = 0, transmission begins in three additional bit times. ?if cts is not already asserted when rts is asserted and gsmr_h[ct ss] = 1, transmission begins in two additional bit times. 1. gsmr_h[cds] = 0. cdp = 0. rclk first bit of frame data notes: cd sampled low here rclk cd sampled high here last bit of frame data 2. if cd is negated prior to the last bit of the receive frame, cd lost is signaled in the frame bd. 3. if cdp = 1, cd lost cannot occur and cd negation has no effect on reception. 1. gsmr_h[cds] = 1. cdp = 0. notes: 2. if cd is negated prior to the last bit of the receive frame, cd lost is signaled in the frame bd. 3. if cdp = 1, cd lost cannot occur and cd negation has no effect on reception. last bit of frame data first bit of frame data cd assertion immediately gates reception cd negation immediately halts reception rxd (input) cd (input) cd (input) rxd (input) 4 datasheet u .com
serial communications controllers (sccs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 28-20 freescale semiconductor 28.4.6 digital phase-locked loop (dpll) operation each scc channel includes a digital phase-locked l oop (dpll) for recovering cl ock information from a received data stream. for applicati ons that provide a direct clock s ource to the scc, the dpll can be bypassed by selecting 1x mode for gsmr_l[rdcr, tdcr]. if the dpll is bypassed, only nrz or nrzi encodings are available. th e dpll is optional for protocols. figure 28-13 shows the dpll receiver block; figure 28-14 shows the transmitter block diagram. figure 28-13. dpll receiver block diagram dpll hsrclk rxd rinv tsnc edge rdcr renc receiver carrier snc decoded data hunting noise 0 s recovered clock hsrclk rclk 1 1x mode 0 s sccr data 1 1x mode d clk q hsrclk rxd rinv renc nrzi 4 datasheet u .com
serial communications controllers (sccs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 28-21 figure 28-14. dpll transmitter block diagram the dpll can be driven by one of the baud rate generator outputs or an external clock, clk x . in the block diagrams, this clock is labeled hsrclk/hstclk. the hsrclk /hstclk should be approximately 8x, 16x, or 32x the data rate, depending on the coding chosen. the dpll uses this clock, along with the data stream, to construct a data clock that can be used as the scc rx and/or tx cloc k. in all modes, the dpll uses the input clock to determine the nominal b it time. if the dpll is bypassed, hsrclk/hstclk is used directly as rclk/tclk. at the beginning of operation, the dpll is in search mode, whereas the fi rst transition resets the internal dpll counter and begins dpll operation. while the counter is counting, the dpll watches the incoming data stream for transitions; when one is detected, the dpll adjusts the count to produce an output clock that tracks incoming bits. the dpll has a carrier-sense signal that indicates wh en data transfers are on rxd. the carrier-sense signal asserts as soon as a transition is detected on r xd; it negates after the pr ogrammed number of clocks in gsmr_l[tsnc] when no transitions are detected. to prevent itself from locking on the wrong edges and to provide fast synchronization, the dpll should receive a preamble pattern be fore it receives the data. in some prot ocols, the preceding flags or syncs can function as a preamble; others use the patterns in table 28-8 . when transmission occurs, the scc can generate preamble patterns, as programmed in gsmr_l[tpp, tpl]. table 28-8. preamble requirements decoding method preamble pattern minimum preamble length required nrzi mark all zeros 8-bit nrzi space all ones 8-bit fm0 all ones 8-bit dpll hstclk tend tenc transmitter 0 s divided clock hstclk tclk 1 1x mode 0 s 1 tenc = nrzi d clk q scct data 0 s 1 1x mode tdcr d clk q hstclk txen hstclk txd tinv encoded 4 datasheet u .com
serial communications controllers (sccs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 28-22 freescale semiconductor the dpll can also be used to invert th e data stream of a transfer. this f eature is available in all encodings, including standard nrz format. als o, when the transmitter is idling, the dpll can either force txd high or continue encoding the data supplied to it. the dpll is used for uart encoding/decoding, which gives the option of select ing the divide ratio in the uart decoding process (8 , 16 , or 32 ). typically, 16 is used. note the 1:4 system clock/se rial clock ratio does not a pply when the dpll is used to recover the clock in the 8 , 16 , or 32 modes. synchronization occu rs internally after the dp ll generates the rx clock. therefore, even the fastest dpll clock generation (the 8 option) easily meets the required 1:4 ratio clocking limit. 28.4.6.1 encoding data with a dpll each scc contains a dpll unit that can be programme d to encode and decode the scc data as nrz, nrzi mark, nrzi space, fm0, fm1, manchester, and di fferential manchester. figure 28-15 shows the different encoding methods. figure 28-15. dpll encoding examples fm1 all zeros 8-bit manchester 101010...10 8-bit differential manchester all ones 8-bit table 28-8. preamble requirements (continued) decoding method preamble pattern minimum preamble length required data nrz nrzi mark nrzi space fm0 fm1 manchester differential manchester 011001 4 datasheet u .com
serial communications controllers (sccs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 28-23 if the dpll is not needed, nrz or nrzi codings can be selected in gs mr_l[renc, tenc]. coding definitions are shown in table 28-9 . 28.4.7 reconfiguring the sccs the proper reconfiguration sequence must be follow ed for scc parameters that cannot be changed dynamically. for instance, the internal baud rate generators allow on-the-fly changes, but the dpll-related gsmr does not. the steps in the followi ng sections show how to disable, reconfigure and re-enable an scc to ensure that buf fers currently in use are properly cl osed before reconfiguring the scc and that subsequent data goes to or from new buffers accor ding to the new configuration. modifying parameter ram does not require the scc to be fully disabled. see the parameter ram description for when values can be changed. to disable all peripheral c ontrollers, set cpcr[rst] to reset the entire cpm. 28.4.7.1 general reconfiguration se quence for an scc transmitter an scc transmitter can be reconfigur ed by following these general steps: 1. if the scc is se nding data, issue a stop transmit command. transmission should stop smoothly. if the scc is not transmitti ng (no txbds are ready or the graceful stop transmit command has been issued and completed) or the init tx parameters command is issued, the stop transmit command is not required. 2. clear gsmr_l[ent] to disable the scc transmitter and put it in reset state. 3. modify scc tx parameters or parameter ram. to switch protoc ols or restore the initial tx parameters, issue an init tx parameters command. 4. if an init tx parameters command was not issued in step 3, issue a restart transmit command. table 28-9. dpll codings coding description nrz a one is represented by a high level for the duration of the bit and a zero is represented by a low level. nrzi mark a one is represented by no transition at all. a zero is represented by a transition at the beginning of the bit (the level present in the preceding bit is reversed). nrzi space a one is represented by a transiti on at the beginning of the bit (the level pr esent in the preceding bit is reversed) . a zero is represented by no transition at all. fm0 a one is represented by a transition only at the beginning of the bit. a zero is represented by a transition at the beginning of the bit and another trans ition at the center of the bit. fm1 a one is represented by a transition at the beginning of the bit and another tr ansition at the center of the bit. a zero is represented by a transition only at the beginning of the bit. manchester a one is represented by a high-to- low transition at the center of the bit. a zero is represented by a low to high transition at the center of the bit. in both cases there ma y be a transition at the beginning of the bit to set up the level required to make the correct center transition. differential manchester a one is represented by a transition at the center of the bit with the opposit e direction from the transition at the center of the preceding bit. a zero is represented by a tran sition at the center of the bit with the same polarity from the transition at the center of the preceding bit. 4 datasheet u .com
serial communications controllers (sccs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 28-24 freescale semiconductor 5. set gsmr_l[ent]. transmission begins using the txbd pointe d to by tbptr, assuming the r bit is set. 28.4.7.2 reset sequence for an scc transmitter the following steps reinitialize an scc tr ansmit parameters to the reset state: 1. clear gsmr_l[ent]. 2. make any modifications then issue the init tx parameters command. 3. set gsmr_l[ent]. 28.4.7.3 general reconfigurati on sequence for an scc receiver an scc receiver can be reconfi gured by following these steps: 1. clear gsmr_l[enr]. the scc receiver is now disabled and put in a reset state. 2. modify scc rx parameters or pa rameter ram. to switch protocols or restore rx parameters to their initial state, issue an init rx parameters command. 3. if the init rx parameters command was not issued in step 2, issue an enter hunt mode command. 4. set gsmr_l[enr]. reception begins using the rxbd pointed to by rbpt r, assuming the e bit is set. 28.4.7.4 reset sequence for an scc receiver to reinitialize the scc receiver to the state it was in after reset, follow these steps: 1. clear gsmr_l[enr]. 2. make any modifications then issue the init rx parameters command. 3. set gsmr_l[enr]. 28.4.7.5 switching protocols to switch an scc?s protocol wit hout resetting the board or affecti ng other sccs, follow these steps: 1. clear gsmr_l[ent, enr]. 2. make protocol changes in the gsmr a nd additional parameters then issue the init tx and rx parameters command to initialize both tx and rx parameters. 3. set gsmr_ l[ent, enr] to enable the scc with the new protocol. 28.4.8 saving power to save power when not in use, an scc can be disabled by clearing gsmr_l[ent, enr]. 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 29-1 chapter 29 scc uart mode the universal asynchronous receiver transmitter (uart) pr otocol is commonly used to send low-speed data between devices. the term asynchronous is used because it is not necessary to send clocking information along with the data being sent. uart links are typi cally 38,400 baud or less and are character-based. asynchronous links are used to c onnect terminals with ot her devices. even where synchronous communications are required, the uart is often used as a local port to run board debugger software. the character format of the uart protocol is shown in figure 29-1 . figure 29-1. uart character format because the transmitter and receiver operate asynchronous ly, there is no need to connect the transmit and receive clocks. instead, the receiver oversamples the incoming data st ream (usually by a factor of 16) and uses some of these samples to determine the bit valu e. traditionally, the middle 3 of the 16 samples are used. two uarts can communicate using this system if the transmitter and receiver use the same parameters, such as the parity scheme and character length. when data is not sent, a c ontinuous stream of ones is sent (idle condition). because the start bit is always a zero, the receiver can detect when real data is once again on th e line. uart specifies an all-zeros break character, which ends a character transfer sequence. the most popular protocol that us es asynchronous characters is the rs-232 standar d, which specifies baud rates, handshaking protocols, and me chanical/electrical details. anot her popular format is rs-485, which defines a balanced line system al lowing longer cables than rs-232 links . even synchronous protocols like hdlc are sometimes defined to run over asynchronous links. the pr ofibus standard extends uart protocol to include lan-oriented features such as token passing. all standards provide handshaking si gnals, but some systems require onl y three physical lines?tx data, rx data, and ground. many proprietary standards have been built around the uart?s asynchronous character frame, some of which implement a multidrop configuration where multiple stations, each with a specific address, can be pr esent on a network. in multid rop mode, frames of charac ters are broadcast with the first character acting as a dest ination address. to acc ommodate this, the uart frame is extended one bit to distinguish address charact ers from normal data characters. uart tclk uart txd 8x, 16x, or 32x start bit addr bit parity bit (optional) 5, 6, 7, or 8 data bits with the least-significant bit first 9/16 to 2 stop bits (not to scale) 4 datasheet u .com
scc uart mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 29-2 freescale semiconductor in synchronous uart (isochronous oper ation), a separate clock signal is explicitly provided with the data. start and stop bits are present in synchronous uart, but oversampling is not required because the clock is provided with each bit. the general scc mode register (gsm r) is used to configure an scc channel to function in uart mode, which provides standard serial i/ o using asynchronous character-base d (start-stop) protocols with rs-232c-type lines. using standard asynchronous bit rates and protocols, an scc uart controller can communicate with any existing rs-232- type device and provides a seri al communications port to other microprocessors and terminals (either locally or th rough modems). the independe nt transmit and receive sections, whose operations are async hronous with the core, send data fr om memory (either internal or external) to txd and receive data from rxd. the uart controller supports a multidrop mode for master/slave operations with wakeup capability on both the idle signal a nd address bit. it also supports synchronous operation where a clock (i nternal or external) must be provided with each bit received. 29.1 features the following list summarizes main features of an scc uart controller: ? flexible message-bas ed data structure ? implements synchronous and asynchronous uart ? multidrop operation ? receiver wake-up on idle line or address bit ? receive entire messages into buffers as indicated by receiver idle timeout or by control character reception ? eight control character comparison ? two address comparison in multidrop configurations ? maintenance of four 16-bit error counters ? received break character length indication ? programmable data length (5?8 bits) ? programmable fractional st op bit lengths (from 9/16 to 2 bits) in transmission ? capable of reception without a stop bit ? even/odd/force/no parity generation and check ? frame error, noise error, break, and idle detection ? transmit preamble and break sequences ? freeze transmission option with low-latency stop 29.2 normal asynchronous mode in normal asynchronous mode, the receive sh ift register receives incoming data on rxd x . control bits in the uart mode register (psmr) de fine the length and format of the uart character. bits are received in the following order: 1. start bit 2. 5?8 data bits (lsb first) 4 datasheet u .com
scc uart mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 29-3 3. address/data bit (optional) 4. parity bit (optional) 5. stop bits the receiver uses a clock 8x 16x, or 32x faster than the baud rate and samples each bit of the incoming data three times around its center. the value of the bit is determined by th e majority of those samples; if all do not agree, the noise indi cation counter (nosec) in parameter ram is incremented. when a complete character has been clocked in, the contents of the receive shift register are transferred to the receive fifo before proceeding to the receive buf fer. the cpm flags uart events, including reception errors, in scce and the rxbd status and control fields. the scc can receive fractional stop bits. the next char acter?s start bit can begin any time after the three middle samples are taken. the uart transmit shift register sends outgoing data on txd x . data is then clocked synchronously with the transm it clock, which may have either an internal or external source. characters are sent lsb first. only the data portion of the uart frame is stored in the buffe rs because start and stop bits are generated and stripped by the scc. a parity bit can be generated in transmission and checked during reception; although it is not stored in the buffer, its value can be inferred from the buffer?s reporting mechanism. similarly, the opt ional address bit is not stored in the transmit or receive buffer, but is supplied in the bd itself. parity generation and checking in cludes the optional address bit. gsmr_h[rfw] must be set for an 8-bi t receive fifo in the uart receiver. 29.3 synchronous mode in synchronous mode, the controller uses a 1x data clock for timing. the receive shift register receives incoming data on rxd x synchronous with the clock. the bit length a nd format of the se rial character are defined by the control bits in th e psmr in the same way as in asynchronous mode. when a complete byte has been clocked in, the contents of the receive shift register are transferred to the receive fifo before proceeding to the receive buffer. the cpm flags ua rt events, including reception errors, in scce and the rxbd status and control fi elds. gsmr_h[rfw] must be se t for an 8-bit receive fifo. the synchronous uart transmit shif t register sends outgoing data on txd x . data is then clocked synchronously with the transmit clock, which can have an internal or external source. 29.4 scc uart parameter ram for uart mode, the protocol-specific area of the scc parameter ram is mapped as in table 29-1 . table 29-1. uart-specific scc parameter ram memory map offset 1 name width description 0x30 ? dword reserved 0x38 max_idl hword maximum idle characters. when a character is received, the receiver begins counting idle characters. if max_idl idle characters are re ceived before the next data character, an idle timeout occurs and the buffer is closed, generating a maskable interrupt request to the core to receive the data from the buffer. thus, max_idl offers a way to demarcate frames. to disable the feature, clear max_idl. the bit le ngth of an idle character is calculated as follows: 1 + data length (5?9) + 1 (if parity is used) + number of stop bits (1?2). for 8 data bits, no parity, and 1 stop bit, the character length is 10 bits. 4 datasheet u .com
scc uart mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 29-4 freescale semiconductor 0x3a idlc hword temporary idle counter. holds the current id le count for the idle timeout process. idlc is a down-counter and does not need to be initialized or accessed. 0x3c brkcr hword break count register (transmit). determin es the number of break characters the transmitter sends. the transmitter sends a break character sequence when a stop transmit command is issued. for 8 data bits, no parity, 1 stop bit, and 1 start bit, each break character consists of 10 zero bits. 0x3e parec hword user-initialized,16-bit (modulo?2 16 ) counters incremented by the cp. parec counts received parity errors. frmec counts received characters with framing errors. nosec counts received characters with noise errors. brkec counts break conditions on the signal. a break condition can last for hundreds of bit times, yet brkec is incremented only once during that period. 0x46 brkln hword last received break length. holds the le ngth of the last received break character sequence measured in character units. for example, if rxd x is low for 20 bit times and the defined character length is 10 bits, brkln = 0 002, indicating that the br eak sequence is at least 2 characters long. brkln is accurate to within one character length. 0x48 uaddr1 hword uart address characte r 1/2. in multidrop mode, the re ceiver provides automatic address recognition for two addresses. in this case, program the lower order bytes of uaddr1 and uaddr2 with the two preferred addresses. 0x4a uaddr2 hword 0x50 character1 hword control character 1?8. these characte rs define the rx control char acters on which interrupts can be generated. 0x52 character2 hword 0x54 character3 hword 0x56 character4 hword 0x58 character5 hword 0x5a character6 hword 0x5c character7 hword 0x5e character8 hword 0x60 rccm hword receive control character mask. used to mask comparison of character1?8 so classes of control characters can be defined. a one enables the comparison , and a zero masks it. 0x62 rccr hword receive control character register. used to hold the last rejected control character (not written to the rx buffer). generates a maskable interrupt. if the core does not process the interrupt and read rccr before a new control character arrives, the previous control character is overwritten. 0x64 rlbc hword receive last break character. used in synchronous uart when psmr[rzs] = 1; holds the last break character pattern. by counting zero s in rlbc, the core can measure break length to a one-bit resolution. read rlbc by counting th e zeros written from bit 0 to where the first one was written. rlbc = 0b001xxxxxxxxxxxxx indicates two zeros; 0b1xxxxxxxxxxxxxxx indicates no zeros. note that rlbc can be used in combination with brkln above to calculate the number of bits in the break sequence: (brkln character length) + (number of zeros in rlbc). 1 from scc base. see section 28.4.1, ?scc base addresses.? table 29-1. uart-specific scc parameter ram memory map (continued) offset 1 name width description 4 datasheet u .com
scc uart mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 29-5 29.5 data-handling methods: character- or message-based an scc uart controller uses the same bd table and buffer structures as the other protocols and supports both multi buffer, message-based and si ngle-buffer, character-based operation. for character-based transfers, each character is sent with stop bits a nd parity and received into separate 1-byte buffers. a maskable interrupt is generated when each buffer is received. in a message-based environment, transfers can be made on entire messages rather than on individual characters. to simplify programming an d save processor overhead, a message is transferred as a linked list of buffers without core intervention. for example, before handling input data, a terminal driver may wait for an end-of-line character or an idle timeout rather than be inte rrupted when each character is received. conversely, ascii files can be sent as me ssages ending with an end-of-line character. when receiving messages, up to eight control characters can be configured to mark the end of a message or generate a maskable interrupt wit hout being stored in the buffer. this option is useful wh en flow control characters such as xon or xoff are needed but are not part of the received message. see section 29.9, ?receiving control characters.? 29.6 error and status reporting overrun, parity, noise, and framing er rors are reported throug h the bds and/or error counters in the uart parameter ram. signal status is indi cated in the status register; a mask able interrupt is generated when status changes. 29.7 scc uart commands the transmit commands in table 29-2 are issued to the cp command register (cpcr). table 29-2. transmit commands command description stop transmit after a hardware or software reset and a channel is enab led in the gsmr, the transmitter starts polling the first bd in the txbd table every 8 tx clocks. stop transmit disables character transmission. if the scc receives stop transmit as a message is being sent, the message is abort ed. the transmitter finishes sending data transferred to its fifo and stops. the tbptr is not advanced. the uart transmitter sends a programmable break sequence and starts sending idles. the number of break characters in the sequence (which can be zero) should be written to brkcr in the parameter ram before issuing this command. graceful stop transmit used to stop transmitting smoothly. the transmitter stops after the current bu ffer has been completely sent or immediately if no buffer is being sent. scce[gra] is se t once transmission stops, then the uart tx parameters, including the txbd, can be modified. tbptr points to the next txbd in the table. transmission begins once the r bit of the next bd is set and a restart transmit command is issued. restart transmit enables transmission. the controller expects this comman d after it disables the c hannel in its psmr, after a stop transmit command, after a graceful stop transmit command, or after a transmitter error. transmission resumes from the current bd. init tx parameters resets the transmit parameters in the parameter ram. issue only when the transmitter is disabled. note that init tx and rx parameters resets both tx and rx parameters. 4 datasheet u .com
scc uart mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 29-6 freescale semiconductor receive commands are described in table 29-3 . 29.8 multidrop systems and address recognition in multidrop systems, more than two stations ca n be on a network, each with a specific address. figure 29-2 shows two examples of this configuration. frames made up of many characters can be broadcast as long as the first charact er is the destination address. the uart fram e is extended by one bit to distinguish an address charac ter from standard data character s. programmed in psmr[um], the controller supports the foll owing two multidrop modes: ? automatic multidrop mode ? the controller checks the incomi ng address character and accepts subsequent data only if the addres s matches one of two us er-defined values. th e two 16-bit address registers, uaddr1 and uaddr2, s upport address recognition. only th e lower 8 bits are used so the upper 8 bits should be cleared; for addresses less than 8 bits, unused high-order bits should also be cleared. the incoming address is checked against uaddr1 and uaddr2. when a match occurs, rxbd[am] indicates wh ether uaddr1 or uaddr2 matched. ? manual multidrop mode ? the controller receives all characters . an address character is always written to a new buffer and can be followed by data characters. user software performs the address comparison. table 29-3. receive commands command description enter hunt mode forces the receiver to close the rxbd in use and enter hunt mode. after a hardware or software reset, once an scc is enabled in the gsmr, the receiver is automatically enabled and uses the first bd in the rxbd table. if a message is in progress, the receiver continues receiving in the next bd. in multidrop hunt mode, the receiver continually scans the input data stream for the address char acter. when it is not in multidrop mode, it waits for the idle sequence (one character of idle). data present in the rx fifo is not lost when this command is executed. close rxbd forces the scc to close the rxbd in use and use the ne xt bd for subsequent received data. if the scc is not in the process of receivin g data, no action is taken. note that in an scc uart controller, close rxbd functions like enter hunt mode but does not need to receive an idle character to continue receiving. init rx parameters resets the receive parameters in the parameter ram. shoul d be issued when the receiver is disabled. note that init tx and rx parameters resets both tx and rx parameters. 4 datasheet u .com
scc uart mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 29-7 figure 29-2. two uart multidrop configurations 29.9 receiving control characters the uart receiver can rec ognize special control char acters used in a message-based environment. eight control characters can be defined in a control character table in the uart parameter ram. each incoming character is compared to the table entries using a ma sk (the received control character mask, rccm) to strip don?t cares. if a match occurs, th e received control charact er can either be written to the receive buffer or rejected. if the received control charact er is not rejected, it is written to the receive buffer. the receive buffer is then automatically closed to allow softwa re to handle end-of-message charac ters. control characters that are not part of the actual message, su ch as xoff, can be rejected. rejected characters bypass the receive buffer and are written directly to th e received control character register (rccr), which triggers maskable interrupt. the 16-bit entries in the control character table suppor t control character recognition. each entry consists of the control character, a valid bit (end of table), and a reject bit. see figure 29-3 . tx rx 1 tx rx 2 tx rx 3 tx rx 4 tx rx tx rx tx rx tx rx slave 2 slave 3 slave 1 master uaddr1 uaddr2 pao d r choose wired-or operation in the port a open-drain register to allow multiple transmit + v r two 8-bit addresses can be automatically recognized in either configuration + v r pins to be directly connected 4 datasheet u .com
scc uart mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 29-8 freescale semiconductor table 29-4 describes the data structure used in control character recognition. offset 1 012 78 15 0x50 e r ? character1 0x52 e r ? character2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0x5e e r ? character8 0x60 1 1 ? rccm 0x62 ? rccr 1 from scc x base address. figure 29-3. control character table table 29-4. control character ta ble, rccm, and rccr descriptions offset bits name description 0x50? 0x5e 0 e end of table. in tables with eight control characters, e is always 0. 0 this entry is valid. 1 the entry is not valid and is not used. 1 r reject character. 0 a matching character is not rejected but is wri tten into the rx buffer, which is then closed. if rxbd[i] is set, the buffer closing generates a maskable interrupt through scce[rx]. a new buffer is opened if more data is in the message. 1 a matching character is written to rccr an d not to the rx buffer. a maskable interrupt is generated through scce[ccr]. th e current rx buffer is not closed. 2?7 ? reserved 8?15 charactern control character values 1?8. defines control characters to be compared to the incoming character. for characters smaller than 8 bits , the most significant bits should be zero. 0x60 0?1 0b11 must be set. used to mark the end of the control character table in case eight characters are used. setting these bits ensures correct operation during control character recognition. 2?7 ? reserved 8?15 rccm received control character mask. used to mask the comparison of character n . each rccm bit corresponds to the respective bit of character n and decodes as follows. 0 ignore this bit when comparing the incoming character to character n . 1 use this bit when comparing the incoming character to character n . 0x62 0?7 ? reserved 8?15 rccr received control character register. if t he newly arrived character matches and is rejected from the buffer (r = 1), the pip controller writes the character into the rccr and generates a maskable interrupt. if the core does not process the interrupt and read rccr before a new control character arrives, the previous control character is overwritten. 4 datasheet u .com
scc uart mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 29-9 29.10 hunt mode (receiver) a uart receiver in hunt mode remains deactivated until an idle or addres s character is recognized, depending on psmr[um]. a receiver is fo rced into hunt mode by issuing an enter hunt mode command. the receiver aborts any message in progress when enter hunt mode is issued. when the message is finished, the receiver is re-enabled by detecting the idle line (one idle character) or by the address bit of the next message, depending on psmr[um]. when a r eceiver in hunt mode receives a break sequence, it increments brkec and genera tes a brk inte rrupt condition. 29.11 inserting control characters in to the transmit data stream the scc uart transmitter can send out-of-sequence, flow-control ch aracters like xon and xoff. the controller polls the transmit out-of- sequence register (toseq), shown in figure 29-4 , whenever the transmitter is enabled for uart operation, in cluding during a uart freeze operation, uart buffer transmission, and when no buffer is ready for tr ansmission. the toseq char acter (in charsend) is sent at a higher priority than the other characters in the transmit buffer, but doe s not preempt characters already in the transmit fifo. this means that the xon or xoff character may not be sent for eight or four (scc) character times. to re duce this latency, set gsmr_h[tfl] to decrease the fifo size to one character before enabling the transmitter. table 29-5 describes toseq fields. 012345678 15 field ? rea i ct ? a charsend reset 0000_0000_0000_0000 r/w r/w offset scc base + 0x4e figure 29-4. transmit out-of-sequence register (toseq) table 29-5. toseq field descriptions bits name description 0?1 ? reserved, should be cleared. 2 rea ready. set when the character is ready for transmission. remains 1 while the character is being sent. the cp clears this bit after transmission. 3 i interrupt. if this bit is set, tr ansmission completion is flagged in th e event register (scce[tx] is set), triggering a maskable interrupt to the core. 4 ct clear-to-send lost. operates only if the scc monitors cts (gsmr_l[diag]). the cp sets this bit if cts negates when the toseq ch aracter is sent. if cts negates and the toseq character is sent during a buffer transmission, the txbd[c t] status bit is also set. 5?6 ? reserved, should be cleared. 4 datasheet u .com
scc uart mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 29-10 freescale semiconductor 29.12 sending a break (transmitter) a break is an all-zeros character with no stop bit that is sent by issuing a stop transmit command. the scc finishes transmitting outstanding data, se nds a programmable number of break characters (determined by brkcr), and reverts to idle or sends data if a restart transmit command is given before completion. when the break code is complete, the transmitter sends at least one high bit before sending more data, to guarantee recogni tion of a valid start bit. becaus e break characters do not preempt characters in the transmit fifo, th ey may not be sent for eight (scc) or four (scc) character times. to reduce this latency, set gsmr_h[tfl] to decrease th e fifo size to one character before enabling the transmitter. 29.13 sending a preamble (transmitter) sending a preamble sequence of consecuti ve ones ensures that a line is idle before sending a message. if the preamble bit txbd[p] is set, the scc sends a pr eamble sequence (idle character) before sending the buffer. for example, for 8 data bits, no parity, 1 stop bit, and 1 start bit, a preamble of 10 ones is sent before the first character in the buffer. 29.14 fractional stop bits (transmitter) the asynchronous uart transmitter, shown in figure 29-5 , can be programmed to send fractional stop bits. the fsb field in the data sync hronization register (dsr ) determines the fracti onal length of the last stop bit to be sent. fsb can be modi fied at any time. if two stop bits are sent, only the se cond is affected. idle characters are always se nt as full-length characters. 7 a address. setting this bit indicates an address character for multidrop mode. 8?15 charsend character send. contains the character to be sent. any 5- to 8-bit character value can be sent in accordance with the uart configur ation. the character should be pl aced in the lsbs of charsend. this value can be changed only while rea = 0. 01 456789101112131415 field? fsb ??????????? reset0 1111 11001111110 r/w r/w offset figure 29-5. asynchronous uart transmitter table 29-5. toseq field descriptions (continued) bits name description 4 datasheet u .com
scc uart mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 29-11 table 29-6 describes dsr fields. 29.15 handling errors in the scc uart controller the uart controller reports character reception and transmission error conditions through the bds, the error counters, and the scce. modem interface line s can be monitored by the port c pins. transmission errors are described in table 29-7 . table 29-6. dsr fields descriptions bits name description 0?0b0 1?4 fsb fractional stop bits. for 16 oversampling: 1111 last transmitted stop bit 16/16. default value after reset. 1110 last transmitted stop bit 15/16 .? 1000 last transmitted stop bit 9/16. 0xxx invalid. do not use. for 32 oversampling: 1111 last transmitted stop bit 32/32. default value after reset. 1110 last transmitted stop bit 31/32. .? 0000 last transmitted stop bit 17/32. for 8 oversampling: 1111 last transmitted stop bit 8/8. default value after reset. 1110 last transmitted stop bit 7/8. 1101 last transmitted stop bit 6/8. 1100 last transmitted stop bit 5/8. 10xx invalid. do not use. 0xxx invalid. do not use. the uart receiver can always receive fractional stop bits. the next character?s start bit can begin any time after the three middle samples have been taken. 5?6 ? 0b11 7?8 ? 0b00 9?14 ? 0b111111 15 ? 0b0 table 29-7. transmission errors error description cts lost during character transmission when cts negates during transmission, the channel stops afte r finishing the current character. the cp sets txbd[ct] and generates the tx interrupt if it is not masked. the channel resumes transmission after the restart transmit command is issued and cts is asserted. note that if cts is used, the uart also offers an asynchronous flow control option that does not generate an error. see the description of psmr[flc] in ta b l e 2 9 - 9 . 4 datasheet u .com
scc uart mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 29-12 freescale semiconductor reception errors are described in table 29-8 . 29.16 uart mode register (psmr) for uart mode, the scc protocol-sp ecific mode register (p smr) is called the uart mode register. many bits can be modified while the receiver and transmitter are enabled. figure 29-6 shows the psmr in uart mode. table 29-8. reception errors error description overrun occurs when the channel overwrites the previous char acter in the rx fifo with a new character, losing the previous character. the channel then writes the new ch aracter to the buffer, closes it, sets rxbd[ov], and generates an rx interrupt if not masked. in auto matic multidrop mode, the receiver enters hunt mode immediately. cd lost during character reception if this error occurs and the channel is using this pin to automatically control reception, the channel terminates character reception, closes the buffer, sets rxbd[cd], and generates the rx interrupt if not masked. this error has the highest priority. the last character in the buffer is lost and other errors are not checked. in automatic multidrop mode, the receiver enters the hunt mode immediately. parity when a parity error occurs, the channel writes the received character to the buffer, closes the buffer, sets rxbd[pr], and generates the rx interrupt if not masked. the channel also increments the parity error counter parec. in automatic multidrop mode, th e receiver enters hunt mode immediately. noise a noise error occurs when the three samples of a bit are not identical. when this error occurs, the channel writes the received character to the buffer, proceeds normally , but increments the noise error counter nosec. note that this error does not occur in synchronous mode. idle sequence receive if the uart is receiving data and gets an idle characte r (all ones), the channel begins counting consecutive idle characters received. if max_idl is reached, the buffer is closed and an rx interrupt is generated if not masked. if no buffer is open, this event does not generate an inte rrupt or any status informati on. the internal idle counter (idlc) is reset every time a character is received. to disable the idle sequence function, clear max_idl. framing the uart reports a framing errors when it receives a character with no stop bit, regardless of the mode. the channel writes the received character to the buffer, clos es it, sets rxbd[fr], generates the rx interrupt if not masked, increments frmec, but does not check parity for this character. in automatic multidrop mode, the receiver immediately enters hunt mode. if the uart al lows data with no stop bits (psmr[rzs] = 1) when in synchronous mode (psmr[syn] = 1), framing errors are reported but reception continues assuming the unexpected zero is the start bit of the next character; in this case, the user may ignore a reported framing error until multiple framing errors occur within a short period. break sequence when the first break sequence is received, the uart increments the break error counter brkec. it updates brkln when the sequence completes. after the first 1 is received, the uart sets scce[brke], which generates an interrupt if not masked. if the uart is receiv ing characters when it receives a break, it closes the rx buffer, sets rxbd[br], and sets scce[rx], which ca n generate an interrupt if not masked. if psmr[rzs] = 1 when the uart is in synchronous mode, a break sequence is detected after two successive break characters are received. 4 datasheet u .com
scc uart mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 29-13 table 29-9 describes psmr uart fields. 0123456789101112131415 field flc sl cl um frz rzs syn drt ? pen rpm tpm reset 0 r/w r/w offset 0x9_1a08 (psmr1); 0x9_1a 48 (psmr3); 0x9_1a68 (psmr4) figure 29-6. protocol-specific mode register for uart (psmr) table 29-9. psmr uart field descriptions bits name description 0 flc flow control 0 normal operation. the gsmr and port c registers determine the mode of cts . 1 asynchronous flow control. when cts is negated, the transmitter stops at the end of the current character. if cts is negated past the middle of the current character, the next full character is sent before transmission stops. when cts is asserted again, transmission continues where it left off and no cts lost error is reported. only idle characters are sent while cts is negated. 1 sl stop length. selects the number of stop bits the scc sends. sl can be modified on-the-fly. the receiver is always enabled for one stop bit unless the scc uart is in synchronous mode and psmr[rzs] is set. fractional stop bits are configured in the dsr. 0 1stop bit 1 2 stop bits 2?3 cl character length. determines the number of data bits in the character, not including optional parity or multidrop address bits. if a character is less than 8 bi ts, most-significant bits are received as zeros and are ignored when the character is se nt. cl can be modified on-the-fly. 00 5 data bits 01 6 data bits 10 7 data bits 11 8 data bits 4?5 um uart mode. selects the asynchronous chann el protocol. um can be modified on-the-fly. 00 normal uart operation. multidrop mode is disabled and idle-line wake-up mode is selected. the uart receiver leaves hunt mode by receiving an idle character (all ones). 01 manual multidrop mode. an additional address/data bit is sent with each character. multidrop asynchronous modes are compatible with the mc68681 duart, mc68hc11 sci, dsp56000 sci, and intel 8051 serial interface. the receiver leaves hunt mode when the address/data bit is a one, indicating the received character is an address that all inactive processors must process. the controller receives the address character and writes it to a new buffer. the core then compares the wr itten address with its own address and decides whether to ignore or process subsequent characters. 10 reserved. 11 automatic multidrop mode. the cpm compares th e address of an incoming address character with uaddr x parameter ram values; subsequent data is accepted only if a match occurs. 6 frz freeze transmission. allows the uart transmit ter to pause and later continue from that point. 0 normal operation. if the buffer was previously frozen , it resumes transmission fr om the next character in the same buffer that was frozen. 1 the scc completes transmission of any data already transfe rred to the tx fifo (the number of characters depends on gsmr_h[tfl]) and then freezes. after frz is cleared, transmission resumes from the next character. 4 datasheet u .com
scc uart mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 29-14 freescale semiconductor 29.17 scc uart receive buffer descriptor (rxbd) the cpm uses rxbds to report on each buffer received. the cpm closes the current buffer, generates a maskable interrupt, and starts receiving data into the next buffer after one of the following occurs: ? a user-defined control character is received. ? an error occurs during message processing. ? a full receive buffer is detected. ? a max_idl number of consecutive idle characters is received. ?an enter hunt mode or close rxbd command is issued. 7 rzs receive zero stop bits 0 the receiver operates normally, but at least one stop bit is needed between characters. a framing error is issued if a stop bit is missing. break status is set if an all-zero character is received with a zero stop bit. 1 configures the receiver to receive data without stop bits. useful in v.14 applications where scc uart controller data is supplied synchronously and all stop bi ts of a particular character can be omitted for cross-network rate adaptation. rzs shou ld be set only if syn is set. the receiver continues if a stop bit is missing. if the stop bit is a zero, the next bit is consi dered the first data bit of the next character. a framing error is issued if a stop bit is missing, but a brea k status is reported only af ter two consecutive break characters have no stop bits. 8 syn synchronous mode 0 normal asynchronous operation. gsmr_l[tenc, renc] must select nrz and gsmr_l[tdcr, rdcr] select either 8 , 16 , or 32 . 16 is recommended for most applications. 1 synchronous scc uart controller using 1 clock (isochronous uart operation). gsmr_l[tenc, renc] must select nrz and gsmr _l[rdcr, tdcr] select 1 mode. a bit is transferred with each clock and is synchronous to the clock, which can be internal or external. 9 drt disable receiver while transmitting 0 normal operation 1 while the scc is sending data, the internal rts disables and gates the receiver. useful for a multidrop configuration in which the user does not want to re ceive its own transmission. for multidrop uart mode, set the bds? preamble bit, txbd[p]. 10 ? reserved, should be cleared. 11 pen parity enable 0 no parity 1 parity is enabled and determined by the parity mode bits. 12?13, 14?15 rpm, tpm receiver/transmitter parity mode. selects the type of parity check the receiver/transmitter performs; can be modified on-the-fly. receive parity errors can be ignored but not disabled. 00 odd parity. if a transmitter counts an even number of ones in the data word, it sets the parity bit so an odd number is sent. if a receiver receives an even number, a parity error is reported. 01 low parity (space parity). a transmitter sends a zero in the parity bit position. if a receiver does not read a 0 in the parity bit, a parity error is reported. 10 even parity. like odd parity, the transmitter adjusts the parity bit, as necessary, to ensure that the receiver receives an even number of one bits; otherwise, a parity error is reported. 11 high parity (mark parity). the transmitter sends a one in the parity bit position. if the receiver does not read a 1 in the parity bit, a parity error is reported. table 29-9. psmr uart field descriptions (continued) bits name description 4 datasheet u .com
scc uart mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 29-15 ? an address character is received in multidrop m ode. the address character is written to the next buffer for a software comparison. figure 29-7 shows an example of how rxbds are used in receiving. figure 29-7. scc uart receiving using rxbds byte 5 buffer 0 0008 32-bit buffer pointer 0 eid rxbd 0 status length pointer 0 0002 32-bit buffer pointer 1 eid rxbd 1 status length pointer 0 0004 32-bit buffer pointer 0 eid rxbd 2 status length pointer 1 xxxx 32-bit buffer pointer e rxbd 3 status length pointer byte 1 byte 2 byte 8 buffer byte 9 byte 10 buffer byte 1 byte 2 byte 3 buffer byte 4 error! empty additional bytes will be stored unless idle count expires (max_idl) 8 bytes 8 bytes 8 bytes 8 bytes characters received by uart fourth character 10 characters long idle period has framing error! present time time 5 characters buffer full idle time-out occurred byte 4 has framing error reception still in progress with this buffer 1 fr etc. empty mrblr = 8 bytes for this scc 4 datasheet u .com
scc uart mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 29-16 freescale semiconductor figure 29-8 shows the scc uart rxbd. table 29-10 describes rxbd status and control fields. 0123456789101112131415 offset + 0 e ? w i c a cm id am ? br fr pr ? ov cd offset + 2 data length offset + 4 rx buffer pointer offset + 6 figure 29-8. scc uart receive buffer descriptor (rxbd) table 29-10. scc uart rxbd status and control field descriptions bits name description 0eempty 0 the buffer is full or reception was aborted due to an erro r. the core can read or write to any fields of this bd. the cpm does not reuse this bd while e = 0. 1 the buffer is not full. the cpm controls this bd and buffer. the core should not modify this bd. 1 ? reserved, should be cleared. 2 w wrap (last buffer descriptor in the bd table) 0 not the last descriptor in the table 1 last descriptor in the table. after this buffer is used, the cpm receives incoming data using the bd pointed to by rbase. the number of bds in this table is programmable and determined only by the w bit and overall space constraints of the dual-port ram. 3 i interrupt 0 no interrupt is generated after this buffer is filled. 1 the cp sets scce[rx] when this buffer is completely filled by the cpm, indicating the need for the core to process the buffer. setting scce[rx] causes an interrupt if not masked. 4 c control character 0 this buffer does not contain a control character. 1 the last byte in this buffer matches a user-defined control character. 5aaddress 0 the buffer contains only data. 1 for manual multidrop mode, a indicates the first byte of this buffer is an address byte. software should perform address comparison. in automatic multidr op mode, a indicates the buffer contains a message received immediately after an address matched uaddr1 or uaddr2. the address itself is not written to the buffer but is indicated by the am bit. 6 cm continuous mode 0 normal operation. the cpm clears e after this bd is closed. 1 the cpm does not clear e after this bd is closed, allowing the buffer to be overwritten when the cpm accesses this bd again. e is cleared if an error occurs during reception, regardless of cm. 7 id buffer closed on reception of idles. the buffer is clos ed because a programmable number of consecutive idle sequences (max_idl) was received. 8 am address match. significant only if the address bit is set and automatic multidrop mode is selected in psmr[um]. after an address match, am identifies which user-defined address character was matched. 0 the address matched the value in uaddr2. 1 the address matched the value in uaddr1. 4 datasheet u .com
scc uart mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 29-17 section 28.3, ?scc buffer descriptors (bds),? describes the data length and buffer pointer fields. 29.18 scc uart transmit buffer descriptor (txbd) the cpm uses bds to confirm transmission and indicat e error conditions so the core knows that buffers have been serviced. figure 29-9 shows the scc uart txbd. table 29-11 describes txbd status and control fields. 9 ? reserved, should be cleared. 10 br break received. set when a break sequence is received as data is being received into this buffer 11 fr framing error. set when a character with a framing error (a character without a stop bit) is received and located in the last byte of this buffer. a new rx buffer is used to receive subsequent data. 12 pr parity error. set when a character with a parity error is received and located in the last byte of this buffer. a new rx buffer is used to receive subsequent data. 13 ? reserved, should be cleared. 14 ov overrun. set when a receiver overrun occurs during reception 15 cd carrier detect lost. set when the carrier detect signal is negated during reception 0123456789 1415 offset + 0 r ? w i cr a cm p ns ? ct offset + 2 data length offset + 4 tx buffer pointer offset + 6 figure 29-9. scc uart transmit buffer descriptor (txbd) table 29-11. scc uart txbd status and control field descriptions bits name description 0 r ready 0 the buffer is not ready. this bd and buffer can be modified. the cpm automatically clears r after the buffer is sent or an error occurs. 1 the user-prepared buffer is waiting to begin transmi ssion or is being transmitted. do not modify the bd once r is set. 1 ? reserved, should be cleared. 2 w wrap (last buffer descriptor in txbd table) 0 not the last bd in the table 1 last bd in the table. after this buffer is used, t he cpm sends data using the bd pointed to by tbase. the number of txbds in this table is determined only by the w bit and space constraints of the dual-port ram. 3 i interrupt 0 no interrupt is generated after this buffer is processed. 1 scce[tx] is set after this buffer is proces sed by the cpm, which can cause an interrupt. table 29-10. scc uart rxbd status and control field descriptions (continued) bits name description 4 datasheet u .com
scc uart mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 29-18 freescale semiconductor the data length and buffer point er fields are described in section 28.3, ?scc buffer descriptors (bds).? 29.19 scc uart event register (s cce) and mask register (sccm) the scc event register (scce) is used to report events recognized by the uart channel and to generate interrupts. when an event is rec ognized, the controller sets the corresponding scce bi t. interrupts can be masked in the uart mask regist er (sccm), which has the same fo rmat as scce. setting a mask bit enables the corresponding scce in terrupt; clearing a bit masks it. figure 29-10 shows example interrupts that can be generated by the scc uart controller. 4 cr clear-to-send report 0 the next buffer is sent with no delay (assuming it is ready), but if a cts lost condition occurs, txbd[ct] may not be set in the correct txbd or may not be set at all. asynchronous flow co ntrol, however, continues to function normally. 1normal cts lost error reporting and three bits of idle are sent between consecutive buffers. 5 a address. valid only in multidrop mode?automatic or manual 0 this buffer contains only data. 1 this buffer contains address characters. all data in this buffer is sent as address characters. 6 cm continuous mode 0 normal operation. the cpm clears r after this bd is closed. 1 the cpm does not clear r after this bd is closed, allowing the buffer to be resent next time the cpm accesses this bd. however, r is cleared by transmission errors, regardless of cm. 7ppreamble 0 no preamble sequence is sent. 1 before sending data, the controller sends an idle characte r consisting of all ones. if the data length of this bd is zero, only a preamble is sent. 8 ns no stop bit or shaved stop bit sent. 0 normal operation. stop bits are sent with all characters in this buffer. 1 if psmr[syn] = 1, data in this buffer is sent without stop bits. if syn = 0, the stop bit is shaved, depending on the dsr setting; see section 29.14, ?fractional stop bits (transmitter).? 9?14 ? reserved, should be cleared. 15 ct cts lost. the cpm writes this status bit after sending the associated buffer. 0cts remained asserted during transmission. 1cts negated during transmission. table 29-11. scc uart txbd status and control field descriptions (continued) bits name description 4 datasheet u .com
scc uart mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 29-19 figure 29-10. scc uart interrupt event example scce bits are cleared by writing ones; writing zeros has no effect. unmask ed bits must be cleared before the cpm clears an internal interrupt request. figure 29-11 shows scce/sccm for uart operation. 0123456789101112131415 field ? ab idl gra brke brks ? ccr bsy tx rx reset 0000_0000_0000_0000 r/w r/w offset 0x9_1a10 (scce1); 0x9_1a50 (scce3); 0x9_1a70 (scce4) 0x9_1a14 (sccm1); 0x9_1a54 (sccm3); 0x9_1a74 (sccm4) figure 29-11. scc uart event register (scce) and mask register (sccm) cd idl rx ccr idl rx idl brks brke idl cd break line idle 10 characters rxd cd characters received by uart time line idle txd rts characters transmitted by uart cts tx cts cts line idle line idle 7 characters notes: uart scce events 1. the first rx event assumes rx buffers are 6 bytes each. 2. the second idl event occurs after an all-ones character is received. 3. the second rx event position is pr ogrammable based on the max_idl value. 4. the brks event occurs after the first break character is received. 5. the cd event must be programmed in the port c parallel i/o, not in the scc itself. legend: a receive control character defined not to be stored in the rx buffer. notes: uart scce events 1. tx event assumes all seven characters were put into a single buffer and txbd[cr] = 1. 2. the cts event must be programmed in the port c parallel i/o, not in the scc itself. 4 datasheet u .com
scc uart mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 29-20 freescale semiconductor table 29-12 describes scce fields for uart mode. 29.20 scc uart status register (sccs) the scc uart status register (sccs), shown in figure 29-12 , monitors the real-time status of rxd. table 29-12. scce/sccm field descriptions for uart mode bits name description 0?5 ? reserved, should be cleared. 6 ab autobaud. set when an autobaud lock is detected. the core should rewr ite the baud rate generator with the precise divider value. see chapter 25, ?baud-rate generators (brgs).? 7 idl idle sequence status changed. set when the channel det ects a change in the serial line. the line?s real-time status can be read in sccs[id]. idle is entered when a character of all ones is received; it is exited when a zero is received. 8 gra graceful stop complete. set as soon as the transmitter finishes any buffer in progress after a graceful stop transmit command is issued. it is set immediately if no buffer is in progress. 9 brke break end. set when an idle bit is received after a break sequence. 10 brks break start. set when the first character of a break sequence is re ceived. multiple brks events are not received if a long break sequence is received. 11 ? reserved, should be cleared. 12 ccr control character received and rejected. set when a co ntrol character is recognized and stored in the receive control character register rccr. 13 bsy busy. set when a character is received and discarded due to a lack of buffers. in multidrop mode, the receiver automatically enters hunt mode; otherwise , reception continues when a buffer is available. the latest point that an rxbd can be changed to empty and guarantee av oiding the busy condition is the middle of the stop bit of the first character to be stored in that buffer. 14 tx tx event. set when a buffer is sent. if txbd[cr] = 1, tx is set no sooner than when the last stop bit of the last character in the buffer begins transmission. if txbd[ cr] = 0, tx is set after the last character is written to the tx fifo. tx also represents a cts lost error; check txbd[ct]. 15 rx rx event. set when a buffer is received, which is no soo ner than the middle of the first stop bit of the character that caused the buffer to close. also represents a general receiver error (overrun, cd lost, parity, idle sequence, and framing errors); the rxbd status and control fields indicate the specific error. 0 67 field ? id reset 0000_0000_0000_0000 r/w r offset 0x9_1a17 (sccs1); 0x9_1a57 (sccs3); 0x9_1a77 (sccs4) figure 29-12. scc status register for uart mode (sccs) 4 datasheet u .com
scc uart mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 29-21 table 29-13 describes uart sccs fields. 29.21 s-records loader application this section describes a downloadi ng application that uses an scc uart controller. the application performs s-record downloads and upl oads between a host computer and an intelligent peripheral through a serial asynchronous line. s-records are strings of ascii characters that begin with ?s? and end in an end-of-line character. this characteristic is used to impose a message st ructure on the communication between the devices. for flow contro l, each device can transmit xon and xoff characters, which are not part of the program bei ng uploaded or downloaded. to receive s-records, the core must wait for an rx interrupt, indicatin g that a complete s-record buffer was received. transmission requires assembling s-reco rds into buffers and linking them to the txbd table; transmission can be paused when an xoff character is received. this scheme minimizes the number of interrupts the core receives (one per s-re cord) and relieves it from continually scanning for control characters. table 29-13. uart sccs field descriptions bits name description 0?6 ? reserved, should be cleared. 7 id idle status. set when rxd has been a logic one for at least a full character time. 0 the line is not idle. 1 the line is idle. table 29-14. uart control characters for s-records example character description line feed both the e and r bits should be cleared. when an end-of-lin e character is received, the current buffer is closed and made available to the core for processing. this buffer co ntains an entire s record that the processor can now check and copy to memory or disk as required. xoff e should be cleared; r should be set. whenever the core receives a control-character-received (ccr) interrupt and the rccr contains xoff, the software should immediat ely stop transmitting by sett ing psmr[frz]. this keeps the other station from losing data when it runs out of rx buffers. xon xon should be received after xoff. e should be clea red and r should be set. psmr[frz] on the transmitter should now be cleared. the cpm automatically resumes tran smission of the serial line at the point at which it was previously stopped. like xoff, the xon charac ter is not stored in the receive buffer. 4 datasheet u .com
scc uart mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 29-22 freescale semiconductor 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 30-1 chapter 30 scc hdlc mode high-level data link co ntrol (hdlc) is one of the most common pr otocols in the data link layer, layer 2 of the osi model. many other common layer-2 prot ocols, such as sdlc, ss#7, appletalk, lapb, and lapd, are based on hdl c and its framing structure in particular. figure 30-1 shows the hdlc framing structure. hdlc uses a zero insertion/deletion process (bit-stuffi ng) to ensure that a data bit pattern matching the delimiter flag does not occur in a field between flag s. the hdlc frame is sy nchronous and relies on the physical layer for clocking and synchr onization of the transmitter/receiver. an address field is needed to carry the frame's dest ination address because the layer 2 frame can be sent over point-to-point links, broadcast ne tworks, packet-switched or circui t-switched systems. an address field is commonly 0, 8, or 16 bits, depending on the data link layer pr otocol. sdlc and lapb use an 8-bit address. ss#7 has no address field because it is always used in poi nt-to-point signal ing links. lapd divides its 16-bit address into diff erent fields to specify various acc ess points within one device. lapd also defines a broadcast address. some hdlc- type protocols permit addressing beyond 16 bits. the 8- or 16-bit control field provides a flow control number and defines the frame type (control or data). the exact use and structure of this field depends on the protocol using the frame. the length of the data in the data field depends on the frame protocol. layer 3 frames are carried in this data field. error control is implemented by appending a cyclic re dundancy check (crc) to the frame, which in most protocols is 16 bits long but can be as long as 32 bits. in hdlc, the lsb of each octet is sent first; the msb of the crc is sent first. hdlc mode is selected for an scc by writing gsmr_l[mode] = 0b0000. in a nonmultiplexed modem interface, scc outputs connect direc tly to external pins. modem signals ca n be supported through port c. the rx and tx clocks can be supplied from either the bank of baud rate generators, by the dpll, or externally. an scc can also be c onnected through the tdm channels of the serial interface (si). in hdlc mode, an scc becomes an hdlc controller, and consists of separate transmit a nd receive sections whose operations are asynchronous with the core and can either be synchronous or asynchronous with respect to other sccs. 30.1 scc hdlc features the main features of an sc c in hdlc mode are follows: ? flexible buffers with multiple buffers per frame ? separate interrupts for frames and buffers (rx and tx) ? received-frames threshold to reduce interrupt overhead ? can be used with the scc dpll 4 datasheet u .com
scc hdlc mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 30-2 freescale semiconductor ? four address comparison registers with mask ? maintenance of five 16-bit error counters ? flag/abort/idle generation and detection ? zero insertion/deletion ? 16- or 32-bit crc-ccitt generation and checking ? detection of nonocte t aligned frames ? detection of frames that are too long ? programmable flags (0?15) between successive frames ? automatic retransmission in case of collision 30.2 scc hdlc channel frame transmission the hdlc transmitter is de signed to work with little or no core intervention. once enabled by the core, a transmitter starts sending flags or idles as program med in the hdlc mode re gister (psmr). the hdlc polls the first bd in the txbd table. when there is a frame to transmit, the scc fetches the data (address, control, and information) from th e first buffer and starts sending the frame after inserting the minimum number of flags specified between frames. when the end of the current buffer is reached and txbd[l] (last buffer in frame) is set, the scc appends the crc and closing flag. in hdlc mode, the lsb of each octet and the msb of the crc are sent first. figure 30-1 shows a typical hdlc frame. figure 30-1. hdlc framing structure after a closing flag is sent, the scc updates the frame status bits of the bd and clears txbd[r] (buffer ready). at the end of the current buf fer, if txbd[l] is not set (multi ple buffers per frame), only txbd[r] is cleared. before the scc proceeds to the next txbd in the table, an interrupt can be issued if txbd[i] is set. this interrupt programmabilit y allows the core to intervene after each buffer, after a specific buffer, or after each frame. the stop transmit command can be used to expe dite critical data ahead of previously linked buffers or to support efficient error handling. when the scc receives a stop transmit command, it sends idles or flags instead of the current frame until it receives a restart transmit command. the graceful stop transmit command can be used to insert a high-prio rity frame without abor ting the current one?a graceful-stop-complete event is generated in scce [gra] when the current frame is finished. see section 30.6, ?scc hdlc commands.? 30.3 scc hdlc channel frame reception the hdlc receiver is designed to work with little or no core intervention to perform address recognition, crc checking, and maximum frame length checking. re ceived frames can be us ed to implement any hdlc-based protocol. opening flag address control information (optional) crc closing flag 8 bits 16 bits 8 bits 8 n bits 16 bits 8 bits 4 datasheet u .com
scc hdlc mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 30-3 once enabled by the core, the receiver waits for an opening flag characte r. when it detects the first byte of the frame, the scc compares the frame address with four user-programmable, 16-bit address registers and an address mask. the scc compar es the received address field with the user-defined values after masking with the address mask. to detect broadcast (a ll ones) address frames, one address register must be written with all ones. if an address match is detected, the scc fetches the next bd and sc c starts transferring the incoming frame to the buffer if it is empty. when the buf fer is full, the scc clears rxbd[e] and generates a maskable interrupt if rxbd[i] is set. if the incomi ng frame is larger than the current buffer, the scc continues receiving using th e next bd in the table. during reception, the scc checks for frames that are too long (using mflr). when the frame ends, the crc field is checked against the recalculated value a nd written to the buffer. rxbd[data length] of the last bd in the hdlc frame contains the entire frame length. this also enables so ftware to identify the frames in which the maximum frame length violatio ns occur. the scc sets rxbd[l] (last buffer in frame), writes the frame status bits , and clears rxbd[e]. it then gene rates a maskable event (scce[rxf]) to indicate a frame was received. the scc then wait s for a new frame. back-to-back frames can be received with only one shar ed flag between frames. the received frames threshold parameter (rfthr) can be used to postpone interrupts until a specified number of frames is receiv ed. this function can be combined with a timer to implement a timeout if fewer than the specified number of threshold frames is received. note that sccs in hdlc mode, or any other synchronous m ode, must receive a mini mum of eight clocks after the last bit arrives to account for rx fifo delay. 30.4 scc hdlc parameter ram for hdlc mode, the protocol-specific area of the scc parameter ram is mapped as in table 30-1 . table 30-1. hdlc-specific sc c parameter ram memory map offset 1 name width description 0x30 ? word reserved 0x34 c_mask word crc mask. for the 16-bit crc-ccitt, initia lize with 0x0000_f0b8. for 32-bit crc-ccitt, initialize with 0xdebb_20e3. 0x38 c_pres word crc preset. for the 16-bit crc-ccitt, init ialize with 0x0000_ffff. for 32-bit crc-ccitt, initialize with 0xffff_ffff. 0x3c disfc hword modulo 2 16 counters maintained by the cp. initialize them while the channel is disabled. disfc (discarded frame counter) counts error-fr ee frames discarded due to lack of free buffers. crcec (crc error counter) includes frames not addressed to the user or frames received in the bsy condition, but does not include overrun errors. abtsc (abort sequence counter) nmarc (nonmatching address received counter) includes error-free frames only. retrc (frame retransmission counter) counts number of frames re sent due to collision. 0x3e crcec hword 0x40 abtsc hword 0x42 nmarc hword 0x44 retrc hword 4 datasheet u .com
scc hdlc mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 30-4 freescale semiconductor figure 30-2 shows 16- and 8-bit address recognition. figure 30-2. hdlc address recognition 30.5 programming the scc in hdlc mode hdlc mode is selected for an scc by writing gs mr_l[mode] = 0b0000. the hdlc controller uses the same buffer and bd data structure as other m odes and supports multi buff er operation and address 0x46 mflr hword max frame length register. the hdlc co mpares the incoming hdlc frame?s length with the user-defined limit in mflr. if th e limit is exceeded, the rest of the frame is discarded and rxbd[lg] is set in the last bd of that frame. at the end of the frame the scc reports frame status and frame length in the last rxbd. the mf lr is defined as all in-frame bytes between the opening and closing flags. 0x48 max_cnt hword maximum length counter. a tempor ary down-counter used to track frame length. 0x4a rfthr hword received frames threshold. used to reduce potential interrupt overhead when each in a series of short hdlc frames causes an scce[rxf] even t. setting rfthr dete rmines the frequency of rxf interrupts, which occur only when the rfthr limit is reached. provide enough empty rxbds for the number of frames specified in rfthr. 0x4c rfcnt hword received frames count. rfcnt is a down-counter used to implement rfthr. 0x4e hmask hword mask register (hmask) and four address registers (haddr n ) for address recognition. the scc reads the frame address from the hdlc receiver, compares it with the haddrs, and masks the result with hmask. se tting an hmask bit enables the corresponding comparison bit, clearing a bit masks it. when a match occurs, the frame addr ess and data are written to the buffers. when no match occurs and a frame is error-free, the nonmatching address received counter (nmarc) is incremented. the eight low-order bits of haddr n should contain the first address byte after the opening flag. for example, to recognize a frame that begins 0x7e (flag), 0x68, 0xaa, using 16-bit address recognition, haddr n should contain 0xaa68 and hmask should contain 0xffff. for 8-bit addresses, clear the eight high-order hmask bits. see figure 30-2 . 0x50 haddr1 hword 0x52 haddr2 hword 0x54 haddr3 hword 0x56 haddr4 hword 0x58 tmp hword temporary storage 0x5a tmp_mb hword temporary storage 1 from scc base. see section 28.4.1, ?scc base addresses.? table 30-1. hdlc-specific scc parameter ram memory map (continued) offset 1 name width description flag 0x7e etc. flag 0x7e address 0x68 address 0xaa control 0x44 etc. address 0x55 control 0x44 16-bit address recognition 8-bit address recognition 0x00ff hmask 0xxx55 haddr1 0xxx55 haddr2 0xxx55 haddr3 0xxx55 haddr4 0xffff hmask 0xaa68 haddr1 0xffff haddr2 0xaa68 haddr3 0xaa68 haddr4 recognizes one 16-bit address (haddr1) and the 16-bit broadcast address (haddr2) recognizes a single 8-bit address (haddr1) 4 datasheet u .com
scc hdlc mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 30-5 comparisons. receive errors are reported through the rxbd; tran smit errors are reported through the txbd. 30.6 scc hdlc commands the transmit and recei ve commands are issued to the cp comm and register (cpcr). transmit commands are described in table 30-2 . receive commands are described in table 30-3 . table 30-2. transmit commands command description stop transmit after a hardware or software reset and a channel is enab led in the gsmr, the transmitter starts polling the first bd in the txbd table every 64 tx clocks, or immediately if todr[tod] = 1, and begins sending data if txbd[r] is set. if the scc receives the stop transmit command while not transmitting, the transmitter stops polling the bds. if the scc receives the command during transmission, transmission is aborted after a maximum of 64 additional bits, the tx fifo is flushed, and the curre nt bd pointer tbptr is not advanced (no new bd is accessed). the transmitter then sends an abort sequence (0x7f) and stops polling the bds. when not transmitting, the channel sends flags or idles as programmed in the gsmr. note that if psmr[mff] = 1, multiple small frames could be flushed from the tx fifo; a graceful stop transmit command prevents this. graceful stop transmit stops transmission smoothly. unlike a stop transmit command, it stops transmission after the current frame is finished or immediately if no frame is being sent. scce[gra] is set when transmission stops. hdlc tx parameters and txbds can then be updated. tbptr points to the next txbd. transmission begins once txbd[r] of the next bd is set and a restart transmit command is issued. restart transmit enables frames to be sent on the transmit channel. the hdlc controller expects this command after a stop transmit is issued and the channel in its gsmr is disabled, after a graceful stop transmit command, or after a transmitter error. the transmitt er resumes from the current bd. init tx parameters resets the tx parameters in the parameter ram. issue only when the transmitter is disabled. init tx and rx parameters resets both tx and rx parameters. table 30-3. receive commands command description enter hunt mode after a hardware or software reset, once an scc is enabl ed in the gsmr, the receiver is automatically enabled and uses the first bd in the rxbd table. while the scc is looking for the beginning of a frame, that scc is in hunt mode. the enter hunt mode command is used to force the hdlc receiver to stop receiving the current frame and enter hunt mode, in which the hdlc continually scans the input data stream for a flag sequence. after receiving the command, the buffer is closed and the crc is reset. further frame reception uses the next bd. close rxbd should not be used in the hdlc protocol. init rx parameters resets the rx parameters in the parameter ram.; iss ue only when the receiver is disabled. note that init tx and rx parameters resets both tx and rx parameters. 4 datasheet u .com
scc hdlc mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 30-6 freescale semiconductor 30.7 handling errors in the scc hdlc controller the scc hdlc controller reports fr ame reception and transmission errors using bds, error counters, and the scce. transmission errors are described in table 30-4 . reception errors are described in table 30-5 . table 30-4. transmit errors error description tr a n s m i t t e r underrun the channel stops transmitting, closes the buffer, sets txbd[un], and generates a t xe interrupt if not masked. transmission resumes when a restart transmit command is issued. the scc send and receive fifos are 32 bytes each. cts lost during frame transmission the channel stops transmitting, closes the buffer, sets txbd[ct], and generates the txe interrupt if not masked. transmissi on resumes after a restart transmit command. if this error occurs on the first or second buffer of the frame and psmr[rte] = 1, the channel resends the frame when cts is reasserted and no error is reported. if collisions are possible, to ensure proper re transmission of multi-buffer frames, the first two buffers of each frame should in total contain more than 36 bytes for scc or 20 bytes for scc. the channel also increments the retransmission coun ter retrc in the parameter ram. table 30-5. receive errors error description overrun each scc maintains an internal fifo for receivin g data. the cp begins programming the sdma channel (if the buffer is in external memory) and updating the crc when a full or partial fifo?s worth of data (according to gsmr_h[rfw]) is received in the rx fifo. when an rx fifo overrun occurs, the previous byte is overwritten by the next byte. the previous data byte and t he frame status are lost. the channel closes the buffer with rxbd[ov] set and generates an rxf interrupt if not masked. the receiver then enters hunt mode. even if an overrun occurs during a frame whose address is not recognized, an rxbd with data length two is opened to report the overrun and the interrupt is generated. cd lost during frame reception highest priority error. the channel stops frame recepti on, closes the buffer, sets rxbd[cd], and generates the rxf interrupt if not masked. the rest of the frame is lost and other errors are not checke d in that frame. at this point, the receiver enters hunt mode. abort sequence occurs when seven or more consecutive ones are receiv ed. when this occurs while receiving a frame, the channel closes the buffer, sets rxbd[ab] and gene rates a maskable rxf interrupt. the channel also increments the abort sequence counter abtsc. the crc and nonoctet error status conditions are not checked on aborted frames. the receiver then enters hunt mode. 4 datasheet u .com
scc hdlc mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 30-7 30.8 hdlc mode register (psmr) the protocol-specific mode register (psmr), shown in figure 30-3 , functions as the hd lc mode register. table 30-6 describes psmr hdlc fields. nonoctet aligned frame the channel writes the received data to the buffer, closes the buffer, sets rxbd[no], and generates a maskable rxf interrupt. crc error status should be disregarded on nonoctet frames. after a nonoctet aligned frame is received, the receiver enters hunt mode. an immediat e back-to-back frame is still received. the nonoctet data may be derived from the last word in the buffer as follows: note that if buffer swapping is used (rfcr[bo] = 0b0x), the figure above refe rs to the last byte, rather than the last word, of the buffer. the lsb of each octet is sent first while the msb of the crc is sent first. crc the channel writes the received crc to the buffer, closes the buffer, sets rxbd[cr], generates a maskable rxf interrupt, and increments the crc error counter crcec. after receiving a frame with a crc error, the receiver enters hunt mode. an immediate back-to-back frame is still received. crc checking cannot be disabled, but the crc error can be ignored if checking is not required. 0 3 4 5 6 7 8 9 10 11 12 13 15 field nof crc rte ? fse drt bus brm mff ? reset 0 r/w r/w address 0x9_1a08 (psmr1); 0x9_1 a48 (psmr3); 0x9_1a68 (psmr4) figure 30-3. hdlc mode register (psmr) table 30-6. psmr hdlc field descriptions bits name description 0?3 nof number of flags. minimum number of flags between or before frames. if nof = 0b0000, no flags are inserted between frames and the closing flag of one frame is follow ed by the opening flag of the next frame in the case of back-to-back frames. nof can be modified on-the-fly. 4?5 crc crc selection. 00 16-bit ccitt-crc (hdlc). x16 + x12 + x5 + 1 x1 reserved 10 32-bit ccitt-crc (hdlc). x32 + x 26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x1 +1 6 rte retransmit enable 0 no retransmission 1 automatic frame retransmission is enabled. particul arly useful in the hdlc bus protocol and isdn applications where multiple hdlc controllers can collide. note that retransmission occurs only if a lost cts occurs on the first or second buffer of the frame. table 30-5. receive errors (continued) error description msb lsb 10 0 valid data nonvalid data 4 datasheet u .com
scc hdlc mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 30-8 freescale semiconductor 30.9 scc hdlc receive bu ffer descriptor (rxbd) the cp uses the rxbd, shown in figure 30-4 , to report on data received for each buffer. 7 ? reserved, should be cleared 8 fse flag sharing enable. fse can be set only if gsmr_h[rtsm] is already set. can be modified on-the-fly 0 normal operation 1 if nof[0?3] = 0b0000, a single shared flag is sent between back-to-back frames. other values of nof[0?3] are decremented by 1. useful in signaling system #7 applications 9 drt disable receiver while transmitting 0 normal operation 1 as the scc sends data, the receiver is disabled and gated by the internal rts . this helps if the hdlc channel is on a multidrop line and the scc does not need to receive its own transmission. 10 bus hdlc bus mode 0 normal hdlc operation 1 hdlc bus operation is selected. see section 30.13, ?hdlc bus mode with collision detection .? 11 brm hdlc bus rts mode. valid only if bus = 1. otherwise, it is ignored. 0normal rts operation during hdlc bus mode. rts is asserted on the first bit of the tx frame and negated after the first collision bit is received. 1 special rts operation during hdlc bus mode. rts is delayed by one bit with respect to the normal case, which helps when the hdlc bus protocol is being run lo cally and sent over a long-distance line at the same time. the one-bit delay allows rts to be used to enable the transmission line buffers so that the electrical effects of collisions are not sent over the transmission line. 12 mff multiple frames in tx fifo . the receiver is not affected. 0 normal operation. the tx fifo must never contain more than one hdlc frame. the cts lost status is reported accurately on a per-frame basis. 1 the tx fifo can hold multiple frames, but lost cts may not be reported on the buffer/frame it occurred on. this can improve performance of hdlc transmissi ons of small back-to-back frames or when the number of flags between frames should be limited. 13?15 ? reserved, should be cleared. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 offset + 0 e ? wi lf cm ? de ? lg no ab cr ov cd offset + 2 data length offset + 4 rx buffer pointer offset + 6 figure 30-4. scc hdl c receive buffer descriptor (rxbd) table 30-6. psmr hdlc field descriptions (continued) bits name description 4 datasheet u .com
scc hdlc mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 30-9 table 30-7 describes hdlc rxbd st atus and control fields. data length and buffer pointer fields are described in section 28.3, ?scc buffer descriptors (bds).? because hdlc is a frame-based protoc ol, rxbd[data length] of the last buffer of a frame contains the total number of frame bytes, including the 2 or 4 bytes for crc. figure 30-5 shows an example of how rxbds are used in receiving. table 30-7. scc hdlc rxbd status and control field descriptions bits name description 0 e empty 0 the buffer is full or reception stopped because of an erro r. the core can read or write to any fields of this rxbd. the cp does not use this bd while e = 0. 1 the buffer is not full. the cp controls the bd and buffer. the core should not update the bd. 1 ? reserved, should be cleared. 2 w wrap (last bd in the rxbd table) 0 not the last bd in the table 1 last bd in the table. after this buffer is used, the cp receives incoming data using the bd pointed to by rbase. the number of bds in this table are prog rammable and determined only by rxbd[w] and overall space constraints of the dual-port ram. 3 i interrupt 0 scce[rxb] is not set after this buffer is used; scce[rxf] is unaffected. 1 scce[rxb] or scce[rxf] is set when the scc uses this buffer. 4 l last buffer in frame 0 not the last buffer in frame 1 last buffer in frame. indicates reception of a closing flag or an error, in which case one or more of the cd, ov, ab, and lg bits are set. the scc writes the number of frame octets to the data length field. 5 f first in frame 0 not the first buffer in a frame 1 first buffer in a frame 6 cm continuous mode. note that rxbd[e] is cleared if an error occurs during reception, regardless of cm. 0 normal operation 1 rxbd[e] is not cleared by the cp after this bd is closed, allowing the associated buffer to be overwritten next time the cp accesses it. 7 ? reserved, should be cleared. 8 de dpll error. set when a dpll error occurs while this buffer is being received. de is also set due to a missing transition when using decoding modes in which a transitio n is required for every bit. note that when a dpll error occurs, the frame closes and error checking halts. 9 ? reserved, should be cleared. 10 lg rx frame length violation. set when a frame larger than the maximum defined for this channel is recognized. only the maximum-allowed number of bytes (mflr) is wri tten to the buffer. this event is not reported until the buffer is closed, scce[rxf] is set, and the closi ng flag is received. the total number of bytes received between flags is still written to the data length field. 11 no rx nonoctet aligned frame. set when a received frame contains a number of bits not divisible by eight. 12 ab rx abort sequence. set when at least seven co nsecutive ones are received during frame reception. 13 cr rx crc error. set when a frame contains a crc error. crc bytes received are always written to the rx buffer. 14 ov overrun. set when a receiver overrun occurs during frame reception. 15 cd carrier detect lost (nmsi mode only). set when cd is negated during frame reception. 4 datasheet u .com
scc hdlc mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 30-10 freescale semiconductor figure 30-5. scc hdlc receiving using rxbds buffer 0 0x0008 32-bit buffer pointer 1 ef receive bd 0 status length pointer 0 0x000b 32-bit buffer pointer 0 ef receive bd 1 status length pointer 0 0x0003 32-bit buffer pointer 1 ef receive bd 2 status length pointer 1 xxxx 32-bit buffer pointer e receive bd 3 status length pointer address 1 address 2 control byte buffer crc byte 1 crc byte 2 buffer address 1 address 2 buffer control byte empty 8 bytes 8 bytes 8 bytes 8 bytes two frames received in hdlc unexpected abort stored in rx buffer line idle occurs before present time time stored in rx buffer buffer full buffer closed when closing flag buffer still empty 1 ab 5 empty mrblr = 8 bytes for this scc empty last i-field byte information (i-field) bytes received abort was received after control byte 0 l 1 l 1 l faaciiiiii cr cr f closing flag abort/idle faac legend: f = flag a = address byte c = control byte i = information byte cr = crc byte 4 datasheet u .com
scc hdlc mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 30-11 30.10 scc hdlc transmit buffer descriptor (txbd) the cp uses the txbd, shown in figure 30-6 , to confirm transmissions and indicate error conditions. table 30-8 describes hdlc txbd st atus and control fields. the data length and buffer point er fields are described in section 28.3, ?scc buffer descriptors (bds).? 01234567 131415 offset + 0 r ? wi ltccm ?unct offset + 2 data length offset + 4 tx buffer pointer offset + 6 figure 30-6. scc hdlc transmit buffer descriptor (txbd) table 30-8. scc hdlc txbd status and control field descriptions bits name description 0 r ready 0 the buffer is not ready for transmission. both the buffer and the bd can be updated. the cp clears r after the buffer is sent or an error is encountered. 1 the buffer has not been sent or is being sent and the bd cannot be updated. 1 ? reserved, should be cleared. 2 w wrap (last bd in txbd table) 0 not the last bd in the table 1 last bd in the bd table. after this buffer is used , the cp sends data using the bd pointed to by tbase. the number of txbds in this table is determined by txbd[w] and the space constraints of the dual-port ram. 3 i interrupt 0 no interrupt is generated after this buffer is processed. 1 scce[txb] or scce[txe] is set when this buffer is processed, causing interrupts if not masked. 4 l last 0 not the last buffer in the frame 1 last buffer in the frame 5 tc tx crc. valid only when txbd[l] = 1. otherwise, it is ignored. 0 transmit the closing flag after the last data byte. this setting can be used to send a bad crc after the data for testing purposes. 1 transmit the crc sequence after the last data byte. 6 cm continuous mode 0 normal operation 1 the cp does not clear txbd[r] after this bd is closed allowing the buffer to be resent the next time the cp accesses this bd. however, txbd[r] is cleared if an error occurs during transmission, regardless of cm. 7?13 ? reserved, should be cleared. 14 un underrun. set after the scc sends a buffer and a transmitter underrun occurred 15 ct cts lost. indicates when cts in nmsi mode or layer 1 grant is lost in gci or idl mode during frame transmission. if data from more than one buffer is cu rrently in the fifo when this error occurs, the hdlc writes ct in the current bd after sending the buffer. 4 datasheet u .com
scc hdlc mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 30-12 freescale semiconductor 30.11 hdlc event register (scc e)/hdlc mask register (sccm) the scc event register (scce) is used as the hdlc event register to report events recognized by the hdlc channel and to generate interrupts. when an event is recognized, the scc sets the corresponding scce bit. interrupts gene rated through scce can be masked in the scc mask register (sccm) which has the same bit format as the scce. setting an sccm bit enables the correspondi ng interrupt; clearing a bit masks it. scce bits are cleared by writing ones; writing zeros has no ef fect. all unmasked bits must be cleared before the cp clears th e internal interrupt request. figure 30-7 shows scce/sccm for hdlc operation. table 30-9 describes scce/sccm fields. 0 456789101112131415 field ? dcc flg idl gra ? txe rxf bsy txb rxb reset 0000_0000_0000_0000 r/w r/w offset 0x9_1a10 (scce1); 0x9_1a50 (scce3); 0x9_1a70 (scce4) 0x9_1a14 (sccm1); 0x9_1a54 (sccm3); 0x9_1a74 (sccm4) figure 30-7. hdlc event register (scce)/hdlc mask register (sccm) table 30-9. scce/sccm field descriptions bits name description 0?4 ? reserved, should be cleared. 5 dcc dpll carrier sense changed. set when the carrier sense status generated by the dpll changes. real-time status can be read in sccs[cs]. this is not the cd status reported in port c. valid only when the dpll is used. 6 flg flag status. set when the scc stops or starts re ceiving hdlc flags. real-time status can be read in sccs[fg]. 7 idl idle sequence status changed. set when hdlc line stat us changes. real-time status of the line can be read in sccs[id]. 8 gra graceful stop complete. a graceful stop transmit command completed execution. set as soon as the transmitter has sent a frame in progress when the command was issued. set immediately if no frame was in progress when the command was issued. 9?10 ? reserved, should be cleared. 11 txe tx error. indicates an error (cts lost or underrun) has occurred on the transmitter channel. 12 rxf rx frame. set when the number of receive frames specified in rfthr are received on the hdlc channel. it is set no sooner than two clocks after the last bit of th e closing flag is received. this event is not maskable through the rxbd[i] bit. 13 bsy busy condition. indicates a frame arrived but was discarded due to a lack of buffers. 14 txb transmit buffer. enabled by setting txbd[i]. txb is set when a buffer is sent on the hdlc channel. for the last buffer in the frame, txb is not set before the last bit of the closing flag begins its transmission; otherwise, it is set after the last byte of th e buffer is written to the tx fifo. 15 rxb receive buffer. enabled by setting rxbd[i]. rxb is set when the hdlc channel receives a buffer that is not the last in a frame. 4 datasheet u .com
scc hdlc mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 30-13 figure 30-8 shows interrupts that can be ge nerated using the hdlc protocol. figure 30-8. scc hdlc interrupt event example 30.12 scc hdlc status register (sccs) the scc status regist er (sccs), shown in figure 30-9 , permits monitoring of re al-time status conditions on rxd. the real-time status of cts and cd are part of the port c parallel i/o. 0 4567 field ? fg cs id reset 0000_0000 r/w r offset 0x9_1a17 (sccs1); 0x9_1a57 (sccs3); 0x9_1a77 (sccs4) figure 30-9. scc hdlc status register (sccs) cd idl flg rxb rxf idl cd line idle stored in rx buffer rxd cd frame received by hdlc time line idle txd rts frame transmitted by hdlc cts txb cts cts line idle line idle stored in tx buffer notes: hdlc scce events 1. rxb event assumes receive buffers are 6 bytes each. 2. the second idl event occurs after 15 ones are received in a row. 3. the flg interrupts show the beginning and end of flag reception. 4. the flg interrupt at the end of the frame may pr ecede the rxf interrupt due to receive fifo latency. 5. the cd event must be programmed in the port c parallel i/o, not in the scc itself. notes: hdlc scce events 1. txb event shown assumes all three bytes were put into a single buffer. 2. example shows one additional opening flag. this is programmable. f faaciiicrcrf flg flg flg 6. f = flag, a = address byte, c = control byte, i = information byte, and cr = crc byte. ffaaccrcrf 3. the cts event must be programmed in the port c parallel i/o, not in the scc itself. 4 datasheet u .com
scc hdlc mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 30-14 freescale semiconductor table 30-10 describes hdlc sccs fields. 30.13 hdlc bus mode with collision detection the hdlc controller includes an option for hardware collision detection and retransmission on an open-drain connected hdlc bus, refe rred to as hdlc bus mode. most hdlc-based controllers provide only point-to-point communications; however, the hdlc bus enhancement allows implementation of an hdlc-based lan and other point-to- multipoint configurations. the hdlc bus is based on techniques used in the ccitt isdn i.430 and ansi t1.605 standa rds for d-channel point- to-multipoint operation over the s/t interface. however, the hdlc bus doe s not fully comply with i.430 or t1.605 and cannot replace devices that implement th ese protocols. instead, it is mo re suited to non-isdn lan and point-to-multipoint configurations. review the basic features of the i.430 and t1.605 before learning about th e hdlc bus. the i.430 and t1.605 define a way to connect eight terminals over the d-channel of the s/ t isdn bus. the layer 2 protocol is a variant of hdlc, called lapd. however, at layer 1, a method is provided to allow the eight terminals to send frames to the switch through the physical s/t bus. to determine whether a channel is clear, the s/t interface device looks at an echo bit on the line designed to echo the last bit sent on the d channel. depending on the class of terminal and the context, an s/t interface device waits for 7?10 ones on the echo bit be fore letting the lapd frame begin transmission, after which the s/t interfa ce monitors transmitted data. as long as the echo bit matches the sent data, transmission continues. if the echo bit is ever 0 when the transmit bi t is 1, a collision occurs between terminals; the station(s) that sent a zero stops transmitting. the station that sent a 1 continues as normal. the i.430 and t1.605 standards provide a physical layer protocol that allows multiple terminals to share one physical connection. thes e protocols handle collisions efficien tly because one station can always complete its transmission, at which point, it lowers its own priority to give other devices fair access to the physical connection. table 30-10. hdlc sccs field descriptions bits name description 0?4 ? reserved, should be cleared. 5 fg flags. the line is checked after the data has been decoded by the dpll. 0 hdlc flags are not being received. the most recently re ceived 8 bits are examined every bit time to see if a flag is present. 1 hdlc flags are being received. fg is set as soon as an hdlc flag (0x7e) is received on the line. once it is set, it remains set at least 8 bit times and the next eight received bits are examined. if another flag occurs, fg stays set for at least another eight bits. if not, it is cleared and the search begins again. 6 cs carrier sense (dpll). shows the real-time carrier sense of the line as determined by the dpll. 0 the dpll does not sense a carrier. 1 the dpll senses a carrier. 7 id idle status 0 the line is busy. 1 set when rxd is a logic 1 (idle) for 15 or more consecutive bit times. it is cleared after a single logic 0 is received. 4 datasheet u .com
scc hdlc mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 30-15 the hdlc bus differs from the i.430 and t1.605 standards as follows: ? the hdlc bus uses a separate i nput signal rather than the echo bit to monitor data; the transmitted data is simply connected to the cts input. ? the hdlc bus is a sync hronous, digital open-drai n connection for short-di stance configurations, rather than the more complex s/t interface. ? any hdlc-based frame protocol can be used at layer 2, not just lapd. ? hdlc bus devices wait 8?10 rath er than 7?10 bit times before transmitting. (hdlc bus has only one class.) the collision-detection mechanism supports only: ? nrz-encoded data ? a common synchronous clock for all receivers and transmitters ? non-inverted data (gsmr[rinv, tinv] = 0) ? open-drain connection with no external transceivers figure 30-10 shows the most common hdlc bus lan confi guration, a multiple-master configuration. a station can transfer data to or from any other lan st ation. transmissions are half -duplex, which is typical in lans. figure 30-10. typical hdlc bus multiple-master configuration in single-master configuration, a mast er station transmits to any slave station with out collisions. slaves communicate only with the master, but can experience collisions in th eir access over the bus. in this configuration, a slave th at communicates with another slave must first transmit it s data to the master, where the data is buffered in ram and then resent to the other slave. the be nefit of this conf iguration, however, is that full-duplex operation can be obtained. in a point -to-multipoint environment, this is the preferred configuration. figure 30-11 shows the single-master configuration. hdlc bus controller rxd cts txd a rclk/tclk hdlc bus controller rxd cts txd b rclk/tclk hdlc bus controller rxd cts txd c rclk/tclk clock hdlc bus lan + 3.3 v r master master master notes: 1. transceivers may be used to extend the lan size. 2. the txd pins of slave devices should be confi gured to open-drain in the port c parallel i/o port. 3. clock is a common rclk/tclk for all stations. 4 datasheet u .com
scc hdlc mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 30-16 freescale semiconductor figure 30-11. typical hdlc bus single-master configuration 30.13.1 hdlc bus features the main features of th e hdlc bus are as follows: ? superset of the hdlc controller features ? automatic hdlc bus access ? automatic retransmission in case of collision ? may be used with the nmsi or a tdm bus ? delayed rts mode 30.13.2 accessing the hdlc bus the hdlc bus protocol ensures orde rly bus control when multiple tr ansmitters attempt simultaneous access. the transmitter sending a zero bit at the time of collision comp letes the transmission. if a station sends out an opening flag (0 x7e) while another station is already sending, the collis ion is always detected within the first byte, because the transmission in progress is using ze ro bit insertion to prevent flag imitation. while in the active condition (ready to transmit), th e hdlc bus controller monitors the bus using cts . it counts the one bits on cts . when eight consecutive ones are count ed, the hdlc bus controller starts transmitting on the line; if a zero is detected, the inte rnal counter is cleared. du ring transmission, data is continuously compared with the external bus using cts . cts is sampled halfway through the bit time using the rising edge of the tx clock. if the transmitted bit matches the received cts bus sample, transmission continues. howe ver, if the received cts sample is 0 and the trans mitted bit is 1, transmission stops after that bit and waits for an idle line befo re attempting retransmission. since the hdlc bus uses a hdlc controller rxd txd a rclk hdlc bus controller rxd cts txd b hdlc bus controller rxd cts txd c clock1 hdlc bus lan + 3.3 v r slave slave master notes: 1. transceivers may be used to extend the lan size. 2. the txd pins of slave devices should be configured to open-drain in the port c parallel i/o port. 3. clock1 is the master rclk and the slave tclk. clock2 tclk rclk tclk rclk tclk 4. clock2 is the master tclk and the slave rclk. 4 datasheet u .com
scc hdlc mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 30-17 wired-or scheme, a transmitted zero has priority over a transmitted 1. figure 30-12 shows how cts is used to detect collisions. figure 30-12. detecting an hdlc bus collision if both the destination address and source address ar e included in the hdlc frame, then a predefined priority of stations result s; if two stations begin to transmit si multaneously, they necessarily detect a collision no later than the end of the source address. the hdlc bus priority mechanism ensures that stati ons share the bus equally. to minimize idle time between messages, a station normally waits for eight one bits on the li ne before attempting transmission. after successfully sending a frame, a station waits for 10 rather than ei ght consecutive one bits before attempting another transmis sion. this mechanism ensures that anothe r station waiting to transmit acquires the bus before a station can transmit twice. when a lo w priority station detects 10 consecutive ones, it tries to transmit; if it fails, it reinstates th e high priority of waiting for only eight ones. 30.13.3 increasing performance because it uses a wired-or configuration, hdlc bus performance is limited by th e rise time of the one bit. to increase performan ce, give the one bit more rise time by usi ng a clock that is lo w longer than it is high, as shown in figure 30-13 . figure 30-13. nonsymmetrical tx clock duty cycle for increased performance tclk cts (input) txd (output) cts sampled at halfway point. collision detected when txd = 1, but cts = 0. tclk cts (input) txd (output) cts sampled at three quarter point. collision detected when txd = 1, but cts = 0. 4 datasheet u .com
scc hdlc mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 30-18 freescale semiconductor 30.13.4 delayed rts mode figure 30-14 shows local hdlc bus controllers using a sta ndard transmission line and a local bus. the controllers do not communicat e with each other but with a station on the transmission line; yet the hdlc bus protocol controls acces s to the transmission line. figure 30-14. hdlc bus transmission line configuration normally, rts goes active at the beginning of the opening flag?s first bit. setting psmr[brm] delays rts by one bit, which is useful when the hdlc bus connects multiple local stations to a transmission line. if the transmission line driver ha s a one-bit delay, the delayed rts can be used to enable the output of the line driver. as a result, the electrical ef fects of collisions are isolated locally. figure 30-15 shows rts timing. figure 30-15. delayed rts mode local hdlc bus hdlc bus controller rxd cts txd a hdlc bus controller rxd cts txd b rts + 3.3 v r notes: 1. the txd pins of slave devices should be configured to open-drain in the port c parallel i/o port. 2. the rts pins of each hdlc bus controller are configured to delayed rts mode. rts tx rx en (1-bit delay) line driver tclk rts active for only 2 bit times txd cts rts 1st bit 2nd bit 3rd bit collision 4 datasheet u .com
scc hdlc mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 30-19 30.13.5 using the time-slot assigner (tsa) hdlc bus controllers can be used with a time-divisi on multiplexed transmission line and a local bus, as shown in figure 30-16 . local stations use time slots to communicate over the tdm transmission line; stations that share a time slot use the hdlc bus protocol to control access to the local bus. figure 30-16. hdlc bus tdm transmission line configuration the local sccs in hdlc bus mode communicate only with the transmission line and not with each other. the sccs use the tsa of the serial interf ace, receiving and sending data over l1txd x and l1rxd x . because collisions are still det ected from the individual scc cts pin, it must be configured to connect to the chosen scc. because the scc only rece ives clocks during its time slot, cts is sampled only during the tx clock edges of the particular scc time slot. 30.13.6 hdlc bus protocol programming the hdlc bus on the MPC8555E is implemented using the scc in hdlc mode with bus-specific options selected in the psmr and gsmr, as outlined below. see also section 30.5, ?programming the scc in hdlc mode.? 30.13.6.1 programming gsmr and psmr for the hdlc bus protocol to program the protocol-specific mode regist er (psmr), set the bits as described below: ? configure nof as preferred. ? set rte and bus to 1. ? set brm to 1 if delayed rts is desired. ? configure crc to 16-bit crc ccitt (0b00). ? configure other bits to zero or default. local hdlc bus hdlc bus controller l1rxd cts l1txd b hdlc bus controller l1rxd cts l1txd d + 3.3 v r notes: 1. all txd pins of slave devices should be configured to open-drain in the port c parallel i/o port. 2. the tsa in the si of each station is us ed to configure the preferred time slot. tx rx line driver hdlc bus controller l1rxd cts l1txd c hdlc bus controller l1rxd cts l1txd a stations share time-slot n stations share time-slot m 3. the choice of the number of stations to share a time slot is user-defined. it is two in this example. 4 datasheet u .com
scc hdlc mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 30-20 freescale semiconductor to program the general scc mode register (gsmr), set the bits as described below: ? set mode to hdlc mode (0b0000). ? configure ctss to 1 and all ot her bits to zero or default. ? configure the diag bits for normal operation (0b00). ? configure rdcr and tdcr for 1 clock (0b00). ? configure tenc and renc for nrz (0b000). ? clear rtsm to send idles between frames. ? set gsmr_l[ent, enr] as the last step to begin operation. 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 31-1 chapter 31 scc bisync mode the byte-oriented bisync protocol was developed by ibm for use in networking pro ducts. the three classes of bisync frames, shown in figure 31-1 , are transparent, nontransparent with header, and nontransparent without header. the tr ansparent frame type in bisync is not related to transparent mode, discussed in chapter 32, ?scc transparent mode.? transparent bisync mode allows full binary data to be sent with any possible characte r pattern. each class of frame st arts with a standard two-octet synchronization pattern and e nds with a block check code (bcc). the end-of-text character (etx) is used to separate the text and bcc fields. the bulk of a frame is divided into fields whose meaning depends on th e frame type. the bcc is a 16-bit crc format if 8-bit character s are used; it is a combination longitudi nal (sum check) and vertical (parity) redundancy check if 7-bit characters are used. in tr ansparent operation, a special character (dle) is defined that tells the receiver that the next character is text, allowi ng bisync control characters to be valid text data in a frame. a dle sent as data mu st be preceded by a dle character. this is sometimes called byte-stuffing. the physical layer of the bisync communica tions link must synchronize the receiver and transmitter, usually by sending at least one pair of synchronization characters before each frame. bisync protocol is unusual in that a transmit underrun need not be an error. if an underrun occurs, a synchronization pattern is sent until data is again re ady. in nontransparent opera tion, the receiver discards additional synchronization characters (syncs) as they are recei ved. in transparent mode, dle-sync pairs are discarded. normally, for proper transmission, an underrun must not occur between the dle and its following character. this failure mode cannot occur with the MPC8555E. an scc can be configured as a bisync controller to handle basic bisync protocol in normal and transparent modes. the controller can work with th e time-slot assigner (tsa) or nonmultiplexed serial interface (nmsi). the controller ha s separate transmit and receive sections whose operations are asynchronous with the core and either s ynchronous or asynchronous with other sccs. nontransparent with header syn1 syn2 soh header stx text etx bcc nontransparent without header syn1 syn2 stx text etx bcc transparent syn1 syn2 dle stx transparent tex t dle etx bcc figure 31-1. classes of bisync frames 4 datasheet u .com
scc bisync mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 31-2 freescale semiconductor 31.1 features the following list summarizes feat ures of the scc in bisync mode: ? flexible data buffers ? eight control character recognition registers ? automatic sync1?sync2 detection ? 16-bit pattern (bisync) ? 8-bit pattern (monosync) ? 4-bit pattern (nibblesync) ? external sync pin support ? sync/dle stripping and insertion ? crc16 and lrc (sum chec k) generation/checking ? vrc (parity) generation/checking ? supports bisync transparent operation ? maintains parity error counter ? reverse data mode capability 31.2 scc bisync channel frame transmission the bisync transmitter is designed to work with al most no core intervention. when the transmitter is enabled, it starts sending syn1?syn 2 pairs in the data synchronizati on register (dsr) or idles as programmed in the psmr. the bisync controller polls th e first bd in the channel? s txbd table. if there is a message to send, the controller fetches the me ssage from memory and st arts sending it after the syn1?syn2 pair. the entire pair is al ways sent, regardless of gsmr[synl]. after a buffer is sent, if the last (txbd[l]) and the tx block check sequence (txbd[tb]) bits are set, the bisync controller appends the crc16/lrc and then writes the messa ge status bits in txbd status and control fields and clears the ready bit, txbd[r]. it then starts se nding the syn1?syn2 pairs or idles, according to gsmr[rtsm]. if the e nd of the current bd is reached and txbd[l] is not set, only txbd[r] is cleared. in both cases, an interrupt is issued according to txbd[i]. txbd[i] controls whether interrupts are generated after transmis sion of each buffer, a specific buffer, or each block. the controller then proceeds to the next bd. if no additional buffers have been se nt to the controller fo r transmission, an in-fra me underrun is detected and the controller starts se nding syncs or idles. if the controller is in transparent mode , it sends dle-sync pairs. characters are included in the block check se quence (bcs) calculation on a per-buffer basis. each buffer can be programmed independently to be incl uded or excluded from the bcs calc ulation; thus, excluded characters must reside in a separate buffer. the controller can reset the bcs generator before sending a specific buffer. in transparent mode, th e controller inserts a d le before sending a dle character, so that only one d le is used in the calculation. 4 datasheet u .com
scc bisync mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 31-3 31.3 scc bisync channel frame reception although the receiver is designed to work with almost no core interv ention, the user can intervene on a per-byte basis if necessary. the receiver performs crc16, longitudi nal (lrc) or vertical redundancy (vrc) checking, sync stripping in normal mode, dle-sync strippi ng, stripping of the first dle in dle-dle pairs in transparent mode , and control character recognition. control characters are discussed in section 31.6, ?scc bisync cont rol character recognition.? when enabled, the receiver enters hunt mode where the da ta is shifted into the receiver shift register one bit at a time and the contents of th e shift register are compared to th e contents of dsr[syn1, syn2]. if the two are unequal, the ne xt bit is shifted in and the comparison is repeated. when registers match, hunt mode is terminated and character a ssembly begins. the controller is character-synchronized and performs sync stripping and message rece ption. it reverts to hunt m ode when it receives an enter hunt mode command, an error condition, or an appropriate control character. when receiving data, the controller upda tes the cr bit in the bd for each byte transferred. when the buffer is full, the controller clears the e bit in the bd and gene rates an interrupt if the i bit in the bd is set. if incoming data exceeds the buffer length, the controll er fetches the next bd ; if e is zero, reception continues to its buffer. when a bcs is received, it is checked and written to th e buffer. the bisync controller sets the last bit, writes the message status bits into the bd, clears the e bit, and then generates a maskable interrupt, indicating that a block of data was received and is in memory. th e bcs calculations do not include syncs (in nontransparent mode) or dle-sy nc pairs (in transparent mode). note that gsmr_h[rfw] should be set for an 8-bit- wide receive fifo for th e bisync receiver. see section 28.2, ?general scc mode registers (gsmr1?gsmr4).? 31.4 scc bisync parameter ram for bisync mode, the protocol-s pecific area of the scc parame ter ram is mapped as shown in table 31-1 . table 31-1. scc bisync pa rameter ram memory map offset 1 name width description 0x30 ? word reserved 0x34 crcc word crc constant temp value 0x38 prcrc hword preset receiver/transmitter crc16/lrc. these values should be preset to all ones or zeros, depending on the bcs used. 0x3a ptcrc hword 0x3c parec hword receive parity error counter. this 16-bit (modulo 2 16 ) counter maintained by the cp counts parity errors on receive if the parity featur e of bisync is enabled. initialize parec while the channel is disabled. 0x3e bsync hword bisync sync register. co ntains the value of the sync to be sent as the second byte of a dle?sync pair in an underrun condition and stripped from incoming data on receive once the receiver synchronizes to the data using the dsr and syn1?syn2 pair. see section 31.7, ?bisync sync register (bsync).? 4 datasheet u .com
scc bisync mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 31-4 freescale semiconductor gsmr[mode] determines the protoc ol for each scc. the syn1?syn2 synchronization characters are programmed in the dsr (see section 28.2.2, ?data synchroni zation register (dsr).? ) the bisync controller uses the same basic data structure as other modes; receive and transmit errors are reported through their respective bds. there are two basic ways to handle bisync channels: ? the controller can inspect data on a per-byte ba sis and interrupt the core each time a byte is received. ? the controller can be programme d so software handles the first two or three bytes . the controller directly handles subsequent data without interrupting the core. 31.5 scc bisync commands transmit and receive commands are issued to the cp command register (cpcr) . transmit commands are described in table 31-2 . 0x40 bdle hword bisync dle register. contains the val ue to be sent as the first byte of a dle?sync pair and stripped on receive. see section 31.8, ?scc bisync dle register (bdle).? 0x42 character1 hword control character 1?8. these va lues represent control c haracters that the bisync controller recognizes. see section 31.6, ?scc bisync control character recognition.? 0x44 character2 hword 0x46 character3 hword 0x48 character4 hword 0x4a character5 hword 0x4c character6 hword 0x4e character7 hword 0x50 character8 hword 0x52 rccm hword receive control character mask. masks character n comparison so control character classes can be defined. setting a bit enab les and clearing a bit masks comparison. see section 31.6, ?scc bisync cont rol character recognition.? 1 from scc x base address. see section 28.4.1, ?scc base addresses.? table 31-2. transmit commands command description stop transmit after hardware or software is reset and the channel is enabled in the gsmr, the channel is in transmit enable mode and starts polling the first bd every 64 transmit clocks. this command stops transmission after a maximum of 64 additional bits without waiting for the end of the buffer and the trans mit fifo to be flushed. tbptr is not advanced, no new bd is accessed, and no new buffers are sent for this channel. sync?sync or dle?sync pairs are sent continually until a restart transmit is issued. a stop transmit can be used when an eot sequence should be sent and transmission should stop. after transmission resumes, the eot sequence should be the first buffer sent to the controller. note that the controller remains in transpa rent or normal mode after it receives a stop transmit or restart transmit command. table 31-1. scc bisync pa rameter ram memory map offset 1 name width description 4 datasheet u .com
scc bisync mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 31-5 receive commands are described in table 31-3 . 31.6 scc bisync control character recognition the bisync controller rec ognizes special control characters that customize the protoc ol implemented by the bisync controller and aid its operation in a dma-oriented environm ent. they are used for receive buffers longer than one byte. in si ngle-byte buffers, each byte can be eas ily inspected so control character recognition should be disabled. the control character table, shown in figure 31-2 , lets the bisync controller recognize the end of the current block. because the controller imposes no restri ctions on the format of bisync blocks, software must respond to received characters and inform the c ontroller of mode changes and of certain protocol events, such as resetting the bcs. us ing the control character table corr ectly allows the remainder of the block to be received wit hout interrupting software. up to eight control characters can be defined to inform the bisync controller th at the end of the current block is reached and whether a bcs is expected after the character. for example, the end-of-text character (etx) implies an end-of-block (etb) with a subse quent bcs. an enquiry (enq) character designates an end of block without a subs equent bcs. all the control characters are written into the data buffer. the bisync controller uses a table of 16-bit entries to support contro l character recognition. each entry graceful stop transmit stops transmission after the current fr ame finishes sending or immediately if there is no frame being sent. scce[gra] is set once transmission stops. then bisync transmit parameters and txbds can be modified. the tbptr points to the next txbd. transmission resumes when the r bit of the next bd is set and a restart transmit is issued. restart transmit lets characters be sent on the transmit cha nnel. the bisync controller expects it after a stop transmit or a graceful stop transmit command is issued, after a transmitter error occurs, or after a stop transmit is issued and the channel is disabled in its sccm. the controlle r resumes transmission from the current tbptr in the channel?s txbd table. init tx parameters initializes all transmit parameters in the serial channel?s parameter ram to their reset state. issue only when the transmitter is disabled. init tx and rx parameters resets transmit and receive parameters. table 31-3. receive commands command description reset bcs calculation immediately resets the receive bcs accumulator. it can be used to reset the bcs after recognizing a control character, thus signifying that a new block is beginning. enter hunt mode after hardware or software is reset and the channel is enabled in sccm, the channel is in receive enable mode and uses the first bd. this command forces the controll er to stop receiving and enter hunt mode, during which the controller continually scans the data stream for an syn1?syn2 sequence as programmed in the dsr. after receiving the command, the current receive buffer is cl osed and the bcs is reset. message reception continues using the next bd. close rxbd used to force the scc to close the current rxbd if it is in use and to use the next bd for subsequent data. if data is not being received, no action is taken. init rx parameters initializes receive parameters in this serial channel?s par ameter ram to reset state. issue only when the receiver is disabled. an init tx and rx parameters resets transmit and receive parameters. table 31-2. transmit commands (continued) command description 4 datasheet u .com
scc bisync mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 31-6 freescale semiconductor consists of the control character, an end-of-table bit (e), a bcs expected bit (b), and a hunt mode bit (h). the rccm entry defines classes of contro l characters that support masking option. table 31-4 describes control character table and rccm fields. offset from scc x base 0123 78 15 0x42 e b h ? character1 0x44 e b h ? character2 0x46 e b h ? character3 0x48 e b h ? character4 0x4a e b h ? character5 0x4d e b h ? character6 0x4e e b h ? character7 0x50 e b h ? character8 0x52 1 1 1 ? mask value(rccm) figure 31-2. control character table and rccm table 31-4. control character ta ble and rccm field descriptions offset bits name description 0x42?0 x50 0 e end of table. 0 this entry is valid. the lower eight bits are checked against the incoming character. in tables with eight control characters, e should be zero in all eight positions. 1 the entry is not valid. no other valid entries exist beyond this entry. 1 b bcs expected. a maskable interrupt is generated after the buffer is closed. 0 the character is written into the receive buffer and the buffer is closed. 1 the character is written into the receive buffer. the receiver waits for one lrc or two crc bytes of bcs and then closes the buffer. this should be used for etb, etx, and itb. 2 h hunt mode. enables hunt mode wh en the current buffer is closed. 0 the bisync controller maintains character syn chronization after closing this buffer. 1 the bisync controller enters hunt mode after cl osing the buffer. when the b bit is set, the controller enters hunt mode after receiving the bcs. 3?7 ? reserved 8?15 character n control character 1?8. when usi ng 7-bit characters with parity, include the parity bit in the character value. 0x52 0?2 ? all ones 3?7 ? reserved 8?15 rccm received control character mask. ma sks comparison of character n . each bit of rccm masks the corresponding bit of character n . 0 mask this bit in the comparison of the incoming character and character n . 1 the address comparison on this bit proceeds normally and no masking occurs. if rccm is not set, erratic operation can occur during control character recognition. 4 datasheet u .com
scc bisync mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 31-7 31.7 bisync sync register (bsync) the bsync register, as seen in figure 31-3 , defines bisync stripping a nd sync character insertion. when an underrun occurs, the bisync controller in serts sync characters unt il the next buffer is available for transmission. if the r eceiver is not in hunt mode when a sync character is received, it discards this character if the valid bit (bsync[v]) is set. when using 7-bit characters with parity, the parity bit should be included in the sync register value. table 31-5 describes bsync fields. 31.8 scc bisync dle register (bdle) the bdle register, as seen in figure 31-4 , is used to define the bisync stripping and insertion of dle characters. when an underrun occurs while a message is being sent in transparent mode, the bisync controller inserts dle-sync pairs until the next buffer is available for transmission. in transparent mode, the receiver di scards any dle character received a nd excludes it from the bcs if the valid bit (bdle[v]) is set. if the se cond character is sync, the controller discards it and excludes it from the bcs. if it is a dle, the controll er writes it to the buffer and includes it in the bcs. if it is not a dle or sync, the controller examines th e control character table and acts a ccordingly. if the character is not in the table, the buffer is closed with the dle follow character error bit se t. if the valid bit is not set, the receiver treats the character as a normal character. when using 7-bit characters with parity, the parity bit should be included in th e dle register value. 012345678 15 fieldvdis000000 sync reset undefined r/w r/w offset scc base + 0x3e figure 31-3. bisync sync (bsync) table 31-5. bsync field descriptions bits name description 0 v valid. if v = 1 and the receiver is not in hunt mode when a sync character is received, this character is discarded. 1 dis disable bsync stripping 0 normal mode 1 bsync stripping disabled (bisync transparent mode only) 2?7 ? all zeros 8?15 sync sync character 4 datasheet u .com
scc bisync mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 31-8 freescale semiconductor table 31-6 describes bdle fields. 31.9 sending and receiving the synchronization sequence the bisync channel can be programmed to send and receive a synchronization pattern defined in the dsr. gsmr_h[synl] defines pattern length, as shown in table 31-7 . the receiver synchronizes on this pattern. unless synl is zero (external sync), the tran smitter always sends the entire dsr contents, lsb first, before each frame?the chosen 4- or 8-bit pattern can be re peated in the lower-order bits. 012345678 15 fieldvdis000000 dle reset undefined r/w r/w offset scc base + 0x40 figure 31-4. bisync dle (bdle) table 31-6. bdle field descriptions bits name description 0 v valid. if v = 1 and the receiver is not in hunt mode when a sync character is received, this character is discarded. 1 dis disable dle stripping 0 normal mode 1 dle stripping disabled. when dis is enabled in bdle and on bsync the following cases occur: dle-dle sequence. both characters are written to t he memory. the bcs is calculated only on the second dle. dle-sync sequence. both characters are written to the memory, but neither are included in the bcs calculation. dle-etx, dle-itb, dle-etb sequence, both characte rs are written to memory. the bcs is calculated only on the second character. 2?7 ? all zeros 8?15 dle dle character table 31-7. receiver sync pattern lengths of the dsr gsmr_h[synl] setting bit assignments 0123456789101112131415 00 an external sync signal is used instead of the sync pattern in the dsr. 01 4-bit 10 8-bit 11 16-bit 4 datasheet u .com
scc bisync mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 31-9 31.10 handling errors in the scc bisync the controller reports mess age transmit and rece ive errors using the channel bds, error counters, and the scce. modem lines can be directly m onitored through the parallel port pins. table 31-8 describes transmit errors. table 31-9 describes receive errors. 31.11 bisync mode register (psmr) the psmr is used as the bisy nc mode register, shown in figure 31-5 . psmr[rbcs, rtr, rpm, tpm] can be modified on-the-fly. table 31-8. transmit errors error description tr a n s m i t t e r underrun the channel stops sending the buffer, closes it, sets txbd [un], and generates atxe inte rrupt if it is enabled. the channel resumes transmission after a restart transmit command is received. underrun cannot occur between frames or during a dle? xxx pair in transparent mode. cts lost during message transmission the channel stops sending the buffer, closes it, sets txbd[ct], and generates a txe interrupt if not masked. transmission resumes when a restart transmit command is received. table 31-9. receive errors error description overrun the controller maintains a receiver fifo for receiving data. the cp begins programming the sdma channel (if the buffer is in external memory) and updating the crc when the first byte is received in the rx fifo. if an rx fifo overrun occurs, the controller writes the re ceived byte over the previously received byte. the previous character and its status bits are lost. the channel then closes the buffer, sets rxbd[ov], and generates the rxb interrupt if it is enabled. finally, the receiver enters hunt mode. cd lost during message reception the channel stops receiving, closes the buffer, sets rxbd[cd], and generates the rxb interrupt if not masked. this error has the highest priority. if the rest of the message is lost, no other errors are checked in the message. the receiver immediately enters hunt mode. parity the channel writes the received character to the bu ffer and sets rxbd[pr]. the channel stops receiving, closes the buffer, sets rxbd[pr], and generates the rxb interrupt if it is enabled. the channel also increments parec and the receiver immediately enters hunt mode. crc the channel updates the cr bit in the bd every time a character is received with a byte delay of 8 serial clocks between the status update and the crc calculation. when control characte r recognition is used to detect the end of the block and cause crc checking, the channel closes the buffer, sets the cr bit in the bd, and generates the rxb interrupt if it is enabled. 0 3 4 5 6 7 8 9 10 11 12 13 14 15 field nos crc rbcs rtr rvd drt ? rpm tpm reset 0 r/w r/w offset 0x9_1a08 (psmr1); 0x9_1 a48 (psmr3); 0x9_1a68 (psmr4) figure 31-5. protocol-specific m ode register for bisync (psmr) 4 datasheet u .com
scc bisync mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 31-10 freescale semiconductor table 31-10 describes psmr fields. table 31-10. psmr field descriptions bits name description 0?3 nos minimum number of syn1?syn2 pairs (defined in dsr) sent between or before messages.if nos = 0000, one pair is sent. if nos = 1111, 16 pairs are sent. th e entire pair is always sent, regardless of how gsmr[synl] is set. nos can be modified on-the-fly. 4?5 crc crc selection x0 reserved. 01 crc16 (bisync). x16 + x15 + x2 + 1. prcrc and ptcrc should be initialized to all zeros or all ones before the channel is enabled. in either case, th e transmitter sends the calculated crc noninverted and the receiver checks the crc against zero. eight-bit da ta characters (without parity) are configured when crc16 is chosen. 11 lrc (sum check). (bisync). for even lrc, initia lize prcrc and ptcrc to zeros before the channel is enabled; for odd lrc, they should be initialized to ones. note: the receiver checks character parity when bcs is programmed to lrc and the receiver is not in transparent mode. the transmitter sends character parity when bcs is programmed to lrc and the transmitter is not in transparent mode. use of pari ty in bisync assumes that 7-bit data characters are being used. 6 rbcs receive bcs. the receiver internally stores two bcs calculations separated by an eight serial clock delay to allow examination of a received byte to determine whether it should used in bcs calculation. 0 disable receive bcs 1 enable receive bcs. should be set (or reset) within the time taken to receive the following data byte. when rbcs is reset, bcs calculations exclude the latest fully received data byte. when rbcs is set, bcs calculations continue as normal. 7 rtr receiver transparent mode 0 normal receiver mode with sync stripping and control character recognition 1 transparent receiver mode. syncs, dles, and control characters are recognized only after a leading dle character. the receiver calculates the crc16 sequence even if it is programmed to lrc while in transparent mode. initialize prcrc to the crc16 preset value before setting rtr. 8 rvd reverse data 0 normal operation 1 any portion of this scc defined to operate in bisyn c mode operates by reversing the character bit order and sending the msb first. 9 drt disable receiver while sending. drt should not be set for typical bisync operation. 0 normal operation 1 as the scc sends data, the receiver is disabled and gated by the internal rts signal. this helps if the bisync channel is being configured onto a multidrop line and the user does not want to receive its own transmission. although bisync usually uses a half-duplex protocol, the receiver is not actually disabled during transmission. 10?11 ? reserved, should be cleared. 4 datasheet u .com
scc bisync mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 31-11 31.12 scc bisync receive bd (rxbd) the cp uses bds to report on each buffer received. it closes the buffer, generates a maskable interrupt, and starts receiving data into the next buffer after any of the following: ? a user-defined control character is received. ? an error is detected. ? a full receive buffer is detected. ? the enter hunt mode command is issued. ? the close rx bd command is issued. figure 31-6 shows the scc bisync rxbd. table 31-11 describes scc bisync rxbd status and control fields. 12?13 rpm receiver parity mode. selects the type of parity check that the receiver performs. rpm can be modified on-the-fly and is ignored unless crc = 11 (lrc). receive parity errors cannot be disabled but can be ignored. 00 odd parity. the transmitter counts ones in the data word. if the sum is not odd, the parity bit is set to ensure an odd number. an even sum indicates a transmission error. 01 low parity. if the parity bit is not low, a parity error is reported. 10 even parity. an even number must result from the calculation performed at both ends of the line. 11 high parity. if the parity bit is not high, a parity error is reported. 14?15 tpm transmitter parity mode. selects the type of parity th e transmitter performs and can be modified on-the-fly. tpm is ignored unless crc = 11 (lrc). 00 odd parity 01 force low parity (always send a zero in the parity bit position) 10 even parity 11 force high parity (always send a one in the parity bit position) 0123456789101112131415 offset + 0 e ? wi cb cm ? de ? dl pr cr ov cd offset + 2 data length offset + 4 rx data buffer pointer offset + 6 figure 31-6. scc bisync rxbd table 31-11. scc bisync rxbd status and control field descriptions bits name description 0eempty 0 the buffer is full or stopped receiving because of an error. the core can read or write any fields of this rxbd. the cp does not use this bd as long as the e bit is zero. 1 the buffer is not full. the cp controls this bd and buffer. the core should not update this bd. 1 ? reserved, should be cleared. table 31-10. psmr field descriptions (continued) bits name description 4 datasheet u .com
scc bisync mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 31-12 freescale semiconductor data length and buffer pointer fields are described in section 28.3, ?scc buffer descriptors (bds).? data length represents the number of octets the cp writ es into this buffer, including the bcs. for bisync mode, clear these bits. it is incremented each time a received character is written to the buffer. 31.13 scc bisync transmit bd (txbd) the cp arranges data to be sent on an scc channel in buffers referen ced by the channel txbd table. the cp uses bds to confirm transmission or indicate erro rs so the core knows buffers have been serviced. the user configures status and control bits before transmission, but the cp sets them after the buffer is sent. 2 w wrap (last bd in table) 0 not the last bd in the table 1 last bd in the table. after this bu ffer is used, the cp receives incomi ng data into the first bd that rbase points to. the number of bds in this table is determi ned by the w bit and by overall space constraints of the dual-port ram. 3 i interrupt 0 no interrupt is generated after this buffer is used. 1 scce[rxb] is set when the controller closes this bu ffer, which can cause an interrupt if it is enabled. 4 c control character. the last byte in the buffer is a user-defined control character. 0 the last byte of this buffer does not contain a control character. 1 the last byte of this buffer contains a control character. 5 b bcs received. the last bytes in the buffer contain the received bcs. 0 this buffer does not contain the bcs. 1 this buffer contains the bcs. a control character may also reside one byte prior to this bcs. 6 cm continuous mode 0 normal operation 1 the cp does not clear e after this bd is closed; the buffer is overwritten when the cp accesses this bd next. however, e is cleared if an error occurs during reception, regardless of how cm is set. 7 ? reserved, should be cleared. 8 de dpll error. set when a dpll error occurs during re ception. in decoding modes where a transition is should occur every bit, the dpll error is set when a transition is missing. 9?10 ? reserved, should be cleared. 11 dl dle follow character error. while in transparent m ode, a dle character was received, and the next character was not dle, sync, or a valid entry in the control characters table. 12 pr parity error. set when a character with parity error is received. upon a parity error, the buffer is closed; thus, the corrupted character is the last byte of the buffer. a new rx buffer receives subsequent data. 13 cr bcs error. updated every time a byte is written to t he buffer. the cr bit includes the calculation for the current byte. by clearing psmr[rcbs] within 8 serial clocks, the user can exclude the current character from the message bcs calculation. the data length field may be read to determine the current character?s position. 14 ov overrun. set when a receiver overrun occurs during frame reception 15 cd carrier detect lost. indicates when the carrier detect signal, cd , is negated during frame reception table 31-11. scc bisync rxbd status and control field descriptions (continued) bits name description 4 datasheet u .com
scc bisync mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 31-13 table 31-12 describes scc bisync txbd status and control fields. 0123456789101112131415 offset + 0 r ? w i l tb cm br td tr b ? un ct offset + 2 data length offset + 4 tx data buffer pointer offset + 6 figure 31-7. scc bisync transmit bd (txbd) table 31-12. scc bisync txbd status and control field descriptions bits name description 0rready 0 the buffer is not ready for transmission. the current bd and buffer can be updated. the cp clears r after the buffer is sent or after an error condition. 1 the user-prepared buffer has not been sent or is being sent. this bd cannot be updated while r = 1. 1 ? reserved, should be cleared. 2 w wrap (last bd in table) 0 not the last bd in the table 1 last bd in the table. after this buffer is used, th e cp sends data using the bd pointed to by tbase. the number of txbds in this table is determined only by the w bit and overall space constraints of the dual-ported ram. 3 i interrupt 0 no interrupt is generated after this buffer is serviced. 1 scce[txb] or scce[txe] is set after the cp services this buffer, which can cause an interrupt. 4 l last in message 0 the last character in the buffer is not the last character in the current block. 1 the last character in the buffer is the last characte r in the current block. the transmitter enters and stays in normal mode after sending the last char acter in the buffer and the bcs, if enabled. 5 tb transmit bcs. valid only when the l bit is set. 0 send an syn1?syn2 or idle sequence (specified in gs mr[rtsm]) after the last character in the buffer. 1 send the bcs sequence after the last character. th e controller also resets the bcs generator after sending the bcs. 6 cm continuous mode 0 normal operation 1 the cp does not clear r after this bd is closed, so the buffer is resent when the cp next accesses this bd. however, r is cleared if an error occurs during transmission, regardless of how cm is set. 7 br bcs reset. determines whether transmitter bcs accumulation is reset before sending the data buffer. 0 bcs accumulation is not reset. 1 bcs accumulation is reset before sending the data buffer. 8 td transmit dle 0 no automatic dle transmission can occur before the data buffer. 1 the transmitter sends a dle character before sending the buffer, which saves writing the first dle to a separate buffer in transparent mode. see tr for information on control characters. 4 datasheet u .com
scc bisync mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 31-14 freescale semiconductor data length and buffer pointer fields are described in section 28.3, ?scc buffer descriptors (bds).? although it is never modified by the cp, data length should be greater than zero. the cpm writes these fields after it finish es sending the buffer. 31.14 bisync event register (scc e)/bisync mask register (sccm) the bisync controller uses the s cc event register (scce) to report events rec ognized by the bisync channel and to generate interrupts. when an event is recognized, th e controller sets the corresponding scce bit. interrupts are enabled by setting, and masked by clearing, the equivalent bits in the bisync mask register (sccm). scce bits are reset by writing ones; writing ze ros has no effect. unmasked bits must be reset before the cp negates the internal interrupt request signal. 9 tr transparent mode 0 the transmitter enters and stays in normal mode after sending the buffer. the transmitter automatically inserts syncs if an underrun condition occurs. 1 the transmitter enters or stays in transparent m ode after sending the buffer. it automatically inserts dle?sync pairs if an underrun occurs (the controller finishes a buffer with l = 0 and the next bd is not available). it also checks all characters before sendin g them. if a dle is detected, another dle is sent automatically. insert a dle or program the controller to insert one before each control character. the transmitter calculates the crc16 bcs even if psmr[bc s] is programmed to lrc. initialize ptcrc to crc16 before setting tr. 10 b bcs enable 0 the buffer consists of characters that are excluded from bcs accumulation. 1 the buffer consists of characters that are included in bcs accumulation. 11?13 ? reserved, should be cleared. 14 un underrun. set when the bisync controller encount ers a transmitter underrun error while sending the associated data buffer. the cpm writes un after it sends the associated buffer. 15 ct cts lost. the cp sets ct when cts is lost during message transmission after it sends the data buffer. 0 456789101112131415 field ? dcc ? gra ? txe rch bsy txb rxb reset 0000_0000_0000_0000 r/w r/w offset 0x9_1a10 (scce1); 0x9_1a50 (scce3); 0x9_1a70 (scce4) 0x9_1a14 (sccm1); 0x9_1a54 (sccm3); 0x9_1a74 (sccm4) figure 31-8. bisync event register (scce)/bisync mask register (sccm) table 31-12. scc bisync txbd status and control field descriptions (continued) bits name description 4 datasheet u .com
scc bisync mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 31-15 table 31-13 describes scce and sccm fields. 31.15 scc status registers (sccs) the scc status (sccs) register, as seen in figure 31-9 , allows real-time m onitoring of rxd. the real-time status of cts and cd are part of the parallel i/o. table 31-14 describes sccs fields. table 31-13. scce/sccm field descriptions bits name description 0?4 ? reserved, should be cleared. 5 dcc dpll cs changed. set when carrier sense status gen erated by the dpll changes. real-time status can be found in sccs. this is not the cd status discussed elsewhere. valid only when dpll is used. 6?7 ? reserved, should be cleared. 8 gra graceful stop complete. set as soon the transmitter finishes any message in progress when a graceful stop transmit is issued (immediately if no message is in progress). 9?10 ? reserved, should be cleared. 11 txe tx error. set when an error occurs on the transmitter channel 12 rch receive character. set when a character is received and written to the buffer 13 bsy busy. set when a character is received and discarded due to a lack of buffers. the receiver resumes reception after an enter hunt mode command. 14 txb tx buffer. set when a buffer is sent. txb is set as the last bit of data or the bcs begins transmission. 15 rxb rx buffer. set when the cpm closes the receive buffer on the bisync channel 01234567 field ? cs ? reset 0000_0000 r/w r offset 0x9_1a17 (sccs1); 0x9_1a57 (sccs3); 0x9_1a77 (sccs4) figure 31-9. scc status registers (sccs) table 31-14. sccs field descriptions bits name description 0?5 ? reserved, should be cleared. 6 cs carrier sense (dpll). shows the real-time carrier sense of the line as determined by the dpll. 0 the dpll does not sense a carrier. 1 the dpll senses a carrier. 7 ? reserved, should be cleared. 4 datasheet u .com
scc bisync mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 31-16 freescale semiconductor 31.16 programming the scc bisync controller software has two ways to handle data received by th e bisync controller. the simplest is to allocate single-byte receive buffers, request an interrupt on reception of each buffer, and implement bisync protocol entirely in software on a byte-by-byte basis. this flexible approach can be adapted to any bisync implementation. the obvious penalty is th e overhead caused by interrupts on each received character. a more efficient method is to prepare and link multi- byte buffers in the rxbd table and use software to analyze the first two to three bytes of the buffer to determine the type of block received. when this is determined, reception continues with out further software interventi on until it encounters a control character, which signifies the end of the block and causes software to revert to by te-by-byte reception. to accomplish this, set sccm[rch] to enable an inte rrupt on every received byte so software can analyze each byte. after analyzing the initial characters of a block, either set psmr[rtr] or issue a reset bcs calculation command. for example, if a dle-stx is recei ved, enter transparent mode. by setting the appropriate psmr bit, the controller strips the leading dle from dle- character sequences. thus, control characters are recognized only when they follow a dle character. psmr[ rtr] should be cleared after a dle-etx is received. alternatively, after an soh is received, a reset bcs calculation should be issued to exclude soh from bcs accumulation and reset the bcs. notice that psmr[rbcs] is not needed because the controller automatically excludes syncs and leading dles. after the type of block is recogni zed, scce[rch] should be masked. the core does not interrupt data reception until the end of the current block, which is indicated by the reception of a control character matching the one in the receive control character table. using table 31-15 , the control character table should be set to recognize the end of the block. after etx, a bcs is expected; then the buffer should be closed. h unt mode should be entered when a line turnaround occurs. enq characters are used to st op sending a block and to de signate the end of the block for a receiver, but no crc is expected. af ter control character reception, set sccm[rch] to re-enable interrupts for each byte of data received. table 31-15. control characters control characters ebh etx 011 itb 010 etb 011 enq 000 next entry 0 x x 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 32-1 chapter 32 scc transparent mode transparent mode (also called totally transparent or promiscuous mode) provide s a clear channel on which an scc can send or receive serial data without bit-level manipulation. software im plements protocols run over transparent mode. an scc in transparent mode functions as a high-speed serial-to-parallel and parallel-to-serial converter. transparent mode can be used for serially moving data that requires no supe rimposed protocol, for applications that require serial-to-parallel and parallel-to-se rial conversion fo r communication among chips on the same board, and for appli cations that require data to be switched without interfering with the protocol encoding itself, such as when data from a high-speed time -multiplexed serial stream is multiplexed into low-speed data st reams. the concept is to switch th e data path without altering the protocol encoded on that data path. transparent mode is configured in the gsmr; see section 28.2, ?general scc mode registers (gsmr1?gsmr4).? transparent mode is selected in gs mr_h[ttx, trx] for the transmitter and receiver, respectively. setting both bits enables full -duplex transparent operation. if only one is set, the other half of the scc uses the protocol specified in gsmr_l[mode]. this allows loopback modes to dma data from one memory location to another whil e data is converted to a specific serial format. the scc operations are async hronous with the core and can be synchronous or asynchronous with other sccs. each clock can be supplied fro m the internal baud rate generato r bank, dpll output, or external pins. the scc can work with the time-slot assigner (tsa ) or nonmultiplexed serial interface (nmsi) and supports modem lines with th e general-purpose i/o pins. data can be tr ansferred either the msb or lsb first in each octet. 32.1 features the following list summarizes the main fe atures of the scc in transparent mode: ? flexible buffers ? automatic sync de tection on receive ? crcs can be sent and received ? reverse data mode ? another protocol can be performe d on the other half of the scc. ? mc68360-compatible sync options 4 datasheet u .com
scc transparent mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 32-2 freescale semiconductor 32.2 scc transparent channel frame transmission process the transparent transmitter is designed to work with minimal intervention from the core. when the core enables the scc transmitter in transparent mode, it st arts sending idles, which are logic high or encoded ones, as programmed in gsmr_l[tend]. the scc polls the first bd in the txbd table. when there is a message to send, the scc fe tches data from memory, loads the tran smit fifo, and wait s for transmitter synchronization, which is achieved with cts or by waiting for the receiver to achieve synchronization, depending on gsmr_h[txsy]. transm ission begins when transmitter synchronization is achieved. when all bd data has been sent, if txbd[l] is set, the scc writes th e message status bits into the bd, clears txbd[r], and sends idles until the next bd is ready. if it is r eady, some idles are still sent. the transmitter resumes sending only af ter it achieves synchronization. if txbd[l] is cleared when the e nd of the bd is reached, only txbd[r ] is cleared and the transmitter moves immediately to the next buffe r to begin transmission with no gap on the serial line between buffers. failure to provide the next buf fer in time causes a transmit underrun which sets scce[txe]. in both cases, an interrupt is issu ed according to txbd[i]. by appropria tely setting txbd[i] in each bd, interrupts are generated after each buf fer or group of buffers is sent. the scc then proceeds to the next bd in the table and any whole number of bytes can be sent. if gsmr_h[revd] is set, the bit order of each byte is reversed before being sent ; the msb of each octet is sent first. setting gsmr_h[tfl] makes th e transmit fifo smaller and reduces transmitter la tency, but it can cause transmitter underruns at hi gher transmission speeds. an optional cr c, selected in gsmr_h[tcrc], can be appended to each transparent fram e if it is enabled in the txbd. when the time-slot assigner (tsa) is used with a tr ansparent-mode channel, synchronization is provided by the tsa. there is a start-up delay for the transmitter, but delays will always be some whole number of complete tsa frames. this means that n -byte transmit buffers can be mapped directly into n -byte time slots in the tsa frames. 32.3 scc transparent channel frame reception process when the core enables the scc receiver in transparen t mode, it waits to achieve synchronization before data is received. the receiver can be synchronized to the data by a synchronizati on pulse or sync pattern. after a buffer is full, the scc clears rxbd[e] and gene rates a maskable interrupt if rxbd[i] is set. it moves to the next rxbd in the table and begins moving data to its buffer. if the next buffer is not available, scce[bsy] signifies a busy signal that can generate a maskable interrupt. the receiver reverts to hunt mode when an enter hunt mode command or an error is received. if gsmr_h[revd] is set, the bit order of each byte is reversed be fore it is written to memory. setting gsmr_h[rfw] redu ces receiver latency by making the rece ive fifo smaller, which may cause receiver overruns at higher transmission speeds. the receiver always checks the crc of the received frame, according to gsmr_h[tcrc]. if a crc is not required, resulting errors can be ignored. 4 datasheet u .com
scc transparent mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 32-3 32.4 achieving synchronization in transparent mode once the scc transmitter is enabled for transparent ope ration, the txbd is prepared and the transmit fifo is preloaded by the sdma channel, anot her process must occur before data ca n be sent. it is called transmit synchronization. similarly, once the scc receiver is enabled for transparent operation in the gsmr and the rxbd is made empty for the scc, receive synchronization must occur before data can be received. an in-line synchronization patter n or an external synchronization signal can provide bit-level control of the synchronization process wh en sending or receiving. 32.4.1 synchronization in nmsi mode this section describes sync hronization in nmsi mode. 32.4.1.1 in-line synchronization pattern the transparent channel can be prog rammed to receive a synchronizati on pattern. this pattern is defined in the data synchronization register, dsr; see section 28.2.2, ?data synchroni zation register (dsr).? pattern length is specified in gsmr_h[synl], as shown in figure 32-1 . see also section 28.2, ?general scc mode registers (gsmr1?gsmr4).? if a 4-bit sync is selected, recept ion begins as soon as these four b its are received, beginning with the first bit following the 4-bit sync. the transm itter synchronizes on the receiver pattern if gsmr_h[rsyn] = 1. note that the transparent controller does not automati cally send the synchronizati on pattern; therefore, the synchronization pattern must be included in the transmit buffer. 32.4.1.2 external sync hronization signals if gsmr_h[synl] is 0b00, the transmitter uses cts and the receiver uses cd to begin the sequence. these signals share two opt ions?pulsing and sampling. gsmr_h[cdp] and gsmr_h[ct sp] determine whether cd or cts need to be asserted only once to begin reception/transmission or whether they must remain asserted for the duration of the transparent frame. pulse operation allows an unint errupted stream of data. however, use envelope mode to identify frames of transparent data. table 32-1. receiver sync pattern lengths of the dsr gsmr_h[synl] setting bit assignments 0123456789101112131415 00 an external sync signal is used instead of the sync pattern in the dsr 01 4-bit 10 8-bit 11 16-bit 4 datasheet u .com
scc transparent mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 32-4 freescale semiconductor the sampling option determines the delay between cd and cts being asserted and the resulting action by the scc. assume either that these signals are asynchronous to the data and internally synchronized by the scc or that they are synchronous to the data with faster ope ration. this option allows rts of one scc to be connected to cd of another scc and to have the data synchr onized and bit aligned. it is also an option to link the transmitter synchronization to the receiv er synchronization. diagrams for the pulse/envelope and sampling options are shown in section 32.4, ?achieving synchroni zation in transparent mode.? 32.4.1.2.1 external s ynchronization example figure 32-1 shows synchronization using external signals. figure 32-1. sending transparent frames between MPC8555Es MPC8555E(a) and MPC8555E(b) exchange transparent frames and synchronize each other using rts and cd . however, cts is not required because transmi ssion begins at any time. thus, rts is connected directly to the other MPC8555E cd pin. gsmr_h[rsyn] is not used and transmission and reception from each MPC8555E are independent. rxd cd clk x txd rts cd rxd brgo x rts txd clk x brgo x brgo x last bit of frame data first bit of frame data (output is clkx input) txd (output is rxd input) rts (output is cd input) or crc txbd[l] = 1 causes negation of rts cd lost condition terminates reception of frame MPC8555E (a) MPC8555E (b) notes: ? each MPC8555E generates its own transmit clocks. if th e transmit and receive clocks are the same, one MPC8555E can generate transmit and receive clocks for the other MPC8555E. for example, clk x on MPC8555E (b) could be used to clock the transmitter and receiver. ?cts should be configured as always asserted in the parallel i/o or connected to ground externally. ? the required gsmr configurations are diag = 00, ctss = 1, ctsp is a ?don?t care?, cds = 1, cdp = 0, ttx = 1, and trx = 1. revd and tcrc are application-dependent. ? the transparent frame contains a crc if txbd[tc] is set. 4 datasheet u .com
scc transparent mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 32-5 32.4.1.3 transparent mode without explicit synchronization if there is no need to synchronize the transparent co ntroller at a specific point, the user can ?fake? synchronization in one of the following ways: ? tie a parallel i/o pin to the cts and cd lines. then, after enabling the receiver and transmitter, provide a falling edge by manipul ating the i/o pin in software. ? enable the receiver and transmitter for th e scc in loopback mode and then change gsmr_l[diag] to 0b00 wh ile the transmitter and receiver and enabled. 32.4.2 synchronization and the tsa a transparent-mode scc using the time-slot assigner can s ynchronize either on a user-defined inline pattern or by inhere nt synchronization. note that when using the tsa, a newly-enabled tran smitter sends from 10 to 15 frames of idles before sending the actual transparent data due to startup requirements of the tdm. therefore, when loopback testing through the tdm, expect to receive se veral bytes of 0xff before the actual data. 32.4.2.1 inline synchronization pattern the receiver can be programmed to begi n receiving data into the receive buffers only after a specified data pattern arrives. to synchr onize on an inline pattern: ? set gsmr_h[synl]. ? program the dsr with the desired pattern. ? clear gsmr_h[cdp]. ? set gsmr_h[ctsp, ctss, cds]. if gsmr_h[txsy] is also used, the transmitter begins transmission 8 clocks afte r the receiver achieves synchronization. 32.4.2.2 inherent synchronization inherent synchronization assumes sync hronization by default when the chan nel is enabled; all data sent from the tdm to the scc is received. to implement inherent synchronization: ? set gsmr_h[cdp, cds, ctsp, ctss]. if these bits are not set, the received bit stream wi ll be bit-shifted. the scc loses the first received bit because cd and cts are treated as asynchronous signals. 32.4.3 end of frame detection an end of frame cannot be detected in the transparent data st ream since there is no de fined closing flag in transparent mode. therefore, if frami ng is needed, the user must use the cd line to alert the transparent controller of an end of frame. 4 datasheet u .com
scc transparent mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 32-6 freescale semiconductor 32.5 crc calculation in transparent mode the crc calculations follow the itu/ieee standard. the crc is cal culated on the transmitted data stream; that is, from lsb to ms b for non-bit-reversed (gsmr_h[revd] = 0) and from msb to lsb for bit-reversed (gsmr_h[revd] = 1) transmission. the appended crc is sent msb to lsb. when receiving, the crc is calculated as the incomi ng bits arrive. the optional reversal of data (gsmr_h[revd] = 1) is done just before data is stored in memory (after the crc calculation). 32.6 scc transparent parameter ram for transparent mode, the protocol-specific area of the scc parameter ram is mapped as in table 32-2 . crc_p and crc_c overlap with the crc parameters for the hdlc-bas ed protocols. however, this overlap is not detrimental si nce the crc constant is used only for th e receiver and the c rc preset is used only for the transmitter, so only one entry is re quired for each. thus, the user can choose an hdlc transmitter with a transparent receiver or a transparent transm itter with an hdlc receiver. 32.7 scc transparent commands the following transmit and r eceive commands are issued to the cp command register. table 32-3 describes transmit commands. table 32-2. scc transparent parameter ram memory map offset 1 1 from scc base address. see section 28.4.1, ?scc base addresses.? name width description 0x 30 crc_p long crc preset for totally transparent. for th e 16-bit crc-ccitt, initialize with 0x0000_ffff. for the 32-bit crc-ccitt, initialize with 0xffff_f fff and for the crc-16, initialize with ones (0x0000_ffff) or zeros (0x0000_0000). 0x 34 crc_c long crc constant for totally transparent re ceiver. for the 16-bit crc-ccitt, initialize with 0x0000_f0b8. for the 32-bit crc-ccitt, crc_c initialize with 0xdebb_20e3 and for the crc-16, which is normally used with bisync, initialize with 0x0000_0000. table 32-3. transmit commands command description stop transmit after hardware or software is reset and the channel is enabled in the gsmr, the channel is in transmit enable mode and starts polling the first bd every 64 clocks (or immediately if todr[tod] = 1). stop transmit disables frame transmission on the transmit channel. if the tr ansparent controller receives the command during frame transmission, transmission is aborted after a maximum of 64 a dditional bits and the transmit fifo is flushed. the current txbd pointer (tbptr) is not advanced, no new bd is accessed and no new buffers are sent for this channel. the transmitter will send idles. graceful stop transmit stops transmission smoothly, rather than abruptly , in much the same way that the regular stop transmit command stops. it stops transmission after the current fram e finishes or immediately if no frame is being sent. a transparent frame is not complete until a bd with txbd[l ] set has its buffer complete ly sent. scce[gra] is set once transmission stops; transmit parameters and their bds can then be modified. the current txbd pointer (tbptr) advances to the next txbd in the table. transmission resumes once txbd[r] is set and a restart transmit command is issued. 4 datasheet u .com
scc transparent mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 32-7 table 32-4 describes receive commands. 32.8 handling errors in the transparent controller the scc reports message reception and transmission errors using the chan nel buffer descriptors, the error counters, and scce. table 32-5 describes transmit errors. restart transmit re-enables transmission of characters on the transmit channel. the transparent cont roller expects it after a stop transmit command is issued (at which point the channel is disabled in sccm), after a graceful stop transmit command is issued, or after a transmitter error. the trans parent controller resumes transmission from the current tbptr in the channel txbd table. init tx parameters initializes all transmit parameters in the serial channe l parameter ram to reset state. issue only when the transmitter is disabled. init tx and rx parameters resets receive and transmit parameters. table 32-4. receive commands command description enter hunt mode after hardware or software is reset and the channel is enabled, the channel is in receive enable mode and uses the first bd in the table. enter hunt mode forces the transparent receiver to the current frame and enter hunt mode where the transparent controller waits for the syn chronization sequence. after receiving the command, the current buffer is closed. further data reception uses the next bd. close rxbd forces the scc to close the rxbd if it is being used an d to use the next bd for an y subsequently received data. if the scc is not receiving data, no action is taken by this command. init rx parameters initializes all receive parameters in this serial channel pa rameter ram to reset state. issue only when the receiver is disabled. init tx and rx parameters resets receive and transmit parameters. table 32-5. transmit errors error description tr a n s m i t t e r underrun when this occurs, the channel stops sending the buffer, closes it, sets txbd[un], and generates a txe interrupt if it is enabled. transmission resumes after a restart transmit command is received. underrun occurs after a transmit frame for which txbd[l] was not set. in this case, only scce[txe] is set. underrun cannot occur between transparent frames. cts lost during message transmission when this occurs, the channel stops sending the buff er, closes it, sets txbd[ct], and generates the txe interrupt if it is enabled. the channel resumes sending after restart transmit is received. table 32-3. transmit commands (continued) command description 4 datasheet u .com
scc transparent mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 32-8 freescale semiconductor table 32-6 describes receive errors. 32.9 transparent mode and the psmr the protocol-specific mode regist er (psmr) is not used by the tr ansparent controller because all transparent mode selections are made in the gsmr. if only half of an scc (transmitter or receiver) is running the transparent protocol, the ot her half (receiver or transmitter) can support another protocol. in such a case, use the psmr for the non-transparent protocol. 32.10 scc transparent receive buffer descriptor (rxbd) the cpm reports information about the received data for each buffer using an rxbd (see figure 32-2 ), closes the current buffer, generates a maskable interrupt , and starts receivi ng data into the next buffer after one of the following occurs: ? an error is detected. ? a full receive buffer is detected. ?an enter hunt mode command is issued. ?a close rxbd command is issued. table 32-6. receive errors error description overrun the scc maintains a receive fifo. the cpm starts programming the sdma channel if the buffer is in external memory and updating the crc when 8 or 32 bits are received in the fifo as determined by gsmr_h[rfw]. if a fifo overrun occu rs, the scc writes the received byte over the previously received byte. the previous character and its status bits are lost. afterwards, the channel closes the buffer, sets ov in the bd, and generates the rxb interrupt if it is enab led. the receiver immediately enters hunt mode. cd lost during message reception when this occurs, the channel stops receiving messages , closes the buffer, sets rxbd[cd], and generates the rxb interrupt if it is enabled. this error has highest priority. the rest of the me ssage is lost, and no other errors are checked in the message. the receiver immediately enters hunt mode. 0123456789101112131415 offset + 0 e ? w i l f cm ? de ? no ? cr ov cd offset + 2 data length offset + 4 rx buffer pointer offset + 6 figure 32-2. scc transparent receive buffer descriptor (rxbd) 4 datasheet u .com
scc transparent mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 32-9 table 32-7 describes rxbd status and control fields. table 32-7. scc transparent rxbd status and control field descriptions bits name description 0eempty 0 the buffer is full or stopped receiving data because an error occurred. the core can read or write to any fields of this rxbd. the cpm does not use this bd when rxbd[e] is zero. 1 the buffer is not full. this rxbd and buffer are owned by the cpm. once e is set, the core should not write any fields of this rxbd. 1 ? reserved, should be cleared. 2 w wrap (final bd in table) 0 not the last bd in the table 1 last bd in the table. after this bu ffer is used, the cpm receives data into the first bd that rbase points to. the number of bds in this table is determined onl y by rxbd[w] and overall space constraints of the dual-port ram. 3 i interrupt 0 no interrupt is generated after this buffer is used. 1 when this buffer is closed by the transparent contro ller, the scce[rxb] is set. scce[rxb] can cause an interrupt if it is enabled. 4 l last in frame. set by the transparent controller when th is buffer is the last in a frame, which occurs when cd is negated (if gsmr_h[cdp] = 0) or an error is received. if an error is received, one or more of rxbd[ov, cd, de] are set. note that the scc transparen t controller writes the number of buff er (not frame) octets to the last bd?s data length field. 0 not the last buffer in a frame 1 last buffer in a frame 5 f first in frame. the transparent controller sets f when this buffer is the first in the frame: 0 not the first buffer in a frame 1 first buffer in a frame 6 cm continuous mode 0 normal operation 1 the cpm does not clear rxbd[e] after this bd is cl osed, letting the buffer be overwritten when the cpm next accesses this bd. however, rxbd[e] is cleared if an error occurs during reception, regardless of how cm is set. 7 ? reserved, should be cleared. 8 de dpll error. set by the transparent controller when a dpll error occurs as this buffer is received. in decoding modes, where a transition is promised every bit, de is set when a missing transition occurs. if a dpll error occurs, no other error checking is performed. 9?10 ? reserved, should be cleared. 11 no rx non-octet. set when a frame containing a number of bits not exactly divisible by eight is received. 12 ? reserved, should be cleared. 13 cr crc error indication bits. indicates that this frame contains a crc error. the received crc bytes are always written to the receive buffer. crc checking cannot be disabled, but it can be ignored. 14 ov overrun. indicates that a receiver overrun occurred during buffer reception 15 cd carrier detect lost. indicates when cd is negated during buffer reception 4 datasheet u .com
scc transparent mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 32-10 freescale semiconductor data length and buffer pointer fields are described in section 28.3, ?scc buffer descriptors (bds).? the rx buffer pointer must be divisible by four, unless gsmr_h[rfw] is set to 8 bits wide, in which case the pointer can be even or odd. the buffer can reside in internal or external memory. 32.11 scc transparent transmit buffer descriptor (txbd) data is sent to the cpm for tran smission on an scc channel by arranging it in buffers referenced by the txbd table. the cpm uses bds to confirm transmis sion or indicate error conditions so the processor knows buffers have been serviced. stat us and control bits must be prepar ed before transmission; they are set by the cpm after the buffer is sent. the txbd is shown in figure 32-3 . figure 32-8 describes scc transparent txbd status and control fields. 01234567 131415 offset + 0 r ? w i l tc cm ? un ct offset + 2 data length offset + 4 tx buffer pointer offset + 6 figure 32-3. scc transparent transmit buffer descriptor (txbd) table 32-8. scc transparent txbd st atus and control field descriptions bits name description 0 r ready 0 the buffer is not ready for transmission. the bd and buffer can be updated. the cpm clears r after the buffer is sent or after an error is encountered. 1 the user-prepared buffer is not sent yet or is being sent. this bd cannot be updated while r = 1. 1 ? reserved, should be cleared. 2 w wrap (final bd in table) 0 not the last bd in the table 1 last bd in the table. after this buffer is used, the cpm receives incoming data in to the first bd that tbase points to. the number of txbds in this table is determined only by txbd[w] and overall space constraints of the dual-port ram. 3 i interrupt. note that clea ring this bit does not disable all scce[txe] events. 0 no interrupt is generated after this buffer is serviced. 1 when the cpm services this buffer, scce[txb] or scce [txe] is set. these bits can cause interrupts if they are enabled. 4 l last in message 0 the last byte in the buffer is not the last byte in the transmitted transparent fr ame. data from the next transmit buffer is sent immediately after the last byte of this buffer. 1 the last byte in the buffer is the last byte in the tran smitted transparent frame. after this buffer is sent, the transmitter requires synchronization before the next buffer is sent. 5 tc transmit crc. 0 no crc sequence is sent after this buffer. 1 a frame check sequence defined by gsmr_h[tcrc] is sent after the last byte of this buffer. 4 datasheet u .com
scc transparent mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 32-11 data length and buffer pointer fields are described in section 28.3, ?scc buffer descriptors (bds).? although it is never modified by the cp, data length should be greater th an zero. the buffer pointer can be even or odd and can reside in internal or external memory. 32.12 scc transparent event regist er (scce)/mask register (sccm) when the scc is in transparent mode, the scc event register (scce) functions as the transparent event register to report events recognized by the transparent channel and to ge nerate interrupts. when an event is recognized, the transparent controller sets the co rresponding scce bit. interr upts are enabled by setting, and masked by clearing, the equivalent bits in the transparent mask register (sccm). event bits are reset by writing ones; writing zeros has no effect. all unm asked bits must be reset before the cp clears the internal interrupt re quest to the cpm interrupt controller. figure 32-4 shows the event and mask registers. table 32-9 describes scce/sccm fields. 6 cm continuous mode 0 normal operation 1 the cpm does not clear txbd[r] after this bd is clos ed, so the buffer is automatically resent when the cpm accesses this bd next. however, txbd[r] is cleared if an error occurs during transmission, regardless of how cm is set. 7?13 ? reserved, should be cleared. 14 un underrun. set when the scc encounters a transmi tter underrun condition while sending the buffer. 15 ct cts lost. indicates the cts was lost during frame transmission. 0 4 5 6 7 8 9 10 11 12 13 14 15 field ? dcc ? gra ? txe ? bsy txb rxb reset 0000_0000_0000_0000 r/w r/w offset 0x9_1a10 (scce1); 0x9_1a50 (scce3); 0x9_1a70 (scce4) 0x9_1a14 (sccm1); 0x9_1a54 (sccm3); 0x9_1a74 (sccm4) figure 32-4. scc transparent event register (scce)/mask register (sccm) table 32-9. scce/sccm field descriptions bits name description 0?4 ? reserved, should be cleared. 5 dcc dpll cs changed. set when the dpll-generated carrier sense status changes (valid only when the dpll is used). real-time status can be read in sccs. this is not the cd status mentioned elsewhere. 6?7 ? reserved, should be cleared. table 32-8. scc transparent txbd status and control field descriptions (continued) bits name description 4 datasheet u .com
scc transparent mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 32-12 freescale semiconductor 32.13 scc status register in transparent mode (sccs) the scc status register (sccs), shown in figure 32-5 , allows monitoring of r eal-time status conditions on the rxd line. the real-time status of cts and cd are part of the parallel i/o. table 32-10 describes sccs fields. 8 gra graceful stop complete. set when a graceful stop init iated by completes as soon as the transmitter finishes any frame in progress when the graceful stop transmit command was issued. imm ediately if no frame was in progress when the command was issued. 9?10 ? reserved, should be cleared. 11 txe tx error. set when an error occurs on the transmitter channel. 12 ? reserved, should be cleared. 13 bsy busy condition. set when a byte or word is received and discarded due to a lack of buffers. the receiver resumes reception after it gets an enter hunt mode command. 14 txb tx buffer. set no sooner than when the last bit of the la st byte of the buffer begins transmission, assuming l is set in the txbd. if it is not, txb is set when the last byte is written to the transmit fifo. 15 rxb rx buffer. set when a complete buffer was received on the scc channel, no sooner than 2 serial clocks after the last bit of the last byte in which the buffer is received on rxd. 0 567 field ? cs ? reset 0000_0000 r/w r offset 0x9_1a17 (sccs1); 0x9_1a57 (sccs3); 0x9_1a77 (sccs4) figure 32-5. scc status register in transparent mode (sccs) table 32-10. sccs field descriptions bits name description 0?5 ? reserved, should be cleared. 6 cs carrier sense (dpll). shows the real-time carrier sense of the line as determined by the dpll. 0 the dpll does not sense a carrier. 1 the dpll senses a carrier. 7 ? reserved, should be cleared. table 32-9. scce/sccm field descriptions (continued) bits name description 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 33-1 chapter 33 scc appletalk mode appletalk is a set of protocols developed by apple computer, inc. to provide a lan service between macintosh computers and pr inters. although appletalk can be implemented over a variety of physical and link layers, including ethernet, applet alk protocols have been most clos ely associated with the localtalk physical and link-layer protoc ol, an hdlc-based protocol that runs at 230.4 kbps. in this manual, the term ?appletalk controller? refers to the support that the MPC8555E provides for localtalk protocol. the appletalk controller provides requi red frame synchronization, bit sequen ce, preamble, and onto standard hdlc frames. these capabilities, with the use of the hdlc controller in conjunction with dpll operation in fm0 mode, provide the proper connection formats to the localtalk bus. 33.1 operating the localtalk bus a localtalk frame, shown in figure 33-1 , is basically a m odified hdlc frame. figure 33-1. localtalk frame format first, a synchronization sequence of more than three bi ts is sent. this sequence consists of at least one logical one bit (fm0 encoded) follow ed by two bit times or more of line idle with no particular maximum time specified. the idle time allows localtalk equi pment to sense a carrier by detecting a missing clock on the line. the remainder of the frame is a typical half-duplex hdlc frame. two or more flags are sent, allowing bit, byte, and frame delineation or detecti on. two bytes of address, destination, and source are sent next, followed by a byte of co ntrol and 0?600 data bytes. next, two bytes of crc (the common 16-bit crc-ccitt polynomial referenced in th e hdlc standard protocol) are sent . the localtalk frame is then terminated by a flag and a restricted hdlc abort se quence. then the transmitte r?s driver is disabled. the control byte within the localtalk frame indicat es the type of frame. control byte values from 0x01?0x7f are data frames; control byt e values from 0x80?0xff are contro l frames. four control frames are defined: ? enq?enquiry ? ack?enquiry acknowledgment ?rts ?request to send a data frame ?cts ?clear to send a data frame frames are sent in groups known as dialogs, which are handled by the soft ware. for instance, to transfer a data frame, three frames ar e sent over the network. an rts frame (not to be c onfused with the rs-232 > 3 bits 2 or more 1 byte 1 byte 0?600 bytes 2 bytes 12?18 ones 1 byte 1 byte bytes hdlc crc-16 flags destination address data (optional) control byte sync sequence source address closing flag abort sequence 4 datasheet u .com
scc appletalk mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 33-2 freescale semiconductor rts pin) is sent to re quest the network, a cts frame is sent by the destinat ion node, and the data frame is sent by the requesting node. these three frames comp rise one possible type of dialog. after a dialog begins, other nodes cannot start sending until the dialog is complete. frames within a dialog are sent with a maximum interframe gap (ifg) of 200 s. although the localtalk spec ification does not state it, there is also a minimum recommended if g of 50 s. dialogs must be sepa rated by a minimum interdialog gap (idg) of 400 s. in general, these ga ps are implemented by the software. depending on the protocol, collisions should be encountered only during rts and enq frames. once frame transmission begins, it is fully sent, regardless of whether it co llides with another frame. enq frames are infrequent and are sent only when a node powers up and enters the network. a higher-level protocol controls the uniqueness and transmission of enq frames. in addition to the frame fields, localtalk requires th at the frame be fm0 (diffe rential manche ster space) encoded, which requires one level tran sition on every bit boundary. if the va lue to be encoded is a logical zero, fm0 requires a second transitio n in the middle of the bit time. the purpose of fm0 encoding is to avoid having to transmit clocking in formation on a separate wire. with fm0, the clocking information is present whenever valid data is present. 33.2 features the following list summar izes the features of the scc in appletalk mode: ? superset of the hdlc controller features ? fm0 encoding/decoding ? programmable transmissi on of sync sequence ? automatic postamble transmission ? reception of sync sequence does not cause extra scce[dcc] interrupts ? reception is automatically di sabled while sending a frame ? transmit-on-demand feat ure expedites frames ? connects directly to an rs-422 transceiver 33.3 connecting to appletalk as shown in figure 33-2 , the MPC8555E connects to localtalk, and, using txd, rts , and rxd, is an interface for the rs-422 transceiver. the rs-422, in turn, is an interface fo r the localtalk connector. although it is not shown, a passive rc circuit is recommended between the tr ansceiver and connector. 4 datasheet u .com
scc appletalk mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 33-3 figure 33-2. connecting the MPC8555E to localtalk the 16x overspeed of a 3.686-mh z clock can be generated from an exte rnal frequency source or from one of the baud rate generato rs if the resulting output frequency is close to a multiple of the 3.686 mhz frequency. the MPC8555E asserts rts throughout the duration of the frame so that rts can be used to enable the rs-422 transmit driver. 33.4 programming the scc in appletalk mode the appletalk controller is implem ented by setting certain bits in the hdlc controller. otherwise, chapter 30, ?scc hdlc mode,? describes how to program the hdlc controller. use gsmr, psmr, or todr to program the appletalk controller. 33.4.1 programming the gsmr program the gsmr as described below: 1. set mode to 0b0010 (appletalk). 2. set diag to 0b00 for normal operation, with cd and cts grounded or configured for parallel i/o. this causes cd and cts to be internally asserted to the scc. 3. set rdcr and tdcr to (0b10) a 16 clock. 4. set the tenc and renc bits to 0b010 (fm0). 5. clear tend for default operation. 6. set tpp to 0b11 for a preamble pattern of all ones. 7. set tpl to 0b000 to transmit the next frame wi th no synchronization sequence and to 001 to transmit the next frame with the localtalk synchr onization sequence. for example, data frames do not require a preceding synchroniza tion sequence. these bits may be modified on-the-fly if the appletalk protocol is selected. 2 hdlc crc-16 flags destination address data control byte 6-bit sync sequence source address closing flag 16 ones (abort) rs-422 txd rts rxd standard hdlc frame handling mini-din 8 scc rts txd tx data tx enable rx data MPC8555E connection stored in transmit buffer stored in receive buffer 4 datasheet u .com
scc appletalk mode MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 33-4 freescale semiconductor 8. clear tinv and rinv so da ta will not be inverted. 9. set tsnc to 1.5 bit times (0b10). 10. clear edge. both the positive and negative edges are used to change the sample point (default). 11. clear rtsm (default). 12. set all other bits to zero or default. 13. set ent and enr as the last step to begin operation. 33.4.2 programming the psmr follow these steps to program the protocol-specific mode register: 1. set nof to 0b0001 giving two flags before frames (one opening flag, plus one additional flag). 2. set crc 16-bit crc-ccitt. 3. set drt. 4. set all other bits to zero or default. for the psmr definition, see section 30.8, ?hdlc mode register (psmr).? 33.4.3 programming the todr use the transmit-on-demand (todr) register to expedite a transmit frame. see section 28.2.3, ?transmit-on-demand register (todr).? 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 34-1 chapter 34 quicc multi-channel controller (qmc) the quicc multi-channel controller (qmc) functionality can emulat e up to 64 time-division serial channels, using a serial communi cation controller (scc), and a time-division-multiplexed (tdm) physical interface. each of the qmc channels can be independently programmed to perform in either hdlc or transparent mode. any available tdm in the serial inte rface (si) can be used for the qmc protocol. the si transfers the data between the tdm interface and the scc. the scc then performs the multiplexi ng/demultiplexing of the qmc channels. figure 34-1 provides an overview of the qmc functionality. each scc can work in qmc mode, either alone or t ogether in any combination, spreading any of the 64 available qmc channels across the multiple sccs. on e tdm connection can be r outed to one or more sccs operating in qmc mode , with each scc operating on different time slots. it is also possible to use multiple tdms for qmc with combined routing to one scc or to separate sccs. when using multiple tdms connected to the same scc, restrictions such as using common clocks and sync inputs apply; it is also impor tant to avoid collisions by separati ng the serial interface (si) routing, making sure that only one tdm will be accessing the scc at any given time. figure 34-1. qmc channel addressing capability ch0 ch1 ch2 ..... serial interface sccs performs muxing/ unmuxing of tdm?s qmc channel routes all qmc-related time slots to desired sccs si2 ram ch0 ch1 ch2 . . . . data on tdmx interface MPC8555E 4 datasheet u .com
quicc multi-channel controller (qmc) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 34-2 freescale semiconductor 34.1 features qmc-specific features include the following: ? up to 64 independent communication channels on one scc, or split across multiple sccs (64 channels total per device) ? arbitrary mapping of any of 0?63 channels to any tdm time slot ? can support up to two simu ltaneous 32-channel e1 links ? independent mapping possible for receive/transmit ? supports either transparent or hd lc protocols for each channel ? interrupt circular buffer with program mable size and overflow identification ? global loop mode ? individual channel loop mode through the si ? programmable frame length through the si qmc features related to the seri al interface include the following: ? serial-multiplexed (full duplex) input/ output 2048-, 1544-, or 1536-kbps pcm highways ? compatible with t1/ds1 24-channel and cept e1 32-channel pcm highwa y, isdn basic rate, isdn primary rate and user-defined ? subchanneling on each time slot ? allows independent transmit and receiv e routing, frame syncs, and clocking ? concatenation of any, not necessarily consecutiv e, time slots to cha nnels independently for receive/transmit ? supports h0, h11, and h12 isdn channels ? allows dynamic allocation of channels qmc features related to the system interface include the following: ? on-chip bus arbitration for serial dmas with no pe rformance penalty ? efficient bus usage (no bus usage for nonactive channels and active channels that have nothing to transmit) ? efficient control of the interrupts to the cpu ? supports external buffer descriptors table ? uses on-chip enlarged dual-ported ram for parameter storage 34.2 qmc and the serial interface qmc is designed to work in conjunction with the se rial interface, taking adva ntage of its programmable siram and additional functionalities. see chapter 23, ?serial interface with time-slot assigner,? for details on proper programming of the si ?s registers and siram. however, it is pos sible to operate qmc in nonmultiplexed serial interface (nmsi) mode, directly using the s cc?s own pins instead of the tdm interlace pins. functions such as frame synchr onization, loopback, echo, and inverted signals are performed in the serial inte rface and cannot be achieved in nmsi mode . it is recommended to use the serial interface even if only one scc is used for the tdm bus. 4 datasheet u .com
quicc multi-channel controller (qmc) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 34-3 connecting an scc to the si or to its own pins in nmsi mode is selected by programming the cmx scc clock route regist er (cmxscr). see section 24.4.4, ?cmx scc clock route register (cmxscr),? for details on proper programming of the cmxscr. this section describes additional functional ity that the si provides to qmc operation. 34.2.1 synchronization independent receive and transmit cl ocks and frame synchronization signal s control the data transfer. in nmsi operation, synchronization occurs only once after activating qmc, to initiate transfer using the cd (receive) and cts (transmit) signals in pulse mode. if any noise corrupt s either signal or the clock, the qmc will be out of synchronization unt il the whole protocol is restarted. in contrast, the more robus t si performs a synchronizat ion on each frame, limiti ng the damage from noise error on the clock or synchronization lines. noisy channels can be restar ted individually without interrupting other channels. 34.2.2 loopback mode the loopback from a transmitter to a receiver can be implemented on a per qmc channel basis. if channel-specific loopback is desire d, it is important to ha ve each individual qmc time slot represented as an entry in the siram in order to achieve proper operation. a common tr ansmit and receive clock as well as a common frame synchroni zation pulse must be provi ded for loopback mode to work. the loopback is done on a fixed time slot of the actual tdm. 34.2.3 echo mode the si can be programmed to echo in coming data. in this mode, the co mplete tdm link is retransmitted from the incoming l1rxdx to the l1txdx pin on a bit- by-bit basis. the receiver section of the selected scc can operate normally and also receive the inco ming bit stream. this is also known as global echo mode on the whole link. indi vidual time slot echo is not possible with qmc without software intervention. 34.2.4 inverted signals all qmc-related receive and transmit data can be logically inverted by setting the rinv and tinv bits of the gsmr_l register. a logical inversion on a per channel basis is not possible in the qmc without external hardware. to invert a speci fic channel, the si can be program med to send a strobe signal at the qmc channel?s corresponding time slot on the tdm interf ace. this strobe can then be connected to an external xor gate to perform the inversion. 34.2.5 qmc routing changes on-the-fly changes can be made on-the- fly in the qmc routing ta bles, but changes made to si ram require the qmc link to be disabled or require usag e of a shadow ram routing table. th e shadow table can hold alternative routing information to be switched in at the appropriate time-slot boundary. 4 datasheet u .com
quicc multi-channel controller (qmc) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 34-4 freescale semiconductor 34.3 qmc memory organization 34.3.1 qmc memory structure figure 34-2 shows how data is addressed by the qmc prot ocol. it discusses addressing the dual-ported ram to access data within the buffers. figure 34-2. qmc memory structure 34.3.2 scc base and global multi-channel parameters the scc base points to the start of the parameter ram for each of the sccs at 256-byte intervals. when the qmc protocol is enabled on an scc, its para meter ram is used to store the global multi-channel parameters for all the logical channels. this area cont ains parameters and pointer s that are common to all channels. note as the qmc requires 0xaf bytes of parameter ram for its global multi-channel parameters, this ma y cause conflict with other cpm functionality. time slot channel 0 specific parameters 12345678 abcdef12 txbd 1 pointer lc5 tbase channel 1 specific parameters channel 5 specific parameters channel 30 specific parameters channel 31 specific parameters mcbase tx_s_ptr rx_s_ptr tsa table rx tsa table tx 9. data buffer data buffer external memory txbd 2 pointer txbd n pointer 12345678 abcdef12 rxbd 1 pointer rxbd 2 pointer + + pointer 0 scc1 parameter ram scc3 parameter ram scc4 parameter ram 1. dual-ported ram base 4. channel pointer time slot pointer 1 time slot pointer 5 time slot pointer 30 time slot pointer 31 time slot pointer 0 time slot pointer 1 time slot pointer 5 time slot pointer 30 time slot pointer 31 lc5 rbase 6. mcbase 7. bd table scc1 parameter ram 2. scc base 3. time-slot assignment table 64 k external memory 5. logical channel tbase & rbase 8. data buffer pointer rxbd n pointer 4 datasheet u .com
quicc multi-channel controller (qmc) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 34-5 34.3.2.1 tsatrx/tsattx pointers and time-slot assignment table the time-slot assignment table pointers are within the global multi-channel parameters. there are two pointers?tx_s_ptr for transmit an d rx_s_ptr for receive. the rx_s_ptr is normally set to scc base + 20; this is the normal locati on of the receive time-sl ot assignment table. th e tx_s_ptr is normally set to scc base + 60; this is the normal location of the transmit time-slot assignment table. however, if the receiver and the transmitter have the same mappi ng for the logical channels, tx_s_ptr can point to scc base + 20 so that rx and tx have a common time -slot assignment table. note that if a single tdm channel is routed to more than one scc, they may al so use just one time-slot a ssignment table for all sccs. see section 34.3.3, ?multiple s cc assignment tables,? for more information. the time-slot assignment table holds one 32-bit entry for each time-slot. it ha s options for subchanneling, a valid bit, and a logical channel pointer. for 64-channel support there is only sp ace for one table; therefore, common rx and tx parameters will need to be used unless one of the tsa tables can be accommodated elsewhere in memory, such as in the parameter ram area of another scc. associated with the rx/tx_s_ptr are the rx/txptr pointers that are maintained by the cpm and point to the current time slot. 34.3.2.2 tsatrx/tsattx channel pointers the channel pointers are 12-bit pointers to the channe l-specific parameters in the internal dual-ported ram. these should not be confused with tsatrx/tsattx pointers as described in section 34.3.2.1, ?tsatrx/tsattx pointers and time-slot assignment table.? the 6 most-significant bits of the address are taken from the tim e-slot assignment table. the 6 least-sign ificant bits are zero, mapping out a 64-byte area for each of the channel-specif ic parameters. the channel-specific parameters are common for rx and tx. for 32-channel support, 2 kbytes of dual-ported ram is required (32 64), and for 64-channel support, 4 kbytes of dual- ported ram is required (64 64). in most cases, time slot 0 channel pointer will address the base of dual-ported ram for logical channel 0, and time slot 1 channel pointer would address the base of dual-ported ram + 4 for logical channel 1. in figure 34-2 , time slot 5 channel pointer addresses logical channel 5, requiring the channel pointer being set to 0b000101. note it is possible to concatenate multiple ti me slots to one logi cal channel. this is achieved by setting the channel point ers of the grouped time slots to the same logical channel. 34.3.2.3 logical channel tbase and rbase tbase and rbase are within the channel-specific para meters. tbase is the tx buffer descriptor base address, and rbase is the rx buffe r descriptor base address. these 16-bit offsets from mcbase point to individual logical channel?s buffer descriptors located within the buffer descriptor table. note that there are individual tbase and rbase va lues for each logical channel. 34.3.2.4 mcbase mcbase is located in the global multi-channel parameters. each scc has a unique mcbase value pointing to the base of the scc?s buf fer descriptor table in external me mory. for example, the address of logical channel five?s tx buffer de scriptor table is mcbase + logi cal channel five tbase. mcbase 4 datasheet u .com
quicc multi-channel controller (qmc) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 34-6 freescale semiconductor normally points to external ra m, but it is permissible to set it up so that some or all bds are placed within free areas of the dpram. this may save valuab le access time if external memory is slow. 34.3.2.5 buffer descriptor table a buffer descriptor table for each scc is located in a 64-kbyte area of external memory. this block size is determined by the tbase and rbase addre ssing range. the memory segment must be long-word-aligned but can start a nywhere in memory. each scc ha s a maximum of 16,384 (64 kbytes memory 4-byte pointers) buffers. for a 32-channel impleme ntation, each logical channel has a maximum of 256 (16,384 / (32 2)) buffers for recei ve and 256 buffers for transmit. for each logical channel, there is a circular queue with progra mmable start address and length. 34.3.2.6 data buffer pointer as with the standard cpm protocols, the data buffe r is addressed by a 32-bit pointer within the buffer descriptor. this addresses th e data received or transmitt ed from external memory. 34.3.2.7 data buffer the data buffers in external memory can hold up to 64 kbytes of data as determined by the data length in the buffer descriptor. 34.3.2.8 global multi-channel parameters the global multi-channel pa rameters reside in the scc?s parame ter ram page and are common to all logical channels. the largest portion of the global area is the time-slot as signer tables for the receiv er and transm itter section of the scc. for 32-channel support, there is one table for tx and one for rx within the parameter ram. if the connection is split over multiple sccs, this ta ble only needs to be present once for multiple sccs operating in qmc mode. see section 34.3.3, ?multiple s cc assignment tables,? for more information. for 64-channel support there is only space for one table; th erefore common rx and tx parameters will need to be used unless one of the tsa tables can be accommodated elsewhere in memory, such as in the parameter ram area of another scc. the dual-ported ram is used for the ch annel-specific area for all sccs. it is important that individual time slots are mapped to only one scc, and that individual logical channels are sepa rated to avoid contention. table 34-1 lists the global parameters. no te that the boldfaced parameters must be initialized by the user. see section 34.7, ?qmc initialization,? for more information. 4 datasheet u .com
quicc multi-channel controller (qmc) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 34-7 table 34-1. global multi-channel parameters offset to scc base name width (bits) description 00 mcbase 32 multi-channel base pointer?this host-initializ ed parameter points to the starting address of the 64-kbyte buffer descriptor table in external memory. the mcbase is used with the tbase and rbase registers in t he channel-specific parameters. 04 qmcstate 16 multi-channel controller state (initialize to 0x8000)?internal qmc state machine value used by risc processor fo r global state definition. 06 mrblr 16 maximum receive buffer length?this host-initialized entry defines the maximum number of bytes written to a receive buffer before moving to the next buffer for this channel. this parameter is only valid in hdlc mode. the buffer area allocated in memory for each buffer is mrblr + 4. the qmc adds another long word if non-octet-aligned fr ames are received in hdlc operation. the non-octet information is written only to the last buffer of a frame, but it can happen in any buffer. see section 34.6.1, ?receive buffer descriptor,? for more information. as the qmc works on long-word alignment, mrblr value should be a multiple of 4 bytes. 08 tx_s_ptr 16 tx time-slot assignment table pointer (scc base + 60 in normal mode; scc base + 20 for common rx & tx time-slot assignment tables)?this global qmc parameter defines the start value of the tsattx table. the tsattx table in the global multi-channel parameter listing starts by default at scc base + 60. tx_s_ptr lets the user move the starting address of this table. if the same routing and masking are used for the transmitter and receiver, the tables can be overlaid, so tx_s_ptr can point to scc base + 20. this parameter is an offset fr om dprbase. this tabl e must be present only once per scc global area. other sccs can access this location. 0a rxptr 16 rx pointer (initialize to scc base + 20)?this global qmc parameter is a risc variable that points to the current receiver time slot. the host must initialize this pointer to the starting location of tsatrx. the risc proces sor increments this pointer whenever it completes the processing of a received time slot. 0c grfthr 16 global receive frame threshold?used to reduce interrupt overhead when many short hdlc frames arrive, each causing an rxf interrupt. grfthr can be set to limit the frequency of interrupts. set to 1 to get an interrupt per frame received. note that the rxf event is written to the interrupt table on each received frame, but gint is set only when the number of rxf events (by all channel s) reaches the grfthr value. grfthr can be changed on-the-fly. for information about exception handling, see section 34.5, ?qmc exceptions.? 0e grfcnt 16 global receive frame count (initialized grfcnt = grfthr)?a down-counter used to implement the grfthr feature. grfcnt decrements for each frame received. no other receiver interrupts affect this counter. the counter value is set to the threshold during initialization. grfcnt is automatically reset to the grfthr value by the cpm after a global interrupt. 10 intbase 32 multi-channel interrupt base address (host-initialized)?this pointer contains the starting address of the interrupt circular queue in external memory. each entry contains information about an interrupt request that has been generat ed by the qmc to the host. each scc operating in qmc mode has its own interrupt table in external memory. see section 34.5, ?qmc exceptions . ? 14 intptr 32 multi-channel interrupt pointer (host-init ialized)?this global parameter holds the address of the next qmc interrupt entry in the circular interrupt table. the risc processor writes the next interrupt information to this entry when an exception occurs. the host must copy the value of intbase to intptr before enabling interrupts. 4 datasheet u .com
quicc multi-channel controller (qmc) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 34-8 freescale semiconductor 18 rx_s_ptr 16 rx time-slot assignment table pointer (default = scc base + 20 in normal mode)?this global qmc parameter defines the start val ue of the tsatrx table, which must be present only once per scc global area. other sccs may access this location. 1a txptr 16 txptr (initialize to scc base + 60)?this global parameter is a risc variable that points to the current transmitte r time slot. the host must initialize it to the starting location of tsattx. the risc processor incr ements this pointer whenever it completes the processing of a transmitter time slot. 1c c_mask32 32 crc constant (0xdebb20e3) ?required to calcul ate 32-bit crc-cci tt. c_mask32 is written by the host during qmc initialization. it is used for 32-bit crc-ccitt calculation if hdlc mode of operation is chosen for a selected channel. (this is a programmable option. for each hdlc channel, one of two crcs can be chosen, as programmed in chamr.) for more information, see section 34.3.4.1, ?channel-specific hdlc parameters.? this entry must have a correct value if at least one hdlc channel is used; otherwise, it can be cleared (0). 20 tsatrx 32 entries x 16 time slot assignment table rx?host-initiali zed, 16-bit-wide table with 32 entries that define mapping of logical channels to time slots for the qmc receiver. the qmc protocol looks at chunks of 8 bits regardless of whether they come from one physical time slot of the tdm or whatever other combination of bits the tsa transfers to the scc. these 8 bits are referred to as a time slot in the assignment table. it is recommended but not required to route all bits from the tdm to the scc and to do all enabling and masking in the time-slot assignment table. see figure 34-3 . 60 tsattx 32 entries x 16 time slot assignment table tx?maps a specific logical channel to each physical time slot. time slot assignment table tx is a host- initialized, 16-bit table with 32 entries that define the mapping of channels to time slots for the qmc transmitter. the qmc protocol looks at chunks of 8 bits regardless if they go to one physical time slot of the tdm or whatever other combination of bits are tran sferred from the scc to the tdm through the tsa. these 8 bits are referred to as a time slot in the assignment table. it is recommended but not required to route all bits from the tdm to the scc and to do all enabling and masking in the time-slot assignment table. see figure 34-3 . a0 c_mask16 16 crc constant (0xf0b8)?required to calc ulate 16-bit crc-ccitt. this constant is written by the host during qmc initialization. it is used for 16-bit crc-ccitt calculation if hdlc mode of operation is chosen for a selected channel. (this is a programmable option. for each hdlc channel, one of two crcs can be chosen, as programmed in chamr.) for more information, see section 34.3.4.1, ?channel-specific hdlc parameters.? this entry must have a correct value if at least one hdlc channel is used; otherwise, it can be cleared (0). a4 temp_rba 32 temporary receive buffer address a8 temp_crc 32 temporary cyclic redundancy check table 34-1. global multi-channel parameters (continued) offset to scc base name width (bits) description 4 datasheet u .com
quicc multi-channel controller (qmc) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 34-9 note there is no way the receiver and transmitter can shar e the same structure as done on the tsa table when the tdm f unctionality of th e receiver is identical to this of the transmitter. an area of 64 bytes starting at address scc base+0xc 0 up to scc base+0xff is available for this data structure. the user must program the area pointed by rx_frm_base / tx_frm_base as follow: each 1-byte entry corresponds to a tdm channe l numbered per the qmc time-slot assignment table. the number of entries is determined by the number of active channels in the system. each time a channel is initialized, the correspondi ng entry should be programmed to this value. note the area between scc base + 20 and s cc base + 9f is normally used for tsa tables. the mapping a bove is ideal for 32-cha nnel support. the exact mapping of the tsa tables is determ ined by the programming of rx_s_ptr and tx_s_ptr, and is not fixed. for 64- channel support it is suggested to use common rx and tx parameters. the tsa table will be common and have 64 entries starting at scc base + 20; see figure 34-4 . alternatively, another scc?s parameter ram may be used, as determined by rx_s_ptr and tx_s_ptr; see figure 34-6 for more information. however implemented, the tsa tables may resi de anywhere in internal memory. figure 34-3 shows a general time-slot assignmen t table for 32 16-bit time slots. the fields will be used to either transmit or receive channels. ac rx_frm_base 16 this entry contains a pointer to an area in the dpr where the receiver framer temporary parameters reside. the area designated for these parameters is a single byte per tdm channel. when the qmc is handling up to 32 channels it is possible to program this entry to the value scc base+0xc0 thus locating this data structure inside the scc parameter page and save dpr space when using 64 channels this entry should point to a free area of 64 bytes in the dpr which is 64 bytes aligned. ae tx_frm_base 16 this entry contains a pointer to an area in the dpr where the receiver framer temporary parameters reside. the area designated for these parameters is a single byte per tdm channel. when the qmc is handling up to 32 channels it is possible to program this entry to the value scc base+0xe0 thus locating th is data structure inside the scc parameter page and save dpr space when using 64 channels this entry should point to a free area of 64 bytes in the dpr which is 64 bytes aligned. table 34-1. global multi-channel parameters (continued) offset to scc base name width (bits) description 4 datasheet u .com
quicc multi-channel controller (qmc) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 34-10 freescale semiconductor figure 34-3. time-slot assignment table table 34-2 describes the fields in the time -slot assignment table for receive. table 34-2. time-slot assignment table entry fields for receive section field description v valid bit?the valid bit indicates whether this time slot is valid. 0 the data in this 8-bit time slot is tota lly ignored and not written to any buffer. 1 the data in this 8-bit time slot is valid and written to the current buffer, pointed to by the channel pointer entry, after protocol processing (for example, zero deletion in hdlc). individual bits can be masked out as described later. w wrap bit?identifies the last entry in tsatrx 0 this is not the last ti me slot in the frame. 1 the risc processor wraps around and handles time slot 0 or the first 8 bits transferred from the tsa in the next request. the next request is identified by a frame synchronization pulse. rx channel pointer this 6-bit field of the tsatrx entry identifies the data channel routed to this time slot. the actual channel pointer is 12 bits long, and contains the starting addr ess of the channel-specific parameter area (address of rbase). the 6 most-significant bits are taken from the ts atrx channel pointer field, and the 6 leas t-significant bits are always internally set to zero. mask(0?7) mask bits?these 8 bits identify the valid bits in this time slot for subchanneling support. for 8-bit resolution, all mask bits should be set to 1. any unmasked bit (1) is processed in the receiver for a valid time slot. any masked bit (0) is ignored by the receiver for a valid channel and no bit counter is affected. channel pointer w v time slot 0 time slot 1 time slot 30 time slot 31 32 x 16 mask(2:7) mask(0:1) channel pointer w v mask(2:7) mask(0:1) channel pointer w v mask(2:7) mask(0:1) channel pointer w v mask(2:7) mask(0:1) channel pointer w v mask(2:7) mask(0:1) channel pointer w v mask(2:7) mask(0:1) channel pointer w v mask(2:7) mask(0:1) 4 datasheet u .com
quicc multi-channel controller (qmc) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 34-11 table 34-3 describes the fields in the time-slot assignment table for transmit. if the transmitter and receiver have the same mappi ng, it is possible to use a common time-slo t assignment table. this is initialized by setting both tx_s_p tr and rx_s_ptr to scc base + 20. for 64-channel support it is suggested to use common rx and tx parame ters. the time-slot assignment table will then also be common and have 64 entries starting at scc base + 20; see figure 34-4 . table 34-3. time-slot assignment table entry fields for transmit section name description v valid bit?the valid bit indicates whether this time slot is valid. 0 logic 1 is transmitted. if the tx signal of the tdm interface is programmed to be an open drain output (port b programming), other devices can transmit on nonvalid time slots. 1 data is transmitted from its associated buffer in combination with the mask bit settings. w wrap bit?the wrap bit identifies the last entry in tsattx. 0 this is not the last ti me slot in the frame. 1 the risc processor wraps around and handles time slot 0 or the first 8 bits of data in the scc in the next request. the next request is identified by a frame synchronization pulse. tx channel pointer this 6-bit field of the tsattx entry identifies the data ch annel routed to this time slot. the actual channel pointer is 12 bits long, and contains the starting address of the channel-specific paramet er area (address of tbase). the 6 most-significant bits are taken from the tsattx channel pointer field, and the 6 least-significant bits are always internally set to zero. mask(0?7) mask bits?identifies the valid bits in this time slot for subchanneling support. for 8-bit resolution, all mask bits should be set to 1. for a valid channel with an unmasked bit (1), the bit position is filled according to the protocol. a valid channel with a masked bit (0) transmits a logic high (1). 4 datasheet u .com
quicc multi-channel controller (qmc) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 34-12 freescale semiconductor f figure 34-4. time-slot assignment table for 64-channel common rx and tx mapping 34.3.3 multiple scc assignment tables assume a scenario as depicted in figure 34-5 . a 2.048-mbps tdm link is fed directly into the tsa. within the si ram, the even channels (byte-wide ) are muxed to scc3 and the odd channels are muxed to scc1. this arrangement is used to spread the load over two sccs. this effectively doubles the fifo depth on the qmc protocol. ti me slots are switched to alternate sccs to avoid da ta bursts that may stress the fifos. each scc sees a continuous bitstr eam without any gaps as described earlier. channel pointer w v time slot 0 time slot 1 time slot 62 time slot 63 64 x 16 mask(2:7) mask(0:1) channel pointer w v mask(2:7) mask(0:1) channel pointer w v mask(2:7) mask(0:1) channel pointer w v mask(2:7) mask(0:1) channel pointer w v mask(2:7) mask(0:1) channel pointer w v mask(2:7) mask(0:1) channel pointer w v mask(2:7) mask(0:1) 4 datasheet u .com
quicc multi-channel controller (qmc) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 34-13 figure 34-5. rx time-slot assignment table for 32 channels over 2 sccs note it is important that multiples of bytes are routed to each scc to delineate between time slots. unused bits shall be routed to the scc and be masked in the time-slot assignment table. in figure 34-5 , each scc has its own pointer, rx_s_p tr_1 and rx_s_ptr_3, addressing scc1?s time-slot assignment table. this tabl e only needs to be present once in one of the scc1?s global parameter area. rx_s_ptr_1 points to the start of the table, address scc base + 20. the 16 logical channels from scc1 are located in the first 16 entries of the table. the entry for logical channel 30 has the wrap bit (w) set, causing the cpm to wrap back to logical channel 0 on reception of the next byte routed to scc1. rx_s_ptr_3 addresses scc base + 40, the start of the 16 entries for s cc3. the entry for logical channel 31 has the wrap bit (w) set, causing the cpm to wrap back to logi cal channel 1 on reception of the next byte routed to scc3. each entry within the table has a channel pointer to a logical cha nnel. it is important that different sccs do not point to the same logical channel. the tsattx is also located in scc1?s parameter ram. this means that the area reserved for the tsa tables in scc3?s parameter ra m is free for alternative use. v = 1, w = 0, c.p ?> lc0 v = 1, w = 0, c.p ?> lc2 v = 1, w = 0, c.p ?> lc4 v = 1, w = 0, c.p ?> lc28 v = 1, w = 1, c.p ?> lc30 v = 1, w = 0, c.p ?> lc1 v = 1, w = 0, c.p ?> lc3 v = 1, w = 0, c.p ?> lc5 0 2 4 6 28 30 even channels muxed to scc3 odd channels muxed to scc1 1357 2931 0 2 4 6 28 30 rx data stream into tsa 1357 2931 ???? ???? ???? scc1 parameter ram time-slot assignment table rx_1 rx_s_ptr_1 scc3 parameter ram time-slot assignment table rx_3 rx_s_ptr_3 (not used) cpm tsa scc3 scc1 v = 1, w = 0, c.p ?> lc29 v = 1, w = 1, c.p ?> lc31 common tsatrx located in scc1 parameter ram scc base +0x20 scc base +0x40 4 datasheet u .com
quicc multi-channel controller (qmc) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 34-14 freescale semiconductor a second scenario is depicted in figure 34-6 . a 4.096-mbps tdm link is fed di rectly into the tsa. again, within the si ram, the even cha nnels (byte-wide) are m uxed to scc3 and the odd channels are muxed to scc1. this arrangement is used to spread the lo ad over two sccs. another reason this method may be used is to facilitate separate routing for the rx a nd tx logical channels. this requires two 64-entry tables that require 256 bytes, but only 128 bytes are allocate d in the parameter ram of an scc for time-slot assignment tables. in this case, the rx table is loca ted in scc1?s parameter ra m, and the tx table is located in scc3?s parameter ram, making most efficient use of memory. changes on-the-fly are easily accomplished by setting or clearing the valid bit fo r each time slot. changes to the mask bits can also be made on-the-fly. th is does not cause any problems to the qmc microcode itself, but may cause protocol errors on the channe l in question depending on when this change is done. it is possible to have a time-slot assignment table for ev ery scc in its correspondi ng ram page and have all of the tdm routed to th e different sccs. this gives the user a very flexible sy stem that can be changed on-the-fly without disconnecting the td m interface. in this case the user must ensure that no collisions occur on the transmit lines from several sccs. figure 34-6. time-slot assignment tables for 64 channels over 2 sccs scc1 parameter ram time-slot assignment table rx tx_s_ptr_1 scc3 parameter ram tx_s_ptr_3 rx_s_ptr_1 located in scc1 parameter ram time-slot assignment table rx located in scc3 parameter ram rx_s_ptr_3 v = 1, w = 0, c.p ?> lc0 v = 1, w = 0, c.p ?> lc2 v = 1, w = 0, c.p ?> lc4 v = 1, w = 0, c.p ?> lc60 v = 1, w = 1, c.p ?> lc62 v = 1, w = 0, c.p ?> lc1 v = 1, w = 0, c.p ?> lc3 v = 1, w = 0, c.p ?> lc5 0 2 4 6 60 62 even channels muxed to scc3 odd channels muxed to scc1 1357 6163 0 2 4 6 60 62 data stream into tsa 1357 6163 ???? ???? ???? cpm tsa scc3 scc1 v = 1, w = 0, c.p ?> lc61 v = 1, w = 1, c.p ?> lc63 common tsatrx located in scc1 parameter ram scc1 base +0x20 scc1 base +0x60 scc3 base +0x60 scc3 base +0x20 common tsattx located in scc3 parameter ram 4 datasheet u .com
quicc multi-channel controller (qmc) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 34-15 34.3.4 channel-specific parameters the channel-specific parameters are located in th e lower part of the dual-ported ram. each channel occupies 64 bytes of parameters. ph ysical time slots can be matched to logical channels in several combinations. unused logical channels leave a hole in the channel-spec ific parameters that can be used for buffer descriptors for the other sccs. the channel-specific area determines the operating m ode?hdlc or transparent. several entries take on different meanings depending on the protocol chosen. 34.3.4.1 channel-specific hdlc parameters table 34-4 describes the channel-specific hdlc parameters . boldfaced parameters must be initialized by the user. table 34-4. channel-sp ecific hdlc parameters offset name width (bits) description 00 tbase 16 tx buffer descriptor base address?offset of the channel?s transmit buffer descriptor table relative to mcbase, ho st-initialized. see figure 34-2 . 02 chamr 16 channel mode register. see section 34.3.4.1.1, ?cha mr?channel mode register (hdlc).? 04 tstate 32 tx internal state ?tstate defines the internal tx state. initialize before enabling the channel. see section 34.3.4.1.2, ?tstate?tx internal state (hdlc).? 08 ? 32 tx internal data pointer?points to current absolute address of channel. 0c tbptr 16 tx buffer descriptor pointer (host-initialized to tbase before enabling the channel or after a fatal error before reinit ializing the channel agai n)?offset of current bd relative to mcbase. see table 34-1 . mcbase + tbptr gives the address for the bd in use. 0e ? 16 tx internal byte count?number of remaining bytes 10 tupack 32 (tx temp) unpack 4 bytes from 1 long word 14 zistate 32 zero-insertion state (host-initialized to 0x0000 _ 0200 for hdlc or transparent operation)?contains the previous state of the zero-insertion state machine. 18 tcrc 32 temp transmit crc?temp value of crc calculation result 1c intmsk 16 channel?s interrupt mask flags?see section 34.3.4.1.3, ?intms k?interrupt mask (hdlc).? 1e bdflags 16 temp 20 rbase 16 rx buffer descriptor offset (host-initialized) ? defines the offset of the channel?s receive bd table relative to mcbase (64-kbyte table). see figure 34-2 . 4 datasheet u .com
quicc multi-channel controller (qmc) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 34-16 freescale semiconductor 34.3.4.1.1 chamr?channel mo de register (hdlc) the channel mode register is a wo rd-length, host-ini tialized register. figure 34-7 shows the channel mode register for hdlc operation. figure 34-7. chamr?channel mode register (hdlc) table 34-5 describes the channel mode regi ster?s fields for hdlc operation. boldfaced parameters must be initialized by the user. 22 mflr 16 maximum frame length register (host-initialized)?defines the longest expectable frame for this channel. its maximum value is 64 kbytes. th e remainder of a frame which is larger than mflr is discarded and a flag in the last frame? s bd is set (lg). an interrupt request (rxf and rxb) might be generated depending on the interrupt mask. the frame length is considered to be everything between flags, including crc. mflr is checked every long word, but the content may be on any number of bytes. if mflr is set to 5 for example, checking is done when 8 bytes have been received. at this point, the sdma transfers the long word to memory, and all 8 bytes will be in the receive buffer. also at this point the mflr violation (>5) is detected and the interrupt may be generated. no more data will be written into this buffer when the mflr violation is detected. 24 rstate 32 rx internal state. see section 34.3.4.1.4, ?rstate? rx internal state (hdlc),? for more information. 28 ? 32 rx internal data pointer?points to current address of specific channel. 2c rbptr 16 rx buffer descriptor pointer (host-initialize d to rbase prior to operation or due to a fatal error)?contains the offset from mcbase to the current receive buffer. see ta b l e 3 4 - 1 . mcbase + rbptr gives the address for the bd in use. 2e ? 16 rx internal byte count?per channel: number of remaining bytes in buffer 30 rpack 32 (rx temp) packs 4 bytes to 1 long word before writing to buffer. should be initialized to 0xffff_ffff. 34 zdstate 32 zero deletion machine state?(host-initialized to 0x80ff _ ffe0 in hdlc mode prior to operation and after a fatal rx error (global overrun, busy) before channel initialization.)?contains the previous state of zero deletion state machine. the middle 2 bytes, represented by zeros in th e initialization value above, hold the received pattern during reception. a window of 16 bits shows the history of what is received on this logical channel. more information is given in the application note section. 38 rcrc 32 temp receive crc?temp value of crc calculation result 3c max_cnt 16 max_length counter?count length remaining 3 e tmp_mb 16 temp?holds min(max_cnt, rx internal byte count) 0 1234 6789101112 15 field mode 0 idlm ent reserved pol crc 0 reserved nof reset 0000_0000_0000_0000 table 34-4. channel-specific hdlc parameters (continued) offset name width (bits) description 4 datasheet u .com
quicc multi-channel controller (qmc) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 34-17 table 34-5. chamr field descriptions (hdlc) bits name description 0 mode mode?each channel has a programmable option whether to use transparent mode or hdlc mode. 0 transparent mode 1 hdlc mode 1?0 2 idlm idle mode. 0 idle mode is disabled. no idle patterns are tr ansmitted between frames. after transmitting the nof + 1 flags, the transmitter starts the data of the frame. if between frames and the frame buffer is not ready, the transmitter sends flags until it can start transmitting the data. the nof shall be greater or equal to the pad setting; see section 34.6.2, ?transmit buffer descriptor.? if nof = 0, this is identical to flag sharing in hdlc mode. for a high cpm load or with long bus latencies, the qmc protocol may insert additional flags. 1 idle mode enabled. at least one idle pattern is transmitted between adjacent frames. if between frames and the frame buffer is not ready, the transmitter sends idle characters. when data is ready, the nof + 1 flags are sent followed by the data frame. if in idle mode and nof = 1, the following sequence is transmitted: ......init value, ff, ff, flag, flag, data,...... the init value before the idle will be 1?s, in this case it is assumed the transmitter was uninitialized. an uninitialized scc transmits 1s in every position. 3 ent enable transmit. 0 disable transmitter. if this bit is cleared and the channe l?s transmitter is routed to a certain time slot (within tsattx, see figure 34-3 ) the transmitter sends 1?s on this time slot. 1 the transmit portion of the channel is enabled and data is sent according to protocol and to other control settings. note that there is no enr bit in the qmc protocol. to enable the receiver, the zdstate and rstate parameters shall be set to their initial values. 4?6 ? reserved 7 pol enable polling. this bit enables the transmitter to poll the transmit buffer descriptors. 0 the cpm does not check the ready bit (r) in the transmit buffer descriptor. 1 the cpm checks the ready bit (r) in the transmit buffer descriptor. the user can use this bit to prevent unnecessary exte rnal bus cycles when checking the ready bit (r) in the buffer descriptor. this bit should alwa ys be set by the software at the beginning of a transmit sequence of one or more frames. this bit is cleared (0) by the risc processor when no more buffers are ready in the transmit queue when it finds a buffer descriptor with the r bit cleared (0), that is, at the end of a frame or at the end of a multi-frame transmissi on. in order to prevent deadlock the software should always prepare the new bd, or multiple bds, and set (1) the ready bit in the bd, before setting (1) the pol bit. note that as this bit is automatically cleared by the cpm; the user should not attempt to clear this bit in software. 8 crc this bit selects the type of crc when using the hdlc channel mode. 0 16-bit ccitt-crc is selected for this channel 1 32-bit ccitt-crc is selected 9?0 10?11 ? reserved 12?15 nof number of flags?defines the minimu m number of flags before frames. ho wever, even if nof = 0, at least one flag is transmitted before the first frame. see the description of the idlm bit for more information. 4 datasheet u .com
quicc multi-channel controller (qmc) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 34-18 freescale semiconductor 34.3.4.1.2 tstate?tx internal state (hdlc) tstate defines the internal transm itter state. the high byte of tstate defines the function code/address type. figure 34-8 shows the tstate register for hdlc operation. table 34-6 describes tstate fields. 34.3.4.1.3 intmsk?in terrupt mask (hdlc) each event defined in the interrupt circular queue en try maps directly to a bi t in intmsk as shown in figure 34-10 . there is one mask bit for each event?nid (bit 2), idl (bit 3) , mrf (bit 10), un (bit 11), rxf (bit 12), bsy (bit 13), txb (bit 14) and rxb (bit 15). bits that do not map to an event are reserved. reserved bits must be set to zero. refer to section 34.5, ?qmc exceptions,? for more detail. ? 0 = no interrupt request is generated and no new en try is written in the circular interrupt table. ? 1 = interrupts are enabled. this register is initialized by the host prior to operation. : 01234567 field ? gbl bo tc2 ? reset 0000_0000_0000_0000 r/w r/w figure 34-8. tstate?tx internal state (hdlc) table 34-6. tstate field descriptions (hdlc) bits name description 0?1 ? reserved, should be cleared. 2 gbl global 0 snooping disabled 1 snooping enabled 3?4 bo byte ordering. set bo to select the required byte ordering for the buffer. if bo is changed on-the-fly, it takes effect at the beginning of the next fr ame (ethernet, hdlc, and transparent) or at the beginning of the next bd. 00 reserved 01 munged little endian 1x big endian or true little endian 5 tc2 transfer code. contains the transfer code value of tc[2], used during this sdma channel memory access. tc[0:1] is driven with a 0b11 to identify this sdma channel access as a dma-type access. 6?7 ? reserved, should be cleared. 0 1 2 3 4 9 10 11 12 13 14 15 field v w nid idl channel number mrf un rxf bsy txb rxb reset 0000_0000_0000_0000 figure 34-9. interrupt table entry 4 datasheet u .com
quicc multi-channel controller (qmc) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 34-19 34.3.4.1.4 rstate?rx internal state (hdlc) the rstate is host-initialized before enabling the ch annel or after a fatal e rror (that is, global overrun, busy) or after a stop rx command. the high byte of rstate defines the function code/address type. figure 34-11 shows the rstate register for hdlc operation. table 34-7 describes rstate fields. 34.3.4.2 channel-specific transparent parameters table 34-8 describes the channel-specific transparent parameters. boldfaced parameters must be initialized by the user. 01 2 3 4 910 15 field reserved interrupt mask reserved interrupt mask bits reset 0000_0000_0000_0000 figure 34-10. intmsk (hdlc) 01234567 field ? gbl bo tc2 ? reset 0000_0000_0000_0000 r/w r/w figure 34-11. rstate?rx internal state (hdlc) table 34-7. rstate field descriptions (hdlc) bits name description 0?1 ? reserved, should be cleared. 2 gbl global 0 snooping disabled 1 snooping enabled 3?4 bo byte ordering. set bo to select the required byte order ing for the buffer. if bo is changed on-the-fly, it takes effect at the beginning of t he next frame (ethernet, hdlc, and transpar ent) or at the beginning of the next bd. 00 reserved 01 munged little endian 1x big endian or true little endian 5 tc2 transfer code. contains the transfer code value of tc[2], used during this sdma channel memory access. tc[0:1] is driven with a 0b11 to identify this sdma channel access as a dma-type access. 6?7 ? reserved, should be cleared. 4 datasheet u .com
quicc multi-channel controller (qmc) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 34-20 freescale semiconductor table 34-8. channel-specific transparent parameters offset name width description 00 tbase 16 tx buffer descriptor base a ddress?defines the offset of t he channel?s transmit bd table relative to mcbase, ho st-initialized. see figure 34-2 . 02 chamr 16 channel mode register. see section 34.3.4.2.1, ?cha mr?channel mode register (transparent mode).? 04 tstate 32 tx internal state ?tstate defines the internal tx state. initialize before enabling the channel. see section 34.3.4.2.2, ?tstate?tx internal state (transparent mode).? 08 32 tx internal data pointer?points to current absolute address of channel. 0c tbptr 16 tx buffer descriptor pointer (host-initialized to tbase before enabling the channel or after a fatal error before reinitializing the channel)?co ntains the offset of current bd relative to mcbase. see table 34-1. mcbase + tbptr gives the address for the bd in use. 0e 16 tx internal byte count?number of remaining bytes 10 tupack 32 (tx temp) unpack 4 bytes from 1 long word 14 zistate 32 zero-insertion machine state (host-initialized to 0x0000 _ 0200)?contains the previous state of the zero-insertion state machine. 18 res 32 ? 1c intmsk 16 channel?s interrupt mask flags. see figure 34-15 . 1e bdflags 16 temp 20 rbase 16 receive buffer descriptor base offset?defines the offset of the channel?s 64-kbyte receive bd table relative to mcbase. host-initialized. see also figure 34-2 . 22 tmrblr 16 transparent maximum receive buffer length (host-initialized entry)?defines the maximum number of bytes written to a receive buffer before moving to the next buffer for this channel. note that this value must be a multiple of 4 bytes as the qmc works on long-word alignment. 24 rstate 32 rx internal state. see section 34.3.4.2.5, ?rstate?rx in ternal state (transparent mode),? for more information. 28 32 rx internal data pointer?points to current address of specific channel. 2c rbptr 16 rx buffer descriptor pointer (host-initialized to rbase, prior to operation or due to a fatal error)?contains the offset from mcbase to the current receive buffer. see figure 34-2 . mcbase + rbptr gives the address for the bd in use. 2e 16 rx internal byte count?per channel: number of remaining bytes in buffer 30 rpack 32 (rx temp)?packs 4 bytes to 1 long word before writing to buffer. should be initialized to 0xffff_ffff. 34 zdstate 32 zero deletion machine state?(host-initialized to 0x02ff _ 33e0 in transparent mode prior to operation and after a fatal rx error (global overrun, busy) before channel initialization.)?contains the pr evious state of the zero-delet ion state machine. the middle 2 bytes, represented by zeros in the initializatio n value above, holds the received pattern during reception. a window of 16 bits shows the history of what is received on this logical channel. 38 res 32 ? 4 datasheet u .com
quicc multi-channel controller (qmc) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 34-21 34.3.4.2.1 chamr?channel mode register (transparent mode) the channel mode register is a wo rd-length, host-init ialized register. figure 34-12 shows the channel mode register for transparent mode. table 34-9 describes the channel mode register?s fields for transparent operation. boldfaced parameters must be initialized by the user. 3c trnsync 16 transparent synchronization?in transparent mode , this register controls synchronization for single time slots or superchannel applications. see section 34.3.4.2.4, ?trnsync?transparent synchroni zation (transparent mode).? 3e res 16 ? 0 1234 5 6789101112 15 field mode rd 1 ent ? sync ? pol 0 0 ? 0 reset 0000_0000_0000_0000 figure 34-12. chamr?channel mode register (transparent mode) table 34-9. chamr bit settings (transparent mode) bits name description 0 mode mode?each channel has a programmable option whether to use transparent mode or hdlc mode. 0 transparent mode 1 hdlc mode 1 rd reverse data 0 the bit order will not be reversed, transmitting/receiving the lsb of each octet first. 1 the bit order as seen on the channels is reversed, transmitting/receiving the msb of each octet first. 2?1 3 ent enable transmit 0 disable transmitter. if this bit is cleared and the channe l?s transmitter is routed to a certain time slot (within tsattx, see figure 34-3. ) the transmitter sends 1?s on this time slot. 1 the transmit portion of the channel is enabled and data is sent according to protocol and to other control settings. 4?reserved 5 sync synchronization?controls synchronization of multi-channel operation in transparent mode. 0 the first byte is put in the first available time slot or is read from the first available time slot to this logical channel. 1 the synchronization algorithm according to transync is done. 6resreserved table 34-8. channel-specific transparent parameters (continued) offset name width description 4 datasheet u .com
quicc multi-channel controller (qmc) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 34-22 freescale semiconductor 34.3.4.2.2 tstate?tx inter nal state (transparent mode) tstate defines the internal transm itter state. the high byte of tstate defines the function code/address type. figure 34-13 shows the tstate register for transparent mode. table 34-10 describes tstate fields. 7 pol enable polling?enables the transmitter to poll the transmit bds. 0 the cpm will not check the ready (r) bit in the transmit buffer descriptor. 1 the cpm will go check the ready (r) bit in the transmit buffer descriptor. the user can use this bit to prevent unnecessary exte rnal bus cycles when checking the ready bit (r) in the buffer descriptor. software should always set pol at th e beginning of a transmit sequence of one or more frames. the risc processor clears pol (0) when no mo re buffers are ready in the transmit queue when it finds a buffer descriptor with the r bit cleared (0), that is, at the end of a frame or at the end of a multi-frame transmission. to prevent deadlock, software should prepare the new bd, or multiple bds, and set (1) the ready (r) bit in the bd before setting (1) pol. note that the cpm automatically clear s this bit; the user should never try to clear this bit in software. 8?9 ? 0 10?11 ? reserved 12?15 ? 0 01234567 field ? gbl bo tc2 ? reset 0000_0000_0000_0000 r/w r/w figure 34-13. tstate?tx internal state (transparent mode) table 34-10. tstate field descriptions (transparent mode) bits name description 0?1 ? reserved, should be cleared. 2 gbl global 0 snooping disabled 1 snooping enabled 3?4 bo byte ordering. set bo to select the required byte order ing for the buffer. if bo is changed on-the-fly, it takes effect at the beginning of t he next frame (ethernet, hdlc, and transpar ent) or at the beginning of the next bd. 00 reserved 01 munged little endian 1x big endian or true little endian 5 tc2 transfer code. contains the transfer code value of tc[2], used during this sdma channel memory access. tc[0:1] is driven with a 0b11 to identify this sdma channel access as a dma-type access. 6?7 ? reserved, should be cleared. table 34-9. chamr bit settings (t ransparent mode) (continued) bits name description 4 datasheet u .com
quicc multi-channel controller (qmc) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 34-23 34.3.4.2.3 intmsk?interrupt mask (transparent mode) each event defined in the interrupt circular queue en try maps directly to a bi t in intmsk as shown in figure 34-15 . there is one mask bit for each event?un (b it 11), bsy (bit 13), txb (bit 14), and rxb (bit 15). bits that do not map to an event are reserved. reserved bits must be set to zero. ? 0 = no interrupt request is generated and no new en try is written in the circular interrupt table. ? 1 = interrupts are enabled. this register is initialized by the host before operation. 34.3.4.2.4 trnsync?transparent sync hronization (transparent mode) in transparent mode, the trnsync register contro ls the synchronization fo r single time slots or superchannel applications. note this register has no meaning if the sy nc bit in the channel mode register (chamr) is cleared (0). when sending a transparent message over several time slot s, it is necessary to know in which time slot the first byte of data appears. the trnsync word-length register is divided into two parts with the high byte controlling the first received time slot and the low byte cont rolling the transmitter synchronization. take the example of a supercha nnel of several time slots: ts n , ts n + 1, ts n + 2 ....... ts n + x the algorithm for the receiver byte in decimal is: (ts n + 1) 2 the algorithm for the transmit byte in decimal is: (ts n + x + 1) 2 the result from these calculations is a decimal value programmed into trnsync. 0 1 2 4 5 9 101112131415 field v w ? channel number ? un ? bsy txb rxb reset 0000_0000_0000_0000 figure 34-14. interrupt table entry 0 10 11 15 field reserved interrupt mask bits reset 0000_0000_0000_0000 figure 34-15. intmsk (transparent mode) 4 datasheet u .com
quicc multi-channel controller (qmc) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 34-24 freescale semiconductor note note that ts n is not necessarily the first time slot in the frame. for example, if a superchannel is produced from ts2, ts4, and ts6, the message may be arranged with ts4 holding th e first byte, then ts6, a nd the final byte held in ts2 of the following frame. the following nine cases in figure 34-16 , named c1 to c9, show differen t scenarios ranging from a single time slot per logical channel to a superchannel using several time slots. in this application, 24 time slots are routed to this scc from the si ram. after time slot 23, the frame starts with 0 again. the arrow in all the figures illustrates the starting position. c1 is for a single byte in ts7, so ts n = 7 rx byte: (7+1) 2 = 16 as x = 0, ts n + x = ts n = 7, so tx byte: (7 + 1) 2 = 16 c2 is a single byte in ts23, so ts n = 23. note that time slot after 23 is 0, so in the calculations below 23 + 1 = 0. rx byte: (23 + 1) 2 = 0 as x = 0, ts n + x = ts n = 23, so tx byte: (23 + 1) 2 = 0 c3 is a 2-byte pattern ts7, ts8, so ts n = 7 rx byte: (7 + 1) 2 = 16 as x = 1, ts n + x = 8, so tx byte: (8 + 1) 2 = 18 c4 is a 2-byte pattern ts8, ts7, so ts n = 8 rx byte: (8 + 1) 2 = 16 as x = 1, ts n + x = 7, so tx byte: (7 + 1) 2 = 16 c5 is a 2-byte pattern ts19, ts23, so ts n = 19 rx byte: (19 + 1) 2 = 40 as x = 1, ts n + x = 23, so tx byte: (23 + 1) 2 = 0 c6 is a 2-byte pattern ts23, ts19, so ts n = 23 rx byte: (23 + 1) 2 = 0 as x = 1, ts n + x = 19, so; tx byte: (19 + 1) 2 = 40 4 datasheet u .com
quicc multi-channel controller (qmc) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 34-25 c7 is a 4-byte pattern ts 20, ts23, ts8, ts9, and ts19, so ts n = 20 rx byte: (20 + 1) 2 = 42 as x = 5, ts n + x = 19, so tx byte: (19 + 1) 2 = 40 c8 is a 4-byte pattern ts8, ts9, ts19, ts20, and ts23, so ts n = 8 rx byte: (8 + 1) 2 = 18 as x = 5, ts n + x = 23, so tx byte: (23 + 1) 2 = 0 c9 is a 4-byte pattern ts19, ts20, ts23, ts8, and ts9, so ts n = 19 rx byte: (19 + 1) 2 = 40 as x = 5, ts n + x = 9, so tx byte: (9 + 1) 2 = 20 note case c1 and c2 can be used as described above. a more elegant solution for single time slot applications is to have the sync bit cleared (0) in the channel mode register. both sc enarios produce the same result. 4 datasheet u .com
quicc multi-channel controller (qmc) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 34-26 freescale semiconductor figure 34-16. examples of different t1 time-slot allocation 34.3.4.2.5 rstate?rx inter nal state (transparent mode) the rstate is host-initialized before enabling the ch annel or after a fatal e rror (that is, global overrun, busy) or after a stop rx command. the high byte of rstate defines the function code/address type. figure 34-17 shows the rstate register for hdlc operation. 01234567 field ? gbl bo tc2 ? reset 0000_0000_0000_0000 r/w r/w figure 34-17. rstate?rx internal state (transparent mode) single-channel in ts7 7 0 single-channel in ts23 23 0 dual-channel in ts7+8 7 8 0 dual-channel in ts7+8 7 8 0 dual-channel in ts19+23 19 23 0 dual-channel in ts19+23 19 23 0 multi-channel in ts8+9+19+20+23 20 19 89 23 0 20 19 89 23 0 20 19 89 23 0 multi-channel in ts8+9+19+20+23 multi-channel in ts8+9+19+20+23 c9 c8 c7 c6 c5 c4 c3 c2 c1 4 datasheet u .com
quicc multi-channel controller (qmc) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 34-27 table 34-11 describes rstate fields. 34.4 qmc commands the host issues commands to th e qmc by writing to the comma nd register (cpcr). refer to section 21.3.1, ?cp command register (cpcr).? 34.4.1 transmit commands stop transmit the stop transmit command disables the transmissi on of data on the selected channel and clears chamr[pol]. upon asserting this co mmand in the middle of a frame, the risc processor sends an abort indication (7f) followed by idles or flags, depending on the mode, on the selected channel. if this command is issued between frames, the risc processor continue s sending idles or flags (depending on chamr[idlm]) in this channel. the tx buffer descriptor pointer (tbptr) is not advanced to the next buffer; see table 34-4 and section 34.3.2.8, ?global multi-channel parameters.? set the chamr[pol] bit to 1 to start transm ission or to continue after a stop command. only after transmission starts for a deactivated cha nnel, which is identified by a cleared v bit in the time-slot assignment table or a cleared ent bit, is it necessary to initialize zistate and tstate before setting chamr[pol]. to deactivate a channel, clear both the v bit in the tsa table and chamr[ent]. table 34-11. rstate field descriptions (transparent mode) bits name description 0?1 ? reserved, should be cleared. 2 gbl global 0 snooping disabled 1 snooping enabled 3?4 bo byte ordering. set bo to select the required byte order ing for the buffer. if bo is changed on-the-fly, it takes effect at the beginning of t he next frame (ethernet, hdlc, and transpar ent) or at the beginning of the next bd. 00 reserved 01 munged little endian 1x big endian or true little endian 5 tc2 transfer code. contains the transfer code value of tc[2], used during this sdma channel memory access. tc[0:1] is driven with a 0b11 to identify this sdma channel access as a dma-type access. 6?7 ? reserved, should be cleared. 4 datasheet u .com
quicc multi-channel controller (qmc) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 34-28 freescale semiconductor 34.4.2 receive commands stop receive the stop receive command forces the receiver of the selected channel to stop receiving. after issuing this command, the microcode does not change any of the receive parameters in the dual-ported ram. the command immediately stops activity on the channel. it does not wait for a frame re ception to be finished. because the current buffer descriptor can remain open if a reception was in progress, it is possible to get errors on this buffer once you restart reception. when restarting, set zdstate first and rstate afterwards. initialize zdstate and rstate to their initial values to start reception or to co ntinue receiving after a stop command. note no commands exist to start transmission and reception. this function is realized through th e gsmr register. 34.5 qmc exceptions qmc interrupt handling involves two principle data structures?the s cc event register (scce) and the circular interrupt table. figure 34-18 illustrates the circ ular interrupt table. figure 34-18. circular interrupt table in external memory intbase (interrupt base) points to the starting location of the queue in external memory, and intptr (interrupt pointer) marks the curren t empty position available to the ri sc processor. both pointers are host-initialized global qmc parameters; see table 34-1 . the entry whose w (wrap) bit is set to 1 marks the end of the queue. when one of the qmc channels generates an inte rrupt request, the risc processor writes a new entry to the queue. in addition to the ch annel?s number, this entry contains a description of v = 1 interrupt flags v = 0 x v = 0 x v = 0 x v = 1 interrupt flags v = 1 interrupt flags v = 1 interrupt flags v = 0 x v = 0 x v = 0 x intbase software pointer intptr w = 0 w = 0 w = 0 w = 0 w = 0 w = 0 w = 0 w = 0 w = 0 w = 1 16 bits 4 datasheet u .com
quicc multi-channel controller (qmc) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 34-29 the exception. the v (valid) bit is then set and intp tr is incremented. when intptr reaches the entry with w = 1, intptr is reset to intbase. an interrupt is written to the interru pt table only if it surv ives a mask with the in tmask (interrupt mask) register. following a write to the queue, the qmc protocol updates the scc event register (scce) according to the type of exception. following a request that is not masked out by th e intmask or the sccm (scc mask) register, an interrupt is generated to the host. the host reads the scce to determine the cause of inte rrupt. a dedicated scce bit (gint) indicates that at least one new en try was added to the queue. after clearing gint, the host starts processing the queue. the host then clears this entry?s valid bit (v). the host follows this procedure until it reaches an entry wi th v = 0, indicating an invalid entry. note it is very important that the user clear all bits but the wrap bit in a queue entry even though its valid bit may be cleared. clearing only the interrupt bits confuse user software wi th incorrect channel interrupts. 34.5.1 global error events a global error affects the operation of the scc. a global error can occur for two reasons?serial data rates being too high for the cpm to handle, and cpm bus latency being too long fo r correct fifo operation. there are two global errors?globa l transmitting underrun (gun) a nd global receiver overrun (gov). gun indicates that transmission has failed due to lack of data; and gov indicates that the receiver has failed because the risc processor did not write previ ous data to the receive buffer. in both cases, it is unknown which channel(s) are affected. nonglobal, individual channel errors are handled differently. see section 34.5.3, ?inter rupt table entry,? for underrun and overrun in a specific channel. the incoming data to the cpm is governed by transfer s between the scc and the si. every transfer in either direction causes a request to the cpm state machine. if requests are received too quickly, the cpm may lose track of the mapping of seri al data to the qmc channels. if this happens, the cpm has to cause a global error to halt activity on al l qmc channels until user software intervenes. note that this problem typically indicates a performance-re lated design problem. also note th at latency is very important. the other error condition is bus latency. a receiving channel submits data to th e fifo for transfer to external memory as long as the ch annel operates normally. if the bus latency for the sdma channels is too long and the receive fifo is filled and overwritte n, a receiver overflow occurs. the overwriting channels cannot be traced, af fecting entire qmc operation. a similar situation can occur duri ng transmission when the sdma cannot fill the fifo from external memory because of bus latency. ag ain, it cannot be determined whic h channel is underrun, and the whole qmc operation is affected. global errors are unlikely to occur in normal system operation, if correct serial speed is used. the only area of concern is data movement between the fifo and external memo ry. to avoid problems, the user must understand the bus arbitration mechanism of the quicc and meet the latency requirements. 4 datasheet u .com
quicc multi-channel controller (qmc) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 34-30 freescale semiconductor 34.5.1.1 global underrun (gun) the qmc performs the following act ions when it detects a gun event: ? transmits an abort sequence of mini mum sixteen 1?s in each time slot ? generates an interrupt request to the host (if en abled) and sets the gun bit in the scce register ? stops reading data from buffer ? sends idles or flags in all time slots dependi ng on channel mode settings until the host does the following: host initializes all transmitting channels and ti me slots by preparing all buffer descriptors for transmission (r bits are set) and setting the pol bit. no ot her re-initialization is needed. 34.5.1.2 global overr un (gov) in the fifo a global overrun affects all channe ls operating from an scc. foll owing gov, the qmc performs the following: ? updates the rstate register to prevent further r eception on this channel. bit 20 in the rstate register indicates that the receiver is stopped. ? generates an interrupt request to the host (i f enabled) and sets the gov bit in the scce ? stops writing data to all channel?s buffers ? waits for host to initialize all the receiving channels by setting first the zdstate followed by the rstate to their initial values 34.5.1.3 restart from a global error the last two bullets in the above two sections descri be the only steps necessary for re-initialization. the transmit and receive sections must be restarte d individually for each separate logical channel. for details about initialization, see section 34.7, ?qmc initialization.? 34.5.2 scc event register (scce) the qmc?s scce is a word-length register used to report events and generate interrupt requests. see figure 34-19 and table 34-12 for scce field descriptions. fo r each of its flags, a corresponding programmable mask/enable bit in the sccm determines whether an interr upt request is generated. if a bit in the sccm register is zero, the corresponding inte rrupt flag does not survive, and the cpm does not proceed with its usual interrupt handling. if a bit in the sccm is set, the corresponding interrupt flag in the scce survives, and the scc event bit is set in the cpm interrupt-pending register. see figure 34-20 for sccm assignments. figure 34-19. scc event register 0 34567 field ? iqov gint gun gov 4 datasheet u .com
quicc multi-channel controller (qmc) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 34-31 figure 34-20. sccm register 34.5.3 interrupt table entry the interrupt table contains info rmation about channel-specific events. its flags are shown in figure 34-21 . note that some bits have no meaning when operating in transparent mode. for more detailed description on which bits are used in hdlc and transparent operation, refer to section 34.3.4, ?channel-specific parameters.? table 34-13 describes the fields of an interrupt table entry. table 34-12. scc event register field descriptions bits name description 0?3 ? reserved 4 iqov interrupt table (interrupt queue) overflow 0 no interrupt table overflow has occurred. 1 an overflow condition in the circular interrupt tabl e occurs (and an interrupt request is generated). this condition occurs if the risc processor attempts to wr ite a new interrupt entry into an entry that was not handled by the host. such an entry is identified by v = 1. this bit should be cleared immediately after reading the scce and recognizing this condition by writing a 1 to its location in the scce. if this co ndition occurs, the interrupt last received is lost. it does not overwrite the first entry that is still to be handled by the cpu. 5 gint global interrupt 0 no global interrupt has occurred. 1 this flag indicates that at least one new entry in the circular interrupt table has been generated by the qmc. the host clears gint by writing a 1 to its location in scce. after clearing it, the host reads the next entry from the circular interrupt table, an d starts processing a specific channel?s exception. the user must make sure that no more valid interrupt s are pending in the interrupt table after clearing the gint bit, before performing the rte to avoid deadlock. this procedure ensures that no pending interrupts exist in the queue. 6 gun global transmitter underrun 0 no global transmitter underrun has occurred. 1 this flag indicates that an underrun occurred in the scc? s transmitter fifo. this error is fatal since it is unknown which channel(s) are affected. following the assertion of the gun bit in the scce, the qmc stops transmitting data on all channels. the tdm tx line goes into idle mode. this error affects only the transmitter; the receiver continues to work. after initializing all the individual channels, the host ma y resume transmitting. if enabled in the sccm, an interrupt request is generated when gun is set. the host may clear gun by writing 1 to its location in the scce. 7 gov global receiver overrun 0 no global receiver overrun has occurred. 1 this flag indicates that an overrun occurred in the sc c?s receiver fifo. this error is fatal since it is unknown which channel(s) are affected. following the assertion of the gov bit in the scce, the qmc stops receiving data on all channels. data is no lo nger written to memory. this error affects only the receiver; the transmitter continues to work. after initializing all the individual channels, the host may resume receiving. if enabled in sccm, an interrupt request is generated when gov is set. the host may clear gov by writing 1 to its location in the scce. 0 34567 field ? iqov gint gun gov 4 datasheet u .com
quicc multi-channel controller (qmc) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 34-32 freescale semiconductor 0 1 2 3 4 9 10 11 12 13 14 15 field v w nid idl channel number mrf un rxf bsy txb rxb reset 0000_0000_0000_0000 figure 34-21. interrupt table entry table 34-13. interrupt table entry field descriptions bits name description 0 v valid bit 0 entry is not valid. 1 valid entry containing interrupt information. upon generating a new entry, the risc processor sets this bit. the v bit is cleared by the host immediately after it reads the interrupt flags in this entry (before processing the interrupt). the v bits in the queue are host-initialized. during the initialization procedure, the host must clear those bits in all queue entries. 1 w wrap bit 0 this is not the last entry in the circular interrupt table. 1 this is the last circular interrupt table entry. the next event?s entry is writte n/read (by risc/host) from the address contained in intbase. during initialization, the host must clear all w bits in the queue except the last one which must be set. the length of the queue is left to the us er and can be a maximum of 64 kbytes. 2 nid not idle 0 no nid event has occurred. 1 a pattern which is not an idle pattern was identified. nid interrupts are not generated in transparent mode. 3 idl idle 0 no idl event has occurred. 1 the channel?s receiver has identified the first occurrence of hdlc idle (fffe) after any non-idle pattern. idl interrupts are not generated in transparent mode. 4?9 channel number identifies the requesting logical channel index (0?31). 10 mrf maximum receive frame length violation?this inte rrupt occurs in hdlc mode when more than mflr number bytes are received. as soon as mflr is exce eded, this interrupt is generated and the remainder of the frame is discarded. at this point the receiv e buffer is not closed and the reception process continues. the receive buffer is closed upon detecting a flag. the length field written to this buffer descriptor is the entire number of bytes received between the two flags. mrf interrupts are not generated in transparent mode. note : the mrf interrupt is generated directly when th e mflr value is a multiple of 4 bytes. the checking of this is done on a long-word boundary whenever the sdma transfers 32 bits to memory. if mflr is not aligned to 4x bytes, this interrupt may be 1- to 3-byte timings late for this channel. in any case, the violation can be checked to any number of by tes. the last entry in the data buffer is always a full long word. 4 datasheet u .com
quicc multi-channel controller (qmc) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 34-33 34.5.4 interrupt handling to handle interrupts by the qmc, first read the scce register. writ e back immediately al l the bits that you recognize and handle. this clears the respective interrupt events. it is, fo r example, incorrect to first handle all the new interrupt table entries and clear gint afterwards. to avoid deadlocks in your software, you must clear the recognized interrupt b its in the scce before actually ha ndling the interrupt entries. clear only the bits that you handle. never clear bits for events in the sc ce that you do not handle. this facilitates debugging. upon receiving a new gint event, always handle all the new entries in the queue, not just a single one. after handling an entry, make sure that the entry is completely cleared out with the exception of the wrap bit. any entry that does not have the valid bit set must be completely cleared out, including the channel number. if all the entries are not clea red out on startup or after handling, th ese bits will confuse the software 11 un tx no data 0 no un event has occurred. 1 there is no valid data to send to the transmitter. the transmitter sends an abort indication consisting of 16 consecutive 1?s and then sends idles or flags according to the protocol and the channel mode register setting. this error occurs when a transmit channel has no data buffer ready for a multi-buffer transmission already in progress. transmission of a frame is a continuous bitstream without gaps or interruption. when a buffer is not ready in the middle of this sequence, it is an error situation. this can be viewed as channel underrun. the transmitter for this channel is stopped. see section 34.7.1, ?restarting the transmitter,? for recovery information. 12 rxf rx frame 0 no rxf event has occurred. 1 a complete hdlc frame is received. data is stored in external memory and the buffer descriptor is updated. if during frame reception an abort sequence of at least seven 1?s is detected, the buffer is closed and both rxb and rxf are reported along with the ab in the buffer descriptor. as a result of end-of-frame, the global frame coun ter grfcnt is decremented for interrupt generation. this counter is decremented on rxf only, regardless if the rxf was caused by correct closing or due to an error. rxf interrupts are not generated in transparent mode. 13 bsy busy 0 no bsy event has occurred. 1 a frame was received but was discarded due to lack of buffers. this can be viewed as channel overrun. after a busy condition, the receiver for this channel is disabled and no more data is transferred to memory. receiver restart is described in section 34.7.2, ?restarting the receiver.? 14 txb tx buffer 0 no txb event has occurred. 1 a buffer has been completely transmitted. this bit is set (and an interrupt request is generated) as soon as the programmed number of pad characters (or the closing flag, for pad = 0) is written to the scc?s transmit fifo. the number of pad characters determin es the timing of the txb interrupt in relation to the closing flag sent out at txd. see section 34.6, ?buf fer descriptors,? for an explanation of pad characters and their use. 15 rxb rx buffer 0 no rxb event has occurred. 1 a buffer has been received on this channel. table 34-13. interrupt table entry field descriptions (continued) bits name description 4 datasheet u .com
quicc multi-channel controller (qmc) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 34-34 freescale semiconductor when the entry is used again. qmc wi ll only or in new bits and numbers. it will not overwrite and clear bits that were set previously. 34.5.5 channel interrupt processing flow figure 34-22 illustrates the flow of a cha nnel interrupt. note that this doe s not describe the processing of the global interrupts gun and gov. figure 34-22. channel interrupt flow 34.6 buffer descriptors qmc buffer descriptors are located within 64 kbytes in external memory; see figure 34-2 . each buffer descriptor contains key informat ion about the buffer it defines. the first two sections describe th e contents of the receive and tran smit buffer descriptors for the qmc protocol. start make new entry including v=1; increment intptr intptr?> citentry.v=0 ? yes interrupt occurs rxf event ? no set sccex.gint end yes decrement grfcnt grfcnt=0 ? yes end no no set sccex.iqov no yes interrupt intmsk ? masked in end 4 datasheet u .com
quicc multi-channel controller (qmc) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 34-35 the third section discusses the placement of qmc and non-qmc buffer descriptors in internal and external memory. note the cpm ?ors? the various status bits into the bd. you must clear all the status bits generated by the cpm befo re (re-)enabling th e bd or you may confuse your own software with left over old status values. 34.6.1 receive buffer descriptor figure 34-23 shows a receive bu ffer descriptor. note: entries in boldface must be initialized by the user. figure 34-23. receive buffer descriptor (rxbd) table 34-14 describes the individual fields of a receive buffer descriptor. boldfaced entries must be initialized by the user. 0123456789101112131415 offset + 0 e ? w i l f cm ? ub ? lgnoabcr ? ? offset + 2 data length offset + 4 rx data buffer pointer offset + 6 table 34-14. rxbd field descriptions bits name description 0 e empty 0 the data buffer associated with this bd has been f illed with received data, or data reception has been aborted due to an error condition. the user is free to examine or write to any fields of this rxbd. the cp does not use this bd again while the empty bit remains zero. 1 the data buffer associated with this bd is empty, or reception is in progress. this rxbd and its associated receive buffer are in use by the cp. when e = 1, the user should not write any fields of this rxbd. 1 ? reserved, should be cleared. 2 w wrap (final bd in table) 0 this is not the last bd in the rxbd table. 1 this is the last bd in the rxbd table. after this bu ffer has been used, the cp receives incoming data into the first bd in the table (the bd po inted to by rbase). the number of rxbds in this table is programmable and is determined by the wrap bit. 3 i interrupt 0 the rxb bit is not set after this buffer has been used, but rxf operation remains unaffected. 1 the rxb or rxf bit in the hdlc interrupt circular table entry is set when this buffer has been used by the hdlc controller. these two bits may cause interrupts (if enabled). 4 datasheet u .com
quicc multi-channel controller (qmc) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 34-36 freescale semiconductor 4 l last in frame (only for hdlc mode of operation). the hdlc controller sets l = 1, when this buffer is the last in a frame. this implies the reception either of a closing flag or of an error, in which case one or more of the cd, ov, ab, and lg bits are set. the hdlc controller wr ites the number of frame octets to the data length field. 0 this buffer is not the last in a frame. 1 this buffer is the last in a frame. 5 f first in frame. the hdlc controller sets f = 1 for the fi rst buffer in a frame. in transparent mode, f indicates that there was a synchronization before receiving data in this bd. 0 this is not the first buffer in a frame. 1 this is the first buffer in a frame. 6 cm continuous mode 0 normal operation (the empty bit (bit 0) is cleared by the cp after this bd is closed.) 1 the empty bit (bit 0) is not cleared by the cp after th is bd is closed, allowing the associated data buffer to be overwritten automatically when the cp next accesses this bd. however, if an error occurs during reception, the empty bit is cleared regardless of the cm bit setting. 7 ? reserved, should be cleared. 8 ub user bit. ub is a user-defined bit that the cpm never se ts nor clears. the user determines how this bit is used. 9 ? reserved, should be cleared. 10 lg rx frame length violation (hdlc mode only). indica tes that a frame length grea ter than the maximum value was received in this channel. only the maximum-allowed number of bytes, mflr rounded to the nearest higher word alignment, are written to the data buffer. th is event is recognized as soon as the mflr value is exceeded when data is word-aligned. when data is not word-aligned, this interrupt occurs when the sdma writes 64 bits to memory. the worst-case latency from mflr violation until detected is 7 bytes timing for this channel. when mflr violation is detected, the receiver is still receiving even though the data is discarded. the buffer is closed upon detecting a flag, and this is co nsidered to be the closing flag for this buffer. at this point, lg is set (1) and an interrupt may be generated. the length field for this buffer is everything between the opening flag and this last identifying flag. 11 no rx nonoctet-aligned frame. a frame of bits not divisibl e exactly by eight was received. no = 1 for any type of nonalignment regardless of frame length. the shortest frame that can be detected is of type flag-bit-flag, which causes the buffer to be cl osed with no error indicated. the non octet byte is not written into memory and t he data length dl field is not updated with this count. 12 ab rx abort sequence. a minimum of seven consecutive 1s was received during frame reception. abort is not detected between frames. the sequence closing-flag, data, crc, ab, data, opening-flag... does not cause an abort error. if the abort is long e nough to be an idle, an idle line interrupt may be generated. an abort within the frame is not reported by a unique interrupt but rather with a rxf interrupt and the user has to examine the bd. 13 cr rx crc error. this frame contains a crc error. t he received crc bytes are always written to the receive buffer. 14 ? reserved, should be cleared. 15 ? reserved, should be cleared. table 34-14. rxbd field descriptions (continued) bits name description 4 datasheet u .com
quicc multi-channel controller (qmc) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 34-37 note: rxbd and mrblr when the length of a received frame is an exact mult iple of mrblr, it is possible that the cp will not mark the bd that contains the last of the frame?s data as the la st bd in the frame. the cp will close the bd, mark it with e = 0, se t the data length field to be the le ngth of the data in this buffer, but leave l (bit 4) cleare d. then, the cp will clos e the next bd, erroneously mark it as containing data (e = 0), and mark it as the last bd in the frame (l = 1). figure 34-24 shows how non-octet alignment is reported and how data is st ored. the two diagrams on the left show the reception of a single-buffer, 12-byte fr ame including the crc. in th e top case, the reception is correctly octet-aligned and th e frame length i ndicates 12 bytes. figure 34-24. nonoctet alignment data in the bottom case, two more bits are received. the fra me length is now 13 bytes, and the address positions x13 through x15 point to invalid data. address pos ition x12 contains inform ation about the non-octet alignment. valid information is writ ten starting at the msb position, show n as ?x? in the diagram. starting from the lsb position, zeros are filled in follow ed by a ?1? immediately preceding the valid data. the two diagrams on the right show how the data and the extra information is stored for a frame length that is not a multiple of 4 bytes. the additional informati on is always on a long-word boundary. in the top case the frame length is 10 bytes and in the bottom case the length is 11 bytes. for a minimum frame consisting of ?fla g, 1 bit, flag? the frame length is 1. the only vali d entry is at address xx0 with content of x1000000. to accommodate the extra long word that may be writ ten at the end of a frame and to avoid overwritten memory beyond the end of a buffer, it is recommended to reserve mr blr + 8 bytes for each buffer area. the xtra information shown in figure 34-24 is written as 32-bit word. u nder special, but quite possible circumstances the xtra data is writ ten four bytes further than indicat ed. therefore, users must allocate mrblr+8 bytes for each buffer area fo r qmc to avoid the risk of thes e memory areas being overwritten with xtra info. 9 ? 10 ? 5 7 68 1 3 24 9 11 10 12 5 7 68 1 3 24 x 1 0 0 x000 xtra ? ?? 9 ? 10 ? 5 7 68 1 3 24 address xx8 address x12 address xx4 address xx0 address xx8 address x12 address xx4 address xx0 x 1 0 0 x000 xtra ? ?? 9 11 10 12 5 7 68 1 3 24 address xx8 address x12 address xx4 address xx0 address xx8 address x12 address xx4 address xx0 4 datasheet u .com
quicc multi-channel controller (qmc) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 34-38 freescale semiconductor 34.6.2 transmit buffer descriptor figure 34-25 shows the transmit buffer descriptor. note : entries in boldface must be initialized by the user. figure 34-25. transmit buffer descriptor (txbd) table 34-15 describes the individual fields of a transmit buffer descript or. boldfaced entries must be initialized by the user. 0123456789101112131415 offset + 0 r ? w i l tc cm ? ub ? ? ? pad offset + 2 data length offset + 4 tx data buffer pointer offset + 6 table 34-15. transmit buffer descriptor (txbd) field descriptions bits name description 0 r ready 0 the data buffer associated with this buffer descriptor is not ready for transmission. the user can manipulate this buffer descriptor or its associated dat a buffer. the cpm clears this bit after the buffer has been transmitted or after an error condition is encountered. 1 the data buffer, which has been prepared for transmi ssion by the user, has not been transmitted or is being transmitted. if r = 1, the user cannot write to fields of this buffer descriptor. 1?? 2 w wrap (final buffer descriptor in table) 0 this is not the last buffer descriptor in the txbd table. 1 this is the last descriptor in the tx buffer descriptor table. after this buffer is used, the cpm transmits data from the first buffer descriptor in the table (t he buffer descriptor pointed to by tbase). the number of txbds in this table is programmable and is de termined only by the wrap bit and the overall space constraints of the dual-ported ram. 3 i interrupt 0 no interrupt is generated after this buffer has been serviced. 1 txb in the circular interrupt table entry is set when the controller services this buffer. this bit can cause an interrupt (if enabled). 4 l last 0 this is not the last buffer in the frame. 1 this is the last buffer in the current frame. 5 tc tx crc (hdlc mode only). this bit is valid only when l = 1; otherwise, it is ignored. 0 transmit the closing flag after the last data byte. th is setting can be used for testing purposes to send an erroneous crc after the data. 1 transmit the crc sequence after the last data byte. 6 cm continuous mode 0 normal operation 1 the r bit is not cleared by the cpm after this buffer descriptor is closed, allowing the associated data buffer to be retransmitted au tomatically when the cpm next accesses this buffer descriptor. 7?? 4 datasheet u .com
quicc multi-channel controller (qmc) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 34-39 figure 34-26 shows a txb interrupt generated after (pad + 1) flag characters foll owing the closing flag. four flags (nof = 3) precede the ne xt data. to set up this sequence correctly, the pad value must not exceed nof. figure 34-26. relation between pad and nof 34.6.3 placement of buffer descriptors the internal dual-ported ram is used to store th e buffer descriptors for all non-qmc operation. this solution causes minimum loading of the external bus. when starting any operation or switching between buffers during operations, several acc esses must be made by the cpm to find the actual data buffers and to read and write control and status information. this process is unseen by the user for internal accesses, and any external bus master or memory refresh control can occur uninterrupted. 8 ub user bit?the cpm never touches, sets, or clears this user-defined bit. the user determines how this bit is used. for example, it can be used to signal between higher-level protocols whether a buffer has been processed by the cpu. 9?11 ? ? 12?15 pad padding bits?these four bits indicate the number of pad characters (0x7e or 0xff depending on idlm mode in the chamr register) that the transmitter se nds after the closing flag. the transmitter issues a txb interrupt only after sending the programmed value of pads to the tx fifo. the user can use the pad value to guarantee that a txb interrupt occurs after the closing flag has been sent on the txd line. pad = 0 means the txb interrupt is issued immediately after sending the closing flag to the tx fifo. the number of pad characters depends on the fifo size and the number of time slots in use. an example explains the calculation: in scc1 the fifo is 32 bytes. if 16 time slots are used in the link, the resulting number of pad characters is 32/16 = 2, to append to this buffer to ensure that the txb interrupt is not given before the closing flag has been transmitted through the txd line. the number of pad characters must not exceed t he nof characters, ensuring that the closing of one buffer (the interrupt generation) occurs before t he start of the next frame (clearing of r-bit). after the sequence of a closing flag followed by (pad + 1) flag characters, a txb interrupt will be generated; see figure 34-26 . 16?31 dl data length?the data length is the nu mber of bytes the cpm should transmit from this buffer descriptor?s data buffer. it is never modified by the cpm. this field should be greater than zero. 32?63 txbp tx buffer pointer?the transmit buffer pointer, which contains the address of the associated data buffer, may be even or odd. the buffer may reside in either internal or external memory. this value is never modified by the cpm. table 34-15. transmit buffer descriptor (txbd) field descriptions (continued) bits name description data flg flg data crc flg flg txb interrupt clearing r-bit pad = 1, nof = 3 4 datasheet u .com
quicc multi-channel controller (qmc) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 34-40 freescale semiconductor 34.6.3.1 parameter ram usage for qmc over several sccs there are two possible memory conf igurations for operating the qmc pr otocol on several sccs. for each scc in qmc protocol, a global parame ter area is used, consuming at mo st 190 bytes if every global area contains the routing tables. the time-slot assign ment tables (tsatrx and tsattx) together occupy 128 bytes. the tables for each scc in the paramete r ram can be duplicated, re quiring 190 bytes per scc. alternatively, multiple sccs ca n use one set of common time-slo t assignment tables (tsatrx and tsattx), as described in section 34.3.2.1, ?tsatrx/tsattx pointers and time-slot assignment table.? one scc ram page uses 190 bytes, 62 bytes for parameter fields and 128 bytes for the common time-slot assignment tables, allowi ng the other sccs to use only 62 bytes of parameter ram for qmc protocol, freeing their 128 bytes of time-slot assignment table space. 34.6.3.2 internal memory structure for details about the MPC8555E internal memory, refer to chapter 2, ?memory map,? and section 21.4, ?internal ram.? to support 32 channels, only 2-kbyte dual-ported ram is needed for channel-sp ecific parameters. each logical channel occupies 64 bytes; thus 32 channels require 2 k bytes, leaving 2 kbytes free in the dual-ported ram for buffer desc riptors for other protocols. to support 64 channels, 4-kbyte dual-ported ram is required for ch annel-specific parameters. each logical channel occupies 64 bytes, requiring 4 kbytes for 64 channels. non-qmc protocol implementations may be constrained by these memory requirements since their buffer descriptors need to use internal memory space. if fewer than 64 logical cha nnels are used or if multiple time slots are concatenated to form super channels, using one qmc channel to manage t hose time slots, space is freed in the dual-ported ram. each unused logical channel creates a 64- byte hole in the dual-ported ram. this ar ea is free for buffer descriptors for any scc. qmc channels can also use this space inst ead of external memory for buffer descriptors, reducing the load on the external bus. 34.7 qmc initialization the following are the general initialization st eps necessary after a reset for qmc operation: 1. initialize qmc global parameters , including all parameter fields, tx and rx time-slot assignment tables and framer tables. 2. initialize channel-specific parameters. 3. initialize the txbds and the corresponding tx data buffers. 4. initialize rxbds. 5. connect the scc to the tdm interface th rough the scc clock muxing register cmxscr. 6. initialize scc registers, including enabling the scc. 7. program rx and tx siram to point appropria te time slots to the scc used for qmc. 4 datasheet u .com
quicc multi-channel controller (qmc) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 34-41 8. initialize the si registers. 9. enable the tdm. 34.7.1 restarting the transmitter a global underrun may require the scc transmitter to be rest arted. however, for ch annel-specific errors, only the affected channel need be restarted. the following steps are required to restart each channel: 1. prepare buffer descriptors. 2. set the pol bit in the channel mode register. a stopped, but not deactivated channel is started as described above. a d eactivated channel must first have the zistate and tstate reinitialized to their co rrect values, followed by setting tsattx[v] and chamr[ent]. lastly, set chamr[po l] if the buffers are ready. 34.7.2 restarting the receiver a global receiver overrun may require the scc receiver to be rest arted. however, for channel-specific errors, only the affected channel need be restarted. the following steps ar e required to rest art each channel: 1. prepare buffer descriptors. 2. reinitialize the zdstate. 3. reinitialize the rstate. 34.7.3 disabling receiver and transmitter a transmit channel can be stopped from sending any more data to the line with the stop command described in section 34.4.1, ?transmit commands.? the transmitter will continue to send idles or flags according to the channel mode re gister setting. to deactivate a chan nel, the v bit has to be cleared in the time-slot assignment table and the ent bit ha s to be cleared in the channel mode register. to stop a channel while receiving, use the stop command as described in section 34.4.2, ?receive commands,? and perform a restart as described above. 4 datasheet u .com
quicc multi-channel controller (qmc) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 34-42 freescale semiconductor 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 35-1 chapter 35 universal serial bus controller the universal serial bus (usb) controller allows the MPC8555E to communicate with other devices through a usb connection. this chapter describes the MPC8555E usb controller, including its basic operation, the parameter ram, and th e registers. it also provides pr ogramming examples for initializing the host mode and function mode in the usb controller. 35.1 usb integration in the MPC8555E the following restrictions apply when en abling the usb controller in the MPC8555E: ? the usb controller pins are multiplexed with scc3 pins in the parallel i/o. refer to chapter 45, ?parallel i/o ports.? the user programs the parall el i/o registers as if s cc3 was being used. if the usb controller is enabled, the signals are automa tically routed to the us b controller instead of scc3. ? the usb controller uses the transmit clock of scc3 as its clock. the user must program cmxscr[ts3cs] (refer to section 24.4.4, ?cmx scc clock route register (cmxscr)? ) to the desired source for usb when the usb controller is enabled. 35.2 overview the usb is an industry-standard ex tension to the pc architecture. the usb controller on the MPC8555E supports data exchange between a wide range of simultaneously accessible peripherals. attached peripherals share usb bandwidth through a host-scheduled, token-based protocol. the usb physical interconnect is a tiered-star topology and the center of each star is a hub. each wire segment is a point-to-point connection between the host and a hub or function, or a hub connected to another hub or a function. the usb transfers signal a nd power over a four-wire cable, and the signaling occurs over two wires and point-to-poi nt segments. the usb full speed si gnaling bit rate is 12 mbps. also, a limited capability low spee d signaling mode is defined at 1.5 mbps. refer to the usb specification revision 2.0, for further details. it can be downloaded from http://www.usb.org. the MPC8555E usb controller consists of a transmitte r module, receiver module, and two protocol state machines. the protocol state machin es control the receiver and transm itter modules. one state machine implements the function state di agram and the other implements the host state diagram. the usb controller can implement a usb f unction endpoint, a usb host, or bot h for testing purposes (loopback diagnostics). 4 datasheet u .com
universal serial bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 35-2 freescale semiconductor 35.2.1 usb controller key features the usb function mode features are as follows: ? four independent endpoints supp ort control, bulk, interrupt, a nd isochronous data transfers ? crc16 generation and checking ? crc5 checking ? nrzi encoding/decodi ng with bit stuffing ? 12- or 1.5-mbps data rate ? flexible data buffers with multiple buffers per frame ? automatic retransmission upon transmit error the usb host controller features are as follows: ? supports control, bulk, interrupt, and isochronous data transfers ? crc16 generation and checking ? nrzi encoding/decodi ng with bit stuffing ? supports both 12- and 1.5-mbps data rates (automatic generation of preamble token and data rate configuration). note that low-spee d operation requires an external hub. ? flexible data buffers with multiple buffers per frame ? supports local loopback mode fo r diagnostics (12 mbps only) 35.3 host controller limitations the following tasks are not suppor ted by the hardware and must be implemented in software: ? crc5 generation for tokens (because crc5 is calculated on 11 bits, this task should not impose much software overhead) ? retransmission after an error and error recovery ? generation and transmission of an so f (start of frame) token every 1 ms ? scheduling the various transf ers within and between frames because the MPC8555E usb host controller does not in tegrate the root hub, an external hub is required when more than one device is connected to the hos t. an external hub is also required for low-speed operation. also note that the host controller programming m odel is similar to the f unction endpoint programming model but does not conform to the open host controll er interface (ohci) or universal host controller interface (uhci) standards in which so ftware drivers are hardware-independent. 35.3.1 usb controller pin functions and clocking the usb controller interfaces to the usb bus through a differential line driver and differential line receiver. the oe (output enable) signal enables the line driv er when the usb controller transmits on the bus. 4 datasheet u .com
universal serial bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 35-3 figure 35-1. usb interface the reference clock for the usb controller (usbclk) is used by the dpll circuitry to recover the bit rate clock. the source for usbclk is selected in cmxscr[ts3cs] (refer to section 24.4.4, ?cmx scc clock route register (cmxscr)? ). the MPC8555E can run at diff erent frequencies, but the usb reference clock must be four times the usb bit rate. thus, usbclk must be 48 mhz for a 12-mbps full-speed transfer or 6 mhz fo r a 1.5-mbps low-speed transfer. there are six i/o pins associat ed with the usb port. their f unctionality is described in table 35-1 . additional control lines that might be needed by some transceivers (for example, speed select, low power control) may be supported by general purpose output lines. table 35-1. usb pins functions signal i/o function usbtxn, usbtxp o outputs from the usb transmitter, inputs to the differential driver. . usb oe o output enable. enables the transceiver to send data on the bus. usbtxp usbrxd d+ d? usboe usbtxn usbrxp usbrxn MPC8555E + ? usb transceiver tp tn result 0 0 single ended ?0? 0 1 logic ?0? 1 0 logic ?1? 11 ? 4 datasheet u .com
universal serial bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 35-4 freescale semiconductor 35.4 usb function description as shown in figure 35-2 , the usb function consists of transmitter and r eceiver sections a nd a control unit. the usb transmitter contains four independent fifos, each contai ning 16 bytes. there is a dedicated fifo for each of the four suppo rted endpoints. the usb receiv er has a single 16-byte fifo. figure 35-2. usb function block diagram usbrxd i receive data. input to the usb receiver from the differential line receiver. usbrxp, usbrxn i gated version of d+ and d?. used to det ect single-ended zeros and the interconnect speed. table 35-1. usb pins functions (continued) signal i/o function rp rn result 0 0 single-ended ?0? 1 0 full speed 0 1 low speed 11 ? mode register peripheral bus u-bus command register port control transmitter receiver usb function dpll/ bus interface rx fifo tx data fifo tx data fifo tx data fifo tx data fifo mode register mode register end-point registers address register port configuration external transceiver state machine 16-byte 16-byte 4 datasheet u .com
universal serial bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 35-5 35.4.1 usb function cont roller transmit/receive after reset condition, the usb func tion is addressable at the default address (0x00). during the enumeration process the usb function is assigned by the host with a unique address. the usb slave address register (refer to section 35.5.7.2, ?usb slave a ddress register (usadr)? ) should be programmed with the assigned addr ess. the usb function controll er supports four independent end-points. each endpoint can be configured to support either cont rol, interrupt, bulk, or isochronous transfers modes. this is do ne by programming the end-poi nt registers. (refer to section 35.5.7.3, ?usb endpoint registers (usep1?usep4).? ) note it is mandatory that endpoint 0 be configured as a c ontrol transfer type. this endpoint is used by the usb system so ftware as a contro l pipe. additional control pipes may be provided by other endpoints. once enabled, the usb function controll er looks for valid token packets. figure 35-3 and table 35-2 describe the behavior of the usb c ontroller for each token. tokens that are not valid (that is, pid check fails or crc check fails or pack et length is not 3 bytes) are ignor ed by the usb f unction controller. figure 35-3. usb controller operating modes reset unenumerated idle setup transmit receive start of frame setup to k e n in to ke n out to k e n sof to ke n enumeration process 4 datasheet u .com
universal serial bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 35-6 freescale semiconductor table 35-2. usb tokens token description out reception begins when an out token is received. the usb controller fetches the next bd associated with the endpoint; if the bd is empty, the controller starts sending the incoming packet to the buffer. after the buffer is full, the usb controller clears rxbd[e] and g enerates an interrupt if rxbd[i] = 1. if the incoming packet is larger than the buffer, the usb controller fetches the next bd, and, if it is empty, sends the rest of the packet to its buffer. the entire packet, including the data0/data1 pid, are writt en to the receive buffers. software must check data packet synchronization by monitoring the data0/data1 pid sequence toggle. if the packet reception has no crc or bit stuff errors, the usb receiver sends the handshake selected in the endpoint configuration register usep n [rhs] (see table below) to the host. if an error occurs, no handshake packet is returned and error status bits are se t in the last rxbd associated with this packet. usb out token reception usep n [rhs] data packet corrupted handshake sent to host xx yes none (data discarded) 00 (normal) no ack 01 (ignore) no none 10 (nak) no nak 11 (stall) no stall in to guarantee a transfer, the control software must preloa d the endpoint fifo with a data packet before receiving an in token. software should set up the endpoint txbd ta ble and set uscom[str]. the usb controller fills the transmit fifo and waits for the in token. once the tok en is received and the fifo has been loaded with the last data byte or with at least 4 bytes, transmission begins. th e 4-byte minimum is a threshold to prevent underruns in the fifo. if data is not ready in t he transmit fifo or if usep n [ths] is set to respond with nak, a nak handshake is returned. if usep n [ths] was set to respond with stall, a stall handshake is returned. (see table below.) when the end of the last buffer is reached (txbd[l] is set), the crc is appended. after the frame is sent, the usb controller waits for a handshake packet. if the host fails to acknowledge the packet, the timeout status bit txbd[to] is set. software must set the prope r data0/data1 pid in the transmitted packet. usb in token reception usep n [ths] fifo loaded hand shake sent to host 00 (normal) no nak yes data packet is sent 01 (ignore) ? none 10 (nak) ? nak 11 (stall) ? stall 4 datasheet u .com
universal serial bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 35-7 35.5 usb host description when programmed as a host, the us b controller supports a limited host functionality. the following sections describe the availabl e host functionality, its limitat ions, and the programming model. figure 35-4 illustrates the functionality of the usb contro ller in host mode. the us b controller consists of transmitter and recei ver sections, host control unit, and a functi on control unit, which is used for testing purposes. the usb transmitter cont ains 4 independent fifos, each containing 16 bytes. endpoint 1 is dedicated for host transact ions; endpoints 2?4 are for function transa ctions in test mode. there is a dedicated fifo for each of the 4 supported endpoints; endpoint 1 fifo is for host transactions. the usb receiver has a single 16-byte fifo. setup the format of setup transactions is similar to out bu t uses a setup rather than an out pid. a setup token is recognized only by a control endpoint. when a setup token is received, setup reception begins. the usb controller fetches the next bd associ ated with the endpoint; if it is empty, the controller starts transferring the incoming packet to the buffer. when the buffer is full, the usb controller clears rxbd[e] and generates an interrupt if rxbd[i] = 1. if the incoming packet is larger than the buffer, the usb controller fetches the next bd and, if it is empty, continues transferring the rest of the packet to this buffer. the entire data packet including the data0 pid is written to the receive buffers. if the pa cket was received without crc or bit stuff errors, an ack handshake is sent to the host. if an error occurs, no handshak e packet is returned and error status bits are set in the last rxbd associated with this packet. start of frame (sof) when an sof packet is received, the usb controller issues a sof maskable interrupt and the frame number entry in the parameter ram is updated. preamble (pre) the pre token signals the hub that a low-speed transaction is about to occur. the pre token is read only by the hub. the usb controller ignores the pre token function in function mode. table 35-2. usb tokens (continued) token description 4 datasheet u .com
universal serial bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 35-8 freescale semiconductor figure 35-4. usb controller block diagram 35.5.1 usb host controller transmit/receive the usb host controller init iates all usb transactions in the sy stem. after the reset condition, the host bit in usb mode register should be set (refer to section 35.5.7.1, ?usb mode register (usmod),? ) to enable host operation. setting us mod[test] enables the loopback operation, where three of the endpoints are function endpoints. the usb controller supports four independent e ndpoints. each endpoint can be configured to support either control, interrupt, bulk, or isochronous transfers modes. this is done by programming the endpoint registers. (refer to section 35.5.7.3, ?usb endpoint registers (usep1?usep4).? ) endpoint 1 must be used for host tran sactions (think exac tly how it should be programmed and its limitations) after reset the host should enumerat e the functions in the system. th e enumeration process is done by software. once enabled, the usb host controller waits for a packet in its fifo. when the fifo is filled with packet the host transaction starts. figure 35-3 and table 35-2 describe the behavior of the usb host controller for each token. tokens are not checked for validity and tr ansmitted as is. the user is responsible for token validity as well as crc5 ge neration. low speed transactions start wi th a preamble which is generated by the usb host controller state machine when lsp bit in token txbd is set. the signaling on the usb lines is controlled by usmod[lss]. mode register peripheral bus u-bus command register port control transmitter receiver dpll/ bus interface rx fifo tx data fifo tx data fifo tx data fifo mode register mode register end-point registers address register port configuration external transceiver 16-byte 16-byte usb host state machine usb function state machine tx data fifo ep0 4 datasheet u .com
universal serial bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 35-9 figure 35-5. usb controller operating modes 35.5.1.1 packet-level interface if usep1[rte] is 0, the usb host c ontroller uses a packet-level interf ace to communicate with the user. each transmit packet is prepared in a buffe r and referenced by a txbd as described in section 35.6.3, ?usb transmit buffer desc riptor (txbd) for host.? each receive packet is st ored in a buffer referenced by a rxbd as described in section 35.6.1, ?usb receive buffer de scriptor (rxbd) for host and function.? a setup or out transaction requires at least two txbds, one for the token and one or more for the data packet. an in transaction requires one txbd for the token and one or more rxbds for the data packet. tokens are not checked fo r validity and are transmitted as is . the user is responsible for token validity as well as crc5 generation. 35.5.1.2 transaction-level interface if usep1[rte] is 1, the usb host controller uses a transaction-level interface to communicate with the user. each transaction uses one trdb as described in section 35.6.4, ?usb transaction buffer descriptor (trbd) for host.? the usb host controller generates the toke n based on the tok field in the trbd. for setup and out transactions, the tr bd points to a single buffer cont aining the data packet to be transmitted. for in transactions, th e trbd points to a single buffer wh ich is used for the receive data packet. reset idle setup transmit receive setup to ke n out to ke n in to ke n preamble low speed full speed 4 datasheet u .com
universal serial bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 35-10 freescale semiconductor table 35-3. usb tokens token description out packet-level interface tra nsaction-level interface transmission begins when the usb host controller fetches a txbd containing an out token and a data txbd and loads them to the host fifo. the token and data are transmitted and a handshake is expected. if a handshake is not received within the expected time interval, the usb controller clears txbd[r] of data bd, sets the txbd[to] indication and generates a txe1 interrupt. when stall or nak is received within the expected time interval, the usb controller clears txbd[r] of data bd, sets the txbd[stall] or txbd[nak] indication and generates a txe1 interrupt. when ack is received within the expected time interval, the usb controller clears txbd[r] of data bd, and generates an interrupt if txbd[i] = 1. no indication is set. the token txbd[r] is cleared right after the out token transmission. transmission begins when the usb host controller fetches a trbd with the tok field indicating an out transaction. the token is generated and then the data packet from the buffer is transmitted and a handshake is expected. if a handshake is not receiv ed within the expected time interval, the usb controller clears trbd[r], sets the trbd[to] indication and generates a txe1 interrupt. when stall or nak is received within the expected time interval, the usb controller clears trbd[r], sets the trbd[stall] or trbd[nak] indication and generates a txe1 interrupt. when ack is received within the expected time interval, the usb controller clears trbd[r], and generates a txb interrupt if trbd[i] = 1.no indication is set. usb out transaction token data handshake received by host indication on txbd/trbd out sent by host none to ack none nak nak stall stall 4 datasheet u .com
universal serial bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 35-11 in packet-level interface tra nsaction-level interface transmission begins when the usb host controller fetches a txbd containing an in token and loads the token to fifo. after the in token is transmitted the usb host controller waits for reception of data within expected time inte rval. on reception of a valid data pid an rxbd is fetched. the received data and data pid are stored in receive fifo. if rxbd[e] is set pid and data will be moved to the buffer. while receiving the data the usb host controller calculates crc16, performs bit un-stuffing. on end of reception calculated crc is compared to received and octet alignment is checked, rxbd[e] is cleared, rxbd[pid] is set according to received data pid and error indications are set if required:rxbd[cr] for failed crc check, rxbd[no] for non-octet sized data and rxbd[ab] if bit stuffing error occurred. if no valid data pid or no data at all received during the expected time interval a to indication in the token txbd is set. transmission begins when the usb host controller fetches a trbd with the tok field indicating an in transaction. after the in token is generated and transmitted, the usb host controller waits for reception of data within the expected time interval. the received data packet is stored in buffer reference by the trbd. while receiving the data the usb host controller calculates crc16 and performs bit un-stuffing. at end of the packet, the calculat ed crc is compared to the received value and octet alignment is checked, trbd[r] is cleared, trbd[pid] is set according to the received data pid and error indications are set if required: trbd[cr] for failed crc check, trbd[no] for non-octet sized data and trbd[ab] if bit stuffing error occurred. if any of the above errors are reported, trbd[rxer] is also set, and a txe1 interrupt is generated. if no valid data pid or no data at all received during the expected time interval, a trbd[to] is set and a txe1 interrupt is generated. if no errors occurred and trbd[i] is set, a txb interrupt is generated to indicate succe ssful completion of the transaction. usb in transaction token data transmitted by function handshake generated by host indication on bd in received correctly ack rxbd[e]/trbd[r] is cleared received corrupted none rxbd[cr]/trbd[cr} or rxbd[ab]/trbd[ab] or rxbd[no]/trbd[no] none none txbd[to]/trbd[to] setup the format of setup transactions is similar to out but uses a setup rather than an out pid. a setup token is recognized only by a control endpoint. when a setup token is received, setup reception begins. the usb controller fetches the next bd associated with the endpoint; if it is empty, the controller starts transferring the incoming packet to the buffer. when the buffer is full, the usb controller clears rxbd[e] and generates an interrupt if rxbd[i] = 1. if the inco ming packet is larger than the buffer, the usb controller fetches the next bd and, if it is empty, continues transfer ring the rest of the packet to this buffer. the entire data packet including the data0 pid is written to the receive buffers. if the packe t was received without crc or bit stuff errors, an ack handshake is sent to the host. if an error occurs, no handshake packet is returned and error status bits are set in the last rxbd associated with this packet. start of frame (sof) when an sof packet is received, the usb controller issues a sof maskable interrupt and the frame number entry in the parameter ram is updated. preamble (pre) the pre token signals the hub that a low-speed transaction is about to occur. the pre token is read only by the hub. the usb controller ignores the pre token function in function mode. table 35-3. usb tokens (continued) token description 4 datasheet u .com
universal serial bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 35-12 freescale semiconductor 35.5.2 sof transmission for usb host controller the following section describes th e mechanism used by the usb host controller to support the automatic transmission of sof tokens . this mechanism is enab led by setting usmod[sfte]. sof packets should be transm itted every 1 ms. since the time interv al between two sof packets must be more precise than could be accomplished by software, a hardware timer is used to assert an interrupt to the cp. when the interrupt is serviced by the cp, it pr epares a sof token and load s it to the host endpoint. once the sof token is loaded to the fifo, it is transmitted like any other packet. before each sof transmission, the software should pr epare a value for the frame number and crc5 to be transmitted in sof token and place it in the parameter ram (for further details refer to section 35.5.5, ?frame number (frame_n).? one possible implementation would be to use the sof interrupt (see section 35.5.7.5, ?usb even t register (usber)? ) to prepare the frame numbe r for the next sof packet. the sft interrupt should not be used fo r this purpose since it is generate d before the sof packet is actually transmitted. the application software should also guarantee that the usb host has complete d all pending transactions prior to the 1 ms tick, so that the transmit fifo is em pty at this point. the current value of the sof timer may be read at any time to synchronize the software with the usb frames. see section 35.5.7.8, ?usb start of frame timer (ussft),? for more information. 35.5.3 usb function and host parameter ram memory map the usb controller parame ter ram area, shown in table 35-4 , begins at the usb base address, 0x8b00 (offset from ram_base). note that the user must initialize certain parameter ram values before the usb controller is enabled. table 35-4. usb parame ter ram memory map address name 1 width description usb base + 00 ep0ptr half word endpoint pointer registers 0?3. the endpoint parameter block pointers are index pointers to each endpoint?s parameter block. parameter blocks can be allocated to any address divisible by 32 in the dual port ram. see figure 35-6 . the map of the endpoint parameter block is shown in ta b l e 3 5 - 5 . note : when usb host mode is set ep0ptr must be used for the host endpoint. usb base + 02 ep1ptr half word usb base + 04 ep2ptr half word usb base + 06 ep4ptr half word usb base + 08 rstate word receive internal state. reserved for cp use only. should be cleared before enabling the usb controller. usb base + 0c rptr word receive internal data pointer. updated by the sdma channels to show the next address in the buffer to be accessed. usb base + 10 frame_n half word frame number. see figure 35-7 . note : the definition of this parameter is different for host mode and function mode. usb base + 12 rbcnt half word receive internal byte co unt. a down-count value t hat is initialized with the mrblr value and decremented with every byte written by the sdma channels. usb base + 14 rtemp word receive temp. reserved for cp use only. 4 datasheet u .com
universal serial bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 35-13 once initialized, the parameter ram values do not normally need to be accessed by user software. they should only be modified when no usb activity is in progress. 35.5.4 endpoint parameters block pointer (ep n ptr) the endpoint paramete r block pointers (ep n ptr) are dpram in indices to an endpoint?s parameter block. the parameter block can be allocate d to any address that is divisibl e by 32. the format of the endpoint pointer registers (ep n ptr) is shown in figure 35-6 . the map of the endpoint para meter block is shown in table 35-5 . usb base + 18 rxusb_ data word rx data temp usb base + 1c rxuptr half word rx microcode return address temp 1 the items in boldface should be initialized by the user before the usb cont roller is enabled; other val ues are initialized by the cp. 0 10 11 15 field endpoint index pointer ? r/w r/w reset 0000_0000_0000_0000 offset usb base + 0x00 (ep0ptr), 0x02 (ep1ptr), 0x04 (ep2ptr), 0x06 (ep3ptr) figure 35-6. endpoint pointer registers (ep n ptr) table 35-5. endpoint parameter block offset 1 name 2 width description 0x00 rbase 16 bits rxbd/txbd base addresses. define the starting location in dual-port ram for the usb controller?s txbds and rxbds. this provides flexibility in how bds are partitioned. setting w in the last bd in each list determines how many bds to allocate for the controller?s send and receive sides. these entries must be initialized before the controller is enabled. overlapping usb bd tables with another serial controller?s bds causes erratic operation. rbase and tbase values should be divisible by 8. 0x02 tbase 16 bits 0x04 rfcr 8 bits rx/tx function code. controls the value to appear on at[1:3] when the associated sdma channel accesses memory and the byte-ordering convention. 0x05 tfcr 8 bits table 35-4. usb parameter ram memory map (continued) address name 1 width description 4 datasheet u .com
universal serial bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 35-14 freescale semiconductor 35.5.5 frame number (frame_n) this entry is used for frame numbe r updates both in function mode and in host mode. in function mode it is updated by the usb controller; in host mode it is updated by the application software. 0x06 mrblr 16 bits maximum receive buffer length. defines the maximum number of bytes the MPC8555E writes to the usb receive buffer before moving to the next buffer. mrblr must be divisible by 4. the MPC8555E can write fewer data bytes to the buffer than the mrblr value if a condition such as an error or end-of-packet occurs, but it never exceeds mrblr. therefore, user-supplied buffers should never be smaller than mrblr. mrblr is not designed to be changed dynamically for the currently active rxbd during usb operation; however, mrblr can be modified sa fely for the next and subsequent rxbds using a single bus cycle with one 16-bit move (not two 8-bit bus cycles back-to-back). transmit buffers for the usb controller are not affected by the mrblr value. transmit buffer lengths can vary individually, as needed. the number of bytes to be sent is chosen by programming txbd[data length]. 0x08 rbptr 16 bits rxbd pointer. points to the next bd the receiver will transfer data to when it is in an idle state or to the current bd while processing a frame. software should initialize rbptr after reset. when the end of the bd table is reached, the cp initializes this pointer to the value programmed in rbase. although the user does not need to write rbptr in most applications (except initialization), it can be changed when the receiver is disabled or when no receive buffer is being used. 0x0a tbptr 16 bits txbd pointer. points to the next bd that t he transmitter will transfer data from when it is in an idle state or to the current bd during frame transmission. tbptr should be initialized by the software after reset. when the end of bd table is reached, the cp initializes this pointer to the value programmed in the tbasen entry. alth ough the user never needs to write tbptr, in most applications (except in itialization), it can be changed wh en the transmitter is disabled or when no transmit buffer is being used. 0x0c tstate 3 32 bits transmit internal state. reserved for cp use only. should be cleared before enabling the usb controller. 0x10 tptr 3 32 bits transmit internal data pointer. updated by the sdma channels to show the next address in the buffer to be accessed. 0x14 tcrc 3 16 bits transmit temp crc. reserved for cp use only. 0x16 tbcnt 3 16 bits transmit internal byte count. a down-count value that is initialized with the txbd data length and decremented with every byte read by the sdma channels. 0x18 ttemp 32 bits tx temp 0x1c txusbu_ ptr 16 bits tx microcode return address temp 0x1e himmr 16 bits when using the transaction-based interface in host mode, this field must be programmed to {ccsrbar[0:11], 0x9}. otherwis e, this field is unused. 1 offset from endpoint parameter block base. 2 note that the items in boldface should be initialized by the user. 3 these parameters need not be accessed in normal operation but may be helpful for debugging. table 35-5. endpoint parameter block (continued) offset 1 name 2 width description 4 datasheet u .com
universal serial bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 35-15 this entry is updated by the usb controller in functi on mode whenever a sof (start of frame) token is received. the entry contains 11 bits that represent th e frame number. an sof inte rrupt is issued upon an update of this entry. table 35-6 describes frame_n fields. this entry is updated by the appli cation software whenever a sof (start of fr ame) token should be received. the software should prepare the frame number and the crc and place it in frame_n field. table 35-6 describes frame_n fields. note the frame number field is also updated by the usb controller when the usb controller is configured as the host, thus indicating that sof was transmitted. therefore, the frame number field should always be regenerated and rewritten to the entry before sof is issued. 01 45 15 field v 1 1 this bit is set if the sof token was received error free. ? frame number reset 0000_0000_0000_0000 r/w r/w offset usb base + 0x10 figure 35-7. frame number (frame_n) in function mode?updated by usb controller table 35-6. frame_n field descriptions bits name description 0 v the valid bit is set if the sof token is received without error. 1?4 ? reserved, should be cleared. 5?15 frame number the frame number is loaded with the value received in the sof packet. be sure the frame number is cleared before beginning usb operation. 01 45 15 field crc5 frame number reset 0000_0000_0000_0000 r/w r/w offset usb base + 0x10 figure 35-8. frame number (frame_n) in fun ction mode?updated by application software table 35-7. frame_n field descriptions bits name description 0?4 crc5 crc5 calculated on frame number 5?11 frame number the frame number is inserted by the application software. 4 datasheet u .com
universal serial bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 35-16 freescale semiconductor 35.5.6 usb function code registers (rfcr and tfcr) rfcr and tfcr control the value that the user would like to appear on the address type pins (at1?at3) when the associated sdma channel accesses memory. table 35-8 describes rfcr and tfcr fields. 35.5.7 usb function programming model the following sections descri be usb controller registers. 01234567 field ? gbl bo tc2 dtb ? figure 35-9. usb function code registers (rfcr and tfcr) table 35-8. rfcr and tfcr fields bits name description 0?1 ? reserved, should be cleared. 2 gbl global 0 snooping disabled 1 snooping enabled 3?4 bo byte ordering. this bit field should be set by the user to select the required byte ordering for the data buffer. if this bit field is modified on-the-fly, it will take effect at the beginning of the next frame. 00 dec (and intel) convention is used for byte ordering?swapped operation. it is also called little-endian byte ordering. the transmission order of bytes within a buffer word is reversed as compared to the big-endian mode. this mode is supported only for 32-bit port size memory. 01 powerpc little-endian byte ordering. as data is tr ansmitted onto the serial line from the data buffer, the least significant byte of the buffer double-word contains data to be transmitted earlier than the most significant byte of the same buffer double word. 1x big-endian byte ordering?normal operation. as data is transmitted onto the serial line from the data buffer, the most significant byte of the buffer word contains data to be transmitted earlier than the least significant byte of the same buffer word. 5 tc2 transfer code. contains the transfer code value of tc[2] used during this sdma channel memory access. tc[0:1] is driven with a 0b11 to identify this sdma channel access as a dma-type access 6 dtb data bus indicator 0 use system bus for sdma operation 1 use local bus for sdma operation 7 ? reserved, should be cleared. 4 datasheet u .com
universal serial bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 35-17 35.5.7.1 usb mode register (usmod) usmod controls the usb controller operation mode. table 35-9 describes usmod fields. 0 1 234567 field lss resume ? sfte test host en reset 0000_0000 r/w r/w offset 0x9_1b60 figure 35-10. usb mode register (usmod) table 35-9. usmod fields bits name description 0 lss low-speed signaling. selects the signaling speed. t he actual bit rate depends on the usb clock source. 0 full-speed (12-mbps) signaling. normal operation. 1 low-speed (1.5-mbps) signaling. for a point-to-point connection with a low-speed device or for local loopback testing. 1 resume generate resume condition. when set, this bit generates a resume condition on the usb. this bit should be used if the function wants to exit the suspend state. 2?3 ? reserved, should be cleared. 4 sfte start-of-frame timer enable. setting this bit ena bles the start-of-frame timer and automatic sof transmission. see section 35.5.7.8, ?usb star t of frame timer (ussft),? and section 35.5.2, ?sof transmission for usb host controller,? for more information. 0 sof timer is disabled 1 sof timer is enabled note: when sfte is 1, the pc21 pin canno t be used as cp_int since the cp interrupt is used internally for generating the sof packet. 5 test usb controller test(loopback) mode 0 test mode is disabled 1 test mode is enabled note: this bit may be set only when host is set (usb host mode) 6 host usb host mode 0 usb host disabled 1 usb host is enabled 7 en enable usb. when the en bit is cleared, the usb is in a reset state 0 usb is disabled 1 usb is enabled note: setting this bit automatically disables scc3. note: other bits of the usmod should not be modified by the user while en is set. 4 datasheet u .com
universal serial bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 35-18 freescale semiconductor 35.5.7.2 usb slave address register (usadr) the usb address register is an 8-bi t, memory-mapped register. it holds the address for this usb port when operating as function. table 35-10 describes usadr fields. 35.5.7.3 usb endpoint re gisters (usep1?usep4) there are four memory-mapped e ndpoint configuration registers. table 35-11 describes the fields of usep 1?usep4. the setting for usb host controller should be set only in usep1, when usmod[host] is set. 01 7 field ? sadx reset 0000_0000 r/w r/w offset 0x9_0x9_1b61 figure 35-11. usb slave address register (usadr) table 35-10. usadr fields bits name description 0 ? reserved, should be cleared. 1?7 sadx slave address 0?6. holds the slave address for the usb port, when configured as function. 0 3 4 5 6 7 8 9 10 11 12 13 14 15 field epn ? tm ? mf rte ths rhs reset 0000_0000_0000_0000 r/w r/w offset 0x9_1b64 (usep1); 0x9_1b66 (usep2); 0x9_1b68 (usep3); 0x9_1b6a (usep4) figure 35-12. usb endpoint registers (usep1?usep4) table 35-11. usep n field descriptions bits name usb function mode usb host mode 0?3 epn endpoint number. for usb function controller defines the supported endpoint number. for usb host controller, should be cleared. 4?5 ? reserved, should be cleared. reserved, should be cleared. 6?7 tm transfer mode for usb function controller 00 control 01 interrupt 10 bulk 11 isochronous transfer mode for usb host controller 00 control /interrupt/bulk 11 isochronous 8?9 ? reserved, should be cleared. reserved, should be cleared 4 datasheet u .com
universal serial bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 35-19 35.5.7.4 usb command register (uscom) uscom is used to start usb transmit operation. 10 mf enable multi-frame. for usb function controller allows loading of the next transmit packet into the fifo before transmission completion of the previous packet. 0 transmit fifo may hold only one packet 1 transmit fifo may hold more than one packet note: for usb function configuration: should be cleared unless the endpoint is configured for iso transfer mode. enable multi-frame for usb host controller. should be always set. 11 rte retransmit enable for usb function controller 0 no retransmission 1 automatic frame retransmission is enabled. the frame will be retransmitted if transmit error occurred (time-out). note: may be set only if the transmit packet is contained in a single buffer. if it is not, retransmission should be handled by software intervention. note: should be set to zero for endpoint which is configured for iso transfer mode for usb host controller, should be cleared. 12?13 ths transmit handshake for usb function controller 00 normal handshake 01 ignore in token 10 force nack handshake. not allowed for control endpoint. 11 force stall handshake. not allowed for control endpoint. transmit handshake for usb host controller 00 normal handshake 14?15 rhs receive handshake for usb function controller 00 normal handshake 01 ignore out token 10 force nack handshake. not allowed for control endpoint. 11 force stall handshake. not allowed for control endpoint. receive handshake for usb host controller 00 normal handshake 01234567 field str flush isft dsft ? ep reset 0000_0000 r/w r/w offset 0x9_1b62 figure 35-13. usb command register (uscom) table 35-11. usep n field descriptions (continued) bits name usb function mode usb host mode 4 datasheet u .com
universal serial bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 35-20 freescale semiconductor table 35-12 describes uscom fields. 35.5.7.5 usb event register (usber) the usber reports events recognized by the usb channel and generate s interrupts. upon recognition of an event, the usb sets its corresponding bit in the us ber. interrupts generated by this register may be masked in the usb mask register. the usber may be read at any time . a bit is cleared by writing a one (writing a zero does not affect a bit?s value). more than one bit may be cleared at a time. all unmasked bi ts must be cleare d before the cp will clear the internal interrupt request . this register is cleared at reset. table 35-13 describes usber fields. table 35-12. uscom fields bits name description 0 str start fifo fill. setting the str bit to one causes the usb controller to start the filling the corresponding endpoint transmit fifo with data. transmission will begin once the in token for this end-point is received. the str bit is read always as a zero. 1 flush flush fifo. setting the flush bit to one causes the usb controller to flush the corresponding endpoint transmit fifo. before flushing the fifo, the user sh ould issue the stop_tx command. after flushing the fifo the user should issue the restart_tx command. (refer to section 35.7, ?usb cp commands.? ) flush is always read as a zero. 2 isft increment start-of-frame time. se tting the isft bit increments the star t-of-frame time by one. this bit could be used to synchronize the usb frames to an external timing source. 3 dsft decrement start-of-frame time. setting the dsft bi t decrements the start-of-frame time by one. this bit could be used to synchronize the usb frames to an external timing source. 4?5 ? reserved, should be cleared. 6?7 ep endpoint. selects one of the four supported endpoints. 0456789101112131415 field ? sft reset idle txe4 txe3 txe2 txe1 sof bsy txb rxb reset 0000_0000_0000_0000 r/w r/w offset 0x9_1b70 figure 35-14. usb event register (usber) table 35-13. usber fields bits name description 0?4 ? reserved, should be cleared. 5 sft the start-of-frame timer (ussf t[sft]) wrapped from 11,999 to 0. 6 reset reset condition detected. usb re set condition was detected asserted. 7 idle idle status changed. a change in t he status of the serial line was detec ted. the real time suspend status is reflected in the usb status register. 4 datasheet u .com
universal serial bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 35-21 35.5.7.6 usb mask register (usbmr) the usbmr is a 16-bit read/write register (0x9_1b74) that has the sa me bit formats as the usb event register. if a bit in the usbmr is one, the corresponding interrupt in the usber is enabled. if the bit is zero, the corresponding interrupt in the usber will be masked. this register is cleared at reset. 35.5.7.7 usb status register (usbs) the usb status register, described in figure 35-15 and table 35-14 , is a read-only regist er that allows the user to monitor real-time st atus condition on the usb lines. table 35-14 describes usbs fields. 35.5.7.8 usb start of frame timer (ussft) when enabled by usmod[sfte], the u ssft contains the current time wi thin the frame with a resolution of one bit time. when the value of ussft wraps from 11,999 to 0, a cp inte rrupt is asserted to trigger the transmission of a sof pack et, and usber[sft] is set. 8?11 txex tx error. an error occurred during transmission for endpoint x (packet not acknowledged or underrun). 12 sof start-of-frame. a start of frame packet was rece ived. the packet is stored in the frame_n parameter ram entry. 13 bsy busy condition. received data has been discarded due to a lack of buffers. this bit is set after the first character is received for which there is no receive buffer available. 14 txb tx buffer. a buffer has been transmitted. this bit is set once the transmit data of the last character in the buffer was written to the transmit fifo (if l = 0 (last bit)) or after the last character was transmitted on the line (if l = 1). 15 rxb rx buffer. a buffer has been received. this bit is se t after the last character has been written to the receive buffer and the rxbd is closed. 0 67 field ? idle reset 0000_0000 r/w r offset 0x9_1b77 figure 35-15. usb status register (usbs) table 35-14. usbs fields bits name description 0?6 ? reserved 7 idle idle status. idle is set when an idle condition is de tected on the usb lines, it is cleared when the bus is not idle. table 35-13. usber fields (continued) bits name description 4 datasheet u .com
universal serial bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 35-22 freescale semiconductor the ussft may be read at any time. table 35-15 describes ussft fields. 35.6 usb buffer descriptor ring the data associated with the usb ch annel is stored in buffers that ar e referenced by bds organized in bd rings located in the du al-port ram (refer to figure 35-17 ). these rings have the same basic configuration as those used by the sccs and smcs. there are four separate transmit bd rings and four separate receive bd rings, one for each endpoint. the bd ring allows the user to define buffers for transmission and buffers for reception. each bd ring forms a circular queue. the cp confirms reception and transmission or indicat es error conditions using the bds to inform the processor that th e buffers have been serviced. the buffers may reside in either external or internal memory. 012 15 field ? sft reset 0010_1110_1101_1000 r/w r addr 0x9_1b78 figure 35-16. usb start of frame timer (ussft) table 35-15. ussft fields bits name description 0?1 ? reserved, should be cleared. 2?15 sft start-of-frame time. this field contains the number of bit times since the last sof trigger. note that the actual sof transmission occurs slightly later. 4 datasheet u .com
universal serial bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 35-23 figure 35-17. usb memory structure frame status data length data pointer usb endpoint 1 dual- port ram external memory tx buffer descriptors tx data buffer rx data buffer ep1 rx bd table pointer ep1 tx bd table pointer frame status data length data pointer tx buffer descriptors tx data buffer endpoint 4 tx bd table endpoint 1 tx bd table endpoint 1 rx bd table endpoint 4 rx bd table ep4 rx bd table pointer ep4 tx bd table pointer frame status data length data pointer rx buffer descriptors frame status data length data pointer rx buffer descriptors rx data buffer 4 datasheet u .com
universal serial bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 35-24 freescale semiconductor 35.6.1 usb receive buffer descripto r (rxbd) for host and function the cp reports information about eac h buffer of received data using rx bds. the cp closes the current buffer, generates a maskable interrupt , and starts receiving da ta in the next buffer when the current buffer is full. additionally, it closes the buffer on the following conditions: ? end of packet detected ? overrun error occurred ? bit stuff violation detected as shown in figure 35-18 , the first word of the rxbd contains status and control bits. these bits are prepared by the user before reception and are set by the cp after the buffer ha s been closed. the second word contains the data length?in bytes?that was r eceived. the third and fourth words contain a pointer that always points to the beginni ng of the received data buffer. the rxbd is identical for both the host mode (when using the packet-level in terface) and the function mode. there are no rxbds in host mode when using the transaction-level interface. table 35-16 describes usb receive buf fer descriptor fields. 0123456789101112131415 offset + 0 e ? w i l f ?pid?noabcrov? offset + 2 data length offset + 4 rx data buffer pointer offset + 6 figure 35-18. usb receive buffer descriptor (rxbd) 1,2 1 entries in boldface must be initialized by the user. 2 all fields should be written by the cpu core before enabling the usb table 35-16. usb rxbd fields offset bits name description 0x00 0 e empty 0 the data buffer associated with this rxbd has been filled with received data, or data reception has been aborted due to an error condition. the cpu core is free to examine or write to any fields of this rxbd. the cp will not use this bd again while the e-bit remains zero. 1 the data buffer associated with this bd is empty, or reception is currently in progress. this rxbd and its associated receive buffer ar e owned by the cp. once the e-bit is set, the cpu core should not write any fields of this rxbd. 1 ? reserved, should be cleared. 2 w wrap (final bd in table) 0 this is not the last bd in the rxbd table. 1 this is the last bd in the rxbd table. after this buffer has been used, the cp will receive incoming data into the first bd in the table (the bd poin ted to by rbase). the number of rxbds in this table is programmable and is determined only by the w-bit and the overall space constraints of the dual-port ram. 4 datasheet u .com
universal serial bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 35-25 data length represents the number of octets that the cp has written into this bd?s buffer. it is written once by the cp as the bd is closed. 3 i interrupt 0 no interrupt is generated after this buffer has been filled. 1 the rxb bit in the usb event register will be set when this buffer has been completely filled by the cp, indicating the need for the cpu core to process the buffer. the rxb bit can cause an interrupt if it is enabled. 4 l last. this bit is set by the usb controller when the buffer is closed due to detection of end-of-packet condition on the bus, or as a result of error. written by the usb controller after the received data has been pl aced into the associated data buffer. 0 buffer does not contain the last byte of the message. 1 buffer contains the last byte of the message. 5 f first. this bit is set by the usb controller when the buffer contains the first byte of a packet. written by the usb controller after the received data has been placed into the associated data buffer. 0 buffer does not contain the first byte of the message. 1 buffer contains the first byte of the message. 6?7 ? reserved, should be cleared. 8?9 pid packet id. this bit field is set by the usb c ontroller to indicate the type of the packet. this bit is valid only if the usb r xbd[f] is set. written by the us b controller after the received data has been placed into the associated data buffer. 00 buffer contains data0 packet 01 buffer contains data1 packet 10 buffer contains setup packet. this option can never be set on host rxbd. 10 ? reserved, should be cleared. 11 no rx non-octet aligned packet. a packet that cont ained a number of bits not exactly divisible by eight was received. written by the usb controller after the received data has been placed into the associated data buffer. 12 ab frame aborted. bit stuff error occurred during reception. written by the usb controller after the received data has been placed into the associated data buffer. 13 cr crc error. this frame contains a crc error. the received crc bytes are always written to the receive buffer. written by the usb controller after the received data has been placed into the associated data buffer. 14 ov overrun. a receiver overrun occurred during re ception. written by the usb controller after the received data has been placed into the associated data buffer. 15 ? reserved, should be cleared. 0x02 0?15 data length data length is the number of octets that the cp has written into this bd?s data buffer. it is written once by the cp as the bd is closed. note: the actual amount of memory allocated fo r this buffer should be greater than or equal to the contents of the mrblr. 0x04 0?31 rx data buffer pointer the receive buffer pointer, which always points to the first location of the associated data buffer, must be divisible by 4. the buffer may reside in either internal or external memory table 35-16. usb rxbd fields (continued) offset bits name description 4 datasheet u .com
universal serial bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 35-26 freescale semiconductor the receive buffer pointer always point s to the first location of the associ ated buffer. the pointer must be divisible by four. the buffer may reside in either internal or external memory. 35.6.2 usb transmit buffer descriptor (txbd) for function data that the usb function wishes to transmit to th e host is arranged in buffers referenced by the txbd ring. the first word of the txbd cont ains the status and control bits. table 35-17 describes usb txbd fields. 0123456789101112131415 offset + 0 r ? w i l tc cnf pid ?toun? offset + 2 data length offset + 4 tx data buffer pointer offset + 6 figure 35-19. usb transmit buffer descriptor (txbd) 1,2 1 entries in boldface must be initialized by the user. 2 all fields should be prepared by the user before transmission. table 35-17. usb function txbd fields offset bits name description 0x00 0 r ready 0 the data buffer associated with this bd is not ready for transmission. the user is free to manipulate this bd or its associated data buffer. the cp clears this bit after the buffer has been transmitted or after an error condition is encountered. 1 the data buffer, which has been prepared for transmission by the user, has not been transmitted or is currently being transmitted. no fields of this bd may be written by the user once this bit is set. 1 ? reserved, should be cleared. 2 w wrap (final bd in table) 0 this is not the last bd in the txbd table. 1 this is the last bd in the txbd table. after this buffer has been used, the cp will send data using the first bd in the table (the bd pointed to by tbasex). the number of txbds in this table is programmable, and is determined only by the txbd[w] and the overall space constraints of the dual-port ram. 3 i interrupt 0 no interrupt is generated after this buffer has been serviced. 1 the txb or txe bit in the event register is set when this buffer is serviced. txb and txe can cause interrupts if they are enabled. 4 l last 0 buffer does not contain the last byte of the message 1 buffer contains the last byte of the message 5 tc transmit crc. valid only when the l bit is se t; otherwise it is ignored. prepare tc before sending data. 0 transmit end-of-packet after the last data byte. this setting can be used for testing purposes to send a bad crc after the data. 1 transmit the crc sequence after the last data byte. 4 datasheet u .com
universal serial bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 35-27 data length (the second half word of a txbd) is the number of octets the cp s hould send from this bd?s data buffer. it is never modified by the cp. tx buffer pointer (the third and fourth half words of a txbd) always points to the first location of the buffer in internal or external memory. the pointer may be even or odd. 35.6.3 usb transmit buffer descriptor (t xbd) for host the txbd described in this section is used wh en the packet-level in terface is active. see section 35.5.1.1, ?packet-level interface,? for more information. 6 cnf transmit confirmation. valid only when the l bi t is set; otherwise it is ignored. applies to multi-frame enabled endpoints (usep n [mf] = 1); refer to section 35.5.7.3, ?usb endpoint registers (usep1?usep4).? 0 continue to load the transmit fifo with the next packet. several packets may be loaded to the fifo. 1 last packet that is loaded to fifo. no more packets will be loaded to fifo after a packet marked cnf, till it transmitted. 7 reserved, should be cleared 8?9 pid packet id. this bit field is valid for the first bd of a packet; otherwise it is ignored. 0x do not append pid to the data. 10 transmit data0 pid before sending the data. 11 transmit data1 pid before sending the data. 10?12 ? reserved, should be cleared. 13 to time out. indicates that the host failed to acknowledge the packet. 14 un underrun. indicates that the usb encount ered a transmitter underrun condition while sending the buffer. 15 ? reserved, should be cleared. 0x02 0?15 data length the data length is the number of octets that the cp should tr ansmit from this bd?s data buffer. it is never modified by the cp. this value should normally be greater than zero. 0x04 0?31 tx data buffer pointer the transmit buffer pointer, which always points to the first location of the associated data buffer, may be even or odd.the buffer may reside in either internal or external memory. table 35-17. usb function txbd fields (continued) offset bits name description 4 datasheet u .com
universal serial bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 35-28 freescale semiconductor data to be transmitted with the usb to the cp is arranged in buffers referenced by the txbd ring. the first word of the txbd contai ns status and control bits. table 35-17 describes usb txbd fields. 0123456789101112131415 offset + 0 r ? wi ltccnflsp pid ? nak stal to un ? offset + 2 data length offset + 4 tx data buffer pointer offset + 6 figure 35-20. usb transmit buffer descriptor (txbd) 1,2 1 entries in boldface must be initialized by the user. 2 all fields should be prepared by the user before transmission. table 35-18. usb host txbd fields offset bits name description 0x00 0 r ready 0 the data buffer associated with this bd is not ready for transmission. the user is free to manipulate this bd or its associated data buffer. the cp clears this bit after the buffer has been transmitted or after an error condition is encountered. 1 the data buffer, which has been prepared for transmission by the user, has not been transmitted or is currently being transmitted. no fields of this bd may be written by the user once this bit is set. 1 ? reserved, should be cleared. 2 w wrap (final bd in table) 0 this is not the last bd in the txbd table. 1 this is the last bd in the txbd table. after this buffer has been used, the cp will send data using the first bd in the table (the bd pointed to by tbasex). the number of txbds in this table is programmable, and is determined only by the txbd[w] and the overall space constraints of the dual-port ram. 3 i interrupt 0 no interrupt is generated after this buffer has been serviced. 1 the txb or txe bit in the event register is set when this buffer is serviced. txb and txe can cause interrupts if they are enabled. 4 l last 0 buffer does not contain the last byte of the message 1 buffer contains the last byte of the message 5 tc transmit crc. valid only when the l bit is se t; otherwise it is ignored. prepare tc before sending data. 0 transmit end-of-packet after the last data byte. this setting can be used for testing purposes to send a bad crc after the data. 1 transmit the crc sequence after the last data byte. 4 datasheet u .com
universal serial bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 35-29 data length (the second half word of a txbd) is th e number of octets the cp should send from this bd data buffer. it is never modified by the cp. tx buffer pointer (the third and fourth half words of a txbd) always points to the first location of the buffer in internal or external memory. the pointer may be even or odd. 35.6.4 usb transaction buffer descriptor (trbd) for host the trbd described in this section is used when the transaction-level interface is active. see section 35.5.1.2, ?transaction-level interface,? for more information. 6 cnf transmit confirmation. valid only when the l bi t is set; otherwise it is ignored. applies to multi-frame enabled endpoints (usep n [mf] = 1); see section 35.5.7.3, ?usb endpoint registers (usep1?usep4).? 0 continue to load the transmit fifo with the next packet. no handshake or response is expected from the function for this packet. 1 wait for handshake or response from the function before starting the next packet, or this is the last packet. do not clear cnf for a token preceding a data packet unless the data packet?s bd is ready. 7 lsp low-speed transaction. use for tokens only. 0 the following transaction is with the host or a full-speed device. 1 the following transaction is with a low-speed device. required only for tokens. note that lsp should always be cleared in slave mode. 8?9 pid packet id. this bit field is valid for the first bd of a packet; otherwise it is ignored. 0x do not append pid to the data. 10 transmit data0 pid before sending the data. 11 transmit data1 pid before sending the data. 10 ? reserved, should be cleared. 11 nak 1 nak received. indicates that the endpoint has responded with a nak handshake. the packet was received error-free; however, the endpoint could not accept it. 12 stal 1 stall received. indicates that the endpoint has responded with a stall handshake. the endpoint needs attention th rough the control pipe. 13 to 1 time out. indicates that the endpoi nt failed to acknowledge the packet. 14 un 1 underrun. indicates that the usb encounter ed a transmitter underrun condition while sending the buffer. 15 ? reserved, should be cleared. 0x02 0?15 data length the data length is the number of octets that the cp should tr ansmit from this bd?s data buffer. it is never modified by the cp. this value should normally be greater than zero. 0x04 0?31 tx data buffer pointer the transmit buffer pointer, which always points to the first location of the associated data buffer, may be even or odd.the buffer may reside in either internal or external memory. 1 written by the usb controller after it finishes sending the associated data buffer. table 35-18. usb host txbd fields (continued) offset bits name description 4 datasheet u .com
universal serial bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 35-30 freescale semiconductor data to be transmitted with the usb to the cp by is arranged in buffers referenced by the trbd ring. the first word of the trbd contai ns status and control bits. table 35-19 describes usb trbd fields. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 offset + 0x0 r ? wi ltccnflsppid rxer nak stal to un bov offset + 0x2 data length offset + 0x4 data buffer pointer offset + 0x6 offset + 0x8 tok ? iso ? endp addr offset + 0xa reserved figure 35-21. usb transaction buffer descriptor (trbd) 1,2 1 entries in boldface must be initialized by the user. 2 all fields should be prepared by the user before transmission. table 35-19. usb host trbd fields offset bits name description 0x00 0 r ready 0 the data buffer associated with this bd is not ready for transmission. the user is free to manipulate this bd or its associated data buffer. the cp clears this bit after the buffer has been transmitted or after an error condition is encountered. 1 the data buffer, which has been prepared for transmission by the user, has not been transmitted or is currently being transmitted. no fields of this bd may be written by the user once this bit is set. 1 ? reserved, should be cleared. 2 w wrap (final bd in table) 0 this is not the last bd in the trbd table. 1 this is the last bd in the trbd table. after this buffer has been used, the cp will send data using the first bd in the table (the bd pointed to by tbase). the number of trbds in this table is programmable, and is determined only by the trbd[w] and the overall space constraints of the dual-port ram. 3 i interrupt 0 no interrupt is generated after this buffer has been serviced. 1 the txb bit in the event register is set when this buffer is serviced. txb can cause an interrupt if it is enabled. 4 l last this bit should always be 1 since each trbd represents an entire transaction. 5 tc transmit crc. append crc to transmitted data packet. 0 transmit end-of-packet after the last data byte. this setting can be used for testing purposes to send a bad crc after the data. 1 transmit the crc sequence after the last data byte. 6 cnf transmit confirmation. this bit should always be set to 1 to obtain confirmation for each transaction. 4 datasheet u .com
universal serial bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 35-31 7 lsp low-speed transaction. 0 this transaction is with the host or a full-speed device. 1 this transaction is with a low-speed device. transmit a pre packet before the token. 8?9 pid packet id. for out/setup transactions, this field is prepared by the user with the following values: 0x do not append pid to the data packet. 10 transmit data0 pid before sending the data packet. 11 transmit data1 pid before sending the data packet. for in transactions, this field is provided by the usb host controller with the following values: 00 buffer contains data0 packet. 01 buffer contains data1 packet. 10 rxer 1 receive error. this bit indicates that an error was detected while receiving the data packet of an in transaction. if rxer is 1, bits 11- 15 have a different meaning as explained below. 11 nak/no 1 rxer = 0: nak received. indicates that the endpoint has responded with a nak handshake (out transaction). the packet was received error-free; however, the endpoint could not accept it. rxer = 1: rx non-octet aligned packet. a pack et that contained a number of bits not exactly divisible by eight was received. written by the usb controller after the received data has been placed into the associated data buffer. 12 stal/ab 1 rxer = 0: stall received. indicates th at the endpoint has responded with a stall handshake (out transaction). the endpoint needs attention through the control pipe. rxer = 1: frame aborted. bit stuff error occu rred during reception. written by the usb controller after the received data has been placed into the associated data buffer. 13 to/cr 1 rxer = 0: time out. indicate s that the endpoint failed to acknowledge the token (in transaction) or the data packet (out/setup transaction). rxer = 1: crc error. this frame contains a crc error. the received crc bytes are always written to the receive buffer. written by the usb controller after the received data has been placed into the associated data buffer. 14 un/ov 1 rxer = 0: underrun. indicates that the usb encountered a transmit fifo underrun condition while sending the data packet (out/setup transaction). rxer = 1: overrun. an internal receive fifo overrun occurred during reception. written by the usb controller after the received data has been placed into the associated data buffer. 15 bov 1 buffer overflow. in transactions only. indicates that the number of received bytes is larger than the buffer size as provided in the data length field. 0x02 0?15 data length for out/setup transactions, the user prepares th is field with the numb er of bytes to be sent from the data buffer. it will not be modified by the cp. for in transactions, the user prepares this field with the size of the data buffer, which must be divisible by 4. the cp will return the actual number of bytes written to the data buffer. if the number of received bytes, including the 2- byte crc, is larger than the data buffer, the bov bit will be set by the cp. 0x04 0?31 data buffer pointer the data buffer pointer. the buffer may reside in either internal or external memory. for out/setup transactions, this points to the buffer containing the data packet to transmit. it may have any alignment. for in transac tions, this points to the buffer into which the data packet should be received, the pointer must be divisible by 4. table 35-19. usb host trbd fields (continued) offset bits name description 4 datasheet u .com
universal serial bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 35-32 freescale semiconductor 35.7 usb cp commands the following transmit commands are issued to the cp command register (cpcr). refer to section 21.3.1, ?cp command register (cpcr) .? 35.7.1 stop tx command this command disables the transmi ssion of data on the se lected endpoint. after i ssuing the command the corresponding endpoint fifo should be flushed. no furt her transmissions will take place until the restart tx command is issued. 35.7.2 restart tx command this command enables the transmission of data from the corresponding endpoint on the usb. this command is expected by the usb controller after a stop tx command, or after transmission error (underrun or time-out). 0x08 0?1 tok token type this field determines the type of token to be transmitted and the type of transaction. 00 setup 01 out 10 in 11 reserved 2 ? reserved, should be cleared. 3 iso isochronous this bit indicates that the transaction is isochronous, so no handshake is required. 0 bulk/control/interrupt. the hands hake packet is automatically expected or generated by the usb host controller. 1 isochronous. no handshake packets are expected or generated. this bit actually controls the value that is written to usep1[tm] before processing this transaction. 5 ? reserved, should be cleared. 5?8 endp endpoint this field indicates the endpoint number to be included in the token. 9?15 addr address this field indicates the device address to be included in the token. 0x0a 0?15 ? reserved, should be cleared. 1 written by the usb controller after it finishes sending or receiving the associated data buffer. table 35-19. usb host trbd fields (continued) offset bits name description 4 datasheet u .com
universal serial bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 35-33 35.8 usb controller errors the usb controller reports frame reception and transmission error c onditions using the bds and the usb event register (usber). tran smission errors are shown in table 35-20 . errors which exist exclusively in host mode or function mode are marked as such. table 35-21 describes the usb controller reception errors. 35.9 usb function controller initialization example the following is an exampl e initialization sequence for the usb cont roller operating in function mode. it can be used to set up two function endpoints to fill tr ansmit fifos so that data is ready for transmission when an in token is received from the usb. the t okens can be generated using a usb traffic generator. 1. program cmxscr to provide a 48 mhz clock to the usb controller. table 35-20. usb controller transmission errors error description transmit underrun if an underrun occurs, the transmitter forces a bit stuffi ng violation, terminates buffer transmission, closes the buffer, sets txbd[un] an d the corresponding usber[txe n ]. the endpoint resumes transmission after the restart tx endpoint command is received. transmit timeout transmit packet not acknowledged. if a timeout oc curs, the controller trie s to retransmit if usep n [rte] = 1. if rte = 0 or the second atte mpt fails, the controller closes the buffer and se ts txbd[to] and usber[txe n ]. the endpoint resumes transmission after receiving a restart tx endpoint command. tx data not ready for usb function mode only. this error occurs if an in token is received, but the corresponding endpoint?s transmit fifo is empty, or if the target endpoint is configured to nak or stall. the controller sets usber[txe n ]. reception of nak or stall handshake for usb host mode only. if this error occurs, the channel closes the buffer, sets the corresponding status bit in the txbd (nak or stal), and sets the txe bit in the usb event register. the host will resume transmission after reception of the restart transmit command. table 35-21. usb controller reception errors error description overrun error if the 16-byte receive fifo overruns, the previous ly received byte is overwritten. the controller closes the buffer and sets both rxbd[ov] and usber[rxb]. for usb function mode the nak handshake is sent after the end of the received packet if the packet was received error-free. busy error a frame was received and discarded due to lack of buffers. the controller sets usber[bsy]. non octet-aligned packet if this error occurs, the controller writes the received data to the buffer, closes the buffer and sets both rxbd[no] and usber[rxb]. crc error when a crc error occurs, the controller closes the buffer, and sets both rxbd[cr] and usber[rxb]. in isochronous mode (usep n [tm] = 0b11), the usb controller reports a crc error; however, there are no handshake packets (ack) and the transfer continues normally when an error occurs. buffer overflow for usb host mode packet-level interface only. if the received data packet is larger than the allocated buffer, the remaining data is discarded, and trbd[bov] is set. the txe1 interrupt bit is set. 4 datasheet u .com
universal serial bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 35-34 freescale semiconductor 2. program the port registers to select us brxd, usbrxp, usbrxn, usbtxp, usbtxn, and usboe . 3. clear frame_n. 4. write (dpram+0x500) to ep1ptr, and (dpram +0x520) to ep2ptr to set up the endpoint pointers. 5. write 0xbc80_0004 to dpram+0x20 to set up the txbd [status and control, data length] fields of endpoint 1. 6. write dpram+0x200 to dpram+0x24 to set up the txbd[buffer pointer] field of endpoint 1. 7. write 0xbcc0_0004 to dpram+0x28 to set up the txbd [status and control, data length] fields of endpoint 2. 8. write dpram+0x210 to dpram+0x2c to set up the txbd[buffer po inter] field of endpoint 2. 9. write 0xcafe_cafe to dpram+0x200 to set up the endpoint 1 tx data pattern. 10. write 0xface_face to dpram+0x210 to set up the endpoint 2 tx data pattern. 11. write 0x0000_0020 to dpram+0x500 to set up the rbase and tbas e fields of the endpoint 1 parameter ram. 12. write 0x1818_0100 to dpram+0x504 to set up the rfcr, tfcr, and mrblr fields of the endpoint 1 parameter ram. 13. write 0x0000_0020 to dpram+0x508 to set up the rbptr and tbptr fields of the endpoint 1 parameter ram. 14. clear the tstate field of the endpoint 1 parameter ram. 15. write 0x0008_0028 to dpram+0x520 to set up the rbase and tbase fields of the endpoint 2 parameter ram. 16. write 0x1818_0100 to dpram+0x524 to set up the rfcr, tfcr, and mrblr fields of the endpoint 2 parameter ram. 17. write 0x0008_0028 to dpram+0x528 to set up the rbptr and tbptr fields of the endpoint 2 parameter ram. 18. clear the tstate field of the endpoint 2 parameter ram. 19. write 0x0000 to usep1: endpoint number 0, cont rol transfer, one packet only, and normal handshake. 20. write 0x7200 to usep2: endpoint number 7, bul k transfer, one packet only, and normal handshake. 21. write 0x00 to the usmod for full-speed 12 mbps function endpoint mode and disable the usb. 22. write 0x05 to the usad for slave address 5. 23. set usmod[en] to enable the usb controller. 24. write 0x80 to uscom to start filling the tx fi fo with endpoint 1 data ready for transmission when an in token is received. 25. write 0x81 to uscom to start filling the tx fi fo with endpoint 2 data ready for transmission when an in token is received. 26. generate an in token to a ddress 5, endpoint number 0, control. 27. generate an in token to address 5, endpoint number 7, bulk. 4 datasheet u .com
universal serial bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 35-35 35.10 programming the usb host controller (packet-level) the MPC8555E implementation of a us b host uses the endpoint represen ted by usep1 to control the host transmission and reception. the other endpoints are typically not used, exce pt for testing purposes (loopback). programming the usb controller to act as host is similar to configuri ng an endpoint for function operation. a general outline of how to program the host controll er follows. (a more detailed example can be found in section 35.10.1, ?usb host controll er initialization example.? ) ? set the host bit in the mode regi ster (usbmod[host] = 1) to conf igure the controller as a host. ? set the multi-frame bit in the endpoint confi guration register (usep1[mf] = 1) to allow setup/out tokens and data0/data1 pa ckets to be sent back-to-back. ? prepare tokens in separate bds. ? using software, append the crc5 as part of the transmitted data because the cpm does not support automatic crc5 generation. ? clock the usb host controller as a high speed function (48-mhz reference clock). ? for low-speed transactions with an external hub, set txbd[lsp] in the token?s bd. this causes the usb host controller to genera te a preamble (pre token) at full speed before changing the transmit rate to low sp eed and sending the data packet. after completion of the tr ansaction, the host returns to full-speed operation. note th at lsp should be set only for token bds. 35.10.1 usb host controller initialization example the following is a local loopback example initializa tion sequence for the usb controller operating as a host. it can be used to set up the host endpoint a nd one function endpoint to demonstrate an in token transaction. 1. program cmxscr to provide a 48-mh z clock to the usb controller. 2. program the port registers to select us brxd, usbrxp, usbrxn, usbtxp, usbtxn, and usboe . 3. write (dpram+0x500) to ep1ptr, (dpram+0x520) to ep2ptr to set up the endpoint pointers. 4. write 0x0000_0020 to dpram+0x500 to set up the rbase and tbase fields of the host endpoint parameter ram. 5. write 0x1818_0100 to dpram+0x504 to set up the rf cr, tfcr, and mrblr fields of the host endpoint parameter ram. 6. write 0x0000_0020 to dpram+0x508 to set up the rbptr and tbptr fields of the host endpoint parameter ram. 7. clear the tstate field of th e host endpoint parameter ram. 8. write 0x0008_0028 to dpram+0x520 to set up the rbase and tbase fields of the endpoint 2 parameter ram. 9. write 0x1818_0100 to dpram+0x524 to set up the rfcr, tfcr, and mrblr fields of the endpoint 2 parameter ram. 4 datasheet u .com
universal serial bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 35-36 freescale semiconductor 10. write 0x0008_0028 to dpram+0x528 to set up the rbptr and tbptr fields of the endpoint 2 parameter ram. 11. clear the tstate field of the endpoint 2 parameter ram. 12. write 0xb000_0000 to dpram+0x00 to set up the rxbd[status and cont rol, data length] fields of the host endpoint. 13. write dpram+0x100 to dpram+0x04 to set up the rxbd[buffer pointer] field of the host endpoint. 14. write 0xb800_0003 to dpram+0x20 to set up the txbd [status and control, data length] fields of the host endpoint. 15. write dpram+0x200 to dpram+0x24 to set up th e txbd[buffer pointer] field of the host endpoint. 16. write 0xbc80_0003 to dpram+0x28 to set up the txbd [status and control, data length] fields of the function endpoint. 17. write dpram+0x210 to dpram+0x2c to set up the txbd[buffer po inter] field of the function endpoint. 18. write 0x698560 to dpram+0x200 to set up the host endpoint tx data pattern. this pattern consists of the in token and the crc5. 19. write 0xabcd_1234 to dpram+0x210 to set up the function endpoint tx data pattern. 20. write 0x0020 to usep1 for the host: non-isochr onous transfer, multi-packet, packet-level interface. 21. write 0x1100 to usep2 for the function: interrupt transfer, one packet only. 22. write 0x06 to usmod for full-speed 12 mbps si gnaling, local loopback configuration (test and host modes set), and disable the usb. 23. write 0x05 to the usad for slave address 5. 24. set usmod[en] to enable the usb controller. 25. write 0x81 to the uscom to start filling the tx fifo with endpoint 2 data to be ready for transmission when an in token is received. 26. write 0x80 to the uscom to st art transmitting the in token. the expected result s are as follows: ? txbd[status and control] of th e host endpoint should contain 0x3800. ? txbd[data length] of the host endpoint should contain 0x0003. ? txbd[status and control] of endpoint 2 should contain 0x3c80. ? txbd[data length] of e ndpoint 2 should contain 0x0003. ? rxbd[status and control] of th e host endpoint should contain 0x3c00. ? rxbd[data length] of the hos t endpoint should contain 0x0005. ? the receive buffer of the host e ndpoint should contain 0xabcd_122b, 0x42xx_xxxx. 4 datasheet u .com
universal serial bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 35-37 35.11 programming the usb host controller (transaction-level) the MPC8555E implementation of a us b host uses the endpoint represen ted by usep1 to control the host transmission and reception. the other endpoints are typically not used, exce pt for testing purposes (loopback). programming the usb controller to act as host is similar to configuri ng an endpoint for function operation. a general outline of how to program the host controll er follows. (a more detailed example can be found in section 35.11.1, ?usb host controller initialization example.? ) ? set the host bit in the mode regi ster (usbmod[host] = 1) to conf igure the controller as a host. ? set the multi-frame bit in the endpoint confi guration register (usep1[mf] = 1) to allow setup/out tokens and data0/data1 pa ckets to be sent back-to-back. ? set usep1[rte] to enable the transaction-level interface. ? clock the usb host controller as a high speed function (48-mhz reference clock). ? for low-speed transactions with an extern al hub, set trbd[lsp]. this causes the usb host controller to generate a preamble (pre token) at full speed befo re changing the transmit rate to low speed and sending the token. after completion of the transaction, the host returns to full-speed operation. 35.11.1 usb host controller initialization example the following is a local loopback example initializa tion sequence for the usb controller operating as a host. it can be used to set up the host endpoint a nd one function endpoint to demonstrate an in token transaction. 1. program cmxscr to provide a 48-mh z clock to the usb controller. 2. program the port registers to select us brxd, usbrxp, usbrxn, usbtxp, usbtxn, and usboe . 3. write (dpram+0x500) to ep1ptr, (dpram+0x520) to ep2ptr to set up the endpoint pointers. 4. write 0x0020 to dpram+0x502 to set up the tbase field of the host endpoint parameter ram. 5. write 0x1818 to dpram+0x504 to set up the rfcr and tfcr fields of the host endpoint parameter ram. 6. write 0x0020 to dpram+0x50a to set up the tbpt r field of the host e ndpoint parameter ram. 7. clear the tstate field of th e host endpoint parameter ram. 8. initialize the himmr field of the host endpoint parameter ram. 9. write 0x0008_0028 to dpram+0x520 to set up the rbase and tbase fields of the endpoint 2 parameter ram. 10. write 0x1818_0100 to dpram+0x524 to set up the rfcr, tfcr, and mrblr fields of the endpoint 2 parameter ram. 11. write 0x0008_0028 to dpram+0x528 to set up the rb ptr and tbptr fields of the endpoint 2 parameter ram. 12. clear the tstate field of the endpoint 2 parameter ram. 4 datasheet u .com
universal serial bus controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 35-38 freescale semiconductor 13. write 0xb800_0040 to dpram+0x20 to set up the trbd[s tatus and control, data length] fields of the host endpoint. 14. write dpram+0x100 to dpram+0x24 to set up th e trbd[buffer pointer] field of the host endpoint. 15. write 0x8085 to dpram+0x28 to set up the trbd token fields of the host endpoint. 16. write 0xbc80_0003 to dpram+0x28 to set up the txbd [status and control, data length] fields of the function endpoint. 17. write dpram+0x210 to dpram+0x2c to set up the txbd[buffer po inter] field of the function endpoint. 18. write 0xabcd_1234 to dpram+0x210 to set up the function endpoint tx data pattern. 19. write 0x0030 to usep1 for the host: non-isochronous transfer, multi-pack et, transaction-level interface. 20. write 0x1100 to usep2 for the function: interrupt transfer, one packet only. 21. write 0x06 to usmod for full-speed 12 mbps si gnaling, local loopback configuration (test and host modes set), and disable the usb. 22. write 0x05 to the usad for slave address 5. 23. set usmod[en] to enable the usb controller. 24. write 0x81 to the uscom to start filling the tx fifo with endpoint 2 data to be ready for transmission when an in token is received. 25. write 0x80 to the uscom to st art transmitting the in token. the expected result s are as follows: ? trbd[status and control] of th e host endpoint should contain 0x3800. ? trbd[data length] of the host endpoint should contain 0x0005. ? txbd[status and control] of endpoint 2 should contain 0x3c80. ? txbd[data length] of e ndpoint 2 should contain 0x0003. ? the receive buffer of the host e ndpoint should contain 0xabcd_122b, 0x42xx_xxxx. 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 36-1 chapter 36 serial management controllers (smcs) the two serial management controller s (smcs) are full-duplex ports that can be configured independently to support one of three protocols or modes?uart, transparent, or genera l-circuit interface (gci). simple uart operation is used to provide a debug/monitor port in an application, which allows the sccs to be free for other purposes. the smc in uart mode is not as complex as that of the scc in uart mode. the smc clock can be derived from one of the internal baud rate generators or from an external clock signal. however, the clock should be a 16 clock. in totally transparent mode, the smc can be connected to a tdm channel (such as a t1 line) or directly to its own set of signals. the receive and transmit clocks are derived from the tdm channel, the internal baud rate generators, or from an external 1 clock. the transparent protocol allows the transmitter and receiver to use the external synchronization signal. the smc in transparent mode is not as complex as that of the scc in transparent mode. each smc supports the c/i and m onitor channels of the gci bus, for which the smc connects to a time-division multiplex (tdm) ch annel in a serial interface (si x ). smcs support loopback and echo modes for testing. the smc receive r and transmitter are double-buffere d, corresponding to an effective fifo size (latency) of two characters. chapter 23, ?serial interface with time-slot assigner,? describes gci interface configuration. figure 36-1 shows the smc block diagram. figure 36-1. smc block diagram shifter sync rx data register tx data register rxd control logic txd control registers shifter peripheral bus clk system bus 4 datasheet u .com
serial management controllers (smcs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 36-2 freescale semiconductor the receive data source can be l1rxd if the smc is connected to a tdm channel of an si x , or smrxd if it is connected to the nmsi. th e transmit data source can be l1tx d if the smc is c onnected to a tdm or smtxd if it is connected to the nmsi. if the smc is connected to a tdm, the smc receive and transmit clocks can be independent from each other, as defined in chapter 23, ?serial interface with time-slot assigner.? however, if the smc is connected to the nmsi, receive and transmit clocks mu st be connected to a singl e clock source (smclk), an internal signal name for a cloc k generated from the bank of clocks. smclk originat es from an external signal or one of the four internal baud rate generators. an smc connected to a tdm derives a synchronizati on pulse from the tsa. an smc connected to the nmsi using transparent protocol can use smsyn for synchronization to de termine when to start a transfer. smsyn is not used when the smc is in uart mode. 36.1 features the following is a list of the smc?s main features: ? each smc can implement the uart protocol on its own signals. ? each smc can implement a totall y transparent protocol on a mul tiplexed or nonmultiplexed line. this mode can also be used for a fa st connection between microprocessors. ? each smc channel fully supports the c/i and m onitor channels of the gci (iom-2) in isdn applications. ? two smcs support the two sets of c/i and moni tor channels in the scit channels 0 and 1 ? full-duplex operation ? local loopback and echo capability for testing 36.2 common smc settings and configurations the following sections describe settings and configurations that ar e common to the smcs. 36.2.1 smc mode registers (smcmr1, smcmr2) the smc mode registers (smc mr1 and smcmr2), shown in figure 36-2 , select the smc mode as well as mode-specific parameters. the functions of smcmr[8?15] are the same for each protocol. bits 0?7 vary according to protocol selected by the sm bits. 4 datasheet u .com
serial management controllers (smcs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 36-3 table 36-1 describes smcmr fields. bit0123456 7 89101112131415 field: uart ? clen sl pen pm ? sm dm ten ren transparent ? bs revd gci me ? c# reset 0000_0000_0000_0000 r/w r/w offset 0x0x9_1a82(smcmr1 ), 0x0x9_1a92(smcmr2) figure 36-2. smc mode registers (smcmr1, smcmr2) table 36-1. smcmr1, smcmr2 field descriptions bits name description 0 ? reserved, should be cleared 1?4 clen character length (uart). number of bits in the character minus one. the total is the sum of 1 (start bit always present) + number of data bits (5?14) + number of parity bits (0 or 1) + number of stop bits (1 or 2). for example, for 8 data bits, no parity, and 1 stop bit, the total number of bits in the character is 1 + 8 + 0 + 1 = 10. so, clen should be programmed to 9. characters range from 5?14 bits. if the data bit length is less than 8, the msbs of each byte in memory are not used on transmit and are written with zeros on receive. if the length is more than 8, the msbs of each 16-bit word are not used on transmit and are written with zeros on receive. the character must not exceed 16 bits. for a 14-bit data length, set sl to one stop bit and disable parity. for a 13-bit data length with parity enabled, set sl to one stop bit. writing values 0 to 3 to clen causes erratic behavior. character length (transparent). the values 3?15 specify 4?16 bits per character. if a character is less than 8 bits, the most-significant bits of the byte in buffer memory are not used on transmit and are written with zeros on receive. if character length is more than 8 bits but le ss than 16, the most-significant bits of the half-word in buffer memory are not used on transmit and are written with zeros on receive. note: using values 0?2 causes erratic behavior. la rger character lengths increase an smc channel?s potential performance and lowers the performance impac t of other channels. for instance, using 16- rather than 8-bit characters is encour aged if 16-bit characters are a cceptable in the end application. character length (gci). number of bits in the c/i and monitor channels of the scit channels 0 or 1. (values 0?15 correspond to 1?16 bits.) clen should be 13 for scit channel 0 or gci (8 data bits, plus a and e bits, plus 4 c/i bits = 14 bits). it should be 15 for the scit channel 1 (8 data, bits, plus a and e bits, plus 6 c/i bits = 16 bits). 5 sl stop length (uart) 0 one stop bit 1 two stop bits ? reserved, should be cleared. (transparent) me monitor enable (gci) 0 the smc does not support the monitor channel. 1 the smc supports the monitor channel. 4 datasheet u .com
serial management controllers (smcs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 36-4 freescale semiconductor 36.2.2 smc buffer descriptor operation in uart and transparent modes, the smc?s memory structure is like the scc?s, except that smc-associated data is stored in buffers. each buffer is referenced by a bd and organized in a bd table located in the dual-port ram. see figure 36-3 . 6 pen parity enable (uart) 0 no parity 1 parity is enabled for the transmitter and receiver as determined by the pm bit. bs byte sequence(transparent). controls the byte transm ission sequence if revd is set for a character length greater than 8 bits. clear bs to maintain behavior compatibility with mc68360 quicc. 0 normal mode. this should be selected if th e character length is not larger than 8 bits. 1 transmit lower address byte first. ? reserved, should be cleared. (gci) 7 pm parity mode (uart) 0 odd parity 1even parity revd reverse data (transparent) 0 normal mode 1 reverse the character bit order. the msb is sent first. c# scit channel number (gci) 0 scit channel 0 1 scit channel 1. required for siemens arcofi and sgs s/t chips 8?9 ? reserved, should be cleared. 10?11 sm smc mode 00 gci or scit support 01 reserved. 10 uart (must be selected for smc uart operation) 11 totally transparent operation 12?13 dm diagnostic mode. 00 normal operation 01 local loopback mode 10 echo mode 11 reserved 14 ten smc transmit enable 0 smc transmitter disabled 1 smc transmitter enabled 15 ren smc receive enable 0 smc receiver disabled 1 smc receiver enabled table 36-1. smcmr1, smcmr2 field descriptions (continued) bits name description 4 datasheet u .com
serial management controllers (smcs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 36-5 figure 36-3. smc memory structure the bd table allows buffers to be defined for tran smission and reception. each table forms a circular queue. the cp uses bds to confirm reception and transmission so th at the processor knows buffers have been serviced. the data resides in external or internal buffers. when smcs are configured to operate in gci mode, their memory structure is predefined to be one half-word long for transmit and one half-word long fo r receive. for more inform ation on these half-word structures, see section 36.5, ?smc in gci mode.? 36.2.3 smc parameter ram the cp accesses each smc?s parameter tabl e using a user-programmed pointer (smc x _base) located in the parameter ram; see section 21.4.2, ?parameter ram.? each smc paramete r ram table can be placed at any 64-byte aligned addres s in the dual-port ram?s general-purpose area (banks 1?8, 11, and 12). the protocol-specific portions of the smc parameter ram are discusse d in the sections that follow. the smc parameter ram shared by the uart and transparent protocols is shown in table 36-2 . parameter ram for gci prot ocol is described in table 36-16 . status and control data length buffer pointer pointer to smcx txbd table pointer to smcx rxbd table smc rxbd ta bl e smc txbd ta bl e dual-port ram status and control data length buffer pointer tx data buffer external memory rxbd table txbd table rx data buffer 4 datasheet u .com
serial management controllers (smcs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 36-6 freescale semiconductor table 36-2. smc uart and transparent parameter ram memory map offset 1 name width description 0x00 rbase hword rxbds and txbds base address. (bd table poin ter) define starting points in the dual-port ram of the set of bds for the smc send and receive func tions. they allow flexible partitioning of the bds. by selecting rbase and tbase entries for all smcs and by setting w in the last bd in each list, bds are allocated for the send and receive side of every smc. initialize these entries before enabling the corresponding channel. configuring bd tables of two enabled smcs to overlap causes erratic operation. rbase and tbase should be a multiple of eight. 0x02 tbase hword 0x04 rfcr byte rx/tx function code. see section 36.2.3.1, ?smc function code registers (rfcr, tfcr).? 0x05 tfcr byte 0x06 mrblr hword maximum receive buffer length. the most byte s the MPC8555E writes to a receive buffer before moving to the next buffer. it can write fewer bytes than mrblr if a condition like an error or end-of-frame occurs, but it cannot exceed mr blr. MPC8555E buffers should not be smaller than mrblr. smc transmit buffers are unaffected by mrblr. transmit buffers can be individually given varying lengths through the data length field. mrblr can be changed while an smc is oper ating only if it is done in a single bus cycle with one 16-bit move (not two 8-bit bus cycles back-to-back). this occurs when the cp shifts control to the next rxbd, so the change does not take effect immedi ately. to guarantee the exact rxbd on which the change occurs, change mrblr only while the smc receiver is disabled. mrblr should be greater than zero and should be even if character length exceeds 8 bits. 0x08 rstate word rx internal state. 2 can be used only by the cp. 0x0c ? word rx internal data pointer. 2 updated by the sdma channels to show the next address in the buffer to be accessed. 0x10 rbptr hword rxbd pointer. points to the next bd for each smc channel that the receiver transfers data to when it is in idle state, or to the current bd during frame processing. after a reset or when the end of the bd table is reached, the cp in itializes rbptr to the value in rbase. most applications never need to write rbptr, but it c an be written when the receiver is disabled or when no receive buffer is in use. 0x12 ? hword rx internal byte count. 2 a down-count value initialized with the mrblr value and decremented with every byte the sdma channels write. 0x14 ? word rx temp 2 can be used only by the cp. 0x18 tstate word tx internal state. 2 can be used only by the cp. 0x1c ? word tx internal data pointer. 2 updated by the sdma channels to show the next address in the buffer to be accessed. 0x20 tbptr hword txbd pointer. points to the next bd for each smc channel the transmitter transfers data from when it is in idle state or to the current bd duri ng frame transmission. after reset or when the end of the table is r eached, the cp initializes tbptr to t he tbase value. most applications never need to write tbptr, but it can be written when th e transmitter is disabled or when no transmit buffer is in use. for instance, after a stop transmit or graceful stop transmit command is issued and the frame completes its transmission. 0x22 ? hword tx internal byte count. 2 a down-count value initialized with the txbd data length and decremented with every byte the sdma channels read. 0x24 ? word tx temp. 2 can be used only by the cp. 4 datasheet u .com
serial management controllers (smcs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 36-7 to extract data from a partiall y full receive buffer, issue a close rxbd command. certain parameter ram values must be initialized before the smc is en abled. other values are initialized or written by the cp. once values are initialized, software typically does not need to update them because activity centers mostly around transm it and receive bds rather than parameter ram. however, note the following: ? parameter ram can be read at any time. ? values that pertain to the smc transmitter can be written only if smcmr[ten ] is zero or between the stop transmit and restart transmit commands. ? values for the smc receiver can be written onl y when smcmr[ren] is zero, or, if the receiver is previously enabled, after an enter hunt mode command is issued but before the close rxbd command is issued and ren is set. 0x28 max_idl hword maximum idle characters. (uart protocol-speci fic parameter) when a character is received on the line, the smc starts counting idle characters received. if max_idl idle characters arrive before the next character, an idle time-out occu rs and the buffer closes, which sends an interrupt request to the core to receive data from the buffer. max_idl demarcates frames in uart mode. clearing max_idl disables the function so the buffer never closes, regardless of how many idle characters are received. an idle character is calculated as follows: 1 + data length (5 to 14) + 1 (if parity bit is used) + number of stop bits (1 or 2). for example, for 8 data bits, no parity, and 1 stop bit, character length is 10 bits. 0x2a idlc hword temporary idle counter. (uart protocol-s pecific parameter) down-counter in which the cp stores the current idle counter val ue in the max_idl time-out process. 0x2c brkln hword last received break length. (uart protoc ol-specific parameter) holds the length of the last received break character sequence measured in character units. for example, if the receive signal is low for 20 bit times and the defin ed character length is 10 bits, brkln = 0x002, indicating that the break sequence is at least 2 characters long. brkln is accurate to within one character length. 0x2e brkec hword receive break condition counter. (uart prot ocol-specific parameter) counts break conditions on the line. a break condition may last for hund reds of bit times, yet brkec increments only once during that period. 0x30 brkcr hword break count register (transmit). (uart prot ocol-specific parameter) determines the number of break characters the uart controller sends. set when the smc sends a break character sequence after a stop transmit command. for 8 data bits, no parity, 1 stop bit, and 1 start bit, each break character is 10 zeros. 0x32 r_mask hword temporary bit mask. (uart protocol-specific parameter) 0x34 ? word sdma temp 1 from the pointer value programmed in smc x _base: smc1_base at 0x87fc, smc2_base at immr + 0x88fc. 2 not accessed for normal operation. may hold helpful information for experienced users and for debugging. table 36-2. smc uart and transparent parameter ram memory map (continued) offset 1 name width description 4 datasheet u .com
serial management controllers (smcs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 36-8 freescale semiconductor 36.2.3.1 smc function code registers (rfcr, tfcr) the function code registers contain the transaction specification associ ated with sdma channel accesses to external memory. figure 36-4 shows the register format. table 36-3 describes fcr fields. 36.2.4 disabling smcs on-the-fly an smc can be disabled a nd re-enabled later by ensuring that buffers are closed properl y and new data is transferred to or from a new buffer. such a sequence is required if the parameters to be changed are not dynamic. if the register or bit description states th at dynamic changes are allo wed, the sequences need not be followed and the register or bits may be changed immediately. note the smc does not have to be fully disabled for parameter ram to be modified. table 36-2 describes when parameter ram values can be modified. to disable all sc cs, smcs, the spi, and the i 2 c, use the cpcr to reset the cpm with a single command. 01234567 field gbl bo tc2 dtb ? r/w r/w offset smc base + 0x04 (rfcr)/smc base + 0x05 (tfcr) figure 36-4. smc function code registers (rfcr, tfcr) table 36-3. rfcr, tfcr field descriptions bit name description 0?1 ? reserved, should be cleared. 2 gbl global access bit 0 disable memory snooping 1 enable memory snooping 3?4 bo byte ordering. selects byte ordering of the data buffer. 00 the dec/intel convention (swapped operation or little-endian). the transmission order of bytes within a buffer word is opposite of big-endian mode. (32-bit port size memory only). 01 munged little-endian. as data is sent onto the se rial line from the buffer, the lsb of the buffer double word contains data to be sent earlier than the msb of the same double word. 1x big-endian byte ordering (normal operation). as data is sent onto the serial line from the buffer, the msb of the buffer word contains data to be sent earlier than the lsb of the same word. 5 tc2 transfer code 2. contains the transfer code valu e of tc[2], used during this sdma channel memory access. tc[0:1] is driven with a 0b11 to identify this sdma channel access as a dma-type access. 6 dtb data bus indicator 0 use system bus for sdma operation 1 reserved. 7 ? reserved, should be cleared. 4 datasheet u .com
serial management controllers (smcs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 36-9 36.2.4.1 smc transmitter full sequence follow these steps to fully enable or disable the smc transmitter: 1. if the smc is sending data, issue a stop transmit command to stop transm ission smoothly. if the smc is not sending, if tbptr is overwritten, or if an init tx parameters command is executed, this command is not required. 2. clear smcmr[ten] to disable the smc tr ansmitter and put it in reset state. 3. update smc transmit parameters, including th e parameter ram. to switch protocols or reinitialize parameters, issue an init tx parameters command. 4. issue a restart transmit if an init tx parameters was issued in step 3. 5. set smcmr[ten]. transmission now begins using the txbd that the tbptr value pointed to as soon as the r bit is set in the txbd. 36.2.4.2 smc transmitter shortcut sequence this shorter sequence reinitializes transmit pa rameters to the state they had after reset. 1. clear smcmr[ten]. 2. issue an init tx parameters command and make any additional changes. 3. set smcmr[ten]. 36.2.4.3 smc receiver full sequence follow these steps to fully enable or disable the receiver: 1. clear smcmr[ren]. reception is aborted immedi ately, which disables the smc receiver and puts it in a reset state. 2. modify smc receive pa rameters, including parameter ram. to switch protocols or reinitialize smc receive parameters, issue an init rx parameters command. 3. issue a close rxbd command if init rx parameters was not issued in step 2. 4. set smcmr[ren]. reception immedi ately uses the rxbd that rbptr pointed to if e is set in the rxbd. 36.2.4.4 smc receiver shortcut sequence this shorter sequence reinitializes receive parameters to their state after reset. 1. clear smcmr[ren]. 2. issue an init rx parameters command and make any additional changes. 3. set smcmr[ren]. 36.2.4.5 switching protocols to switch the protocol th at the smc is executing wi thout resetting the board or affecting any other smc, use one command and follow these steps: 1. clear smcmr[ren] and smcmr[ten]. 4 datasheet u .com
serial management controllers (smcs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 36-10 freescale semiconductor 2. issue an init tx and rx parameters command to initialize transmit and receive parameters. make any additional smcmr changes. 3. set smcmr[ren, ten]. the smc is now enabled with the new protocol. 36.2.5 saving power when smcmr[ten, ren] are cleared, the smc consumes little power. 36.2.6 handling interrupts in the smc follow these steps to handle an interrupt in the smc: 1. once an interrupt occurs , read smce to identify the interrupt source. the smce bits are usually cleared at this time. 2. process the txbd to reuse it if smce[txb] is set. extract da ta from the rxbd if smce[rxb] is set. to send another buffer, set txbd[r]. 3. execute the rfi instruction. 36.3 smc in uart mode smcs generally offer less functiona lity and performance in uart mode than do sccs, wh ich makes them more suitable for simpler debug/monitor ports instea d of full-featured uarts. smcs do not support the following features in uart mode. ?rts , cts , and cd signals ? receive and transmit sections clocked at different rates ? fractional stop bits ? built-in multidrop modes ? freeze mode for implementing flow control ? isochronous (1 clock) operation (a 16 clock is required for uart operation.) ? interrupts on special cont rol character reception ? ability to transmit da ta on demand using the todr ? sccs register to determine idle status of the receive signal ? other features for the sccs as described in the gsmr however, smcs allow a data length of up to 14 bits; sccs support up to 8 bits. figure 36-5. smc uart frame format smclk smtxd 16x start bit parity bit (optional) 5 to 14 data bits with the least-significant bit first 1 or 2 stop bits (not to scale) 4 datasheet u .com
serial management controllers (smcs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 36-11 36.3.1 features the following list summarizes the main features of the smc in uart mode: ? flexible message-oriented data structure ? programmable data length (5?14 bits) ? programmable 1 or 2 stop bits ? even/odd/no parity generation and checking ? frame error, break, and idle detection ? transmit preamble and break sequences ? received break character length indication ? continuous receive and transmit modes 36.3.2 smc uart channel transmission process the uart transmitter is designed to work with almo st no intervention from the core. when the core enables the smc transmitter, it starts sending idle s. the smc immediately polls the first bd in the transmit channel bd table and once every character time after that, depending on character length. when there is a message to transmit, the smc fetches data from memory and starts sending the message. when a bd data is completely written to the transmit fifo, the smc writes the message status bits into the bd and clears r. an interr upt is issued if the i bit in the bd is set. if the next txbd is ready, the data from its buffer is appended to the pr evious data and sent over the trans mit signal without any gaps between buffers. if the next txbd is not ready, the smc star ts sending idles and waits for the next txbd to be ready. by appropriately setting the i bit in each bd, interrupts can be generated after each buffer, a specific buffer, or each block is sent. the smc then proceeds to the ne xt bd. if the cm bit is set in the txbd, the r bit is not cleared, allowing a buffer to be automatically resent next time the cp accesses this buffer. for instance, if a single txbd is initiali zed with the cm and w bits set, th e buffer is sent c ontinuously until r is cleared in the bd. 36.3.3 smc uart channel reception process when the core enables the smc receiver, it enters hunt mode and waits for the fi rst character. the cp then checks the first rxbd to see if it is empty and starts storing characters in the buffer. when the buffer is full or the max_idl timer expires (if enabled), the smc clears the e bit in the bd and generates an interrupt if the i bit in the bd is set. if incoming data exceeds the buff er?s length, the smc fetches the next bd, and, if it is empty, cont inues transferring data to this bd?s buffe r. if cm is set in the rxbd, the e bit is not cleared, so the cp can overw rite this buffer on its next access. 36.3.4 programming the smc uart controller uart mode is selected by setting smcmr[sm] to 0b10. see section 36.2.1, ?smc mode registers (smcmr1, smcmr2).? uart mode uses the same data stru cture as other modes. this structure supports multibuffer operation and allo ws break and preamble sequences to be sent. overrun, parity, and 4 datasheet u .com
serial management controllers (smcs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 36-12 freescale semiconductor framing errors are reported through the bds. at its simplest, the smc uart controller functions in a character-oriented environment, wherea s each character is sent with the selected stop bits and parity. they are received into separate 1-byte buf fers. a maskable interrupt can be generated when each buffer is received. many applications can take advant age of the message-oriented capa bilities that the smc uart supports through linked buffers for sending or receiving. data is handled in a message-oriented environment, so entire messages can be handled inst ead of individual characters. a message can span several linked buffers; each one can be sent and received as a linked list of buffers without core intervention, which simplifies programming and saves processor overhead. in a message-oriented environment, an idle sequence is used as the message deli miter. the transmitter can generate an idle sequence before starting a new message and the receiver can close a buffer when an idle sequence is found. 36.3.5 smc uart transmit and receive commands table 36-4 describes transmit comma nds issued to the cpcr. table 36-5 describes receive commands issued to the cpcr. 36.3.6 sending a break a break is an all-zeros ch aracter without st op bits. it is sent by issuing a stop transmit command. after sending any outstanding data, the smc sends a character of consecutive zeros, the number of which is the table 36-4. transmit commands command description stop transmit disables transmission of characters on the transmit chann el. if the smc uart controller receives this command while sending a message, it stops sending. the smc uart controller finishes sending any data that has already been sent to its fifo and shift regi ster and then stops sending data. th e tbptr is not advanced when this command is issued. the smc uart controller sends a programmable number of break sequences and then sends idles. the number of break sequences, which can be zero, should be written to the brkcr before this command is issued to the smc uart controller. restart transmit enables characters to be sent on the transmit channel. the smc uart controller expects it after disabling the channel in its smcmr and after issuing the stop transmit command. the smc uart controller resumes transmission from the current tbptr in the channel?s txbd table. init tx parameters initializes transmit parameters in this serial channel?s parameter ram to their reset state and should only be issued when the transmitter is disabled. the init tx and rx parameters command can also be used to reset the transmit and receive parameters. table 36-5. receive commands command description enter hunt mode use the close rxbd command instead enter hunt mode for an smc uart channel. close rxbd forces the smc to close the current receive bd if it is currently being used and to use the next bd in the list for any subsequently received data. if the smc is not receiving data, no action is taken. init rx parameters initializes receive parameters in this serial channel paramet er ram to reset state. issue it only if the receiver is disabled. init tx and rx parameters resets both receive and transmit parameters. 4 datasheet u .com
serial management controllers (smcs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 36-13 sum of the character length, plus th e number of start, pari ty, and stop bits. the sm c sends a programmable number of break characters according to brkcr and then reverts to idle or sends data if a restart transmit is issued before completion. when the break comp letes, the transmitter sends at least one idle character before sending any data to gua rantee recognition of a valid start bit. 36.3.7 sending a preamble a preamble sequence provides a way to ensure that the line is idle before a new message transfer begins. the length of the preamble sequence is constructed of consecutive ones that are one-chara cter long. if the preamble bit in a bd is se t, the smc sends a preamble sequence before sending that buffer. for 8 data bits, no parity, 1 stop bit, and 1 start bit, a preamble of 10 ones would be sent before the first character in the buffer. if no preamble seque nce is sent, data from two ready transm it buffers can be sent on the transmit signal with no delay between them. 36.3.8 handling errors in the smc uart controller the smc uart controller re ports character recepti on error conditions through the channel bds and the smce. table 36-6 describes the reception errors. the smc uart controller has no transmission errors. table 36-6. smc uart errors error description overrun the smc maintains a two-character le ngth fifo for receiving data. data is moved to the buffer after the first character is received into the fifo; if a receiver fifo overrun occurs, the channel writes the received character into the internal fifo. it then writes the character to the buffer, closes it, sets the ov bit in the bd, and generates the rxb interrupt if it is enabled. reception then resumes as normal. overrun errors that occasionally occur when the line is idle can be ignored. parity the channel writes the received character to the buffer , closes it, sets the pr bit in the bd, and generates the rxb interrupt if it is enabled. reception then resumes as normal. idle sequence receive an idle is found when a character of all ones is receiv ed, at which point the channel counts consecutive idle characters. if the count reaches max_idl, the buffer is closed and an rxb interrupt is generated. if no receive buffer is open, this does not generate an interrupt or any status information. the idle counter is reset each time a character is received. framing the smc received a character with no stop bit. when it occurs, the channel writes the received character to the buffer, closes the buffer, sets fr in the bd, and generates the rxb interrupt if it is enabled. when this error occurs, parity is not checked for the character. break sequence the smc receiver received an all-zero character with a framing error. the channel increments brkec, generates a maskable brk interrupt in smce, meas ures the length of the break sequenc e, and stores this value in brkln. if the channel was processing a buffer when the break was received, the buffer is closed with the br bit in the rxbd set. the rxb interrupt is generated if it is enabled. 4 datasheet u .com
serial management controllers (smcs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 36-14 freescale semiconductor 36.3.9 smc uart rxbd using the bds, the cp reports inform ation about the received da ta on a per-buffer basis. then it closes the current buffer, generates a maskable interrupt, and starts recei ving data into the next buffer after one of the following occurs: ? an error is received during message processing ? a full receive buffer is detected ? a programmable number of consecuti ve idle characters are received figure 36-6 shows the format of the smc uart rxbd. table 36-7 describes rxbd fields. 0123456789101112131415 offset + 0 e ? wi ? cm id ? brfrpr ? ov ? offset + 2 data length offset + 4 rx data buffer pointer offset + 6 figure 36-6. smc uart rxbd table 36-7. smc uart rxbd field descriptions bits name description 0 e empty 0 the buffer is full or data reception stopped due to an error. the core can read or write any fields of this rxbd. the cp does not use this bd while e is zero. 1 the buffer is empty or reception is in progress. this rxbd and its buffer are owned by the cp. once e is set, the core should not write any fields of this rxbd. 1 ? reserved, should be cleared. 2 w wrap (last bd in rxbd table) 0 not the last bd in the table 1 last bd in the table. after this bu ffer is used, the cp receives incomi ng data into the first bd that rbase points to in the table. the number of rxbds in this table is determined only by the w bit and overall space constraints of the dual-port ram. 3 i interrupt 0 no interrupt is generated after this buffer is filled. 1 the smce[rxb] is set when this buffer is completely filled by the cp, indicating the need for the core to process the buffer. rxb can cause an interrupt if it is enabled. 4?5 ? reserved, should be cleared. 6 cm continuous mode 0 normal operation 1 the cp does not clear the e bit after this bd is closed, allowing the cp to automatically overwrite the buffer when it next accesses the bd. however, e is cleared if an error occurs during reception, regardless of how cm is set. 7 id buffer closed on reception of idles. set when the buffer has closed because a programmable number of consecutive idle sequences is received. the cp writes id after received data is in the buffer. 4 datasheet u .com
serial management controllers (smcs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 36-15 data length represents the number of octets the cp writes into the buffer . after data is re ceived in buffer, the cp only writes them once as the bd closes. note that the memory allocated for this buffer should be no smaller than mrblr. the rx data buffer pointer point s to the first location of the buffer and must be even. the buffer can be in internal or external memory. figure 36-7 shows the uart rxbd process, showing rxbds after they receive 10 characters, an idle period, and fi ve characters (one with a framing error). the example assumes that mrblr = 8. 8?9 ? reserved, should be cleared. 10 br buffer closed on reception of break. set when the buffer closes because a break sequence was received. the cp writes br after the received data is in the buffer. 11 fr framing error. set when a character with a framing error is received and located in the last byte of this buffer. a framing error is a character with no stop bit. a new rece ive buffer is used to receive additional data. the cp writes fr after the received data is in the buffer. 12 pr parity error. set when a character with a parity error is received in the last byte of the buffer. a new buffer is used for additional data. the cp writes pr after received data is in the buffer. 13 ? reserved, should be cleared. 14 ov overrun. set when a receiver overrun occurs during reception. the cp writes ov after the received data is in the buffer. 15 ? reserved, should be cleared. table 36-7. smc uart rxbd field descriptions (continued) bits name description 4 datasheet u .com
serial management controllers (smcs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 36-16 freescale semiconductor figure 36-7. rxbd example byte 5 buffer 0 0008 32-bit buffer pointer 0 eid receive bd 0 status length pointer 0 0002 32-bit buffer pointer 1 eid receive bd 1 status length pointer 0 0004 32-bit buffer pointer 0 eid receive bd 2 status length pointer 1 xxxx 32-bit buffer pointer e receive bd 3 status length pointer byte 1 byte 2 byte 8 buffer byte 9 byte 10 buffer byte 1 byte 2 byte 3 buffer byte 4 error! empty additional bytes are stored unless idle count expires (max_idl) 8 bytes 8 bytes 8 bytes 8 bytes characters received by uart fourth character 10 characters long idle period has framing error! present time time 5 characters buffer full idle time-out occurred byte 4 has framing error reception still in progress with this buffer 1 fr etc. empty mrblr = 8 bytes for this smc 4 datasheet u .com
serial management controllers (smcs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 36-17 36.3.10 smc uart txbd data is sent to the cp for tran smission on an smc channel by arrangi ng it in buffers referenced by the channel txbd table. using the bds, the cp conf irms transmission or indicates error conditions so that the processor knows the buffers have been serv iced. an smc uart txbd is displayed in figure 36-8 . table 36-8 describes smc uart txbd fields. data length represents the nu mber of octets that the cp should transmit fr om this bd data buffer. however, it is never modified by the cp and normally is greate r than zero. it can be zero if p is set and only a preamble is sent. if there are more than 8 bits in the uart charact er, data length should be even. for example, to transmit three uart characters of 8-bi t data, 1 start, and 1 stop, init ialize the data length field to 3. to send three uart characters of 9-bit data, 1 start, and 1 stop, th e data length fiel d should 6, because 012345678 15 offset + 0 r ? wi ? cm p ? offset + 2 data length offset + 4 tx data buffer pointer offset + 6 figure 36-8. smc uart txbd table 36-8. smc uart txbd field descriptions bits name description 0 r ready 0 the buffer is not ready for transmission; bd and its buffer can be altered. the cp clears r after the buffer has been sent or an error occurs. 1 the buffer has not been completely sent. this bd cannot updated while r is set. 1 ? reserved, should be cleared. 2 w wrap (final bd in the txbd table) 0 not the last bd in the table. 1 last bd in the table. after this buffer is used, the cp receives incoming data into the first bd that tbase points to. the number of txbds in this table is det ermined only by the w bit and overall space constraints of the dual-port ram. 3 i interrupt 0 no interrupt is generated after this buffer is serviced. 1 the smce[txb] is set when this buffer is serviced. txb can cause an interrupt if it is enabled. 4?5 ? reserved, should be cleared. 6 cm continuous mode 0 normal operation 1 the cp does not clear r after this bd is closed and automatically retransmits the buffer when it accesses this bd next. 7 p preamble 0 no preamble sequence is sent. 1 the uart sends one all-ones character before it sends the data so that the other end detects an idle line before the data is received. if this bit is set and the dat a length of this bd is zero, only a preamble is sent. 8?15 ? reserved, should be cleared. 4 datasheet u .com
serial management controllers (smcs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 36-18 freescale semiconductor the three 9-bit data fields occupy three half words in memory (the 9 least-signifi cant bits of each half word). tx data buffer pointer points to the first location of the buffer. it can be even or odd, unless the number of data bits in the uart character is greater than 8 bits. then the buffer pointer must be even. for instance, the pointer to 8-bit data, 1 start, and 1 stop characters can be even or odd, but the pointer to 9-bit data, 1 start, and 1 stop characters must be even. the buf fer can reside in internal or external memory. 36.3.11 smc uart event register (smce)/mask register (smcm) the smc event register (smce) ge nerates interrupts and report ev ents recognized by the smc uart channel. when an event is recogni zed, the smc uart contro ller sets the correspond ing smce bit. bits are cleared by writing a 1; writing 0 has no effect. the smc mask regi ster (smcm) has th e same bit format as smce. setting an smcm bit enables, and clear ing it disables, the corresponding interrupt. all unmasked bits must be cleared before the cp clears the internal interrupt request. figure 36-9 represents the smce/smcm registers. table 36-9 describes smce/smcm fields. 01234567 field ? brke ? brk ? bsy txb rxb reset 0 r/w r/w offset 0x0x9_1a86(smce1); 0x0x9_1a96(smce2 )/ 0x0x9_1a8a(smcm1); 0x0x9_1a9a(smcm2) figure 36-9. smc uart event register (smce)/mask register (smcm) table 36-9. smce/smcm field descriptions bits name description 0 ? reserved, should be cleared. 1 brke break end. set no sooner than after one idle bit is received after the break sequence. 2 ? reserved, should be cleared. 3 brk break character received. set when a break character is received. if a very long break sequence occurs, this interrupt occurs only once after the first all-zeros character is received. 4 ? reserved, should be cleared. 5 bsy busy condition. set when a character is received and discarded due to a lack of buffers. set no sooner than the middle of the last stop bit of the first receive char acter for which there is no available buffer. reception resumes when an empty buffer is provided. 6 txb tx buffer. set when the transmit data of the last charac ter in the buffer is written to the transmit fifo. wait two character times to ensure that data is completely sent over the transmit signal. 7 rxb rx buffer. set when a buffer is received and its associ ated rxbd is closed. set no sooner than the middle of the last stop bit of the last character that is written to the receive buffer. 4 datasheet u .com
serial management controllers (smcs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 36-19 figure 36-10 shows an example of the timing of various events in the smce. figure 36-10. smc uart interrupts example 36.3.12 smc uart controller programming example the following initialization sequence assumes 9,600 baud, 8 data bits, no parity, and 1 stop bit in a 66-mhz system. brg1 and smc1 are used. (the smc transparent programming ex ample uses an external clock configuration; see section 36.4.11, ?smc transparent nmsi programming example.? ) 1. configure the port d pins to enable smtx d1 and smrxd1. set ppard[8,9] and pdird[9]. clear pdird[8] and psord[8,9]. 2. configure the brg1. write brgc1 with 0x0001_035a. the div16 bit is not used and the divider is 429 (decimal). the resulting brg1 clock is 16 the preferred bit rate. 3. connect brg1 to smc1 using the cpm mux by clearing cmxsmr[smc1, smc1cs]. 4. in address 0x87fc, assign a pointer to the smc1 parameter ram. 5. assuming one rxbd at the be ginning of dual-port ram follo wed by one txbd, write rbase with 0x0000 and tbase with 0x0008. 6. write 0x1d01_0000 to cpcr to execute the init rx and tx parameters command. 7. write rfcr and tfcr with 0x10 for normal operation. 8. write mrblr with the maximum number of byt es per receive buffer. assume 16 bytes, so mrblr = 0x0010. 9. write max_idl with 0x0000 in the smc uart -specific parameter ram to disable the max_idl functionality for this example. 10. clear brkln and brkec in the sm c uart-specific parameter ram. 11. set brkcr to 0x0001; if a stop transmit command is issued, one break character is sent. rx rx brk brke break line idle 10 characters rxd characters received by smc uart time line idle txd characters transmitted by smc uart tx line idle line idle 7 characters notes: smc uart smce events 1. the first rx event assumes receive buffers are 6 bytes each. 2. the second rx event position is programmable based on the max_idl value. 3. the brk event occurs after the first break character is received. smc uart smce events notes: the tx event assumes all seven characters were put into a single buffer, and the tx event occurred when the seventh character was written to the smc transmit fifo. 1. 4 datasheet u .com
serial management controllers (smcs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 36-20 freescale semiconductor 12. initialize the rxbd. assume the rx data buffer is at 0x0000_10 00 in main memory. write 0xb000 to rxbd[status and control] , 0x0000 to rxbd[data length] ( not required), and 0x0000_1000 to rxbd[buffer pointer]. 13. assuming the tx data buffer is at 0x0000_2000 in main memory and contains five 8-bit characters, write 0xb000 to txbd[statu s and control], 0x0005 to txbd [data length], and 0x0000_2000 to txbd[buffer pointer]. 14. write 0xff to the smce1 register to clear any previous events. 15. write 0x57 to the smcm1 re gister to enable all possible smc1 interrupts. 16. write 0x0000_1000 to the siu interrupt mask register low (simr_l) so the smc1 can generate a system interrupt. write 0xffff_ffff to the siu in terrupt pending register low (sipnr_l) to clear events. 17. write 0x4820 to smcmr to configure normal operation (not loopb ack), 8-bit characters, no parity, 1 stop bit. the transmitter and receiver are not yet enabled. 18. write 0x4823 to smcmr to enable the smc tran smitter and receiver. this additional write ensures that the ten and ren bits are enabled last. after 5 bytes are sent, the txbd is closed. the receive buffer closes after receiving 16 bytes. subsequent data causes a busy (out-of-buffers) c ondition since only one rxbd is ready. 36.4 smc in transparent mode compared to the scc in transparent mode, the smcs generally offer less functi onality, which helps them provide simpler functions and slower speeds. transparent mode is selected by programming smcmr[sm] to 0b10. section 36.2.1, ?smc mode regi sters (smcmr1, smcmr2),? describes other protocol-specific bits in the smcmr. the smc in transparent mode does not support the following features: ? independent transmit and receive clocks, un less connected to a tdm channel of an si x ? crc generation and checking ? full rts , cts , and cd signals (supports only one smsyn signal) ? ability to transmit da ta on demand using the todr ? receiver/transmitter in transparent m ode while executing another protocol ? 4-, 8-, or 16-bit sync recognition ? internal dpll support however, the smc in transparent mode provides a data character length option of 4 to 16 bits, whereas the sccs provide 8 or 32 bits , depending on gsmr[rfw]. the smc in tr ansparent mode is also referred to as the smc transparent controller. 36.4.1 features the following list summari zes the features of the smc in transparent mode: ? flexible data buffers ? connects to a tdm bus using the tsa in an si x 4 datasheet u .com
serial management controllers (smcs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 36-21 ? transmits and receives transparen tly on its own set of signals usin g a sync signal to synchronize the beginning of transmission and re ception to an external event ? programmable character length (4?16) ? reverse data mode ? continuous transmission and reception modes ? four commands 36.4.2 smc transparent channel transmission process the transparent transmitter is designed to work with almost no core intervention. when the core enables the smc transmitter in transparent mode, it starts sending idles. the smc immediately polls the first bd in the transmit channel bd table and once every character time, depending on the character length (every 4 to 16 serial clocks). when there is a message to transmit, the smc fetches the data from memory and starts sending the message when synchronization is achieved. synchronization can be achieved in tw o ways. first, when the transmitte r is connected to a tdm channel, it can be synchronized to a time slot . once the frame sync is received, th e transmitter waits for the first bit of its time slot before it starts transmitting. data is se nt only during the time slots defined by the tsa. secondly, when working with its own set of signa ls, the transmitter star ts sending when smsyn x is asserted. when a bd data is completely writte n to the transmit fifo, the l bit is checked and if it is set, the smc writes the message status bits into the bd and clears the r bit. it then starts transmitting idles. when the end of the current bd is reached and the l bit is not set, only r is cleared. in both cases, an interrupt is issued according to the i bit in the bd. by appropria tely setting the i bit in each bd, interrupts can be generated after each buffer, a specific buffer, or each block is sent . the smc then procee ds to the next bd. if no additional buffers have been presented to th e smc for transmission and the l bit was cleared, an underrun is detected and th e smc begins sending idles. if the cm bit is set in the txbd, the r bit is not cl eared, so the cp can overwr ite the buffer on its next access. for instance, if a single tx bd is initialized with the cm a nd w bits set, the buffer is sent continuously until r is cleared in the bd. 36.4.3 smc transparent channel reception process when the core enables the smc receiver in transpar ent mode, it waits for synchr onization before receiving data. once synchronization is achieved, the receiver transfers the incoming data into memory according to the first rxbd in the table. synchronization can be achieved in two ways. first, when the receiver is connected to a tdm channel, it can be synchronized to a time slot. once the frame sync is received, the receiver waits for the first bit of its time slot to occur before reception begins. data is received only during the time slots defined by the tsa. secondly, when work ing with its own set of si gnals, the receiver starts reception when smsyn x is asserted. when the buffer full, the smc clears the e bit in the bd and generates an interrupt if the i bit in the bd is set. if incoming data exceeds th e data buffer length, the smc fetches th e next bd; if it is empty, the 4 datasheet u .com
serial management controllers (smcs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 36-22 freescale semiconductor smc continues transferring data to this bd?s buffer. if the cm bit is set in the rxbd, the e bit is not cleared, so the cp can automatically overwrite the buffer on its next access. 36.4.4 using smsyn for synchronization the smsyn signal offers a way to externally sync hronize the smc channel. this method differs somewhat from the synchronization opt ions available in the sccs and should be studied carefully. see figure 36-11 for an example. once smcmr[ren] is set, the first ri sing edge of smclk that finds smsyn low causes the smc receiver to achieve synchronization. da ta starts being received or latc hed on the same rising edge of smclk that latched smsyn . this is the first bit of data r eceived. the receiver does not lose synchronization again, regardle ss of the state of smsyn , until ren is cleared. once smcmr[ten] is set, the first risi ng edge of smclk that finds smsyn low synchronizes the smc transmitter which begins sending ones async hronously from the falling edge of smsyn . after one character of ones is sent, if the transmit fifo is loaded (the txbd is ready with data), data starts being send on the next falling edge of smclk after one character of ones is sent. if the transmit fifo is loaded later, data starts being sent after some mu ltiple number of all-ones characters is sent. note that regardless of whether the transmitter or receiver uses smsyn , it must make glitch-free transitions from high-to-low or low-to-high. glitches on smsyn can cause errant behavior of the smc. the transmitter never loses synchronization again, regardle ss of the state of smsyn , until the ten bit is cleared or an enter hunt mode command is issued. 4 datasheet u .com
serial management controllers (smcs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 36-23 figure 36-11. synchronization with smsyn x if both smcmr[ren] and smcmr[ten] are se t, the first falling edge of smsyn causes both the transmitter and receiver to achieve synchronization. the smc transmitter can be disa bled and re-enabled and smsyn can be used again to resync hronize the transmitter itself. section 36.2.4, ?disabling smcs on-the-fly,? describes how to safely disa ble and re-enable the smc. si mply clearing and setting ten may be insufficient. the receiver can also be resynchronized this way. 36.4.5 using the time-slot assign er (tsa) for synchronization the tsa offers an alternative to using smsyn to internally synchronize the smc channel. this method is similar, except that the synchronization event is the first time-slot for this smc receiver/transmitter after the frame sync indication rather than the falling edge of smsyn . chapter 23, ?serial interface with time-slot assigner,? describes how to configure time slots. the tsa allows the smc receiver and transmitter to be enabled simultaneous ly and synchronized separately; smsyn does not provide this capability. figure 36-12 shows synchronization using the tsa. smclk smsyn smtxd 1s are sent five 1s are sent ten set here tx fifo loaded approximately here five 1s assume character length equals 5 first bit of first 5-bit transmit character (lsb) transmission could begin here if tx fifo not loaded in time smsyn detected low here smclk smsyn smrxd ren set here or first bit of receive data (lsb) smsyn detected low here enter hunt mode command issued notes: smclk is an internal clock derived from an external clkx or a baud rate generator. 1. this example shows the smc receiver and transmitter 2. enabled separately. if the ren and ten bits were set at the same time, a single falling edge of smsyn would synchronize both. smc1 transmit data smc1 receive data 4 datasheet u .com
serial management controllers (smcs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 36-24 freescale semiconductor figure 36-12. synchronization with the tsa once smcmr[ren] is set, the first time-slot after the frame sync causes the smc receiver to achieve synchronization. data is received im mediately, but only during defined re ceive time slots. the receiver continues receiving data duri ng its defined time slots unt il ren is cleared. if an enter hunt mode command is issued, the receiver lose s synchronization, closes the buffer, and resynchronizes to the first time slot after the frame sync. once smcmr[ten] is set, the smc waits for the transm it fifo to be loaded before trying to achieve synchronization. when the transmit fifo is loaded, synchronization and transmission begins depending on the following: ? if a buffer is made ready when the smc2 is enable d, the first byte is placed in time slot 1 if clsn is 8 and to slot 2 if clsn is 16. ? if a buffer has its smc enabled, then the first byte in the next buffer can a ppear in any time slot associated with this channel. ? if a buffer is ended with the l bit set, then the ne xt buffer can appear in any time slot associated with this channel. if the smc runs out of tran smit buffers and a new buffer is provided la ter, idles are sent in the gap between buffers. data transmission from the late r buffer begins at the start of an smc time sl ot, but not necessarily the first time slot after the frame sync. so, to maintain a certain bit alignment beginning with the first time slot, make sure that at least one txbd is always ready and that underruns do not occur. otherwise, the smc transmitter should be disabled and re-enabled. section 36.2.4, ?disabling smcs on-the-fly,? tdm tx clk tdm tx sync tdm tx after ten if smc runs out of tx buffers and new ones are provided later, transmission begins at is set, transmission begins here. the beginning of either time slot. smc1 smc1 tdm rx clk tdm rx sync tdm rx after ren is set or after enter hunt mode command, reception begins here. smc1 smc1 4 datasheet u .com
serial management controllers (smcs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 36-25 describes how to safely disable and re-enable the smc. simply clearing and setting ten may not be enough. 36.4.6 smc transparent commands table 36-10 describes transmit comma nds issued to the cpcr. table 36-11 describes receive commands issued to the cpcr. 36.4.7 handling errors in th e smc transparent controller the smc uses bds and the smce to re port message send and receive errors. table 36-10. smc transparent transmit commands command description stop transmit after hardware or software is reset and the channel is enabled in the smcm, the channel is in transmit enable mode and polls the first bd. this command disables transmission of frames on the transmit channel. if the transparent controller receives this command while sendin g a frame, it stops after the contents of the fifo are sent (up to 2 characters). the tbptr is not advanced to the next bd, no new bd is accessed, and no new buffers are sent for this channel. the transmitter sends idles until a restart transmit command is issued. restart transmit starts or resumes transmission from the current tbptr in the channel txbd table. when the channel receives this command, it polls the r bit in this bd. the smc expects this command after a stop transmit is issued. the channel in its mode register is disabled or after a transmitter error occurs. init tx parameters initializes transmit parameters in this serial channel to reset state. use only if the transmitter is disabled. the init tx and rx parameters command resets transmit and receive parameters. table 36-11. smc transparent receive commands command description enter hunt mode forces the smc to close the current receive bd if it is in use and to use the next bd for subsequent data. if the smc is not receiving data, the buffer is not closed. addi tionally, this command causes the receiver to wait for a resynchronization before reception resumes. close rxbd forces the smc to close the current receive bd if it in use and to use the next bd in the list for subsequent received data. if the smc is not in the proc ess of receiving data, no action is taken. i nit rx parameters initializes receive parameters in this serial channel to reset state. use only if the receiver is disabled. the init tx and rx parameters command resets receive and transmit parameters. table 36-12. smc transparent error conditions error descriptions underrun the channel stops sending the buffer, closes it, sets un in the bd, and generates a txe interrupt if it is enabled. the channel resumes sending after a restart transmit command. underrun cannot occur between frames. overrun the smc maintains an internal fifo for receiving dat a. if the buffer is in external memory, the cp begins programming the sdma channel when the first character is received into the fifo. if a fifo overrun occurs, the smc writes the received data character over the previously received charac ter. the previous character and its status bits are lost. then the channel closes the buffer, sets ov in the bd, and generates the rxb interrupt if it is enabled. reception continues as normal. 4 datasheet u .com
serial management controllers (smcs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 36-26 freescale semiconductor 36.4.8 smc transparent rxbd using bds, the cp reports information about the r eceived data for each buffer and closes the current buffer, generates a maskable interrupt , and starts to receive data into the next buffer after one of the following events: ? an overrun error occurs. ? a full receive buffer is detected. ? the enter hunt mode command is issued. table 36-13 describes smc transp arent rxbd fields. 0123456789101112131415 offset + 0 e ? wi ? cm ?ov? offset + 2 data length offset + 4 rx data buffer pointer offset + 6 figure 36-13. smc transparent rxbd table 36-13. smc transparent rxbd field descriptions bits name description 0 e empty 0 the buffer is full or reception was aborted due to an error. the core can read or write any fields of this rxbd. the cp does not use this bd while e = 0. 1 the buffer is empty or is receiving data. the cp owns this rxbd and its buffer. once e is set, the core should not write any fields of this rxbd. 1 ? reserved, should be cleared. 2 w wrap (last bd in rxbd table) 0 not the last bd in the table 1 last bd in the table. after this bu ffer is used, the cp receives incomi ng data into the first bd that rbase points to. the number of rxbds is determined only by the w bit and overall space constraints of the dual-port ram. 3 i interrupt 0 no interrupt is generated after this buffer is filled. 1 smce[rxb] is set when the cp completely fills this bu ffer indicating that the core must process the buffer. the rxb bit can cause an interrupt if it is enabled. 4?5 ? reserved, should be cleared. 6 cm continuous mode 0 normal operation 1 the cp does not clear e after this bd is closed, a llowing the buffer to be overwritten when the cp next accesses this bd. however, e is cleared if an error occurs during reception, regardless of how cm is set. 7?13 ? reserved, should be cleared. 14 ov overrun. set when a receiver overrun occurs during reception. the cp writes ov after the received data is placed into the buffer. 15 ? reserved, should be cleared. 4 datasheet u .com
serial management controllers (smcs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 36-27 data length and buffer pointer fields are described in section 28.3, ?scc buffer descriptors (bds).? 36.4.9 smc transparent txbd data is sent to the cp for tran smission on an smc channel by arrangi ng it in buffers referenced by the channel txbd table. the cp uses bds to confir m transmission or indicate error conditions so the processor knows buffers have been serviced. table 36-14 describes smc transparent txbd fields. 0123456789101112131415 offset + 0 r ? wi l ? cm ?un? offset + 2 data length offset + 4 tx data buffer pointer offset + 6 figure 36-14. smc transparent txbd table 36-14. smc transparent txbd field descriptions bits name description 0 r ready 0 the buffer is not ready for transmission. the bd and buffer can be updated. the cp clears r after the buffer is sent or after an error occurs. 1 the user-prepared data buffer is not sent or is bei ng sent. bd fields cannot be updated if r is set. 1 ? reserved, should be cleared. 2 w wrap (final bd in table) 0 not the last bd in the table 1 last bd in the table. after this buffer is used, the cp receives incoming data into the first bd that tbase points to. the number of txbds in this table is prog rammable and determined by thew bit and overall space constraints of the dual-port ram. 3 i interrupt 0 no interrupt is generated after this buffer is serviced. 1 smce[txb] or smce[txe] are set when the buffer is serviced. they can cause interrupts if they are enabled. 4 l last in message 0 the last byte in the buffer is not the last byte in the transmitted transparent fr ame. data from the next transmit buffer (if ready) is sent immediat ely after the last byte of this buffer. 1 the last byte in this buffer is the last byte in the tr ansmitted transparent frame. after this buffer is sent, the transmitter requires synchronization before the next buffer is sent. 5 ? reserved, should be cleared. 6 cm continuous mode 0 normal operation 1 the cp does not clear r after this bd is closed, allowi ng the buffer to be automatically resent when the cp accesses this bd again. however, the r bit is cleared if an error occurs during transmission, regardless of how cm is set. 7?13 ? reserved, should be cleared. 4 datasheet u .com
serial management controllers (smcs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 36-28 freescale semiconductor data length represents the number of octets the cp s hould transmit from this buffer. it is never modified by the cp. the data length can be even or odd, but if the number of bits in the transparent character is greater than 8, the data le ngth should be even. for exam ple, to transmit three tr ansparent 8-bit characters, the data length field should be initialized to 3. however, to transmit three transp arent 9-bit characters, the data length field should be initialize d to 6 because the three 9-bit char acters occupy three half words in memory. the data buffer pointer points to the first byte of th e buffer. they can be even or odd, unless character length is greater than 8 bits, in which case the tran smit buffer pointer must be even. for instance, the pointer to 8-bit transparent characters can be even or odd, but the pointer to 9-bit transparent characters must be even. the buffer can reside in internal or external memory. 36.4.10 smc transparent event regi ster (smce)/mask register (smcm) the smc event register (smce) ge nerates interrupts and reports even ts recognized by th e smc channel. when an event is recognized, the smc sets the co rresponding smce bit. interrupts are masked in the smcm, which has the same format as the smce. smce bits are cleared by wr iting a 1 (writing 0 has no effect). unmasked bits must be cl eared before the cp clears the inte rnal interrupt request. the smce and smcm registers are displayed in figure 36-15 . table 36-15 describes smce/smcm fields. 14 um underrun. set when the smc encounters a transmitter underrun condition while sending the buffer. 15 ? reserved, should be cleared. 01234567 field ? txe ? bsy txb rxb reset 0 r/w r/w offset figure 36-15. smc transparent event register (smce)/mask register (smcm) table 36-15. smce/smcm field descriptions bits name description 0?2 ? reserved, should be cleared. 3 txe tx error. set when an underrun error occurs on the transmitter channel. 4 ? reserved, should be cleared. 5 bsy busy condition. set when a character is received and discarded due to a lack of buffers. reception begins after a new buffer is provided. executing an enter hunt mode command makes the receiver wait for resynchronization. table 36-14. smc transparent txbd field descriptions (continued) bits name description 4 datasheet u .com
serial management controllers (smcs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 36-29 36.4.11 smc transparent nmsi programming example the following example initializes the smc1 transpar ent channel over its own set of signals. the clk9 signal supplies the transmit and receive clocks; the smsyn x signal is used for synchronization. (the smc uart programming example uses a brg configuration; see section 36.3.12, ?smc uart controller programming example.? ) 1. configure the port d pins to en able smtxd1, smrxd1, and smsyn1 . set ppard[7,8,9] and pdird[9]. clear pdird[ 7,8] and psord[7,8,9]. 2. configure the port c pins to enable clk9. set pparc[23]. clear pd irc[23] and psorc[23]. 3. connect clk9 to smc1 using the cp m mux. clear cmxsmr[smc1] and program cmxsmr[smc1cs] to 0b11. 4. in address 0x87fc, assign a pointer to the smc1 parameter ram. 5. write rbase and tbase in the smc parameter ram to point to the rxbd and txbd in the dual-port ram. assuming one rxbd at the be ginning of the dual-port ram followed by one txbd, write rbase with 0x0000 and tbase with 0x0008. 6. write 0x1d01_0000 to cpcr to execute the init rx and tx parameters command. 7. write rfcr and tfcr with 0x10 for normal operation. 8. write mrblr with the maxi mum bytes per receive buffer. assuming 16 bytes mrblr = 0x0010. 9. initialize the rxbd assuming the buffer is at 0x0000_1000 in main memory. write 0xb000 to rxbd[status and control], 0x0000 to rxbd [data length] (optional), and 0x0000_1000 to rxbd[buffer pointer]. 10. initialize the txbd assuming the tx buffer is at 0x0000_2000 in main memory and contains five 8-bit characters. write 0xb800 to txbd[status and control], 0x0005 to txbd[data length], and 0x0000_2000 to txbd[buffer pointer]. 11. write 0xff to smce1 to clear any previous events. 12. write 0x13 to smcm1 to enable all possible smc1 interrupts. 13. write 0x0000_1000 to the siu interrupt mask register low (simr_l) so the smc1 can generate a system interrupt. write 0xffff_ffff to the siu in terrupt pending register low (sipnr_l) to clear events. 14. write 0x3830 to the smcmr to c onfigure 8-bit characters, unrev ersed data, and normal operation (not loopback). the transmitter and receiver are not enabled yet. 6 txb tx buffer. set after a buffer is sent. if the l bit of t he txbd is set, txb is set when the last character starts being sent. a one character-time delay is required to ensure that data is completely sent over the transmit signal. if the l bit of the txbd is cleared, txb is set when the last character is wr itten to the transmit fifo. a two character-time delay is required to en sure that data is completely sent. 7 rxb rx buffer. set when a buffer is received (after the last character is written) on the smc channel and its associated rxbd is now closed. table 36-15. smce/smcm field descriptions (continued) bits name description 4 datasheet u .com
serial management controllers (smcs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 36-30 freescale semiconductor 15. write 0x3833 to the smcmr to enable the smc tr ansmitter and receiver. this additional write ensures that ten and ren are enabled last. after 5 bytes are sent, the txbd is closed; after 16 bytes are received the receive buffer is closed. any data received after 16 bytes causes a busy (out-of-buffers) condition sinc e only one rxbd is prepared. 36.5 smc in gci mode the smc can control the c/i and monitor channels of the gci frame. when usi ng the scit configuration of a gci, one smc can handle scit channel 0 and the other can handle sc it channel 1. the main features of the smc in gci mode are as follows: ? each smc channel supports the c/i and mon itor channels of the gci (iom-2) in isdn applications ? two smcs support both sets of c/i and monitor channels in scit channels 0 and 1 ? full-duplex operation ? local loopback and echo capability for testing to use the smc gci channels properly, the tsa must be configured to route the monitor and c/i channels to the preferred smc. chapter 23, ?serial interface with time-slot assigner,? describes how to program this configuration. gci mode is se lected by setting smcmr[sm] to 0b10. section 36.2.1, ?smc mode registers (smcmr1, smcmr2),? describes other protoc ol-specific smcmr bits. 36.5.1 smc gci parameter ram the gci parameter ram differs from that for uart and transparent mode. the cp accesses each smc?s gci parameter table using a user-programmed pointer (smc x _base) located in the parameter ram; see section 21.4.2, ?parameter ram.? each smc gci parameter ram tabl e can be placed at any 64-byte aligned address in the dual-port ram?s general-purpose area (banks 1?8, 11, and 12). in gci mode, parameter ram contains the bds inst ead of pointers to them. compare table 36-16 with table 36-2 to see the differences. (in gci mode, the smc ha s no extra protocol-spe cific parameter ram.) table 36-16. smc gci parameter ram memory map offset 1 name width description 0x00 m_rxbd half word monitor channel rxbd. see section 36.5.5, ?smc gci monitor channel rxbd.? 0x02 m_txbd half word monitor channel txbd. see section 36.5.6, ?smc gci monitor channel txbd.? 0x04 ci_rxbd half word c/i channel rxbd. see section 36.5.7, ?smc gci c/i channel rxbd.? 0x06 ci_txbd half word c/i channel txbd. see section 36.5.8, ?smc gci c/i channel txbd.? 0x08 rstate 2 word rx/tx internal state 0x0c m_rxd 2 half word monitor rx data 0x0e m_txd 2 half word monitor tx data 4 datasheet u .com
serial management controllers (smcs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 36-31 36.5.2 handling the gci monitor channel the following sections describe how the gci monitor channel is handled. 36.5.2.1 smc gci monitor channel transmission process monitor channel 0 is used to exchange data with a layer 1 device (reading and writing internal registers and transferring of the s and q bits). monitor ch annel 1 is used for programming and controlling voice/data modules such as codecs. the core writes the byte into the txbd. the smc sends the data on the monitor channel and handles the a and e c ontrol bits according to the gci monitor channel protocol. the timeout command resolves deadlocks when errors in the a and e bit states occur on the data line. 36.5.2.2 smc gci monitor channel reception process the smc receives data and handles the a and e c ontrol bits according to the gci monitor channel protocol. when the cp stores a received data byte in the smc rxbd, a maskable interrupt is generated. a transmit abort request command causes the MPC8555E to send an abort request on the e bit. 36.5.3 handling the gci c/i channel the c/i channel is used to control the layer-1 devi ce. the layer-2 device in the te sends commands and receives indication to or from the upstream layer-1 device through c/i channel 0. in the scit configuration, c/i channel 1 is used to convey real-time status informat ion between the layer-2 device and non?layer 1 periphera l devices (codecs). 36.5.3.1 smc gci c/i channel transmission process the core writes the data byte into the c/i txbd a nd the smc transmits the data continuously on the c/i channel to the phys ical layer device. 36.5.3.2 smc gci c/i ch annel reception process the smc receiver continuously monitors the c/i channel. when it recognizes a change in the data and this value is received in two suc cessive frames, it is interpreted as vali d data. this is call ed the double last-look method. the cp stores the received da ta byte in the c/i rxbd and a maskab le interrupt is generated. if the smc is configured to support scit channe l 1, the double last-look method is not used. 0x10 ci_rxd 2 half word c/i rx data 0x12 ci_txd 2 half word c/i tx data 1 from the pointer value programmed in smc x _base: smc1_base at 0x87fc, smc2_base at 0x88fc. 2 rstate, m_rxd, m_txd, ci_rxd, and ci_txd do not need to be accessed by the user in normal operation, and are reserved for risc use only. table 36-16. smc gci parameter ram memory map (continued) offset 1 name width description 4 datasheet u .com
serial management controllers (smcs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 36-32 freescale semiconductor 36.5.4 smc gci commands the commands in table 36-17 are issued to the cpcr. 36.5.5 smc gci monitor channel rxbd this bd, seen in figure 36-16 , is used by the cp to report information about th e monitor channel receive byte. table 36-18 describes smc monitor channel rxbd fields. table 36-17. smc gci commands command description init tx and rx parameters initializes transmit and receive parameters in the paramete r ram to their reset state. it is especially useful when switching protocols on a given serial channel. transmit abort request this receiver command can be issued when the MPC8555E implements the monitor channel protocol. when it is issued, the MPC8555E sends an abort request on the a bit. timeout this transmitter command can be issued when the mpc855 5e implements the monitor channel protocol. it is usually issued because the device is not responding or a bit errors are detected. the MPC8555E sends an abort request on the e bit at the time this command is issued. 01234 78 15 offset + 0 e l er ms ?data figure 36-16. smc monitor channel rxbd table 36-18. smc monitor channel rxbd field descriptions bits name description 0 e empty 0 the cp clears e when the byte associated with this bd is available to the core. 1 the core sets e when the byte associated with this bd has been read. 1 l last (eom). valid only for monitor channel protocol and is set when the eom indication is received on the e bit. note that when this bit is set, the data byte is invalid. 2 er error condition. valid only for monitor channel protocol. set when an error occurs on the monitor channel protocol. a new byte is sent before the smc acknowledges the previous byte. 3 ms data mismatch. valid only for monitor channel protocol. set when two different consecutive bytes are received; cleared when the last two consecutive bytes ma tch. the smc waits for the reception of two identical consecutive bytes before writing new data to the rxbd. 4?7 ? reserved, should be cleared. 8?15 data data field. contains the monitor channel data byte that the smc received. 4 datasheet u .com
serial management controllers (smcs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 36-33 36.5.6 smc gci monitor channel txbd the cp uses this bd, shown in figure 36-17 , to report about the monitor channel transmit byte. table 36-19 describes smc monitor channel txbd fields. 36.5.7 smc gci c/i channel rxbd the cp uses this bd, seen in figure 36-18 , to report information about the c/i channel receive byte. table 36-20 describes smc c/i channel rxbd fields. 0123 78 15 offset + 0 r l ar ?data figure 36-17. smc monitor channel txbd table 36-19. smc monitor channel txbd field descriptions bits name description 0 r ready 0 cleared by the cp after transmission. the txbd is now available to the core. 1 set by the core when the data byte associated with this bd is ready for transmission. 1 l last (eom). valid only for monitor channel protocol. w hen l = 1, the smc first transmits the buffer data and then transmits the eom indication on the e bit. 2 ar abort request. valid only for monitor channel protocol . set by the smc when an abort request is received on the a bit. the transmitter sends the eom on the e bit after receiving an abort request. 3?7 ? reserved, should be cleared. 8?15 data data field. contains the data to be sent by the smc on the monitor channel. 01 78 131415 offset + 0 e ? c/i data ? figure 36-18. smc c/i channel rxbd table 36-20. smc c/i channe l rxbd field descriptions bits name description 0 e empty 0 cleared by the cp to indicate that the byte associated with this bd is available to the core. 1 the core sets e to indicate that the byte associated with this bd has been read. note that additional data received is discarded until e bit is set. 1?7 ? reserved, should be cleared. 8?13 c/i data command/indication data bits. for c/i channel 0, bits 10?13 contain the 4-bit data field and bits 8?9 are always written with zeros. for c/i channel 1, bits 8?13 contain the 6-bit data field. 14?15 ? reserved, should be cleared. 4 datasheet u .com
serial management controllers (smcs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 36-34 freescale semiconductor 36.5.8 smc gci c/i channel txbd the cp uses this bd, as seen in figure 36-19 , to report about the c/i channel transmit byte. table 36-21 describes smc c/i channel txbd fields. 36.5.9 smc gci event register (smce)/mask re gister (smcm) the smce generates interrupts and report events r ecognized by the smc channel. when an event is recognized, the smc sets its corresponding smce bit. smce bits are cleared by writing ones; writing zeros has no effect. sm cm has the same bit format as smce. setting an smcm bit enables, and clearing an smcm bit disables , the corresponding interrupt. unmasked bits must be cleared before the cp clears the internal interrupt request to the siu interrupt controller. figure 36-20 displays the smce/smcm registers. table 36-22 describes smce/smcm fields. 0123456789101112131415 offset + 0 r ? c/i data ? figure 36-19. smc c/i channel txbd table 36-21. smc c/i channe l txbd field descriptions bits name description 0 r ready. 0 cleared by the cp after transmission to indi cate that the bd is available to the core 1 set by the core when data associated with this bd is ready for transmission 1?7 ? reserved, should be cleared. 8?13 c/i data command/indication data bits. for c/i channel 0, bits 10?13 hold the 4-bit data field (bits 8 and 9 are always written with zeros). for c/i channel 1, bits 8?13 contain the 6-bit data field. 14?15 ? reserved, should be cleared. 01234567 field ? ctxb crxb mtxb mrxb reset 0000_0000 r/w r/w offset figure 36-20. smc gci event register (smce)/mask register (smcm) table 36-22. smce/smcm field descriptions bits name description 0?3 ? reserved, should be cleared. 4 ctxb c/i channel buffer transmitted. set when the c/i transmit buffer is now empty 5 crxb c/i channel buffer received. set when the c/i receive buffer is full 4 datasheet u .com
serial management controllers (smcs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 36-35 6 mtxb monitor channel buffer transmitted. set when the monitor transmit buffer is now empty 7 mrxb monitor channel buffer received. set when the monitor receive buffer is full table 36-22. smce/smcm field descriptions (continued) bits name description 4 datasheet u .com
serial management controllers (smcs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 36-36 freescale semiconductor 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 37-1 chapter 37 fast communications controllers (fccs) the MPC8555E fast communications controllers (fcc s) are serial communica tions controllers (sccs) optimized for synchronous high-ra te protocols. fcc key feat ures include the following: ? supports hdlc/sdlc and totally transparent protocols ? fcc clocks can be derived from a baud- rate generator or an external signal. ? supports rts , cts , and cd modem control signals ? use of bursts to improve bus usage ? multibuffer data structur e for receive and transmit, external buffer descriptors (bds) anywhere in system memory ? 192-byte fifo buffers ? full-duplex operation ? fully transparent option for one half of an fcc (receiver/transmitter) wh ile hdlc/sdlc protocol executes on the other half (transmitter/receiver) ? echo and local loopback modes for testing ? assuming a 100-mhz cpm clock, th e fccs support the following: ? full 10/100-mbps ethernet/ieee 802.3x standard through an mii or rmii ? full 55-mbps atm segmentation and reasse mbly (sar) through utopia (on fcc1 and fcc2 only) ? 45-mbps (ds-3/e3 rates) hdlc and/or transparent data rates supported on each fcc fccs differ from sccs as follows: ? no dpll support ? no bisync, uart, or appletalk/localtalk support ? no hdlc bus 37.1 overview MPC8555E fccs can be configured i ndependently to implement different protocols. together, they can be used to implement bridging func tions, routers, and gateways, and to interface with a wide variety of standard wans, lans, and proprietary networks. fc cs have many physical interface options such as interfacing to tdm buses, isdn buses , standard modem interfaces, fast ethernet interface (mii), and atm interfaces (utopia); see chapter 23, ?serial interface with time-slot assigner,? and chapter 41, ?atm controller.? the fccs are independent from the physi cal interface, but fcc logic formats and manipulates data from the physical interface. that is why the in terfaces are described separately. 4 datasheet u .com
fast communications controllers (fccs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 37-2 freescale semiconductor the fcc is described in terms of the protocol that it is chosen to run. when an fcc is programmed to a certain protocol, it implements a ce rtain level of functionality associat ed with that protocol. for most protocols, this corresponds to portions of the link layer (layer 2 of the se ven-layer osi model). many functions of the fcc are common to all of the prot ocols. these functions ar e described in the fcc description. following that, the impl ementation details that differentiat e protocols from one another are discussed, beginning with the transpar ent protocol. thus, the reader should read from this point to the transparent protocol and then skip to the appropriate protocol. since th e fccs use similar data structures across all protocols, the reader's learning time decreases dr amatically after understanding the first protocol. each fcc supports a number of protocols?ethern et, hdlc/sdlc, atm, and totally transparent operation. although the selected protocol usually applies to both the fcc tr ansmitter and rece iver, half of one fcc can run transparent operati on while the other runs hdlc/sdlc protocol. the internal clocks (rclk, tclk) for each fcc can be pr ogrammed with either an external or internal source. the internal clocks originate from one of the baud- rate generators or one of the exte rnal clock signals. these clocks can be as fast as one-third th e cpm clock frequency. see chapter 23, ?serial interface with time-slot assigner.? however, the fcc?s ability to support a sustaine d bit stream depends on the protocol as well as on other factors. note this clock ratio is based on the hardwa re architecture and does not ensure that an application will r un at that speed. it is the responsibility of the system designer to check ac specifications of the i/o pins and determine the maximum frequency. each fcc can be connected to its own set of pins on the MPC8555E. this configuration, the nonmultiplexed serial interface, or nmsi, is described in chapter 23, ?serial interface with time-slot assigner.? in this configuration, each fcc can support the standard modem interface signals (rts , cts , and cd ) through the appropriate port pins and the interr upt controller. additiona l handshake signals can be supported with additional parallel i/o li nes. the fcc block diagram is shown in figure 37-1 4 datasheet u .com
fast communications controllers (fccs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 37-3 figure 37-1. fcc block diagram 37.2 general fcc mode registers (gfmr x ) each fcc contains a genera l fcc mode register (gfmr x ) that defines common fc c options and selects the protocol to be run. the gfmr x are read/write registers cleared at reset. figure 37-2 shows the gfmr format. 0123456789 15 field diag tci trx ttx cdp ctsp cds ctss ? reset 0000_0000_0000_0000 r/w r/w offset 0x9_1300 (gfmr1 ), 0x9_1320 (gfmr2) 16 17 18 19 20 21 22 23 24 25 26 27 28 31 field synl rtsm renc revd tenc tcrc enr ent mode reset 0000_0000_0000_0000 r/w r/w offset 0x9_1302 (gfmr1 ), 0x9_1322 (gfmr2) figure 37-2. general fcc mode register (gfmr) control registers shifter shifter delimiter clock generator delimiter decoder encoder receive control unit transmit control unit receive data fifo transmit data fifo modem lines modem lines system bus peripheral bus tclk rclk internal clocks rxd txd 4 datasheet u .com
fast communications controllers (fccs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 37-4 freescale semiconductor table 37-1 describes gfmr fields. table 37-1. gfmr register field descriptions bits name description 0?1 diag diagnostic mode. 00 normal operation?receive data enters through rxd, and transmit data is shift ed out through txd. the fcc uses the modem signals (cd and cts ) to automatically enable and disable transmission and reception. timings are shown in section 37.12, ?fcc timing control.? 01 local loopback mode?transmitter output is connected internally to the receiver input, while the receiver and the transmitter operate normally. rxd is ignored. data can be programmed to appear on txd, or txd can remain high by programming the appropriate parallel port register. rts can be disabled in the appropriate parallel i/o register. the transmitter and receiver must use the same clock source, but separate clk x pins can be used if connected to the same external clock source. if external loopback is preferred, program diag for normal operation and externally connect txd and rxd. then, physically connect the control signals (rts connected to cd , and cts grounded) or set the parallel i/o registers so cd and cts are permanently asserted to the fcc by configuring the associated cts and cd pins as general-purpose i/o.; see chapter 41, ?atm controller.? 10 automatic echo mode?the channel automatically retr ansmits received data, using the receive clock provided. the receiver operates normally and receives data if cd is asserted. the transmitter simply transmits received data. in this mode, cts is ignored. the echo function can also be accomplished in software by receiving buffers from an fcc, linking them to txbds, and transmitting them back out of that fcc. 11 loopback and echo mode?loopback and echo operation occur simultaneously. cd and cts are ignored. refer to the loopback bit description for clocking requirements. for tdm operation, the diagnostic mode is selected by si x mr[sdm x ]; see section 23.6.2, ?si mode registers (si2mr).? 2 tci transmit clock invert 0 normal operation 1 the fcc inverts the internal transmit clock. the edge on which the fcc outputs the data depends on the protocol: ? in hdlc and transparent mode, when tci = 0, data is sent on the falling edge; when tci = 1, on the rising edge. ? in ethernet mode, when tci = 0, data is sent on the rising edge; when tci = 1, on the falling edge. 3 trx transparent receiver. the MPC8555E fccs offer totally transparent operation. however, to increase flexibility, totally transparent operation is configured with the ttx and trx bits instead of the mode bits. this lets the user implement unique applications such as an f cc transmitter configured to hdlc and a receiver configured to totally transparent operation. to do this, program mode = hdlc, ttx = 0, and trx = 1. 0 normal operation 1 the receiver operates in totally transparent mode, regar dless of the protocol selected for the transmitter in the mode bits. note that full-duplex, totally transparent operation for an fcc is obtained by setting both ttx and trx. attempting to operate an fcc with ether net or atm on its transmitter and transparent operation on its receiver causes erratic behavior. in other words, if the mode = ethernet or atm, ttx must equal trx. 4 ttx transparent transmitter. the MPC8555E fccs offer to tally transparent operation. however, to increase flexibility, totally transparent operation is configured wi th the ttx and trx bits instead of the mode bits. this lets the user implement unique applications, such as configuring an fcc receiver to hdlc and a transmitter to totally transparent operation. to do this , program mode = hdlc, ttx = 1, and trx = 0. 0 normal operation 1 the transmitter operates in totally transparent mode, re gardless of the receiver protocol selected in the mode bits. note that full-duplex totally transparent operation fo r an fcc is obtained by setting both ttx and trx. attempting to operate an fcc with ether net or atm on its receiver and transparent operation on its transmitter causes erratic behavior. in other words, if gfmr[mode] selects ethernet or atm, ttx must equal trx. 4 datasheet u .com
fast communications controllers (fccs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 37-5 5 cdp cd pulse (transparent mode only) 0 normal operation (envelope mode). cd should envelope the frame; to negate cd while receiving causes a cd lost error. 1 pulse mode. once cd is asserted (high to low transition), synchronization has been achieved, and further transitions of cd do not affect reception. cdp must be set if this fcc is used with the tsa in transparent mode. 6 ctsp cts pulse 0 normal operation (envelope mode). cts should envelope the frame; to negate cts while transmitting causes a cts lost error. see section 37.12, ?fcc timing control.? 1 pulse mode. cts is asserted when synchronization is achieved; further transitions of cts do not affect transmission. when running hdlc, the fcc samples cts only once before sending the first frame after the transmitter is enabled (ent = 1). 7 cds cd sampling 0 the cd input is assumed to be asynchronous with the data. the fcc synchronizes it internally before data is received. (this mode is not allow ed in transparent mode when synl = 0b00.) 1 the cd input is assumed to be synchronous with the data, giving faster operation. in this mode, cd must transition while the receive clock is in the low state. when cd goes low, data is received. this is useful when connecting MPC8555Es in transparent mode, since it allows the rts signal of one MPC8555E to be connected directly to the cd signal of another MPC8555E. 8 ctss cts sampling 0 the cts input is assumed to be asynchronous with the da ta. when it is internally synchronized by the fcc, data is sent after a delay of no more than two serial clocks. 1 the cts input is assumed to be synchronous with the data , giving faster operation. in this mode, cts must transition while the transmit clock is in the low state. as soon as cts is low, data transmission begins. this mode is useful when connecting MPC8555E in transparent mode, because it allows the rts signal of one MPC8555E to be connected directly to the cts signal of another MPC8555E. 9--15 ? reserved, should be 0. 16?17 synl sync length (transparent mode only). determines the operation of an fcc receiver configured for totally transparent operation only. see section 39.3.1, ?in-line synchronization pattern.? 00 the sync pattern in the fdsr is not used. an external sync signal is used instead (cd signal asserted: high to low transition). 01 automatic sync (assumes always synchronized, ignores cd signal). 10 8-bit sync. the receiver synchronizes on an 8-bi t sync pattern stored in the fdsr. negation of cd causes cd lost error. 11 16-bit sync. the receiver synchronizes on a 16-bi t sync pattern stored in the fdsr. negation of cd causes cd lost error. note that if synl = 1x, cdp should be cleared (not in cd pulse mode). 18 rtsm rts mode 0 send idles between frames as defined by the protocol. rts is negated between frames (default). 1 send flags/syncs between frames according to the protocol. rts is asserted whenever the fcc is enabled. 19?20 renc receiver decoding method. the user should set renc = tenc in most applications. 00 nrz 01 nrzi (one bit mode hdlc or transparent only) 1x reserved table 37-1. gfmr register field descriptions (continued) bits name description 4 datasheet u .com
fast communications controllers (fccs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 37-6 freescale semiconductor 21 revd reverse data (valid for a totally transparent channel only) 0 normal operation 1 the totally transparent channels on this fcc (either the receiver, transmitter, or both, as defined by ttx and trx) reverse bit order, transmitting the msb of each octet first. 22?23 tenc transmitter encoding method. the user should set tenc = renc in most applications. 00 nrz 01 nrzi (one bit mode hdlc or transparent only) 1x reserved 24-25 tcrc transparent crc (totally transparent channel only). selects the type of frame checking provided on the transparent channels of the fcc (either the receiver, tran smitter, or both, as defined by ttx and trx). this configuration selects a frame check type; the decision to send the frame check is made in the txbd. thus, it is not required to send a frame check in transparent mo de. if a frame check is not used, the user can ignore any frame check errors generated on the receiver. 00 16-bit ccitt crc (hdlc). (x16 + x12 + x5 + 1) 01 reserved 10 32-bit ccitt crc (ethernet and hdlc) (x32 + x 26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x1 +1) 11 reserved 26 enr enable receive. enables the receiver hardware state machine for this fcc. 0 the receiver is disabled and any data in the receive fifo buffer is lost. if enr is cleared during reception, the receiver aborts the current character. 1 the receiver is enabled. enr may be set or cleared regardless of whether serial clocks are present. describes how to disable and re-enable an fcc. note that the fcc provides other tools for controlling reception?the enter hunt mode command, close rxbd command, and rxbd[e]. 27 ent enable transmit. enables the transmitter hardware state machine for this fcc. 0 the transmitter is disabled. if ent is cleared during transmission, the transmitter aborts the current character and txd returns to idle state. data in the transmit shift register is not sent. 1 the transmitter is enabled. ent can be set or cleared, regardless of whether serial clocks are present. see section 37.13, ?disabling the fccs on-the-fly,? for a description of the proper methods to disable and re-enable an fcc. note that the fcc provides other tools for controllin g transmission besides the ent bit?the stop transmit , graceful stop transmit , and restart transmit commands, cts flow control, and txbd[r]. 28?31 mode channel protocol mode 0000 hdlc 0001 reserved for ram microcode 0010 reserved 0011 reserved for ram microcode 0100 reserved 0101 reserved for ram microcode 0110 reserved 0111 reserved for ram microcode 1000 reserved 1001 reserved for ram microcode 1010 atm 1011 reserved for ram microcode 1100 ethernet 11xx reserved table 37-1. gfmr register field descriptions (continued) bits name description 4 datasheet u .com
fast communications controllers (fccs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 37-7 37.3 general fcc expansion mode register (gfemr) the general fcc expansion mode register (gfemr) defines the e xpansion modes. it should be programmed according to the protocol used. table 37-2 describes gfemr x fields. 37.4 fcc protocol-specific mode registers (fpsmr x ) the functionality of the fcc varies according to the protocol sele cted by gfmr[mode]. each fcc has an additional 32-bit, memory-mapped, read/write protocol-specific mode register (fpsmr) that configures them specifically for a chosen mode. the section for each specific protocol describes the fpsmr bits. 37.5 fcc data synchronization registers (fdsr x ) each fcc has a 16-bit, memory-ma pped, read/write data synchronizat ion register (fdsr), shown in figure 37-2 , that specifies the pattern used in the fr ame synchronization proce dure of the synchronous protocols. in the totally transparent protocol, the fdsr should be programmed with the preferred sync pattern. for ethernet protocol, it s hould be programmed with 0xd555. at re set, it defaults to 0x7e7e (two hdlc flags), so it does not need to be written for hdlc mode. the fdsr conten ts are always sent lsb first. 0123 7 field tirem lpb clk ? reset 0000_0000 r/w r/w offset 0x9_1390 (gfemr1), 0x9_13b0(gfemr2) figure 37-3. general fcc expansion mode register (gfemr) table 37-2. gfemr x field descriptions bit name description 0 tirem transmit internal rate expanded mode (atm mode) 0 internal rate mode: internal rate for phys[0?3] is controlled only by ftirr[0?3]. firper, firsr_hi, firsr_lo, fiter are unused. 1 internal rate expanded mode: phys[0?31] are controlled by ftirr[0?3], firper, firsr_hi, and firsr_lo. underrun status for phys[0?31] is ava ilable by firer. this bit should be set only in transmit master multi-phy mode. in this mode mixing of internal rate and external rate is not enabled. 1 lpb rmii loopback diagnostic mode (ethernet mode): 0 normal mode 1 loopback mode 2 clk rmii reference clock rate for 50-mhz input clock from external oscillator (ethernet mode): 0 50 mhz (for fast ethernet) 1 5 mhz (for 10baset) 3?7 ? reserved, should be cleared. 4 datasheet u .com
fast communications controllers (fccs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 37-8 freescale semiconductor 37.6 fcc transmit-on-demand registers (ftodr x ) if no frame is being sent by the fcc, the cp periodically polls the r bit of the next txbd to see if the user has requested a new frame/buffer to be sent. the polling algorithm de pends on the fcc configuration, but occurs every 256 serial transmit cl ocks. the user, however, can request that the cp begin processing the new frame/buffer without waiting the normal polling time. for immediate processing, set the transmit-on-demand (tod) bit in the transmit-on-demand re gister (ftodr), shown in figure 37-5 , after setting txbd[r]. this feature, which decreases the transmission latency of the transmit buffer/frame, is particularly useful in lan-type protocols where maximum interframe gap times are limited by th e protocol specification. since the transmit-on-demand f eature gives a high priority to the spec ified txbd, it can conceivably affect the servicing of the other fcc fifo buffers. therefor e, it is recommended that the transmit-on-demand feature be used only for a high-prio rity txbd and when transmission on this fcc has not occurred for a given time period, which is protocol-dependent. if a new txbd is added to the bd table while preceding txbds have not completed transmission, the new txbd is processed immediately after the older txbds are sent. fields in the ftodr are described in table 37-3 . 07815 field syn2 syn1 reset0111111001111110 r/w r/w address 0x9_130c (fdsr1), 0x9_132c (fdsr2) figure 37-4. fcc data synchronization register (fdsr) 01 15 field tod ? reset 0000_0000_0000_0000 r/w r/w offset 0x9_1308 (ftodr1), 0x9_1328 (ftodr2) figure 37-5. fcc transmit-on- demand register (ftodr) table 37-3. ftodr field descriptions field name description 0 tod transmit on demand 0 normal polling 1 the cp gives high priority to the current txbd and begins sending the frame does without waiting for the normal polling time to check txbd[r]. tod is cleared automatically. 1?15 ? reserved, should be cleared. 4 datasheet u .com
fast communications controllers (fccs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 37-9 37.7 fcc buffer descriptors data associated with each fcc is st ored in buffers. each buffer is refe renced by a buffer descriptor (bd). all of the transmit bds for an fcc are grouped into a txbd circular table with a programmable length. likewise, receive bds form an rxbd table. the user can program the start address of the bd tables anywhere in system memory. see figure 37-6 . figure 37-6. fcc memory structure the format of transmit and receive bds, shown in figure 37-7 , is the same for every fcc mode of operation except atm mode; see section 41.10.5, ?atm controller buffer descriptors (bds).? the first 16 bits in each bd contain status and control information, which di ffers for each protocol. the second 16 bits indicate the data buffe r length in bytes (the wrap bit is the bd table lengt h indicator). the remaining 32 bits contain the 32-bit address pointer to the act ual buffer in memory. for frame-based protocols, a message can reside in as many buffers as necessary (transmit or receive). each buffer has a maximum length of (64k?1) bytes. the cp doe s not assume that al l buffers of a single frame are currently linked to the bd table. it does assume , however, that unlinked buffers are provided by the core soon enough to be sent or received. failure to do so causes an error condition being reported by 0 15 offset + 0 status and control offset + 2 data length offset + 4 high-order data buffer pointer offset + 6 low-order data buffer pointer figure 37-7. buffer descriptor format rx buffer status and control data length buffer pointer fccx txbd table fccx rxbd table fccx rxbd ta b l e fccx txbd ta b l e system memory status and control data length buffer pointer tx buffer dual-port ram rx buffer descriptors tx buffer descriptors pointer (rbase) pointer (tbase) 4 datasheet u .com
fast communications controllers (fccs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 37-10 freescale semiconductor the cp. an underrun error is reported in the case of transmit; a busy error is reported in the case of receive. because bds are prefetched, the receive bd table must always contain at least one empty bd to avoid a busy error; therefore, rxbd tables must always have at least two bds. the bds and data buffers can be anywhere in the system memory. the cp processes the txbds in a stra ightforward fashion. once the transmit side of an fcc is enabled, it starts with the first bd in that fcc?s txbd table. when the cp detects that txbd[r] is set, it begins processing the buffer. the cp detects that the bd is ready either by polling the r bit periodically or by the user writing to the ftodr. when the data from the bd has been placed in the transmit fifo buffer, the cp moves on to the next bd, again waiting for the r bit to be set. thus, the cp does no look-ahead bd processing, nor does it skip over bds that are not ready. when the cp sees the wrap (w) bit set in a bd, it goes back to the beginning of the bd tabl e after processing of the bd is complete. after using a bd, the cp nor mally clears r (not-ready); thus, the cp does not use a bd ag ain until the bd has been prepared by the core. some protocols support continuous mode, which allows repeated transmission and for which the r bit remains set (always ready). the cp uses rxbds in a simil ar fashion. once the receive si de of an fcc is enabled, it starts with the first bd in the fcc?s rxbd table. once data arrives from the serial line into the fcc, the cp performs the required protocol processing on the data and moves the resultant data to the buffer pointed to by the first bd. use of a bd is complete when no room is left in the buffer or when certain events occur, such as the detection of an error or e nd-of-frame. regardless of the reason, the buffer is then said to be closed and additional data is stored using the next bd. whenever the cp needs to begin us ing a bd because new data is arriving, it checks the e bit of that bd. this check is made on a prefetched copy of the current bd. if the current bd is not empty, it reports a busy error. however, it does not move from the current bd until it is empty. because there is a periodic prefetch of the rxbd, the busy error may recur if the bd is not prepared soon enough. when the cp sees the w bit set in a bd, it returns to the be ginning of the bd table after processing of the bd is complete. after using a bd, the cp clears the e bit (not empty) and does not use a bd again until the bd has been processed by the core. however, in continuous mode, available to some protocols, the e bit remains set (always empty). 37.8 fcc parameter ram each fcc parameter ram area begins at the same offset from each fcc base area. the protocol-specific portions of the fcc parameter ram are discussed in the speci fic protocol descriptions. table 37-4 shows portions common to all fcc protocols. some parameter ram values must be initialized before the fcc is enabled; other values are initialized/written by the cp. once in itialized, most parameter ram valu es do not need to be accessed by user software because most activity centers around th e txbds and rxbds rather than the parameter ram. however, if the parameter ram is accessed, note the following: ? parameter ram can be read at any time. ? tx parameter ram can be wr itten only when the transmitt er is disabled?after a stop transmit command and before a restart transmit command or after the buffer/frame finishes 4 datasheet u .com
fast communications controllers (fccs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 37-11 transmitting after a graceful stop transmit command and before a restart transmit command. ? rx parameter ram can be written only when the receiver is disabled. note the close rxbd command does not stop reception, but it does allow the user to extract data fro m a partially full rx buffer. ?see section 37.13, ?disabling the fccs on-the-fly.? some parameters in table 37-4 are not described and are listed only to provide information for experienced users and for debugging. the user need not access these paramete rs in normal operation. table 37-4. fcc parameter ram common to all protocols except atm offset 1 name width description 0x00 riptr hword receive internal temporary data pointer. us ed by microcode as a temporary buffer for data. user to specify only the lowest 16 bits of the dpra m address offset calculated from the value in ccsrbar. must be 32-byte aligned and the size of the internal buffer must be 32 bytes, unless it is stated otherwise in the protocol specification. 0x02 tiptr hword transmit internal temporary data pointer. used by microcode as a temporary buffer for data. user to specify only the lowest 16 bits of the dpra m address offset calculated from the value in ccsrbar. must be 32-byte aligned and the size of the internal buffer must be 32 bytes, unless it is stated otherwise in the protocol specification. 0x04 ? hword reserved, should be cleared. 0x06 mrblr hword maximum receive buffer length (a multiple of 32 for all modes). the num ber of bytes that the fcc receiver writes to a receive buffer before moving to the next buffer. the receiver can write fewer bytes to the buffer than mrblr if a condition such as an error or end-of-frame occurs, but it never exceeds the mrblr value. therefore, user-suppli ed buffers should be at least as large as the mrblr. note that fcc transmit buffers can have varyin g lengths by programming txbd[data length], as needed, and are not affected by the value in mrblr. mrblr is not intended to be changed dynamically while an fcc is operating. change mrblr only when the fcc receiver is disabled. 0x08 rstate word receive internal state. the high byte, rs tate[0?7], contains the f unction code register; see section 37.8.1, ?fcc function code registers (fcrx).? rstate[8?31] is used by the cp and must be cleared initially. 0x0c rbase word rxbd base address (must be divisible by ei ght). defines the st arting location in the memory map for the fcc rxbds. this provides great flex ibility in how fcc rxbds are partitioned. by selecting rbase entries for both f ccs and by setting the w bit in the last bd in each bd table, the user can select how many bds to allocate fo r the receive side of every fcc. the user must initialize rbase before enabling the corresponding channel. furthermore, the user should not configure bd tables of two enabled fccs to overlap or erratic operation occurs. 0x10 rbdstat hword rxbd status and control. reserved for cp use only. 0x12 rbdlen hword rxbd data length. a down-count value in itialized by the cp with mrblr and decremented with every byte written by the sdma channels. 0x14 rdptr word rxbd data pointer. updated by the sdma channels to show the next address in the buffer to be accessed. 0x18 tstate word tx internal state. the high byte, tstate[0?7], contains the function code register; see section 37.8.1, ?fcc function code registers (fcrx).? tstate[8?31] is used by the cp and must be cleared initially. 4 datasheet u .com
fast communications controllers (fccs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 37-12 freescale semiconductor 37.8.1 fcc function code registers (fcr x ) the function code registers contain the transaction specification associ ated with sdma channel accesses to external memory. figure 37-8 shows the format of the transmit a nd receive function code registers, which reside at tstate[0?7] and rs tate[0?7] in the fcc parameter ram. 0x1c tbase word txbd base address (must be divisible by eigh t). defines the starting loca tion in the memory map for the fcc txbds. this provides great flexibilit y in how fcc txbds are partitioned. by selecting tbase entries for both fccs and by setting the w bit in the last bd in each bd table, the user can select how many bds to allocate for the transm it side of every fcc. the user must initialize tbase before enabling the corresponding channel. furthermore, the user should not configure bd tables of two enabled fccs to overlap or erratic operation occurs. 0x20 tbdstat hword txbd status and control. reserved for cp use only. 0x22 tbdlen hword txbd data length. a down-count value initialized with the txbd data length and decremented with every byte read by the sdma channels. 0x24 tdptr word txbd data pointer. updated by the sdma chan nels to show the next address in the buffer to be accessed. 0x28 rbptr word rxbd pointer. points to the next bd that the receiver transfers data to when it is in idle state or to the current bd during frame processing. after a reset or when the end of the bd table is reached, the cp sets rbptr = rbase. although th e user need never write to rbptr in most applications, the user can modify it when the receiv er is disabled or when no receive buffer is in use. 0x2c tbptr word txbd pointer. points either to the next bd that the transmitter transfers data from when it is in idle state or to the current bd during frame transmission. after a reset or when the end of the bd table is reached, the cp sets tbptr = tbase. although the user need never write to tbptr in most applications, the user can modify it when the transmitter is disabled or when no transmit buffer is in use (after a stop transmit or graceful stop transmit command is issued and the frame completes transmission). 0x30 rcrc word temporary receive crc 0x34 ? word reserved 0x38 tcrc word temporary transmit crc 0x3c ? word first word of protocol-specific area 1 offset from fcc base: 0x8400 (fcc1), 0x8500 (fcc2); see section 21.4.2, ?parameter ram.? 01234567 field ? fccp gbl bo ? dtb bdb figure 37-8. function code register (fcr x ) table 37-4. fcc parameter ram common to all protocols except atm (continued) offset 1 name width description 4 datasheet u .com
fast communications controllers (fccs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 37-13 fcr x fields are described in table 37-5 . 37.9 interrupts from the fccs interrupt handling for each of the fcc channels is configured on a global (per channel) basis in the interrupt pending register (sipnr_l) and interrupt mask regi ster (simr_l). one bit in each register is used to either mask, enable, or re port an interrupt in an fcc channel. the interrupt priority between the fccs is programmable in the cpm in terrupt priority register (scprr_h ). the interrupt vector register (sivec) indicates which pending channel has highest priority. registers within the fccs manage interrupt handling for fcc-specific events. events that can cause the fcc to interrupt the processor vary slight ly among protocols and are described with each protocol. these events are handled independently for each channel by the fcc event and mask registers (fcce and fccm). 37.9.1 fcc event registers (fcce x ) each fcc has an fcc event register (fcce) used to report events. on recognition of an event, the fcc sets its corresponding fcce bit regard less of the corresponding mask bit. to the user it appears as a memory-mapped register that can be read at any time. bits are cleare d by writing ones; writing zeros has no effect on bit values. fcce is cleared at reset. fiel ds of this register are protocol-dependent and are described in the respecti ve protocol sections. table 37-5. fcr x field descriptions bits name description 0 ? reserved, should be cleared. 1 fccp fcc priority 0 disables cpm low request level to refer to fccs 1 enables cpm low request level to refer to fccs 2 gbl global. indicates whether the memory operation should be snooped 0 snooping disabled 1 snooping enabled 3?4 bo byte ordering.used to select the byte ordering of the buffer. if bo is modified on-the-fly, it takes effect at the start of the next frame (ethernet, hdlc, and trans parent) or at the beginning of the next bd. 0x reserved 10 1x big endian 5 ? reserved, should be cleared. 6 dtb indicates on what bus the data is located 0 on the system bus 1 on the local bus 7 bdb indicates on what bus the bds are located 0 on the system bus 1 on the local bus 4 datasheet u .com
fast communications controllers (fccs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 37-14 freescale semiconductor 37.9.2 fcc mask registers (fccm x ) each fcc has a read/write fcc mask register (fccm) us ed to enable or disable cp interrupts to the core for events reported in an event register (fcce). bit positions in fccm are identical to those in fcce. note that an interrupt is genera ted only if the fcc interrupts are also enabled in the cpm interrupt controller; see section 22.5.1.4, ?cpm interrupt mask registers (simr_h, simr_l).? if an fccm bit is zero, the cp does not proceed wi th its usual interrupt handling whenever that event occurs. any time a bit in the fccm register is set, a 1 in the corresponding bit in the fcce register sets the fcc event bit in the in terrupt pending register; see section 22.5.1.4, ?cpm interrupt mask registers (simr_h, simr_l).? 37.9.3 fcc status registers (fccs x ) each fcc has an 8-bit, read/write fc c status register (fccs) that lets the user monitor real-time status conditions (flags, idle) on the rxd line. it does not show the status of cts and cd ; their real-t ime status is available in the appropria te parallel i/o port. (see chapter 45, ?parallel i/o ports.? ) 37.10 fcc initialization the fccs require a number of regist ers and parameters to be configured after a power-on reset. the following outline gives the proper sequence for initializing the fccs, regardless of the protocol used. 1. write the parallel i/o ports to configur e and connect the i/o pins to the fccs. 2. write the appropriate port registers to configure cts and cd to be parallel i/o with interrupt capability or to connect directly to the fcc (if modem support is needed). 3. if the tsa is used, the si must be configure d. if the fcc is used in the nmsi mode, the cpm multiplexing logic (cmx) mu st still be initialized. 4. write the gfmr, but do not wr ite the ent or enr bits yet. 5. write the fpsmr. 6. write the fdsr. 7. initialize the required values for this fcc in its parameter ram. 8. clear out any current events in fcce, as needed. 9. write the fccm register to enable the interrupts in the fcce register. 10. write the scprr_h to configure the fcc interrupt priority. 11. clear out any current interrupts in the sipnr_l, if preferred. 12. write the simr_l to enable interrupts to the cp interrupt controller. 13. issue an init tx and rx parameters command (with the correct protocol number). 14. set gfmr[ent] and gfmr[enr]. the first rxbd?s empty bit must be set before the init rx command . however, txbds can have their ready bits set at any time. notice that the cpcr does not need to be accessed after a power-on reset until an fcc is to be used. an fcc shoul d be disabled and re-ena bled after any dynamic change in its parallel i/o ports or serial channel physical interface c onfiguration. a full reset using cpcr[rst] is a comprehensive reset that also can be used. 4 datasheet u .com
fast communications controllers (fccs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 37-15 37.11 fcc interrupt handling the following describes what usually oc curs within an fcc interrupt handler: 1. when an interrupt occurs, read fcce to determin e interrupt sources. fcce bits to be handled in this interrupt handler are norm ally cleared at this time. 2. process the txbds to reuse them if the fcce[tx,tx e] were set. if the transmit speed is fast or the interrupt delay is long, more than one transmit buffer may have been sent by the fcc. thus, it is important to check more than just one txbd during the interrupt ha ndler. one common practice is to process all txbds in the interrupt handler until one is found with r set. 3. extract data from the rxbd if fcce[rx, rxb, or rxf] is set. if the receive speed is fast or the interrupt delay is long, the fcc ma y have received more than one receive buffer. thus, it is important to check more than ju st one rxbd during interrupt handl ing. typically, all rxbds in the interrupt handler are processed un til one is found with e set. because the fcc prefetches bds, the bd table must be big enough such that always there will be another empty bd to prefetch. 4. clear fcce. 5. continue normal execution. 37.11.1 fcc transmit errors there are four errors in the fcc transmitter that make it necessary for software to act on the transmitter before correct operation can conti nue. the errors are as follows: ? cts-lost indication in hdlc transmit ter (use re-initial ization procedure) ? underrun in any of the serial fcc transmitte r protocols (use re-ini tialization procedure) ? late collision in fast ethernet transmitter (use recovery or re-i nitialization procedure) ? expiration of retry limit in fast ethernet (use recovery or re-i nitialization procedure) in addition to status bits in the current txbd, thes e errors are reported through the txe event bit in the fcce as a convenience for the user to implement error handling. txe is a safe indication that a recovery or re-initialization pro cedure must be started. 37.11.1.1 re-initialization procedure 1. disable the fcc transmi ssion by clearing gfmr[ent]. 2. remember the tbptr value take n from the fcc parameter ram. 3. issue an ?init tx params? command using the cpcr. 4. restore the remembered tbpt r into the fcc parameter ram. 5. adjust txbd handling as described in section section 37.11.1.3, ?adjusting transmitter bd handling.? 6. enable fcc transmission by setting gfmr[ent]. 4 datasheet u .com
fast communications controllers (fccs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 37-16 freescale semiconductor 37.11.1.2 recovery sequence 1. adjust txbd handling as described in section section 37.11.1.3, ?adjusting transmitter bd handling.? 2. issue a ?restart tx? command using the cpcr. 37.11.1.3 adjusting transmitter bd handling when a txe event occurs, the tbptr may already point beyond bd s still marked as ready due to internal pipelining. if the tbptr is not adjusted, these bds w ould be skipped while still being marked as ready. software must determine if these bds should be retr ansmitted or if they should be skipped, depending on the protocol and application needs. this requires the following steps: 1. from the current tbptr value, search backwards over all (if any) bds still marked as ready to find the first bd that has not been closed by the cpm. the search process should stop if the bd to be checked next is not ready or if it is the mo st recent bd marked as ready by the cpu transmit software. this is to avoid an endless loop in cas e the cpu software fills the bd ring completely. 2. a) for skipping bds, manually close all bds from the bd just found up to and including the bd just before tbptr. leave the tbptr value untouched. b) for retransmitting bds, change the tb ptr value to point to the bd just found. 37.12 fcc timing control when gfmr[diag] is program med to normal operation, cd and cts are automatically controlled by the fcc. gfmr[tci] is assumed to be cleared, which implies normal tr ansmit clock operation. rts is asserted when fcc has data to transmit in th e transmit fifo and a fall ing transmit clock occurs. at this point, the fcc begins sending the data, once the appropr iate conditions occur on cts . in all cases, the first bit of data is the start of the opening flag, or sync pattern. figure 37-9 shows that the delay between rts and data is 0 bit times, regardless of the setting of gfmr[ctss]. this opera tion assumes that cts is either already asserted to the fcc or is reprogrammed to be a parallel i/o line, in which case the cts signal to the fcc is always asserted. rts is negated one clock after the last bit in the frame. figure 37-9. output delay from rts asserted 1. a frame includes opening and closing flags and syncs, if present in the protocol. tclk txd last bit of frame data first bit of frame data note: (output) rts (output) cts (input) 4 datasheet u .com
fast communications controllers (fccs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 37-17 if cts is not already asserted when rts is asserted, the delays to the fi rst bit of data depend on when cts is asserted. figure 37-10 shows that the delay between cts and the data can be approximately 0.5 to 1 bit-times or no delay, depending on gfmr[ctss]. figure 37-10. output delay from cts asserted if it is programmed to envelope the data, cts must remain asserted duri ng frame transmission or a cts lost error occurs. the negation of cts forces rts high and the transmit data to the idle state. if gfmr[ctss] = 0, the fcc must sample cts before a cts lost is recognized. otherwise, the negation of cts immediately causes the cts lost condition. see figure 37-11 . 1. gfmr[ctss] = 0. ctsp is a don?t care. tclk txd last bit of frame data first bit of frame data note: cts sampled low 1. gfmr[ctss] = 1. ctsp is a don?t care. tclk txd last bit of frame data first bit of frame data note: (output) rts (output) cts (input) (output) rts (output) cts (input) 4 datasheet u .com
fast communications controllers (fccs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 37-18 freescale semiconductor figure 37-11. cts lost note note that if gfmr[ctss] = 1, all cts transitions must occur while the transmit clock is low. reception delays ar e determined by cd as figure 37-12 shows. if gfmr[cds] = 0, cd is sampled on the rising receive clock edge before data is received. if gfmr[cds] = 1, cd transitions immediately cause data to be gated into the receiver. 1. gfmr[ctss] = 0. ctsp = 0 or no cts lost can occur. tclk txd first bit of frame data note: cts sampled low 1. gfmr[ctss] = 1. ctsp = 0 or no cts lost can occur. tclk first bit of frame data note: cts sampled high data forced high rts forced high data forced high rts forced high cts lost signaled in bd cts lost signaled in bd (output) rts (output) cts (input) cts (input) rts (output) txd (output) 4 datasheet u .com
fast communications controllers (fccs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 37-19 figure 37-12. using cd to control reception if it is programmed to envelope data, cd must remain asserted duri ng frame transmission or a cd lost error occurs. the negation of cd terminates reception. if [cds] = 0, cd must be sampled by the fcc before a cd lost is recognized. othe rwise, the ne gation of cd immediately causes the cd lost condition. note that if gfmr[cds] = 1, all cd transitions must occur while the receive clock is low. 37.13 disabling the fccs on-the-fly unused fccs can be tempor arily disabled. in this cas e, a operation sequence is fo llowed that ensures that any buffers in use are closed properly and that new da ta is transferred to or from a new buffer. such a sequence is required if the parameters that must be changed are not allowed to be changed dynamically. if the register or bit description st ates that dynamic changes are allowe d, the following sequences are not required and the register or bit ma y be changed immediately. in all other cases, the sequence should be used. modifying parameter ram does not require the fcc to be fully disabled. see the parameter ram description for when values can be changed. to disable all peripheral c ontrollers, set cpcr[rst] to reset the entire cpm. 1. gfmr[cds] = 0. cdp = 0. rclk first bit of frame data notes: cd sampled low rclk cd sampled high last bit of frame data 2. if cd is negated prior to the last bit of the receive frame, cd lost is signaled in the bd. 3. if cdp = 1, cd lost cannot occur and cd negation has no effect on reception. 1. gfmr[cds] = 1. cdp = 0. notes: 2. if cd is negated prior to the last bit of the receive frame, cd lost is signaled in the bd. 3. if cdp = 1, cd lost cannot occur and cd negation has no effect on reception. last bit of frame data first bit of frame data cd assertion immediately gates reception cd negation immediately halts reception rxd (input) cd (input) cd (input) rxd (input) 4 datasheet u .com
fast communications controllers (fccs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 37-20 freescale semiconductor 37.13.1 fcc transmitter full sequence for the fcc transmitter, the full disable and enable sequence is as follows. 1. issue the stop transmit command. this is recommended if the fcc is currently transmitting data because it stops transmission in an orderly way. if the fcc is not transmitting (no txbds are ready or the graceful stop transmit command has been issued and completed), then the stop transmit command is not required. furt hermore, if the tbptr is ove rwritten by the user or the init tx parameters command is executed, this command is not required. 2. clear gfmr[ent]. this disables the f cc transmitter and puts it in a reset state. 3. make changes. the user can m odify fcc transmit parameters, including the parameter ram. to switch protocols or restore the fcc transmit parameters to their initial state, the init tx parameters command must be issued. 4. if an init tx parameters command was not issued in step 3, issue a restart transmit command. 5. set gfmr[ent]. transmission begins using th e txbd that the tbptr points to as soon as txbd[r] = 1. 37.13.2 fcc transmitter shortcut sequence a shorter sequence is possible if the us er prefers to reinitialize the transm it parameters to the state they had after reset. this sequence is as follows: 1. clear gfmr[ent]. 2. issue the init tx parameters command. any additional changes can be made now. 3. set gfmr[ent]. 37.13.3 fcc receiver full sequence the full disable and enable sequenc e for the receiver is as follows: 1. clear gfmr[enr]. reception is a borted immediately, which disables the receiver of the fcc and puts it in a reset state. 2. make changes. the user can modify the fcc receive parameters, incl uding the parameter ram. if the user prefers to switch protocols or restore the fcc receive parameters to their initial state, the init rx parameters command must be issued. 3. issue the enter hunt mode command. this command is required if the init rx parameters command was not issued in step 2. 4. set gfmr[enr]. reception begins immediately using the rxbd that the rbptr points to if rxbd[e] = 1. 37.13.4 fcc receiver shortcut sequence a shorter sequence is possible if the user prefers to re initialize the receive paramete rs to the state they had after reset. this sequence is as follows: 1. clear gfmr[enr]. 4 datasheet u .com
fast communications controllers (fccs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 37-21 2. issue the init rx parameters command. any additional changes can be made now. 3. set gfmr[enr]. 37.13.5 switching protocols a user can switch the protocol that the fcc is executing (hdlc) without resetting the board or affecting any other fcc by taking the following steps: 1. clear gfmr[ent] and gfmr[enr]. 2. issue the init tx and rx parameters command. this command initializes both transmit and receive parameters. additional changes can be made in the gfmr to change the protocol. 3. set gfmr[ent] and gfmr[enr]. the fc c is enabled with the new protocol. 37.14 saving power clearing an fcc?s ent and enr bits minimizes its power consumption. 4 datasheet u .com
fast communications controllers (fccs) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 37-22 freescale semiconductor 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 38-1 chapter 38 fcc hdlc controller layer 2 of the seven-layer osi mode l is the data link layer (dll), in which hdlc is one of the most common protocols. the framing structure of hdlc is shown in figure 38-1 . hdlc uses a zero insertion/deletion process (commonly know n as bit stuffing) to ensure that the bit pattern of the delimiter flag does not occur in the fields between flags. the hdlc frame is synchronous and therefore relies on the physical layer for a method of clocking a nd of synchronizing the transmitter/receiver. because the layer 2 frame can be transmitted ove r a point-to-point link, a broadcast network, or a packet-and-circuit switched system, an address field is needed for th e frame's destination address. the length of this field is commonly 0, 8, or 16 bits, de pending on the data link laye r protocol. for instance, sdlc and lapb use an 8-bit address and ss#7 has no address field because it is used always in point-to-point signaling links. lapd further divides its 16-bit addr ess into different fields to specify various access points within one device. it also defi nes a broadcast address. some hdlc-type protocols also permit extended addressing beyond 16 bits. the 8- or 16-bit control fi eld provides a flow-control number and defines the frame type (control or data). the exact use and structure of this field depends upon th e protocol using the frame. data is transmitted in the data field, which can va ry in length depending upon the protocol usi ng the frame. layer 3 frames are carried in this data field. error control is implemented by a ppending a cyclic redundancy check (crc ) to the frame, which in most protocols is 16-bits long but can be as long as 32-bits. in hdlc, the lsb of each octet is transmitted first and the msb of the crc is transmitted first. when gfmr[mode] selects hdlc mode, that fcc functions as an hdlc controller. when an fcc in hdlc mode is used with a nonmultiplexed modem in terface, the fcc outputs are connected directly to the external pins. modem signals can be supported through the appropriate port pins. the receive and transmit clocks can be supplied ei ther externally or from the bank of baud-rate generators. the hdlc controller can also be conne cted to one of the tdm channels of the serial interface and used with the tsa. the hdlc controller consists of separate transmit and receive sections whose operations are asynchronous with the core and can either be synchr onous or asynchronous with other fccs. the user can allocate external buffer de scriptors (bds) for receive and transmit tasks so many frames can be sent or received without core intervention. 38.1 key features key features of the hdlc include the following: ? flexible data buffers with multiple buffers per frame ? separate interrupts for frames and buffers (receive and transmit) ? received frames threshold to reduce interrupt overhead 4 datasheet u .com
fcc hdlc controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 38-2 freescale semiconductor ? four address comparison registers with masks ? maintenance of four 16-bit error counters ? flag/abort/idle generation and detection ? zero insertion/deletion ? 16- or 32-bit crc-cci tt generation/checking ? detection of nonocte t-aligned frames ? detection of frames that are too long ? programmable flags (0?15) between successive frames ? external bd table ? up to t3 rate ? support of time stamp mode for rx frames ? support of nibble mode hdlc (4 bits per clocks) 38.2 hdlc channel frame transmission processing the hdlc transmitter is designed to work with almost no core intervention. when the core enables a transmitter, it starts sending flag s or idles as programmed in the hdlc mode register (fpsmr). the hdlc controller polls the first bd in the transmit channel bd table. wh en there is a frame to transmit, the hdlc controller fetches the data (address, contro l, and information) from the first buffer and begins sending the frame after first inserti ng the user-specified minimum numbe r of flags between frames. when the end of the current buffer is reached and txbd[l] (last buffer in frame) is set, the fcc appends the crc (if selected) and closing flag. in hdlc, the lsb of each octet and the msb of the crc are sent first. figure 38-1 shows a typical hdlc frame. figure 38-1. hdlc framing structure after the closing flag is sent, the hdlc controller writes the frame status bits into the bd and clears the r bit. when the end of the current bd is reached a nd the l (last) bit is not set (working in multibuffer mode), only the r bit is cleared. in ei ther mode, an interrupt can be issued if the i bit in the txbd is set. the hdlc controller then proceeds to the next txbd in the table. in this way, the core can be interrupted after each buffer, after a specific buffer, af ter each frame, or after a number of frames. to rearrange the transmit queue before the cp has sent all buffers, issue the stop transmit command. this can be useful for sending expedited data before pr eviously linked buffers or for error situations. when receiving the stop transmit command, the hdlc controller aborts the current frame transmission and starts transmitting idles or flags. when the hdlc controller is given the restart transmit command, it resumes transmission. to insert a high-priority frame without aborting the current frame, the graceful stop transmit command can be issued. a special interrupt (g ra) can be gene rated in the event register when the current frame is complete. opening flag address control information (optional) crc closing flag 8 bits 16 bits 8 bits 8 n bits 16 bits 8 bits 4 datasheet u .com
fcc hdlc controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 38-3 38.3 hdlc channel frame reception processing the hdlc receiver is designed to work with almo st no core intervention and can perform address recognition, crc checking, and maximu m frame length checking. the receive d frame is available for any hdlc-based protocol. when the core enables a receiver, the receiver waits for an opening flag character. when it detects the first byte of the frame, the hd lc controller compares the frame address against the user-programmable addresses. the user has four 16-bit addres s registers and an address mask available for address matching. the hdlc controller compares the received address field to the user-defined values after masking with the address mask. the hdlc contro ller can also detect broa dcast (all ones) address frames if one address regist er is written with all ones. if a match is detected, the hdlc controller checks the pref etched bd; if it is empty, it starts transferring the incoming frame to the bd?s associated buffer. wh en the buffer is full, the hdlc controller clears bd[e] and generates an interrupt if bd[i] = 1. if the incoming frame is larger than the buffer, the hdlc controller fetches the next bd in the table and, if it is empty, continues tr ansferring the frame to the associated buffer. during this process, the hdlc controller checks for fr ames that are too long. when the frame ends, the crc field is checked against the recalculated value a nd written to the buffer. th e data length written to the last bd in the hdlc frame is the length of the entire frame. this enables hdlc protocols that lose frames to correctly recogni ze a frame-too-long condition. the hdlc controller then sets the last buffer in frame bit, writes the frame stat us bits into the bd, and clears the e bit and fetches the next bd. the hdlc controller then generates a maskable interrupt, indicating that a fram e was received and is in memo ry. the hdlc controller th en waits for a new frame. back-to-back frames can be received separated only by a single shared flag. the user can configure the hdlc cont roller not to interrupt the core until a specified number of frames have been received. this is configured in the recei ved frames threshold (rfthr) location of the parameter ram. this function can be combined with a timer to implement a time-out if fewer than the threshold number of frames are received. 38.4 hdlc parameter ram when an fcc operates in hdlc mo de, the protocol-specific area of the fcc parameter ram is mapped with the hdlc-specific parameters in table 38-1 . table 38-1. fcc hdlc-specific parameter ram memory map offset 1 name 2 width description 0x3c ? 2 words reserved 0x44 c_mask word crc constant. for the 16-bit crc-ccitt, initialize c_mask to 0x0000_f0b8. fo r the 32-bit crc-ccitt, initialize c_mask to 0xdebb_20e3. 0x48 c_pres word crc preset. for the 16-bit crc-ccitt, init ialize c_pres to 0x0000_ffff. for the 32-bit crc-ccitt, initialize c_ pres to 0xffff_ffff. 0x4c disfc 3 hword discard frame counter. counts error-fr ee frames discarded due to lack of buffers. 4 datasheet u .com
fcc hdlc controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 38-4 freescale semiconductor 0x4e crcec 3 hword crc error counter. counts frames not addre ssed to the user or frames received in the bsy condition, but does not include overrun, cd lost, or abort errors. 0x50 abtsc 3 hword abort sequence counter 0x52 nmarc 3 hword nonmatching address rx counter. counts nonmatching addresses received (error-free frames only). see the hmask and haddr[1?4] parameter description. 0x54 max_cnt word max_length counter. temporary decrementing counter that tracks frame length. 0x58 mflr hword max frame length register. if the hdlc cont roller detects an incoming hdlc frame that exceeds the user-defined value in mflr, the re st of the frame is discarded and the lg (rx frame too long) bit is set in the last bd belonging to that frame. the hdlc controller waits for the end of the frame and then reports the fram e status and length in the last rxbd. mflr includes all in-frame bytes between the opening and closing flags (address, control, data, and crc). 0x5a rfthr hword received frames threshold. used to reduce t he interrupt overhead that might otherwise occur when a series of short hdlc frames arrives, each causing an rxf interrupt. by programming rfthr, the user lowers the frequency of rxf interrupts, which occur only when the rfthr value is reached. note that the user shou ld provide enough empty rxbds to receive the number of frames specified in rfthr. 0x5c rfcnt hword received frames count. a decrementing counter used to implement this feature. initialize this counter with rfthr. 0x5e hmask hword hmask and haddr[1?4]. the hdlc controller reads the frame address from the hdlc receiver, checks it against t he four address register valu es, and masks the result with hmask. in hmask, a 1 represents a bit posit ion for which address comparison should occur; 0 represents a masked bit position. when addresses match, the address and subsequent data are written into the buffers. when addresses do not match and the frame is error-free, the nonmatching address received counter (nmarc) is incremented. note that for 8-bi t addresses, mask out (clear) the eigh t high-order bits in hmask. the eight low-order bits and haddrx should contain the address byte that immediately follows the opening flag. for example, to recognize a frame that begins 0x7e (flag), 0x68, 0xaa, using 16-bit address recognition, haddrx shou ld contain 0xaa68 and hmask should contain 0xffff. see figure 38-2 . 0x60 haddr1 hword 0x62 haddr2 hword 0x64 haddr3 hword 0x66 haddr4 hword 0x68 ts_tmp hword temporary storage 0x6a tmp_mb hword temporary storage 1 offset from fcc base: 0x8400 (fcc1) and 0x8500 (fcc2); see section 21.4.2, ?parameter ram.? 2 boldfaced entries must be initialized by the user. 3 disfc, crcec, abtsc, and nmarc?these 16-bit (modulo 216) co unters are maintained by the cp. the user can initialize them while the channel is disabled. table 38-1. fcc hdlc-specific parameter ram memory map (continued) offset 1 name 2 width description 4 datasheet u .com
fcc hdlc controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 38-5 figure 38-2 shows an example of us ing hmask and haddr[1?4]. figure 38-2. hdlc address recognition example 38.5 programming model the core configures each fcc to operate in th e protocol specified in gfmr[mode]. the hdlc controller uses the same data structure as other modes. this da ta structure supports multibuffer operation and address comparisons. 38.5.1 hdlc command set the transmit and receive commands are issued to the cpcr; see section 21.3, ?command set.? table 38-2 describes the transmit commands th at apply to the hdlc controller. table 38-2. transmit commands command description stop transmit after the hardware or software is reset and the channel is enabled in the fcc mode register, the channel is in transmit enable mode and starts polling the first bd in the table every 256 transmit clocks (immediately if ftodr[tod] = 1). stop transmit command disables the transmission of frames on the transmit channel. if this command is received by the hdlc controller during frame transmission, transmission is aborted after a maximum of 64 additional bits are sent and the transmit fifo buffer is flushed. the tbptr is not advanced, no new bd is accessed, and no new frames are sent for this channel. the transmitter sends an abort sequence consisting of 0x7f (if the command was gi ven during frame transmission) and begins sending flags or idles, as indicated by the hdlc mode register. note that if fpsmr[mff] = 1, one or more small frames can be flushed from the transmit fifo buffer. the graceful stop transmit command can be used to avoid this. graceful stop transmit used to stop transmission smoothly rather than abruptly, as performed by the regular stop transmit command. it stops transmission after the current frame fi nishes sending or immediately if no frame is being sent. fcce[gra] is set once transmi ssion has stopped. then the hdlc tran smit parameters (including bds) can be modified. the tbptr points to the next txbd in the table. transmission begins once the r bit of the next bd is set and the restart transmit command is issued. hmask 8-bit address recognition address 0x68 control 0x44 flag 0x7e address 0xaa etc. 16-bit address recognition 0xffff 0xaa68 0xffff 0xaa68 0xaa68 hmask address 0x55 control 0x44 flag 0x7e etc. 0x00ff 0xxx55 0xxx55 0xxx55 0xxx55 haddr1 haddr2 haddr3 haddr4 haddr1 haddr2 haddr3 haddr4 recognizes one 16-bit address (haddr1) and the 16-bit broadcast address (haddr2) recognizes one 8-bit address (haddr1) 4 datasheet u .com
fcc hdlc controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 38-6 freescale semiconductor table 38-3 describes the receive commands th at apply to the hdlc controller. 38.5.2 hdlc error handling the hdlc controller reports frame reception and tran smission error conditions using the channel bds, error counters, and hdlc event register (fcce). table 38-4 describes hdlc transmission errors, which are reported through the txbd. restart transmit enables character transmission on the transmit channel . this command is expected by the hdlc controller after a stop transmit command, after a stop transmit command is issued and the channel in its fcc mode register is disabled, after a graceful stop transmit command, or after a transmitter error (underrun or cts lost with no automatic frame retransmission). the hdlc controller resumes sending from the current tbptr in the channel txbd table. init tx parameters initializes all transmit parameters in this serial cha nnel parameter ram to their reset state. this command should only be issued when the transmitter is disabled. notice that the init tx and rx parameters command can also be used to reset the transmit and receive parameters. table 38-3. receive commands command description enter hunt mode after the hardware or software is reset and the channel is enabled in the fcc mode register, the channel is in receive enable mode and uses the first bd in the table. the enter hunt mode command is generally used to force the hdlc receiver to abort reception of the cu rrent frame and enter the hunt mode. in hunt mode, the hdlc controller continually scans the input data stream for the flag sequence. after receiving the command, the current receive buffer is closed, the error status fl ags and length field are cleared, rxbd[e] (the empty bit) is set, and the crc calculation is reset. further frame reception uses the current rxbd. init rx parameters initializes all the receive parameters in this serial channel parameter ram to t heir reset state and should be issued only when the receiver is disabled. notice that the init tx and rx parameters command resets both receive and transmit parameters. table 38-4. hdlc transmission errors error description tr a n s m i t t e r underrun when this error occurs, the channel terminates bu ffer transmission, transmit an abort sequence (a sequence which will generate crc error on the frame), closes the buffer, sets the underrun (u) bit in the bd, and generates the txe interrupt if it is enabled. the channel resumes transmission after receiving the restart transmit command. cts lost during frame transmission when this error occurs, the channel terminates buffer transmission, closes the buffer, sets txbd[ct], and generates a txe interrupt (if it is enabled). th e channel resumes transmission after receiving the restart transmit command. table 38-2. transmit commands (continued) command description 4 datasheet u .com
fcc hdlc controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 38-7 table 38-5 describes hdlc reception errors, which are reported through the rxbd. table 38-5. hdlc reception errors error description overrun error the hdlc controller maintains an internal fifo buffer for receiving data. the cp begins programming the sdma channel and updating the crc whenever data is received in the fifo buffer. when a receive fifo overrun occurs, the channel writes the received data byte to the internal fifo buffer over the previously received byte. the previous byte and the frame status are lost. the channel closes the buffer with rxbd[ov] set and generates the rxf interrupt if it is enabled. the receiver then enters hunt mode. even if the overrun occurs during a frame whose address is not matched in the address recognition logic, an rxbd with data length two is opened to report the overrun and the rxf interrupt is generated if it is enabled. cd lost during frame reception when this error occurs, the channel terminates frame reception, closes the buffer, sets rxbd[cd], and generates the rxf interrupt if it is enabled. this error has highest priority. the rest of the frame is lost and other errors are not checked in that frame. at this point, the receiver enters hunt mode. if cd is lost during the first 8 serial bits it will not be reported as cd lost error and there will be no indication of error. abort sequence the hdlc controller detects an abort sequence when seven or more consecutive ones are received. when this error occurs and the hdlc controller receives a fram e, the channel closes the bu ffer by setting rxbd[ab] and generates the rxf interrupt (if enabled). the c hannel also increments the abort sequence counter. the crc and nonoctet error status conditions are not che cked on aborted frames. the receiver then enters hunt mode. when an abort sequence is received, the user is gi ven no indication that an hdlc controller is not currently receiving a frame. nonoctet aligned frame when this error occurs, the channel writes the received data to the data buffer, closes the buffer, sets the rx nonoctet aligned frame bit rxbd[no], and generates the rx f interrupt (if it is enabled). the crc error status should be disregarded on nonoctet frames. after a nonocte t aligned frame is received, the receiver enters hunt mode. an immediate back-to-back frame is still receiv ed. the nonoctet data portion may be derived from the last byte in the buffer by finding the least-significant set bit, which marks the end of valid data as follows: msb lsb valid data 1000 crc error when this error occurs, the channel writes the re ceived crc to the data buffer, closes the buffer, sets rxbd[cr], and generates the rxf inte rrupt (if it is enabled). the cha nnel also increments the crc error counter. after receiving a frame with a crc error, the re ceiver enters hunt mode. an immediate back-to-back frame is still received. crc checking cannot be disabled , but the crc error can be ignored if checking is not required. 4 datasheet u .com
fcc hdlc controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 38-8 freescale semiconductor 38.6 hdlc mode register (fpsmr) when an fcc is configured for hdlc mode, the fpsm r is used as the hdlc mode register, shown in figure 38-3 . the fpsmr fields are described in table 38-6 . 0 3456 8910 15 field nof fse mff ? ts ? reset 0000_0000_0000_0000 r/w r/w offset 0x0x9_1304 (fpsmr1), 0x0x9_1324 (fpsmr2) 16 17 23 24 25 26 31 field nbl ? crc ? reset 0000_0000_0000_0000 r/w r/w offset 0x9_1306 (fpsmr1), 0x9_1326 (fpsmr2) figure 38-3. hdlc mode register (fpsmr) table 38-6. fpsmr field descriptions 1 bits name description 0?3 nof number of flags. minimum number of flags between or before frames (0?15 flags). if nof = 0000, no flags are inserted between the frames. thus, for back-to-back frames, the closing flag of one frame is immediately followed by the opening flag of the next frame. 4 fse flag sharing enable. this bit is valid only if gfmr[rtsm] is set. 0 normal operation 1 if nof = 0000, a single shared flag is transmitted between back-to-back frames. other values of nof are decremented by 1 when fse is set. this is us eful in signaling syst em #7 applications. 5 mff multiple frames in fifo. sett ing mff applies only when in rts mode (gfmr x [rtsm] = 1). 0 normal operation. the transmit fifo buffer must never contain more than one hdlc frame. the cts lost status is reported accurately on a per-frame basi s. the receiver is not affected by this bit. 1 the transmit fifo buffer can contain multiple frames, but lost cts is not guaranteed to be reported on the exact buffer/frame it occurred on. this option, however, can improve the performance of hdlc transmissions for small back-to-back frames or if the user prefers to strongly limit the number of flags sent between frames. mff does not affect the receiver. refer to note 1 at the end of this table. 7?8 ? reserved, should be cleared. 9 ts time stamp 0 normal operation. 1 a 32-bit time stamp is added at the beginning of the re ceive bd data buffer, thus the buffer pointer must be (32-byte aligned - 4). the bd?s data length does not include the time stamp. see section 21.2.7, ?risc time-stamp control register (rtscr).? 10?15 ? reserved, should be cleared. 4 datasheet u .com
fcc hdlc controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 38-9 38.7 hdlc receive buffer descriptor (rxbd) the hdlc controller uses the rxbd to report on data received for each buffer. figure 38-4 shows an example of the rxbd process. 16 nbl nibble mode enable 0 nibble mode disabled (1 bit of data per clock). note that at the end of the frame (after the closing flag), rts negates immediately after the active edge of tclk. 1 nibble mode enabled (4 bits of data per clock). the negation of the rts output signal is not synchronized to the serial clock. the rts is negated after the last nibble of t he data and always before the next edge of the serial clock. note that at the end of the frame (after the closing flag), rts negates a maximum of 5 cpm clocks after the active edge of tclk. 17?23 ? reserved, should be cleared. 24?25 crc crc selection 00 16-bit ccitt-crc (hdlc). x16 + x12 + x5 + 1 01 reserved 10 32-bit ccitt-crc (ethernet and hdlc). x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x1 +1 11 reserved 26?31 ? reserved, should be cleared. 1 when operating an fcc in hdlc nibble mode with the multif rame per fifo bit off (fpsmr[mff] = 0), the cpm might lose synchronization with the fcc hdlc controller. as a result th e hdlc controller will become stuck and stop transmission. therefore in hdlc nibble mode, fpsmr[ mff] must be set or the fcc must alternatively operate in hdlc bit mode. table 38-6. fpsmr field descriptions (continued) 1 bits name description 4 datasheet u .com
fcc hdlc controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 38-10 freescale semiconductor figure 38-4. fcc hdlc receiving using rxbds buffer 0 0x0020 32-bit buffer pointer 1 ef rxbd 0 status length pointer 0 0x0023 32-bit buffer pointer 0 ef rxbd 1 status length pointer 0 0x0003 32-bit buffer pointer 1 ef rxbd 2 status length pointer 1 xxxx 32-bit buffer pointer e rxbd 3 status length pointer address 1 address 2 control byte buffer crc byte 1 crc byte 2 buffer address 1 address 2 buffer control byte empty 32 bytes 32 bytes 32 bytes 32 bytes two frames received in hdlc unexpected abort stored in rx buffer line idle occurs before present time time stored in rx buffer buffer full buffer closed when closing flag buffer still empty 1 ab 29 empty mrblr = 32 bytes for this fcc empty last i-field byte information (i-field) bytes received abort was received after control byte 0 l 1 l 1 l faac i i i cr cr f closing flag abort/idle faac legend: f = flag a = address byte c = control byte i = information byte cr = crc byte . . . 4 datasheet u .com
fcc hdlc controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 38-11 figure 38-5 shows the fcc hdlc rxbd. table 38-7 describes rxbd fields. 0123456789101112131415 offset + 0 e ? wi lf cm ?lgnoabcrovcd offset + 2 data length offset + 4 rx data buffer pointer offset + 6 figure 38-5. fcc hdlc receive buffer descriptor (rxbd) table 38-7. rxbd field descriptions bits name 1 description 0 e empty 0 the buffer is full with received data or data reception stopped because of an error. the core can read or write to any fields of this rxbd. the cp does not use this bd while e = 0. 1 the buffer associated with this bd is empty. this rx bd and its associated receive buffer are owned by the cp. once e is set, the core should not write any fields of this rxbd. 1 ? reserved, should be cleared. 2 w wrap (final bd in table) 0 not the last bd in the rxbd table. 1 last bd in the rxbd table. after this buffer is used, the cp receives incoming data into the first bd that rbase points to in the table. the num ber of rxbds in this table is pr ogrammable and is determined only by the w bit and the overall spac e constraints of the dual-port ram. the rxbd table must contain more than one bd in hdlc mode. 3 i interrupt 0 the rxb bit is not set after this buffer is used, but rxf operation remains unaffected. 1 fcce[rxb] or fcce[rxf] is set when the hdlc controll er uses this buffer. these two bits can cause interrupts if they are enabled. 4 l last in frame. set by the hdlc controller when this buffer is the last one in a frame. this implies the reception of a closing flag or reception of an error, in which case one or more of the cd, ov, ab, and lg bits are set. the hdlc controller writes the number of frame octets to the data length field. 0 not the last buffer in a frame. 1 last buffer in a frame. 5 f first in frame. set by the hdlc controller when this buffer is the first in a frame. 0 not the first buffer in a frame. 1 first buffer in a frame. 6 cm continuous mode 0 normal operation. 1 the e bit is not cleared by the cp after this bd is closed, allowing the associated data buffer to be automatically overwritten the next ti me the cp accesses this bd. however, the e bit is cleared if an error occurs during reception, regardless of the cm bit. 7?9 ? reserved, should be cleared. 10 lg rx frame length violation. a frame length greater than the maximum defined for this channel is recognized, and only the maximum-allowed number of bytes (mflr) is written to the data buffer. this event is not reported until the rxbd is closed, the rxf bit is set, and the closing flag is received. the number of bytes received between flags is written to t he data length field of this bd. 4 datasheet u .com
fcc hdlc controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 38-12 freescale semiconductor the rxbd status bits are written by the hdlc cont roller after receiving th e associated data buffer. the remaining rxbd parameters are as follows: ? data length is the number of octets the cp writes into this bd?s data buffer. it is written by the cp once the bd is closed. when this is the last bd in the frame (l = 1), this field contains the total number of frame octets, including 2 or 4 bytes for crc. the memory allocated for this buffer should be no smaller than the mrblr value. ? rx data buffer pointer. the receive buffer pointer, wh ich always points to the first location of the associated data buffer, resides in internal or external memory and must be divisible by 32 unless fpsmr[ts] = 1 (see table 38-6 ). 38.8 hdlc transmit buffer descriptor (txbd) data is presented to the hdlc controller for tran smission on an fcc channel by arranging it in buffers referenced by the channel txbd table. the hdlc cont roller confirms transmis sion (or indicates errors) using the bds to inform the core th at the buffers have been serviced. figure 38-6 shows the fcc hdlc txbd. 11 no rx nonoctet-aligned frame. set when a received fram e contains a number of bits not divisible by eight. 12 ab rx abort sequence. at least seven consecut ive 1s are received during frame reception. 13 cr rx crc error. this frame contains a crc error. received crc bytes are written to the receive buffer. 14 ov overrun. a receiver overrun occurs during frame reception. 15 cd carrier detect lost. cd has negated during frame reception. this bit is valid only for nmsi mode. 1 boldfaced entries must be initialized by the user. 0123456789101112131415 offset + 0 r ? wi ltccm ?unct offset + 2 data length offset + 4 tx data buffer pointer offset + 6 figure 38-6. fcc hdlc transmit buffer descriptor (txbd) table 38-7. rxbd field descriptions (continued) bits name 1 description 4 datasheet u .com
fcc hdlc controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 38-13 table 38-8 describes hdlc txbd fields. the txbd status bits are written by the hdlc c ontroller after sending the associated data buffer. the remaining txbd parameters are as follows: ? data length is the number of bytes the hdlc controller should transmit from this data buffer; it is never modified by the cp. the value of this field should be greater than zero. ? tx data buffer pointer. the transmit buffer pointer , which contains the addr ess of the associated data buffer, can be even or odd. th e buffer can reside in internal or external memory. this value is never modified by the cp. table 38-8. hdlc txbd field descriptions bits name 1 1 boldfaced entries must be initialized by the user. description 0 r ready 0 the buffer associated with this bd is not ready for tr ansmission. the user can manipulate this bd or its associated buffer. the cp clears r after the buffer has been sent or an error occurs. 1 the buffer is ready to be sent. the transmission may have begun, but it has not completed. the user cannot set fields in this bd once r is set. 1 ? reserved, should be cleared. 2 w wrap (final bd in table) 0 not the last bd in the txbd table. 1 last bd in the txbd table. after this buffer has be en used, the cp sends data fr om the first bd that tbase points to in the table. the number of txbds in this table is determined only by the w bit and the overall space constraints of the dual-port ram. 3 i interrupt 0 no interrupt is generated after this buffer is serviced. 1 either fcce[txb] or fcce[txe] is set when this buffer is serviced by the hdlc controller. these bits can cause interrupts if they are enabled. 4 l last 0 not the last buffer in the frame. 1 last buffer in the current frame. 5 tc tx crc.valid only when the l bit is set. otherwise, it is ignored. 0 transmit the closing flag after the last data byte. this setting can be used to send a bad crc after the data for testing purposes. 1 transmit the crc sequence after the last data byte. 6 cm continuous mode 0 normal operation. 1 the r bit is not cleared by the cp after this bd is closed, allowing the buffer to be retransmitted automatically the next time the cp accesses this bd. however, the r bit is cleared if an error occurs during transmission, regardless of the cm bit. 7?13 ? reserved, should be cleared. 14 un underrun. the hdlc controller encounters a transmit ter underrun condition while sending the buffer. the hdlc controller writes un after sending the buffer. 15 ct cts lost. set when cts is lost during frame transmission in nmsi mode. if data from more than one buffer is in the fifo buffer when this error occurs, ct is set in the currently open txbd. the hdlc controller writes ct after sending the buffer. 4 datasheet u .com
fcc hdlc controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 38-14 freescale semiconductor 38.9 hdlc event register (fcce)/mask register (fccm) the fcce is used as the hdlc event register when the fcc operates as an hdlc controller. the fcce reports events recognized by the hdlc channel and generates interrupts. on recognition of an event, the hdlc controller sets the corresponding fcce bit. fcce bits are cleare d by writing ones; writing zeros does not affect bit values. all unmasked bits must be cleared before the cp clears the internal interrupt request. interrupts generated by the fcce can be masked in the hdlc mask register (fccm), which has the same bit format as fcce. if an fccm bit = 1, the corresponding interrupt in the event register is enabled. if the bit is 0, the interrupt is masked. figure 38-7 represents the fcc/fccm. table 38-9 describes fcce/fccm fields. 0123456789101112131415 field ? gra ? txe rxf bsy txb rxb reset 0000_0000_0000_0000 r/w r/w offset 0x0x9_1310 (fcce1), 0x0x9_1330 (fcce 2), 0x0x9_1314 (fccm1), 0x0x9_1334 (fccm2) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field ? flg idl ? reset 0000_0000_0000_0000 r/w r/w offset 0x9_1312 (fcce1), 0x9_1332 (fcce2), 0x9_1316 (fccm1), 0x9_1336 (fccm2) figure 38-7. hdlc event register (fcce)/mask register (fccm) table 38-9. fcce/fccm field descriptions bits name description 0?7 ? reserved, should be cleared. 8 gra graceful stop complete. a graceful stop, which was initiated by the graceful stop transmit command, is now complete. gra is set as soon as the transmitter fi nishes transmitting any frame that is in progress when the command was issued. it is set immediately if no frame is in progress when the command is issued. 9?10 ? reserved, should be cleared. 11 txe tx error. an error (cts lost or underrun) occurs on the transmitter channel. 12 rxf rx frame. a complete frame is received on the hdlc channel. this bit is set no sooner than two clocks after receipt of the last bit of the closing flag. 13 bsy busy condition. a frame is received and discarded due to a lack of buffers. 14 txb transmit buffer. enabled by setting txbd[i]. a buffer is sent on the hdlc channel. txb is set no sooner than when the last bit of the closing flag begi ns its transmission if the buffer is the last one in the frame. otherwise, txb is set after the last byte of the buffer is written to the transmit fifo buffer. 4 datasheet u .com
fcc hdlc controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 38-15 figure 38-8 shows interrupts that can be generated in the hdlc protocol. figure 38-8. hdlc interrupt event example 15 rxb receive buffer. when rxb = 1, a buffer for which the i bit is set in the corresponding bd was filled, regardless if the end of a frame was completed in it. 16?21 ? reserved, should be cleared. 22 flg flag status changed. the hdlc controller stops or st arts receiving hdlc flags. the real-time status can be obtained in fccs; see section 38.10, ?fcc status register (fccs).? 23 idl idle sequence status changed. a change in the stat us of the serial line is detected on the hdlc line. the real-time status can be read in fccs; see section 38.10, ?fcc status register (fccs).? 24?31 ? reserved, should be cleared. table 38-9. fcce/fccm field descriptions (continued) bits name description cd idl flg rxb rxf idl cd line idle stored in rx buffer rxd cd frame received by hdlc time line idle txd rts frame transmitted by hdlc cts txb ct ct line idle line idle stored in tx buffer notes : hdlc fcce events 1. rxb event assumes receive buffers are 6 bytes each. 2. the second idl event occurs after 15 ones are received in a row. 3. the flg interrupts show the beginning and end of flag reception. 4. the flg interrupt at the end of the frame may precede the rxf interrupt due to receive fifo latency. 5. the cd event must be programmed in the parallel i/o port, not in the fcc itself. notes: hdlc fcce events 1. txb event shown assumes all three bytes were put into a single buffer. 2. example shows one additional opening flag. this is programmable. f faaciiicrcrf flg flg flg 6. f = flag, a = address byte, c = control byte, i = information byte, and cr = crc byte ffaaccrcrf 3. the ct event must be programmed in the parallel i/o port, not in the fcc itself. 4 datasheet u .com
fcc hdlc controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 38-16 freescale semiconductor 38.10 fcc status register (fccs) the fccs register, shown in figure 38-9 , allows the user to monitor re al-time status conditions on the rxd line. the real-time status of the cts and cd signals are part of th e parallel i/o port; see chapter 45, ?parallel i/o ports.? table 38-10 describes fccs bits. 01234567 field ? fg ? id reset 0000_0000 r/w r offset 0x0x9_1318 (fccs 1), 0x0x9_1338 (fccs2) figure 38-9. fcc status register (fccs) table 38-10. fccs register field descriptions bits name description 0?4 ? reserved, should be cleared. 5 fg flags. while fg is cleared, each time a new bit is rece ived the most recently received 8 bits are examined to see if a flag is present. fg is set as soon as an hdlc fl ag (0x7e) is received on the line. once fg is set, it remains set at least 8 bit times while the next 8 bits of input data are examined. if another flag occurs, fg stays set for at least another eight bits. otherwise, fg is cleared and the search begins again. 0 hdlc flags are not currently being received. 1 hdlc flags are currently being received. 6 ? reserved, should be cleared. 7 id idle status. id is set when the rxd signal is a logic one for 15 or more consecutive bit times; it is cleared after a logic zero is received. 0 the line is busy. 1 the line is idle. 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 39-1 chapter 39 fcc transparent controller the fcc transparent controller functio ns as a high-speed serial-to-parallel and parallel-to-serial converter. transparent mode provides a clear channel on which the fcc perf orms no bit-level manipulation? implementing higher-level protocols w ould require software. transparent m ode is also referred to as a totally transparent or promiscuous operation. basic applications for an fcc in tran sparent mode include the following: ? for data, such as voice, moving serially without the need for protocol processing ? for board-level applications, such as chip-to- chip communications , requiring a se rial-to-parallel and parallel-to-serial conversion ? for applications requiri ng the switching of data paths without altering the protocol encoding itself, such as a multiplexer in which da ta from a high-speed td m serial stream is di vided into multiple low-speed data streams an fcc transmitter and receiver can be programmed in transpar ent mode independently. setting gfmr x [ttx] enables the transparent transmitter; setting gfmr x [trx] enables the transparent receiver. both bits must be set for full-duplex transparent operation. if only one bit is set, the other half of the fcc operates with the protocol programmed in gfmr x [mode]. this allows loopback modes to transfer data from one memory location to another (using dma) while the data is convert ed to a specific serial format. however, the ethernet and atm controll ers cannot be split in this way. see section 37.2, ?general fcc mode registers (gfmrx).? the fcc in transparent mode can work with th e tsa or nmsi and support modem lines using the general-purpose i/o signals. th e data can be transmitted and received with msb or lsb first in each octet. the fcc consists of separate transmit and receiv e sections whose operations are asynchronous with the core and can either be s ynchronous or asynchronous with respect to the other fccs. each clock can be supplied from the internal brg bank or external signals. 39.1 features the following is a list of the transparent controller?s important features: ? flexible data buffers ? automatic sync de tection on receive ? 16-bit pattern ? 8-bit pattern ? automatic sync (always synchronized) ? external sync signal support ? crcs can optionally be transmitted and received 4 datasheet u .com
fcc transparent controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 39-2 freescale semiconductor ? reverse data mode ? another protocol can be performed on the fcc?s other half (transmitter or receiver) during transparent mode ? external bd table 39.2 transparent channel operation the transparent transmitter and receiv er operates in the same way as the hdlc controller of the fcc (see chapter 38, ?fcc hdlc controller,? ) except in the following ways: 1. the fpsmr does not affect the transparent controller, only the gfmr does. 2. in table 38-1 , mflr, hmask, rfthr, and rfcnt must be cleared for proper operation of the transparent receiver. 3. transmitter synchronization ha s to be achieved using cts before the transmitter begins sending; see section 39.3, ?achieving synchroni zation in transparent mode.? 39.3 achieving synchronization in transparent mode once the fcc transmitter is enabled for transparent ope ration in the gfmr, the txbd is prepared for the fcc, and the transmit fifo is preloaded by the sdma channel, transmit synchronization must be established before data can be sent. similarly, once the fcc receiver is enabled for transparent operation in the gfmr and the rxbd is made empty for the fcc, receive synchroni zation must occur before data can be received. the synchronization process gives the user bit-level c ontrol of when the transmission a nd reception begins. the methods for this are as follows: ? an in-line synchronization pattern ? external synchronization signals ? automatic sync 39.3.1 in-line synchronization pattern the transparent channel can be programmed to tr ansmit and receive a s ynchronization pattern if gfmr[synl] 0; see section 37.2, ?general fcc mode registers (gfmrx).? the pattern is defined in the fdsr; see section 37.5, ?fcc data synchr onization registers (fdsrx).? gfmr[synl] defines the sync pattern length. the synchr onization pattern is shown in figure 39-1 . the receiver synchronizes on the sync hronization pattern located in the fdsr. for instance, if an 8-bit sync is selected, reception begins as soon as these eight bits are r eceived, beginning with the first bit 07815 field 8-bit sync pattern ? field 16-bit sync pattern (second byte) (first byte) figure 39-1. in-line synchronization pattern 4 datasheet u .com
fcc transparent controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 39-3 following the 8-bit sync. this effectively links the transmitter synchronization to the receiver synchronization. 39.3.2 external synchronization signals if gfmr[synl] = 00, an external signal is used to begin the sequence. cts is used for the transmitter and cd is used for the receiver; these signa ls share the following sampling options: ? the pulse/envelope optio n determines whether cd or cts need to be asserted only once to begin reception/transmission or whether they must be asse rted and stay that way for the duration of the transparent frame. this option is controlled by th e cdp and ctsp bits of the gfmr. if the user expects a continuous stream of data without interruption, th e pulse option should be used. however, if the user needs to identify frames of transparent data, the enve lope mode of the these signals should be used. note that the first bit of a frame is transmitted as zero every time rts is asserted before cts is asserted (gfmr[ctss] = 1); subse quent data bits are sent accurately. similarly, if cts is in pulse mode (gfmr[ctsp] = 1), onl y the first frame is affected. if cts is not in pulse mode (gfmr[ctsp] = 0), every frame is affected separately. note that if nrzi encoding is used (gfmr[tenc] = 01), rts must be asserted before cts , or else the first bit of the frame might be corrupted. ? the sampling option determines the delay between cd and cts being asserted and the resulting action by the fcc. these signals ca n be assumed to be asynchronous to the data and then internally synchronized by the fcc, or they can be assume d to be synchronous to the data giving faster operation. this option allows the rts of one fcc to be connected to the cd of another fcc (on another MPC8555E) and to have the data synchronized and bit aligned. it is also an option to link the transmitter synchronization to the receiver synchronization. when working with the fcc r eceiver in envelope mode, rts should be asserted for at least 3 cl ock cycles between frames. otherwise, the rece iver cannot recognize the start of a new frame. diagrams for the pulse/envelope and sampling options are in section 37.12, ?fcc timing control.? 4 datasheet u .com
fcc transparent controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 39-4 freescale semiconductor 39.3.3 transparent synchronization example figure 39-2 shows an example of synchroni zation using external signals. figure 39-2. sending transparent frames between MPC8555Es MPC8555E(a) and MPC8555E(b) exchange transparent frames and synchronize each other using rts and cd . however, cts is not required because transmi ssion begins at any time. thus, rts is connected directly to the other MPC8555E cd . gfmr[synl] is not used and tr ansmission and reception from each MPC8555E are independent. rxd cd clkx txd rts cd rxd brgox rts txd clkx brgox brgox last bit of frame data first bit of frame data (output is clkx input) txd (output is rxd input) rts (output is cd input) or crc txbd[l] = 1 causes negation of rts cd lost condition terminates reception of frame MPC8555E (a) MPC8555E (b) notes: 1 each MPC8555E generates its own transm it clocks. if the transmit and receive clocks are the same, one can generate transmit and receive clocks for the other MPC8555E. for example, clkx on MPC8555E (b) could be used to clock the transmitter and receiver. 2 cts should be configured as always asserted in the parallel i/o port or connected to ground externally. 3 the required gsmr configurations are diag = 00, ctss = 1, ctsp is a don?t care, cds = 1, cdp = 0, ttx = 1, and trx = 1. revd and tcrc are application-dependent. 4 the transparent frame contains a crc if txbd[tc] is set. 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 40-1 chapter 40 cpm fast ethernet controller the ethernet ieee 802.3 standard protocol is a wide ly-used lan based on the carrier-sense multiple access/collision detect (csma/cd) approach. because ethernet and ieee 802.3 standard protocols are similar and can coexist on the same l an, both are referred to as ethern et in this manual, unless otherwise noted. ethernet/ieee 802.3 stan dard frames are based on the frame structure shown in figure 40-1 . figure 40-1. ethernet frame structure the elements of an ethernet frame are as follows: ? 7-byte preamble of alte rnating ones and zeros ? start frame delimiter (sfd)?signi fies the beginning of the frame ? 48-bit destination address ? 48-bit source address. original versions of the ieee 802.3 st andard allowed 16-bit addressing, which has never been used widely. ? ethernet type field/ieee 802.3 standa rd length field. the type field si gnifies the protocol used in the rest of the frame, such as tcp/ip; the length field specifies th e length of the da ta portion of the frame. for ethernet and ieee 802.3 standard frames to exist on the same lan, the length field must be unique from any t ype fields used in ethernet. this requi rement limits the length of the data portion of the frame to 1,500 bytes and, therefore, the to tal frame length to 1,518 bytes. ?data ? four-bytes frame-check sequence (fcs), which is the standard, 32-bi t ccitt-crc polynomial used in many protocols when a station needs to transmit, it waits until the lan becomes silent for a specified period (interframe gap). when a station starts sendi ng, it continually checks for collisions on the lan. if a collision is detected, the station forces a jam signal (all ones) on its frame and st ops transmitting. collisions usually occur close to the beginning of a frame. the stati on then waits a random time period (backoff) before attempting to send again. when the b ackoff completes, the station wait s for silence on the lan and then begins retransmission on the l an. this process is called a retry. if th e frame is not succe ssfully sent within 15 retries, an error is indicated. preamble start frame data delimiter destination address ty p e / length source address frame check sequence 7 bytes 1 byte 6 bytes 6 bytes 2 bytes 46?1500 bytes 4 bytes frame length is 64?1,518 bytes note: the lsb of each octet is transmitted first. 4 datasheet u .com
cpm fast ethernet controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 40-2 freescale semiconductor 10-mbps ethernet basic timing specifications follow: ? transmits at 0.8 s per byte ? the preamble plus start frame delimiter is sent in 6.4 s ? the minimum interframe gap is 9.6 s ? the slot time is 51.2 s 100-mbps ethernet basic ti ming specifications follow: ? transmits at 0.08 s per byte ? the preamble plus start frame delimiter is sent in 0.64 s ? the minimum interframe gap is 0.96 s ? the slot time is 5.12 s 40.1 fast ethernet on the MPC8555E when a general fcc mode register (gfmr x [mode]) selects ethernet protoc ol, that fcc performs the full set of ieee 802.3 standard/ethernet csma/cd media access control (mac ) and channel interface functions. figure 40-2 shows a block diagram of the fcc ethernet control logic. figure 40-2. ethernet block diagram 40.2 features the following is a list of fast ethernet key features: ? support for fast ethernet through the mii (media-i ndependent interface) and the rmii (reduced media-independent interface) ? performs mac (media ac cess control) layer func tions of fast ethernet and ieee 802.3x standard shifter receive receiver control unit fifo shifter transmit transmitter control unit fifo slot time clock generator internal clocks control registers txd[3:0] rxd[3:0] peripheral bus system bus data data rx_clk tx_clk and defer counter tx_er random no. crs crs col rx_er tx_en col rx_dv 4 datasheet u .com
cpm fast ethernet controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 40-3 ? performs framing functions ? preamble generation and stripping ? destination address checking ? crc generation and checking ? automatic padding of s hort frames on transmit ? framing error (dribbling bits) handling ? full collision support ? enforces the collision (j amming and tx_er assertion) ? truncated binary exponential backoff algorithm for random wait ? two nonaggressive backoff modes ? automatic frame retransmission (until retry lim it is reached) ? automatic discard of incoming collided frames ? delay transmission of new frames for specified interframe gap ? bit rates up to 100 mbps ? receives back-to-back frames ? detection of receive frames that are too long ? multibuffer data structure ? supports 48-bit addresses in three modes ? physical. one 48-bit address recognized or 64-bin hash ta ble for physical addresses ? logical. 64-bin group address hash tabl e plus broadcast address checking ? promiscuous. receives all frames regardless of address (a cam can be used for address filtering) ? external cam support on system bus interfaces ? special rmon counters for monitoring network statistics ? transmitter network ma nagement and diagnostics ? lost carrier sense ? underrun ? number of collisions exceeded the maximum allowed ? number of retries per frame ? deferred frame indication ? late collision ? receiver network management and diagnostics ? crc error indication ? nonoctet alignment error ? frame too short ? frame too long 4 datasheet u .com
cpm fast ethernet controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 40-4 freescale semiconductor ? overrun ? busy (out of buffers) ? error counters ? discarded frames (out of bu ffers or overrun occurred) ? crc errors ? alignment errors ? internal and external loopback mode ? supports fast ethernet in duplex mode ? supports pause flow control frames ? support of out-of-sequenc e transmit queue (for flow-control frames) ? external buffer descriptors (bds) 40.3 connecting the MPC8555E to fast ethernet 40.3.1 connecting the mpc 8555e to ethernet (mii) figure 40-3 shows the basic compone nts of the media-independent interf ace (mii) and the signals required to make the fast ethernet connect ion between the MPC8555E and a phy. figure 40-3. connecting the MPC8555E to ethernet transmit error (tx_er) transmit nibble data 0?3 (txd[0:3]) transmit enable (tx_en) transmit clock (tx_clk) collision detect (col) receive nibble data 0?3 (rxd[0:3]) receive error (rx_er) receive clock (rx_clk) receive data valid (rx_dv) carrier sense output (crs) management data i/o1 (mdio) management data clock1 (mdc) fast ethernet phy medium media-independent interface (mii) 1 the management signals (mdc and mdio) can be common to all of the fast ethernet connections in the system, assuming that each phy has a different ma nagement address. use parallel i/o port pins to implement mdc and mdio. (the i 2 c controller cannot be used for this function.) MPC8555E 4 datasheet u .com
cpm fast ethernet controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 40-5 each fcc has 18 signals, defined by the ieee 802.3u sta ndard, for connecting to an ethernet phy. the two management signals (mdc and mdio) required by the mii should be implemented separately using the parallel i/o. the MPC8555E has additional signals for interfacing with an optional extern al content-addressable memory (cam), which are described in section 40.7, ?cam interface.? the MPC8555E uses the sdma channels to store ever y byte received after the st art frame delimiter into system memory. on transmit, the user provides the de stination address, source a ddress, type/length field, and transmit data. to meet mini mum frame requirements, MPC8555E au tomatically pads frames with fewer than 64 bytes in the data field. the MPC8555E also appends the fcs to the frame. 40.3.2 connecting the mpc 8555e to ethernet (rmii) figure 40-4 shows the basic components of the reduced media-independent inte rface (rmii) and the signals required for the fast ethernet connectio n between the MPC8555E and a phy. the mdc/mdio management interface is the same as in mii. the rmii reference clock (ref_clk) is distributed over the fcc transmit clock. in rmii m ode receive clock is not used. figure 40-4. connecting the MPC8555E to ethernet (rmii) 40.4 ethernet channel frame transmission the ethernet transmitter requires al most no core intervention. when the core enables the transmitter, the ethernet controller polls the first txbd in the fcc?s txbd table every 256 serial clocks. if the user has a frame ready to transmit, setting ft odr[tod] eliminates waiting for the next poll. when there is a frame to transmit, the ethernet controller begins fetching the data from the data buf fer and asserts tx_en. the preamble sequence, start frame de limiter, and frame information ar e sent in that order; see figure 40-1 . in full-duplex mode, because collisions are ignored, fr ame transmission maintains only the interframe gap 28 serial clocks (112 bit-time peri od) regardless of crs assertion. transmit di-bit data (txd[1:0]) transmit enable (tx_en) reference clock (ref_clk) receive di-bit data (rxd[1:0]) receive error (rx_er) receive crs_dv (crs_dv) management data i/o 1 (mdio) management data clock 1 (mdc) fast ethernet rmii phy medium 1 the management signals (mdc and mdio) can be common to all of the fast ethernet connections in the system, assuming that each phy has a di fferent management address. use parallel i/o port pins to implement mdc and mdio. (the i 2 c controller cannot be used for this function.) clock from board MPC8555E 4 datasheet u .com
cpm fast ethernet controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 40-6 freescale semiconductor there is one internal buffer for out-of-sequence flow c ontrol frames (in full-duplex fast ethernet). when the fast ethernet controller is betw een frames, this buffer is polled if flow control is enabled. this buffer must contain the whole frame. however, in half-duplex mode, the controller defers tr ansmission if the line is bus y (crs asserted). before transmitting, the controller waits fo r carrier sense to become inactive , at which point the controller determines if crs remains negated fo r 16 serial clocks. if so, the tran smission begins after an additional 8 serial clocks (96 bit-time s after crs originally became negated). in the fast et hernet transmitter, if crs is asserted and then negated within 10 clocks after txen is negated, th e next frame is not deferred and a defer indication is asserted. if a collision occurs during the tr ansmit frame, the ethernet contro ller follows a specified backoff procedure and tries to retransmit the frame until the re try limit is reached. the et hernet controller stores at least the first 64 bytes of data of the transmit frame in the fcc fifo, so that the data does not have to be retrieved from syst em memory in case of a collision. this improves bus usage and la tency if the backoff timer output requires an immediate retransmission. when the end of the current buffer is reached and txbd[l] = 1, the fcs (32-bi t crc) bytes are appended (if txbd[tc] = 1), and tx_en is negated. this notif ies the phy of the need to generate the illegal manchester encoding that signifies th e end of an ethernet frame. foll owing the transmission of the fcs, the ethernet controller writes the frame status bits into the bd and clears txbd[r]. when the end of the current buffer is reached and txbd[l] = 0 (a frame is comprised of multiple buffers), only txbd[r] is cleared. for both half- and full-duplex modes, an interrupt can be issued depending on txbd[i]. the ethernet controller then proceeds to the next txbd in the table. in this way, the core can be interrupted after each frame, after each buffer, or after a specific buffer is sent. if txbd[pad] = 1, the ethernet controller pads short frames to the value of the minimum fra me length register (minflr), described in table 40-2 . to rearrange the transmit queue before th e cp finishes sending all frames, issue a graceful stop transmit command. this can be useful for transmitting e xpedited data ahead of pr eviously linked buffers or for error situations. when the graceful stop transmit command is issued, th e ethernet controller stops immediately if no tran smission is in progress or continues transmi ssion until the current frame either finishes or terminates with a collision. wh en the ethernet controller is given the restart transmit command, it resumes transmission. the ethernet controller sends bytes least-significant nibble first. 40.5 ethernet channel frame reception the ethernet receiver is designed to work with almost no core intervention and can perform address recognition, crc checking, short frame checking, ma ximum dma transfer checking, and maximum frame-length checking. when the core enables the ethernet receiver, it enters hunt mode when rx_dv is asserted as long as col remains negated (full-duplex mode ignores col). in hunt mode, as data is shifted into the receive shift register four bits at a time, the cont ents of the register are compared to the contents of the syn2 field in the fcc?s data synchronization register (fdsr). when the registers match, the hunt mode is terminated and character assembly begins. 4 datasheet u .com
cpm fast ethernet controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 40-7 when the receiver detects the first byt es of a frame, the ethernet cont roller performs address recognition functions on the frame; see section 40.12, ?ethernet address recognition.? the receiver can receive physical (individual), group (m ulticast), and broadcast ad dresses. because ethernet receive frame data is not written to memory until the internal address rec ognition algorithm is complete, bus usage is not wasted on frames not addressed to this station. the receiver can also operate with an ex ternal cam, in which case frame reception continues normally, unless the cam spec ifically signals the fram e to be rejected. see section 40.7, ?cam interface.? if an address is recognize d, the ethernet controller fetches the next rxbd and, if it is empty, starts transferring the incoming frame to the rxbd?s associated data buffer. in half-duplex mode, if a collision is detected during the frame, the rxbds associated with this frame are reused. thus, no collision frames are presented to th e user except late collisions, which indicate serious lan problems. when the buffer has be en filled, the ethernet controller clears rxbd[e] and generates an interrupt if rxbd[i] is set. if the incoming frame is la rger than the buffer, the et hernet controller fetches the next rxbd in the table; if it is empty, it continues receiving the rest of the frame. the rxbd length is determined by mrblr in the pa rameter ram. the user should program mrblr to be at least 64 bytes. during reception, the ethernet controller checks for frames that are too short or too long. when the frame ends, th e receive crc field is checked and writte n to the data buffer. the data length written to the last bd in the ethernet frame is the le ngth of the entire frame, which enables the software to recognize a frame-t oo-long condition. if an external cam is used (fpsmr x [cam] = 1), the ethernet controller adds the 2 lower bytes of the cam output at the end of each frame. note that the data length does not include these 2 bytes; that is, the extra 2 bytes could push th e buffer length past mrblr. when the receive frame is complete, the ethernet cont roller sets rxbd[l], writ es the other frame status bits into the rxbd, and clears rxbd[e]. the ethern et controller next genera tes a maskable interrupt, indicating that a frame was received and is in memory. the ethernet controller then wait s for a new frame. the ethernet controller receives serial data least-signifi cant nibble first. 40.6 flow control because collisions cannot occur in full-duplex mode , fast ethernet can operate at the maximum rate. when the rate becomes too fast for a station?s recei ver, the station?s transmitter can send flow-control frames to reduce the rate. flow-control instructions are transferred by special frames of minimum frame size. the length/type fields of th ese frames have a special value. table 40-1 shows the flow-control frame structure. table 40-1. flow control frame structure size [octets] description value comment 7preamble 1 sfd start frame delimiter 6 destination address 01-80c2-00-00-01 multicast address reserved for use in mac frames 4 datasheet u .com
cpm fast ethernet controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 40-8 freescale semiconductor when flow-control mode is enabled (fpsmr x [fce]) and the receiver identifies a pause-flow control frame sent to individual or broadcas t addresses, transmission stops for the time specified in the control frame. during this pause, only the out-of-sequence frame is sent. norm al transmission resumes after the pause timer stops count ing. if another pause-control frame is received during th e pause, the period changes to the new value received. 40.7 cam interface the MPC8555E internal address recognition logic can be used in combination with an external cam. when using a cam, the fcc must be in promiscuous mode (fpsmr x [pro] = 1). see section 40.12, ?ethernet address recognition.? the ethernet controller writes two 32-bit accesses to the cam and then reads the result in a 32-bit access. if the high bit of the result is set, the frame is rejected; otherwise, the lower 16 bits are attached to the end of the frame. when an external cam is used for address filtering, users can choose to either di scard rejected frames (fpsmr[ecm] = 0) or receive re jected frames and signal the ca m miss in the rxbd (fpsmr[ecm] =1). note the bus atomicity mechanism for cam accesses may not function correctly when the cpm performs a dma access to an external cam device. this only impacts systems in which mu ltiple cpms will access the cam. 6 source address 2 length/type 88-08 control frame type 2 mac opcode 00-01 pause command 2 mac parameter up to 0xfffe pause period measured in slot times, most-significant octet first with a two time-slot resolution. note: because the pause period has a resolution of two time slots, the value programmed in this field is rounded up to the nearest even number before being used, as follows: mac parameter value pause period 0 none 1 or 2 2 x slot time 3 or 4 4 x slot time ?? 42 reserved ? 4 fcs frame check sequence (crc) table 40-1. flow control frame structure (continued) size [octets] description value comment 4 datasheet u .com
cpm fast ethernet controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 40-9 40.8 ethernet parameter ram for ethernet mode, the protocol-specific area of the fcc parameter ram is mapped as in table 40-2 . table 40-2. ethernet-specific parameter ram offset 1 name 2 width description 0x3c stat_buf word buffer of internal usage 0x40 cam_ptr word cam address. for fcc fast ethernet operati on the cam should be located on the same bus as the data buffers. 0x44 c_mask word constant mask for crc (i nitialize to 0xdebb_20e3). for the 32-bit crc-ccitt. 0x48 c_pres word preset crc (initialize to 0xffff _ffff). for the 32 -bit crc-ccitt. 0x4c crcec 3 word crc error counter. counts each received frame with a crc error. does not count frames not addressed to the station, frames received in th e out-of-buffers condition, frames with overrun errors, or frames with alignment errors. 0x50 alec 3 word alignment error counter. counts frames received with dribbling bits. does not count frames not addressed to the station, frames received in the out-of-buffers cond ition, or frames with overrun errors. 0x54 disfc 3 word discard frame counter. incremented for disc arded frames because of an out-of-buffers condition or overrun error. the crc need not be correct for this counter to be incremented. 0x58 ret_lim hword retry limit (typically 15 decimal). number of retries that should be made to send a frame. if the frame is not sent after this limit is reached, an interrupt can be generated. 0x5a ret_cnt hword retry limit counter. temporary decrementer used to count retries made. 0x5c p_per hword persistence. allows the ether net controller to be less persistent after a collision. normally cleared, p_per can be from 0 to 9 (9 = least pe rsistent). the value is added to the retry count in the backoff algorithm to reduce the chance of transmission on the next time-slot. using a less persistent backoff algorithm increases throughput in a congested ethernet lan by reducing the chance of collisions. fpsmr[sbt] can also reduce persistence of the ethernet controller. the ethernet/802.3 standard specifications permit the use of p_per. 0x5e boff_cnt hword backoff counter 0x60 gaddr_h word group address filters high and low are used in the hash table function of the group addressing mode. the user may write zeros to these values after reset and before the ethernet channel is enabled to disable all group hash address recognition functions. the set group address command is used to enable the hash table. see section 40.13, ?hash table algorithm.? 0x64 gaddr_l word 0x68 tfcstat hword out-of-sequence txbd. includes the status/contr ol, data length, and buffer pointer fields in the same format as a regular txbd. useful for sending flow control frames. this area?s txbd[r] is always checked between frames, regardless of fpsmr x [fce]. if it is not ready, a regular frame is sent. the user must set txbd[l ] when preparing this bd. if txbd[i] is set, a txc event is generated after frame transmission. this area should be cleared when not in use. 0x6a tfclen hword 0x6c tfcptr word 0x70 mflr hword maximum frame length register (typically1518 decimal). if the ethernet controller detects an incoming frame exceeding mflr, it sets rxbd[l g] (frame too long) in the last rxbd, but does not discard the rest of the frame. the cont roller also reports the frame status and length of the received frame in the last rxbd. mflr includes all in-frame bytes between the start frame delimiter and the end of the frame. 4 datasheet u .com
cpm fast ethernet controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 40-10 freescale semiconductor 0x72 paddr1_h hword the 48-bit individual address of this stat ion. paddr1_l is the lowest order half-word, and paddr1_h is the highest order half-word. 0x74 paddr1_m hword 0x76 paddr1_l hword 0x78 ibd_cnt hword internal bd counter 0x7a ibd_start hword internal bd start pointer 0x7c ibd_end hword internal bd end pointer 0x7e tx_len hword tx frame length counter 0x80 ibd_base 32 bytes internal microcode usage 0xa0 iaddr_h word individual address filter high/low. used in the has h table function of the individual addressing mode. the user can write zeros to these val ues after reset and before the ethernet channel is enabled to disable all individual hash address recognition functions. issuing a set group address command enables the hash table. see section 40.13, ?hash table algorithm.? 0xa4 iaddr_l word 0xa8 minflr hword minimum frame length register (typically 64 decimal). if the ethernet receiver detects an incoming frame shorter than minflr, it disca rds that frame unless fpsmr[rsh] (receive short frames) is set, in which case rxbd[sh] (f rame too short) is set in the last rxbd. the ethernet transmitter pads frames that are too short (according to txbd[pad] and the pad value in the parameter ram). pads are added to make the transmit frame minflr bytes. 0xaa taddr_h hword allows addition of addresses to the individual and group hashing tables. after an address is placed in taddr, issue a set group address command. taddr_l is the lowest-order half-word; taddr_h is the highest. a zero in the i/g bit indicates an individual address; 1 indicates a group address. 0xac taddr_m hword 0xae taddr_l hword 0xb0 pad_ptr hword internal pad pointer. this internal 32-byte a ligned pointer points to a 32-byte buffer filled with pad characters. the pads may be any value, but all the bytes should be the same to assure padding with a specific character. if a specific padding character is not needed, pad_ptr should equal the internal temporary data pointer tiptr; see section 37.8, ?f cc parameter ram.? 0xb2 ? hword reserved, should be cleared. 0xb4 cf_range hword control frame range. internal usage 0xb6 max_b hword maximum bd byte count. internal usage 0xb8 maxd1 hword max dma1 length register (typically 1520 decimal). lets th e user prevent system bus writes after a frame exceeds a specified size. the maxd1 value is valid only if an address match is detected. if the ethernet controller detects an incoming ethernet frame larger than the user-defined value in maxd1, the rest of the frame is discarded. the ethernet controller waits for the end of the frame (or until mflr bytes have been received) and reports the frame status and length (including the discarded bytes) in the last rxbd. this value must be greater than 32. table 40-2. ethernet-specific parameter ram (continued) offset 1 name 2 width description 4 datasheet u .com
cpm fast ethernet controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 40-11 0xba maxd2 hword max dma2 length register (typically 1520 decimal). lets th e user prevent system bus writes after a frame exceeds a specified size. the value of maxd2 is valid in promiscuous mode when no address match is detected. if the ethernet controller detects an incoming ethernet frame larger than the value in maxd2, the re st of the frame is discarded. the ethernet controller waits for the end of the frame (or un til mflr bytes are received) and reports frame status and length (including the discarded bytes) in the last rxbd. in a monitor station, maxd2 can be much less than maxd1 to receive en tire frames addressed to this station, but receive only the headers of all other fram es.this value must be less than maxd1. 0xbc maxd hword rx maximum dma. internal usage 0xbe dma_cnt hword rx dma counter. temporary do wn-counter used to track the frame length. 0xc0 octc 3 word (rmon mode only) the total number of octets of data (including those in bad packets) received on the network (excluding framing bits but including fcs octets). 0xc4 colc 3 word (rmon mode only) the best estimate of the total number of collisions on this ethernet segment. 0xc8 broc 3 word (rmon mode only) the total number of good packets received that were directed to the broadcast address. note that this does not include multicast packets. 0xcc mulc 3 word (rmon mode only) the total number of good packets received that were directed to a multicast address. note that this number does not include packets directed to the broadcast address. 0xd0 uspc 3 word (rmon mode only) the total number of packets received that were less than 64 octets (excluding framing bits but including fcs octets) and were otherwise well-formed. 0xd4 frgc 3 word (rmon mode only) the total number of packets received that were less than 64 octets long (excluding framing bits but including fcs octets) and had either a bad fcs with an integral number of octets (fcs error) or a bad fcs wi th a non-integral number of octets (alignment error). note that it is entirely normal for ether statsfragments to increm ent because it counts both runts (which are normal occurrences due to collisions) and noise hits. 0xd8 ospc 3 word (rmon mode only) the total number of packets received that were longer than 1518 octets (excluding framing bits but including fcs octets) and were otherwise well-formed. 0xdc jbrc 3 word (rmon mode only) the total number of packets received that were longer than 1518 octets (excluding framing bits but including fcs octets), and had either a bad fcs with an integral number of octets (fcs error) or a bad fcs wi th a non-integral number of octets (alignment error). note that this definition of jabber is different than the definition in ieee- 802.3 standard, section 8.2.1. 5 (10base5) and secti on 10.3.1.4 (10base2). t hese documents define jabber as the condition where any packet exceeds 20 ms. the allowed range to detect jabber is between 20 ms and 150 ms. 0xe0 p64c 3 word (rmon mode only) the total number of packets (including bad packets) received that were 64 octets long (excluding framing bits but including fcs octets). 0xe4 p65c 3 word (rmon mode only) the total number of packets (including bad packets) received that were between 65 and 127 octets long inclusive (excluding framing bits but including fcs octets). 0xe8 p128c 3 word (rmon mode only) the total number of packets (including bad packets) received that were between 128 and 255 octets long inclusive (excluding framing bits but including fcs octets). 0xec p256c 3 word (rmon mode only) the total number of packets (including bad packets) received that were between 256 and 511 octets long inclusive (excluding framing bits but including fcs octets). table 40-2. ethernet-specific parameter ram (continued) offset 1 name 2 width description 4 datasheet u .com
cpm fast ethernet controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 40-12 freescale semiconductor 40.9 programming model the core configures an fcc to operate as an ethern et controller using gfmr[mode]. the receive errors (collision, overrun, nonoctet-aligned frame, short frame, frame too long, and crc error) are reported through the rxbd. the transmit errors (underrun, heartbeat, late collision, retransmission limit, and carrier sense lost) are reported through the txbd. the user should program th e fdsr as described in section 37.5, ?fcc data s ynchronization registers (fdsrx),? with fdsr[syn2] = 0xd5 and fdsr[syn1] = 0x55. 40.10 ethernet command set the transmit and receive commands are issued to the cpcr; see section 21.3, ?command set.? note before resetting the cpm, configure tx_en (rts ) to be an input. transmit commands that apply to ethernet are described in table 40-3 . 0xf0 p512c 3 word (rmon mode only) the total number of packets (including bad packets) received that were between 512 and 1023 octets long inclusive (excluding framing bits but including fcs octets). 0xf4 p1024c 3 word (rmon mode only) the total number of packets (including bad packets) received that were between 1024 and 1518 octets long inclusive (excluding framing bits but including fcs octets). 0xf8 cam_buf word internal buffer for cam result 0xfc ? word reserved, should be cleared. 1 offset from fcc base: 0x8400 (fcc1) and 0x8500 (fcc2); see section 21.4.2, ?parameter ram.? 2 boldfaced entries must be initialized by the user. 3 32-bit (modulo 232) counters maintained by the cp; cleared by the user while the channel is disabled. table 40-3. transmit commands command description stop transmit when used with the ethernet contro ller, this command violates a specific behavior of an ethernet/ieee 802.3 standard station. it should not be used. graceful stop transmit used to smoothly stop transmission after the current frame finishes sending or undergoes a collision (immediately if there is no frame being sent). fcce[gra ] is set once transmission stops. then the ethernet transmit parameters (including bds) can be modified by the user. the tbptr points to the next txbd in the table. transmission begins when the r bit of the next bd is set and the restart transmit command is issued. note that if the graceful stop transmit command is issued and the current transmit frame ends in a collision, the tbptr points to the beginning of the collided fram e with txbd[r] still set (the frame looks as if it was never sent). table 40-2. ethernet-specific parameter ram (continued) offset 1 name 2 width description 4 datasheet u .com
cpm fast ethernet controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 40-13 receive commands that apply to ethernet are described in table 40-4 . if an address from the hash table must be deleted, the ethernet channe l must be disabled, the hash table registers must be cleared, and the set group address command must be executed for the remaining preferred addresses. this is required because the hash table might have mapped mu ltiple addresses to the same hash table bit. 40.11 rmon support the fast ethernet controller can automatically gath er network statistics requi red for rmon without the need to receive all addresses using promis cuous mode. setting fpsmr x [mon] enables rmon support. restart transmit enables transmission of characters on the transmit channel . it is expected by the ethernet controller after a graceful stop transmit command or transmitter error (underrun, retransmission limit reached, or late collision). the ethernet controller resumes transmissi on from the current tbptr in the channel txbd table. init tx parameters initializes all the transmit parameters in this serial channel paramete r ram to their reset state. this command should be issued only when the transmitter is disabled. note that the init tx and rx parameters command can also be used to reset the transmit and receive parameters. table 40-4. receive commands command description enter hunt mode after the hardware or software is reset and the channel in the fcc mode register is enabled, the channel is in the receive enable mode and uses the first bd in the table. this command is generally used to force the ethernet receiver to abort reception of the current frame and enter hunt mode. in hunt mode, the ethernet controller continually scans the input data stream for a transition of carrier sense from inactive to active followed by a preamble sequence and the start frame delimiter. after receiving the command, the current receive buffer is closed, the error status flags and leng th field are cleared, rxbd[e] (the empty bit) is set, and the crc calculation is reset. further fr ame reception uses the current rxbd. note that short frames pending in the internal fifo may be lost. init rx parameters initializes all the receive parameters in this serial ch annel parameter ram to their reset state and should only be issued when the receiver is disabled. note that the init tx and rx parameters command can also be used to reset the receive and transmit parameters. set group address used to set one of the 64 bits of the four individual/group address hash filter registers (iaddr[1?4] or gaddr[1?4]). the individual or group address (48 bits) to be added to the hash table should be written to taddr_l, taddr_m, and taddr_h in the parameter ram prior to executing this command. the cp checks the i/g bit in the address stored in taddr to determine whether to use the individual hash table or the group hash table. a 0 in the i/g bit indicates an individual address; 1 indicates a group address. this command can be executed at any time, regardless of whether the ethernet channel is enabled. table 40-3. transmit commands (continued) command description 4 datasheet u .com
cpm fast ethernet controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 40-14 freescale semiconductor the rmon statistics a nd their corresponding counters in th e parameter ram are described in table 40-5 . table 40-5. rmon statistics and counters statistic description counter etherstatsdropevents the total number of events in which packets were detected as dropped by the probe due to lack of resources. note that this may not be the number of packets dropped; it is the number of times this condition is detected. disfc etherstatsoctets the total number of octets of data (including those in bad packets) received on the network (excluding framing bits but including fcs octets). octc etherstatspkts the total number of packets (including bad packets, broadcast packets, and multicast packets) received. uspc + ospc + frgc + jbrc + p64c + p65c + p128c + p256c + p512c + p1024c etherstatsbroadcastpkts the total number of good packets received that were directed to the broadcast address. note that this does not include multicast packets. broc etherstatsmulticastpkts the total number of good pa ckets received that were directed to a multicast address. note that this number does not include packets directed to the broadcast address. mulc etherstatscrcalignerrors the total number of packe ts received that had a length (excluding framing bits but including fcs octets) of between 64 and 1518 octets, inclusive, but had either an integral number of octets (fcs error) or a bad fcs with a non-integral number of octets (alignment error). crcec + alec -frgc -jbrc etherstatsundersizepkts the total number of packets received that were less than 64 octets long (excluding framing bits but including fcs octets) and were otherwise well-formed. uspc etherstatsoversizepkts the total number of packets received that were longer than 1518 octets (excluding framing bits but including fcs octets) and were otherwise well-formed. ospc etherstatsfragments the total nu mber of packets received that were less than 64 octets long (excluding framing bits but including fcs octets) and had either a bad fcs with an integral number of octets (fcs error) or a bad fcs with a non-integral number of octets (alignment error). note that it is entirely normal for etherstatsfragments to increment, because it counts both runts (which are normal occurrences due to collisions) and noise hits. frgc etherstatsjabbers the total number of packets received that were longer than 1518 octets (excluding framing bits but including fcs octets) and had either a bad fcs with an integral number of octets (fcs error) or a bad fcs with a non-integral number of octets (alignment error). note that this definition of jabber is different than the definiti on in ieee-802.3 standar d, section 8.2.1.5 (10base5) and section 10.3.1.4 (10base2). these documents define jabber as the condition where any packet exceeds 20 ms. the allowed range to detect jabber is between 20 ms and 150 ms. jbrc etherstatscollisions the best estima te of the total number of colli sions on this ethernet segment. colc 4 datasheet u .com
cpm fast ethernet controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 40-15 40.12 ethernet address recognition the ethernet controller can filt er the received frames based on different addressing types?physical (individual), group (multicast), br oadcast (all-ones group address), a nd promiscuous. the difference between an individual address and a group address is determined by the i/ g bit in the destination address field. figure 40-5 is a flowchart for address recognition on received frames. etherstatspkts64oct ets the total number of packets (including bad packets) received that were 64 octets long (excluding framing bits but including fcs octets). p64c etherstatspkts65to127octets the total number of pa ckets (including bad packets) received that were between 65 and 127 octets long inclusive (excluding framing bits but including fcs octets). p65c etherstatspkts128to255octets the tota l number of packets (including bad packets) received that were between 128 and 255 octets long inclusive (excluding framing bits but including fcs octets). p128c etherstatspkts256to511octets the tota l number of packets (including bad packets) received that were between 256 and 511 octets long inclusive (excluding framing bits but including fcs octets). p256c etherstatspkts512to1023octets the tota l number of packets (including bad packets) received that were between 512 and 1023 octets long inclusive (excluding framing bits but including fcs octets). p512c etherstatspkts1024to1518octets the tota l number of packets (including bad packets) received that were between 1024 and 1518 octets long inclusive (excluding framing bits but including fcs octets). p1024c table 40-5. rmon statistics and counters (continued) statistic description counter 4 datasheet u .com
cpm fast ethernet controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 40-16 freescale semiconductor figure 40-5. ethernet address recognition flowchart check address i/g address individual addr match? i g broadcast addr broadcast enabled t receive frame t hash search use group ta b l e hash search use individual ta b l e t match? t promiscuous? discard frame t f f f f f use cam? start receive rejected by cam? f t t f 4 datasheet u .com
cpm fast ethernet controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 40-17 in the physical type of address rec ognition, the ethernet controller comp ares the destination address field of the received frame with the physical address that the user programs in the paddr. if it fails, the controller performs address rec ognition on multiple individual addr esses using the iaddr_h/l hash table. since the controller always checks paddr and the individual ha sh, for individual address the user must write zeros to the hash in or der to avoid a hash match and ones to paddr in order to avoid individual address match. in the group type of address recogni tion, the ethernet contro ller determines whethe r the group address is a broadcast address. if it is a broadcast and broadcast addresses ar e enabled, the frame is accepted. if the group address is not a broadcast address, the us er can perform address recognition on multiple group addresses using the gaddr_h/l hash ta ble. in promiscuous mode, the ethe rnet controller receives all of the incoming frames regardless of their addr ess when an external cam is not used. if an external cam is used for address recognition (fpsmr[cam] = 1), the user should select promiscuous mode; the frame can be rejected if ther e is no match in the cam. if the on-chip address recognition functions detect a match, the external cam is not accessed. otherwise, the cpm issues a match transaction to the cam using the bus on which the data buffers reside. (the data buffer bus is selected in fcr x [dtb]; see section 37.8.1, ?fcc function code registers (fcrx).? ) 40.13 hash table algorithm the hash table process used in th e individual and group hash filtering operates as follows. the ethernet controller maps any 48-bit addr ess into one of 64 bins, which ar e represented by the 64 bits in gaddr_h/l or iaddr_h/l. when the set group address command is executed, the ethernet controller maps the selected 48-bit address in taddr into one of the 64 bits. this is performed by passing the 48-bit address through the on-chip 32-bit crc genera tor and using 6 bits of the crc-encoded result to generate a number between 1 and 64. bit 26 of the crc result selects which address filter registers are used in the hashing process?either gaddr_ h/iaddr_h or gaddr_l/ iaddr_l? and bits 27?31 of the crc result sele ct which bit is set. the same process is used when the ethernet controller receives a frame. if the crc generator selects a bit that is set in the group/individual hash table, the frame is accepted; otherwise, it is rejected. the result is that if eight group addresses are stored in the hash table and random group addresse s are received, the hash table prevents roughly 56/64 (87.5%) of the group address frames from reaching memory. the core must further filter those that reach memory to determine if they contain one of the eight preferred addresses. better performance is achieved by using the group and i ndividual hash tables in combination. for instance, if eight group and eight physical addr esses are stored in their respectiv e hash tables, 87.5% of all frames (not just group address frames) ar e prevented from reaching memory. the effectiveness of the hash table declines as the number of addresses increase s. for instance, with 128 addresses stored in a 64-bin hash table, the vast majo rity of the hash table bits are set, preventing only a small fraction of frames fr om reaching memory. in such instances, an external cam is advised if the extra bus use cannot be tolerated. see section 40.7, ?cam interface.? 4 datasheet u .com
cpm fast ethernet controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 40-18 freescale semiconductor note the hash tables cannot be used to reject frames that match a set of selected addresses because unintended addresses can map to the same bit in the hash table. thus, an external cam must be used to implement this function. 40.14 interpacket gap time the minimum interpacket gap time for back-to-back tr ansmission is 96 bit-times. the receiver receives back-to-back frames with this minimum spacing. in addition, after the backoff algorithm, the transmitter waits for carrier sense to be negated before re transmitting the frame. the retransmission begins 96 bit-times after carrier sense is negated if it stays negated for at leas t 64 bit-times. so if there is no change in the carrier sense indication during the first 64 bit-times (16 serial clocks), the retransmission begins 96 clocks after carrier sense is first negated 40.15 handling collisions if a collision occurs duri ng frame transmission, the ethernet controll er continues transm ission for at least 32-bit times, transmitting a jam pattern of 32 ones. if the collision occurs dur ing the preamble sequence, the jam pattern is sent after the sequence ends. if a collision occurs within 64 byte-times, the pro cess is retried. the transm itter waits a random number of slot times. (a slot time is 512 bit-times.) if a collision occurs af ter 64 byte-times, no retransmission is performed, fcce[txe] is set, and th e buffer is closed with a late-co llision error indication in txbd[lc]. if a collision occurs during frame reception, reception is stopped. this error is reported only in the rxbd if the frame is at least as long as the minflr or if fpsmr[rsh] = 1. 40.16 internal and external loopback both internal and external loopback are supported by the ethernet controller. in loopback mode, both receive and transmit fifo buffers are used and the fcc operates in full-duplex mode. both internal and external loopback are configured using combinati ons of fpsmr[lpb] and gfmr [diag]. because of the full-duplex nature of the loopback operation, the performance of the othe r fccs is degraded. internal loopback disconnects the fcc from the si. the r eceive data is connected to the transmit data. the transmitted data from the transmit fifo is received immediately in to the receive fifo. there is no heartbeat check in this mode. in external loopback operation, the ethernet controller listens for data received from the phy while it is sending. 4 datasheet u .com
cpm fast ethernet controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 40-19 40.17 ethernet error-handling procedure the ethernet controller reports fra me reception and transmission error conditions using the channel bds, the error counters, and the fcc event regist er. transmission errors are described in table 40-6 . reception errors are described in table 40-7 . 40.18 fast ethernet registers the following sections desc ribe registers used for c onfiguring and operating the fa st ethernet controller. 40.18.1 general fcc expansio n mode register (gfemr) the general fcc expansion mode register (gfemr) defines the e xpansion modes. it should be programmed according to the protocol used. table 40-6. transmission errors error response tr a n s m i t t e r underrun the controller sends 32 bits that ensure a crc error, te rminates buffer transmission, closes the buffer, sets txbd[un] and fcce[txe]. the controller re sumes transmission after receiving the restart transmit command. carrier sense lost during frame transmission if no collision is detected in the frame, the controll er sets txbd[csl] and fcce[txe], and it continues the buffer transmission normally. no retries are performed as a result of this error. retransmission attempts limit expired the controller terminates buffer transmission, closes the buffer, sets txbd[rl] and fcce[txe]. transmission resumes after receiving the restart transmit command. late collision the controller terminates buffer transmissi on, closes the buffer, sets txbd[lc] and fcce[txe]. the controller resumes transmi ssion after receiving the restart transmit command. note that late collision parameters are defined in fpsmr[lcw]. table 40-7. reception errors error description overrun error the ethernet controller mainta ins an internal fifo buffer for receiving data. if a receiver fifo buffer overrun occurs, the controller writes the received data byte to the internal fifo buffer over the previously received byte. the previous data byte and frame status are los t. the controller closes the buffer, sets rxbd[ov] and fcce[rxf], and increments the discarded frame count er (disfc). the receiver then enters hunt mode. busy error a frame is received and discard ed due to a lack of buffers. the cont roller sets fcce[ bsy] and increments the discarded frame counter (disfc). non-octet error (dribbling bits) the ethernet controller handles a nibble of dribbling bits when the receive frame terminates as nonoctet aligned and it checks the crc of the frame on the last octet boundary. if there is a crc error, the frame nonoctet aligned (rxbd[no]) error is reported, fcce[rxf ] is set, and the alignment error counter (alec) in the parameter ram is incremented. if there is no crc error, no error is reported. crc error when a crc error occurs, the controller closes the bu ffer, and sets rxbd[cr] and fcce[rxf]. also, the crc error counter (crcec) in the parameter ram is in cremented. after receiving a frame with a crc error, the receiver enters hunt mode. crc checking cannot be disabled, but the crc error can be ignored if checking is not required. 4 datasheet u .com
cpm fast ethernet controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 40-20 freescale semiconductor table 40-8 describes gfemr x fields. 40.18.2 fcc ethernet mode register (fpsmr) the MPC8555E supports 10/100 mbps ethernet th rough a rmii interface (according to rmii specification march 20, 19 98). the rmii use a single reference cloc k (50 mhz) and seven pins which are a proper subset of the mii interface pins. ethernet features are unchanged in rmii mode. to select rmii-phy interface, a mode bit in the ethernet mode register (fpsm r) has been added, as shown in figure 40-7 . 0123 7 field tirem lpb clk ? reset 0000_0000 r/w r/w offset 0x9_1390 (gfemr1), 0x9_13b0(gfemr2) figure 40-6. general fcc expansion mode register (gfemr) table 40-8. gfemr x field descriptions bit name description 0 tirem transmit internal rate expanded mode (atm mode) 0 internal rate mode: internal rate for phys[0?3] is controlled only by ftirr[0?3]. firper, firsr_hi, firsr_lo, fiter are unused. 1 internal rate expanded mode: phys[0?31] are co ntrolled by ftirr[0?3], firper, firsr_hi, and firsr_lo. underrun status for phys[0? 31] is available by firer. this bit should be set only in transmit master multi-phy mode. in this mode mixing of internal rate and external rate is not enabled. 1 lpb rmii loopback diagnostic mode (ethernet mode): 0 normal mode 1 loopback mode 2 clk rmii reference clock rate for 50 mhz input clock from external oscillator (ethernet mode): 0 50 mhz (for fast ethernet) 1 5 mhz (for 10baset) 3?7 ? reserved, should be cleared. 4 datasheet u .com
cpm fast ethernet controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 40-21 table 40-9 describes fpsmr fields. 0123456789101112131415 field hbc fc sbt lpb lcw fde mon ? pro fce rsh ? rmii ? reset 0000_0000_0000_0000 r/w r/w offset 0x9_1304 (fpsmr1), 0x9_1324 (fpsmr2) 16 20 21 22 23 24 25 26 31 field ? cam bro ? crc ? reset 0000_0000_0000_0000 r/w r/w offset 0x9_1306 (fpsmr1), 0x9_1326 (fpsmr2) figure 40-7. fcc ethernet mode register (fpsmr x ) table 40-9. fpsmr ethernet field descriptions bits name description 0 hbc heartbeat checking 0 no heartbeat checking is performed. do not wait for a collision after transmission. 1 wait 40 transmit serial clocks for a collision asserted by the transceiver after transmission. txbd[hb] is set if the heartbeat is not heard within 40 transmit serial clocks. 1 fc force collision 0 normal operation 1 the channel forces a collision on transmission of every transmit frame. the MPC8555E should be configured in loopback operation when using this feat ure, which allows the user to test the MPC8555E collision logic. it causes the retry limit to be exceeded for each transmit frame. 2 sbt stop backoff timer 0 the backoff timer functions normally. 1 the backoff timer (for the random wait after a collision) is stopped whenever carrier sense is active. in this method, the retransmission is less aggressive than the maximum allowed in the ieee 802.3 standard. the persistence (p_per) feature in the parameter ram can be used in combination with the sbt bit (or in place of the sbt bit). 3 lpb loopback operation 0 normal operation (receiver does not receive when transmitter sends). 1 the channel is configured for internal or external loopback operation as determined by gfmr[diag]. for external loopback, configure diag for normal operation; for internal loopback configure diag for loopback operation. 4 lcw late collision window 0 a late collision is any collision that occurs at least 64 bytes from the preamble. 1 a late collision is any collision that occurs at least 56 bytes from the preamble. 5 fde full-duplex ethernet 0 disable full duplex 1 enable full duplex. must be set if fsmr[lpb] is set or external loopback is performed. 6 mon rmon mode 0 disable rmon mode 1 enable rmon mode 4 datasheet u .com
cpm fast ethernet controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 40-22 freescale semiconductor 40.18.3 ethernet event register (fcce)/mask register (fccm) the fcce, shown in figure 40-8 , is used as the ethernet event regi ster when the fcc functions as an ethernet controller. it generates interrupts and repor ts events recognized by the ethernet channel. on recognition of an event, the ethern et controller sets the corresponding fcce bit. interrupts generated by this register can be masked in th e ethernet mask register (fccm). the fccm has the same bit format as fcce. settin g an fccm bit enables and clearing a bit masks the corresponding interrupt in the fcce. the fcce can be read at any time. bits are cleared by writi ng ones; writing zero s does not affect bit values. unmasked fcce bits must be cleared before the cp clears the internal interrupt request. 7?8 ? reserved, should be zero 9 pro promiscuous 0 check the destination address of incoming frames. 1 receive the frame regardless of its address. a ca m can be used for address filtering when fsmr[cam] is set. 10 fce flow control enable 0 flow control is not enabled 1 flow control is enabled 11 rsh receive short frames 0 discard short frames (frames smaller than the value specified in minflr). 1 receive short frames. 12?13 ? reserved, should be zero 14 rmii rmii interface mode 0 mii interface 1 rmii interface. rmii to/from mii conversion logic is enabled. 15?20 ? reserved, should be zero 21 cam cam address matching 0 normal operation. 1 use the cam for address matching; cam result (16 bits) is added at the end of the frame. 22 bro broadcast address 0 receive all frames contai ning the broadcast address. 1 reject all frames containing the broadcast address unless fsmr[pro] = 1. 23 ? reserved, should be zero 24?25 crc crc selection 0x reserved 10 32-bit ccitt-crc (ethernet). x32 + x26 + x23 + x2 2 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x1 +1. select this to comp ly with ethernet specifications. 11 reserved 26?31 ? reserved, should be zero table 40-9. fpsmr ethernet field descriptions (continued) bits name description 4 datasheet u .com
cpm fast ethernet controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 40-23 table 40-10 describes fcce/fccm fields. 0 7 8 9 10 11 12 13 14 15 field ? gra rxc txc txe rxf bsy txb rxb reset 0000_0000_0000_0000 r/w r/w offset 0x0x9_1310 (fcce1), 0x0x9_1330 (fcce 2), 0x0x9_1314 (fccm1), 0x0x9_1334 (fccm2) 16 31 field ? reset 0000_0000_0000_0000 r/w r/w offset 0x9_1312 (fcce1), 0x9_1332 (fcce2), 0x9_1316 (fccm1), 0x9_1336 (fccm2) figure 40-8. ethernet event register (fcce)/mask register (fccm) table 40-10. fcce/fccm field descriptions bits name description 0?7 ? reserved, should be cleared. 8 gra graceful stop complete. a graceful stop, initiated by the graceful stop transmit command, is complete. when the command is issued, gra is set as soon the transmitter finishes sending a frame in progress. if no frame is in progress, gra is set immediately. 9 rxc rx control. a control frame has been received (fsmr[fc e] must be set). as soon as the transmitter finishes sending the current frame, a pause operation is performed. 10 txc tx control. an out-of-sequence frame was sent. 11 txe tx error. an error occurred on the transmitter channel. 12 rxf rx frame. set when a complete frame is received on the ethernet channel. 13 bsy busy condition. set when a frame is received and discarded due to a lack of buffers. 14 txb tx buffer. set when a buffer has been sent on the ethernet channel. 15 rxb rx buffer. a buffer that was not a complete frame is received on the ethernet channel. 16?31 ? reserved, should be cleared. 4 datasheet u .com
cpm fast ethernet controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 40-24 freescale semiconductor figure 40-9 shows interrupts that can be gene rated in the ethernet protocol. figure 40-9. ethernet interrupt events example note the fcc status register is not valid for the ethernet protocol. the current state of the mii signals can be read through the parallel ports. rxb line idle stored in rx buffer rxd rx_dv frame received in ethernet time line idle txd tx_en frame transmitted by ethernet col txb, gra txb line idle line idle stored in tx buffer notes: ethernet fcce events 1. rxb event assumes receive buffers are 64 bytes each. 2. the rxf interrupt may occur later than rx_dv due to receive fifo latency. notes: ethernet fcce events 1. txb events assume the frame required two transmit buffers. 2. the gra event assumes a graceful stop transmit command was issued during frame transmission. psfddasa cr rxf t/l d psfddasa cr t/l d legend: p = preamble, sfd = start frame delimiter, da and sa = destination/source address, t/l = type/length, d = data, cr = crc bytes 4 datasheet u .com
cpm fast ethernet controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 40-25 40.19 ethernet rxbds the ethernet controller uses the rxbd to report in formation about the received data for each buffer. figure 40-10 shows the fcc ethernet rxbd format. table 40-11 describes ethernet rxbd fields. 0123456789101112131415 offset + 0 e ? wi l f cmr m bc mc lg no sh cr ov cl offset + 2 data length offset + 4 rx data buffer pointer offset + 6 figure 40-10. fast ethernet receive buffer (rxbd) table 40-11. rxbd field descriptions bits name description 0 e empty 0 the buffer associated with this rxbd is full or reception terminated due to an error. the core can examine or read to any fields of this rxbd. the cp does not use this bd as long as e = 0. 1 the associated buffer is empty. the rxbd and buffer are owned by the cp. once e = 1, the core should not write any fields of this rxbd. 1 ? reserved, should be cleared. 2 w wrap (final bd in rxbd table) 0 not the last bd in the table. 1 last bd in the table. after this bu ffer is used, the cp receives incomi ng data into the first bd that rbase points to in the table. the number of rxbds in this table is programmable and determined only by the w bit. the rxbd table must contain more than one bd in ethernet mode. 3 i interrupt 0 no interrupt is generated after this buffer is used. 1 fcce[rxb] or fcce[rxf] are set when this buffer is used by the ethernet controller. these two bits can cause interrupts if they are enabled. 4 l last in frame. set by the ethernet controller when this buffer is the last in a frame. this implies the end of the frame or a reception error, in which case one or more of the cl, ov, cr, sh, no, and lg bits are set. the ethernet controller writes the number of frame octets to the data length field. 0 not the last buffer in a frame 1 last buffer in a frame 5 f first in frame. set by the ethernet controlle r when this buffer is the first in a frame. 0 not the first buffer in a frame 1 first buffer in a frame 6 cmr cam match result for the frame. set by the ethernet controller when using a cam for address matching and fpsmr[ecm] = 1. valid only if the l bit is set. 0 a hit in the cam 1 a miss in the cam 4 datasheet u .com
cpm fast ethernet controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 40-26 freescale semiconductor data length is the number of octets th e cp writes into this bd data buffer. it is written by the cp as the buffer is closed. when this bd is the last bd in the frame (rxbd[l] = 1), the data length contains the total number of frame octets (including f our bytes for crc). note that at least as much memory should be allocated for each receive buffer as the size specified in mrblr. mrblr should be divisible by 32 and not less than 64. the receive buffer pointer, which points to the first location of the associ ated data buffer, can reside in external memory. this value must be divisible by 32. when a received frame?s data length is an exact multip le of mrblr, the last bd contains only the status and total frame length. note at least two bds must be prep ared before beginning reception. 7 m miss. set by the ethernet controller for frames that are accepted in promiscuous mode, but are flagged as a miss by the internal address recognition. thus, while us ing promiscuous mode, the user uses the miss bit to determine quickly whether the frame is destined for this station. valid only if rxbd[i] is set. 0 the frame is received because the address is recognized. 1 the frame is received because of promiscuous mode (address is not recognized). 8 bc broadcast address. valid only for the last buffer in a frame (rxbd[l] = 1). the received frame address is the broadcast address. 9 mc multicast address. valid only for the last buffer in a frame (rxbd[l] = 1). the received frame address is a multicast address other than a broadcast address. 10 lg rx frame length violation. a frame length greater th an the mflr (maximum frame length) defined for this fcc is recognized. 11 no rx nonoctet aligned frame. a frame that contained a numb er of bits not divisible by eight is received and the crc check at the preceding byte boundary generated an error. 12 sh short frame. a frame length less than the minflr (minimum frame length) defined for this channel is recognized. this indication is possible only if the fpsmr[rsh] = 1. 13 cr rx crc error. this frame contains a crc error. 14 ov overrun. a receiver overrun occurred during frame reception. 15 cl collision. this frame is closed because a collision occurr ed during frame reception. set only if a late collision occurs or if fpsmr[rsh] is set. the late collision definition is deter mined by the setting of fpsmr[lcw]. table 40-11. rxbd field descriptions (continued) bits name description 4 datasheet u .com
cpm fast ethernet controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 40-27 figure 40-11 shows how rxbds are used during ethernet reception. figure 40-11. ethernet receiving using rxbds 40.20 ethernet txbds data is sent to the ethernet c ontroller for transmission on an fcc channel by arranging it in buffers referenced by the channel?s txbd table. the ethernet controller uses txbds to confirm transmission or buffer 0 0x0040 32-bit buffer pointer 1 ef receive bd 0 status length pointer 0 0x0045 32-bit buffer pointer 0 ef receive bd 1 status length pointer 1 xxxx 32-bit buffer pointer e receive bd 2 status length pointer 1 xxxx 32-bit buffer pointer e receive bd 3 status length pointer destination address source address (6) type/length (2) buffer crc bytes (4) tag byte (1) buffer buffer old data from empty 64 bytes 64 bytes 64 bytes 64 bytes two frames received in ethernet collision line idle present time time buffer full buffer closed after crc received. buffer still empty empty mrblr = 64 bytes for this fcc empty data bytes (50) optional tag byte collision causes buffer to be reused 0 l 1 l frame 2 collided frame will be overwritten appended non-collided ethernet frame 1 (6) 4 datasheet u .com
cpm fast ethernet controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 40-28 freescale semiconductor indicate errors so the core knows when buffers have been serviced. figure 40-12 shows the fcc ethernet txbd format. table 40-12 describes ethern et txbd fields. 0123456789101112131415 offset + 0 rpadw i l tc def hb lc rl rc un csl offset + 2 data length offset + 4 tx data buffer pointer offset + 6 figure 40-12. fast ethernet transmit buffer (txbd) table 40-12. ethernet txbd field definitions field name 1 description 0 r ready 0 the buffer associated with this bd is not ready for tr ansmission; the user can manipulate this bd or its associated buffer. the cp clears r after t he buffer has been sent or after an error. 1 the buffer is ready to be sent. the buffer is either waiting or in the process of being sent. the user cannot change fields in this bd or its associated buffer once r = 1. 1 pad short frame padding. valid only when l = 1; otherwise, it is ignored. 0 do not add pads to short frames. 1 add pads to short frames. pad bytes are inserted until the length of the transmitted frame equals the minflr. the pad bytes are stored in a buffer pointed to by pad_ptr in the parameter ram. 2 w wrap (final bd in table) 0 not the last bd in the txbd table. 1 last bd in the txbd table. after this buffer is used, the cp receives incoming data into the first bd that tbase points to in the table. the number of txbds in this table is programmable and determined only by the w bit. the txbd table must contain more than one bd in ethernet mode. 3 i interrupt 0 no interrupt is generated after this buffer is serviced. 1 fcce[txb] or fcce[txe] is set after this buffer is se rviced. these bits can cause interrupts if they are enabled. 4 l last 0 not the last buffer in the transmit frame. 1 last buffer in the current transmit frame. 5 tc tx crc. valid only when the l bit is set; otherwise, it is ignored. 0 end transmission immediately after the last data byte. 1 transmit the crc sequence after the last data byte. 6 def defer indication. this frame did not have a collision before it was sent but it was sent late because of deferring. 7 hb heartbeat. the collision input is not asserted within 40 transmit serial clocks following completion of transmission. this bit cannot be set unless fpsmr[hbc] = 1. written by the ethernet controller after sending the associated buffer. 8 lc late collision. a collision occurred after the number of bytes defined in fpsmr[lcw] (56 or 64) are sent. the ethernet controller terminates the transmission and updates lc after sending the buffer. 4 datasheet u .com
cpm fast ethernet controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 40-29 data length is the number of octets the ethernet controller should tran smit from this bd data buffer. this value should be greater than zero. the cp never modifies the data length in a txbd. tx data buffer pointer, which contains the address of the associated data buffer, can be even or odd. the buffer can reside in external memory. th e cp never modifies the buffer pointer. 9 rl retransmission limit. the transmitter failed (ret_lim + 1) attempts to successful ly send a message due to repeated collisions. the ethernet controller updates rl after sending the buffer. 10?13 rc retry count. indicates the number of retries required fo r this frame to be successfully sent. if rc = 0, the frame is sent correctly the first time. if rc = 15 and ret _lim = 15 in the parameter ram, 15 retries were needed. if rc = 15 and ret_lim > 15, 15 or more retries we re needed. the ethernet controller updates rc after sending the buffer. 14 un underrun. the ethernet controller encountered a transmitter underrun cond ition while sending the associated buffer. the ethernet controller updates un after sending the buffer. 15 csl carrier sense lost. carrier sense is lost during fr ame transmission. the ethernet controller updates csl after sending the buffer. 1 boldfaced entries must be initialized by the user. table 40-12. ethernet txbd fi eld definitions (continued) field name 1 description 4 datasheet u .com
cpm fast ethernet controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 40-30 freescale semiconductor 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 41-1 chapter 41 atm controller the atm controller provides the atm and aal layers of the atm pr otocol using the universal test and operations physical layer (phy) interf ace for atm (utopia level ii) for both master and slave modes. it performs segmentation and reassemb ly (sar) functions of aal5, aa l2, and aal0, and most of the common parts of the convergence subl ayer (cp-cs) of these protocols. for each virtual channel (vc), the controller?s atm pace control (apc ) unit generates a cell transmission rate to implement constant bit rate (cbr), variable bit rate (vbr), av ailable bit rate (a br), unspecified bit rate (ubr) or ubr+ tr affic. to regulate vbr traffic, the ap c unit performs a co ntinuous-state leaky bucket algorithm. the apc unit also uses up to eight prio rity levels to prioritize real-time atm channels, such as cbr and real-time vbr, over non-real-time atm channels such as vbr, abr, and ubr. the atm controller performs the atm forum (uni-4.0) abr flow control. to perform feedback rate adaptation, it supports forward and backward resource management (r m) cell generation and atm forum floating-point calculation. ab r flow control is implem ented in hardware and fi rmware (without software intervention) to prevent potential delays during backward rm cell processing and feedback rate adaptation. the MPC8555E supports a special m ode for atm/tdm interworking. th e cpm performs au tomatic data forwarding without core intervention. the MPC8555E atm sar controller applications are as follows: ? atm line card controllers ? atm-to-wan interworking (frame relay, t1/e1 circuit emulation) ? residential broadband network inte rface units (niu) (atm-to-ethernet) ? high-performance atm netw ork interface cards (nic) ? bridges and routers with atm interface 41.1 features the atm controller has the following features: ? full duplex segmentation and reassembly at 155 mbps ? utopia level ii master and slave modes 8 bit ? aal5, aal1, aal2, aal0 protocols ? up to 255 active vcs internally, and up to 64k vcs using external memory ? tm 4.0 cbr, vbr, ubr, ubr+ traffic types ? vbr type 1 and 2 traffic using leaky buckets (gcra) ? tm 4.0 abr flow control (efci and er) 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 41-2 freescale semiconductor ? idle/unassign cells screen ing/transmission option ? external and internal rate transmit modes ? special mode for atm-to-port 2 or atm-to-atm data forwarding ? clp and congestion indication marking ? user-defined cells up to 65 bytes ? separate txbd and rxbd tables for each virtual channel (vc) ? special mode of global free buffer pools for dyna mic and efficient memory allocation with early packet discard (epd) support ? interrupt report per channel usi ng four priority interrupt queues ? compliant with atmf un i 4.0 and itu specification ? aal5 cell format ? reassembly ? reassemble pdu directly to external memory ? crc32 check ? clp and congestion report ? cpcs_uu, cpi, and length check ? abort message report ? segmentation ? segment pdu directly from external memory ? performs pdu padding ? crc32 generation ? automatic last cell marking ? automatic cpcs_uu, cpi, and length insertion ? abort message option ? aal1 cell format ? reassembly ? reassemble pdu directly to external memory ? support for partially filled cells (configurable on a per-vc basis) ? sequence number check ? sequence number protection (crc-3 and parity) check ? segmentation ? segment pdu directly from external memory ? partially filled cells support (c onfigurable on a per-vc basis) ? sequence number generation ? sequence number protection (crc-3 and even parity) generation 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 41-3 ? structured aal1 cell format ? automatic synchronization using the structured pointer during reassembly ? structured pointer generation during segmentation ? unstructured aal1 cell format ? clock recovery using external srts (s ynchronous residual time stamp) logic during reassembly ? srts generation using extern al logic during segmentation ? aal0 format ? receive ? whole cell is put in memory ? crc10 pass/fail indication ? transmit ? reads a whole cell from memory ? crc10 insertion option ? aal2 format ? refer to chapter 42, ?atm aal2? ? support for user-defined cells ? support cells up to 65 bytes ? extra header insert/l oad on a per-frame basis ? extra header size has byte resolution ? asymmetric cell size for send and receive ? hec octet insertion option ?phy ? utopia level ii supports 8 bits 25/50 mhz ? supports utopia master and slave modes ? supports cell-level handshake ? supports multiple-phy polling mode ? atm pace control (apc) unit ? peak cell rate pacing on a per-vc basis ? peak-and-sustain cell rate paci ng using gcra on a per-vc basis ? peak-and-minimum cell rate pacing on a per-vc basis ? up to eight priority levels ? fully managed by cp with no host intervention ? available bit rate (abr) ? performs atmf uni 4.0 abr flow control on a per-vc basis ? automatic forward-rm, ba ckward-rm cells generation ? automatic feedback rate adaptation 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 41-4 freescale semiconductor ? support for efci (explicit forward congest ion indication) and er (explicit rate) ? rm cell floating- point calculations ? fully managed by cp with no host intervention ? receive address look-up mechanism ? two modes of addres s look-up are supported ? external cam ? address compression ? oam (operations and maintenance) cells ? oam filtering according to pt i field and reserved vci field ? raw cell queues for tran smission and reception ? crc-10 generation/check ? performance monitoring support ? support up to 64 bidirectional block tests simultaneously ? automatic fmc and brc cell generation and termination ? user transmit cell 0+1 count ? user transmit cell 0 count ? pm cells time stamp insertion ? block error detection code (bedc 0+1 ) generation/check ? total receive cell 0+1 count ? total receive cell 0 count ? specifying channel code for f5 oam cells ? atm layer statistic gathering on a per phy basis. ? utopia receiver error cells count (rx pa rity error or short/long cells error) ? misinserted cell count ? crc-10 error cells count (abr flow only) ? memory management ? rxbd table per vc with option of global free buffer pool for aal5 ? txbd table per vc 41.2 atm controller overview the following sections provide an ov erview of the transmitte r and receiver portions of the atm controller. 41.2.1 transmitter overview before the transmitter is enabled, the host must in itialize the MPC8555E and cr eate the tran smit data structure, described in section 41.10, ?atm memory structure.? when data is ready for transmission, the host arranges the bd table a nd writes the pointer of the first bd in the transmit connection table (tct). the host issues an atm transmit command, which inserts the current channel to the atm pace control 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 41-5 (apc) unit. the apc unit controls the at m traffic of the transmitter. it r eads the traffic parameters of each channel and divides the total bandwidth among th em. the apc unit can pace the peak cell rate, peak-and-sustain cell rate (gcra traffic) or peak -and-minimum cell rate traffic. the apc implements up to eight priority levels for servicing real -time channels before non-real-time channels. the transmitter atm cell is 53?65 byt es and includes 4 bytes of atm cell header, a 1-byte hec, and 48 bytes of payload. the hec is a constant taken from fdsr x [8?15]; see section 37.5, ?fcc data synchronization registers (fdsrx).? user-defined cells (udc mode) include an extra header of 1?12 bytes with an optional hec octet. cell transfers use the utopia level ii, cell-level handshake. transmission starts when the apc sc hedules a channel. according to th e channel code, the atm controller reads the channel?s entry in the tct and opens the fi rst bd for transmission. in auto-vc-off mode, the apc automatically deactivates the current channel when no buffer is ready to transmit. in this case, a new atm transmit command is needed for transmission of the vc to resume. 41.2.1.1 aal5 transmitter overview the transmitter reads 48 bytes from the external buffer, adds the ce ll header, and sends the cell through the utopia interface. the transmitter ad ds any padding needed and appends the aal5 trailer in the last cell of the aal5 frame. the trailer consists of cpcs- uu+cpi, data length, and crc-32 as defined in itu i.363. the cpcs-uu+cpi (2-byte entry) can be speci fied by the user or optionally cleared by the transmitter; see section 41.10.2.3, ?transmit connection table (tct).? the transmitter identifies the last cell of the aal5 message by setting the last (l) indi cation bit in the pti field of the cell header. an interrupt may be generated to i ndicate the end of the frame. when the transmission of the current frame ends and no additional valid buffers are in the bd table, the transmit process ends. the transmitte r keeps polling the bd ta ble every time this ch annel is scheduled to transmit. note that a buffer-not-ready indication dur ing frame transmission abor ts the frame transfer. 41.2.1.2 aal1 transmitter overview the MPC8555E supports both structured and unstructure d aal1 formats. for the unstructured format, the transmitter reads 47 bytes from the external buffer and inserts them in to the aal1 user data field. the aal1 pdu header, which consists of the sequence number (sn) and the sequence number protection (snp) (crc-3 and parity bit), is generated and inserted into the cell. the MPC8555E supports synchronous residual time stamp (srt s) generation using external pll. if this mode is enabled, the MPC8555E reads the srts code from the external logic and inserts it into four outgoing cells. for the structured format, the transmitter reads 47 or 46 bytes from the external buffer and inserts them into the aal1 user data field. the cp generates the aal1 pdu header and inserts it into the cell. the header consists of the sn, sn p, and the structured pointer. the MPC8555E supports partially fill ed cells configured on a per-vc basis. in this mode (tct[pfm] = 1), only valid octets are copied from the buffer to the atm cel l; the rest of the cell is filled with padding octets. 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 41-6 freescale semiconductor 41.2.1.3 aal0 transmitter overview no specific adaptation layer is pr ovided for aal0. the atm controller reads a whole cell from an external buffer, which always contains ex actly one aal0 cell. the atm cont roller optionally generates crc10 on the cell payload and plac es it at the end of the payload (crc10 field). aal0 m ode can be used to send oam cells or aal3/4 raw cells. 41.2.1.4 aal2 transmitter overview refer to section 42.3.1, ?transmitter overview.? 41.2.1.5 transmit external rate and internal rate modes the atm controller supports th e following two rate modes: ? external rate mode?the total transmission rate is determined by the ph y transmission rate. the fcc sends cells to keep the phy fifos full; the fcc inserts idle/unassign cells to maintain the transmission rate. ? internal rate mode?the total transmission rate is determined by the fcc internal rate timers. in this mode, the fcc does not insert idle/unassign cells. the internal rate mechanism supports up to 4 different rates. each phy ha s its own ftirr, described in section 41.13.5, ?fcc transmit internal rate registers (ftirrx).? the ftirr includes the initial value of the internal rate timer. a cell transmit request is sent when an internal ra te timer expires. when us ing internal rate mode, the user assigns one of the baud-ra te generators (brgs) to clock the four internal rate timers. 41.2.2 receiver overview before the receiver is enabled, the hos t must initialize the MPC8555E and create the receive data structure described in section 41.10, ?atm memory structure.? the host arranges a bd table for each atm channel. buffers for each connection can be statically allocated (that is, each bd in the bd table is associated with a fixed buf fer location) or in the ca se of aal5, can be fetche d by the cp from a global free buffer pool. see section 41.10.5, ?atm controller buffer descriptors (bds).? the receiver atm cell size is 53?65 bytes. the cell in cludes: 4 bytes atm cell header, 1 byte hec, which is ignored, and 48 bytes payload. user-defined cells (udc mode) include an extra header of 1?12 bytes with an optional hec octet. ce ll transfers use the utopia level ii, cell-level handshake. reception starts when the phy assert s the receive cell available signal (r xclav) to indicate that the phy has a complete cell in its receive fi fo. the receiver reads a complete cell from the utopia interface and translates the header address (vp/ vc) to a channel code by performi ng an address look-up. if no matches are found, the cell is discarded and the user-network interface (uni) statistics tables are updated. the receiver uses the channel code to read the channel parameters from the recei ve connection table (rct). 41.2.2.1 aal5 receiver overview the receiver copies the 48-byte ce ll payload to the external buffer and calculates crc-32 on the entire cpcs-pdu. when the last aal5 cell arrive s, the receiver checks the length, crc-32, and cpcs-uu+cpi fields and sets the corresponding rxbd st atus bits. an interrupt may be generated to one 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 41-7 of the four interrupt queues. the receiver copies the last cell to me mory including the padding and the aal5 trailer. the cpcs-uu+cpi ( 16-bit entry) may be read dire ctly from the aal5 trailer. the atm controller monitors the cl p and cng state of the incoming cell s. when the message is closed, these events set rxbd[clp] and rxbd[cng]. when no buffer is ready to receive cel ls (busy state), the rece iver switches to hunt st ate and drops all cells associated with the current frame (p artial packet discard). the receiver tries to open new buffers for cell reception only after the last cell of the discarded aal5 frame arrives. 41.2.2.2 aal1 receiver overview the atm controller supports both aal1 structured and unstructure d formats. for the unstructured format, 47 octets are copied to the current receive buffer. the aal1 pdu header, which consists of the sequence number (sn) and the sequence number protection (s np) (crc-3 and parity bit), is checked. the MPC8555E supports srts clock recovery using an external pll. in th is mode, the MPC8555E tracks the srts from the four incoming cells and wr ites the srts code to external logic. in the unstructured format, when the receive process begins, the receiver hunts for the first cell with a valid sequence number (sn field). when one arrives, the re ceiver leaves the hunt stat e and starts receiving. if an sn mismatch is detected, the receiver closes the rxbd, sets the sequence number error flag (rxbd[sne]), and switches to hunt state, where it stays until a cell with a valid sn field is received. for the structured format, 47 or 46 octets are copied to the current receive buffer. th e aal1 pdu header, which consists of sn and snp, is checked and the pdu status is written to the bd. in the structured format, when the receive process begins, th e receiver hunts for the first cell with a valid structured pointer to gain synchroni zation. when one arrives, the receiver leaves the hunt state and starts receiving. then the receiver opens a new buffer. the st ructured pointer points to the first octet of the structured block, which then becomes the first byte of the new buffer. if an sn mismatch is detected, the atm receiver closes the current rxbd , sets rxbd[sne], and returns to the hunt state. the receiver then waits for a cell with a valid structur ed pointer to regain synchronization. the MPC8555E supports partially fill ed cells configured on a per-vc basis. in this mode (rct[pfm] = 1), the atm controller copies only the valid octe ts from the cell user data field to the buffer. 41.2.2.3 aal0 receiver overview for aal0, no specific adaptation laye r processing is done. the atm contro ller copies the whole cell to an external buffer. each buffer c ontains exactly one aal0 cell. the at m controller calculates and checks the crc10 of the cell payl oad and sets rxbd[ cre] if a crc error occurs. aal 0 mode can be useful for receiving oam cells or aal3/4 raw cells. 41.2.2.4 aal2 receiver overview refer to section 42.4.1, ?receiver overview.? 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 41-8 freescale semiconductor 41.2.3 performance monitoring the atm controller supports performance monitori ng testing according to itu i.610. when performance monitoring is enabled, the atm controller automati cally generates and terminates fmcs (forward monitoring cells) and brcs (b ackward reporting cells). see section 41.6.6, ?performance monitoring.? 41.2.4 abr flow control when aal5-abr is enabled, the atm controller implements the atm fo rum tm 4.0 available-bit-rate flow. it automatically inserts forw ard- and backward-rm cells into th e user cell stream and adjusts the transmission rate according to the backwards rm cell feedback; see section 41.10.2.2.2, ?aal5-abr protocol-specific rct.? the abr flow is controlled on a per-vc basis. 41.3 atm pace control (apc) unit the atm pace control (apc ) unit schedules the atm channels fo r transmitting. while performing this task, the apc unit uses the following parameters: ? frequency (bandwidth) of each atm channel ? atm traffic pacing?peak cell rate (pcr), su stain cell rate (scr), and minimum rate (mcr) ? priority level?real-time channe ls (cbr or vbr-rt) are schedul ed at high-priority levels; non-real-time channels (vbr-nrt, a br, ubr) are scheduled at low- priority levels. up to eight priority levels are available. 41.3.1 apc modes and atm service types the atm forum (http://www.atmforum.com) defines the service types described in table 41-1 . for information about cell rate pacing, see section 41.3.5, ?atm traffic type.? for information about prioritization, see section 41.3.6, ?determining the pr iority of an atm channel.? table 41-1. atm service types service type cell rate pacing real-time/ non-real-time relative priority cbr pcr rt 1 (highest) vbr-rt pcr, scr (peak-and-sustain) rt 2 vbr-nrt pcr, scr (peak-and-sustain) nrt 3 abr 1 1 when abr flow control is active, the cp automatically adapts the apc parameters pcr, pcr_fraction. these parameters function as the channel?s allowed cell rate (acr). pcr nrt 4 ubr+ pcr, mcr (peak-and-minimum) nrt 5 ubr pcr nrt 6 (lowest) 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 41-9 41.3.2 apc unit scheduling mechanism the apc unit consists of an apc data structure in the dual-port ram for each phy and a special scheduling algorithm performed by the cp. each phy? s apc data structure includes three elements: an apc parameter table, an apc priority table, and cell transmission scheduling tables for each priority level. (see section 41.10.4, ?apc data structure.? ) each phy?s apc parameter table holds parameters that define the prio rity table location, the number of priority levels, and other apc para meters. the priority table holds poi nters that define the location and size of each priority le vel?s scheduling table. each scheduling table is divided into time slots, as shown in figure 41-1 . the user determines the number of atm cells to be sent each time slot (cells per slot). after a channel is sent, it is removed from the current time slot and advanced to a future time slot according to the channel?s assigned traffic rate (specified in time slots). the pcr parame ter in the tct, or the scr or mcr pa rameters in the tct extension (tcte) determine the channel?s actual rate. figure 41-1. apc scheduling table mechanism each 2-byte time-slot entry points to one atm channel. additional channe ls scheduled to transmit in the same slot are linked to each other using the apc linke d-channel field in the tct. the linked list is not limited; however, if the numb er of channels for the current slot exce eds the cells per slot parameter (cps), the extra channels are sent in subs equent time slots. (the rescheduli ng of extra channels is based on the original slot to maintain each channel?s pace.) note that a channel can appear only once in the schedul ing table at a given time, because each channel has only one apc linked-channel field. 41.3.3 determining the scheduling table size the following sections describe how to determine the number of cells sent per time slot and the total number of slots needed in a scheduling table. 41.3.3.1 determining the cells per slot (cps) in a scheduling table the number of cells sent per time slot is determin ed by the channel with the maximum bit rate; see equation a. the maximum bit rate is achieved when a ch annel is rescheduled to the next slot. for example, if the line rate is 155.52 mbps and there are eight cells per slot, equati on a yields a maximum vc rate of 19.44 mbps. 1 5 9 4 6 7 8 2 3 cells per slot number of slots current slot cell rescheduling 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 41-10 freescale semiconductor note that a channel can appe ar only once per time slot; thus, 19.44 mbps = 155.52mbps/8. the cells per slot parameter (cps) affects the cell delay variation (c dv). because the apc unit does not put cells in a definite order within each time slot (lifo?last-in/first-out implementation), as cps increases, the cdv increases. howeve r as cps decreases, the size of the scheduling table in the dual-port ram increases and more cpm bandwidth is required. 41.3.3.2 determining the number of slots in a scheduling table the number of time slots in a scheduling table is de termined by the channel with the minimum bit rate; see equation b. the minimum bit rate is achieved when the channel reschedules only once in a whole table scan. (the maximum schedule advance allowed is equal to number_of_slots ? 1.) for example, if the line rate is 155.52 mbps, the minimum bit rate is 32 kbps and th e cps is 4, then, according to equation b, the number of slots should be 1,216. note the following apc configuration is not recommended for values outside the following ranges (pcr = peak cell rate, pcrf = peak cell rate fraction, nos = number of slots): pcr = 1 and pcrf = 0 pcr = nos ? 1 and pcrf = 0 for the above example, 32 kbps = 155.52 mbps/((1216-1) 4). use equations (a) and (b) to obtain the maximum a nd minimum bit rates of a scheduling table. for example, given a line rate = 155.52 m bps, number_of_slots = 1025, and cps = 8: 41.3.4 determining the time-slot scheduling rate of a channel the time-slot scheduling rate of each atm channel is defined by equation c. th e resulting number of apc slots is written in either tct[pcr], tcte[s cr] or tcte[mcr], dependi ng on the traffic type. max bit rate = (a) line rate cells per slot min bit rate = (b) (number_of_slots - 1) cells per slot line rate max bit rate = (155.52 mbps)/8 = 19.44 mbps min bit rate = (155.52 mbps)/(1024 8) = 18.98 kbps rate [slots] = (c) vc rate [bps] cells per slot line rate [bps] 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 41-11 41.3.5 atm traffic type the apc uses the cell rate pacing parameters (pcr, scr, and mcr) to gene rate cbr, vbr, abr, ubr+, and ubr traffic. the user determines the kind of traffic that is generate d per vc by writing to tct[att] (atm traffic type); see section 41.10.2.3, ?transmit connection table (tct).? 41.3.5.1 peak cell rate traffic type when the peak cell rate traffic type is selected, th e apc schedules channels to transmit according to the pcr and pcr_fraction traffic parameters. other traffi c parameters do not apply to this traffic type. 41.3.5.2 determining the pcr traffic type parameters suppose a vc uses 15.66 mbps of the total 155.52 mbps and cps = 8. equation c yields: the resulting number of slots is written into tct[pcr] a nd tct[pcr_fraction]. because pcr_fraction is in units of 1/256 slots, the fraction must be converted as follows: 41.3.5.3 peak and sustain traffic type (vbr) variable bit rate (vbr) traffic can bur st at the peak cell rate as long as the long-term average rate does not exceed the sustainable cell rate. to support vbr cha nnels, the apc implements the gcra (generic cell rate algorithm) using three parameters?the peak cell rate (pcr), th e sustained cell rate (scr), and burst tolerance (bt), as shown in figure 41-2 . (the gcra is also known as the leaky bucket algorithm.) figure 41-2. vbr pacing using the gcra (leaky bucket algorithm) when a vbr channel is activated, it bursts at the peak cell rate (pcr ) until reaching its initial burst tolerance (bt), which is the buffer length the networ k allocated for this vc. when the burst limit is reached, the apc reduces the vc?s scheduling rate to the sustained cell rate (scr). the vc continues pcr [slots] = (155.52 mbps)/(15.66 mbps 8) = 1.241 1.241 = 1+0.241 256/256 =1+ 61.79/256 ~ 1 + 62/256 pcr = 1 pcr_fraction = 62 conforming vbr traffic burst tolerance (bt) sustained cell rate (scr) incoming cells fill the bucket at the peak cell rate ( pcr) or at the scr if the bucket is full. 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 41-12 freescale semiconductor sending at scr as long as txbds are ready. however, as each scr time allotment elapses with no txbd ready to send, the apc grants the vc a credit for bur sting at the peak cell rate (pcr). (gaining credit implies that the buffer at the switch is not full a nd can tolerate a burst transmission.) if a txbd becomes ready, the apc schedules the vc to burst at the pcr as long as credit remains. wh en the burst credit ends (the network?s upc leaky bucket r eaches its limit), the apc schedul es the vc according to scr. 41.3.5.3.1 example for usi ng vbr traffic parameters suppose the traffic parameters of a vbr channe l are pcr = 6 mbps, scr = 2 mbps, mbs (maximum burst size) = 1000 cells, and cps = 8. equation c (see section 41.3.4, ?determining the time-slo t scheduling rate of a channel? ) yields the apc parameters, pcr, pcr_fraction, scr, and scr_fraction, which the user writes to the channel?s tct. equation d yields the number of slots the user writes to the channel?s tct[bt]. 41.3.5.3.2 handling the cell loss prio rity (clp)?vbr types 1 and 2 the MPC8555E supports two ways to schedule vbr traffi c based on the cell loss priority (clp). when tcte[vbr2] is cleared, clp 0+1 cells are schedu led by pcr or scr according to the gcra state. when tcte[vbr2] is set, clp 0 cells are still scheduled by pcr or scr according to the gcra state, but clp 1 cells are always scheduled by pcr. see section 41.10.2.3.5, ?vbr prot ocol-specific tcte.? 41.3.5.4 peak and minimum cell rate traffic type (ubr+) to support ubr+ channels, the apc schedules transmission according to pcr and mcr. for each priority level, the apc maintains a parameter that moni tors the traffic load measur ed as the time-slot delay between the service pointer (pointing to the current time slot waiting transmission) and a real-time slot pointer. if the transmission delay is greater than mda (maximum delay allowed), the apc begins scheduling channels according to the mcr parameter. if the delay, however, drops below mda, the apc again schedules channels according to the pcr. note th at in order to guarantee a minimum cell rate for ubr+ channels, there must be enough bandwidth to simultaneously send all pos sible channels at the mcr. see section 41.10.2.3.6, ?ubr+ prot ocol-specific tcte.? pcr [slots] = (155.52 mbps)/(6 mbps 8) = 3.24 3.24 = 3 + 0.24 256/256 = 3 + 61.44/256 ~ 3 + 62/256 pcr = 3 pcr_fraction = 62 scr [slots] = (155.52 mbps)/(2 mbps 8) = 9.72 9.72 = 9 + (0.72 256/256) = 9 + 184.32/256 ~ 9 + 185/256 scr = 9 scr_fraction = 185 bt [slots] = (mbs[cells] ? 2) (scr[slots] ? pcr[slots]) + scr[slots] (d) = (1000 ? 2) ((9+185/256) ? (3+62/256)) + (9 +185/256) = 6477 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 41-13 41.3.6 determining the prio rity of an atm channel the priority mechanism is implemen ted by adding priority ta ble levels, which point to separate scheduling tables; see section 41.10.4, ?apc data structure.? the apc flow control services the apc_level1 slots first. if there are no cells to send, the apc goes to the next priority level. the ap c has up to eight priority levels with apc_level8 being the lowest. the user specifies the priority of an atm channel when issuing the atm transmit command; see section 41.14, ?atm transmit command.? the real-time channels, cbr and v br-rt, should be inserted in apc_level1; non-real-time channels, vbr-nrt, abr, and ubr should be in serted in lower priority levels. 41.4 vci/vpi address lookup mechanism the MPC8555E supports two ways to look up addresses for incoming cells: ? external cam lookup ? address compression writing to gmode[alm] (addre ss-lookup-mechanism bit) in th e parameter ram selects the mechanism. both mechanisms are de scribed in the following sections. 41.4.1 external cam lookup an external cam is usually used when the range of vci/ vpi values varies wide ly or is unknown. clearing gmode[alm] selects the external ca m address lookup mechanism. if ther e is no match in the external cam, the cell is considered a misinser ted cell. the external cam can point to internal or external channels (channels whose connection tabl e resides in external memory ). the cam input, shown in figure 41-3 , is the 32-bit cell address: phy address, gfc + vpi, and vci. note the bus atomicity mechanism for cam accesses may not function correctly when the cpm performs a dma access to an external cam device. this only impacts systems in which mu ltiple cpms will access the cam. the output of the cam, shown in figure 41-4 , is a 32-bit entry (16-bit channel code and a match-status bit). 034 1516 31 phy addr (mphy) gfc + vpi vci figure 41-3. external cam data input fields 0 1 15 16 31 ms ? channel code figure 41-4. external cam output fields 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 41-14 freescale semiconductor the external cam fields are described in table 41-2 . 41.4.2 address compression the address compression mechanism uses two levels of address translation to he lp minimize the memory space needed to cover the available address range. the first level of translation (vp-level) uses a look-up table based on the 4-bit phy address a nd the 12-bit virtual path identifier ; the second level (vc-level) uses the 16-bit virtual channel identifier. if there is no ma tch during address compression, the cell is considered a misinserted cell. during the vp-level translation, vp_mask in the atm parameter ram compresses an incoming cell?s phy address and vpi to create an index into the vp-l evel table. the vp-level table entry consists of another mask (vc_mask) and a pointer to one of th e vc-level tables (vcoffset). note that the vp table should reside in the dual-port ram. in the vc-level translation, the vci is compressed with the vc_mask to generate a pointer to the vc-level table entry containing the received cell?s chan nel code. the vc table should reside in external memory. table 41-2. external cam input and output field descriptions field description phy addr in multiple phy mode, this field contains the 4 least-significant bits of the current channel?s physical address. because this cam comparison field is limited to 4 bits, two cam devices are needed if using more than 16 phys.the msb of the phy address (bit 4) selects between the two devices. if the msb is zero, the cp accesses the cam whose address is written in the ext_cam_base pa rameter in the parameter ram; if the msb is set, the cp uses ext_cam1_base. see section 24.4.1, ?cmx utopia address register (cmxuar).? in single phy mode, clear this field. gfc+vpi, vci the gfc, vpi, and vci of the current channel. ch code pointer to internal or external connection table. ? reserved, should be cleared. ms match status. 0 match was found. 1 match was not found. 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 41-15 figure 41-5 shows an example of address compression. figure 41-5. address compression mechanism figure 41-5 shows vp_mask selecting five vpi bits to index the vp-level table. the vp-level table entry contains the 16-bit mask (vc_mask) and the vc-level table offset (vcoffset) for the next level of address mapping. the vc_mask select s vci bits 4?10, which is used with vct_base and vcoffset to indicate the received cell?s channel code. addr ess compression field descriptions are shown in table 41-3 . table 41-3. field descriptions for address compression field description phy addr in multiple phy mode, this field contains the 4 least-significant bits of the current channel?s physical address. because this comparison field is limited to 4 bits, two sets of look-up tables are needed if using more than 16 phys.the msb of the phy address (bit 4) selects between the two sets of tables. if the msb is zero, the cp accesses the tables at vpt_base and vct_base; if the msb is set, the cp uses vpt1_base and vct1_base. see section 24.4.1, ?cmx utopia address register (cmxuar).? in single phy mode, clear this field. vci, vpi the vci and vpi of the current channel. ch code pointer to internal or external connection table. 32-bit entries vp-level addressing table vpi 0000 00011111 vppointer vpt_base vcoffset vc_mask vci 00000111 11110000 vcpointer 32-bit entries vc-level addressing tables vct_base vp_mask 16 bit 16 bit phy addr 0000 16 bit 12 bit 4 bit (in external memory) (in dual-port ra m recommended) ch code[15?0] ? 16 bit 15 bit ms 1 bit 31 0 31 0 0b00011 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 41-16 freescale semiconductor 41.4.2.1 vp-level address compression table (vplt) the size of the vp-level table depends on the number of mask bits in vp_mask. for example, if only one phy is available (phy address = 0) and vpmask = 0b11_1111_1111, vp pointer contains ten bits and the table is 4 kbytes. because eac h vplt entry is 4 bytes, the addre ss of an entry is vpt_base + vp pointer 4. each vplt entry has two parameters: ? vc_mask?a 16-bit vc-level mask for masking the incoming cell?s vci ? vcoffset?a 16-bit vc-level table offset from vc_base that points to the appropriate vc-level table?s (vclt) starting address. the address of the vclt is vc_base + vcoffset 4. if the vclts are to be placed contiguously in memory, each table?s vcoffset depends on the size of preceding tables. each table?s size depends on the number of ones in vc_mask. figure 41-6 gives the general formul a for determining vcoffset. table 41-4 shows example vcoffset calculations fo r a vp-level table with four entries. the MPC8555E can check that all una llocated bits of the phy + vp i are 0 by setting gmode[cuab] (check unallocated bits) in the parameter ram. if th ey are not, the cell is c onsidered a misinserted cell. ? reserved, should be cleared. ms match status. 0 match was found. 1 match was not found. general formula: vcoffset (n+1) = vcoffset n + 2 (number of ones in vc_maskn) figure 41-6. general vcoffset formula for contiguous vclts table 41-4. vcoffset calculation examples for contiguous vclts vp-level table entry vc_mask number of ones in vc_mask vc-level table size vcoffset 0 0x0237 6 2 6 = 64 entries 0 1 0x0230 3 2 3 = 8 entries 64 2 0xa007 5 2 5 = 32 entries 64 + 8 = 72 3 x x x 72 + 32 = 104 table 41-3. field descriptions for address compression (continued) field description 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 41-17 table 41-5 gives an example of vp-level table entry address calculation. figure 41-7 shows the vp pointer ad dress compression from table 41-5 . figure 41-7. vp pointer address compression 41.4.2.2 vc-level address co mpression tables (vclts) each vplt entry points to a single vclt. like the vplt, the size of each vclt depends on vc_mask. because the vclt contains word entries, if vc _mask = 0b11_1111_1111, the table is 4 kbytes. the address of an entry in this table is vct_base + vcoffset 4 + vcpointer 4. the MPC8555E can check that al l unallocated vci bits are 0 by setting gmode[cuab] (check unallocated bits). if they are not, the cell is considered a misinserted cell. an example of vc-level table entr y address calculat ion is shown in table 41-6 . note that vcoffset is assumed to be 0x100 for this example. table 41-5. vp-level table entry address calculation example vpt_base vp-level table size vp_mask phy+vpi vp pointer vp entry address 0x0024_0000 64 entries 0x0237 0x0011 0x09 vp base = 0x240000 0x09 x 4 = 0x 000024 0x240024 table 41-6. vc-level table entry address calculation example vct_base vcoffset vc-l evel table size vc_mask vci vc pointer vc entry address 0x0084_0000 0x0100 32 entries 0x0037 0x0031 0x19 vc base = 0x840000 0x100 x 4 = 0x000400 0x19 x 4 = 0x 000064 0x840464 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 1 0 1 1 1 0 0 1 phy+vpi vp_mask vp pointer 1 0 0000 0000 0 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 41-18 freescale semiconductor figure 41-8 shows the vc pointer a ddress compression from table 41-6 . figure 41-8. vc pointer address compression 41.4.3 misinserted cells if the address lookup mechanism cannot find a match (ms = 1), the cell is discarded and atm layer statistics are updated, as described in section 41.8, ?atm la yer statistics.? 41.4.4 receive raw cell queue channel one in the rct is reserved as a raw cell queue. the user shoul d program channel one to operate in aal0 protocol. the receive raw cell queue is used for re moving management cells from the regular cell flow to the host. when a management cell is sent to the receive raw ce ll queue, the cp sets rxbd[oam]. the all0 bd specifies the channel code associated with the current oam cell. the following are optionally removed from the re gular flow and sent to the raw cell queue: ? segment f5 oam (pti = 0b100). to enab le f5 segment filtering, set rct[segf]. ? end-to-end f5 oam (pti = 0b101). to enable f5 end-to-end filtering, set rct[endf]. ? rm cells (pti = 0b110). when abr flow is enabled the cells are terminated internally; otherwise, they are sent to the raw cell queue. ? reserved pti value (pti = 0b111). always sent to the raw cell queue. ? vci value: 3, 4, 6, 7?15. to enable vci filtering se t the associated bit in the vcif entry in the parameter ram. 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 1 1 0 1 1 1 0 0 1 vci vc_mask vc pointer 1 1 0000 0000 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 41-19 figure 41-9 shows a flowchart of the atm cell flow. figure 41-9. atm address recognition flowchart note even reserved vci channels shoul d appear in the cam or address compression tables; otherwise, a cel l on a reserved channel will be considered misinserted. 41.5 available bit rate (abr) flow control while cbr service provides a fixed bandwidth and is useful for real-time appl ications with strictly bounded end-to-end cell transfer dela y and cell-delay variation, abr service is intended for data applications that can adapt to time-varying bandwidth and can tolerate significant cell transfer delay and cell delay variation. the MPC8555E implements the two following mechanisms defined by the atm forum tm 4.0 rate-based flow control. ? explicit forward congestion indi cation (efci). the network supplie s binary indication of whether congestion occurred along the connect ion path. this information is car ried in the pti field of the atm cell header (similar to that used in frame relay). the source initially clears ea ch atm cell?s efci bit, but as the cell passes through th e connection, any congested node can set it. the MPC8555E detects this indication an d sets the congestion indication (c i) bit in the next backwards rm cell to signal the s ource end station to reduce its transmission rate. ? explicit rate (er) feedback. th e network carries explicit bandw idth information, to allow the source to adjust its rate. the source sends forwar d rm cells specifying its chosen transmit rate (source er). a congested switch along the network may decrease er to the exact rate it can no pti=1xx or vci=3,4,6,7-15 and filter enable yes check address no match yes discard cell send cell to vc queue send cell to raw cell queue 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 41-20 freescale semiconductor support. the destination receives forward rm cells and returns th em to the source as backward rm cells. the MPC8555E implements source behavior by adjusting the rate according to each returning backward rm cell?s er. explicit rate feedback ha s several advantages over bi nary feedback (efci). expl icit rate feedback allows immediate source rate adaptation, el iminating rate oscillation caused by incremental rate changes. using the information in rm cells, the network can allo cate bandwidth evenly among active abr channels. 41.5.1 abr model figure 41-10 shows the MPC8555E abr model. figure 41-10. MPC8555E abr basic model the MPC8555E abr flow control implements both source and destination behavior. the MPC8555E abr flowchart is described in section 41.5.1.3, ?abr flowcharts.? 41.5.1.1 abr flow control source end-system behavior the MPC8555E?s implementation of abr flow contro l for end-system sources is described in the following steps: 1. an abr channel?s allowed cell rate (acr) lies between the minimum cell rate (mcr) and the peak cell rate (pcr). 2. acr is initialized to the initial cell rate (icr). 3. an f-rm (forward-rm) cell is se nt for every nrm data cell sent. if more than mr m cells are sent and the time elapsed since the last f-rm exceeds trm, an f-rm cell is sent. 4. when sending an f-rm cell, the cu rrent acr is written in the ccr (current cell rate) field of the rm cell. 5. when b-rm (backward-rm ) cell is received with ci = 1 (c ongestion indication), acr is reduced by acr rdf (rate decrease factor). after the re duction, the new acr is determined first by letting acrtemp be the min of (acr, er), and then taking the max of (acrtemp, mcr). 6. when b-rm is received with ci=0 and ni=0 (no increase ), acr is increased by rif pcr (rate increase factor). the new acr is determined firs t by letting acrt emp be the min of (acr, er), and then taking the max of (acrtemp, mcr). source behavior destination behavior nrm data cells f-rm cell b-rm cell update rate ccr,er er, ci, ni f-rm cell b-rm cell set ci, ni turn-around reduce er 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 41-21 7. before sending an f-rm cell, if more than adt f (acr decrease time factor) has elapsed since sending the last f-rm cell, acr is reduced to icr. in other words, if the source does not fully use its gained bandwidth, it loses it and re sumes sending at its initial cell rate. 8. before sending an f-rm cell and after action 7, if more than crm f-rm cells were sent since the last b-rm cell was received with bn=0 (backwa rd notification), the acr is reduced by acr cdf (cutoff decrease factor). 9. a source whose acr is less than the tag cell rate (tcr) sends out-of-rate cel ls at the tcr. this behavior is intended for sources whose rates were set to zero by the network. these sources should periodically sense the network state by sending out-of-rate rm cells. in this case data cells will not be sent. 10. an rm cell with an incorrect crc10 is disc arded and the uni statis tics tables are updated. 41.5.1.2 abr flow control dest ination end-system behavior the MPC8555E?s implementation of abr flow control fo r end-system destinations is described in the following steps: 1. a received f-rm cell is turned around and sent as a b-rm cells. 2. the dir field of the received f-rm cell is changed from 0 to 1 (backward dir). 3. the ccr and mcr fields are taken from the f-rm and is not changed. 4. the ci bit of the b-rm cell is set if the previous data cell arrived with efci = 1 (congestion bit in the atm cell header). 5. the er field of the turn around b- rm cells is limited by tcte[er-brm]. 6. if a f-rm cell arrives before th e previous f-rm cell was turned around (for the sa me connection), the new rm cell overwrites the old rm cell. 41.5.1.3 abr flowcharts the MPC8555E abr transmit and receive flow contro l is described in the following flowcharts. see figure 41-11 , figure 41-12 , figure 41-13 , and figure 41-14 . 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 41-22 freescale semiconductor figure 41-11. abr transmit flow start channel tx acr < tcr send rm (dir = forward, ccr = acr, er = pcr, ci = ni = 0, clp =1) schedule: time_to_send = now+1/tcr acr is low sent only exit rm/data in rate cell tx acr>=tcr out-of-rate cells at tcr source end-sys 9 ye s no 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 41-23 figure 41-12. abr transmit flow (continued) rm/data in rate cell tx count >= nrm or (count > mrm and now (last_rm+trm)) nrm=number of data cells between every rm cell mrm=fixed number=2 trm=max time between every f-rm cells. count=number of data cells from last f-rm. time = now - last_rm checking ?time-out factor? max time allowed between rm cells before a rate decrease is required. time >adtf acr = icr acr is too high idle adjust (?use it or loose it?) unack crm acr = acr-acrcdf acr = max(acr,mcr) unack=number of f-rm cells sent without any b-rm cell received. crm=max number of f-rm cells without any b-rm cell allowed before rate decrease is required. send rm (dir = forward, ccr = acr, er = pcr, ci = ni = clp = 0) count=0 last_rm = now first-turn = true unack = unack+1 exit first-turn = flag indicate s first turn of rm cell with priority over data cells. b-rm/data in rate cell tx f-rm in rate cell tx count = count+1 source end-sys 3 source end-sys 4 source end-sys 7 source end-sys 8 ye s no ye s no ye s no 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 41-24 freescale semiconductor figure 41-13. abr transmit flow (continued) b-rm/data in rate cell tx b-rm in rate cell tx turn-around and (first-turn or not data-in-queue) ci-ta = ci-ta || ci-vc send rm cell (dir = backwards, ccr-ta, er-ta, mcr-ta, ci-ta, ni-ta, clp=0) ci-vc = 0 turn-around = first-turn = false exit send data cell clp = efci = 0 count = count+1 schedule:time_to_send = now+1/acr exit data cell tx count = count+1 destination end-sys 1,2,3,4 ye s no 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 41-25 figure 41-14. abr receive flow b-rm cells rx ci = 1 acr = acr-acr rdf ni = 0 acr = acr+rif pcr acr = min(acr,pcr) acr = min(acr,er) acr = max(acr,mcr) bn = 0 unack = 0 exit the source generate this rm unack = number of f-rm in absence of b-rm = 0 source end-sys 5 source end-sys 1, 6 source end-sys 5, 6 ye s no ye s no no ye s 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 41-26 freescale semiconductor 41.5.2 rm cell structure table 41-7 describes the structure of th e rm cell supported by the mpc 8555e. for more in formation, see the abr flow-control traffic management sp ecification (tm 4.0) on the atm forum website. 41.5.2.1 rm cell rate representation rates in the rm cells are represente d in a binary floating-point format using a 5-bit exponent (e), a 9-bit mantissa (m), and a 1-bit nonzero flag (nz), as shown in figure 41-15 . the rate (in cells/second) is calculated as in figure 41-16 . figure 41-16. rate formula for rm cells table 41-7. fields and their positions in rm cells fields octet bits description value header 1?5 all atm cell header rm-vcc pti = 6 id 6 all protocol id 1 dir 7 0 direction of rm cell (0 = forward, 1 = backward) bn 7 1 backward notification (bn = 0, the ce ll was generated by the source; bn = 1, the cell was generated by the network or by the destination) ci 7 2 congestion indication. (1 = congestion, 0 = otherwise) ni 7 3 no increase indication. (1 = no increase allowed, 0 = otherwise) ra 7 4 not used (atm forum abr) 0 ? 7 5?7 reserved, should be cleared. 0 er 8?9 all explicit rate; see section 41.5.2.1 ccr 10?11 all current cell rate; see section 41.5.2.1 mcr 12?13 all minimum cell rate; see section 41.5.2.1 ql 14?17 all not used (atm forum abr) 0 sn 18?21 all not used (atm forum abr) 0 ? 22?51 all reserved, should be cleared. 0x6a for each byte ? 52 0?5 reserved, should be cleared. 0 crc-10 52 6?7 crc-10 53 all 012 67 15 0 nz exponent mantissa figure 41-15. rate format for rm cells rate 2 e 1 m 512 --------- - + ?? ?? nz = 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 41-27 initialize the traffic parameters (e r, mcr, pcr, or icr) in the abr protocol-specific connection tables using the rate formula in figure 41-16 . 41.5.3 abr flow control setup follow these steps to setup abr flow control: 1. initialize the abr data structure: rct, tct, rct-abr protocol -specific, tcte-abr protocol-specific. 2. initialize abr global paramete rs in the parameter ram. see section 41.10.1, ?parameter ram.? 3. program the aal-type in the rct a nd tct to aal5 and set tct[abrf]. note abr flow control is available only with aal5. 4. the time stamp timer generates the rm cell?s ti me stamp, which the abr flow control monitors to maintain source behavior in steps #3 and #7 of section 41.5.1.1, ?abr flow control source end-system behavior.? enable the time stamp timer by writing to the rtscr; see section 21.2.7, ?risc time-stamp control register (rtscr).? 5. initialize the abr parameters (cps_abr and line_rate_abr) in the apct; see section 41.10.4.1, ?apc parameter tables.? note that when using abr, the cps (cells per slot) parameter in the apcpt should be a power of two. 6. finally, send the atm transmit command to restart channel transmission. 41.6 oam support this section describes the MPC8555E?s support for atm-layer (f4 out-of-band, and f5 in-band) operations and maintenanc e (oam) of connections. alarm surveillance, con tinuity checking, remote defect indication, and loopba ck cells are supported using oam receiv e and transmit aal0 cell queues. using dedicated support, performan ce management block tests can be performed on up to 64 connections simultaneously. the cp automatically inserts forward monitoring cells (fmc) and generates backward-reporting cells (brc) as recommended by itu i.610. 41.6.1 atm-layer oam definitions table 41-8 lists pre-assigned header values at the user-network interface (uni). table 41-8. pre-assigned header values at the uni use gfc vpi vci pti clp segment oam f4 flow cell xxxx aaaa_aaaa 0000_0000_0000_0011 0a0 a end-to-end oam f4 flow cell xxxx aaaa_aaaa 0000_0000_0000_0100 0a0 a segment oam f5 flow cell xxxx aaaa_aaaa aaaa_aaaa_aaaa_aaaa 100 a end-to-end oam f5 flow cell xxxx aaaa_aaaa aaaa_aaaa_aaaa_aaaa 101 a a = available for use by the appropriate atm layer function 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 41-28 freescale semiconductor table 41-9 lists pre-assigned header values at the network-node interface (nni). 41.6.2 virtual path (f4) flow mechanism the f4 flow is designated by pre-assigned virtual channe l identifiers within the vi rtual path. the following two kinds of f4 flows can exist simultaneously: ? end-to-end (identified as vci 4)?this flow is used for end-to-end vpc operations communications. cells inserted in to this flow can be removed onl y by the endpoints of the virtual path. ? segment (identified as vci 3) ?this flow is used for commun icating operations information within one vpc link or among multiple interconnect ed vpc links. the concat enation of vpc links is called a vpc segment. cells inserted into this flow can be removed only by the segment endpoints, which must remove these cells to prevent conf usion in adjacent segments. 41.6.3 virtual channel (f5) flow mechanism the f5 flow is designated by pre-as signed payload type iden tifiers. the following two kinds of f5 flow can exist simultaneously: ? end-to-end (identified by pti = 5)?this flow is used for end-to-end vcc operations communications. cells inserted into this flow can be removed only by vc endpoints. ? segment (identified by pti = 4)?this flow is used for communicating operations information with the bound of one vcc link or multiple inte rconnected vcc links. a concatenation of vcc links is called a vcc segment. segment endpoints must remove th ese cells to prevent confusion in adjacent segments. 41.6.4 receiving oam f4 or f5 cells oam f4/f5 flow cells are received us ing the raw cell queue, described in section 41.4.4, ?receive raw cell queue.? an f4/f5 oam cell which does not appear in the cam or address compression tables is considered a misinserted cell. 41.6.5 transmitting oa m f4 or f5 cells oam f4/f5 flow cells are sent using the usual aa l0 transmit flow. for oam f4/f5 cell transmission, program channel one in the tct to operate in aal0 m ode. enable the cr10 (crc-10 insertion) mode as table 41-9. pre-assigned header values at the nni use vpi vci pti clp segment oam f4 flow cell aaaa_aaaa_aaaa 0000_0000_0000_0011 0a0 a end-to-end oam f4 flow cell aaaa_aaaa_aaaa 0000_0000_0000_0100 0a0 a segment oam f5 flow cell aaaa_aaaa_aaaa aaaa_aaaa_aaaa_aaaa 100 a end-to-end oam f5 flow cell aaaa_aaaa_aaaa aaaa_aaaa_aaaa_aaaa 101 a a= available for use by the appropriate atm layer function 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 41-29 described in section 41.10.2.3.3, ?aal0 prot ocol-specific tct.? prepare the oam f4/f5 flow cell and insert it in an aal0 txbd. finally, issue a atm transmit command to send the oam cell. for multiple phys, use several aal0 ch annels?each phy should have one transmit raw cell queue that is associated with its scheduling table. a series of oam cells can be sent using one atm transmit command by creating a table of aal0 txbds. if the channel?s tct[avcf] (auto vc off) is set, the transmitter automatically removes it from the apc (that is, it does not genera te periodic transmit requests for th is channel after all aal0 bds are processed). 41.6.6 performance monitoring a connection?s performance is monitored by inspecting blocks of cells (delimit ed by forward monitoring cells) sent between connect ion or segment endpoints. ea ch fmc contains statisti cs about the immediately preceding block of cells. when an endpoi nt receives an fmc, it adds the statistics generated locally across the same block to produce a backward reporting cell (brc), which is then returned to the opposite endpoint. the MPC8555E can run up to 64 bidirect ional block tests simulta neously. when a bidirectional test is run, fmcs are generated for one dire ction and checked for the opposite. figure 41-17 shows the fmc and brc cell structure. figure 41-17. performance monitoring cell structure (fmcs and brcs) header = 5 bytes payload = 48 bytes 0010 = performance management oam cell ty p e function ty p e gfc/ vpi vci pti clp hec function specific fields reserved vpi 44 6 45 x 8 10 crc-10 unused 2 octets 4 octets 1 octet 29 octets 2 octets time- stamp total user cell 0+1 2 octets count 1 octet 0000 = forward monitoring (fmc) 0001 = backward reporting (brc) monitoring sequence number block error result to t a l received cells 0+1 2 octets total user cell 0 count 2 octets to t a l received cells 0 block error detection code (mcsn) (tuc0+1) (bedc0+1) 1 (tuc0) (tstp) (trcc0) 2 (bler) 2 (trcc0+1) 2 1 bedc 0+1 appears in fmcs only. 2 trcc 0 , bler, and trcc 0+1 appear in brcs only. 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 41-30 freescale semiconductor table 41-10 describes performance monitoring cell fields. 41.6.6.1 running a performance block test for bidirectional pm block te sts, fmcs are monitored at the receive side and genera ted at the transmit side. the following setup is required to run a bidirectional pm block test on an active vcc: 1. assign one of the available 64 performance moni toring tables by writi ng to both rct[pmt] and tct[pmt] and initializing the one chosen. see section 41.10.3, ?oam performance monitoring tables.? 2. for pm f5 segment termination set rct[segf ]; for pm f5 end-to-end termination set rct[endf]. 3. finally, set the channel?s rct[pm] and tct[pm] and the receive raw cell?s rct[pm]. for unidirectional pm block tests: ? for pm block monitoring only, set only the rct fields above. ? for pm block generation only, set only the tct fields above. to run a block test on a vpc, assign all the vccs of the tested vpc to the same performance monitoring table. configure rct[pmt] and tct[ pmt] to specify the performance monitoring table associated with each f4 channel. 41.6.6.2 pm block monitoring pm block monitoring is done by the receiver. after initialization (see section 41.6.6.1, ?running a performance block test? ), whenever a cell is received for a vcc or vpc, the trcc counters are incremented and the bedc is calcula ted. when an fmc is received, the cp adds the brc fields into the table 41-10. performance monitoring cell fields field description brc fmc mcsn monitoring cell sequence number. the seq uence number of the performance monitoring cell (modulo 256). ye s ye s tuc 0+1 total user cell 0+1 count. counts all user cells (modulo 65,536) sent before the fmc was inserted. ye s ye s tuc 0 total user cell 0 count. counts clp = 0 user cells (modulo 65,536) sent before the fmc was inserted. ye s ye s tstp time stamp. used to indicate when the cell was inserted. yes yes bedc 0+1 block error detection code. even parity over the payload of the block of user cells sent since the last fmc. no yes trcc 0 total received cell count 0. counts clp=0 user cells (modulo 65,536) received before the fmc was received. ye s n o bler block error result. counts error parity bits detected by the bedc of the received fmc. yes no trcc 0+1 total received cell count 0+1. counts all user cells (modulo 65,536) received before the fmc was received. ye s n o 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 41-31 cell payload (trcc 0 , trcc 0+1 , bler) and transfers the cell to the receive raw cell queue. the user can monitor the brc cell results and transfer the cell to the transmit raw cell queue. before the brc is transferred to the transmit raw ce ll queue, the pm function t ype should be changed to backward reporting and additional checking should be done regarding the bler field. if the sequence numbers (mcsn) of the last two fm cs are not sequential or the differ ences between the last two tucs and the last two trccs are not equa l, bler should be set to all ones (see the itu i.610 recommendation). note trccs are free-running counters (m odulo 65,536) that count user cells received. the total received cells of a particular block is the difference between trcc values of two consecu tive brc cells. trcc values are taken from a vc?s performance monitoring table. 41.6.6.3 pm block generation the transmitter generates the pm block. each time the transmitted cell count parameter (tcc) in the performance monitoring table re aches zero, the cp inserts an fmc into the user cell stre am. the cp copies the fmc header, sn-fmc, tuc 0+1 , tuc 0 , bedc 0+1 -tx from the performan ce monitoring table and inserts them into the fmc payload. the tstp value (fmc time stamp fi eld) is taken from the MPC8555E time stamp timer; see section 21.2.7, ?risc time-stamp control register (rtscr).? the tucs are free-running counters (modulo 65,536) that count transm itted user cells. the total transmitted cells of a part icular block is the differ ence between tuc values of two consecutive fmcs. the bedc (bip-16, bit interleaved parity ) calculation is done on the payload of all user cells of the current tested block. the performance moni toring block can range from 1 to 2k cells, as specified in the blcksize parameter in the performance monitoring table; see section 41.10.3, ?oam performance monitoring tables.? in figure 41-18 , the performance monitoring bl ock size is 512 cells. for every 512 user cells sent, the atm controller automatically inserts an fmc into the regular cell stream as defined in itu i.610. when an fmc is received, the atm controller adds the brc fields to the cell payloa d and sends the cell to the raw cell queue. the user can monitor the brc cell results and transfer the cell to the transmit raw cell queue. 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 41-32 freescale semiconductor figure 41-18. fmc, brc insertion 41.6.6.4 brc performance calculations brc reception uses the regular aal0 raw cell queue . on receiving two consecutive brc cells, the management layer can calculate the following: ? the difference between two tucs (nt) ? the difference between two trccs (nr) information about the connection can be gained by comparing nt and nr: ? if nt > nr, the difference indicates the number of lost cells of this block test. ? if nt < nr, the difference indicates the numbe r of misinserted cells of this block test. ? when nt = nr, no cells are lost or misinserted. 41.7 user-defined cells (udc) typical atm cells are 53 bytes long and consist of a 4-byte header, 1- byte hec, and 48-byte payload. the MPC8555E also supports user-defined cells with up to 12 bytes of extra header fields for internal information for switching applicati ons. this choice is made during initialization by writing to the fpsmr; see section 41.13.3, ?fcc protocol-speci fic mode register (fpsmr).? as shown in figure 41-19 , the extra header size can vary between 1 to 12 bytes (byte resolution) and the hec octet is optional. extra header (1?12 bytes) atm cell header (4 bytes) + hec (optional) payload (48 bytes) figure 41-19. format of user-defined cells fmc cell data cell data cell fmc cell data cell data cell fmc cell 512 user cells 512 user cells tuc0 source cells stream 1 2 3 tstp bedc tuc0+1 brc cell tuc0 destination brc?s transmit stream 1 tuc0+1 tstp bler trcc0 trcc0+1 brc cell 2 brc cell 3 tuc0 tuc0+1 tstp bler trcc0 trcc0+1 tuc0 tuc0+1 tstp bler trcc0 trcc0+1 tuc0 tstp bedc tuc0+1 tuc0 tstp bedc tuc0+1 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 41-33 for aal5 the extra header is taken from the rx and txbds. the transm itter reads the extra header from the udc txbd and adds it to each atm cell associated with the curren t buffer. at the receive side, the extra header of the last cell in the current buffer is written to the udc rxbd. for aal0 the extra header is attached to the regular atm cell in the buffer. the transmitter reads the extra header and the atm cell from the buffer. the receiver writes the extra header and the regular atm cell to the buffer. 41.7.1 udc extended address mode (uead) for external cam accesses, the udc extra header can be used to supply extra routing information; see figure 41-20 . if gmode[uead] = 1, two bytes of the udc h eader are used as extensions to the atm address and the cam match cycle performs a doubl e-word access. uead_offset in the parameter ram determines the offset from th e beginning of the udc extra header to the uead entry. the offset should be half-word ali gned (even address). see section 41.10.1, ?parameter ram.? 41.8 atm layer statistics atm layer statistics can be used to identify problems, such as the line-b it error rate, that affect the uni performance. statistics are kept in three 16-bit wrap-around counters: ? utopia error dropped cells count?counts cells di scarded due to utopia errors: rx parity errors and short or long cells. ? misinserted dropped cell count?counts cells discarded due to a ddress look-up failure. ? crc10 error dropped cell count?counts cells discarded due to crc10 errors. (abr only). counters are implemented in the dual-port ram for each phy device. the counters of each phy are located in the uni statistics table, described in section 41.10.7, ?uni statistics table.? 41.9 interworking the MPC8555E supports port-to-port interworking. data forwarding betw een two atm ports can be done in two ways: ? core intervention?when a receive buffer in one atm port is full and its rxbd is closed, that port interrupts the core. the core copies the port?s receive buffer pointer to the second atm port?s txbd and sets the ready bit (txbd[r]). this mode is useful when additional core processing is required. ? automatic data forwarding. this mode enables automatic data forwarding between aal1/aal0 and transparent mode over an atm port. see section 41.9.1, ?atm-to-atm automatic data forwarding.? 16-bit 4-bit 12-bit 16-bit cam data in field: uead phy addr vpi vci 015161920313247 figure 41-20. exte rnal cam address in udc extended address mode 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 41-34 freescale semiconductor 41.9.1 atm-to-atm auto matic data forwarding automatic data forwarding can be used to switch at m aal0 cells from one atm port to another without core intervention. the receiver of one port and transmitter of the other port should be progr amed to process the same bd table. when the one por t?s receiver fills an aal0 buffer, th e other port?s tran smitter sends it, as shown in figure 41-21 . figure 41-21. atm-to-atm data forwarding as figure 41-21 shows, when data is being forwarded from atm port 2 to atm port 1, the receiver of port 2 reassembles data received from a partic ular channel to a specific bd table. the tran smitter of port 1 is programmed to operate on the same table. when port 2 fills a receive buffer, the port transmits it. the two atm ports synchronize on port 2?s rxbd[e] and port 1?s txbd[r]. when data is being forwarded from por t 1 to port 2, the receiver of port 1 r outes data to a specific bd table and port 2?s transmitter is programmed to operate on the same table. when port 1 fills a receive buffer, the port 2 sends it. the controllers synchronize on port 1?s rxbd[e] and the port 2?s txbd[r]. the receivers must be programmed to operate in opposite e-bit polarity. that is, both receivers receive data into buffers whose rxbd[e] = 0 and set rxbd[e ] when a buffer is full. for the atm receiver, set rct[inve] of the aal1- and aal0-specific areas of the receive connection table.; see section 41.10.2.2, ?receive conne ction table (rct).? 41.9.2 using interrupts in automatic data forwarding the core can program the interrupt m echanism of the atm to trigger inte rrupts for events such as a buffer closing or transfer errors. the interrupt mechanism can be used to synchronize the start of the automatic bridging process. for example, to st art the transmitter of a one atm port after a specific buffer reaches the other atm port?s receiver (the buffe ring is required to cope with th e atm network?s cdv), set rxbd[i] port 2 transmitter port 2 buffer 1 buffer 2 buffer 3 buffer 4 buffer 5 port 1* receiver port 1 bd table 0bd 1 1bd 2 1bd 3 0bd 4 0bd 5 tx ptr rx ptr port 1 transmitter port 1 buffer 1 buffer 2 buffer 3 buffer 4 buffer 5 port 2* receiver port 2 bd table 0bd 1 1bd 2 1bd 3 0bd 4 0bd 5 tx ptr rx ptr * the receivers should be programmed to operate in opposite polarity e (empty) bit. 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 41-35 in the second atm port. when the re ceive buffer is full, the rxbd is closed, rxbd[e] is set (because it is operating in opposite e-bit polarity), and the core is interrupted. the core then starts the first port?s transmitter. 41.10 atm memory structure the atm memory structure, described in the fo llowing sections, includes the parameter ram, the connection tables, oam performance monitoring tables, the apc data st ructure, bd tables, and the uni statistics table. 41.10.1 parameter ram when configured for atm mode, the fcc parameter ram is mapped as shown in table 41-11 . note that there are additional paramete rs for aal2 (refer to table 42-13 ). table 41-11. atm parameter ram map offset 1 name width description 0x00? 0x3f ? ? reserved, should be cleared. 0x40 rcell_tmp_base hword rx cell temporary base address. points to a total of 64 bytes reserved dual-port ram area used by the cp. should be 64 byte aligned. user to specify only the lowest 16 bits of the dpram address o ffset calculated from the value in ccsrbar. 0x42 tcell_tmp_base hword tx cell temporary base address. points to total of 64 bytes reserved dual-port ram area used by the cp. should be 64-byte aligned. user to specify only the lowest 16 bits of the dpram address o ffset calculated from the value in ccsrbar. 0x44 udc_tmp_base hword udc mode only. points to a total of 64 bytes reserved dual-port ram area used by the cp. should be 64-byte aligned. user to specify only the lowest 16 bits of the dpram address offset calculated from the value in ccsrbar. 0x46 int_rct_base hword internal receive connection tabl e base. user-defined offset from dual-port ram base. 0x48 int_tct_base hword internal transmit connection ta ble base. user-defined offset from dual-port ram base. 0x4a int_tcte_base hword internal transmit connection table extension base. user-defined offset from dual-port ram base. 0x4c ? word reserved, should be cleared. 0x50 ext_rct_base word external receive connection table base. user-defined. 0x54 ext_tct_base word external transmit connection table base. user-defined. 0x58 ext_tcte_base word external transmit conn ection table extension base. user-defined. 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 41-36 freescale semiconductor 0x5c uead_offset hword user-defined cells mode only. offset to the user-defined extended address (uead) in the udc extra header. must be an even address. see section 41.10.1.1, ?determining uead_offset (uead mode only).? if rct[bo] = 01, uead_offset should be in little-endian format. for example, if the uead entry is the first half word of the extra header in external memory, uead_offset should be programmed to 2 (second half word entry in dual-port ram). 0x5e ? hword reserved, should be cleared. 0x60 pmt_base hword performance moni toring table base. user-defin ed offset from dual-port ram base. 0x62 apcp_base hword apc parameter table base addr ess. user-defined offset from dual-port ram base. 0x64 fbt_base hword free buffer pool parameter table base. user-defined offset from dual-port ram base. 0x66 intt_base hword interrupt queue parameter table base. user-defined offset from dual-port ram base. 0x68 ? ? reserved, should be cleared. 0x6a uni_statt_base hword uni statistics table base. user -defined offset from dual- port ram base. note that this must be set up according to section 29 .10.7, ?uni statistics table>? it is not optional. 0x6c bd_base_ext word bd table base address extension. bd_base_ext [0?7] holds the 8 most-significant bits of the rx/txb d table base address. bd_base_ext[8?31] should be zero. user-defined. 0x70 vpt_base / ext_cam_base word base address of the address compression vp table/external cam. user-defined. 0x74 vct_base word base address of the addr ess compression vc table. user-defined. 0x78 vpt1_base / ext_cam1_base word base address of the address compression vp1 table/ext cam1. user-defined. 0x7c vct1_base word base addre ss of the address compression vc1 table. user-defined. 0x80 vp_mask hword vp mask for address compression lookup. user-defined. 0x82 vcif hword vci filtering enable bits. when cells with vci = 3, 4, 6, 7-15 are received and the associated vcif bit = 1 the cell is sent to the raw cell queue. vcif[0?2, 5] should be zero. see section 41.10.1.2, ?vci filtering (vcif).? 0x84 gmode hword global mode. user-defined. see section 41.10.1.3, ?g lobal mode entry (gmode).? 0x86 comm_info hword the information field associat ed with the last host co mmand. user-defined. see section 41.14, ?atm transmit command.? 0x88 hword 0x8a hword 0x8c ? word reserved, should be cleared. 0x90 crc32_pres word preset for crc32. initialize to 0xffff_ffff. table 41-11. atm parameter ram map (continued) offset 1 name width description 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 41-37 41.10.1.1 determining uead_o ffset (uead mode only) the uead_offset value is based on the position of the user-defined extended address (uead) in the udc extra header. figure 41-22 shows how to determine uead_offset: first determine the half-word?aligned location of the uead, and th en read the corresponding uead_offset value. 0x94 crc32_mask word constant mask for crc32. initialize to 0xdebb_20e3. 0x98 aal1_snpt_base hword aal1 snp protection look-up table base address. (aal1 ces only.) the 32-byte table resides in dual-port ram. aal1_snpt_base must be half-word aligned. user-defined offset from dual-port ram base. see section 41.10.6, ?aal1 sequence number (sn) protection table.? 0x9a ? hword reserved, should be cleared. 0x9c srts_base word external srts logic base address. aal1 ces only. should be 16-byte aligned. the four least-significant bi ts are taken from srts_dev in the aal1-specific area of the connection table entries. 0xa0 idle/unassign_base hword idle/una ssign cell base address. points to dual-port ram area contains idle/unassign cell template (little-endian format). should be 64-byte aligned. user-defined offset from dual-port ram base. the atm header should be 0x0000_0000 or 0x0100_0000 (clp=1). 0xa2 idle/unassign_size hword idle/u nassign cell size. 52 in regular mode; 53?64 in udc mode. 0xa4 epayload word reserved payload. initialize to 0x6a6a_6a6a. 0xa8 trm word (abr only) the upper bound on the time between f-rm cells for an active source. tm 4.0 defines the trm period as 100 msec. the trm value is defined by the system clock and the time st amp timer prescaler; see section 21.2.7, ?risc time-stamp control register (rtscr).? for time stamp prescaler of 1s, program trm to be 100 ms/1s = 100,000. 0xac nrm hword (abr only) controls the maximum cells the source may send for each f-rm cell. set to 32 cells. 0xae mrm hword (abr only) controls the bandwidth between f-rm, b-rm and user data cell. set to 2 cells. 0xb0 tcr hword (abr only) tag cell rate. the minimum cell rate allowed for all abr channels. an abr channel whose acr is less than tcr sends only out-of-rate f-rm cells at tcr. should be set to 10 cells/sec as defined in the tm 4.0. uses the atmf tm 4.0 floating-point format. note that the apc minimum cell rate (mcr) should be at least tcr. 0xb2 abr_rx_tcte hword (abr only) points to total of 16 bytes reserved dual-port ram area used by the cp. should be 16-byte aligned. user-def ined offset from dual-port ram base. 1 offset from fcc base: 0x8400 (fcc1) and 0x8500 (fcc2); see section 21.4.2, ?parameter ram.? table 41-11. atm parameter ram map (continued) offset 1 name width description 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 41-38 freescale semiconductor 41.10.1.2 vci filtering (vcif) vci filtering enable bits are shown in figure 41-23 . table 41-12 describes the operation of th e vci filtering enable bits. 41.10.1.3 global mode entry (gmode) figure 41-24 shows the layout of the global mode entry (gmode). table 41-13 describes gmode fields. offset 0151631 0x0 uead_offset = 0x2 uead_offset = 0x0 0x4 uead_offset = 0x6 uead_offset = 0x4 0x8 uead_offset = 0xa uead_offset = 0x8 figure 41-22. uead_offsets for extended addresses in the udc extra header 012 3 4 5678910 11 12 13 14 15 field 0 0 0 vc3 vc4 0 vc6 vc7 vc8 vc9 vc10 vc11 vc12 vc13 vc14 vc15 figure 41-23. vci filtering enable bits table 41-12. vci filtering enable field descriptions bits name description 0?2, 5 ? clear these bits. 3, 4, 6, 7?15 vc x vci filtering enable 0 do not send cells with this vci to the raw cell queue. 1 send cells with this vci to the raw cell queue. 012345678 9 10 11 12 131415 field 0 0 gbl 0 0 0 alb ctb rem 0 0 uead cuab evpt 0 alm figure 41-24. global mode entry (gmode) table 41-13. gmode field descriptions bits name description 0?1 ? reserved, should be cleared. 2 ? global. asserting gbl enables snooping of connection tables. gbl should not be asserted if any of the related dmas will access the local bus. 3?5 ? reserved, should be cleared. 6 alb address look up bus for cam or address compression tables 0 reside on the system bus. 1 reside on the local bus. 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 41-39 41.10.2 connection tables (rct, tct, and tcte) the receive and transmit c onnection tables, rct and tct, store hos t-initialized connection parameters after connection set-up. these incl ude aal type, connection traffic parameters, bd parameters and temporary parameters used during segmentation and reassembly (sar). the transmit connection table extension (tcte) supports special connections that use abr, v br or ubr+ services. each connection table entry resides in a 32-byte space. table 41-14 lists sizes for rct, tct, and tcte. 7 ctb external connection tables bus 0 reside on the system bus. 1 reside on the local bus 8 rem receive emergency mode 0 enable rem operation. when the receive fifo is full , the atm transmitter stops sending data cells until the receiver emergency state is clear ed (fifo not full). the transmitter pace is maintained, although a small cdv may be introduced. this mode enables the rece iver to receive bursts of cells above the steady state performance. 1 disable rem operation. note that to check system performance the user may want to set this bit. 9?10 ? reserved, should be cleared. 11 uead user-defined cells extended address mode. see section 41.7.1, ?udc extended address mode (uead).? 0 disable uead mode. 1 enable uead mode. 12 cuab check unallocated bits 0 do not check unallocated bits during address compression. 1 check unallocated bits during address compression. 13 evpt external address compression vp table 0 vp table resides in dual-port ram. 1 vp table reside in external memory. 14 ? reserved, should be cleared. 15 alm address look-up mechanism. see section 41.4, ?vci/vpi address lookup mechanism.? 0 external cam lookup. 1 address compression. table 41-14. receive and transmit connection table sizes atm service class rct tct tcte cbr, ubr service 32 bytes 32 bytes ? abr, vbr, ubr+ service 32 bytes 32 bytes 32 bytes table 41-13. gmode field descriptions (continued) bits name description 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 41-40 freescale semiconductor note an atm channel is considered internal if its tables are in an internal dual-port ram; it is considered extern al if its tables are in external memory.to improve performance, store parameters for fast channels in internal dual-port ram and parameters for slower channels in external memory. connection tables for external channels are read and written from external memory each time the cp pr ocesses a cell. the cp does, however, minimize memory access time by burst fetching the 32-byte entry and writing back only the first 24 bytes. in all connection tables, fields wh ich are not used must be cleared. 41.10.2.1 atm channel code each atm channel has a cha nnel code used as an inde x to the channel?s connecti on table entry. the first channel in the table has channel c ode one, the second has channel code two, and so on. codes of 255 or less indicate internal channels; codes greater than 255 indicate external channe ls. channel code one is reserved as the raw cell queue and cannot be used for anothe r purpose. the channel code is used to specify a vc when sending a atm transmit command, initiating the external cam or address compression tables, and when the cp sends an interrupt to an interrupt queue. example: suppose a configuration supports 1,024 regular atm channels. to alloca te 4 kbytes of dual-port ram space to the internal connection table, determin e that channel codes 0?63 are internal (64 vcs 64 bytes (rct and tct) = 4 k). channels 0?1 are reserved. the re maining 962 (1024 ? 62) external channels are assigned channel codes 256?1217. see figure 41-25 . figure 41-25. example of a 1024-entry receive connection table the general formula for determining th e real starting address for all inte rnal and external connection table entries is as follows: connection table base a ddress + (channel code 32) dual-port ram int_rct_base reserved rct2 rct3 rct63 external memory ext_rct_base rct256 rct257 rct258 rct259 rct1217 raw cell (aal0) 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 41-41 thus, the real starting address of the rct entry associated with channel code 3 is as follows: int_rct_base+ (3 32) = int_rct_base + 96 even though it produces a gap in the c onnection table, the firs t external channel?s r eal starting address of the rct entry (channel code 256) is as follows: ext_rct_base+ (256 32) = ext_rct_base + 8192 see section 41.10.1, ?parameter ram,? to find all the connection tabl e base address parameters. (the transmit connection table base address pa rameters are int_tct_base, ext_tct_base, int_tcte_base, and ext_tcte_base.) 41.10.2.2 receive connection table (rct) figure 41-26 shows the format of an rct entry. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 offset + 0x00 ? gbl bo ? dtb bib ? bufm segf endf ? intq offset + 0x02 ? inf ? abrf aal offset + 0x04 rx data buffer pointer (rxdbptr) offset + 0x06 offset + 0x08 cell time stamp offset + 0x0a offset + 0x0c rbd_offset offset + 0x0e protocol specific see: ? for aal5, section 41.10.2.2.1, ?aal5 protocol-specific rct.? ? for aal2, section 42.4.4.1, ?aal2 protocol-specific rct.? ? for aal1, section 41.10.2.2.3, ?aal1 protocol-specific rct.? ? for aal0, section 41.10.2.2.4, ?aal0 protocol-specific rct.? offset + 0x10 offset + 0x12 offset + 0x14 offset + 0x16 offset + 0x18 offset + 0x1a mrblr offset + 0x1c ? pmt rbd_base offset + 0x1e rbd_base ? pm figure 41-26. receive connection table (rct) entry 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 41-42 freescale semiconductor table 41-15 describes rct fields. table 41-15. rct field descriptions offset bits name description 0x00 0?1 ? reserved, should be cleared. 2 gbl global. asserting gbl enables snooping of data buffers, bd, interrupt queues and free buffer pool. 3?4 bo byte ordering?used for data buffers. 00 reserved 01 munged little endian 1x big endian 5 ? reserved, should be cleared. 6 dtb data buffers bus 0 data buffers reside on the system bus. 1 data buffers reside on the local bus 7 bib bd, interrupt queues, free buffer pool and external srts logic bus 0 reside on the system bus. 1 reside on the local bus. 8 ? reserved, should be cleared. 9 bufm buffer mode. (aal5 only) see section 41.10.5.3, ?atm controller buffers.? 0 static buffer allocation mode. each bd is associated with a dedicated buffer. 1 global buffer allocation mode. free buffers are fetched from global free buffer pools. 10 segf oam f5 segment filtering 0 do not send cells with pti = 100 to the raw cell queue. 1 send cells with pti = 100 to the raw cell queue. 11 endf oam f5 end-to-end filtering 0 do not send cells with pti=101 to the raw cell queue. 1 send cells with pti=101 to the raw cell queue. 12?13 ? reserved, should be cleared. 14?15 intq points to one of four interrupt queues available. 0x02 0 ? internal use only. should be cleared. 1 inf (aal5 only) indicates the receiver state. initialize to 0 0 in idle state. 1 in aal5 frame reception state. 2?11 ? internal use only. should be cleared. 12 abrf (aal5 only). controls abr flow. 0 abr flow control is disabled. 1 abr flow control is enabled. 13?15 aal aal type 000 aal0?reassembly with no adaptation layer 001 aal1?atm adaptation layer 1 protocol 010 aal5?atm adaptation layer 5 protocol 100 aal2?atm adaptation layer 2 protocol. refer to chapter 42, ?atm aal2.? 101 aal1_ces all others reserved. 0x04 ? rxdbptr receive data buffer pointer. holds real address of current position in the rx buffer. 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 41-43 41.10.2.2.1 aal5 prot ocol-specific rct figure 41-27 shows the aal5 protocol-sp ecific area of an rct entry. table 41-16 describes aal5 protocol specific rct fields. 0x08 ? cell time stamp used for reassembly time-out. whenever a cell is received, the MPC8555E time stamp timer is sampled and written to this field. see section 21.2.7, ?risc time-stamp control register (rtscr).? 0x0c ? rbd_offset rxbd offset from rbd_base. points to t he channel?s current bd. user-initialized to 0; updated by the cp. 0x0e-0x 18 ? protocol-specific area. 0x1a ? mrblr maximum receive buffer length. used in both static and dynamic buffer allocation. 0x1c 0?1 ? reserved, should be cleared. 2?7 pmt performance monitoring table. points to one of the available 64 performance monitoring tables. the starting address of th e table is pmt_base+pmt 32. can be changed on-the-fly. 8?15 rbd_base rxbd base. points to the first bd in the channel?s rxbd table. the 8 most-significant bits of the address are taken from bd _base_ext in the parameter ram. the four least-significant bits of the address are taken as zeros. 0x1e 0?11 12?14 ? reserved, should be cleared. 15 pm performance monitoring. can be changed on-the-fly. 0 no performance monitoring for this vc. 1 perform performance monitoring for this vc. whenever a cell is received for this vc the performance monitoring table that its code is written in the pmt field is updated. 0 15 offset + 0x0e tml offset + 0x10 rx crc offset + 0x12 offset + 0x14 rbdcnt offset + 0x16 ? offset + 0x18 ? rxbm rxfm ? bpool figure 41-27. aal5 protocol-specific rct table 41-16. rct settings (aal5 protocol-specific) offset bits name description 0x0e ? tml total message length. this field is used by the cp. 0x10 ? rxcrc crc32 temporary result. 0x14 ? rbdcnt rxbd count. indicates how may bytes remain in the current rx buffer. rbdcnt is initialized with mrblr whenever the cp opens a new buffer. 0x16 ? ? reserved, should be cleared. table 41-15. rct field descriptions (continued) offset bits name description 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 41-44 freescale semiconductor 41.10.2.2.2 aal5-abr protocol-specific rct figure 41-28 shows the aal5-abr protocol-s pecific area of an rct entry. table 41-17 describes aal5-abr protoc ol-specific rct fields. 0x18 0?7 ? reserved, should be cleared. 8 rxbm receive buffer interrupt mask. determines whether the receive buffer event is disabled. can be changed on-the-fly. 0 the event is disabled for this channel. (the rxb event is not sent to the interrupt queue when receive buffers are closed.) 1 the event is enabled for this channel. 9 rxfm receive frame interrupt mask. determines whether the receive frame event is disabled. can be changed on-the-fly. 0 the event is disabled for this channel. (rxf event is not sent to the interrupt queue.) 1 the event is enabled for this channel. 10?13 ? reserved, should be cleared. 14?15 bpool buffer pool. global buffer allocation mode only. points to one of four free buffer pools. see section 41.10.5.2.4, ?free buff er pool parameter tables.? 0 15 offset + 0x0e aal5 protocol-specific offset + 0x10 offset + 0x12 offset + 0x14 offset + 0x16 pcr offset + 0x18 rdf rif aal5 protocol-specific figure 41-28. aal5-abr protocol-specific rct table 41-17. abr protocol-specific rct field descriptions offset bits name description 0x0e ? ? aal5 protocol-specific 0x16 ? pcr peak cell rate. the peak number of cells per second of the current abr channel. the acr (allowed cell rate) never exceeds this value. pcr uses the atmf tm 4.0 floating-point format. 0x18 0?3 rdf rate decrease factor for the current abr channel . controls the decrease in cell transmission rate upon receipt of a backward rm cell. rdf repres ents a negative exponent of two, that is, the decrease factor = 2 ?rdf . the decrease factor ranges from 1/32768 (rdf = 0xf) to 1 (rdf = 0). 4?7 rif rate increase factor of the current abr channel. controls the increase in the cell transmission rate upon receipt of a backward rm cell. rif represents a negative exponent of two, that is, the increase factor = 2 ?rif . the increase factor ranges from 1/32768 (rif = 0xf) to 1 (rif = 0). 8?15 ? aal5 protocol-specific table 41-16. rct settings (aal5 protocol-specific) (continued) offset bits name description 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 41-45 41.10.2.2.3 aal1 prot ocol-specific rct figure 41-29 shows the aal1 protocol-speci fic area of an rct entry. table 41-18 describes aal1 protoc ol-specific rct fields. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 offset + 0x0e ? pfm srt inve stf ? offset + 0x10 srts_tmp ? ? srts_dev offset + 0x12 ? valid octet size (vos) spv structured pointer (sp) offset + 0x14 rbdcnt offset + 0x16 ? sn offset + 0x18 ? snem ? rxbm ? figure 41-29. aal1 protocol-specific rct table 41-18. aal1 protocol-specific rct field descriptions offset bits name description 0x0e 0?7 ? reserved, should be cleared. 8 pfm partially filled mode. 0 partially filled cells mode is not used. 1 partially filled cells mode is used. the receiver copies only valid octets from the aal1 cell to the rx buffer. the number of the valid oc tets from the beginning of the aal1 user data field is specified in the vos (valid octet size) field. 9 srt synchronous residual time stamp. unstruct ured format only. the MPC8555E supports clock recovery using an external srts pll. the MPC8555E tracks the srts from the incoming four cells with sn = 1, 3, 5, and 7 and writes it to the external srts device. every eight cells the cp writes a valid srts to external logic. 0 srts mode is not used. 1 srts mode is used. 10 inve inverted empty. 0 rxbd[e] is interpreted normally (1 = empty, 0 = not empty). 1 rxbd[e] is handled in negative lo gic (0 = empty, 1 = not empty). 11 stf structured format 0 unstructured format is used. 1 structured format is used. 12?15 ? reserved, should be cleared. 0x10 0?3 srts_tmp used by the cp to store the received sr ts code. after a cell with sn = 7 is received, the cp writes the srts code to the external srts device. 4?11 ? reserved, should be cleared. 12?15 srts_dev selects an srts device, whose addr ess is srts_base[0?27] + srts_dev[28?31]. the 16 byte-aligned srts_base is taken from the parameter ram. 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 41-46 freescale semiconductor 41.10.2.2.4 aal0 prot ocol-specific rct figure 41-30 shows the layout for the aa l0 protocol-specific rct. 0x12 0?1 ? reserved, should be cleared. 2?7 vos valid octet size. specifies the number of valid octets from the beginning of the aal1 user data field. for unstructured, service values 1?47 ar e valid; for structured service, values 1-46 are valid. partially filled cell mode only. 8 spv structured pointer valid. should be user-ini tialized user to zero. structured format only. 9?15 sp structured pointer. used by the cp to calculate the structured pointer. this field should be initialized by the user to zero. used in structured format only. 0x14 ? rbdcnt rxbd count. indicates how may bytes remain in the current rx buffer. initialized with mrblr whenever the cp opens a new buffer. 0x16 0?12 ? reserved, should be cleared. 13?15 sn sequence number. used by the cp to check incoming cell?s sequence number. 0x18 0?3 ? reserved, should be cleared. 4 snem sequence number error flag interrupt mask 0 this mode is disabled. 1 when an out-of-sequence error occurs, an rxb interrupt is sent to the interrupt queue even if rct[rxbm] is cleared. note that this mode is the buffer error reporting mechanism during automatic data forwarding (atm-to-tdm bridging) when no buffer processing is required (rct[rxbm]=0). 5?7 ? reserved, should be cleared. 8 rxbm receive buffer interrupt mask 0 the receive buffer event of this channel is di sabled. (the event is not sent to the interrupt queue.) 1 the receive buffer event of this channel is enabled. 9?15 ? reserved, should be cleared. 01234567 8 9101112131415 offset + 0x0e ? 0 1 inve ? offset + 0x10 ? offset + 0x12 offset + 0x14 offset + 0x16 offset + 0x18 ? rxbm ? figure 41-30. aal0 protocol-specific rct table 41-18. aal1 protocol-specific rct field descript ions (continued) offset bits name description 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 41-47 table 41-19 describes aal0 protocol specific rct fields. 41.10.2.2.5 aal2 prot ocol-specific rct refer to section 42.4.4.1, ?aal2 protocol-specific rct.? table 41-19. aal0-specific rct field descriptions offset bits name description 0x0e 0-7 ? reserved, should be cleared. 8-9 0b01 must be programmed to 0b01 for aal0. 10 inve inverted empty. 0 rxbd[e] is interpreted normally (1 = empty, 0 = not empty). 1 rxbd[e] is handled in negative lo gic (0 = empty, 1 = not empty). 11-15 ? reserved, should be cleared. 0x10 ? ? reserved, should be cleared. 0x18 0?7 ? reserved, should be cleared. 8 rxbm receive buffer interrupt mask 0 the receive buffer event of this channel is mask ed. (the rxb event is not sent to the interrupt queue when receive buffers are closed.) 1 the receive buffer event of this channel is enabled. 9?15 ? reserved, should be cleared. 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 41-48 freescale semiconductor 41.10.2.3 transmit connection table (tct) figure 41-31 shows the format of an tct entry. table 41-20 describes general tct fields. 01234567 8 9101112 131415 offset + 0x00 ? gbl bo ? dtb bib avcf ? att cpuu vcon intq offset + 0x02 ? inf ? abrf aal offset + 0x04 tx data buffer pointer (txdbptr) offset + 0x06 offset + 0x08 tbdcnt offset + 0x0a tbd_offset offset + 0x0c rate remainder pcr fraction offset + 0x0e pcr offset + 0x10 protocol specific ? for aal5, see section 41.10.2.3.1, ?aal5 protocol-specific tct.? ? for aal2, see section 42.3.5.1, ?aal2 protocol-specific tct.? ? for aal1, see section 41.10.2.3.2, ?aal1 protocol-specific tct.? ? for aal0, see section 41.10.2.3.3, ?aal0 protocol-specific tct.? offset + 0x12 offset + 0x14 offset + 0x16 apc linked channel (apclc) offset + 0x18 atm cell header (vpi,vci,pti,clp) offset + 0x1a offset + 0x1c ? pmt tbd_base offset + 0x1e tbd_base bnm stpt imk pm figure 41-31. transmit connection table (tct) entry table 41-20. tct field descriptions offset bits name description 0x00 0?1 ? reserved, should be cleared. 2 gbl global. asserting gbl enables snooping of data buffers, bds, interrupt queues and free buffer pool. 3?4 bo byte ordering. this field is used for data buffers. 00 reserved 01 power pc little endian 1x big endian 5 ? reserved, should be cleared. 6 dtb data buffer bus 0 reside on the system bus. 1 reside on the local bus. 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 41-49 7 bib bd, interrupt queue and external srts logic bus 0 reside on the system bus. 1 reside on the local bus. note: when using aal5, aal1 ces in udc mode, bds and data should be placed on the same bus (tct[dtb] = tct[bib]). 8 avcf auto vc off. determines the behavior of the apc when the last buffer associated with this vc has been sent and no more ready buffers are in the vc?s txbd table. 0 the apc does not remove this vc from the schedule table and continues to schedule it to transmit. 1 the apc removes this vc from the schedule table. to continue transmission after the host adds buffers for transmission, a new atm transmit command is needed, which can be issued only after the cp clears tct[vcon]. note: when over-subscribing ubr or ubr+ channels, set avcf so that the cpm does not become overloaded polling non-active vcs. 9 ? reserved, should be cleared. 10?11 att atm traffic type 00 peak cell-rate pacing. the host must initia lize pcr and the pcr fr action. other traffic parameters are not used. 01 peak and sustain cell rate pacing (vbr traffic). the apc performs a continuous-state leaky bucket algorithm (gcra) to pace the channel-sustain cell rate. the host must initialize pcr, pcr fraction, scr, scr frac tion, and bt (burst tolerance). 10 peak and minimum cell rate pacing (ubr+ traffic). the host must initialize pcr, pcr fraction, mcr, mcr fraction, and mda. 11 reserved 12 cpuu cpcs-uu+cpi insertion (used for aal5 only). 0 cpcs-uu+cpi insertion disabled. the transmitter clears the cpcs-uu+cpi fields. 1 cpcs-uu+cpi insertion enabled. the transm itter reads the cpcs-uu+cpi (16-bit entry) from external memory. it should be placed after the end of the last buffer (it should not be included in the buffer length). 13 vcon virtual channel is on. should be set by the host before it issues an atm transmit command. when the host sets tct[stpt] (stop transmit), the cp deactivates this channel and clears vcon when the channel is next encountered in the apc sch eduling table. the host can issue another atm transmit command only after the cp clears vcon. 14?15 intq points to one of four interrupt queues available. 0x02 0 ? internal use only. should be cleared. 1 inf used for aal5 only. indicates the transmitter state. initialize to 0 0 in idle state. 1 in aal5 frame transmission state. 2?11 ? internal use only. should be cleared. 12 abrf used for aal5 only. 0 abr flow control is disabled. 1 abr flow control is enabled. table 41-20. tct field descriptions (continued) offset bits name description 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 41-50 freescale semiconductor 13?15 aal aal type 000 aal0?reassembly with no adaptation layer 001 aal1?atm adaptation layer 1 protocol 010 aal5?atm adaptation layer 5 protocol 100 aal2?atm adaptation layer 2 protocol. refer to chapter 42, ?atm aal2.? 101 aal1_ces all others reserved. 0x04 ? txdbptr tx data buffer pointer. holds the real address of the current position in the tx buffer. 0x08 ? tbdcnt transmit bd count. counts the remaining data to transmit in the current transmit buffer. its initial value is loaded from the data length field of the txbd when a new buffer is open; its value is subtracted for any transmitted cell associated with this channel. 0x0a ? tbd_offset transmit bd offset. holds offset from tbd_base of the current bd. sh ould be cleared initially. 0x0c 0?7 rate reminder rate remainder. used by the apc to hold the rate remainder after adding the pace fraction to the additive channel rate. should be cleared initially. 8?15 pcr fraction peak cell rate fraction. holds the peak cell rate fraction of this channel in units of 1/256 slot. if this is an abr channel, this field is automatically updated by the cp. 0x0e ? pcr peak cell rate. holds the peak cell rate (in units of apc slots) permitted for this channel according to the traffic contract. note that fo r an abr channel, the cp automatically updates pcr to the acr value. 0x10 ? ? protocol-specific 0x16 ? apclc apc linked channel. used by the cp. initialize to 0 (null pointer). 0x18 ? atmch atm cell header. holds the full (4-byte) atm cell header of the current channel. the transmitter appends atmch to the cell payload during transmission. 0x1c 0?1 ? reserved, should be cleared. 2?7 pmt performance monitoring table. points to one of the available 64 performance monitoring tables. the starting address of th e table is pmt_base+pmt 32. can be changed on-the-fly. 8?15 tbd_base txbd base. points to the first bd in the chan nel?s txbd table. the 8 most -significant bits of the address are taken from bd_base_ext in the param eter ram. the four l east-significant bits of the address are taken as zero. 0x1e 0?11 12 bnm buffer-not-ready interrupt mask. can be changed on-the-fly. 0 the transmit buffer-not-ready event of this c hannel is masked. (tbnr event is not sent to the interrupt queue.) 1 the buffer-not-ready event of this channel is enabled. 13 stpt stop transmit. should be cleared initially. w hen the host sets this bit, the cp deactivates this channel and clears tct[vcon] when the channe l is next encountered in the apc scheduling table. note that for aal5 if stpt is set and fr ame transmission is already started (tct[inf]=1), an abort indication will be sent (last cell with zero length field). 0x1e 14 imk interrupt mask. can be changed on-the-fly. 0 the transmit buffer event of this channel is masked. (txb event is not sent to the interrupt queue.) 1 the transmit buffer event of this channel is enabled. 15 pm performance monitoring. can be changed on-the-fly. 0 no performance monitoring for this vc. 1 performance is monitored for this vc. when a cell is sent for this vc, the performance monitoring table indicated in pmt field is updated. table 41-20. tct field descriptions (continued) offset bits name description 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 41-51 41.10.2.3.1 aal5 protocol-specific tct figure 41-32 shows the aal5 protocol-specific tct. table 41-21 describes aal5 protoc ol-specific tct fields. 41.10.2.3.2 aal1 protocol-specific tct figure 41-33 shows the aal1 protocol-specific tct. 0 15 offset + 0x10 tx crc offset + 0x12 offset + 0x14 total message length figure 41-32. aal5 protocol-specific tct table 41-21. aal5-specific tct field descriptions offset name description 0x10 tx crc crc32 temporary result. 0x14 total message length this field is used by the cp. 0123456789101112131415 offset + 0x10 ? valid octet size (vos) pfm srt spf stf ? sn offset + 0x12 srts_dev block size offset + 0x14 srts_tmp structured pointer (sp) figure 41-33. aal1 protocol-specific tct 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 41-52 freescale semiconductor table 41-22 describes aal1 protoc ol-specific tct fields. table 41-22. aal1 protocol-specific tct field descriptions offset bits name description 0x10 0-1 ? reserved, should be cleared. 2?7 vos valid octet size. partially filled cell mode on ly. specifies the number of valid octets from the beginning of the aal1 user data field. for unstructured service, values 1?47 are valid; for structured service, values 1?46 are valid. 8 pfm partially filled mode. 0 partially filled cells mode is not used. 1 partially filled cells mode is used. the transmitte r copies only valid octets from the buffer to the aal1 cell. the size of the valid octets from the beginning of the aal1 user data field is specified in the vos (valid octet size) field. 9 srt synchronous residual time stamp. unstruct ured format only. the MPC8555E supports srts generation using external logic. if this mode is enabled, the MPC8555E reads the srts from external logic and inserts it into four cells for which sn = 1, 3, 5, or 7. the MPC8555E reads the new srts from external logic every eight cells. 0 srts mode is not used. 1 srts mode is used. 10 spf structured pointer flag. indicates that a st ructured pointer has been inserted in the current block. the user should initialize this field to zero. used by the cp only. 11 stf structured format 0 unstructured format is used. 1 structured format is used. 12 ? reserved, should be cleared. 13?15 sn sequence number field. used by the cp to check the incoming cells sn. should be cleared initially. 0x12 0?3 srts_dev used to select a srts device. the srts device address is srts_base[0?27]+srts_dev[28:31]. srts_base is taken from the parameter ram and is 16-byte aligned. 4?15 block size used only in structured format. specif ies the structured block size (block size = 0xfff = 4 kbytes maximum). 0x14 0?3 srts_tmp before a cell with sn = 1 is sent, the cp r eads the srts code from external srts logic, writes it to srts_tmp, and then inserts srts_tmp into the next four cells with an odd sn. 4?15 sp structured pointer. used by the cp to calc ulate the structured pointer. should be cleared initially. structured format only. 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 41-53 41.10.2.3.3 aal0 protocol-specific tct figure 41-34 shows the aal0 protocol-specific tct. table 41-23 describes aal0 protoc ol-specific tct fields. 41.10.2.3.4 aal2 protocol-specific tct refer to section 42.3.5.1, ?aal2 protocol-specific tct.? 0 7 8 9 10 11 12 15 offset + 0x10 ? 0 cr10 ? achc ? offset + 0x12 ? offset + 0x14 figure 41-34. aal0 protocol-specific tct table 41-23. aal0-specific tct field descriptions offset bits name description 0x10 0?7 ? reserved, should be cleared. 8 0 must be 0. 9 cr10 crc-10 0 crc10 insertion is disabled. 1 crc10 insertion is enabled. 10 ? reserved, should be cleared. 11 achc atm cell header change 0 normal operation atm cell header is taken from aal0 buffer. 1 vpi/vci (28 bits) are taken from tct. 12?15 ? reserved, should be cleared. 0x12?0x14 ? ? reserved, should be cleared. 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 41-54 freescale semiconductor 41.10.2.3.5 vbr prot ocol-specific tcte figure 41-35 shows the vbr protocol-specific tcte. table 41-24 describes vbr protocol -specific tcte fields. 01 78 15 offset + 0x00 scr offset + 0x02 burst tolerance (bt) offset + 0x04 out of buffer rate (oobr) offset + 0x06 sustain rate remainder (srr) scr fraction (scrf) offset + 0x08 sustain rate (sr) offset + 0x0a offset + 0x0c vbr2 ? offset + 0x0e-1e ? figure 41-35. transmit connection table extension (tcte)?vbr protocol-specific table 41-24. vbr-specific tcte field descriptions offset bits name description 0x00 ? scr sustain cell rate. holds the sustain cell rate (in sl ots) permitted for this channel according to the traffic contract. to pace the channel?s sustain cell rate, the apc performs a continuous-state leaky bucket algorithm (gcra). 0x02 ? bt burst tolerance. holds the burst tolerance permitted for this channel according to the traffic contract. the relationship between the bt and the maximum burst size (mbs) is bt=(mbs-2) (scr-pcr) + scr. 0x04 ? oobr out-of-buffer rate. in out of buffer state (wh en the transmitter tries to open txbd whose r bit is not set) the apc reschedules the current channel according to oobr rate. 0x06 0?7 srr sustain rate remainder. holds the sustain rate remainder after adding the pace fraction field to the additive channel sustain rate. used by the apc to calculate the channel gcra (leaky bucket) state. initialized to 0. 8?15 scrf holds the sustain cell rate fraction of this channel in units of 1/256 slot. 0x08 ? sr sustain rate. used by the apc to hold the su stain rate after adding the pace field to the additive channel sustain rate. used by the apc to calculate the channel gcra (leaky bucket) state. 0x0c 0 vbr2 vbr type 0 regular vbr. clp=0+1 cells are rescheduled by pcr or scr according to the gcra state. 1 vbr type 2. clp=0 cells are rescheduled by p cr or scr according to the gcra state. clp = 1 cells are rescheduled by pcr. 1?15 ? reserved, should be cleared. 0x0e? 0x1e ? ? reserved, should be cleared. 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 41-55 41.10.2.3.6 ubr+ pr otocol-specific tcte figure 41-36 shows the ubr+ protocol-specific tcte. table 41-25 describes ubr+ protoc ol-specific tcte fields. 07815 offset + 0x00 mcr offset + 0x02 ? mcr fraction (mcrf) offset + 0x04 maximum delay allowed (mda) offset + 0x06?0x1e ? figure 41-36. ubr+ protocol-specific tcte table 41-25. ubr+ protocol-specific tcte field descriptions offset bits name description 0x00 ? mcr minimum cell rate for this channel. mcr is in units of apc time slots. 0x02 0?7 ? reserved, should be cleared. 8?15 mcrf minimum cell rate fraction. holds the minimum cell rate fraction of this channel in units of 1/256 slot. 0x04 ? mda maximum delay allowed. the maximum time-slot service delay allowed for this priority level before the apc reduces the scheduling rate from pcr to mcr. 0x06? 0x1e ? ? reserved, should be cleared. 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 41-56 freescale semiconductor 41.10.2.3.7 abr protocol-specific tcte figure 41-37 shows the abr protocol-specific tcte. table 41-26 describes abr-specific tcte fields. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 offset + 0x00 er-ta offset + 0x02 ccr-ta offset + 0x04 mcr-ta offset + 0x06 tuar ? ci-ta ni-ta ? cp-ta ? ci-vc ? offset + 0x08 mcr offset + 0x0a unack offset + 0x0c acr offset + 0x0e acrc ? offset + 0x10 rm cell time stamp (rcts) offset + 0x12 offset + 0x14 frst ? cdf count offset + 0x16 icr offset + 0x18 crm offset + 0x1a adtf offset + 0x1c er offset + 0x1e er-brm figure 41-37. abr protocol-specific tcte table 41-26. abr-specific tcte field descriptions offset bits name description 0x00 ? er-ta explicit rate?tur n-around cell. holds the er of the last received f-rm cell. if another f-rm cell arrives before the previous f-rm cell was turned around, this field is overwritten by the new rm cell?s er. 0x02 ? ccr-ta current cell rate?turn-around cell. holds the ccr of the last received f-rm cell. if another f-rm cell arrives before the previous f-rm cell was tu rned around, this field is overwritten by the new rm cell?s ccr. 0x04 ? mcr-ta minimum cell rate?turn-around cell. holds the mcr of the last received f- rm cell. if another f-rm cell arrives before the previous f-rm cell is turn ed around, this field is overwritten by the new rm cell?s mcr. 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 41-57 0x06 0 tuar turn-around flag. the cp sets tuar to indica te that a new f-rm cell was received, which causes the transmitter to send a b-rm cell whenever the abr flow control permits. should be cleared initially. 1 ? reserved, should be cleared. 2 ci-ta congestion indication?turn-around cell. holds the ci of the last received f-rm cell. if another f-rm cell arrives before the previous f-rm cell was turned around, ci-ta is overwritten by the new rm cell?s ci. 3 ni-ta no increase?turn-around cell. holds the ni of the last received f-rm cell. if another f-rm cell arrives before the previous one was turned around, ni-ta is overwritten by the new rm cell?s ni. 4?6 ? reserved, should be cleared. 7 cp-ta cell loss priority?turn-around cell. holds the clp of the last received f-rm cell. if another f-rm cell arrives before the previous one was turned ar ound, cp-ta is overwritten by the new rm cell?s clp. 8?9 ? reserved, should be cleared. 10 ci-vc congestion indication -vc. holds the efci (exp licit forward congestion indication) of the last user data cell. the ci bit of the turned around rm ce ll is ored with the ci-vc. should be cleared initially. 11?15 ? reserved, should be cleared. 0x08 ? mcr minimum cell rate holds the minimum number of cells/sec of the current abr channel. uses the atmf tm 4.0 floating-point format. 0x0a ? unack used by the cp to count f-rm cells sent in an absence of received b-rm cells. should be cleared initially. 0x0c ? acr allowed cell rate the cells per second allowed for the current abr channel. uses the atmf tm 4.0 floating-point format. initialize with icr. 0x0e 0 acrc acr change. indicates a change in acr. initialize to one. 1?15 ? reserved, should be cleared. 0x10 ? rcts rm cell time stamp. used exclusively by the cp. initialize to zero. 0x14 0 frst first turn. used exclusively by the cp. indicates the first turn of a backward rm cell, which has priority over a data cell. initialized to 0. 1?3 ? reserved, should be cleared. 4?7 cdf cutoff decrease factor. controls the decrease in the acr associated with missing b-rm cells feedback. cdf represents a negative exponent of two, that is, the cutoff decrease factor = 2 -cdf . the cutoff decrease factor ranges from 1/64 ( cdf = 0b0110) to 1 (cdf = 0b0000). all other cdf values falling outside this range are invalid. 8?15 count count. used only by the cp. holds the number of cells sent since the last forward rm cell. initialize with nrm (in the parameter ram). 0x16 ? icr initial cell rate. the number of cells per second of the current abr channel. the channel?s acr is initialized with icr. icr uses the atmf tm 4.0 floating-point format. 0x18 ? crm missing rm cells count. limits the number of fo rward rm cells that may be sent in the absence of received backward rm cell. the crm is in units of cells. table 41-26. abr-specific tcte field descriptions (continued) offset bits name description 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 41-58 freescale semiconductor 41.10.3 oam performance monitoring tables the oam performance monitoring tables include pe rformance monitoring block test parameters, as shown in figure 41-38 . each block test needs a 32-byte perfor mance monitoring table in the dual-port ram. in the connection?s rct and tc t, the user allocates an oam perf ormance table to a vcc or vpc. see section 41.6.6, ?perform ance monitoring.? pmt_base in the parameter ram points to the base address of the tables. the starting address of each pm table is given by pm t_base + rct/tct[pmt] 32. 0x1a ? adtf adtf?acr decrease time fact or. the adtf period is 500 ms as defined in the tm 4.0. the adtf value is defined by the system clock and the time stamp timer prescaler; see section 21.2.7, ?risc time-stamp control register (rtscr).? for a time stamp prescaler of 1 s, adtf should be programmed to 500m/(1s 1024) = 488. 0x1c ? er explicit rate. holds the explicit rate value (in cells/sec) of the current abr channel. er is copied to the f-rm cell er field. the user usually initializ es this field to pcr. er uses the atmf tm 4.0 floating-point format. 0x1e ? er-brm explicit rate-backward rm cell. holds the ma ximum explicit rate value (in cells/sec) allowed for b-rm cells. the er-ta field which is inserted to each b-rm cell is limited by this value. er-brm uses the atmf tm 4.0 floating-point format. 012 45 78 15 offset + 0x00 fmce tste ? blcksize offset + 0x02 ? tx cell count ( tcc ) offset + 0x04 tuc1 offset + 0x06 tuc0 offset + 0x08 bedc0+1-tx offset + 0x0a bedc0+1-rx offset + 0x0c trcc1 offset + 0x0e trcc0 offset + 0x10 ? sn-fmc offset + 0x12 ? offset + 0x14 pm cell header (vpi,vci,pti,clp) offset + 0x16 offset + 0x18 ? offset + 0x1a offset + 0x1c offset + 0x1e figure 41-38. oam performance monitoring table table 41-26. abr-specific tcte field descriptions (continued) offset bits name description 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 41-59 table 41-27 describes fields in the performance monitoring table. 41.10.4 apc data structure the apc data structure consists of three elements: the ap c parameter tables for the phy devices, the apc priority table, and the apc scheduling tables. see figure 41-39 . table 41-27. oam?performance monitoring table field descriptions offset bits name 1 1 boldfaced entries must be initialized by the user. description 0x00 0 fmce enables fmc transmission. initialize to 1. 1 tste fmc time stamp enable 0 the time stamp field of t he fmc is coded with all 1s. 1 the value of the time stamp timer is inse rted into the time stamp field of the fmc. 2?4 ? reserved, should be cleared. 5?15 blcksize performance monitoring block size ranging from 1 to 2,047 cells. 0x02 0?4 ? reserved, should be cleared. 5?15 tcc tx cell count. used by th e cp to count data cells sent. initialize to zero. 0x04 ? tuc1 total user cell 1. count of clp = 1 user cells (modulo 65,536) sent. should be cleared initially. 0x06 ? tuc0 total user cell 0. count of clp = 0 user cells (modulo 65,536) sent. should be cleared initially. 0x08 ? bedc0+1-tx block error detection code 0+1?transmitted cells. even parity over the payload of the block of user cells sent since the last fmc. should be cleared initially. 0x0a ? bedc0+1-rx block error detection code 0+1?received cells. even parity over the payload of the block of user cells received since the last fmc. should be cleared initially. 0x0c ? trcc1 total received cell 1. count of clp = 1 user cells (modulo 65,536) received. should be cleared initially. 0x0e ? trcc0 total received cell 0. count of clp = 0 user cells (modulo 65,536) received. should be cleared initially. 0x10 0?7 ? reserved, should be cleared. 8?15 sn-fmc sequence number of the last fmc sent. should be cleared initially. 0x12 ? ? reserved, should be cleared. 0x14 ? pmch pm cell header. holds the atm cell header of the fmc, brc to be inserted by the cp into the tx cell flow. 0x18?0 x1e ? ? reserved, should be cleared. 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 41-60 freescale semiconductor figure 41-39. atm pace control data structure 41.10.4.1 apc parameter tables each phy?s apc parameter table, shown in table 41-28 , holds parameters that de fine the priority table location, the number of priority leve ls, and other apc parame ters. the table resides in the dual-port ram. the parameter apcp_base, described in section 41.10.1, ?parameter ram,? points to the base address of phy#0?s parameter table. for multiple phys, the table structur e is duplicated. each table resides in 32 bytes of memory. the starting address of each apc parameter ta ble is given by apcp_base + phy# 32. note, however, that in slave mode with multiple phys, the parameter table al ways resides at apcp_base regardless of the phy address. table 41-28. apc parameter table offset 1 name width description 0x00 apcl_first hword address of first entry in the priority table. must be 8-byte aligned. user-initialized. 0x02 apcl_last hword address of last entry in the priority table. must be 8-byte aligned. user-initialized as apcl_first + 8 x (number_of_priorities - 1). 0x04 apcl_ptr hword address of current priority entry used by the cp. user-initialized with apcl_first. 0x06 cps byte cells per slot. determines the numb er of cells sent per apc slot. see section 41.3.2, ?apc unit scheduling mechanism.? user-defined. (0x01 = 1 cell; 0xff = 255 cells.) note: if abr is used, cps must be a power of two. 0x07 cps_cnt byte cells sent per apc slot counter. user-initialized to cps; used by the cp. 0x08 max_iteration byte max iteration allowed. num ber of scan iterations allowed in the apc. user-defined. this parameter limits the time spent in a single apc routine, thereby avoiding excessive apc latency. 0x09 cps_abr byte abr only. cells per slot represented as a power of two. user-defined. (for example, if cps is 1, cps_abr = 0x00; if cps is 8, cps_abr = 0x03.) 0x0a line_rate_abr hword abr only. the phy line rate in cells/sec, represented in tm 4.0 floating-point format. user-defined. priority 1 apc priority table apc parameter tables parameter table phy #0 parameter table phy #1 parameter table phy #31 priority 2 priority 3 priority 4 priority 5 priority 6 priority 7 priority 8 apc scheduling tables priority 1 scheduling table priority 2 scheduling table priority 3 scheduling table priority 4 scheduling table priority 5 scheduling table priority 6 scheduling table priority 7 scheduling table priority 8 scheduling table note: the shaded areas represent the active structures for an example implementation of phy #0 with two priorities. (the unshaded areas and dashed arrows represent unused structures.) 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 41-61 41.10.4.2 apc priority table each phy?s apc priority table holds pointers to the apc scheduling table of each priority level. it resides in the dual-port ram. the priority tabl e can hold up to eight priority levels. table 41-29 shows the structure of a priority table entry. 41.10.4.3 apc scheduling tables the apc uses apc scheduling tables ( one table for each priority level) to schedule channel transmission. a scheduling table is divided in to time slots, as shown in figure 41-40 . each slot is a half-word entry. note that the apc scheduling tables should be cleared before the apc unit is enabled. figure 41-40. apc scheduling table structure slot n+1 is used as a c ontrol slot, as shown in figure 41-41 . 0xc real_tstp word real-time stamp pointer used internally by the apc. should be cleared initially. 0x10 apc_state word used internally by the apc. should be cleared initially. 1 offset values are to apcp_base+phy# 32. however, in slave mode, the offset is from apcp_base regardless of the phy address. table 41-29. apc priority table entry offset name width description 0x00 apc_levi_base hword apc level i base address. pointer to the first slot in the apc scheduling table for level i. should be half-word aligned. user-defined. 0x02 apc_levi_end hword apc level i end address. pointer to the last slot in the apc scheduling table for level i. should be half-word aligned. user-defined. 0x04 apc_levi_rptr hword apc level i real-time/service point ers. apc table pointers used internally by the apc. initialize both pointers to apc_levi_base. 0x06 apc_levi_sptr hword 0 123456789101112131415 field tcte 000_0000_0000_0000 figure 41-41. control slot table 41-28. apc parameter table (continued) offset 1 name width description apc_levi_base apc_levi_end half word entry slot 0 slot 1 slot n control slot 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 41-62 freescale semiconductor table 41-30 describes control slot fields. 41.10.5 atm controller bu ffer descriptors (bds) each atm channel has sepa rate receive and transmit bd tables. the number of bds per channel and the size of the buffers is user-defined. the last bd in each table holds a wr ap indication. each bd in the txbd table points to a buffer to send. at the receive side, the user can choos e one of two modes: ? static buffer allocation. in this mode, the user allocates dedicated buffers to each atm channel (that is, the user associates each bd with one buffer). static buffer allocation is useful when the connection rate is known and consta nt and when data must be reas sembled in a particular memory space. ? global buffer allocation. available for aal5 only. in this mode, buffer allocation is dynamic. the user allocates receive buf fers and places them in global buffer pools. when the cp needs a receive buffer, it first fetches a buffer pointer from one of the global buffer pools an d writes the pointer to the current rxbd. globa l buffer allocation is optimized fo r allocating memory among many atm channels with variable data rates, such as abr channels. 41.10.5.1 transmit buffer operation the user prepares a table of bds point ing to the buffers to be sent. the a ddress of the first bd is put in the channel?s tct[tbd_base]. the transmit pr ocess starts when the core issues an atm transmit command. the cp reads the first txbd in the table and sends its associat ed buffer. when the current buffer is finished, the cp increments tbd_ offset, which holds the offset from tbd_base to the current bd. it then reads the next bd in the tabl e. if the bd is ready (txbd[r] = 1), the cp continues sending. if the current bd is not ready, the cp polls the ready bi t at the channel rate unle ss tct[avcf] = 1, in which case the cp removes the channel from the apc a nd clears tct[vcon]. the core must issue a new atm transmit command to restart transmission. table 41-30. control slot field descriptions bits name 1 1 boldfaced entries must be initialized by the user. description 0 tcte used for external channels only. 0 channels in this scheduling table do not use external tcte. (no external vbr, abr, ubr+ channels) 1 channels in this scheduling table use external tcte. (external vbr, abr, ubr+ channels) 1?15 ? reserved, should be cleared. 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 41-63 figure 41-42 shows the ready bit in the txbd tables and their associated buffers for two example atm channels. figure 41-42. transmit buffers and bd table example 41.10.5.2 receive buffer operation for aal5 channels, the user should choose to operate in static buf fer allocation or in global buffer allocation by writing to rct[bufm]. aal0 ch annels must use static buffer allocation. 41.10.5.2.1 static buffer allocation the user prepares a table of bds poi nting to the receive buffers. the addr ess of the first bd is put in the channel?s rct[rbd_base]. when an at m cell arrives, the cp opens the fi rst bd in the table and starts filling its associated buffer with received data. wh en the current buffer is full, the cp increments rbd_offset, which is the offset to the current bd from rbd_base, and reads the next bd in the table. if the bd is empty (rxbd[e] = 1) , the cp continues rece iving. if the bd is not empty, a busy condition has occurred and a busy interrupt is sent to the event queue. tx buffer 1 of channel 1 tx buffer 2 of channel 1 tx buffer 3 of channel 1 tx buffer 4 of channel 1 tx buffer 5 of channel 1 ch1 txbd table 0bd 1 1bd 2 1bd 3 0bd 4 0bd 5 tbd_base tbd_offset note: the shaded buffers are ready to be sent; unshaded buffers are waiting to be prepared. ch1 txbd table pointers in the tct tx buffer 1 of channel 4 tx buffer 2 of channel 4 tx buffer 3 of channel 4 tx buffer 4 of channel 4 tx buffer 5 of channel 4 ch4 txbd table 1bd 1 0bd 2 0bd 3 0bd 4 0bd 5 tbd_base tbd_offset ch4 txbd table pointers in the tct 1bd 6 bd 7 tx buffer 6 of channel 4 tx buffer 7 of channel 4 1 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 41-64 freescale semiconductor figure 41-43 shows the empty bit in the rxbd tables and their associated buffers for two example atm channels. figure 41-43. receive static buffer allocation example 41.10.5.2.2 global buffer allocation the user prepares a table of bds wi thout assigning buffers to them (no buffer pointers). the address of the first bd is put into the channel?s rct[rbd_base]. the user also prepares sets of free buffers (of size rct[mrblr]) in up to f our free buffer pools (chos en in rct[bpool]); see section 41.10.5.2.3, ?free buffer pools.? when an atm cell arrives, the cp opens the first bd in the table, fetches a buffer pointer from the free buffer pool associated with this channel, and writ es the pointer to rxbd[rxd bptr], the receive data buffer pointer field in the bd. when the current buffe r is full, the cp increments rbd_offset, which is the offset from the rbd_base to the current bd, and re ads the next bd in the table. if the bd is empty (rxbd[e] = 1), the cp fetches anot her buffer pointer from the free buffer pool and reception continues. if the bd is not empty, a busy condition occurs and a busy interrupt is sent to the event queue specifying the atm channel code. as software then processes each full buffe r (rxbd[e] = 0), it se ts rxbd[e] and copies the buffer pointer back to the free buffer pool. figure 41-44 shows two atm channels? bd ta bles and one free buffer pool. both channels are associated with free buffer pool 1. the cp allocates the first two buffers of buffer pool 1 to channel 1 and the third to channel 4. rx buffer 1 of channel 1 rx buffer 2 of channel 1 rx buffer 3 of channel 1 rx buffer 4 of channel 1 rx buffer 5 of channel 1 ch1 rxbd table 0bd 1 1bd 2 1bd 3 0bd 4 0bd 5 rbd_base rbd_offset note: the shaded buffers are empty; unshaded buffers are waiting to be processed. ch1 rxbd table pointers in the rct rx buffer 1 of channel 4 rx buffer 2 of channel 4 rx buffer 3 of channel 4 rx buffer 4 of channel 4 rx buffer 5 of channel 4 ch4 rxbd table 1bd 1 0bd 2 0bd 3 0bd 4 0bd 5 rbd_base rbd_offset ch4 rxbd table pointers in the rct 1bd 6 bd 7 rx buffer 6 of channel 4 rx buffer 7 of channel 4 1 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 41-65 figure 41-44. receive global buffer allocation example 41.10.5.2.3 free buffer pools as figure 41-45 shows, when a buffer pointer is fetched from a pool, the cp clears the entry?s valid bit and increments fbp#_ptr. after the cp uses an entry with the wrap bit se t (w = 1), it returns to the first entry in the pool. after a buffer pointer is returned to the pool, the user should set v to indicate that the entry is valid. if the cp tries to read an invalid en try (v = 0), the buffer pool is out of free buffers; the global-buffer-pool-busy event is then set in fcce[gbpb] and a busy interrupt is sent to the interrupt queue specifying the atm channel code associated with the pool. figure 41-45. free buffer pool structure buffer 1 of fbp1 buffer 2 of fbp1 ch1 rxbd table 0bd 1 1bd 2 1bd 3 1bd 4 1bd 5 rbd_base rbd_offset buffer 3 of fbp1 ch4 rxbd table 1bd 1 1bd 2 1bd 3 1bd 4 rbd_base, rbd_offset free buffer pool 1 fbp1_ptr fbp1_base pointer 1 pointer 2 pointer 3 pointer 4 pointer 5 pointer 6 buffer 4 buffer 5 buffer 6 note: buffers 2 and 3 are receiving data. after buffer 1 is processed, it can be returned to the pool. v = 1 w = 0 buffer pointer v = 1 w = 0 buffer pointer v = 1 w = 0 buffer pointer v = 0 w = 0 invalid v = 0 w = 0 invalid v = 0 w = 0 invalid v = 1 w = 0 buffer pointer v = 1 w = 0 buffer pointer v = 1 w = 1 buffer pointer fbp#_base software (core) pointer fbp#_ptr word 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 41-66 freescale semiconductor figure 41-46 describes the structure of a free buffer pool entry. table 41-31 describes free buffer pool entry fields. 41.10.5.2.4 free buffer pool parameter tables the free buffer pool parameters are held in parameter tables in the dual-port ram; see table 41-32 . fbt_base in the parameter ram points to the base a ddress of these tabl es. each of the four free buffer pools has its own parameter table with a st arting address given by fbt_base+ rct[bpool] 16. 01234 15 offset + 0x00 v ? w i buffer pointer (bp) offset + 0x02 buffer pointer (bp) figure 41-46. free buffer pool entry table 41-31. free buffer pool entry field descriptions offset bits name 1 1 boldfaced entries must be initialized by the user. description 0x00 0 v valid buffer entry. 0 this free buffer pool entry contains an invalid buffer pointer. 1 this free buffer pool entry contains a valid buffer pointer. 1 ? reserved, should be cleared. 2 w wrap bit. when set, this bit indicates the last entry in the circular table. during initialization, the host must clear all w bits in the table except the last one, which must be set. 3 i red-line interrupt. can be used to indicate that the free buffer pool has reached a red line and additional buffers should be added to this pool to avoid a busy condition. 0 no interrupt is generated. 1 a red-line interrupt is generated when this buffer is fetched from the free buffer pool. 4?15 bp buffer pointer. points to the start address of the receive buffer. the four msbs are control bits, and the four msbs of the real buffer pointer ar e taken from the four msbs of the parameter fbp_entry_ext in the free bu ffer pool parameter table. 0x02 0?15 table 41-32. free buffer pool parameter table offset 1 bits name 2 description 0x00 ? fbp_base free buffer pool base. holds the pointer to the first entry in the free buffer pool. fbp_base should be word aligned. us er-defined. 0x04 ? fbp_ptr free buffer pool pointer. pointer to the current entry in the free buffer pool. initialize to fbp_base. 0x08 ? fbp_entry_ext free buffer pool entry extension. fbp_entry_ext[0?3] holds the four left bits of fbp_entry. fbp_entry_ext[4?15] s hould be cleared. user-defined. 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 41-67 41.10.5.3 atm controller buffers table 41-33 describes properties of the at m receive and transmit buffers. 41.10.5.4 aal5 rxbd figure 41-47 shows the aal5 rxbd. 0x0a 0 busy the cp sets this bit when it tries to fetch buffer pointer with v bit clear. fcce[gbpb] is also set. initialize to zero. 1 rli red-line interrupt. set by the cp when it fetc hes a buffer pointer with i = 1. fcce[grli] is also set. initialize to zero. 2?7 ? reserved, should be cleared. 8 epd early packet discard. 0 normal operation. 1 aal5 frames in progress are received, but new aal5 frames associated with this pool are discarded. can be used to implement epd under core control. 9?15 ? reserved, should be cleared. 0x0c ? fbp_entry free buffer pool entry. initialize with the first entry of the free buffer pool. note that fbp_entry must be reinitialized with the entry pointed to by fbp_ptr when a busy state occurs to re-enable free buffer pool processing. 1 offset from fbt_base+rct[bpool] 16. 2 boldfaced entries must be initialized by the user. table 41-33. receive and transmit buffers aal receive transmit size alignment size alignment aal5 multiple of 48 octets (exce pt last buffer in frame) double word aligned any no requirement aal1 at least 47 octets no requirement at least 47 octets no requirement aal0 52-64 octets. burst-aligned 52?64 octets. no requirement 0123456789101112 13 1415 offset + 0x00 e ? wi lf cm ? clp cng abrt cpuu lne cre offset + 0x02 data length (dl) offset + 0x04 rx data buffer pointer (rxdbptr) offset + 0x06 figure 41-47. aal5 rxbd table 41-32. free buffer pool parameter table (continued) offset 1 bits name 2 description 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 41-68 freescale semiconductor table 41-34 describes aal5 rxbd fields. m table 41-34. aal5 rxbd field descriptions offset bits name 1 description 0x00 0 e empty. 0 the buffer associated with this rxbd is full or data reception was aborted due to an error. the core can read or write any fields of this rx bd. the cp does not use this bd again while e remains zero. 1 the buffer associated with this rxbd is empty or reception is in progress. this rxbd and its receive buffer are controlled by the cp. once e is set, the core should not write any fields of this rxbd. 1 ? reserved, should be cleared. 2 w wrap (final bd in table) 0 this is not the last bd in the rxbd table of the current channel. 1 this is the last bd in the rxbd table of this current channel. after this buffer has been used, the cp receives incoming data into the first bd in the table. the number of rxbds in this table is programmable and is determined only by the w bit. the current table cannot exceed 64 kbytes. 3 i interrupt 0 no interrupt is generated after this buffer has been used. 1 an rx buffer event is sent to the interrupt queue after the atm controller uses this buffer. fcce[gint x ] is set in the event register when int_cnt reaches the global interrupt threshold. 4 l last in frame. set by the atm controller for the last buffer in a frame. 0 buffer is not last in a frame. 1 buffer is last in a frame. atm controller writ es frame length in dl and updates the error flags. 5 f first in frame. set by the atm contro ller for the first buffer in a frame. 0 the buffer is not the first in a frame. 1 the buffer is the first in a frame. 6 cm continuous mode 0 normal operation. 1 the cp does not clear the empty bit after this bd is closed, allowing the associated buffer to be overwritten automatically when the cp next accesses this bd. 7?9 ? reserved, should be cleared. 10 clp cell loss priority. at least one cell associated with the current message was received with clp = 1. may be set at the last buffer of the message. 11 cng congestion indication. the last cell associ ated with the current message was received with pti middle bit set. cng may be set at the last buffer of the message. 12 abrt abort message indication. the current message was received with length field zero. 13 cpuu cpcs-uu+cpi indication. set when the cpcs-uu+cpi field is non zero. cpuu may be set at the last buffer of the message. 14 lne rx length error. aal5 cpcs-pdu length violatio n. may be set only for the last bd of the frame if the pad length is greater than 47 or less than zero octets. 15 cre rx crc error. indicates crc32 error in the curr ent aal5 pdu. set only for the last bd of the frame. 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 41-69 41.10.5.5 aal1 rxbd figure 41-48 shows the aal1 rxbd. table 41-35 describes aal1 rxbd fields. 0x02 ? dl data length. the number of octets written by the cp into this bd?s buffer. it is written by the cp once the bd is closed. in the last bd of a frame, dl contains the total frame length. 0x04 rxdbptr rx data buffer pointer. points to the first location of the associated buffer; may reside in internal or external memory. this pointer must be burst-aligned. 1 boldfaced entries must be initialized by the user. 0123456789101112131415 offset + 0x00 e ? wi sne ? cm ? offset + 0x02 data length offset + 0x04 rx data buffer pointer offset + 0x06 figure 41-48. aal1 rxbd table 41-35. aal1 rxbd field descriptions offset bits name 1 description 0x00 0 e empty 0 the buffer associated with this rxbd is filled with received data or data reception was aborted due to an error. the core can read or write any fields of this rxbd. the cp cannot use this bd again while e = 0. 1 the buffer is not full. this rxbd and its asso ciated receive buffer are owned by the cp. once e is set, the core should not wr ite any fields of this rxbd. 1 ? reserved, should be cleared. 2 w wrap (final bd in table) 0 this is not the last bd in the rxbd table of the current channel. 1 this is the last bd in the rxbd table of this current channel. after this buffer is used, the cp receives incoming data into the first bd in the table. the num ber of rxbds in this table is programmable and is determined only by the w bit. the current table overall space is constrained to 64 kbytes. 3 i interrupt 0 no interrupt is generated after this buffer has been used. 1 an rx buffer event is sent to the interrupt queue after the atm controller uses this buffer. fcce[gint x ] is set when the int_cnt reaches the global interrupt threshold. 4 sne sequence number error. sne is set when a se quence number error is detected in the current aal1 ces buffer. 5 ? reserved, should be cleared. table 41-34. aal5 rxbd field descriptions (continued) offset bits name 1 description 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 41-70 freescale semiconductor 41.10.5.6 aal0 rxbd figure 41-49 shows the aal0 rxbd. table 41-36 describes aal0 rxbd fields. 0x00 6 cm continuous mode 0 normal operation. 1 the empty bit (rxbd[e]) is not cleared by t he cp after this bd is closed, allowing the associated buffer to be overwritten automa tically when the cp next accesses this bd. 7?15 ? reserved, should be cleared. 0x02 ? dl data length. the number of octets the cp writes into the buffer once its bd is closed. 0x04 ? rxdbptr rx data buffer pointer. points to the first location of the associated buffer; may reside in either internal or external memory. this pointer must be burst-aligned. 1 boldfaced entries must be initialized by the user. 01234567 9101112 15 offset + 0x00 e ? wi ? cm ?creoam ? offset + 0x02 data length (dl)/channel code (cc) offset + 0x04 rx data buffer pointer (rxdbptr) offset + 0x06 figure 41-49. aal0 rxbd table 41-36. aal0 rxbd field descriptions offset bits name 1 description 0x00 0 e empty 0 the buffer associated with this rxbd is filled with received data, or data reception was aborted due to an error. the core can examine or write to any fields of this rxbd. the cp does not use this bd again while e remains zero. 1 the rx buffer is empty or reception is in progress. this rxbd and its associated receive buffer are owned by the cp. once e is set, the co re should not write any fields of this rxbd. 1 ? reserved, should be cleared. 2 w wrap (final bd in table) 0 this is not the last bd in the rxbd table of the current channel. 1 this is the last bd in the rxbd table of t he current channel. after this buffer has been used, the cp will receive incoming data into the first bd in the table. the number of rxbds in this table is programmable and is determined only by the w bit. the current table cannot exceed 64 kbytes. 3 i interrupt 0 no interrupt is generated after this buffer has been used. 1 an rx buffer event is sent to the interrupt queue after the atm controller uses this buffer. fcce[gint x ] is set when the int_cnt reaches the global interrupt threshold. table 41-35. aal1 rxbd field descriptions (continued) offset bits name 1 description 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 41-71 41.10.5.7 aal2 rxbd refer to section 42.4.4.4, ?cps receive buffer descriptor (rxbd).? 41.10.5.8 aal5 user-defined cell?rxbd extension in user-defined cell mode, the aal5 and aal1 ces rxbds are extended to 32 bytes; see figure 41-50 . note for aal0, a complete cell, including the udc header, is stored in the buffer; the aal0 bd size is always 8 bytes. 0x00 4?5 ? reserved, should be cleared. 6 cm continuous mode 0 normal operation. 1 the cp does not clear the e bit after this bd is closed, allowing the associated buffer to be overwritten automatically when t he cp next accesses this bd. 7?9 ? reserved, should be cleared. 10 cre rx crc error. indicates a crc10 error in t he current aal0 buffer. the cre bit is considered an error only if the received cell had a crc10 field in the cell payload. 11 oam operation and maintenance cell. if oam is se t, the current aal0 buffer contains an oam cell. this cell is associated with the channel indicated by the channel code field (cc field). 12-15 ? reserved, should be cleared. 0x02 ? dl/cc data length/channel code. if rxbd[oam] is se t, this field functions as cc; otherwise, it is dl. data length is the size in octets of this bu ffer (mrblr value). channel code specifies the channel code associated with this oam cell. 0x04 ? rxdbptr rx data buffer pointer. points to the first location of the associated buffer; may reside in either internal or external memory. this pointer must be burst-aligned. 1 boldfaced entries must be initialized by the user. offset + 0x08 extra cell header. used to store the user-defined cell?s extra cell he ader. the extra cell header can be 1?12 bytes long. offset + 0x14 reserved (12 bytes) figure 41-50. user-defined cell?rxbd extension table 41-36. aal0 rxbd field descriptions (continued) offset bits name 1 description 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 41-72 freescale semiconductor 41.10.5.9 aal5 txbds figure 41-51 shows the aal5 txbd. table 41-37 describes aal5 txbd fields. 0123456789101112131415 offset + 0x00 r ? wi l ? cm ? clp cng ? offset + 0x02 data length (dl) offset + 0x04 tx data buffer pointer (txdbptr) offset + 0x06 figure 41-51. aal5 txbd table 41-37. aal5 txbd field descriptions offset bits name 1 description 0x00 0 r ready 0 the buffer associated with this bd is not read y for transmission. the user is free to manipulate this bd or its associated buffer. the cp clears r after the buffer is sent or after an error condition is encountered. 1 the user-prepared buffer has not been sent or is currently being sent. no fields of this bd may be written by the user once r is set. 1 ? reserved, should be cleared. 2 w wrap (final bd in table) 0 not the last bd in the txbd table. 1 last bd in the txbd table. after this buffer is used, the cp sends outgoing data from the first bd in the table (the bd pointed to by the channel?s tct[tbd_base]). the number of txbds in this table is determined only by the w bi t. the current table cannot exceed 64 kbytes. 3 i interrupt 0 no interrupt is generated after this buffer has been serviced. 1 a tx buffer event is sent to the interrupt queue after this buffer is serviced. fcce[gint x ] is set when the int_cnt counter reaches the global interrupt threshold. 4 l last in frame. set by the user to indicate the last buffer in a frame. 0 buffer is not last in a frame. 1 buffer is last in a frame. 5 ? reserved, should be cleared. 6 cm continuous mode 0 normal operation. 1 the cp does not clear r after this bd is closed, allowing the associated buffer to be retransmitted automatically when the cp next a ccesses this bd. however, the r bit is cleared if an error occurs during transmission, regardless of cm. 7-9 ? reserved, should be cleared. 10 clp the atm cell header clp bit of the cells associ ated with the current frame are ored with this field. this field is valid only in the first bd of the frame. 11 cng the atm cell header cng bit of the cells associ ated with the current frame are ored with this field. this field is valid only in the first bd of the frame. 12?15 ? reserved, should be cleared. 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 41-73 41.10.5.10 aal1 txbds figure 41-52 shows the aal1 txbd. table 41-38 describes aal1 txbd fields. 0x02 ? dl the number of octets the atm contro ller should transmit from this bd?s buffer. it is not modified by the cp. the value of dl should be greater than zero. 0x04 ? txdbptr tx data buffer pointer. points to the address of the associated buffer, which may or may not be 8-byte-aligned. the buffer may reside in either internal or external memory. this value is not modified by the cp. 1 boldfaced entries must be initialized by the user. 0123456789101112131415 offset + 0x00 r ? wi ? cm ? offset + 0x02 data length (dl) offset + 0x04 tx data buffer pointer (txdbptr) offset + 0x06 figure 41-52. aal1 txbd table 41-38. aal1 txbd field descriptions offset bits name description 0x00 0 r ready 0 the buffer associated with this bd is not ready for transmission. the user is free to manipulate this bd or its associated buffer. the cp clears this bit after the buffer has been sent or after an error condition is encountered. 1 the buffer prepared for transmission by the user has not been sent or is being sent. no fields of this bd may be written by the user once r is set. 1 ? reserved, should be cleared. 2 w wrap (final bd in table) 0 not the last bd in the txbd table. 1 last bd in the txbd table. after this buffer is used, the cp sends outg oing data from the first bd in the table (the bd pointe d to by the channel?s tct[tbd_base]). the number of txbds in this table is determined only by the w bit. the current table cannot exceed 64 kbytes. 3 i interrupt 0 no interrupt is generated after this buffer has been serviced. 1 a tx buffer event is sent to the interrupt queue after this buffer is serviced. fcce[gint x ] is set when the int_cnt counter reaches the global interrupt threshold. 4?5 ? reserved, should be cleared. 6 cm continuous mode 0 normal operation. 1 the cp does not clear the ready bit after this bd is closed, allowing the associated buffer to be retransmitted automati cally when the cp next accesses this bd. table 41-37. aal5 txbd field descriptions (continued) offset bits name 1 description 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 41-74 freescale semiconductor 41.10.5.11 aal0 txbds figure 41-53 shows aal0 txbds. note that the data length field is calculated intern ally as 52 bytes, plus the extra header length (defined in fpsmr[tehs]) when in udc mode. table 41-39 describes aal0 txbd fields. 0x00 7?11 ? reserved, should be cleared. 0x02 ? dl the number of octets the atm cont roller should transmit from this bd?s buffer. it is not modified by the cp. the value of dl should be greater than zero. 0x04 ? txdbptr tx data buffer pointer. points to the address of the associated buffer. the buffer may reside in either internal or external memory. this value is not modified by the cp. 01234567 101112 15 offset + 0x00 r ? wi ? cm ? oam ? offset + 0x02 ? offset + 0x04 tx data buffer pointer (txdbptr) offset + 0x06 figure 41-53. aal0 txbds table 41-39. aal0 txbd field descriptions offset bits name 1 description 0x00 0 r ready 0 the buffer is not ready for transmission. the us er can manipulate this bd or its buffer. the cp clears r after the buffer has been sent or after an error occurs. 1 the buffer that the user prepared for transmission has not been sent or is being sent. no fields of this bd may be written by the user once r is set. 1 ? reserved, should be cleared. 2 w wrap (final bd in table) 0 not the last bd in the txbd table. 1 last bd in the txbd table. after this buffer is used, the cp sends outgoing data from the first bd in the table (the bd pointed to by the channel?s tct[tbd_base]). the number of txbds in this table is determined by the w bit. the current table is constrained to 64 kbytes. 3 i interrupt 0 no interrupt is generated after this buffer has been serviced. 1 a tx buffer event is sent to the interrupt queue after this buffer is serviced. fcce[gint x ] is set when the int_cnt counter reaches the global interrupt threshold. 4?5 ? reserved, should be cleared. 6 cm continuous mode 0 normal operation. 1 the cp does not clear the ready bit after this bd is closed, allowing the associated buffer to be retransmitted automatically wh en the cp next accesses this bd. 7?10 ? reserved, should be cleared. table 41-38. aal1 txbd field descriptions (continued) offset bits name description 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 41-75 41.10.5.12 aal2 txbds refer to section 42.3.5.5, ?sssar transmit buffer descriptor.? 41.10.5.13 aal5, aal1 user-def ined cell?txbd extension in user-defined cell mode, the aal5 a nd aal1 txbds are extended to 32 bytes; see figure 41-54 . note for aal0 a complete cell, including the udc header, is stored in the buffer; the aal0 bd size is always 8 bytes. 41.10.6 aal1 sequence number (sn) protection table the 32-byte sequence number protecti on table, pointed to by aal1_snp t_base in the atm parameter ram, resides in dual-port ram and is used for aal1 only. the ta ble should be initia lized according to figure 41-55 . 0x00 11 oam operation and maintenance cell. if oam is set, the current aal0 buffer contains an f5 or f4 oam cell. performance monitoring calculations are not done on oam cells. 11?15 ? reserved, should be cleared. 0x02 ? ? reserved, should be cleared. 0x04 ? txdbptr tx data buffer pointer. points to the address of the associated buffer, which may or may not be 8-byte-aligned. the buffer may reside in either internal or external memory. this value is not modified by the cp. 1 boldfaced entries must be initialized by the user. offset + 0x08 extra cell header. used to store the user-defined cell?s extra cell he ader. the extra cell header can be 1?12 bytes long. offset + 0x14 reserved (12 bytes) figure 41-54. user-defined cell?txbd extension table 41-39. aal0 txbd field descriptions offset bits name 1 description 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 41-76 freescale semiconductor 41.10.7 uni statistics table the uni statistics table, shown in table 41-40 , resides in the dua l-port ram and holds uni statistics parameters. uni_statt_base points to the base addr ess of this table. each phy?s own table has a starting address given by uni_statt_base+ phy# 8. 0 15 offset + 0x00 0x0000 offset + 0x02 0x0007 offset + 0x04 0x000d offset + 0x06 0x000a offset + 0x08 0x000e offset + 0x0a 0x0009 offset + 0x0c 0x0003 offset + 0x0e 0x0004 offset + 0x10 0x000b offset + 0x12 0x000c offset + 0x14 0x0006 offset + 0x16 0x0001 offset + 0x18 0x0005 offset + 0x1a 0x0002 offset + 0x1c 0x0008 offset + 0x1e 0x000f figure 41-55. aal1 sequence number (sn) protection table table 41-40. uni statistics table offset 1 1 offset from uni_statt_base+phy# 8. name width description 0x00 utopiae hword counts cells dropped as a result of ut opia/atm protocol violations. violations include the following: 1. parity error 2. hec error 3. invalid timing of rxsoc. if rxclav is asserted for the selected phy, rxsoc should be asserted the cycle immediately following the assertion of rxenb . a violation occurs if rxsoc is not asserted at that time (that is, it is late or missing). 0x02 mic_count hword counts misinserted cells dro pped as a result of address look-up failure. 0x04 crc10e_count hword counts cells dropped as a result of crc10 failure. aal5-abr only. 0x06 ? hword reserved, should be cleared. 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 41-77 41.11 atm exceptions the atm controller interrupt handling involves tw o principal data structures: fcces (fcc event registers) and circular interrupt queues. four priority interrupt queues are available. by programming rct[intq] and tct[intq], the user determines which queue receives the interrupt. channel rx buffer, rx frame, or tx buffer events can be masked by clearing interrupt mask bits in rct and tct. note ensure that the transmit intqs and the receive intqs are programmed as separate queues. after an interrupt request, the host reads fcce. if fcce[gint x ] = 1, at least one entry was added to one of the interrupt queues. after clearing fcce[gint x ], the host processes the va lid interrupt queue entries and clears each entry?s valid bit. the host follows this procedure until it reaches an entr y with v = 0. see section 41.11.2, ?interrupt queue entry.? the host controls the number of interrupts sent to th e core using a down counter in the interrupt queue?s parameter table; see section 41.11.3, ?interrupt queue parameter tables.? for each event sent to an interrupt queue, a counter (that has been initialized to a threshold number of interrupts) is decremented. when the counter reaches zero, the global interrupt, fcce[gint x ], is set. 41.11.1 interrupt queues interrupt queues are located in external memory. the pa rameters of each queue are stored in a table. see section 41.11.3, ?interrupt queue parameter tables.? when an interrupt occurs, the cp writes a new entry to the interrupt queue, the v bit is set, and the queue pointer (intq_ptr) is incremented. on ce the cp uses an entry with w = 1, it returns to the first entry in the queue. if the cp tries to overwrite a valid entry (v = 1), an overflow condi tion occurs and the queue?s overflow flag, fcce[into x ], is set. the interrupt queue structure is displayed in figure 41-56 . figure 41-56. interrupt queue structure v = 0 w = 0 invalid v = 0 w = 0 invalid v = 0 w = 0 invalid v = 1 w = 0 interrupt entry v = 1 w = 0 interrupt entry v = 1 w = 0 interrupt entry v = 0 w = 0 invalid v = 0 w = 0 invalid v = 0 w = 1 invalid intq_base s oftware (core) pointer intq_ptr word 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 41-78 freescale semiconductor 41.11.2 interrupt queue entry each one-word interrupt queue entry provides de tailed interrupt information to the host. figure 41-57 shows an entry. table 41-41 describes interrupt queue entry fields. 41.11.3 interrupt queue parameter tables the interrupt queue parameters are held in parameter tables in the dual-port ram; see table 41-42 . intt_base in the parameter ram points to the base a ddress of these tables. each of the four interrupt queues has its own parameter ta ble with a starting address gi ven by intt_base+ rct/tct[intq] 16. 01 23456789101112131415 offset + 0x00 v ? w ? tbnr rxf bsy txb rxb offset + 0x02 channel code (cc) figure 41-57. interrupt queue entry table 41-41. interrupt queue entry field descriptions offset bits name 1 1 boldfaced entries must be initialized by the user. description 0x00 0 v valid interrupt entry 0 this interrupt queue entry is free and can be use by the cp. 1 this interrupt queue entry is valid. the host should read this interrupt and clear this bit. 1 ? reserved, should be cleared. 2 w wrap bit. when set, this is the last interrupt circ ular table entry. during init ialization, the host must clear all w bits in the table except the last one, which must be set. 3?10 ? reserved, should be cleared. 11 tbnr tx buffer-not-ready. set when a transmit buffer-not-ready interrupt is issued. this interrupt is issued when the cp tries to open a txbd that is not ready (r = 0). this interrupt is sent only if tct[bnm] = 1. this interrupt has an associated channel code. note that for aal5, this interrupt is sent only if frame transmission is started. in this case, an abort frame transmission is sent (last cell with length =0), the channel is taken out of the apc, and the tct[vcon] flag is cleared. 12 rxf rx frame. rxf is set when an rx frame interrupt is issued. this interrupt is issued at the end of aal5 pdu reception. this interrupt is issued only if rct[rxfm] = 1. this interrupt has an associated channel code. 13 bsy busy condition. the bd table or the free buffer pool associated with this channel is busy. cells were discarded due to this condition. this interrupt has an associated channel code. 14 txb tx buffer. txb is set when a transmit buffer in terrupt is issued. this interrupt is enabled when both txbd[i] and tct[imk] = 1. this interrupt has an associated channel code. 15 rxb rx buffer. rxb is set when an rx buffer interrupt is issued. this interrupt is enabled when both rxbd[i] and rct[rxbm] = 1. this interrupt has an associated channel code. 0x02 ? cc channel code specifies the channel associated with this interrupt. 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 41-79 41.12 utopia interface the atm controller interfaces with a phy de vice through the utopia interface. the MPC8555E supports utopia level ii for both master and slave modes. 41.12.1 extended number of phys the MPC8555E has additional pin m uxing to support 31 phys on both fc c1 and fcc2. to utilize this feature, do the following: ? select dedicated utopia addre ss lines for fcc1 and fcc2 in the parallel i/o (txaddr[4:3], rxaddr[4:3]). refer to chapter 45, ?parallel i/o ports.? 41.12.2 utopia interface master mode cell transfer on an atm device (w ith single or multiple phys) uses ce ll-level handshaking as defined in the utopia standards. the fcc does not pause cell transmission by the phy and does not stop receiving cells from the phy. table 41-42. interrupt queue parameter table offset 1 1 offset from intt _base+rct/tct[intq] 16. name 2 2 boldfaced entries must be initialized by the user. width description 0x00 intq_base word base address of the interrupt queue. user-defined. 0x04 intq_ptr word pointer to interrupt queue entry. initialize to intq_base. 0x08 int_cnt half word interrupt counter. initialize with int_icnt . the cp decrements int_cnt for each interrupt. when int_cnt reaches zero, the queue?s global interrupt flag fcce[gint x ] is set. 0x0a int_icnt half word interrupt initial count. user-defined glob al interrupt threshold?the number of interrupts required before the cp issues a global interrupt (fcce[gint x ]). 0x0c intq_entry word interrupt queue entry. must be initialized to the entry pointed to by intq_ptr, which is initially the first empty entry of the queue. note that after an overrun occurs, this entry must be reset to the entry pointed to by intq_ptr to re-enable interrupt processing. 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 41-80 freescale semiconductor utopia master signals are shown in figure 41-58 . figure 41-58. utopia master mode signals table 41-43 describes utopia ma ster mode signals. table 41-43. utopia master mode signal descriptions signal description txdata[7:0] carries transmit data from the atm controller to a phy device. txdata[7] is the msb, txdata[0] is the lsb. txsoc transmit start of cell. asserted by the atm controller when the first byte of a cell is sent on txdata lines. txenb transmit enable. asserted by the atm controller when valid data is placed on the txdata lines. txclav/txclav[3:0] transmit cell available. asserted by the ph y device to indicate that the phy has room for a complete cell. txprty transmit parity. asserted by the atm controll er. it is an odd parity bit over the txdata bits. txclk transmit clock. provides the synchroniza tion reference for the txdata, txsoc, txenb , txclav, txprty signals. all the above signals are sampled at low-to-high transitions of txclk. txadd[4:0] transmit address. address bus from the atm controller to the phy device used to select the appropriate m-phy device. each m-phy device needs to maintain its address. txadd[4] is the msb. rxdata[7:0] carries receive data from the phy to the atm controller. rxdata[7] is the msb, rxdata[0] is the lsb. rxsoc receive start of cell. asserted by the phy devi ce as the first byte of a cell is received on rxdata. rxenb receive enable. an atm controller asserts to i ndicate that rxdata and rxsoc will be sampled at the end of the next rxclk cycle. for multiple phys, rxenb is used to three-state rxdata and rxsoc at each phy?s output. rxdata and rxsoc should be ena bled only in cycles after those with rxenb asserted. rxclav/rxclav[3:0] receive cell available. asserted by a phy de vice when it has a complete cell to give the atm controller. rxprty receive parity. asserted by the phy device. it is an odd parity bit over the rxdata. if there is a rxprty error and the receive parity check fpsmr[rx p] is cleared, the cell is discarded. see section 41.13.3, ?fcc protocol-specific mode register (fpsmr),? and section 41.10.7, ?uni statistics table.? rxclk receiver clock. synchronization reference for rxdata, rxsoc, rxenb , rxclav, and rxprty, all of which are sampled at low-to-high transitions of rxclk. rxadd[4:0] receive address. address bus from the atm cont roller to the phy device used to select the appropriate m-phy device. each m-phy device needs to maintain its address. rxadd[4] is the msb. txdata[7:0] txsoc txenb txprty txclk txclav[3:0]/txclav txadd[4:0] rxdata[7:0] rxsoc rxenb rxprty rxclk rxclav[3:0]/rxclav rxadd[4:0] MPC8555E MPC8555E 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 41-81 41.12.2.1 utopia master multiple phy operation the MPC8555E supports two polling modes: ? direct polling uses clav[3:0] with phy selecti on using add[2:0]. up to four phys can be supported. ? single clav polling uses clav and add[4:0]. atm controller polls all act ive phys starting from phy address 0x0 to the addres s written in fpsmr[last_phy]. up to 31 phy devices are supported. both modes support round-robin priority or fixed priority, described in section 41.13.3, ?fcc protocol-specific mode register (fpsmr).? 41.12.3 utopia interface slave mode in utopia slave mode (s ingle or multiple phy), ce lls are transferred using cell-level and octet-level handshakes as defined by the utopia level ii standard . the fcc allows cell transfer to be halted or paused. if the master negates txenb , the cell that the fcc is transmitti ng is halted. if the master negates rxenb , the cell that the fcc is receiving is paused. note the following rest riction on halting a cell transfer: there cannot be a ha lt immediately before the tran sfer of the last data wo rd. there is no restriction on pausing a cell transfer. utopia slave signals are shown in figure 41-59 . figure 41-59. utopia slave mode signals table 41-44 describes utopia slave mode signals. table 41-44. utopia slave mode signals signal description txdata[7:0] transmit data bus. carries transmit data from the atm controller to the master device. txdata[7] is the msb, txdata[0] is the lsb. txsoc transmit start of cell. asserted by an atm controller as the first byte of a cell is sent on the txdata lines. txenb transmit enable. an input to the atm controller. it is asserted by the utopia master to signal the slave to send data in the next txclk cycle. txclav transmit cell available. asserted by the atm cont roller to indicate it has a complete cell to transmit. txprty transmit parity. asserted by the atm cont roller. it is an odd parity bit over the txdata. txdata[7:0] txsoc txenb txprty txclk txclav txadd[4:0] rxdata[7:0] rxsoc rxenb rxprty rxclk rxclav rxadd[4:0] MPC8555E MPC8555E 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 41-82 freescale semiconductor 41.12.3.1 utopia slave multiple phy operation the user should write the atm contro ller phy address in fpsmr[phy id]. 41.12.3.2 utopia clocking modes the utopia clock can be generated internally or ex ternally. if the utopia clock is to be generated internally, the user should assign one of the baud- rate generators to supply the utopia clock. see chapter 24, ?cpm multiplexing.? 41.12.3.3 utopia loopback modes the utopia interface supports loopback mode. in this mode, the rx a nd tx utopia signals are shorted internally. output pins are dr iven; input pins are ignored. note that in loopback mode, the tr ansmitter and receiver must opera te in complementary modes. for example, if the transmitter is master, the receiver must be a slave (fpsmr[t ums] = 0, fpsmr[rums] = 1). txclk transmit clock. provides the synchroniza tion reference for the txdata, txsoc, txenb , txclav, and txprty signals. all of the above signals are sampled at low-to-high transitions of txclk. txadd[4:0] transmit address. address bus from the master to the atm controller used to select the appropriate m-phy device. rxdata[7:0] receive data bus. carries receive data from the master to the atm controller. rxdata[7] is the msb, rxdata[0] is the lsb. rxsoc receive start of cell. asserted by the master device whenever the first byte of a cell is being received on the rxdata lines. rxenb receive enable. asserted by the master device to signal the slave to sample the rxdata and rxsoc signals. rxclav receive cell available. assert ed by the atm controller to indicate it can receive a complete cell. rxprty receive parity. asserted by the phy device. it is an odd parity bit over the rxdata[7:0]. if there is a rxprty error and the receive parity check fpsmr[rxp] is cleared, the cell is discarded. see section 41.13.3, ?fcc protocol-specific mode register (fpsmr),? and section 41.10.7, ?uni statistics table.? rxclk receive clock. provides the synchroniza tion reference for the rxdata, rxsoc, rxenb , rxclav, and rxprty signals. all the above signals are sa mpled at low-to-high transitions of rxclk. rxadd[4:0] receive address. address bus from master to the at m controller device used to select the appropriate m-phy device. table 41-44. utopia slave mode signals (continued) signal description 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 41-83 modes are selected through gfmr[diag], as shown in table 41-45 . 41.13 atm registers the following sections describe the conf iguration of the registers in atm mode. 41.13.1 general fcc mode register (gfmr) the gfmr mode field should be pr ogrammed for atm mode. to enable transmit and receive functions, ent and enr must be set as the last step in the in itialization process. full gfmr details are given in section 37.2, ?general fcc mode registers (gfmrx).? 41.13.2 general fcc expans ion mode register (gfemr x ) the general fcc expansi on mode registers (gfemr x ) define the expansion modes. they should be programmed according to the protocol used. table 41-46 describes gfemr x fields. table 41-45. utopia loopback modes diag description 00 normal mode 01 loopback. utopia rx and tx signals are shorted internally. output pins are driven, input pins are ignored. 1x reserved 0123 7 field tirem lpb clk ? reset 0000_0000 r/w r/w offset 0x9_1390 (gfemr1), 0x9_13b0(gfemr2) figure 41-60. general fcc expansion mode register (gfemr) table 41-46. gfemr x field descriptions bits name description 0 tirem transmit internal rate expanded mode (atm mode) 0 internal rate mode: internal rate for phys[0?3] is controlled only by ftirr[0?3]. firper, firsr_hi, firsr_lo, fiter are unused. 1 internal rate expanded mode: phys[0?31] are controlled by ftirr[0?3], firper, firsr_hi and firsr_lo. underrun status for phys[0?3 1] is available by firer. this bit should be set only in transmit master multi-phy mode. in this mode mixing of internal rate and external rate is not enabled. 1 lpb rmii loopback diagnostic mode (ethernet mode): 0 normal mode 1 loopback mode 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 41-84 freescale semiconductor 41.13.3 fcc protocol-specifi c mode register (fpsmr) the fcc protocol-specific mode register (fpsmr), shown in figure 41-61 , controls various protocol-specific fcc functions. the user should initialize the fpsmr. erratic behavior may result if there is an attempt to write to the fpsmr wh ile the transmitter and receiver are enabled. table 41-47 describes fpsmr fields. 2 clk rmii reference clock rate for 50 mhz input clock from external oscillator (ethernet mode): 0 50 mhz (for fast ethernet) 1 5 mhz (for 10baset) 3?7 ? reserved, should be cleared. 0 3 4 7 8 9 10 11 15 field tehs rehs icd tums rums last phy/phy id reset 0000_0000_0000_0000 r/w r/w offset 0x0x9_1304 (fpsmr1), 0x0x9_1324 (fpsmr2) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field ? tpri tudc rudc rxp tump ? tsize rsize uprm uplm rump heci hecc cos reset 0000_0000_0000_0000 r/w r/w offset 0x9_1306 (fpsmr1), 0x9_1326 (fpsmr2) figure 41-61. fcc atm mode register (fpsmr) table 41-47. fcc atm mode register (fpsmr) bits name description 0?3 tehs note: transmit extra header size. used only in user-def ined cell mode to hold the tx user-defined cells? extra header size. values between 0?11 are valid. te hs = 0 generates 1 byte of extra header; tehs = 11 generates 12 bytes of extra header. 4?7 rehs receive extra header size. used only in user-defin ed cell mode to hold the rx user-defined cells? extra header size. values between 0?11 are valid. for rehs = 0, the receiver expects 1 byte of extra header; for rehs = 11, it expects 12 bytes of extra header. 8 icd idle cells discard 0 discard idle cells (g fc, vpi, vci, pti =0) 1 do not discard idle cells 9 tums transmit utopia master/slave mode 0 transmit utopia master mode is selected 1 transmit utopia slave mode is selected table 41-46. gfemr x field descriptions (continued) bits name description 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 41-85 10 rums receive utopia master/slave mode 0 receive utopia master mode is selected 1 receive utopia slave mode is selected 11?15 last phy/ phy id last phy. (multiple phy master mode only.) the ut opia interface polls all phys starting from phy address 0 and ending with the phy address specified in last phy. (the number of active phys are last phy+1). last phy should be specified in both single-clav and direct-polling modes. phy id. (multiple phy slave mode only.) determines the phy address of the atm controller when configured as a slave in a multiple phy atm port. note: 16?17 ? reserved, should be cleared. 18 tpri transmitter priority. used to adjust the default prio rity of the fcc transmitter. it is strongly recommended to set tpri when in multi-phy mode; for other modes, it should remain cleared. 0 default operation 1 prevents elevation to emergency mode refer to ta bl e 2 1 - 5 . 19 tudc transmit user-defined cells 0 regular 53-byte cells 1 user-defined cells 20 rudc receive user-defined cells 0 regular 53-byte cells 1 user-defined cells 21 rxp receive parity check. 0 check rx parity line 1 do not check rx parity line 22 tump transmit utopia multiple phy mode 0 transmit utopia single phy mode is selected 1 transmit utopia multiple phy mode is selected 23 ? reserved, should be cleared. 24 tsize transmit utopia data bus size 0 utopia 8-bit data bus size 1 reserved 25 rsize receive utopia data bus size 0 utopia 8-bit data bus size 1 reserved 26 uprm utopia priority mode. 0 round robin. polling is done from phy zero to the phy specified in last phy. when a phy is selected, the utopia interface continues to poll the next phy in order. 1 fixed priority. polling is done from phy zero to th e phy specified in last phy. when a phy is selected, the utopia interface continues to poll from phy zero. 27 uplm utopia polling mode. 0 single clav polling. polling is done using add[4:0] and clav. selection is done using add[4:0]. up to 31 phys can be polled. 1 direct polling. polling is done using clav[3:0]. selection is done using add[1:0]. up to 4 phys can be polled. table 41-47. fcc atm mode register (fpsmr) (continued) bits name description 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 41-86 freescale semiconductor 41.13.4 atm event register (fcce)/mask register (fccm) the fcce register is the atm controller event regi ster when the fcc operates in atm mode. when it recognizes an event, the atm controller sets the corresponding fcce bit. interrupts generated by this register can be masked in fccm. fcce is memory-ma pped and can be read at a ny time. bits are cleared by writing ones to them; writing zero s has no effect. unmasked bits must be cleared before the cp clears the internal interrupt request. fccm is the atm controller mask register. the fccm has the same bit format as fcce. setting an fccm bit enables and clearing a bit mask s the corresponding interrupt in the fcce. 28 rump receive utopia multiple phy mode. 0 receive utopia single phy mode is selected 1 receive utopia multiple phy mode is selected 29 heci hec included. used in udc mode only. 0 hec octet is not included when udc mode is enabled. 1 hec octet is included when udc mode is enabled. 30 hecc receive hec check 0 do not check rx hec 1 check rx hec. hec errors are reported in utopiae counter (see section 41.10.7, ?uni statistics ta bl e ? ). 31 cos coset mode enable 0 check rx hec with no coset 1 check rx hec with coset mode enabled 0 456 7 8 9 101112131415 field ? tiru grli gbpb gint3 gint2 gint1 gint0 into3 into2 into1 into0 reset 0000_0000_0000_0000 r/w r/w offset 0x0x9_1310 (fcce1), 0x0x9_1330 (fcce2), 0x0x9_1314 (fccm1), 0x0x9_1334 (fccm2) 16 31 field ? reset 0000_0000_0000_0000 r/w r/w offset 0x9_1312 (fcce1), 0x9_1332 (fcce 2), 0x9_1316 (fccm1) , 0x9_1336 (fccm2) figure 41-62. atm event register (fcce)/fcc mask register (fccm) table 41-47. fcc atm mode register (fpsmr) (continued) bits name description 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 41-87 table 41-48 describes fcce fields. 41.13.5 fcc transmit internal rate registers (ftirr x ) the first four phy devices (address 00?03) on fcc1 an d fcc2 have their own transmit internal rate registers (ftirr x _phy0?ftirr x _phy3) for use in transmit internal rate mode. in this mode, the total transmission rate is determined by fcc internal rate timers. as a ma ster, the controller only polls the phy?s clav status at the rate determined by the internal rate. as a slave, the controller attempts to insert cells into the fifo at the internal rate. the controller can handle a lag of up to seven cell s per phy between the programmable and actual bus rate. when the ce ll count mismatch reaches seven, tiru event is reported, see section 41.13.4, ?atm event register (fcce)/mask register (fccm).? note that a mismatch occurs if the phy rate or the cpm perf ormance are lower then the internal rate. ftirr x , shown in figure 41-63 , includes the initial value of the internal rate timer. the source clock of the internal rate timers is supplied by one of four baud-ra te generators selected in cmxuar; see section 24.4.1, ?cmx utopia address register (cmxuar).? note that in slave mode, ftirr x _phy0 is used regardless of the slave phy address. table 41-48. fcce/fccm field descriptions bits name description 0?4 ? reserved, should be cleared. 5 tiru transmit internal rate underrun. a cumulative lag of seven cells has formed between the programmable rate and the actual rate for a specific phy. a transmit inte rnal rate counter expired and a cell was not sent, either because of slow cpm performance or slow phy perfor mance. tiru may be set only when using transmit internal rate mode; see section 41.13.5, ?fcc transmit inte rnal rate registers (ftirrx).? 6 grli global red-line interrupt. grli is set when a free buffer pool?s rli flag is set. the rl i flag is also set in the free buffer pool?s parameter table. 7 gbpb global buffer pool busy interrupt. gbpb is set when a free buffer pool?s busy flag is set. the busy flag is also set in the free buffer pool?s parameter table. 8?11 gint x global interrupt. set when the number of events sent to the corresponding interrupt queue reaches the corresponding event threshold. see section 41.11, ?atm exceptions.? 12?15 into x interrupt queue overflow. set when an overflow condition occurs in the corresponding interrupt queue. this occurs when the cp attempts to overwrite a valid interrupt entry. see section 41.11.1, ?i nterrupt queues.? 16?31 ? reserved, should be cleared. 01234567 field trm initial value reset 0000_0000 r/w r/w offset fcc1: 0x0x9_131c (ftirr1_phy0), 0x0x9_131d (ftirr1_phy1), 0x0x9_131e (ftirr1_phy2), 0x0x9_131f (ftirr1_phy3) fcc2: 0x0x9_133c (ftirr2_phy0), 0x0x9_133d (ftirr2_phy1), 0x0x9_133e (ftirr2_phy2), 0x0x9_133f (ftirr2_phy3) figure 41-63. fcc transmit internal rate registers (ftirr x ) 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 41-88 freescale semiconductor table 41-49 describes ftirr x fields. figure 41-64 shows how transmit cl ocks are determined. . figure 41-64. fcc transmit internal rate clocking example: suppose the MPC8555E is connected to four 155-mbps phy devices a nd the maximum transmission rate is 155 mbps for the first phy and 10 mbps for th e rest of the phys. th e brg clk should be set according to the highest rate. if the system clock is 133 mhz, the brg should be programmed to divide the system clock by 362 to generate cell transmit requests ever y 362 system clocks: for the 155 mbps phy, the ftirr divider should be programmed to zero (the brg clk is divided by one); for the rest of the 10 mbps phys, the ftirr divider should be programmed to 14 (the brg clk is divided by 15). see also section 41.16.1, ?using transmit internal rate mode.? 41.14 atm transmit command the cpm command set includes an atm transmit that can be sent to the cp command register (cpcr), described in section 21.3.1, ?cp command register (cpcr).? the atm transmit command (cpcr[opcode] = 0b1010, cpcr[sbc[code]] = 0b01110, cpcr[sbc[page]] = 0b00100 or 0b00101) turns a passive cha nnel into an active channel by inserting it into the apc scheduling table. note that an atm transmit command should be issued only after the channel?s tct is completely initialized and the ch annel has bds ready to transmit. note also that cpcr[sbc[code]] = 0b01110 and not fcc1 or fcc2 code. table 41-49. ftirr x field descriptions bits name description 0 trm transmit mode. 0 external rate mode. 1 internal rate mode. 1?7 initial value the initial value of the internal rate timer. a value of 0x7f produces the minimum clock rate (brg clk divided by 128); 0x00 produces the maximum clock rate (brg clk divided by 1). brg clk phy#0 internal rate timer phy# 0 tx rate phy# 1 tx rate phy# 2 tx rate phy# 3 tx rate phy#3 internal rate timer phy#2 internal rate timer phy#1 internal rate timer 133mhz 53 8 () () 155.52mbps ----------------------------------------------------- 362 = 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 41-89 before issuing the command, the user should initia lize comm_info fields in the parameter ram as described in figure 41-65 . table 41-50 describes comm_info fields. 41.15 expanded internal rate 41.15.1 transmit external rate and internal rate modes the atm controller supports th e following three rate modes: ? external rate mode?the total transmission rate is determined by the ph y transmission rate. the fcc sends cells to keep the phy fifos full; the fcc inserts idle/unassign cells to maintain the transmission rate. ? internal rate mode?the total transmission rate is determined by the fcc internal rate timers. in this mode, the fcc does not insert idle/unassign cells. the internal rate mechanism is supported for the first four phy devices (phy address 0- 3). each phy has its own ftirr, described in section 41.13.5, ?fcc transmit intern al rate registers (ftirrx).? the ftirr includes the initial value of the internal rate timer. a cell tran smit request is sent when an internal rate timer offset 0123456789101112131415 0x86 ? ctb phy# act pri 0x88 channel code (cc) 0x8a bt figure 41-65. comm_info field table 41-50. comm_info field descriptions offset bits name description 0x86 0?4 ? reserved, should be cleared. 5 ctb connection tables bus. used for external channels only 0 external connection tables reside on the system bus. 1 external connection tables reside on the local bus. 6?10 phy# phy number. in single phy mode this field should be cleared in multiple phy mode this field is an index to the apc parameter table associated with this channel. 11?12 act atm channel type 00 other channel 01 vbr channel 1x reserved 13?15 pri apc priority level. 000 highest priority (apc_level1) 111 lowest priority (apc_level8). 0x88 0?15 cc channel code. the channel code associated with the current channel. 0x8a 0?15 bt burst tolerance. for use by vbr channels only (act field is 0b01). specifies the initial burst tolerance (gcra burst credit) of the current vc. 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 41-90 freescale semiconductor expires. when using internal rate mode, the user assigns one of the baud- rate generators (brgs) to clock the four internal rate timers. ? internal rate expanded mode?the total transmissi on rate is determined by the fcc internal rate timers and by the assignment of rate per phy. in this mode, the fcc does not insert idle/unassign cells. the internal rate expanded m ode differs from the internal rate mode in that the internal rate mechanism is extended for 31 phy devices (phy addresses 0-30) and ther e cannot be a mix of external and internal rate phys. expanded inte rnal rate is configured by registers gfemrx, firperx, firsrx_hi, firsrx_lo, and by ftirrx. another featur e of internal rate expanded mode is an indication of transmit underrun error st atus per phy. when usin g internal rate expanded mode, the user assigns one of the ba ud-rate generators (brgs) to cloc k the four internal rate timers, and any timer can trigger any phy. 41.15.2 fcc transmit internal rate mode in internal rate mode the total tran smission rate is the sum of the rates assigned for all phys. this register controls how internal rate is configured. in intern al rate mode (gfemr[tirem ] = 0), the internal rate assigned per phy is configured by registers ftirr[0?3]. in internal rate expanded mode (gfemr[tirem] = 1), registers ft irr[0?3] control the available ra tes, but the phy settings are configured in registers firper, firsr_hi and firsr_lo. in tirem = 0 mode internal rate can only be used for phys[0?3], wh ereas in tirem = 1 mode up to 31 phys are supporte d. if tirem = 1 mode is selected, the transmit internal ra te underrun (tiru) status per phy may be read at any time in register firer. 41.15.3 fcc transmit internal rate port enable register (firper) this register enables internal ra te transmission for phys[0?30]. it is valid only if gfemr[tirem] = 1. if a phy is not enabled in firper, all txclav indica tions from that phy will be masked. the user should configure firper according to the phy addresses wh ich are being used on th e utopia bus and should not enable phys with addresses larger then the la st phy address set by fpsmr[ last phy]. phys can be enabled or disabled at any time?for ex ample, if a tiru event has occurred. 0123456789101112131415 field pe0 pe1 pe2 pe3 pe4 pe5 pe6 pe7 pe8 pe9 pe10 pe11 pe12 pe13 pe14 pe15 reset 0000_0000_0000_0000 r/w r/w offset 0x9_1380 (firper1), 0x9_13a0 (firper2) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field pe16 pe17 pe18 pe19 pe20 pe21 pe22 pe23 pe24 pe25 pe26 pe27 pe28 pe29 pe30 ? reset 0000_0000_0000_0000 r/w r/w offset 0x9_1382 (firper1), 0x9_13a2 (firper2) figure 41-66. fcc transmit internal rate port enable register (firper) 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 41-91 table 41-51 describes firper x fields. 41.15.4 fcc internal rate event register (firer) transmit internal rate underrun (tiru) errors are reported fo r any phy that has a tr ansmission deficiency of 8 cells. under this cond ition and in internal rate mode only, fcce[tiru] is set, and if the corresponding bit in the fcc mask register (fccm[tiru]) is set, an interrupt is generate d. if tirem = 1, the tiru status per phy can be read at any time in the fcc internal rate event register (firer). once firer[tiruy] error status is set, it can be cleared only by writing 1 to it. to prevent an underrun phy from continuously reporting errors, it can be disabled by firper. the sequence of disabling a phy is as follows: ? disable phy y by clearing firper[y] ? clear event firer[y] by writing 1 to it ? clear event fcce[tir u] by writing 1 to it table 41-51. firper x field descriptions (tirem = 1) bit name description 0?15 pey port enable 0 transmit internal rate for phy address y is disabled. txclav from this phy is masked. 1 transmit internal rate for phy address y is enabled. the rate assigned for phy y is selected by register firsr_hi (refer to section 41.15.5, ?fcc intern al rate selection registers (firsr_hi, firsr_lo)? ). 16?30 pey port enable. 0 transmit internal rate for phy address y is disabled. txclav from this phy is masked. 1 transmit internal rate for phy address y is enabled. the rate assigned for phy y is selected by register firsr_lo (refer to section 41.15.5, ?fcc intern al rate selection registers (firsr_hi, firsr_lo)? ). 31 ? reserved, should be cleared. 0123456789101112131415 field tiru 0 tiru 1 tiru 2 tiru 3 tiru 4 tiru 5 tiru 6 tiru 7 tiru 8 tiru 9 tiru 10 tiru 11 tiru 12 tiru 13 tiru 14 tiru 15 reset 0000_0000_0000_0000 r/w r/w offset 0x9_1384 (firer1), 0x9_13a4 (firer2) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field tiru 16 tiru 17 tiru 18 tiru 19 tiru 20 tiru 21 tiru 22 tiru 23 tiru 24 tiru 25 tiru 26 tiru 27 tiru 28 tiru 29 tiru 30 ? reset 0000_0000_0000_0000 r/w r/w offset 0x9_1386 (firer1), 0x9_13a6 (firer2) figure 41-67. fcc internal rate event register (firer) 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 41-92 freescale semiconductor table 41-52 describes firer x fields. 41.15.5 fcc internal rate select ion registers (firsr_hi, firsr_lo) if tirem = 1, each phy can be assigned one of four rate s, as configured by the f our fcc transmit internal rate timers. the fcc internal rate selection registers (firsr x _hi, firsr x _lo), shown in figure 41-68 and figure 41-69 , assign rate group to each of the phys. table 41-53 describes firsr x _hi fields. table 41-52. firer x field descriptions (tirem = 1) bit name description 0?30 tiruy transmit internal rate underrun 0 there is no transmission underrun for this phy. 1 transmit internal rate underrun or phy address y has o ccurred. bit is cleared by writing 1 to it. writing 0 has no effect on value. 31 ? reserved, should be cleared. 0123456789101112131415 fieldgs0gs1gs2gs3gs4gs5gs6gs7 reset 0000_0000_0000_0000 r/w r/w offset 0x9_1388 (firsr1_hi), 0x9_13a8 (firsr2_hi) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field gs8 gs9 gs10 gs11 gs12 gs13 gs14 gs15 reset 0000_0000_0000_0000 r/w r/w offset 0x9_138a (firsr1_hi), 0x9_13aa (firsr2_hi) figure 41-68. fcc internal rate selection register hi (firsr x _hi) table 41-53. irsr x _hi field descriptions (tirem = 1) bit name description 0?31 gsy group select for phy y 00 the transmit internal rate for ph y address y is controlled by ftirr x _grp0. 01 the transmit internal rate for ph y address y is controlled by ftirr x _grp1. 10 the transmit internal rate for ph y address y is controlled by ftirr x _grp2. 11 the transmit internal rate for ph y address y is controlled by ftirr x _grp3. 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 41-93 table 41-54 describes firsr x _lo fields. 41.15.6 fcc transmit internal rate register (ftirr x ) if gfemr[tirem] = 0, phys at addresses 0?3 have their own fcc transmit internal rate registers (ftirr x _phy0?ftirr x _phy3) for use in transmit internal rate mode. if tirem = 1, ftirr x are used as group timers and phys at addresses 0-30 are assigne d to a rate group by firsr x _hi and firsr x _lo. ftirr x , shown in figure 41-63 , includes the initial value of the internal rate timer. the clock to the internal rate timers is supplied by one of four baud-rate generators select ed in cmxuar; refer to section 24.4.1, ?cmx utopia a ddress register (cmxuar).? note that in slave mode, ftirr0 is used regardless of the slave phy address. 0123456789101112131415 field gs16 gs17 gs18 gs19 gs20 gs21 gs22 gs23 reset 0000_0000_0000_0000 r/w r/w offset 0x9_138c (firsr1_lo), 0x9_13ac (firsr2_lo) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field gs24 gs25 gs26 gs27 gs28 gs29 gs30 ? reset 0000_0000_0000_0000 r/w r/w offset 0x9_138e (firsr1_lo), 0x9_13ae (firsr2_lo) figure 41-69. fcc internal rate selection register lo (firsr x _lo) table 41-54. firsr x _lo field descriptions (tirem = 1) bit name description 0?29 gsy group select for phy y 00 the transmit internal rate for ph y address y is controlled by ftirr x _grp0. 01 the transmit internal rate for ph y address y is controlled by ftirr x _grp1. 10 the transmit internal rate for ph y address y is controlled by ftirr x _grp2. 11 the transmit internal rate for ph y address y is controlled by ftirr x _grp3. 30?31 ? reserved, should be cleared. 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 41-94 freescale semiconductor table 41-49 describes ftirr x fields. figure 41-64 shows how transmit clocks are determined. . figure 41-71. fcc transmit internal rate clocking 41.15.6.1 example if the MPC8555E is connected to four 155 mbps p hy devices and the maximum transmission rate is 155 mbps for the first phy and 10 mbps for the rest of the phys, the brg cl k should be set according to the highest rate. if the system clock is 133 mhz, the brg should be programme d to divide the system clock by 362 to generate cell transm it requests every 362 system clocks: 01 7 field trm initial value reset 0000_0000 r/w r/w address gfemr[tirem=0] fcc1: 0x9_131c (ftirr1_phy0), fcc1: 0x9_131d (ftirr1_phy1), fcc1: 0x9_131e (ftirr1_phy2), fcc1: 0x9_131f (ftirr1_phy3), fcc2: 0x9_133c (ftirr2_phy0), fcc2: 0x9_133d (ftirr2_phy1), fcc2: 0x9_133e (ftirr2_phy2), fcc2: 0x9_133f (ftirr2_phy3). gfemr[tirem=1] fcc1: 0x9_131c (ftirr1_grp0), fcc1: 0x9_131d (ftirr1_grp1), fcc1: 0x9_131e (ftirr1_grp2), fcc1: 0x9_131f (ftirr1_grp3), fcc2: 0x9_133c (ftirr2_grp0), fcc2: 0x9_133d (ftirr2_grp1), fcc2: 0x9_133e (ftirr2_grp2), fcc2: 0x9_133f (ftirr2_grp3). figure 41-70. fcc transmit internal rate register (ftirr) table 41-55. ftirr x field descriptions bits name description 0trm (tirem = 0) phy transmit mode 0 external rate mode 1 internal rate mode trm (tirem = 1) group transmit mode 0 group rate timer [x] disabled 1 internal rate timer for group[x] is enabled a nd division factor is set by initial value field. 1?7 initial value the initial value of the internal rate timer. a value of 0x7f produces the minimum clock rate (brg clk divided by 128); 0x00 produces the maximum clock rate (brg clk divided by 1). brg clk phy#0 int rate timer phy#1 int rate timer phy#2 int rate timer phy#3 int rate timer phy#0 or grp#0 tx rate phy#1 or grp#1tx rate phy#2 or grp#2 tx rate phy#3 or grp#3 tx rate 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 41-95 for the 155 mbps phy, the ftirr divider should be programmed to zero (the brg clk is divided by one); for the rest of the 10 mbps phys, the ftirr divider should be programmed to 14 (the brg clk is divided by 15). 41.15.7 internal rate programming model the programming sequence in tire m = 0 mode is as follows: 1. clear gfemrx[tirem] 2. program ftirrx the programming sequence in tire m = 1 mode is as follows: 1. clear ftirrx[trm] 2. set gfemrx[tirem] 3. program firsrx_hi and firsrx_lo 4. program ftirrx 5. program firperx if ftirrx are set to generate sa me order of magnitude rates, set ting round robin polling mode is more adequate than fixed priority mode. to reduce the risk of transmit underrun if th ere are a few phys with high internal rate and a number of phys with a lo w internal rate, the fast phys should be assigned consecutive addresses starting at 0 and fixed priority mode should be chosen. 41.16 configuring the atm controll er for maximum cpm performance the following sections recomme nd atm controller configurations to maximize cpm performance. 41.16.1 using transmit internal rate mode when the total transmit rate is less than the phy rate, use the transmit internal rate mode and configure the internal rate clock to th e maximum bit ra te required. (see 41.2.1.5, ?transmit external rate and internal rate modes.? ) the phy then automatically fills the u nused bandwidth with idle cells, not the atm controller. if the internal rate mode is not us ed, cpm performance is consumed generating the idle cell payload and using the scheduling algorithm to fill the unused bandwidth at the higher phy rate. for example, suppose a system uses a 155.52-mbps oc-3 device as phy 0, but the maximum required data rate is only 100 mbps. in tr ansmit internal rate mode, the user can configure the intern al rate mechanism to clock the atm transmitter at a cell rate of 100 mbps. if the syst em clock is 133 mhz, program a brg to divide the system clock by 563 to generate a transmit cell request every 563 cpm clocks: 133mhz 53 8 () () 155.52mbps ----------------------------------------------------- 362 = 133mhz 53 8 () () 100mbps ----------------------------------------------------- 563 = 4 datasheet u .com
atm controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 41-96 freescale semiconductor set ftirr x _phy0[trm] to enable the transmit in ternal rate mode and clear ftirr x _phy0[initial value] since there is no need to further divide the brg. see section 41.13.5, ?fcc transmit internal rate registers (ftirrx).? in external rate mode, however, th e transmit cell request frequency is determined by the phy?s maximum rate, not by internal fcc count ers. if an oc-3 phy is used with the atm controller in external rate mode, the requests must be generated every 362 cpm cl ocks (assuming a 133-mhz cpm clock). if only 100 mbps is used for real data, 36% of the transmit cell requests consume cpm processing time sending idle cells. 41.16.2 apc configuration maximizing the number of cells per sl ot (cps) and minimizing the priority levels defined in the apc data structure improves cpm performance: ? cells per slot. cps defines the maximum number of atm cells allowed to be sent during a time slot. (see section 41.3.3.1, ?determining the cells per slot (cps) in a scheduling table.? ) the scheduling algorithm is more effi cient sending multiple cells per ti me slot using the linked-channel field. therefore, choose the maximum number of cells per slot allo wed by the application. ? priority levels. the user can configure the apc data structure to have from one to eight priority levels. (see section 41.3.6, ?determining the prio rity of an atm channel.? ) for each time slot, the scheduling algorithm scans all priority levels and maintains pointers for each level. therefore, enable only the minimum number of priority levels required. 41.16.3 buffer configuration using statically allocated buffers of opt imal sizes also improves cpm performance: ? buffer size. opening and closing buffer descri ptors consumes cpm processing time. because smaller buffers require more opening and closing of bds, the optimal buf fer size for maximum cpm performance is equal to the pack et size (an aal5 frame, for example). ? free buffer pool. when the free buffer pool is used, the cpm dyna mically allocates buffers and links them to a channel?s bd. in static buffer allocation, the core a ssigns a fixed data buffer to each bd. (see section 41.10.5.2, ?receive buffer operation.? ) when allowed by the application, use static buffer allocation to increase cpm performance. 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 42-1 chapter 42 atm aal2 the microcode implementation of the atm adapta tion layer type 2 (aal2) on the MPC8555E is compliant with the itu-t recomme ndations i.363.2 and i.366.1. this chap ter describes the functionality and data structures of aal2 cps, cps switchi ng, and sssar and should be used as a supplement to chapter 41, ?atm controller.? 42.1 introduction aal2 enables the multiplexing of voice and data cha nnels over a single atm vc. the channels consist of packets transported within individual atm cells (see figure 42-1 ). packet lengths are allowed to vary in order to accommodate bandwidth fluctuations of the individual channels. ea ch packet has a channel identifier (cid) so that each aal2 user (channel) is uniquely identifi ed by the triplet vp | vc | cid. figure 42-1. aal2 data units aal2 is subdivided into two sublayers, as shown in figure 42-2 : ? common part sublayer (cps)?in the cps sublayer , variable length packets coming from multiple users are assembled into cps-p dus belonging to a single atm vc. ? service-specific convergence s ublayer (sscs)?the sscs sublayer handles the mapping of user data to the cps sublayer. the sscs segments large data frames into smaller cps packets and also provides different services to the user, such as transmission error detect ion. the sscs sublayer is further divided into thr ee service-specific layers: ? service-specific segmentation a nd reassembly sublayer (sssar) ? service-specific transmission er ror detection sublayer (ssted) ? service-specific assured data transfer sublayer (ssadt) atm header stf at m c e l l ph pp ph pp padding stf cps pdu ph pp ph pp padding ph pp ph pp sssar sdu sssar cps at m sssar pdu 4 datasheet u .com
atm aal2 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 42-2 freescale semiconductor figure 42-2. aal2 sublayer structure the aal2 microcode implements th e cps and sssar sublayers. (the ssadt and ssted sublayers are not implemented.) as shown in figure 42-2 , the user can access the cps subl ayer directly or through the sssar sublayer. the sssar sublayer is used ma inly for transferring large data frames. the aal2 microcode also enables swit ching from one phy | vp | vc | cid combination to another; an example is shown in figure 42-3 . figure 42-3. aal2 switching example 42.2 features the MPC8555E aal2 features are as follows: ? fully complies with itu-t i.363.2 (09/97 and 11/00) and itu-t i.366.1 (06/98) specifications ? number of aal2 external channels supported is subject to internal memory constraints ? each external channel requires space for one tran smit queue descriptor in internal memory. typically, up to 1000 external channels can be supported. common part sublayer service specific segm entation and reassembly service specific transmission error detection service specific assured data transfer sap sap sap sap user user user sscs cps aal2 ssted sssar ssadt user (sap): service access point cps x vp = 5 | vc = 20 | cid = 13 vp = 27 | vc = 3 | cid = 212 utopia phy4 utopia phy7 4 datasheet u .com
atm aal2 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 42-3 ? supports cbr, vbr, and ubr+ traffic types ? pcr pacing (with optional timer_cu) ? vbr pacing (with optional timer_cu) ? ubr + pacing (no timer_cu support) ? priority mechanism for transmitting per vc. th e priority mechanism provides for tx queues having equal or differing priori ties. the sssar tx queues can be prioritized flexibly among the cps tx queues. ? timer_cu support ? nostf mode support ? support for partially filled cells ? user-defined cells (as described in section 41.7, ?user-defined cells (udc)? ). ? interrupt indications include the atm channel num ber, the cid, and the event type. the events reported are tx buffer not ready, tx buffer tran smitted, rx buffer not ready, rx buffer, rx sssar frame, and rx aal2 error events. ? cps switching ? switching from a receive phy 1 | vp 1 | vc 1 | cid 1 combination to another transmit phy 2 | vp 2 | vc 2 | cid 2 combination ? partial packet discard support ? for each switched queue, a counter for the tota l number of packets in the queue is available. ? cps receiver ? segmentation of cps pdu direct ly to external memory queues ? a separate queue for every vp | vc | cid or a common queue for multiple vp | vc | cid combinations ? receive one or multiple vp | vc | cids directly to a specific tx queue to enable switching ? sequence number (sn) protection check for cps-pdu ? crc5 (hec) check to detect errors in the cps-ph of the cps-packet ? osf (offset field) of the stf (start of fr ame) check (a valid value is less than 48) ? an sdu length limit parameter (m ax_sdu_deliver_length) per atm vc ? odd parity check for the stf octet of the cps-pdu ? cps transmitter ? reassemble cps pdu directly from external memory ? perform cps-pdu padding as needed ? insert sequence number bit of the cps-pdu ? parity bit is calculated to pr ovide odd parity over the stf octet ? calculation of crc-5 on the first 19 bits of the cps-ph ? uui field in the cps-packet header is progr ammed according to the value of the cps_uui parameter (per packet) ? a free running counter (per tx queue) is decremented for each packet sent. 4 datasheet u .com
atm aal2 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 42-4 freescale semiconductor ? sssar receiver ? reassemble cps packets from the same cid into an sssar sdu ? a separate queue for every phy | vp | vc | cid ? perform all the above ment ioned cps receiver functions ? a ras_timer mode is provided. when the ras_ti mer expires the buffer is closed with a timer expired error. the next packet received starts a new sssar sdu in a new buffer. ? the sdu length is checked. if the frame exceeds the length limit (sssar_max_sdu_length), the rece iver discards the rest of the packets from the current frame, closes the buffer and reports a max_sdu violation error in the bd. the next packet received starts a new sssar sdu in a new buffer. ? partial packet discard. if no buf fer is available when a packet arrives, the receiver enters a frame hunt state and discards each in coming packet from the current frame. ? the uui field is stored for the host into the rxbd after receiving the whole sssar frame. ? sssar transmitter ? segmentation of sssar sdus from sssar tx queue into cps packets ? an sssar tx queue may contain several cids ? performs all the above menti oned cps transmitter functions ? a programmable segment length (seg_len) is copied from the sssar sdu into the cps packet payload, except for when at the end of the frame or buffer. ? uui mode available. when uui mode is en abled, the sssar uui is copied from the byte following the last byte of the frame. 42.3 aal2 transmitter the following sections desc ribe the aal2 transmitter. 42.3.1 transmitter overview a transmitter cycle starts when the apc schedules an atm channel number for transmission. the tct is fetched and the aal type of the channel is checked . for aal2 cells, the transmitter first handles uncompleted packets from the previous cell of the current cid (partial and split cases) by filling the beginning of the cell with the remainder of the last packet. then, the transmitter performs the priority mechanism (see section 42.3.2, ?transmit priority mechanism,? ) in order to fill the cell with new packets. the priority mechanism determines the order in which the tx queues are serviced. the transmitter continues to search for ready packets in the tx queues until either the cell is successfully filled with pa ckets, or no more packets are ready but the cell is not yet completed. in the first case the cell is simply sent. in the latter case, the optiona l timer_cu (described in section 42.3.5.1, ?aal2 protocol-specific tct,? ) is examined. if the t imer_cu has expired, the uncompleted cell is padded with zeros and sent; otherwise, the cell is temporarily stored in external memory for the cp to attempt to complete it the next time the channel is scheduled. 4 datasheet u .com
atm aal2 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 42-5 the tx queues are the data structur es that store the cps packets and sssar frames. each tx queue can contain different cids. each tx queue is maintained by a tx queue descriptor (txqd) that holds the queue pointer and paramete rs to manage the queue. when the transmitter fetches a packet out of an sssar tx queue, it usually takes out of the sssar buffer a number of octets equa l to txqd[seg_len]. (see section 42.3.5.4, ?sssar tx queue descriptor.? ) the channel cid is taken from the bd of the first buffer of the sssar frame. (see section 42.3.5.5, ?sssar transmit buffer descriptor.? ) a cps uui = 27 is used for all the in-frame packets until the last packet from the sssar frame is se nt. the last packet can optionally contai n a per frame, user-defined uui. after an sssar buffer is completely sent, an optional interr upt event is issued to the host. also, if an sssar tx queue is empty an optional interrupt event is issued to the host. in case of cps tx queue, the transmitter fetches th e packet header out of a buffer descriptor and the packet payload out of a cps buffer. (see section 42.3.5.3, ?cps buffer structure.? ) the hec in the packet header is calculated by the cp or taken from the buffer descriptor based on the user c onfiguration. after a cps packet is sent, an optional inte rrupt event is issued to the host. also, if the cps tx queue is empty an optional interrupt event is issued to the host. the optional partial filled mode (see section 42.3.3, ?partial fill mode (pfm),? ) limits the number of data octets per cell. this can be used to ensure that a cell does not contain a split packet or to limit transmission to one packet per tx cell by setting a low partial fill threshold (pft). the no-stf (no start of frame) mode (see section 42.3.4, ?no stf mode,? ) enables the transmission of cells that do not include the stf byte, thus allowing for 48-byte packets. 42.3.2 transmit priority mechanism the transmit priority mechanism operates in two modes: ? round robin (tct[fix] = 0) ? fixed priority (tct[fix] = 1) the following sections describe the priority options. 42.3.2.1 round robin priority in round robin priority mode, the tx queues all have equal priority. the transmitter starts with the txqd pointed to by tct[firstq ueue], as shown in figure 42-4 . the number of packets that the transmitter services from each queue is determined by the one-packet bit (tct[onep]). if tct[onep] = 0, the transmitter tries to process as many pa ckets in the queue as needed to fill up the cell. only when the queue is empty does the transmitter move on to the next queue (assuming the cell is not completed). if tct[onep] = 1, the transmitter attempts to take onl y one packet out of each queue. (set tct[onep] for implementations where each que ue contains only one cid.) 4 datasheet u .com
atm aal2 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 42-6 freescale semiconductor figure 42-4. round robin priority the transmitter steps from one txqd to the next along the queue links. the tct[maxstep] parameter limits the number of tx queues that the transmitter visits during a cell time. if maxs tep is reached before the cell has been complete ly filled, one of the fo llowing events takes place: ? tct[et] = 0 (timer cu disabled). th e cell is padded with zeros and sent. ? tct[et] = 1 (timer cu enabled). if the timer has not expired, the cell is not sent. (the transmitter attempts to fill the cell the next time this channel is scheduled.) if the time r has expired, the cell is padded with zeros and sent after the transmitter sends a cell, it saves the queue link of the last txqd serviced in tct[firstqueue]. 42.3.2.2 fixed priority in fixed priority mode (tct[fix] = 1), the transmitter, with each new cell , starts with searching the highest priority queue and then m oves on to the lower priority queues. th e tct[firstqueue] poi nts to the highest priority queue, as shown in figure 42-5 , and remains unchanged by the cp. firstqueue tct nextqueue txqd nextqueue txqd nextqueue txqd fix = 0 4 datasheet u .com
atm aal2 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 42-7 figure 42-5. fixed priority mode the tct[onep] determines the number of packets that the transmitter attempts to take from each queue (see the explanation in round robin mode). the nextqueue field of the lowest priority txqd should be cleared ( null link), and tct[ maxstep] should be programmed to the total number of tx queues in the channel. when the transmitter reaches the null link and the cell is still not complete, the transmitte r checks the timer cu mode as described above for the round robin mode. 42.3.3 partial fill mode (pfm) the partial fill mode (tct[pfm] = 1) allows the user to specify a part ial fill threshold (tct[pft]), which limits the number of data octets sent with each atm ce ll. partial fill mode assure s that packets are not split over two cells, unless the first packet of the cell is gr eater than 47 bytes. in partial fill mode, the transmitter starts by filling the atm cell with the first packet. after the first packet, the cp determines if incl uding the next packet in the cell woul d exceed the pft lim it. if so, the second packet is not inserted into the curr ent cell, the unused payload is padded with zeros, and th e cell is sent. if the second packet does not exceed pft, the cp insert s it into the cps-pdu and moves on to the third packet, and so on. by programming pft = 1, the partial fill mode can also serve to assure that only one packet is sent per cell. firstqueue tct nextqueue txqd nextqueue txqd 0x0000 (null link) txqd fix = 1 highest priority queue lowest priority queue 4 datasheet u .com
atm aal2 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 42-8 freescale semiconductor the following figures provide exampl es of partial f ill mode operation: 42.3.4 no stf mode the no-stf (no start of frame) m ode enables the transmission of 48- byte packets by not including the stf byte in the cps pdu. the no-stf m ode should always be used with pft programmed to 47 in order to prevent split and partial packets. fo r the aal2 channels that use this mode, packets must not be larger than a maximum packet size of 48. the user activates this mode pe r atm channel by doing the following: 1. setting tct[nostf] = 1 and tct[pfm] = 1 2. establishing a partial fill thre shold by programming tct[pft] = 47 figure 42-6 shows a cell using no-stf mode: figure 42-6. cell in no-stf mode cell stf aal2 aal2 aal2 aal2 packet 2 packet 3 packet 4 packet 5 padding header aal2 packet 1 tr a n s m i t 1. five packets fit exactly within the pft limit cell stf aal2 aal2 packet 2 packet 3 empty header aal2 packet 1 pft 0 pft cell stf aal2 packet 2 padding header aal2 packet 1 tr a n s m i t pft 2. because pft is less than the combined lengths of packet 1, packet 2 and packet 3, the atm cell is sent only with packets 1 and 2. (packet 3 will be sent with the next cell.) 0 0 remove packet 3 cell stf padding header aal2 packet 1 pft 3. because the first packet exceeds the pft value, the cps-pdu consists only of this packet (and the unused octets are padded with zeros). 0 tr a n s m i t cell aal2 packet of 48 bytes header 0 4 datasheet u .com
atm aal2 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 42-9 42.3.5 aal2 tx data structures the following sections describe th e transmit connection tables (tct) and the structures in which cps packets and sssar sdus are stored in memory. 42.3.5.1 aal2 protocol-specific tct the transmit connection tabl e (tct) is a vc-level ta ble and is where the aal type for the atm channel number is selected. the parameters related to the at m channel number or to all the tx queues of the atm channel are maintained here. figure 42-7 shows the aal2-specific tct. note when the channel is active, the cp fetches the tct (32 bytes) using burst cycle and writes back only the first (24 bytes). 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 offset + 0x00 ? gbl bo ? dtb bib avcf pfm att et vcon intq offset + 0x02 ? nostf aal offset + 0x04 ? offset + 0x06 offset + 0x08 ? offset + 0x0a firstqueue offset + 0x0c rate remainder pcr fraction offset + 0x0e pcr offset + 0x10 timer_cu_period offset + 0x12 timer_period_shadow offset + 0x14 ? offset + 0x16 apc linked channel offset + 0x18 atm cell header (vpi,vci,pti,clp) offset + 0x1a offset + 0x1c ? pmt maxstep offset + 0x1e ? pft ? onep stpt fix pm figure 42-7. aal2 protocol-specifi c transmit connection table (tct) 4 datasheet u .com
atm aal2 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 42-10 freescale semiconductor table 42-1 describes the aal2 tct fields. table 42-1. aal2 protocol-specific tr ansmit connection table (tct) field descriptions offset bits name 1 description 0x00 0?1 ? reserved, should be cleared during initialization. 2 gbl global. setting gbl enables snooping of data buffers, bd, interrupt queues and free buffer pool. 3?4 bo byte ordering. this field is used for data buffers. 00 reserved 01 power pc little endian 1x big endian 5 ? reserved, should be cleared during initialization. 6 dtb data buffer bus selection. 0 data buffers reside on the system bus. 1 reserved. 7 bib bus selection for the bds, interrupt queues and the free buffer pool. 0 reside on the system bus. 1 reserved. 8 avcf auto vc off. determines apc behavior when the last buffer associated with this vc has been sent and no more buffers are in the vc?s txbd table, 0 the apc does not remove this vc from the schedule table and continues to schedule it to transmit. 1 the apc removes this vc from the sc hedule table. to continue transmission after the host adds buffers for transmission, a new atm transmit command is needed, which can be issued only after the cp clears the vcon bit. (bit 13) 9 pfm partial fill mode. see section 42.3.3, ?parti al fill mode (pfm).? 0 partially filled cells are not supported. 1 partially filled cells are supported. 10?11 att atm traffic type 00 peak cell-rate pacing (regular traffic). the host must initialize pcr and pcr fraction. other traffic parameters are not used. 01 peak and sustain cell rate pacing (vbr traffic). the apc performs a continuous-state leaky bucket algorithm (gcra) to pace t he channel-sustain cell rate. the host must initialize p cr, pcr fraction, scr, scr fraction, and bt (burst tolerance). 10 peak and minimum cell rate pacing. the host must initialize pcr, pcr fraction, mcr, mcr fraction, and mda. 11 reserved. 12 et enable timer_cu. 0 timer_cu operation in this channel is disabled. 1 timer_cu operation in this channel is enabled. 13 vcon virtual channel is on should be set by the host before it issues an atm transmit command. when the host sets the stpt (stop transmit) bit, th e cp deactivates this channel and clears vcon. the host can issue another atm transmit command only when the cp clears vcon. 14?15 intq points to one of the four interrupt queues available. 4 datasheet u .com
atm aal2 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 42-11 0x02 0?11 ? reserved, should be cleared during initialization. 12 nostf no stf byte. see section 42.3.4, ?no stf mode.? 0 normal aal2 cell structure 1 the cell does not include the stf byte. in this mode each cell starts with a new packet and contains only whole packets (no split or partial). 13?15 aal aal type 000 aal0?segmentation with no adaptation layer 001 aal1?atm adaptation layer 1 protocol 010 aal5?atm adaptation layer 5 protocol 100 aal2?atm adaptation layer 2 protocol 101 aal1_ces. all others reserved. 0x04 ? ? reserved, should be cleared during initialization. 0x06 ? ? reserved, should be cleared during initialization. 0x08 ? ? reserved, should be cleared during initialization. 0x0a ? firstqueue points to the first queue to be serviced in the transmitter cycle. in round-robin priority mode (tct[fix] = 0), this pointer could point to any one of the txqds related to this channel. in fixed priority mode (tct[fix] = 1), this pointer should point to the highest priority txqd. 0x0c 0?7 rate remainder rate remainder. used by the apc to hold the rate remainder after adding the pace fraction to the additive channel rate. should be cleared during initialization by the user. 8?15 pcr fraction peak cell rate fraction. holds the peak cell rate fraction of this channel in units of 1/256 slot. if this is an abr channel, this field is automatically updated by the cp. 0x0e ? pcr peak cell rate. holds the peak cell rate (in units of apc slots) permitted for this channel according to the traffic contract. note that for an abr channel, the cp automatically updates pcr to the acr value. 0x10 ? timer_cu_period timer_cu duration in units of apc slots. assures that cps-packet already packed in a cell wait at most the timer_cu duration. the user defines this field. 0x12 ? timer_period_shadow this field must be initialized to the timer_cu period in units of apc slots. 0x14 ? ? reserved, should be cleared during initialization. 0x16 ? apclc apc linked channel. used by the cp. should be cleared during initialization. 0x18 ? atmch atm cell header. holds the full (4-byte) atm cell header of the current channel. the transmitter appends atmch to the cell payload during transmission. 0x1c 0?1 ? reserved, should be cleared during initialization. 2?7 pmt performance monitoring table. points to one of the available 64 performance monitoring tables. the starting a ddress of the table is pmt_base+pmt 32. 8?15 maxstep holds the number of tx queues visited for each cell being prepared for transmission. in fixed priority mode (tct[f ix] = 1), maxstep should be set to the total number of tx queues in the channel. see section 42.3.2, ?transmit priority mechanism.? table 42-1. aal2 protocol-specific tr ansmit connection table (tct) field descriptions (continued) offset bits name 1 description 4 datasheet u .com
atm aal2 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 42-12 freescale semiconductor 42.3.5.2 cps tx queue descriptor each cps txbd table is managed by a cps tx queue descriptor (txqd), as shown in figure 42-8 . the txqd contains the address of the next bd to be serviced, and other queue -specific parameters. the nextqueue pointer is used to create a linked list of txqds, as described in section 42.3.2, ?transmit priority mechanism.? the cps txqd is located in the dual- port ram, in a 16-byte aligned address. 0x1e 0?1 ? reserved, should be cleared during initialization. 2?7 pft partial fill threshold. used for partially filled cells only; see section 42.3.3, ?partial fill mode (pfm).? specifies the maximum number of packet bytes allowed in a cps pdu. the range 1?48 are valid values. if pft = 48 in partial fill mode, performance is adversely affected. when not in partial fill mode, pft must be initialized to 47. 8?11 ? reserved, should be cleared during initialization. 12 onep one packet per queue. see section 42.3.2, ?transmit priority mechanism.? 0 the transmitter reads as many packets as possible from each tx queue before moving to the next queue. 1 the transmitter reads only one packet from each tx queue before advancing to the next queue. 13 stpt stop transmit. should be cleared during init ialization. when the host sets this bit, the cp removes this channel from the apc and clears tct[vcon] flag. 14 fix fixed priority. see section 42.3.2, ?transmit priority mechanism.? 0 round robin priority. the tx queues related to this channel all share the same priority. 1 fixed priority. the tx queues are ordered in a fixed priority ladder. 15 pm performance monitoring 0 no performance monitoring for this vc 1 performance is monitored for this vc. when a cell is sent for this vc, the performance monitoring table indicated in pmt field is updated. 1 boldfaced entries must be initialized by the user. table 42-1. aal2 protocol-specific tr ansmit connection table (tct) field descriptions (continued) offset bits name 1 description 4 datasheet u .com
atm aal2 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 42-13 table 42-2 describes the cps txqd fields. . 0 7 8 9 10 11 12 13 15 offset + 0x00 ? bnm sw hec cps tbm ? offset + 0x02 txbd table offset in (switched mode only) offset + 0x04 txbd table base offset + 0x06 offset + 0x08 txbd table offset out offset + 0x0a number of packets in queue offset + 0x0c nextqueue offset + 0x0e ? figure 42-8. cps tx queue descriptor (txqd) table 42-2. cps txqd field descriptions offset bits name 1 description 0x00 0?7 ? reserved for internal use. (used to save the bd status of the open bd.) 8 bnm buffer not-ready interrupt mask of the txbd table. 0 the transmit buffer-not-ready event for this qu eue is masked. (the event is not sent to the interrupt queue.) 1 the buffer-not-ready event for this queue is enabled. 9 sw switching queue. 0 normal tx queue 1 this txqd handles a switching queue. the receiver and transmitter share this queue. 10 hec hec calculation. 0 transmitter calculates the cps header hec. 1 the cps header hec is taken as is from the cps buffer descriptor. 11 cps sublayer type. for a cps txqd, this field must be set. 0 sssar or ssted. 1 cps packet. 12 tbm transmit buffer interrupt mask. 0 the transmit buffer event of this queue is ma sked. (the event is not sent to the interrupt queue). 1 the transmit buffer event of this queue is enabled. 13?15 ? reserved, should be cleared during initialization. 0x02 ? txbd table offset in used only when this queue is used for s witching (sw=1). should be cleared during initialization. 0x04 ? txbd table base this pointer points to the base address of the bd table. 0x08 ? txbd table offset out holds the offset from the txbd table base to the next bd to be opened by the transmitter. should be cleared during initialization. 4 datasheet u .com
atm aal2 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 42-14 freescale semiconductor 42.3.5.3 cps buffer structure the cps buffer structure consists of a bd table that points to data buffers. the bds contain, apart from the buffer pointer, also the packet header. the buffers contain the packet payload. see figure 42-9 . figure 42-9. buffer structure example for cps packets 0x0a ? number of packets in queue counts the number of packets currently in the queue. if this queue is switched, the receiver increments this counter with each new received packet and the transmitter decrements it with each packet sent. for switching, the user should initialize this counter to zero. when this queue is not switched, this counter counts down with every packet sent. (this can have various purposes such as evaluating the packet rate that is transmitted from this queue.). 0x0c ? nextqueue points to the next txqd to be serviced after this one. see section 42.3.2, ?transmit priority mechanism.? 0x0e ? ? reserved, should be cleared during initialization. 1 boldfaced entries must be initialized by the user. table 42-2. cps txqd field descriptions (continued) offset bits name 1 description bd memory space txbd_table_base txbd table of ch 1 txbd table of ch 4 txbd_table_offset_out pointers txbd 1 txbd 2 txbd 3 txbd 4 txbd 5 txbd 6 txbd 7 txbd 8 txbd 9 txbd 1 txbd 2 txbd 3 txbd 4 txbd 5 txbd 6 tx buffer 3 of channel 1 tx buffer 4 of channel 1 tx buffer 1 of channel 4 tx buffer 2 of channel 4 tx buffer 3 of channel 4 tx buffer 2 of channel 1 tx buffer 8 of channel 4 ? ? ? ? ? ? tx buffer 1 of channel 1 data memory space from cps txqd pointers from another cps txqd txbd_table_base txbd_table_offset_out 4 datasheet u .com
atm aal2 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 42-15 figure 42-10 shows a cps txbd. table 42-3 describes the cps txbd fields. . 0 1 2 3 4 7 8 15 offset + 0x00 r cm w i ? cps packet header offset + 0x02 cps packet header offset + 0x04 tx data buffer pointer (txdbptr) offset + 0x06 figure 42-10. cps txbd table 42-3. cps txbd field descriptions offset bits name 1 1 boldfaced entries must be initialized by the user. description 0x00 0 r ready 0 the buffer associated with this bd is not ready for transmission. the user is free to manipulate this bd or its associated buffer. the cp clears r after the buff er is sent or after an error condition is encountered. 1 the user-prepared buffer has not been sent or is currently being sent. no fields of this bd may be written by the user once r is set. 1 cm 2 2 setting continuous mode (txbd[cm] = 1) is not allowed in cid switching mode. continuous mode 0 normal operation. 1 the cp does not clear r after this bd is closed, allowing the associated buffer to be retransmitted automatically when the cp next accesses this bd. however, the r bit is cleared if an error occurs during transm ission, regardless of the cm bit setting. 2 w wrap (final bd in table) 0 this is not the last bd in the txbd table. 1 this is the last bd in the txbd table. afte r this buffer is used, the cp transmits outgoing data for this channel from the first bd in t he table (the bd pointed to by the channel?s txbd_table_base in the txqd). the number of txbds in this table is determined only by the w bit. 3 i interrupt 0 no interrupt is generated after this buffer has been serviced. 1 a tx buffer event is sent to the interrupt queue after this buffer is serviced. the ghin/glin bit in the event register is set when th e int_cnt counter reaches terminal count. 4?7 ? reserved, should be cleared during initialization. 8?15 cps packet header this field contains the beginning (msb) of the 3-byte packet header. see figure 42-11 for the cps packet header format. 0x02 ? cps packet header this field contains the rest of the packet header . if txqd[hec] = 0, the hec part of the packet header is calculated by the cp, and the user may di sregard the five least-significant bits of this field. see figure 42-11 for the cps packet header format. 0x04 ? txdbptr tx data buffer pointer. points to the address of the associated buffer. there are no byte-alignment requirements for the buffer, and it may reside in either internal or external memory. this pointer is not modified by the cp. 4 datasheet u .com
atm aal2 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 42-16 freescale semiconductor 42.3.5.4 sssar tx queue descriptor a sssar txbd table and its associated buffers ar e collectively called an sssar tx queue. each sssar tx queue is managed by an sssar txqd, as shown in figure 42-12 . the txqd contains the base address of the bd table, the offset of the next bd to be serviced, the data buffer pointer, and other queue-specific parameters. the nextqu eue pointer is used to create a li nked list of txqds, as described in section 42.3.2, ?transmit pr iority mechanism.? the sssar txqd is located in the dual-port ram in a 32-byte aligned address. 0781314181923 channel identifier (cid) length indicator (li) us er-to-user id (uui) header error check (hec) figure 42-11. cps packet header format 0 7 8 9 10 11 12 13 14 15 offset + 0x00 ? bnm uui inf cps tbm sssar ? offset + 0x02 seg_len ? offset + 0x04 txbd table base offset + 0x06 offset + 0x08 txbd table offset out offset + 0x0a ? offset + 0x0c nextqueue offset + 0x0e ? offset + 0x10 offset + 0x12 offset + 0x14 offset + 0x16 offset + 0x18 offset + 0x1a offset + 0x1c offset + 0x1e figure 42-12. sssar tx queue descriptor 4 datasheet u .com
atm aal2 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 42-17 table 42-4 describes the sssar txqd fields. . table 42-4. sssar txqd field descriptions offset bits name 1 1 boldfaced entries must be initialized by the user. description 0x00 0?7 ? reserved, should be cleared during initialization. 8 bnm buffer-not-ready interrupt mask of the txbd table. 0 the transmit buffer-not-ready event for this queue is masked. (the event is not sent to the interrupt queue.) 1 the buffer-not-ready event for this queue is enabled. 9 uui uui insertion mode 0 uui of last cps packet is 0. 1 uui of last cps packet is taken from the next byte after the end of the buffer. 2 2 the 5-bit uui fi eld is inserted into the header of th e last packet of an sssar sdu. the us er must append the uui to the last buffer as an additional byte. this additional byte is then insert ed into the uui field of the last packet header (note that, it is important that this additional byte?the byte after the last byte in the last data buffer of the sssar frame?contains the 5 bits of the uui). the 3 msb bits of this extra byte should be cleared; refer to figure 42-11 . 10 inf indicates the current state of the frame. 0 the next packet will be the first of a new frame. 1 currently in the middle of the frame. 11 cps sublayer type. for an sssar txqd, this field must be cleared. 0 sssar or ssted. 1 cps packet. 12 tbm transmit buffer interrupt mask for txbd table. 0 the transmit buffer event of this queue is masked. (the event is not sent to the interrupt queue.) 1 the transmit buffer event of this queue is enabled. 13 sssar sssar bit 0 ssted sublayer 1 sssar sublayer 14?15 ? reserved, should be cleared during initialization. 0x02 0?7 seg_len specifies the maximum length in bytes of the sssar pdu (excluding the packet header). seg_len is limited to 45 in nostf=1 mode. the cp always attempts to segment the sssar sdu according to th is length, but not more than it. 8?15 ? reserved, should be cleared during initialization. 0x04 ? txbd table base must be initialized to the first txbd by the user. 0x08 ? txbd table offset out used to calculate the poin ter to the next txbd to be used for transmission. should be cleared during initialization. 0x0a ? ? reserved, should be cleared during initialization. 0x0c ? nextqueue points to the next txqd to be serviced after this one. see section section 42.3.2, ?transmit priority mechanism.? 0x0e? 0x1e ? ? reserved, should be cleared during initialization. 4 datasheet u .com
atm aal2 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 42-18 freescale semiconductor 42.3.5.5 sssar transmit buffer descriptor the sssar buffer structure consists of a bd table th at points to data buffers. the buffers may contain sssar sdus belonging to different cids. each buffer may contain a whole sssa r sdu or part of it. the cps cid is located in the first bd of the sssar sdu. see figure 42-13 . . 012345 78 15 offset + 0x00 rcmw i l ? cid offset + 0x02 data length (dl ) offset + 0x04 tx data buffer pointer (txdbptr) offset + 0x06 figure 42-13. sssar txbd table 42-5. sssar txbd field descriptions offset bits name 1 description 0x00 0 r ready 0 the buffer associated with this bd is not ready for transmission. the user is free to manipulate this bd or its associated buffer. the cp clears r after the buff er is sent or after an error condition is encountered. 1 the user-prepared buffer has not been sent or is currently being sent. no fields of this bd may be written by the user once r is set. 1 cm continuous mode 0 normal operation 1 the cp does not clear r after this bd is closed, allowing the associated buffer to be retransmitted automatically when the cp next accesses this bd. however, the r bit is cleared if an error occurs during transm ission, regardless of the cm bit setting. 2 w wrap (final bd in table) 0 this is not the last bd in the txbd table. 1 this is the last bd in the txbd table. afte r this buffer is used, the cp transmits outgoing data for this channel from the first bd in t he table (the bd pointed to by the channel?s txbd_table_base in the txqd). the number of txbds in this table is determined only by the w bit. 3 i interrupt 0 no interrupt is generated after this buffer has been serviced. 1 a tx buffer event is sent to the interrupt queue after this buffer is serviced. the ghin/glin bit in the event register is set when th e int_cnt counter reaches terminal count. 4 l last 0 this is not the last buffer of the sssar sdu. 1 this is the last buffer of the sssar sdu. 5?7 ? reserved, should be cleared during initialization. 8?15 cid contains the cid number of the sssar sdu poin ted by this bd. this field should be written to the first bd of an sssar sdu. 4 datasheet u .com
atm aal2 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 42-19 42.4 aal2 receiver the following sections de scribe the aal2 receiver. 42.4.1 receiver overview the receiver cycle starts after the f cc receives a cell. if th e cell header is successf ully mapped to an atm channel number, the corresponding rct is fetched and th e aal type is read. for aal2 cells, the receiver begins by checking if the la st cell received in this ch annel (cid) has an uncomplet ed (split) packet. if so, the receiver first finishes handling this packet. the receiver then goes thro ugh a validation process. the receiver matches the os f field in the stf with the expected osf based on the actual sp lit packet (if the first packet is not split, th e osf should be zero). if the two values do not match, an o sf error interrupt is issued and the re ceiver drops the last packet. also, if the stf parity check, the sn check or the osf>47 ch eck results in an error, the receiver issues an interrupt and discards the whole cell. if any of the above errors has occurred and the cell has started with the remainder of an uncompleted p acket, the receiver does the following: ? for a cps sublayer cid, the packet?s rx bd[up] (uncompleted packet) bit is set. ? for an sssar sublayer cid, the buffer is cl osed with rxbd[rxerror = us = 10] (uncompleted sdu), and the rest of the frame is dropped. the receiver now begins the process of extracting new cps p ackets out of the cell with another round of error checking. the receiver ex amines each cps packet header for the following errors: ? incorrect packet hec. the packet and rest of the cell are discarded. ? packet length (li+1) is larger than cps_max_s du_length. the receiver di scards the packet and then continues to extract the next packet in the cell. however, if the packet belongs to an sssar cid, the receiver closes the sssar buffer wi th rxbd[rxerror = os = 11] (oversized) and discards the rest of the frame. the receiver issues an interrupt for each of the above errors.whe n a sssar buffer is closed with rxbd[rxerror = us or os], indi cating uncompleted sdu or oversized, then rxbd[l] is set, and if rxqd[rfm] = 1 then the receiver also issues an rxf interrupt. 0x02 ? data length contains the length of the buffer associated with this bd. if this is the last buffer (l = 1) and the uui bit in the sssar txqd is set, the 5-bi t uui field is locate d at (txdbptr+data length)[3?7] with bit 3 being the msb, that is, in the byte (right justified) immediately following the last byte of the buffer. for best bandwidth utilization and optimized partitioning of the sdu to packets of exactly seglen size when an sdu is spread over multiple bd?s, the application should set data length to be an integer multip le of seg_len. (data length == n x seg_len). for an sdu on a single bd this restriction does not apply. 0x04 ? txdbptr tx data buffer pointer. points to the address of the associated buffer. there are no byte-alignment requirements for the buffer, and it may reside in either internal or external memory. this value is not modified by the cp. 1 boldfaced entries must be initialized by the user. table 42-5. sssar txbd field descriptions (continued) offset bits name 1 description 4 datasheet u .com
atm aal2 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 42-20 freescale semiconductor then, if no errors have occurred in the packet header, the p acket cid is used to ma tch the phy | vp | vc | cid with an rxqd; see section 42.4.2, ?mapping of phy | vp | vc | cid.? the match process yields an rxqd pointer. the rxqd indicate s the type of sar operation to be performed on the phy | vp | vc | cid. three sar operation modes are supported: ? for the cps sublayer, each pack et from the cid is stored, as is, in a one packet buffer. ? for switching, the packet is stored directly into the transmit buffer, and the cid is translated. ? for the sssar sublayer, all packets received fro m the cid are reassembled into an sssar sdu similar to the bd and buffer stru ctures used for aal5 frames. ? for the sssar sublayer, last pa cket uui indication is stored in the last rxbd of the sdu. for the sssar sublayer, two additional parameters are verified for each new packet received: ? ras_timer expiration. the ras_timer_duration defined in the aal2 parameter ram limits the time (starting when the first pack et is received) allowed to receive a complete sssar sdu. if this time limit is exceeded, the receiver closes th e current buffer with rxbd[rxerror = te = 01] (ras_timer expired) and starts a new sssar frame with the next packet. when a buffer is closed with rxbd[rxerror = te = 01], rxbd[l] is not set and the receiver does not issue an rxf interrupt. ? sssar_max_sdu_length. with each new packet the receiver checks whether the current accumulated length of the sssar sdu excee ds the sssar_max_sdu_length. if so, the receiver closes the current buffer with rxbd[rxerror = os = 11] (overs ized), discards the rest of the sssar sdu, rxbd[l] is set, and if rxqd[rfm] = 1 issues an rxf interrupt. note cids that have the same number but that are from different aal2 connections cannot use the same rxqd, unless they never have split packets. 42.4.2 mapping of ph y | vp | vc | cid the aal2 mapping mechanism translat es a phy | vp | vc | cid comb ination into an rxqd. an rxqd can be unique per phy | vp | vc | cid. the mapping mechanism, shown in figure 42-14 , can be broken down as follows: ? each atm channel number (rct) has its own ci d mapping table. the mapping table can be placed in internal or external memory (accor ding to rct[map]) and is pointed to by rct[cid mapping table base]. the cid of th e received packet is used as an index into the mapping table. ? each entry in the mapping table contains a 2-byte rx qd offset. this offset, multiplied by 4, is the offset to an rxqd in either the internal or external rxqd table. ? the two rxqd tables serve all the atm channe l numbers of an fcc. (rxqd_base_int and rxqd_base_ext are defined in the fcc parameter ram.) ? rxqd offsets from 8 through 511 poi nt into the internal rxqd ta ble located in dual-port ram at rxqd_base_int. note that the first 32 bytes of th e internal rxqd table are reserved (so offsets 0?7 are reserved). 4 datasheet u .com
atm aal2 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 42-21 ? rxqd offsets greater than 511 point into the ex ternal rxqd table located at rxqd_base_ext + (512 4). ? because the three types of rxqd s are different sizes, some offset numbers may not be used. figure 42-14. cid mapping process 42.4.3 aal2 switching switching is performed by pointing an rx cid at a switch rxqd (see figure 42-15 ). the switch rxqd is unique for each rx cid. the descriptor holds a translation cid number and a pointer to a cps txqd into which this packet is saved and later sent by the transmitter. (the txqd point er is responsible for the actual phy | vp | vc sw itching.) the txqd pointed to by the switch rxqd(s) should have txqd[sw] set and should not be modified by the host when the channel is active. the transmit scheduling of the packet is done by the apc according to the programmed bit rate of the atm channel that holds the switched queue. rxqd table (internal) 0 32 64 72 2044 reserved sssar rxqd cps rxqd switch rxqd rxqd table (external) 2048 cps rxqd switch rxqd rxbd table rxbd table tx queue descriptor txbd table rx buffers rx buffers tx buffers rxqd_base_int + rxqd_offset*4 cid mapping table rxqd offset rxqd offset cid0 cid1 cid255 rxqd_base_ext + 512*4 (in fcc parameter ram) rxqd offset rxqd offset ? ? ? half-word cid mapping table base rxqd_base_int (in fcc parameter ram) aal2 rct atm cell header stf cid-ph cps packet payload cid-ph cps packet payload 4 datasheet u .com
atm aal2 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 42-22 freescale semiconductor figure 42-15. aal2 switching a partial packet discard mode is provided for the aal2 switched channels that perform end-to-end sssar. when this mode is enabled (switch rxqd[ppd] = 1), if no buffer is available to r eceive a packet in the middle of a frame, the subsequent middle packets of the ss sar sdu are discarded. when the last packet of the sssar sdu arrives, the receiver attempts to re-open a buffer. a number-of-packets-in-queue counter is available in the txqd. the cp increments the counter for each packet received and decremen ts it for each packet sent. the host ca n poll the counter periodically to verify that the switching queues are not over-loaded. on any open bd that is partially filled, the receiver se ts the up (un-complete pack et) bit. when the packet is fully received during a normal error-free operation, th e up mark is removed, the empty bit is set, and operation continues. however, if an error is detected by the receiver, the empty bit is set and the up bit remains set. in such a case, the transmitter skips this bd and proceeds to the next one. if for any reason the receiver that was in the middle of the bd stopped receiving traffic, the up bit remains set and the empty bit is cleared. another receiver using the same bd ring monitors th e up bit in addition to the empty bit. if the up bit is se t, the other receiver does not proceed with the reception and gives a busy interrupt. see figure 42-18 . the receiver that is in a ?stuck? state marks the bd wi th the receiver channel code that received the partial packet so that the host interven tion is easier if needed. see figure 42-20 . if the tbnr time out cnt mechanism is used, the transmitter advances af ter it tries to transmit the same bd with up set after a given amount of attempts. th e bd will be freed up for use. refer to the tbnr time out cnt description in table 42-6 . 42.4.4 aal2 rx data structures the following sections describe the receive connection tables and the st ructures in which cps packets and sssar sdus are stored in memory. txqd txbd table txbd table tx buffers tx buffers cid mapping table offset rxqd table switch rxqd switch rxqd cid71 cid mapping table offset cid14 sw = 1 txqd sw = 1 atm rx vc 1 atm rx vc 2 atm tx vc 4 datasheet u .com
atm aal2 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 42-23 42.4.4.1 aal2 protocol-specific rct the receive connection table (rct) is a vc-level table and is where the aal type for the atm channel number is selected. the parameters related to the at m channel number or to al l the rx queues of the atm channel are maintained here. the rct also cont ains the pointer to the cid mapping table for the at m v c . figure 42-16 shows the aal2-specific rct. note for an active channel, the cp uses a burst cycle to fetch the 32-byte rct and writes back only the first 24 bytes. 012345678 9 10 11 12 131415 offset + 0x00 ? gbl bo ? dtb bib ? segf endf ? map intq offset + 0x02 ? nostf aal offset + 0x04 ? offset + 0x06 offset + 0x08 offset + 0x0a offset + 0x0c offset + 0x0e offset + 0x10 offset + 0x12 offset + 0x14 offset + 0x16 offset + 0x18 cid mapping table base offset + 0x1a offset + 0x1c ? pmt tbnr time out cnt offset + 0x1e max_cps_sdu_deliver_length ? em pm figure 42-16. aal2 protocol-specifi c receive connection table (rct) 4 datasheet u .com
atm aal2 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 42-24 freescale semiconductor table 42-6 describes the aal2 rct fields. table 42-6. aal2 protocol-spe cific rct field descriptions offset bits name 1 description 0x00 0?1 ? reserved, should be cleared during initialization. 2 gbl global. setting gbl enables snooping of data buffers, bds, interrupt queues and free buffer pool. 3?4 bo byte ordering?used for data buffers. 00 reserved 01 munged little endian 1x big endian 5 ? reserved, should be cleared during initialization. 6 dtb data buffer bus selection. 0 reside on the system bus 1 reserved. 7 bib bus selection for the bds, interrupt queues, cid mapping table, rxqds, and the free buffer pool. 0 reside on the system bus 1 reserved. 8?9 ? reserved, should be cleared during initialization. 10 segf oam f5 segment filtering 0 do not send cells with pti = 100 to the raw cell queue. 1 send cells with pti = 100 to the raw cell queue. 11 endf oam f5 end-to-end filtering 0 do not send cells with pti = 101 to the raw cell queue. 1 send cells with pti = 101 to the raw cell queue. 12 ? reserved, should be cleared during initialization. 13 map cid mapping table memory location select 0 resides in the dual-port ram. 1 resides in external memory. 14?15 intq assigns one of the four available interrupt queues to this atm channel number. 0x02 0?11 ? reserved, should be cleared during initialization. 12 nostf no stf byte 0 normal aal2 cell structure 1 the cell does not include the stf byte. in this mode each cell starts with a packet and contains only whole packets (no split or part). 13?15 aal aal type 000 aal0?reassembly with no adaptation layer 001 aal1?atm adaptation layer 1 protocol 010 aal5?atm adaptation layer 5 protocol 100 aal2?atm adaptation layer 2 protocol 101 aal1_ces. all others reserved. 4 datasheet u .com
atm aal2 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 42-25 0x04 ? ? reserved, should be cleared during initialization. 0x06 ? 0x08 ? 0x0a ? 0x0c ? 0x0e ? 0x10 ? 0x12 ? 0x14 ? 0x16 ? 0x18 ? cid mapping table base points to the base address of the cid mapping table (see figure 42-14 ). if rct[map] = 0, the pointer contains a dual -port ram address and only the 16 lsb (at 0x1a and 0x1b) are relevant. if map = 1, the pointer is a full 32-bit address in the memory space. 0x1c 0?1 ? reserved, should be cleared during initialization. 2?7 pmt performance monitoring table. assigns one of the available 64 performance monitoring tables to this vc. the table?s starting address is pmt_base+pmt 32. 8?15 tbnr time out cnt the tbnr time-out cnt is a parameter that describes the amount of attempts the transmitter tries to transmit a packet on a bd ring which is current marked as partially filled, that is, waiting for a receiver to finish reception of a packet. this value will be used internally by the transmitter that is the destination for this packet and decremented by the cpm on each attempt. upon reaching the value 1, the transmitter will act as if the receiver is stuck in error condition and proceed to the next bd in the bd ring. this parameter is valid in switch mode only and should be programmed to a higher value than the ratio between the transmitter rate and t he lowest receiver rate in the bd ring. the 8-bit value is scaled by 4 (setting tbnr time-out cnt =1 yields a value of 4 internally) so that the max number is 1k. clearing this field will disable this feature completely 0x1e 0?7 max_cps_ sdu_deliver _length indicates the maximum size cps_sdu in bytes that is allowed to be transported on this channel. this value is compared to the length of each cps_sdu before it is delivered, as specified in the itu- t recommendation i.363.2. 8?13 ? reserved, should be cleared during initialization. 14 em receive error mask for aal2 protocol-specific events. note that buffer-not-ready, rx buffer and rx frame events are not affected by this mask. 0 disable aal2 receive error events. 1 enable aal2 error events. 15 pm enable performance monitoring 0 no performance monitoring for this vc. 1 perform performance monitoring for this vc. whenever a cell is received by this vc, the associated performance monitoring table is updated. 1 boldfaced entries must be initialized by the user. table 42-6. aal2 protocol-specific rct field descriptions (continued) offset bits name 1 description 4 datasheet u .com
atm aal2 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 42-26 freescale semiconductor 42.4.4.2 cid mapping tables and rxqds each phy | vp | vc | cid combin ation is assigned an rxqd using a cid mapping table. to multiplex several receive cids into a single common queue , map each multiplexed phy | vp | vc | cid combination to one rxqd. the atm channel?s rct contains the base address of the associated cid mapping table. this base address is external (32 bits) when rct[map] = 1; otherwise, the table reside s in the dual-port ram and the base address is two bytes. the cid of the received packet is used as an index into the mapping table. the mapping table entries are 2- byte rxqd offsets. if the cid mapping table is external, it must be on the same bus as the bds and interrupt queues as specified by rct[bib]. there are two rxqds?one for internal rxqds a nd one for external rxqds. offsets between 0?511 belong to the 2048-byte internal rxqd table. it is recommended to have as many rxqds as possible in the internal table. note that the fi rst 32 bytes of the internal rxqd table are reserved for internal use; that is, rxqd offsets between 0?7 are reserved. the addr ess of an internal rxqd is rxqd_base_int + 4 rxqd_offset. offsets between 512?65535 belong to the external rxqd table. the address of an external rxqd is rxqd_base_ext + 4 rxqd_offset. the external rxqd table mu st be on the same bus as the bds and interrupt queues as specified by rct[bib]. because the three kinds of rxqds ar e each a different size (for example, an sssar rxqd is 32 bytes and a cps switch rxqd is only 4 bytes), some of the offset numbers are left unused. 42.4.4.3 cps rx queue descriptors each cps rxqd, as shown in figure 42-17 , points to an cps rxbd table. 0 11 12 13 14 15 offset + 0x00 ? rbm ? subtype offset + 0x02 rxbd table offset offset + 0x04 rxbd table base offset + 0x06 figure 42-17. cps rx queue descriptor 4 datasheet u .com
atm aal2 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 42-27 table 42-7 describes the cps rxqd fields. 42.4.4.4 cps receive buff er descriptor (rxbd) the cps rxbd structure consists of a bd table that points to data buf fers. the rxbds contain, apart from the buffer pointer, the packet header, as shown in figure 42-18 . the buffers contain the packet payload. table 42-7. cps rxqd field descriptions offset bits name 1 1 boldfaced entries must be initialized by the user. description 0x00 0?11 ? reserved, should be cleared during initialization. 12 rbm receive buffer mask 0 disable receive buffer interrupt 1 enable receive buffer interrupt 13 ? reserved, should be cleared during initialization. 14?15 subtype subtype. sublayer type, should be 00 (cps) for this descriptor 00 cps sublayer 01 cps switched 10 sssar 11 reserved. 0x02 ? rxbd table offset holds the offset to the next bd to be opened by the receiver. should be cleared during initialization. 0x04 ? rxbd table base holds the pointer to the first bd in the bd table 0 1 2 3 4 6 7 8 15 offset + 0x00 e cm w i ? up cps packet header offset + 0x02 packet header offset + 0x04 rx data buffer pointer (rxdbptr) offset + 0x06 figure 42-18. cps receive buffer descriptor 4 datasheet u .com
atm aal2 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 42-28 freescale semiconductor table 42-8 describes the cps rxbd fields. . 42.4.4.5 cps switch rx queue descriptor the switch rxqd, shown in figure 42-19 , is used for cids that are being switched from one phy 1 |vp 1 |vc 1 |cid 1 to another phy 2 |vp 2 |vc 2 |cid 2 . the rxqd contains the pointer to the txqd that controls the txbd table th rough which the packet is transferred. the switch rxqd also contains the tr anslation cid that is saved with th e packet in the transmit buffer. a ppd mode enables the discarding of the rest of an sssar frame when a buffer is not available. note that the cps switch rxqd must be unique for every rx switched cid. table 42-8. cps rxbd field descriptions offset bits name 1 1 boldfaced entries must be initialized by the user. description 0x00 0 e buffer empty bit 0 the cps rx buffer is full or data reception was aborted due to an error. the core can read or write any fields of this rxbd. the cp does not use this bd while e remains zero. 1 the cps rx buffer is empty or reception is in progress. this is controlled by the cp. once e is set, the core should not a ccess any fields of this buffer. 1 cm continuous mode 0 normal operation 1 the cp does not clear e after this bd is closed, allowing the associated buffer to be reused automatically when the cp next accesses this bd . however, the e bit is cleared if an error occurs while receiving, regardless of the cm bit setting. 2 w wrap (final bd in table) 0 this is not the last bd in the rxbd table. 1 this is the last bd in the rxbd table of this current channel. after this buffer has been used, the cp receives incoming data for this channel into the first bd in the table. the number of rxbds in this table is programmable and is determined only by the w bit. the current table cannot exceed 64 kbytes. 3 i interrupt 0 the cp will not issue an interrupt after this buffer is serviced. 1 the cp will issue an interrupt after this buffer is serviced if the rbm bit in the rxqd is set. 4?6 ? reserved, should be cleared during initialization. 7 up uncompleted packet 0 no error occurred in this packet 1 a receive error occurred that caused this packet to be uncompleted. the receive error type is reported to the interrupt queue. 8?15 cps packet header contains the beginning of the packet header. see figure 42-11 for the cps packet header format. 0x02 ? cps packet header contains the rest of the packet header. the cp checks the packet hec and if appropriate, indicates a packet hec error in an interrupt queue entry with cid = 0. see figure 42-11 for the cps packet header format. 0x04 ? rxdbptr rx data buffer pointer. points to the address of the associated buffer. there are no byte-alignment requirements for the buffer, and it may reside in either internal or external memory. this value is not modified by the cp. 4 datasheet u .com
atm aal2 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 42-29 table 42-9 describes the cps switch rxqd fields. 42.4.4.6 switch receive/transmit buffer descriptor (rxbd) the switch buffer structure consists of a bd table that points to data buffers. the rxbds contain, apart from the buffer pointer, the packet header, as shown in figure 42-20 . the buffers contain the packet payload. this bd is common to th e receiver and the transmitter. 0 7 8 11 12 13 14 15 offset + 0x00 tx cid ? rbm ppd subtype offset + 0x02 txqd pointer figure 42-19. cps switch rx queue descriptor table 42-9. cps switch rxqd field descriptions offset bits name 1 1 boldfaced entries must be initialized by the user. description 0x00 0?7 tx cid translation cid. the received cid is saved in a tx queue with this new cid number. 8?11 ? reserved, should be cleared during initialization. 12 rbm receive buffer mask 0 disable receive buffer interrupt 1 enable receive buffer interrupt 13 ppd partial packet discard 0 normal mode 1 when a buffer-not-ready event causes a packet to be discarded, the remainder of the sssar sdu is also discarded. this allows fo r better performance for switched channels that implement sssar. 14?15 subtype sublayer type. should be 01 (cps switched) for this descriptor. 00 cps sublayer 01 cps switched 10 sssar 11 reserved 0x02 ? txqd pointer points to the txqd into which the packet s of this cid are stored and later sent. 0 1 2 3 4 5 6 7 8 15 offset + 0x00 e/r 0 w i ? up cps packet header offset + 0x02 packet header (receiver cc) offset + 0x04 rx data buffer pointer (rxdbptr) offset + 0x06 figure 42-20. switch receive/transmit buffer descriptor 4 datasheet u .com
atm aal2 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 42-30 freescale semiconductor table 42-10 describes the switch rxbd fields. 42.4.4.7 sssar rx queue descriptor the sssar rxqd, as shown in figure 42-21 , points to the rxbd table a nd contains other parameters specific to the sssar sublayer. this descriptor can belong to only one phy | vp | vc | cid. table 42-10. switch rxbd field descriptions offset bits name 1 1 boldfaced entries must be initialized by the user. description 0x00 0 e/r buffer ready must be set to zero. 1 0 not valid for switching mode, should be cleared to 0 on initialization. 2 w wrap (final bd in table) 0 this is not the last bd in the rxbd table. 1 this is the last bd in the rxbd table of this current channel. after this buffer has been used, the cp receives incoming data for this channel into the first bd in the table. the number of rxbds in this table is programmable and is determined only by the w bit. the current table cannot exceed 64 kbytes. 3 i interrupt. 0 the cp will not issue an interrupt after this buffer is serviced. 1 the cp will issue an interrupt after this buffer is serviced if the rbm bit in the rxqd is set. 4?6 ? reserved, should be cleared during initialization. 7 up uncompleted packet. 0 no error occurred in this packet and the complete packet has been received. 1 if r/e = 1 a receive error occurred that ca used this packet to be uncompleted. the receive error type is reported to the interr upt queue. the transmitter will skip this bd when in this state and continue to the next bd in the ring. if r/e = 0 a receiver has received the first part of a packet and is waiting for the rest of it to be received on the next atm cell. 8?15 cps packet header contains the beginning of the packet header. see figure 42-11 for the cps packet header format. (see remark in next row) 0x02 ? cps packet header (receiver cc) contains the rest of the packet header. the cp checks the packet hec and if appropriate, indicates a packet hec error in an interrupt queue entry with cid = 0. see figure 42-11 for the cps packet header format. in case of a ?stuck? receiver in switch mode, where the bd ring in common to tx and rx, this field indicates the last receiver channel code number which has been received. the terminology for ?stuck? implies a receiver which started receiving a packet and the rest of the packet hasn?t been received.when the receiver is in a ?stuck? state the entry: cps packet header is not valid. if the time-out mechanism is being used this field is being used internally by the cpm. 0x04 ? rxbdptr rx data buffer pointer. points to the address of the associated buffer. there are no byte-alignment requirements for the buffer, and it may reside in either internal or external memory. this value is not modified by the cp. 4 datasheet u .com
atm aal2 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 42-31 table 42-11 describes the sssar rxqd fields. . 0 10 11 12 13 14 15 offset + 0x00 ? rast rbm rfm subtype offset + 0x02 rxbd table offset offset + 0x04 rxbd table base offset + 0x06 offset + 0x08 ? offset + 0x0a offset + 0x0c time stamp offset + 0x0e offset + 0x10 ? offset + 0x12 ? offset + 0x14 mrblr offset + 0x16 max_sssar_sdu_length offset + 0x18 ? offset + 0x1a offset + 0x1c offset + 0x1e figure 42-21. sssar rx queue descriptor table 42-11. sssar rxqd field descriptions offset bits name 1 description 0x00 0?10 ? reserved, should be cleared during initialization. 11 rast ras timer enable 0 ras timer disabled (time stamp field is still valid) 1 ras timer enabled. the ras timer duration is set by the ras timer duration parameter in the parameter ram. if the current sssar s du is not completed before the rastimer expires, the bd is closed showing the ra s_timer expired (te) (sssar rxbd[rxerror] = 01) and the next packet starts a new sdu. 12 rbm receive buffer mask 0 disable receive buffer interrupt 1 enable receive buffer interrupt 13 rfm receive frame mask 0 disable receive frame interrupt 1 enable receive frame interrupt 14?15 subtype sublayer type. should be 10 (sssar) for this descriptor. 00 cps sublayer 01 cps switched 10 sssar 11 reserved 4 datasheet u .com
atm aal2 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 42-32 freescale semiconductor 42.4.4.8 sssar receive buffer descriptor the sssar sdu is stored in a bd-buffer structure si milar to the structures used for aal5 frames. the buffer size is determined by sssar rxqd[mrblr]; the actual buffer space used may be smaller. if the received sssar sdu is greater than mrblr, the sdu spans over multiple buffers. the sssar rxbd is shown in figure 42-22 . 0x02 ? rxbd table offset points to the next bd to be handled by the cp. the user should initialize this pointer to zero. 0x04 ? rxbd table base points to the beginning of the bd table. 0x08 ? ? reserved, should be cleared during initialization. 0x0a ? ? reserved, should be cleared during initialization. 0x0c ? time stamp used for reassembly timeout of the sssar sd u. whenever the first packet of an sssar sdu arrives the timestamp timer is sampled and stored here (regardless of the rast bit). 0x10 ? ? reserved, should be cleared during initialization. 0x12 ? ? reserved, should be cleared during initialization. 0x14 ? mrblr maximum receive buffer length. holds the maximum receive buffer length. the actual buffer size can be less. 0x16 ? max_sssar_ sdu_ length holds the maximum sssar sdu length. upon each new packet the accumulated frame size is compared with this value. if the limit is exceeded, the cp di scards the rest of the packets of the current frame. 0x18?0 x1e ? ? reserved, should be cleared during initialization. 1 boldfaced entries must be initialized by the user. 01234567 1011 15 offset + 0x00 ecmw i l rxerror ? uui offset + 0x02 data length (dl) offset + 0x04 rx data buffer pointer (rxdbptr) offset + 0x06 figure 42-22. sssar rece ive buffer descriptor table 42-11. sssar rxqd fiel d descriptions (continued) offset bits name 1 description 4 datasheet u .com
atm aal2 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 42-33 table 42-12 describes the sssar rxbd fields. table 42-12. sssar rxbd field descriptions offset bits name 1 description 0x00 0 e empty 0 the buffer associated with this rxbd is full or data reception was aborted due to an error. the core can read or write any fields of this rxbd. the cp does not use this bd again while e remains zero. 1 the buffer associated with this rxbd is empty or reception is in progress. this rxbd and its receive buffer are controlled by the cp. once e is set, the core should not write any fields of this rxbd. 1 cm continuous mode 0 normal operation 1 the cp does not clear e after this bd is closed, allowing the associated buffer to be reused automatically when the cp next accesses this bd . however, the e bit is cleared if an error occurs while receiving, regardless of the cm bit setting. 2 w wrap (final bd in the table) 0 this is not the last bd in the rxbd table of the current channel. 1 this is the last bd in the rxbd table of this current channel. after this buffer has been used, the cp receives incoming data for this channel into the first bd in the table. the number of rxbds in this table is programmable and is determined only by the w bit. the current table cannot exceed 64 kbytes. 3 i interrupt 0 no interrupt is generated after this buffer has been serviced. 1 an rx buffer event is sent (provided that rxqd [rbm] is set) to the interrupt queue after this buffer is serviced. the ghin/glin bit in the event register is set when the int_cnt counter reaches terminal count. 4 l last. set by the cp. 0 this is not the last buffer of the sssar sdu. 1 this is the last buffer of the sssar sdu. 5?6 rxerror rx error occurred 00 no rx error occurred 01 te?ras_timer expired. the ras timer expired before this buffer could be completed. the sssar sdu stored in this buffer is not completed. 2 10 us?uncompleted sdu. a receive error c aused a packet belonging to this sssar sdu to be lost. the receiver discar ded the rest of this sssar sdu. 11 os?oversized. the size of the sssar sdu has exceeded the max_sssar_sdu_size parameter. the rest of the sdu was discarded. 7?10 ? reserved, should be cleared during initialization. 11?15 uui contains the uui of the last packet in the received sdu. valid only where the l bit is set. 4 datasheet u .com
atm aal2 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 42-34 freescale semiconductor 42.5 aal2 parameter ram when configured for atm mode, the fcc parameter ram is mapped as shown in table 42-13 . the table includes both the fields for general atm operation a nd also the fields specific to aal2 operation. note that some of the values must be initialized by the user, but values updated by the cp should not be modified by the user. 0x02 ? data length contains the length of the buffer associated with this bd. if this is the last buffer (l = 1) of the sssar sdu, this field contai ns the total frame length. 0x04 ? rxdbptr rx data buffer pointer. points to the address of the associated buffer. there are no byte-alignment requirements for the buffer, and it may reside in either internal or external memory. this value is not modified by the cp. 1 boldfaced entries must be initialized by the user. 2 when ras timer expires the rxbd is closed with ras timer expir ed indication, the last (l) bit is not set, and rxf interrupt is not issued. a new rxbd is opened for the next incoming aal2 pack et and the frame is processed as normal and is treated as a new frame. when the next sssar end-of-fram e indication is received, the rxbd at t hat time is closed wi th an l indication, and if rxqd[rfm] = 1, the receiver issues an rxf interrupt. table 42-13. aal2 parameter ram offset name width description 0x00? 0x3f ? ? reserved. should be cleared during initialization. 0x40 rcell_tmp_base hword rx cell temporary base address. po ints to a total of 64 bytes reserved dual-port ram area used by the cp. should be 64-byte aligned. user to specify only the lowest 16 bits of the dpram address offset calculated from the value in ccsrbar. 0x42 tcell_tmp_base hword tx cell temporary base addres s. points to total of 64 bytes reserved dual-port ram area used by the cp. should be 64-byte aligned. user to specify only the lowest 16 bits of the dpram address offset calculated from the value in ccsrbar. 0x44 udc_tmp_base hword udc mode only. points to a total of 32 bytes reserved dual-port ram area used by the cp. should be 64-byte aligned. user to specify only the lowest 16 bits of the dpram address offset calculated from the value in ccsrbar. 0x46 int_rct_base hword internal receive connection table ba se. user-defined. 0x48 int_tct_base hword internal transmit connection table base. user-defined. 0x4a int_tcte_base hword internal transmit connection table extension base. user-defined. 0x4c ras_timer_duration word contains the ras_time r duration in microseconds for the sssar sublayer. user-defined. 0x50 ext_rct_base word external receive connection table base. user-defined. 0x54 ext_tct_base word external transmit connection table base. user-defined. 0x58 ext_tcte_base word external transmit connection table extension base. user-defined. table 42-12. sssar rxbd field descriptions (continued) offset bits name 1 description 4 datasheet u .com
atm aal2 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 42-35 0x5c uead_offset hword user-defined cells mode only. the offset of the uead entry in the udc extra header. should be an even address. if rct[bo]=01 uead_offset should be in little-endian format. for example if uead entry is the first half word of the extra header in external memory, uead_offset should be set to 2 (second half word entry in internal ram). 0x5e rxqd_base_int hword points to the base address of the internal rxqd table. the pointer should be 32-byte aligned. user-defined. 0x60 pmt_base hword performance moni toring table base. user-defined. 0x62 apcp_base hword apc parameters table base address. user-defined. 0x64 fbt_base hword free buffer pool par ameters table base. user-defined. 0x66 intt_base hword interrupt queue par ameters table base. user-defined. 0x68 ? ? reserved. should be cleared during initialization. 0x6a uni_statt_base hword uni statistics table base. user-defined. 0x6c bd_base_ext word bd table base address extension. bd_base_ext [0?7] hold the 8 most-significant bits of th e rx/txbd table base address. bd_base_ext[8?31] should be zero. user-defined. 0x70 vpt_base / ext_cam_base word base address of the address compression vp table/external cam. user-defined. 0x74 vct_base word base address of the addre ss compression vc table. user-defined. 0x78 vpt1_base / ext_cam1_base word base address of the address compre ssion vp1 table/ext cam1. user-defined. 0x7c vct1_base word base address of the add ress compression vc1 table. user-defined. 0x80 vp_mask hword vp mask for address compression lookup. user-defined. 0x82 vci_filtering hword vci filtering enable bits. when cells with vci = 3, 4, 6, 7-15 are received and the associated vci_filtering bit = 1 the cell is sent to the raw cell queue. vci=3 is associated with vci_filtering[3], vci = 15 is associated with vci_filtering[15]. vci_filtering[0?2, 5] should be zero. see section 41.10.1.2, ?vci filtering (vcif).? 0x84 gmode hword global mode. user-defined. see section 41.10.1.3, ?global mode entry (gmode).? 0x86 comm_info hword the information field associat ed with the last host command. user-defined. see section 41.14, ?atm transmit command.? 0x88 hword 0x8a hword 0x8c ? word reserved. should be cleared during initialization. 0x90 crc32_pres word preset for crc32. initialize to 0xffffffff. 0x94 crc32_mask word constant mask for crc32. initialize to 0xdebb20e3. 0x98 aal1_snpt_base hword aal1 sn protection look up ta ble base address. (aal1 only.) the 32-byte table resides in dual-port ram and must be initialized by the user. (see section 41.10.6, ?aal1 sequence number (sn) protection table.? ) table 42-13. aal2 parameter ram (continued) offset name width description 4 datasheet u .com
atm aal2 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 42-36 freescale semiconductor 0x9a ? hword reserved. should be cleared during initialization. 0x9c srts_base word external srts logic base address. (aal1 only.) should be 16-byte aligned. 0xa0 idle/unassign_base hword idle/unassign cell base address. points to dual- port ram area contains idle/unassign cell template (little-endian format). should be 64-byte aligned. user-defined. the atm header should be 0x0000_0000 or 0x0100_0000 (clp=1). 0xa2 idle/unassign_size hword idle/unassign cell size. 52 in regular mode. 53?64 in udc mode. 0xa4 epayload word reserved payload. initialize to 0x6a6a6a6a. 0xa8 trm word (abr only) the upper bound on the time between f-rm cells for an active source. tm 4.0 defines the trm period as 100 msec. the trm value is defined by the system clock and the time stamp timer pre scaler (see rtscr). for time stamp prescaler of 1s, trm should be set to 100 ms/1s = 100,000. 0xac nrm hword (abr only) controls the maximum cells the source may send for each f-rm cell. set to 32 cells. 0xae mrm hword (abr only) controls the bandwidth between f-rm, b-rm and user data cell. set to 2 cells. 0xb0 tcr hword (abr only) tag cell rate. the minimum cell rate allowed for all abr channels. an abr channel whose acr is less than tcr sends only out-of-rate f-rm cells at tcr. should be set to 10 cells/sec as defined in the tm 4.0. uses the atmf tm 4.0 floating-point format. note that the apc minimum cell rate should be at least tcr. 0xb2 abr_rx_tcte hword (abr only) points to total of 16 bytes reserved dual-port ram area used by the cp. should be 16-byte aligned. user-defined. 0xb4 rxqd_base_ext word points to the base address of the external rxqd table. the actual address of the first rxqd in the table is rxqd_base_ext + 512 4. user-defined. 0xb8 rx_udc_base word valid only for aal2 vcs. points to the base of the rx udc header table that contains the udc headers of the aal2 vcs. the pointer to a vc udc header is: rx_udc_base + 16*ch# (where ch# is the atm channel number) 0xbc tx_udc_base word valid only for aal2 vcs. points to the base of the tx udc header table that contains the udc headers of the aal2 vcs. the pointer to a vc udc header is: tx_udc_base + 16*ch# (where ch# is the atm channel number) 0xc0? 0xdf ? ? reserved. should be cleared during initialization. 0xe0 tcell_tmp_base_ext word transmit cell temporary base address. points to a total of 64*last_aal2_ch# octets reserved in external memory for partially filled cells. note: tcell_tmp_base_ext must be on the sa me bus as the all the aal2 data buffers required for cps, sssar, and cid switching. 0xe4? 0xfb ? ? reserved. should be cleared during initialization. 0xfc pad_tmp_base hword pad template base address. poin ts to an internal memo ry area that contains the zero cell template. should be 64-byte aligned. user-defined. 0xfe ? ? reserved. should be cleared during initialization. table 42-13. aal2 parameter ram (continued) offset name width description 4 datasheet u .com
atm aal2 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 42-37 42.6 user-defined cells in aal2 the user-defined cell (udc) m ode for atm as described in section 41.7, ?user-defined cells (udc),? also applies to aal2 operation. howe ver, for aal2 operation only, the ud c headers reside in a table in external memory, not in the bds. for transmit channels in aal2 udc mode, initialize its udc header entry in the tx udc header table before activating the channel. the header can be up to 12 bytes. the tx_udc _base parameter in the parameter ram (see table 42-13 ), points to the beginning of the tx udc header table. the udc header of a specific aal2 transmit vc is located at the following address: tx_udc_base + ch# 16 (where ch# is the atm channel number) for receive channels in aal2 udc mode, the receiver copies the udc h eader from the first cell received by the vc to the rx_udc header table. the udc header s of subsequent cells of that vc are discarded; udc extended address mode (uead) is not affected. the udc header of a specific aal2 receive vc is located at the following address: rx_udc_base + ch# 16 (where ch# is the atm channel number) the structure of a udc header table (receive or transmit) is shown in figure 42-23 . figure 42-23. udc header table 42.7 aal2 exceptions for each vc, four circular interrupt queues are av ailable. by programming rct[intq] and tct[intq] for each vc, the user assigns an interrupt queue number. when one of the cids generates an interrupt request, the cp writes a new entry to the interrupt queue containing the atm channel number, the cid and a descript ion of the exception. because cid = 0 is a unique cid number, it is used to specify that the event is related to the vc rather than the cid. as with all atm exceptions, the vali d (v) bit is then set an d intq_ptr is incremente d. when intq_ptr reaches a location with the w bit set, it wraps to the firs t entry in the queue. more details can be found in section 41.11, ?atm exceptions.? ch0 udc header ch1 udc header ch n udc header 0 16 n 16 udc_base 4 datasheet u .com
atm aal2 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 42-38 freescale semiconductor an interrupt entry for a cid is shown in figure 42-24 . table 42-14 describes the interrupt queue entry fields for a cid. an interrupt entry for the vc is shown in figure 42-25 . 0 1 2 3 10 11 12 13 14 15 offset + 0x00 v ? w cid tbnr rxb bsy txb rxf offset + 0x02 channel code (cc) figure 42-24. aal2 interrupt queue entry cid 0 table 42-14. aal2 interrupt queue entry cid 0 field descriptions offset bits name description 0x00 0 v valid interrupt entry 0 this interrupt queue entry is free and can be used by the cp. 1 this interrupt queue entry is valid. the host should read this interrupt and clear this bit. 1?? 2 w wrap bit. when set, this is the last interrupt entry in the circular table. during initialization, the host must clear all w bits in the table except the last one, which must be set. 3?10 cid cid number. the exception occurred for this cid. 11 tbnr tx buffer not ready interrupt. this interrupt is issued when the cp tries to open a txbd, which is not ready (r = 0). this interrupt is sent only if txqd[bnm] = 1. the interrupt has an associated channel code and cid. note: the cid number that is placed in the interrupt queue is the one currently located in the last bd. because the cid is not updated when the bd is not ready, the cid value is the one extracted from this bd when it was last processed and transmitted. if the bd is never processed and the bd was cleared, the cid value could be zero. 12 rxb 1 1 these interrupt queue fields are defined differently for other aal types. refer to table 41-41 for more information. rx buffer interrupt. this interrupt is issued when the i bit is set for an rxbd and the rxqd[rbm] bit is set. this interrupt has an associated channel code and cid. 13 bsy busy condition. the rxbd table associated with this channel?s cid is busy. packets were discarded due to this condition. 14 txb transmit buffer interrupt. this interrupt is issued when the txbd[i] bit is set. this interrupt is sent only if txqd[tbm] is set. this interrupt has an associated channel code and cid. 15 rxf 1 receive sssar sdu (frame). an sssar frame belonging to this channel?s cid has been received. this interrupt is sent only if rxqd[rfm] = 1. 0x02 ? cc channel code specifies the atm channel number associated with this interrupt. 0 1 2 3 10 11 12 15 offset + 0x00 v ? w 0000_0000 error_code offset + 0x02 channel code (cc) figure 42-25. aal2 interrupt queue entry cid = 0 4 datasheet u .com
atm aal2 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 42-39 table 42-15 describes the interrupt queue en try fields for the vc. all the r eceive error events are enabled by setting rct[em]. table 42-15. aal2 interrupt queue entry cid = 0 field descriptions offset bits name description 0x00 0 v valid interrupt entry 0 this interrupt queue entry is free and can be used by the cp. 1 this interrupt queue entry is valid. the host should read this interrupt and clear this bit. 1?? 2 w wrap bit. when set, this is the last interrupt circular table entry. during initialization, the host must clear all w bits in the table except the last one, which must be set. 3?10 cid cid number. equals zero. this exception applies to the whole cell. 11 ? reserved 12?15 error_code a receive error was detected. 0000 parity error of the osf. 0001 the stf sequence number is incorrect. 0010 the number of octets expected to over lap into this cell does not match the osf. 0011 osf is greater than 47. 0100 a packet hec error was detected. 0101 the length of the cps packet exceeds the max_sdu_length. 0111 a packet hec error was detected in a split header packet. 0x02 ? cc channel code specifies the atm channel number associated with this interrupt. 4 datasheet u .com
atm aal2 MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 42-40 freescale semiconductor 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 43-1 chapter 43 serial peripheral interface (spi) the serial peripheral interface (spi) allows the mp c8555e to exchange data between other MPC8555E chips, the mpc860, the mc68360, th e mc68302, the m68hc11 and m68hc 05 microcontroller families, and peripheral devices such as eeproms, real-time clocks, a/d converters, and isdn devices. the spi is a full-duplex, synchronou s, character-oriented channel that supports a four-wire interface (receive, transmit, clock a nd slave select). the spi block consists of transmitter and receiver sections, an independent baud-rate genera tor, and a control unit. the transmitte r and receiver sections use the same clock, which is derived from the spi baud rate generator in ma ster mode and generated externally in slave mode. during an spi transfer, data is sent and received simultaneously. because the spi receiver and transmi tter are double-buffere d, as shown in figure 43-1 , the effective fifo size (latency) is two characters. the spi?s msb is shifted out first. when the spi is disabled in the spi mode register (spmode[en] = 0), it consumes little power. figure 43-1. spi block diagram 43.1 features the following is a list of the spi?s main features: ? four-signal interface (spimosi , spimiso, spiclk, and spisel ) multiplexed with port d signals ? full-duplex operation ? works with data characters from 4 to 16 bits long spi mode register transmit_register receive_register counter shift_register spibrg pins interface brgclk spimosi spisel spimiso spiclk txd rxd in_clk system bus peripheral bus 4 datasheet u .com
serial peripheral interface (spi) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 43-2 freescale semiconductor ? supports back-to-back charact er transmission and reception ? master or slave spi modes supported ? multiple-master environment support ? continuous transfer mode for au tomatic scanning of a peripheral ? supports maximum clock rates of 25 mhz in mast er mode and 50 mhz in slave mode, assuming a 100-mhz system clock ? independent programmabl e baud rate generator ? programmable clock phase and polarity ? open-drain outputs support mu ltiple-master configuration ? local loopback capability for testing 43.2 spi clocking and signal functions the spi can be configured as a slave or as a master in single- or mult iple-master environments. the master spi generates the transfer clock spiclk using the spi baud rate generator (brg ). the spi brg takes its input from brgclk, which is generate d in the MPC8555E clock synthesizer. spiclk is a gated clock, active only during data tran sfers. four combinations of spiclk phase and polarity can be configured with spm ode[ci, cp]. spi signals can also be configured as open-drain to support a multiple-master configuration in which a sh ared spi signal is driven by the MPC8555E or an external spi device. the spi master-in slave-out spimiso signal acts as an input for master devices and as an output for slave devices. conversely, the master-out slave-in spimosi signal is an output for master devices and an input for slave devices. the dual functionality of these signal s allows the spis in a multiple-master environment to communicate with one another usi ng a common hardware configuration. ? when the spi is a master, spiclk is the clock out put signal that shifts received data in from spimiso and transmitted data out to spimosi. spi masters must output a slave select signal to enable spi slave devices by using a separate ge neral-purpose i/o signal. assertion of an spi?s spisel while it is master causes an error. ? when the spi is a slave, spiclk is the clock input that shifts r eceived data in from spimosi and transmitted data out through spimiso. spisel is the enable input to the spi slave. in a multiple-master environment, spisel (always an input) is used to detect an error when more than one master is operating. as described in chapter 45, ?parallel i/o ports,? spimiso, spimosi, spiclk, and spisel are multiplexed with port d[16: 19] signals, respectively. they are conf igured as spi signa ls through the port d signal assignment register (pdpar ) and the port d data direction register (pddir), specifically by setting pdpar[dd n ] and pddir[dr n ]. 43.3 configuring the spi controller the spi can be programmed to work in a single- or multiple-master e nvironment. this section describes spi master and slave operation in a single-master c onfiguration and then disc usses the multi-master environment. 4 datasheet u .com
serial peripheral interface (spi) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 43-3 43.3.1 spi as a master device in master mode, the spi sends a messa ge to the slave peripheral, which sends back a simultaneous reply. a single master MPC8555E with multiple slaves can use general-purpose parallel i/ o signals to selectively enable slaves, as shown in figure 43-2 . to eliminate the multiple-mas ter error in a single-master environment, the master?s spisel input can be forced inactive by sele cting port d[19] for general-purpose i/o (pdpar[dd19] = 0). figure 43-2. single-master/multi-slave configuration to start exchanging data, the core writ es the data to be sent into a buffe r, configures a tx bd with txbd[r] set, and configures one or more rxbds. the core then sets spco m[str] in the spi command register to start sending data, which starts once the sd ma channel loads the tx fifo with data. the spi then generates programmable clock pulse s on spiclk for each character and simultaneously shifts tx data out on spimo si and rx data in on spimi so. received data is writte n into a rx buffer using the next available rxbd. the spi k eeps sending and receiving characters unt il the whole buffer is sent or an error occurs. the cp then clears txbd[r] and rxbd[e] and issues a ma skable interrupt to the interrupt controller in the siu. when multiple txbds are ready, txbd[l] determ ines whether the spi k eeps transmit ting without spcom[str] being set again. if the current txbd[l] is cleared, the next txbd is processed after data from the current buffer is sent. typically there is no delay on spimosi betwee n buffers. if the current txbd[l] is set, sending stops after the current buffe r is sent. in addition, the rxbd is closed after transmission stops, even if the rx buffer is not full; therefore, rx buffers need not be the same length as tx buffers. spimosi spimiso spiclk spisel slave 0 spimiso spiclk spisel slave 1 slave 2 master spi spimosi spimiso spiclk spisel spimosi the spisel spiclk spimiso spimosi decoder can be either internal or external logic. MPC8555E 4 datasheet u .com
serial peripheral interface (spi) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 43-4 freescale semiconductor 43.3.2 spi as a slave device in slave mode, the spi receives messages from an sp i master and sends a simult aneous reply. the slave?s spisel must be asserted before rx clocks are recogni zed; once spisel is asserted, spiclk becomes an input from the master to the slav e. spiclk can be any frequency fr om dc to brgclk/2 (12.5 mhz for a 25-mhz system). to prepare for data transfers, the sl ave?s core writes data to be sent in to a buffer, configures a txbd with txbd[r] set, and configures one or more rxbds. the core then sets spcom[str] to activate the spi. once spisel is asserted, the slave shifts data out from spimiso and in through spimosi. a maskable interrupt is issued when a full buffer finishes re ceiving and sending or after an error. the spi uses successive rxbds in the table to continue reception unt il it runs out of rx buffers or spisel is negated. transmission continues until no more data is available or spisel is negated. if it is negated before all data is sent, it stops but the txbd stays open. transmission c ontinues once spisel is reasserted and spiclk begins toggling. after the characters in the buffe r are sent, the spi sends ones as long as spisel remains asserted. 43.3.3 spi in multip le-master operation the spi can operate in a multiple-master environment in which spi devices are c onnected to the same bus. in this configuration, the spimos i, spimiso, and spiclk signals of all spis are shared; the spisel inputs are connected sepa rately, as shown in figure 43-3 . only one spi device can act as master at a time?all others must be slaves. when an spi is confi gured as a master and its spisel input is asserted, a multiple-master error occurs because more than one spi device is a bus master . the spi sets spie[mme] in the spi event register and a maskable interrupt is issued to the core. it also disables spi operation and the output drivers of spi signals. the core must cl ear spmode[en] before the spi is used again. after correcting the problems, clear spie[mme] and re-enable the spi. the maximum sustained data rate th at the spi supports is systemclk/ 50. however, the spi can transfer a single character at much higher rates?systemcl k/4 in master mode a nd systemclk/2 in slave mode. gaps should be inserted be tween multiple charac ters to keep from exceeding the maximum sustained data rate. 4 datasheet u .com
serial peripheral interface (spi) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 43-5 figure 43-3. multiple-master configuration spimiso spimosi selout0 spisel spiclk selout3 selout1 spi #2 spimiso spimosi selout1 spisel spiclk selout3 selout2 spimiso spimosi spi #1 selout0 spisel spiclk selout3 selout2 spi #0 notes: ? all signals are open-drain. ? for a system with more than two masters, spisel and spie[mme] do not detect all possible conflicts ? it is the responsibility of software to arbitrat e for the spi bus (with token passing, for example). ? selout x signals are implemented in software with general-purpose i/o signals. spisel1 spisel0 spisel3 spisel2 spimiso spimosi selout0 spisel spiclk selout2 selout1 spi #3 MPC8555E MPC8555E MPC8555E MPC8555E 4 datasheet u .com
serial peripheral interface (spi) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 43-6 freescale semiconductor 43.4 programming the spi registers the following sections describe the register s used in configuring and operating the spi. 43.4.1 spi mode register (spmode) the spi mode register (spmode), shown in figure 43-4 , controls both the spi operation mode and clock source. table 43-1 describes spmode fields. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 field ? loop ci cp div16 rev m/s en len pm reset 0000_00 ? 0_0000_0000 r/w r/w offset 0x0x9_1aa0 figure 43-4. spmode? spi mode register table 43-1. spmode field descriptions bits name 1 description 0 ? reserved, should be cleared. 1 loop loop mode. enables local loopback operation. 0 normal operation 1 loopback mode. the transmitter output is internally connected to the receiver input. the receiver and transmitter operate normally, except that received data is ignored. 2 ci clock invert. inverts spi clock polarity. see figure 43-5 and figure 43-6 . 0 the inactive state of spiclk is low. 1 the inactive state of spiclk is high. 3 cp clock phase. selects the transfer format. see figure 43-5 and figure 43-6 . 0 spiclk starts toggling in the middle of the data transfer. 1 spiclk starts toggling at the beginning of the data transfer. 4 div16 divide by 16. selects the clock source for the spi baud rate generator when configured as an spi master. in slave mode, spiclk is the clock source. 0 brgclk is the input to the spi brg. 1 brgclk/16 is the input to the spi brg. 5 rev reverse data. determines the receive and transmit character bit order. 0 reverse data?lsb of the character sent and received first. 1 normal operation?msb of the character sent and received first. 6 m/s master/slave. selects master or slave mode. 0 the spi is a slave. 1 the spi is a master. 7 en enable spi. do not change other spmode bits when en is set. 0 the spi is disabled. the spi is in a reset state and consumes minimal power. the spi brg is not functioning and the input clock is disabled. 1 the spi is enabled. configure spimosi, spimiso, spiclk, and spisel to connect to the spi as described in section 45.2, ?port registers.? 4 datasheet u .com
serial peripheral interface (spi) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 43-7 figure 43-5 shows the spi transfer format in which spiclk starts toggling in the middle of the transfer (spmode[cp] = 0). figure 43-5. spi transfer format with spmode[cp] = 0 figure 43-6 shows the spi transfer format in which spiclk starts toggli ng at the beginning of the transfer (spmode[cp] = 1). figure 43-6. spi transfer format with spmode[cp] = 1 8?11 len character length in bits per character. if the character length is not greater than a byte, every byte in memory holds (len+1) valid bits. if the character length is greater than a byte, every half-word holds (len+1) valid bits. see section 43.4.1.1, ?spi examples with different spmode[len] values.? 0000?0010reserved, causes erratic behavior. 0011 4-bit characters ? 1111 16-bit characters 12?15 pm prescale modulus select. specifies the divide ratio of th e prescale divider in the spi clock generator. brgclk is divided by 4 ([pm0?pm3] + 1), a range from 4 to 64. the clock has a 50% duty cycle. 1 boldfaced entries must be initialized by the user. table 43-1. spmode field descriptions (continued) bits name 1 description spiclk spiclk spimosi spisel (from master) spimiso (from slave) (ci = 0) (ci = 1) note: q = undefined signal. msb lsb msb q lsb spiclk spiclk spimosi spisel (from master) spimiso (from slave) (ci = 0) (ci = 1) note: q = undefined signal. msb lsb lsb qmsb 4 datasheet u .com
serial peripheral interface (spi) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 43-8 freescale semiconductor 43.4.1.1 spi examples with di fferent spmode[len] values the examples below show how spmode[len] is used to determine character length. to help map the process, the conventions shown in table 43-2 are used in the examples. once the data string image is determined, it is al ways transmitted byte by byte with the lsb of the most-significant byte sent first. fo r all examples below, assume the me mory contains the following binary image: msb ghij_klmn__opqr_stuv lsb example 1 with len=4 (data size=5), the following data is selected: msb xxxj_klmn__xxxr_stuv lsb with rev=0, the data string image is: msb j_klmn__r_stuv lsb the order of the string appearing on the line, a byte at a time is: first nmlk_j__vuts_r last with rev=1,the string has each byte reversed, and the data string image is: msb nmlk_j__vuts_r lsb the order of the string appearing on the line, one byte at a time is: first j_klmn__r_stuv last example 2 with len=7 (data size=8), the following data is selected: msb ghij_klmn__opqr_stuv lsb the data string is selected: msb ghij_klmn__opqr_stuv lsb with rev=0, the string transmitted, a byte at a time with lsb first is: first nmlk_jihg__vuts_rqpo last w/ rev=1, the string is byte reversed & transmitted, a byte at a time, lsb first: first ghij_klmn__opqr_stuv last table 43-2. example conventions convention description g?v binary symbols x deleted bit __ 1 1 both __ and _ are used to aid readability. original byte boundary _ 1 original 4-bit boundary 4 datasheet u .com
serial peripheral interface (spi) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 43-9 example 3 with len=0xc (data size=13), the following data is selected: msb ghij_klmn__xxxr_stuv lsb the data string selected is: msb r_stuv__ghij_klmn lsb with rev=0, the string transmitted, a byte at a time with lsb first is: first vuts_r__nmlk_jihg last with rev=1, the string is half-word reversed: msb nmlk_jihg__vuts_r lsb and transmitted a byte at a time with lsb first: first ghij_klmn__r_stuv last 43.4.2 spi event/mask registers (spie/spim) the spi event register (spie) gene rates interrupts and reports events recognized by the spi. when an event is recognized, the spi sets th e corresponding spie bit. cl ear spie bits by writ ing a 1?writing 0 has no effect. setting a bit in th e spi mask register (spim) enables a nd clearing a bit masks the corresponding interrupt. unmasked spie bi ts must be cleared before the cp clears internal interrupt requests. figure 43-7 shows both registers. table 43-3 describes the spie/spim fields. 01234567 field ? mme txe ? bsy txb rxb reset 0000_0000 r/w r/w offset 0x0x9_1aa6 (spie); 0x0x9_1aaa (spim) figure 43-7. spie/spim?spi event/mask registers table 43-3. spie/spim field descriptions bits name description 0?1 ? reserved, should be cleared. 2 mme multiple-master error. set when spisel is asserted externally while the spi is in master mode. 3 txe tx error. set when an error occurs during transmission. 4 ? reserved, should be cleared. 5 bsy busy. set after the first character is received but discarded because no rx buffer is available. 6 txb tx buffer. set when the tx data of the last character in the buffer is written to the tx fifo. wait two character times to be sure data is completely sent over the transmit signal. 7 rxb rx buffer. set after the last character is written to the rx buffer and the bd is closed. 4 datasheet u .com
serial peripheral interface (spi) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 43-10 freescale semiconductor 43.4.3 spi command register (spcom) the spi command register (spcom), shown in figure 43-8 , is used to start spi operation. table 43-4 describes the spcom fields. 43.5 spi parameter ram the spi parameter ram area is similar to the scc general-purpose parameter ra m. the cp accesses the spi parameter table using a user-programmed pointer (spi_base) located in the parameter ram; see section 21.4.2, ?parameter ram.? the spi parameter table can be pl aced at any 64-byt e aligned address in the dual-port ram?s general-purpose area (banks 1?8, 11 and 12). some parameter values must be user-initialized before the spi is en abled; the cp initializes the othe rs. once initialized, parameter ram values do not usually need to be accessed. they should be changed only when the spi is inactive. table 43-5 shows the memory map of the spi parameter ram. 01 7 field str ? reset 0000_0000 r/w write only offset 0x0x9_1aad figure 43-8. spcom?spi command register table 43-4. spcom field descriptions bits name 1 1 boldfaced entries must be initialized by the user. description 0 str start transmit. for an spi master, setting str causes th e spi to start transferring data to and from the tx/rx buffers if they are prepared. for a slave, setting str when the spi is idle causes it to load the tx data register from the spi tx buffer and start send ing with the next spiclk after spisel is asserted. str is cleared automatically after o ne system clock cycle. 1?7 ? reserved and should be cleared. table 43-5. spi parame ter ram memory map offset 1 name 2 width description 0x00 rbase hword rx/txbd table base address. indicate where the bd tables begin in the dual-port ram. setting rx/txbd[w] in the last bd in each bd table determines how many bds are allocated for the tx and rx sections of the spi. initialize rbase/tbase before e nabling the spi. furthermore, do not configure bd tables of the spi to overl ap any other active controller?s parameter ram. rbase and tbase should be divisible by eight. 0x02 tbase hword 0x04 rfcr byte rx/tx function code registers. the function c ode registers contain the transaction specification associated with sdma channel accesses to external memory. see section 43.5.1, ?receive/transmit function code registers (rfcr/tfcr).? 0x05 tfcr byte 4 datasheet u .com
serial peripheral interface (spi) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 43-11 0x06 mrblr hword maximum receive buffer length. the spi ha s one mrblr entry to define the maximum number of bytes the MPC8555E writes to a rx buffer before moving to the next buffer. the MPC8555E can write fewer bytes than mrblr if an error or end-of-frame occurs, but never exceeds the mrblr value. user-supplied buffers should be no smaller than mrblr. tx buffers are unaffected by mrblr and can have varying lengths; the number of bytes to be sent is programmed in txbd[data length]. mrblr is not intended to be changed while the spi is operating. however it can be changed in a single bus cycle with one 16-bit move (not two 8-bit bus cycles back-to-back). the change takes effect when the cp moves control to the next rxbd. to guarantee the exact rxbd on which the change occurs, change mrblr only while the spi receiver is disabled. mrblr should be greater than zero; it should be an even number if the character length of the data exceeds 8 bits. 0x08 rstate word rx internal state. 3 reserved for cp use. 0x0c ? word the rx internal data pointer 3 is updated by the sdma channels to show the next address in the buffer to be accessed. 0x10 rbptr hword rxbd pointer. points to the current rxbd being processed or to the next bd to be serviced when idle. after a reset or when the end of the bd ta ble is reached, the cp initializes rbptr to the rbase value. most applications should not modify rbptr, but it can be updated when the receiver is disabled or when no rx buffer is in use. 0x12 ? hword the rx internal byte count 3 is a down-count value that is in itialized with the mrblr value and decremented with every byte the sdma channels write. 0x14 ? word rx temp. 3 reserved for cp use. 0x18 tstate word tx internal state. 3 reserved for cp use. 0x1c ? word the tx internal data pointer 3 is updated by the sdma channels to show the next address in the buffer to be accessed. 0x20 tbptr hword txbd pointer. points to the current txbd during frame transmission or the next bd to be processed when idle. after reset or when the end of the txbd table is reached, the cp initializes tbptr to the tbase value. most applications do not need to modify tbptr, but it can be updated when the transmitter is disabled or when no tx buffer is in use. 0x22 ? hword the tx internal byte count 3 is a down-count value initialized with txbd[data length] and decremented with every byte r ead by the sdma channels. 0x24 ? word tx temp. 3 reserved for cp use. 0x34 ? word sdma temp. 1 from the pointer value programmed in spi_base at ccsrbar + 0x89fc. 2 boldfaced entries must be initialized by the user. 3 normally, these parameters need not be accessed. they are listed to help experienced users in debugging. table 43-5. spi parameter ram memory map (continued) offset 1 name 2 width description 4 datasheet u .com
serial peripheral interface (spi) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 43-12 freescale semiconductor 43.5.1 receive/transmit function code registers (rfcr/tfcr) figure 43-9 shows the fields in the receive/trans mit function code re gisters (rfcr/tfcr). table 43-6 describes the rfcr/tfcr fields. 43.6 spi commands table 43-7 lists transmit/receive commands sent to the cp command register (cpcr). 01234567 field ? gbl bo tc2 dtb ? reset 0000_0000 r/w r/w offset spi base + 04 (rfcr)/spi base + 05 (tfcr) figure 43-9. rfcr/tfcr?function code registers table 43-6. rfcr/tfcr field descriptions bits name 1 1 boldfaced entries must be initialized by the user. description 0?1 ? reserved, should be cleared. 2 gbl global access bit 0 disable memory snooping 1 enable memory snooping 3?4 bo byte ordering. set bo to select the required byte orderin g for the buffer. if bo is changed on-the-fly, it takes effect at the beginning of the next frame or bd. 00 true little endian. note this mode can only be used with 32-bit port size memory. 01 big endian 1x munged little endian 5 tc2 transfer code 2. contains the transfer code value of tc[2], used during this sdma channel memory access. tc[0:1] is driven with a 0b11 to identify this sdma channel access as a dma-type access. 6 dtb data bus indicator. 0 use system bus for sdma operation. 1 reserved. 7 ? reserved, should be cleared. table 43-7. spi commands command description init tx parameters initializes all transmit parameters in the parameter ram to their reset state and should be issued only when the transmitter is disabled. the init tx and rx parameters command can also be used to reset both the tx and rx parameters. 4 datasheet u .com
serial peripheral interface (spi) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 43-13 43.7 spi buffer descriptor (bd) table as shown in figure 43-10 , bds are organized into separate rxbd and txbd tables in dual-port ram. the tables have the same basic c onfiguration as for the sccs and sm cs and form circular queues that determine the order buffers are tran sferred. the cp uses bds to confir m reception and tr ansmission or to indicate error conditions so that the core knows buffers have been serviced. the buffers themselves can be placed in external memory or in any unused parameter area of the dual-port ram. figure 43-10. spi memory structure 43.7.1 spi buffer descriptors (bds) receive and transmit bds report in formation about each buffer transferred and whether a maskable interrupt should be generated. each 64-bit bd, shown in figure 43-11 and figure 43-12 , has the following structure: ? the half word at offset + 0 contains status and control bits. the cp updates the status bits after the buffer is sent or received. ? the half word at offset + 2 contains the da ta length (in bytes) that is sent or received. ? for an rxbd, this is the number of octets th e cp writes into this rxbd?s buffer once the bd closes. the cp updates this field after the recei ved data is placed into the buffer. memory allocated for this buffer should be no smaller than mrblr. ? for a txbd, this is the number of octets the cp should transmit from its buffer. normally, this value should be greater than zero. if the charact er length is more than 8 bits, the data length close rxbd forces the spi controller to close the current rxbd an d use the next bd for subsequently received data. if the controller is not receiving data, no action is taken. us e this command to extract data from a partially full buffer. init rx parameters initializes all receive parameters in the parameter ram to their reset state. should be issued only when the receiver is disabled. the init tx and rx parameters command can also be used to reset both the tx and rx parameters. table 43-7. spi commands (continued) command description frame status data length buffer pointer frame status data length buffer pointer tx buffer pointer to spi rxbd table rx buffer dual-port ram external memory txbd table rxbd table tx buffer pointer to spi txbd table 4 datasheet u .com
serial peripheral interface (spi) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 43-14 freescale semiconductor should be even. for example, to send three charac ters of 8-bit data, 1 st art, and 1 stop, the data length field should be initialized to 3. however, to send three char acters of 9-bit data, the data length field should be initialized to 6 since the three 9-bit data fields occupy three half-words in memory. the cp never modifies this field. ? the word at offset + 4 points to the beginning of the buffer. ? for an rxbd, the pointer must be even and can point to internal or external memory. ? for a txbd, the pointer can be even or odd, unl ess the character exceeds 8 bits, for which it must be even. the buffer can be in internal or external memory. 43.7.1.1 spi receive bd (rxbd) the cp uses rxbds to report on each received buffer. it closes the current buffer, generates a maskable interrupt, and starts receiving data in the next buffer on ce the current buffer is full. the cp also closes the buffer when the spi is configured as a slave and spisel is negated, indicating th at reception stopped. the core should write rxbd bits befo re the spi is enabled. the format of an rxbd is shown in figure 43-11 . table 43-8 describes the rxbd status and control fields. 0123456789101112131415 offset + 0 e ? wi l? cm ?ovme offset + 2 data length offset + 4 rx buffer pointer offset + 6 figure 43-11. spi rxbd table 43-8. spi rxbd status and control field descriptions bits name 1 description 0eempty. 0 the buffer is full or stopped receiving because of an error. the core can examine or write to any fields of this rxbd, but the cp does not use this bd while e = 0. 1 the buffer is empty or reception is in progress. the cp owns this rxbd and its buffer. once e is set, the core should not write any fields of this rxbd. 1 ? reserved, should be cleared. 2 w wrap (last bd in table). 0 not the last bd in the rxbd table. 1 last bd in the rxbd table. after this buffer is used , the cp receives incoming data using the bd pointed to by rbase (top of the table). the number of bds in th is table is determined only by the w bit and overall space constraints of the dual-port ram. 3 i interrupt. 0 no interrupt is generated after this buffer is filled. 1 spie[rxb] is set when this buffer is full, indicating the need for the core to pr ocess the buffer. spie[rxb] causes an interrupt if not masked. 4 l last. updated by the spi when the buffer is closed because spisel was negated (slave mode only). otherwise, rxbd[me] is set. the spi updates l after received data is placed in the buffer. 0 this buffer does not contain the last character of the message. 1 this buffer contains the last character of the message. 4 datasheet u .com
serial peripheral interface (spi) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 43-15 43.7.1.2 spi transmit bd (txbd) data to be sent with the spi is se nt to the cp by arranging it in buffe rs referenced by txbds in the txbd table. txbd fields should be prepared before data is sent. the format of an txbd is shown in figure 43-12 . table 43-9 describes the txbd stat us and control fields. 5 ? reserved, should be cleared. 6 cm continuous mode. master mode only; in slave mode, cm should be cleared. 0 normal operation. 1 the cp does not clear rxbd[e] after this bd is closed; the buffer is overwritten when the cp next accesses this bd. this allows continuous reception from an spi slave into one buffer for autoscanning of a serial a/d peripheral with no core overhead. 7?13 ? reserved, should be cleared. 14 ov overrun. set when a receiver overrun occurs during reception (slave mode only). the spi updates ov after the received data is placed in the buffer. 15 me multiple-master error. set when this buffer is closed because spisel was asserted when the spi was in master mode. indicates a synchronization problem between multiple masters on the spi bus. the spi updates me after the received data is placed in the buffer. 1 boldfaced entries must be initialized by the user. 0123456789101112131415 offset + 0 r ? wi l ? cm ?unme offset + 2 data length offset + 4 tx buffer pointer offset + 6 figure 43-12. spi txbd table 43-9. spi txbd status and control field descriptions bits name 1 description 0 r ready 0 the buffer is not ready to be sent. this bd or its buffer can be modified. the cp clears r (unless rxbd[cm] is set) after the buffer is sent (unle ss rxbd[cm] is set) or an error occurs. 1 the buffer is ready for transmission or is bei ng sent. the bd cannot be modified once r is set. 1 ? reserved, should be cleared. 2 w wrap (last bd in txbd table) 0 not the last bd in the table 1 last bd in the table. after this buffer is used, the cp receives incoming data using the bd pointed to by tbase (top of the table). the number of bds in this table is determined only by the w bit and overall space constraints of the dual-port ram. table 43-8. spi rxbd status and cont rol field descriptions (continued) bits name 1 description 4 datasheet u .com
serial peripheral interface (spi) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 43-16 freescale semiconductor 43.8 spi master programming example the following sequence initializes the spi to run at a high speed in master mode: 1. configure port d to enable spimi so, spimosi, spiclk, and spisel . 2. configure a parallel i/o signal to operate as the spi select output signal if needed. 3. in address 0x89fc, assign a pointer to the spi parameter ram. 4. write rbase and tbase in the spi parameter ra m to point to the rxbd and txbd tables in the dual-port ram. assuming one rxbd followed by one txbd at the beginning of the dual-port ram, write rbase with 0x0000 and tbase with 0x0008. 5. write rfcr and tfcr with 0x10 for normal operation. 6. write mrblr with the maximum number of bytes per rx buffer. for this case, assume 16 bytes, so mrblr = 0x0010. 7. initialize the rxbd. assume the rx buffe r is at 0x0000_1000 in main memory. write 0xb000 to rxbd[status and control], 0x0000 to rxbd [data length] (optional), and 0x0000_1000 to rxbd[buffer pointer]. 8. initialize the txbd. assume the tx buffer is at 0x0000_2000 in main memory and contains five 8-bit characters. write 0xb800 to txbd[status and control], 0x0005 to txbd[data length], and 0x0000_2000 to txbd[buffer pointer]. 9. execute the init rx and tx parameters command by writing 0x2541_0000 to cpcr. 10. write 0xff to spie to clear any previous events. 11. write 0x37 to spim to enable all possible spi interrupts. 3 i interrupt 0 no interrupt is generated after this buffer is processed. 1 spie[txb] or spie[txe] are set when this buffer is processed and causes interrupts if not masked. 4 l last 0 this buffer does not contain the last character of the message. 1 this buffer contains the last character of the message. 5 ? reserved, should be cleared. 6 cm continuous mode. valid only when the spi is in master mode. in slave mode, it should be cleared. 0 normal operation 1 the cp does not clear txbd[r] after this bd is closed, allowing the buffer to be resent automatically when the cp next accesses this bd. 7?13 ? reserved, should be cleared. 14 un underrun. indicates that the spi encountered a transm itter underrun condition while sending the buffer. this error occurs only when the spi is in slave mode. the spi updates un after it sends the buffer. 15 me multiple-master error. indicates that this buffer is closed because spisel was asserted when the spi was in master mode. a synchronization prob lem occurred between devices on the spi bus. the spi updates me after sending the buffer. 1 boldfaced entries must be initialized by the user. table 43-9. spi txbd status and control field descriptions (continued) bits name 1 description 4 datasheet u .com
serial peripheral interface (spi) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 43-17 12. write 0x0370 to spmode to enable normal operati on (not loopback), master mode, spi enabled, 8-bit characters, and the fastest speed possible. 13. set spcom[str] to start the transfer. after 5 bytes are sent, the txbd is closed. additionall y, the rx buffer is closed after 5 bytes are received because txbd[l] is set. 43.9 spi slave programming example the following is an example initiali zation sequence to follow when the spi is in slave mode. it is very similar to the spi master example, except that spisel is used instead of a ge neral-purpose i/o signal (as shown in figure 43-2 ). 1. enable spimiso, spimos i, spiclk, and spisel . 2. in address 0x89fc, assign a pointer to the spi parameter ram. 3. assuming one rxbd at the beginning of the du al-port ram followed by one txbd, write rbase with 0x0000 and tbase with 0x0008 in the spi parameter ram. 4. write rfcr and tfcr with 0x10 for normal operation. 5. program mrblr = 0x0010 for 16 bytes, the maximum number of bytes per buffer. 6. initialize the rxbd. assume the rx buffe r is at 0x0000_1000 in main memory. write 0xb000 to rxbd[status and control], 0x0000 to rxbd [data length] (optional), and 0x0000_1000 to rxbd[buffer pointer]. 7. initialize the txbd. assume the tx buffer is at 0x0000_2000 in main memory and contains five 8-bit characters. write 0xb800 to txbd[status and control], 0x0005 to txbd[data length], and 0x0000_2000 to txbd[buffer pointer]. 8. execute the init rx and tx parameters command by writing 0x2541_0000 to cpcr. 9. write 0xff to spie to clear any previous events. 10. write 0x37 to spim to enable all spi interrupts. 11. set spmode to 0x0170 to enable normal operation (not loopback), slave mode, spi enabled, and 8-bit characters. brg speed is ignored in slave mode. 12. set spcom[str] to enable the spi to be ready once the master begins the transfer. note if the master sends 3 bytes and negates spisel , the rxbd is closed but the txbd remains open. if the master sends 5 or more bytes, the txbd is closed after the fifth byte. if the master sends 16 bytes and negates spisel , the rxbd is closed without triggering an out-of-buffers error. if the master sends more than 16 bytes, the rxbd is closed (full) and an out-of-buffers error occurs after the 17th byte is received. 4 datasheet u .com
serial peripheral interface (spi) MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 43-18 freescale semiconductor 43.10 handling interrupts in the spi the following sequence should be follow ed to handle interrupts in the spi: 1. once an interrupt occurs, read spie to determine the interrupt s ource. normally, sp ie bits should be cleared at this time. 2. process the txbd to reuse it and the rxbd to ex tract the data from it. to transmit another buffer, simply set txbd[r], rxbd[e], and spcom[str]. 3. execute an rfi instruction. 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 44-1 chapter 44 i 2 c controller the inter-integrated circuit (i 2 c) controller lets the MPC8555E exchange data with other i 2 c devices, such as microcontrollers, eeproms, real -time clock devices, a/d convert ers, and lcd displays. the i 2 c controller uses a synchronous, multipl e-master bus that can connect several integrat ed circuits on a board. it uses two signals?serial data (sda) and serial clock (scl)?to carry information between the integrated circuits connected to it. as shown in figure 44-1 , the i 2 c controller consists of transmit a nd receive sections, an independent baud-rate generator (brg), and a cont rol unit. the transmit and receive sections use the same clock, which is derived from the i 2 c brg when in master mode and generate d externally when in slave mode. wait states are inserted during a data transfer if scl is held low by a slave device. in the middle of a data transfer, the master i 2 c controller recognizes the need for wait states by monitoring scl. however, the i 2 c controller has no automatic time-out mechanism if the slave device does not release scl; therefore, software should monitor how long scl st ays low to generate bus timeouts. figure 44-1. i 2 c controller block diagram the i 2 c receiver and transmitter are do uble-buffered, which corresponds to an effective two-character fifo latency. in normal operation, the transmitter shifts the msb (bit 0) out first. when the i 2 c is not enabled in the i 2 c mode register (i2mod[en] = 0 ), it consumes little power. control tx data register rx data register peripheral bus mode register shift register shift register baud-rate generator scl sda system bus 4 datasheet u .com
i 2 c controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 44-2 freescale semiconductor 44.1 features the following is a list of the i 2 c controller?s main features: ? two-signal interface (sda and scl) ? support for master and slave i 2 c operation ? multiple-master environment support ? continuous transfer mode for au tomatic scanning of a peripheral ? supports a maximum clock rate of 2080 khz (w ith a cpm utilization of 25%), assuming a 100-mhz system clock. ? independent, programmabl e baud-rate generator ? supports 7-bit i 2 c addressing ? open-drain output signals allow multiple master configuration ? local loopback capability for testing 44.2 i 2 c controller clocking and signal functions the i 2 c controller can be configured as a master or slave for the serial channel. as a master, the controller?s brg provides the transfer clock. the i 2 c brg takes its input from the brg clock (brgclk), which is gene rated from the cpm clock. sda and scl are bidirectional signa ls connected to a positive supply voltage through an external pull-up resistor. when the bus is free, both signals are pulled high. the general i 2 c master/slave configuration is shown in figure 44-2 . figure 44-2. i 2 c master/slave general configuration when the i 2 c controller is master, the scl cloc k output, taken directly from the i 2 c brg, shifts receive data in and transmit data out through sda. the transm itter arbitrates for the bus during transmission and aborts if it loses ar bitration. when the i 2 c controller is a slave, the scl cl ock input shifts data in and out through sda. the scl frequency ca n range from dc to brgclk/48. 44.3 i 2 c controller transfers to initiate a transfer, the master i 2 c controller sends a message specifyin g a read or write request to an i 2 c slave. the first byte of the message consists of a 7-bi t slave port address and a r/ w request bit. note that vdd vdd master slave (eeprom, for example) scl scl sda sda 4 datasheet u .com
i 2 c controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 44-3 because the r/w request follows the slave port address in the i 2 c bus specification, the r/w request bit must be placed in the ls b (bit 7) unless operating in reverse data mode; see section 44.4.1, ?i 2 c mode register (i2mod).? to write to a slave, the master sends a write request (r/w = 0) along with either the target slave?s address or a general call (broad cast) address of all zer os, followed by the data to be written. to read from a slave, the master sends a read request (r /w = 1) and the target slave?s address. when the target slave acknowledges the read request, the tr ansfer direction is re versed, and the master receives the slave?s transmit buffer(s). if the receiver (master or slave) does not acknowledge each byte transfer in the ninth bit frame, the transmitter signals a transmission error event (i2er[txe]). an i 2 c transfer timing diagram is shown in figure 44-3 . figure 44-3. i 2 c transfer timing select master or slave mode for the controller using the i 2 c command register (i2com[m/s]). set the master?s start bit, i2com[str], to begin a transfer; setting a slave?s i2com[str] activates the slave to wait for a transfer request from a master. if a master or slave transmitter?s cu rrent txbd[l] is set, transmission st ops once the buffer is sent; that is, i2com[str] must be set again to re activate transfers. if txbd[l] is zero, once the current buffer is sent, the controller begins processing the next txbd without waiting for i2com[str] to be set again. the following sections further detail the transfer process. 44.3.1 i 2 c master write (slave read) if the MPC8555E is the master, prep are the transmit buffers and bds be fore initiating a write. initialize the first transmit data byte with the slave address and write request (r/w = 0). if the MPC8555E is the slave target of the write, pr epare receive buffers and bd s to await the master?s request. figure 44-4 shows the timing for a master write. figure 44-4. i 2 c master write timing scl sda data byte start condition stop condition a c k 789 456 123 sda device address w data byte s t a r t s t o p a c k a c k note: data and ack are repeated n times. 4 datasheet u .com
i 2 c controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 44-4 freescale semiconductor a master write occurs as follows: 1. the master core sets i2com[str]. the transfer starts when the sdma ch annel loads the tx fifo with data and the i 2 c bus is not busy. 2. the i 2 c master generates a start condition?a high-to-low tran sition on sda while scl is high?and the transfer clock scl pulses for each bit shifted out on sda. if the master transmitter detects a multiple-master collision (by sensi ng a ?0? on sda while sending a ?1?), transmission stops and the channel reverts to slave mode. a maskab le interrupt is sent to the master?s core so software can try to retransmit later. 3. the slave acknowledges eac h byte and writes to its current rece ive buffer until a new start or stop condition is detected. 4. after sending each byte, the master monitors the acknowledge indication. if th e slave receiver fails to acknowledge a byte, trans mission stops and the master generates a stop condition?a low-to-high transition on sda while scl is high. 44.3.2 i 2 c loopback testing when in master mode, an i 2 c controller supports loopback operation for master write requests. the master i 2 c controller simply issues a writ e request directed to its own a ddress (programmed in i2add). the master?s receiver monitors the transm ission and reads the transmitted data into its receive buffer. loopback operation requires no special register programming. 44.3.3 i 2 c master read (slave write) before initiating a master r ead with the MPC8555E, prepar e a transmit buffer of size n + 1 bytes, where n is the number of bytes to be read fr om the slave. the first transmit byte should be initialized to the slave address with r/w = 1. the next n transmit bytes are used strictly fo r timing and can be left uninitialized. configure suitable receive buffers and bd s to receive the slave?s transmission. if the MPC8555E is the slave target of the read, prepare the i 2 c transmit buffers and bds and activate it by setting i2com[str]. figure 44-5 shows the timing for a master read. figure 44-5. i 2 c master read timing a master read occurs as follows: 1. set the master?s i2com[str] to initiate the r ead. the transfer starts when the sdma channel loads the transmit fifo with data and the i 2 c bus is not busy. 2. the slave detects a star t condition on sda and scl. sda data byte device address r s t o p s t a r t n o a c k a c k note: after the nth data byte, the master does not acknowledge the slave. 4 datasheet u .com
i 2 c controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 44-5 3. after the first byte is shifted in, the slave compares the received data to its slave address. if the slave is an MPC8555E, the address is programmed in its i 2 c address register (i2add). ? if a match is found, the slave acknowledges the r eceived byte and begins transmitting on the clock pulse immediately following the acknowledge. ? if a match is found but the slave is not ready, the read request is not acknowledged and the transaction is aborted. if the slave is an mpc 8555e, a maskable transmis sion error interrupt is triggered to allow software to prepar e data for transmission on the next try. ? if a mismatch occurs, the slave ignores the message and searches for a new start condition. 4. the master acknowledges each byte sent as l ong as an overrun does not occur. if the master receiver fails to acknowledge a byte, the slave aborts transmission. for a slave MPC8555E, the abort generates a maskable interrupt. a maskable inte rrupt is also issued after a complete buffer is sent or after an error. if an underrun occurs, the MPC8555E slave sends on es until a stop condition is detected. 44.3.4 i 2 c multi-master considerations the i 2 c controller supports a multi-master configuration, in which the i 2 c controller must alternate between master and slave modes. the i 2 c controller supports this by implementing i 2 c master arbitration in hardware. however, due to the nature of the i 2 c bus and the implementation of the i 2 c controller, certain software considerations must be made. a MPC8555E i 2 c controller attempting a master read request could simultaneously be targeted for an external master write (slave read). both operations trigger the controll er?s i2cer[rxb] event, but only one operation wins the bus arbitrati on. to determine which operation caus ed the interrupt, software must verify that its transmit operation actually completed befo re assuming that the received data is the result of its read operation. problems could also arise if the MPC8555E's i 2 c controller master sets up a transmit buffer and bd for a write request, but then is the target of a read reque st from another master. wi thout software precautions, the i 2 c controller responds to the other master with the transmit buffer originally intended for its own write request. to avoid this situation, a higher-level handsha ke protocol must be used. for example, a master, before reading a slave, write s the slave with a description of the re quested data (which register should be read, for example). this opera tion is typical with many i 2 c devices. in addition, it is not recommended to enable the MPC8555E i 2 c controller while another i 2 c master is executing transactions on the bus. the MPC8555E i 2 c controller should wait for the bus to become idle. the MPC8555E i 2 c controller assumes that other i 2 c devices on the bus closely conform to the i 2 c specification. unexpected behavior can occur if the MPC8555E i 2 c controller is conne cted with devices which operate outside the specificat ion. for example, a slave device which acknowledges a master write with 2 scl pulses instead of 1 (total of 10 scl pul ses), can cause wrong beha vior of the MPC8555E i 2 c controller on its next transaction. 4 datasheet u .com
i 2 c controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 44-6 freescale semiconductor 44.4 i 2 c registers the following sections describe the i 2 c registers. 44.4.1 i 2 c mode register (i2mod) the i 2 c mode register, shown in figure 44-6 , controls the i 2 c modes and clock source. table 44-1 describes i2mod bit functions. 01234567 field ? revd gcd flt pdiv en reset 0000_0000 r/w r/w offset 0x0x9_1860 figure 44-6. i 2 c mode register (i2mod) table 44-1. i2mod field descriptions bits name description 0?1 ? reserved, should be cleared. 2 revd reverse data. determines the rx and tx character bit order. 0 normal operation. the msb (bit 0) of a character is transferred first. 1 reverse data. the lsb (bit 7) of a character is transferred first. note: clearing revd is strongly recommended to en sure consistent bit ordering across devices. 3 gcd general call disable. determines whether the receiver acknowledges a general call address. 0 general call address is enabled. 1 general call address is disabled. 4 flt clock filter. determines if the i 2 c input clock scl is filtered to prev ent spikes in a noisy environment. 0 scl is not filtered. 1 scl is filtered by a digital filter. 5?6 pdiv predivider. selects the clock division factor before it is input into the i 2 c brg. the clock source for the i 2 c brg is the brgclk generated from the cpm clock. 00 brgclk/32 01 brgclk/16 10 brgclk/8 11 brgclk/4 note: to both save power and reduce noise susceptibility, select the pdiv with the largest division factor (slowest clock) t hat still meets perf ormance requirements. 7 en enable i 2 c operation 0i 2 c is disabled. the i 2 c is in a reset state and consumes minimal power. 1i 2 c is enabled. do not change other i2mod bits when en is set. 4 datasheet u .com
i 2 c controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 44-7 44.4.2 i 2 c address register (i2add) the i 2 c address register, shown in figure 44-7 , holds the address for this i 2 c port. table 44-2 describes i2add fields. 44.4.3 i 2 c baud rate generator register (i2brg) the i 2 c baud rate generator register, shown in figure 44-8 , sets the divide ratio of the i 2 c brg. table 44-3 describes i2brg fields. 44.4.4 i 2 c event/mask registers (i2cer/i2cmr) the i 2 c event register (i2cer) is used to generate interrupts and re port events. when an event is recognized, the i 2 c controller sets the corresponding i2cer bit. i2cer bits are clea red by writing ones; writing zeros has no effect . setting a bit in the i 2 c mask register (i2cmr) enab les and clearing a bit masks 0 67 field sad ? reset undefined r/w r/w offset 0x0x9_1864 figure 44-7. i 2 c address register (i2add) table 44-2. i2add field descriptions bits name description 0?6 sad slave address 0?6. holds the slave address for the i 2 c port. 7 ? reserved, should be cleared. 0 7 field div reset 1111_1111 r/w r/w offset 0x0x9_1868 figure 44-8. i 2 c baud rate generator register (i2brg) table 44-3. i2brg field descriptions bits name description 0?7 div division ratio 0?7. spec ifies the divide ratio of the brg divider in the i 2 c clock generator. the output of the prescaler is divided by 2 ([div0?div7] + 3) and the clock has a 50% duty cycle. div must be programmed to a minimum value of 2 if the digital f ilter is disabled and 6 if it is enabled. 4 datasheet u .com
i 2 c controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 44-8 freescale semiconductor the corresponding interrupt. unmasked i2 cer bits must be clea red before the cp clear s internal interrupt requests. figure 44-9 shows both registers. table 44-4 describes the i2cer/i2cmr fields. 44.4.5 i 2 c command register (i2com) the i 2 c command register, shown in figure 44-10 , is used to start i 2 c transfers and to select master or slave mode. 0 234567 field ? txe ? bsy txb rxb reset 0000_0000 r/w r/w offset 0x0x9_1870(i2cer)/0x0x9_1874 i2cmr) figure 44-9. i 2 c event/mask registers (i2cer/i2cmr) table 44-4. i2cer/i2cmr field descriptions bits name description 0?2 ? reserved and should be cleared. 3 txe tx error. set when an error occurs during transmission. 4 ? reserved and should be cleared. 5 bsy busy. set after the first charac ter is received but discarded because no rx buffer is available. 6 txb tx buffer. set when the tx data of the last character in the buffer is written to the tx fifo. two character times must elapse to guarantee that all data has been sent. 7 rxb rx buffer. set after the last character is wr itten to the rx buffer and the rxbd is closed. 01234567 field str ? m/s reset 0000_0000 r/w r/w offset 0x0x9_186c figure 44-10. i 2 c command register (i2com) 4 datasheet u .com
i 2 c controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 44-9 table 44-5 describes i2com fields. 44.5 i 2 c parameter ram the i 2 c controller parameter table is used for the general i 2 c parameters and is similar to the scc general-purpose parameter ram. the cp accesses the i 2 c parameter table using a user-programmed pointer (i2c_base) located in the parameter ram; see section 21.4.2, ?parameter ram.? the i 2 c parameter table can be placed at any 64-byte aligned address in the dual-port ram?s general-purpose area (banks 1?8, 11, and 12). the user must initiali ze certain parameter ram values before the i 2 c is enabled; the cp initializes the other values . software usually does not access pa rameter ram entries once they are initialized; they should be changed only when the i 2 c is inactive. table 44-6 shows the i 2 c parameter memory map. table 44-5. i2com field descriptions bits name description 0 str start transmit. in master mode, setting str causes the i 2 c controller to start sending data from the i 2 c tx buffers if they are ready. in slave mode, setting str when the i 2 c controller is idle causes it to load the tx data register from the i 2 c tx buffer and start sending when it receiv es an address byte that matches the slave address with r/w = 1. str is always read as a 0. 1?6 ? reserved and should be cleared. 7 m/s master/slave. configures the i 2 c controller to operate as a master or a slave. 0i 2 c is a slave. 1i 2 c is a master. table 44-6. i 2 c parameter ram memory map offset 1 name 2 width description 0x00 rbase hword rx/txbd table base address. indicate where the bd tables begin in the dual-port ram. setting rx/txbd[w] in the last bd in each bd tabl e determines how many bds are allocated for the tx and rx sections of the i 2 c. initialize rbase/tbase before enabling the i 2 c. furthermore, do not configure bd tables of the i 2 c to overlap any other active controller?s parameter ram. rbase and tbase should be divisible by eight. 0x02 tbase hword 0x04 rfcr byte rx/tx function code registers. the function code registers contain the transaction specification associated with sdma channel accesses to external memory. see figure 44-11 and table 44-7 . 0x05 tfcr byte 0x06 mrblr hword maximum receive buffer length. defines the maximum number of bytes the MPC8555E writes to a rx buffer before moving to the next buffer. the MPC8555E writes fewer bytes to the buffer than the mrblr value if an error or end-of-frame occurs. buffers should not be smaller than mrblr. tx buffers are unaffected by mrblr and can vary in length; the number of bytes to be sent is specified in txbd[data length]. mrblr is not intended to be changed while the i 2 c is operating. however it can be changed in a single bus cycle with one 16-bit move (not two 8-bit bus cycles back-to-back). the change takes effect when the cp moves control to the next rxbd. to guarantee the exact rxbd on which the change occurs, change mrblr only while the i 2 c receiver is disabled. mrblr should be greater than zero; it should be an even number if the character length of the data exceeds 8 bits. 0x08 rstate word rx internal state. 3 reserved for cp use. 4 datasheet u .com
i 2 c controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 44-10 freescale semiconductor figure 44-11 shows the rfcr, tfcr bit fields. 0x0c rptr word rx internal data pointer 3 is updated by the sdma channels to show the next address in the buffer to be accessed. 0x10 rbptr hword rxbd pointer. points to the next descriptor the receiver transfe rs data to when it is in an idle state or to the current descriptor during frame processing for each i 2 c channel. after a reset or when the end of the descriptor table is reached , the cp initializes rbptr to the value in rbase. most applications should not write rbpt r, but it can be modified when the receiver is disabled or when no receive buffer is used. 0x12 rcount hword rx internal byte count 3 is a down-count value that is in itialized with the mrblr value and decremented with every byte the sdma channels write. 0x14 rtemp word rx temp. 3 reserved for cp use. 0x18 tstate word tx internal state. 3 reserved for cp use. 0x1c tptr word tx internal data pointer 3 is updated by the sdma channels to show the next address in the buffer to be accessed. 0x20 tbptr hword txbd pointer. points to the next descriptor that the transmitter transfers data from when it is in an idle state or to the current descriptor duri ng frame transmission. after a reset or when the end of the descriptor table is reached, the cp initializes tbptr to the value in tbase.most applications should not write tbptr, but it can be modified when the transmitter is disabled or when no transmit buffer is used. 0x22 tcount hword tx internal byte count 3 is a down-count value initiali zed with txbd[data length] and decremented with every byte r ead by the sdma channels. 0x24 ttemp word tx temp. 3 reserved for cp use. 0x34 sdmatmp word sdma temp. 3 reserved for cp use. 1 from the pointer value programmed in i2c_base at ccsrbar + 0x8afc. 2 boldfaced entries must be initialized by the user. 3 normally, these parameters need not be accessed. 01234567 field ? gbl bo tc2 dtb ? reset 0000_0000 r/w r/w offset i2c_base + 04 (rfcr)/i2c_base + 05 (tfcr) figure 44-11. i 2 c function code registers (rfcr, tfcr) table 44-6. i 2 c parameter ram memory map (continued) offset 1 name 2 width description 4 datasheet u .com
i 2 c controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 44-11 table 44-7 describes the rfcr/tfcr bit fields. 44.6 i 2 c commands the i 2 c transmit and receive commands, shown in table 44-8 , are issued to the cp command register (cpcr). 44.7 i 2 c buffer descriptor (bd) table as shown in figure 44-12 , buffer descriptors (bds) are organized into separate rxbd and txbd tables in dual-port ram. the tables have the same basic configuration as for the sccs and smcs and form circular queues that determine the order buffers ar e transferred. the cp uses bds to confirm reception and transmission or to indicat e error conditions so that the core knows buffers have been serviced. the buffers themselves can be placed in external memory or in any unused parameter area of the dual-port ram. table 44-7. rfcr, tfcr field descriptions bits name 1 1 boldfaced entries must be initialized by the user. description 0?1 ? reserved, should be cleared. 2 gbl global access bit 0 disable memory snooping 0 enable memory snooping 3?4 bo byte ordering. selects the required byte ordering for the buffer. if bo is changed on-the-fly, it takes effect at the beginning of the next frame or bd. 00 true little-endian. note this mode can only be used with 32-bit port size memory. 01 munged little-endian. 1x big-endian. 5 tc2 transfer code 2. contains the transfer code value of tc[2], used during this sdma channel memory access. tc[0:1] is driven with a 0b11 to identify this sdma channel access as a dma-type access. 6 dtb data bus indicator. 0 use system bus for sdma operation. 1 reserved. 7 ? reserved, should be cleared. table 44-8. i 2 c transmit/receive commands command description init tx parameters initializes all transmit parameters in the parameter ram to their reset state. should be issued only when the transmitter is disabled. the init tx and rx parameters command can also be used to reset both the tx and rx parameters. close rxbd forces the i 2 c controller to close the current rx bd and use the next bd for subsequently received data. if the controller is not receiving data, no action is taken. us e this command to extract data from a partially full buffer. init rx parameters initializes all receive parameters in the parameter ram to their reset state. should be issued only when the receiver is disabled. the init tx and rx parameters command can also be used to reset both the tx and rx parameters. 4 datasheet u .com
i 2 c controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 44-12 freescale semiconductor figure 44-12. i 2 c memory structure 44.7.1 i 2 c buffer descriptors (bds) receive and transmit buffer descriptors report information about each buffer transferred and whether a maskable interrupt should be generated. each 64-bit bd, shown in figure 44-13 and figure 44-14 , has the following structure: ? the half word at offset + 0 contains status and control bits. the cp updates the status bits after the buffer is sent or received. ? the half word at offset + 2 contains the da ta length (in bytes) that is sent or received. ? for an rxbd, this is the number of octets the cp writes into this rxbd?s buffer once the descriptor closes. the cp updates this field after the received data is plac ed into the associated buffer. memory allocated for this buf fer should be no smaller than mrblr. ? for a txbd, this is the number of octets the cp should transmit from its buffer. normally, this value should be greater than zero. the cp never modifies this field. ? the word at offset + 4 points to the beginning of the buffer. ? for an rxbd, the pointer must be even and can point to internal or external memory. ? for a txbd, the pointer can be even or odd. th e buffer can reside in internal or external memory. 44.7.1.1 i 2 c receive buffer descriptor (rxbd) using rxbds, the cp reports on each buffer received, closes the current buffer, generates a maskable interrupt, and starts receiving data in the next buffer wh en the current one is full. it closes the buffer when a stop or start condition is found on the i 2 c bus or when an overrun error occurs. the core should write rxbd bits before the i 2 c controller is enabled. status and control data length buffer pointer status and control data length buffer pointer tx buffer i 2 c rxbd table pointer (rbase) rx buffer dual-port ram external memory txbd table rxbd table tx buffer i 2 c txbd table pointer (tbase) i 2 c rxbd table i 2 c txbd table 4 datasheet u .com
i 2 c controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 44-13 table 44-9 describes i 2 c rxbd status and control bits. 44.7.1.2 i 2 c transmit buffer descriptor (txbd) transmit data is arranged in buffers referenced by txbd s in the txbd table. the first word of the txbd, shown in figure 44-14 , contains status and control bits. 012345 131415 offset + 0 e ? wi l?ov? offset + 2 data length offset + 4 rx buffer pointer offset + 6 figure 44-13. i 2 c rxbd table 44-9. i 2 c rxbd status and control bits bits name 1 1 boldfaced entries must be initialized by the user. description 0 e empty 0 the buffer is full or stopped receiving because of an error. the core can examine or write to any fields of this rxbd, but the cp does not use this bd while e = 0. 1 the buffer is empty or reception is in progress. the cp owns this rxbd and its buffer. once e is set, the core should not write any fields of this rxbd. 1 ? reserved and should be cleared. 2 w wrap (last bd in table) 0 not the last bd in the rxbd table 1 last bd in the rxbd table. after this buffer is used , the cp receives incoming data using the bd pointed to by rbase (top of the table). the number of bds in th is table is determined only by the w bit and overall space constraints of the dual-port ram. 3 i interrupt 0 no interrupt is generated after this buffer is full. 1 the i2cer[rxb] is set when the cp fills this buffer, indicating that the core needs to process the buffer. the rxb bit can cause an interrupt if it is enabled. 4 l last. the i 2 c controller sets l. 0 this buffer does not contain the last character of the message. 1 this buffer holds the last character of the message. the i 2 c controller sets l after all received data is placed into the associated buffer, or because of a stop or start condition or an overrun. 5?13 ? reserved and should be cleared. 14 ov overrun. set when a receiver overrun occurs during reception. the i 2 c controller updates this bit after the received data is placed into the associated buffer. 15 ? reserved and should be cleared. 4 datasheet u .com
i 2 c controller MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 44-14 freescale semiconductor table 44-10 describes i 2 c txbd status and control bits. 0123456 12131415 offset + 0 r ? wi ls ? nak un cl offset + 2 data length offset + 4 tx buffer pointer offset + 6 figure 44-14. i 2 c txbd table 44-10. i 2 c txbd status and control bits bits name 1 1 boldfaced entries must be initialized by the user. description 0 r ready. 0 the buffer is not ready to be sent. this bd or its buffer can be modified. the cp clears r after the buffer is sent or an error occurs. 1 the buffer is ready for transmission or is bei ng sent. the bd cannot be modified once r is set. 1 ? reserved and should be cleared. 2 w wrap (last bd in txbd table). 0 not the last bd in the table. 1 last bd in the table. after this bu ffer is used, the cp tran smits data using the bd pointed to by tbase (top of the table). the number of bds in this table is det ermined only by the w bit and overall space constraints of the dual-port ram. 3 i interrupt. 0 no interrupt is generated after this buffer is serviced. 1 i2cer[txb] or i2cer[txe] is set when the buffer is serviced. if enabled, an interrupt occurs. 4 l last. 0 this buffer does not contain the last character of the message. 1 this buffer contains the last character of the message. the i 2 c controller generates a stop condition after sending this buffer. 5 s generate start condition. provides ability to send back-to-back frames with one i2com[str] trigger. 0 do not send a start condition befor e the first byte of the buffer. 1 send a start condition before the first byte of the buffer. (used to separate frames.) note: if this bd is the first one in the frame when i2com[ str] is triggered, a start condition is sent regardless of the value of txbd[s]. 6?12 ? reserved and should be cleared. 13 nak no acknowledge. indicates that the transmission was aborted because the last byte sent was not acknowledged. the i 2 c controller updates nak after the buffer is sent. 14 un underrun. indicates that the i 2 c controller encountered a transmitte r underrun condition while sending the associated buffer. the i 2 c controller updates un afte r the buffer is sent. 15 cl collision. indicates that transmissi on terminated because the transmitter was lost while arbitrating for the bus. the i 2 c controller updates cl af ter the buffer is sent. 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 45-1 chapter 45 parallel i/o ports the cpm supports four genera l-purpose i/o ports?ports a, b, c, and d. each pin in the i/o ports can be configured as a general-purpose i/o signal or as a de dicated peripheral interface signal. port c is unique in that 16 of its pins (pc[0 : 1,4 : 15,23,29]) can generate interrupts to the interrupt controller. each pin can be configured as an i nput or output and has a latch for data output, read or writ ten at any time, and configured as general-purpose i/o or a dedicated peripheral pin. part of the pins can be configured as open-drain (the pin can be configur ed in a wired-or configuration on the board). the pin drives a zero voltage but three-states when driving a high voltage. note that port pins do not have inte rnal pull-up resistors. due to the cpm?s significant flexibility, many dedicated peripheral functions are multiplexed ont o the ports. the func tions are grouped to maximize the pins? usefulness in the greatest numbe r of applications. note that to obtain a full understanding of the pin assignment capability described in this chapte r, a user must understand the cpm peripherals. 45.1 features the following is a list of the para llel i/o ports? important features: ? port a is 24 bits. ? port b is 14 bits. ? port c is 28 bits. ? port d is 16 bits. ? all ports are bidirectional. ? all ports have alternate on-chip peripheral functions. ? all ports are three-stated at system reset. ? all pin values can be read while the pi n is connected to an on-chip peripheral. ? some pins have open-drain capability. ? port c offers 16 interrupt input pins (pc[0 : 1, 4 : 15, 23, 29]). 45.2 port registers each port has four memory-mapped, read/write, 32-bit control registers. 45.2.1 port open-drain registers (podr x ) the port open-drain registers (podr x ), shown in figure 45-1, figure 45-2, figure 45-3 and figure 45-4 , indicate a normal or wired-or configuration of the port pins. 4 datasheet u .com
parallel i/o ports MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 45-2 freescale semiconductor 45.2.1.1 port a open-drain register (podra) table 45-1 describes podra fields. 45.2.1.2 port b open-drain register (podrb) 0 7 8 9 10 11 12 13 14 15 field ? od8 od9 od10 od11 od12 od13 od14 od15 reset 0000_0000_0000_0000 r/w r/w offset 0x9_0d0c 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field od16 od17 od18 od19 od20 od21 od22 od23 od24 od25 od26 od27 od28 od29 od30 od31 reset 0000_0000_0000_0000 r/w r/w offset 0x9_0d0e figure 45-1. port a open-drain registers (podra) table 45-1. podra field descriptions bits name description 0?7 ? reserved, should be cleared. 8?31 od n open-drain configuration. determines whether the corr esponding pin is actively driven as an output or is an open-drain driver. 0 the i/o pin is actively driven as an output. 1 the i/o pin is an open-drain driver. as an output, the pin is driven active-low; otherwise it is three-stated. 0 15 field ? reset 0000_0000_0000_0000 r/w r/w offset 0x9_0d2c 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field ? od18 od19 od20 od21 od22 od23 od24 od25 od26 od27 od28 od29 od30 od31 reset 0000_0000_0000_0000 r/w r/w offset 0x9_0d2e figure 45-2. port b open-drain registers (podrb) 4 datasheet u .com
parallel i/o ports MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 45-3 table 45-2 describes podrb fields. 45.2.1.3 port c open-drain register (podrc) table 45-3 describes podrc fields. table 45-2. podrb field descriptions bits name description 0?17 ? reserved, should be cleared. 18?31 od n open-drain configuration. determines whether the corr esponding pin is actively driven as an output or is an open-drain driver. 0 the i/o pin is actively driven as an output. 1 the i/o pin is an open-drain driver. as an output, the pin is driven active-low; otherwise it is three-stated. 0123456789101112131415 field od0 od1 ? od4 od5 od6 od7 od8 od9 od10 od11 od12 od13 od14 od15 reset 0000_0000_0000_0000 r/w r/w offset 0x9_0d4c 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field od16 od17 od18 od19 od20 od21 od22 od23 od24 od25 od26 od27 od28 od29 ? reset 0000_0000_0000_0000 r/w r/w offset 0x9_0d4e figure 45-3. port c open-drain registers (podrc) table 45-3. podrc field descriptions bits name description 0?1, 4?29 od n open-drain configuration. determines whether the corr esponding pin is actively driven as an output or is an open-drain driver. 0 the i/o pin is actively driven as an output. 1 the i/o pin is an open-drain driver. as an output, the pin is driven active-low; otherwise it is three-stated. 2?3, 30?31 ? reserved, should be cleared. 4 datasheet u .com
parallel i/o ports MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 45-4 freescale semiconductor 45.2.1.4 port d open-drain register (podrd) table 45-4 describes podrd fields. 45.2.2 port data registers (pdat x ) a read of port data registers (pdat x ), shown in figure 45-5 , table 45-6 , table 45-7 , and table 45-8 , returns the data at the pin, independent of whether th e pin is defined as an input or output. this allows detection of output conflicts at the pin by comparing th e written data with the data on the pin. a write to the pdat x is latched, and if the equivalent pdir x bit is configured as an output, the value latched for that bit is driven onto its respective pin. pdat x can be read or writte n at any time and is not initialized. if a port pin is selected as a general-purpose i/o pi n, it can be accessed through the port data register (pdat x ). data written to the pdat x is stored in an output latch. if a port pin is confi gured as an output, the output latch data is gated onto th e port pin. in this case, when pdat x is read, the port pi n itself is read. if a port pin is configured as an input, data written to pdat x is still stored in the output latch, but is prevented from reaching the port pin. in this case, when pdat x is read, the state of the port pin is read. 0 6 7 8 13 14 15 field ? od7 ? od14 od15 reset 0000_0000_0000_0000 r/w r/w offset 0x9_0d0c (podra), 0x9_0d2c (podrb ), 0x9_0d4c (podrc), 0x9_0d6c (podrd) 16 17 18 19 20 21 22 23 24 25 26 28 29 30 31 field od16 od17 od18 od19 od20 od21 od22 od23 od24 od25 ? od29 od30 od31 reset 0000_0000_0000_0000 r/w r/w offset 0x9_0d0e (podra), 0x9_0d2e (po drb), 0x9_0d4e (podrc), 0x9_0d6e (podrd) figure 45-4. port d open-drain registers (podrd) table 45-4. podrd field descriptions bits name description 0?6, 8?13, 26?28 ? reserved, should be cleared. 7, 14?25, 29?31 od n open-drain configuration. determines whether the corr esponding pin is actively driven as an output or is an open-drain driver. 0 the i/o pin is actively driven as an output. 1 the i/o pin is an open-drain driver. as an output, the pin is driven active-low, otherwise it is three-stated. 4 datasheet u .com
parallel i/o ports MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 45-5 45.2.2.1 port a data register (pdata) 45.2.2.2 port b data register (pdatb) 0 7 8 9 10 11 12 13 14 15 field ? d8 d9 d10 d11 d12 d13 d14 d15 reset ? r/w r/w offset 0x9_0d10 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 d28 d29 d30 d31 reset ? r/w r/w offset 0x9_0d12 figure 45-5. port a data registers (pdata) 0 15 field ? reset ? r/w r/w offset 0x9_0d30 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field ? d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 d28 d29 d30 d31 reset ? r/w r/w offset 0x9_0d32 figure 45-6. port b data registers (pdatb) 4 datasheet u .com
parallel i/o ports MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 45-6 freescale semiconductor 45.2.2.3 port c data register (pdatc) 45.2.2.4 port d data register (pdatd) 0123456789101112131415 field d0 d1 ? d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 reset ? r/w r/w offset 0x9_0d50 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 d28 d29 ? reset ? r/w r/w offset 0x9_0d52 figure 45-7. port c data registers (pdatc) 0 6 7 8 13 14 15 field ? d7 ? d14 d15 reset ? r/w r/w offset 0x9_0d70 16 17 18 19 20 21 22 23 24 25 26 28 29 30 31 field d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 ? d29 d30 d31 reset ? r/w r/w offset 0x9_0d72 figure 45-8. port d data registers (pdatd) 4 datasheet u .com
parallel i/o ports MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 45-7 45.2.3 port data direction registers (pdir x ) the port data direct ion registers (pdir x ), shown in figure 45-9 , figure 45-10 , figure 45-11 , and figure 45-12 , are cleared at system reset. 45.2.3.1 port a data dir ection register (pdira) table 45-5 describes pdira fields. 0 7 8 9 10 11 12 13 14 15 field ? dr8 dr9 dr10 dr11 dr12 dr13 dr14 dr15 reset 0000_0000_0000_0000 r/w r/w offset 0x9_0d00 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field dr16 dr17 dr18 dr19 dr20 dr21 dr22 dr23 dr24 dr25 dr26 dr27 dr28 dr29 dr30 dr31 reset 0000_0000_0000_0000 r/w r/w offset 0x9_0d02 figure 45-9. port a data direction regi ster (pdira) table 45-5. pdira field descriptions bits name description 0?7 ? reserved, should be cleared. 8?31 dr n direction. indicates whether the pin is used as an input or an output. 0 the corresponding pin is an input or is bidirectional. 1 the corresponding pin is an output. 4 datasheet u .com
parallel i/o ports MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 45-8 freescale semiconductor 45.2.3.2 port b data dir ection register (pdirb) table 45-6 describes pdirb fields. 45.2.3.3 port c data dir ection register (pdirc) 0 15 field ? reset 0000_0000_0000_0000 r/w r/w offset 0x9_0d20 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field ? dr18 dr19 dr20 dr21 dr22 dr23 dr24 dr25 dr26 dr27 dr28 dr29 dr30 dr31 reset 0000_0000_0000_0000 r/w r/w offset 0x9_0d22 figure 45-10. port b data direction register (pdirb) table 45-6. pdirb field descriptions bits name description 0?17 ? reserved, should be cleared. 18?31 dr n direction. indicates whether the pin is used as an input or an output. 0 the corresponding pin is an input or is bidirectional. 1 the corresponding pin is an output. 0123456789101112131415 field dr0 dr1 ? dr4 dr5 dr6 dr7 dr8 dr9 dr10 dr11 dr12 dr13 dr14 dr15 reset 0000_0000_0000_0000 r/w r/w offset 0x9_0d40 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field dr16 dr17 dr18 dr19 dr20 dr21 dr22 dr23 dr24 dr25 dr26 dr27 dr28 dr29 ? reset 0000_0000_0000_0000 r/w r/w offset 0x9_0d42 figure 45-11. port c data direction register (pdirc) 4 datasheet u .com
parallel i/o ports MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 45-9 table 45-7 describes pdirc fields. 45.2.3.4 port d data dir ection register (pdird) table 45-8 describes pdird fields. table 45-7. pdirc field descriptions bits name description 0?1, 4?29 dr n direction. indicates whether the pin is used as an input or an output. 0 the corresponding pin is an input or is bidirectional. 1 the corresponding pin is an output. 2?3, 30?31 ? reserved, should be cleared. 0 6 7 8 13 14 15 field ? dr7 ? dr14 dr15 reset 0000_0000_0000_0000 r/w r/w offset 0x9_0d60 16 17 18 19 20 21 22 23 24 25 26 28 29 30 31 field dr16 dr17 dr18 dr19 dr20 dr21 dr22 dr23 dr24 dr25 ? dr29 dr30 dr31 reset 0000_0000_0000_0000 r/w r/w offset 0x9_0d62 figure 45-12. port d data direction register (pdird) table 45-8. pdird field descriptions bits name description 0?6, 8?13, 26?28 ? reserved, should be cleared. 7, 14?25, 29?31 dr 7 direction. indicates whether the pin is used as an input or an output. 0 the corresponding pin is an input or is bidirectional. 1 the corresponding pin is an output. 4 datasheet u .com
parallel i/o ports MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 45-10 freescale semiconductor 45.2.4 port pin assignment registers (ppar x ) the port pin assignment registers (ppar x ) are cleared at system reset. 45.2.4.1 port a pin assignment registers (ppara) table 45-9 describes ppara fields. 0 7 8 9 10 11 12 13 14 15 field ? dd8 dd9 dd10 dd11 dd12 dd13 dd14 dd15 reset 0000_0000_0000_0000 r/w r/w offset 0x9_0d04 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field dd16 dd17 dd18 dd19 dd20 dd21 dd22 dd23 dd24 dd25 dd26 dd27 dd28 dd29 dd30 dd31 reset 0000_0000_0000_0000 r/w r/w offset 0x9_0d06 . figure 45-13. port a pin a ssignment register (ppara) table 45-9. ppara field descriptions bits name description 0?7 ? reserved, should be cleared. 8?21 dd n dedicated enable. indicates whether the pin is a general-purpose i/o or a dedicated peripheral pin. 0 general-purpose i/o. the peripheral functions of the pin are not used. 1 dedicated peripheral function. the pin is used by th e internal module. the on-chip peripheral function to which it is dedicated can be determined by other bits such as those in the pdira. 22?23 dd n dedicated enable. refer to description above. ? reserved, should be cleared. note: pa[22:23] can be used only as general purpose. 24?31 dd n dedicated enable. indicates whether the pin is a general-purpose i/o or a dedicated peripheral pin. 0 general-purpose i/o. the peripheral functions of the pin are not used. 1 dedicated peripheral function. the pin is used by th e internal module. the on-chip peripheral function to which it is dedicated can be determined by other bits such as those in the pdira. 4 datasheet u .com
parallel i/o ports MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 45-11 45.2.4.2 port b pin assignment registers (pparb) table 45-10 describes pparb fields. 45.2.4.3 port c pin assignment registers (pparc) 0 15 field ? reset 0000_0000_0000_0000 r/w r/w offset 0x9_0d24 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field ? dd18 dd19 dd20 dd21 dd22 dd23 dd24 dd25 dd26 dd27 dd28 dd29 dd30 dd31 reset 0000_0000_0000_0000 r/w r/w offset 0x9_0d26 figure 45-14. port b pin a ssignment register (pparb) table 45-10. pparb fi eld descriptions bits name description 0?17 ? reserved, should be cleared. 18?31 dd n dedicated enable. indicates whether the pin is a general-purpose i/o or a dedicated peripheral pin. 0 general-purpose i/o. the peripheral functions of the pin are not used. 1 dedicated peripheral function. the pin is used by th e internal module. the on-chip peripheral function to which it is dedicated can be determined by other bits such as those in the pdirb. 0123456789101112131415 field dd0 dd1 ? dd4 dd5 dd6 dd7 dd8 dd9 dd10 dd11 dd12 dd13 dd14 dd15 reset 0000_0000_0000_0000 r/w r/w offset 0x9_0d44 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field dd16 dd17 dd18 dd19 dd20 dd21 dd22 dd23 dd24 dd25 dd26 dd27 dd28 dd29 ? reset 0000_0000_0000_0000 r/w r/w offset 0x9_0d46 figure 45-15. port c pin a ssignment register (pparc) 4 datasheet u .com
parallel i/o ports MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 45-12 freescale semiconductor table 45-11 describes pparc fields. 45.2.4.4 port d pin assignment registers (ppard) table 45-12 describes ppard fields. table 45-11. pparc fi eld descriptions bits name description 0?1, 4-29 dd n dedicated enable. indicates whether the pin is a general-purpose i/o or a dedicated peripheral pin. 0 general-purpose i/o. the peripheral functions of the pin are not used. 1 dedicated peripheral function. the pin is used by th e internal module. the on-chip peripheral function to which it is dedicated can be determined by other bits such as those in the pdirc. 2?3, 30?31 ? reserved, should be cleared. 0 6 7 8 13 14 15 field ? dd7 ? dd14 dd15 reset 0000_0000_0000_0000 r/w r/w offset 0x9_0d64 16 17 18 19 20 21 22 23 24 25 26 28 29 30 31 field dd16 dd17 dd18 dd19 dd20 dd21 dd22 dd23 dd24 dd25 ? dd29 dd30 dd31 reset 0000_0000_0000_0000 r/w r/w offset 0x9_0d66 figure 45-16. port d pin a ssignment register (ppard) table 45-12. ppard fi eld descriptions bits name description 0?6, 8?13, 26?28 ? reserved, should be cleared. 7, 14?25, 29?31 dd n dedicated enable. indicates whether the pin is a general-purpose i/o or a dedicated peripheral pin. 0 general-purpose i/o. the peripheral functions of the pin are not used. 1 dedicated peripheral function. the pin is used by th e internal module. the on-chip peripheral function to which it is dedicated can be determined by other bits such as those in the pdird. 4 datasheet u .com
parallel i/o ports MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 45-13 45.2.5 port special options registers (psor x ) psor x bits are effective onl y if the corresponding ppar x [dd n ] = 1 (a dedicated peripheral function). note if the corresponding ppar x [dd n ] = 1 (configured as a general-purpose pin) before programming a psor x or pdir x bit, a pin might function for a short period as an unwanted de dicated function and cause unknown behavior. figure 45-17 shows the port special options registers (psor x ). 45.2.5.1 port a special options register (psora) table 45-13 describes psora fields. 0 7 8 9 10 11 12 13 14 15 field ? so8 so9 so10 so11 so12 so13 so14 so15 reset 0000_0000_0000_0000 r/w r/w offset 0x9_0d08 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 fieldso16so17so18so19so20so21so22so23so24so25so26so27so28so29so30so31 reset 0000_0000_0000_0000 r/w r/w offset 0x9_0d0a figure 45-17. port a special options register (psora) table 45-13. psor x field descriptions bits name description 0?7 ? reserved, should be cleared. 8?21 so n special-option. determines whether a pin c onfigured for a dedicated function (ppara[dd n ] = 1) uses option 1 or option 2. options are described in section 45.5, ?port tables.? 0 dedicated peripheral function. option 1. 1 dedicated peripheral function. option 2. 22?23 so n special-option. see description above. ? reserved, should be cleared. note: pa[22:23] can be used only as general purpose. 24?31 so n special-option. determines whether a pin c onfigured for a dedicated function (ppara[dd n ] = 1) uses option 1 or option 2. options are described in section 45.5, ?port tables.? 0 dedicated peripheral function. option 1. 1 dedicated peripheral function. option 2. 4 datasheet u .com
parallel i/o ports MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 45-14 freescale semiconductor 45.2.5.2 port b special options registers (psorb) table 45-14 describes psorb fields. 45.2.5.3 port c special options registers (psorc) 0 15 field ? reset 0000_0000_0000_0000 r/w r/w offset 0x9_0d28 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field ? so18 so19 so20 so21 so22 so23 so 24 so25 so26 so27 so28 so29 so30 so31 reset 0000_0000_0000_0000 r/w r/w offset 0x9_0d2a figure 45-18. port b special options registers (psorb) table 45-14. psorb field descriptions bits name description 0?17 ? reserved, should be cleared. 18?31 so n special-option. determines whether a pin c onfigured for a dedicated function (pparb[dd n ] = 1) uses option 1 or option 2. options are described in section 45.5, ?port tables.? 0 dedicated peripheral function. option 1. 1 dedicated peripheral function. option 2. 0123456789101112131415 field so0 so1 ? so4 so5 so6 so7 so8 s o9 so10 so11 so12 so13 so14 so15 reset 0000_0000_0000_0000 r/w r/w offset 0x9_0d48 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 field so16 so17 so18 so19 so20 so21 so22 so23 so24 so25 so26 so27 so28 so29 ? reset 0000_0000_0000_0000 r/w r/w offset 0x9_0d4a figure 45-19. port c special options registers (psorc) 4 datasheet u .com
parallel i/o ports MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 45-15 table 45-15 describes psorc fields. 45.2.5.4 port d special options registers (psord) table 45-13 describes psord fields. table 45-15. psorc field descriptions bits name description 0?1, 4?29 so n special-option. determines whether a pin configured for a dedicated function (ppar c [dd n ] = 1) uses option 1 or option 2. options are described in section 45.5, ?port tables.? 0 dedicated peripheral function. option 1. 1 dedicated peripheral function. option 2. 2?3 30?31 ? reserved, should be cleared. 0 6 7 8 13 14 15 field ? so7 ? so14 so15 reset 0000_0000_0000_0000 r/w r/w offset 0x9_0d68 16 17 18 19 20 21 22 23 24 25 26 28 29 30 31 field so16 so17 so18 so19 so20 so21 so22 so23 so24 so25 ? so29 so30 so31 reset 0000_0000_0000_0000 r/w r/w offset 0x9_0d6a figure 45-20. special options registers (psord) table 45-16. psord field descriptions bits name description 0?6, 8?13, 26?28 ? reserved, should be cleared. 7, 14?25, 29?31 so n special-option. determines whether a pin co nfigured for a dedicated function (ppard[dd n ] = 1) uses option 1 or option 2. options are described in section 45.5, ?port tables.? 0 dedicated peripheral function. option 1. 1 dedicated peripheral function. option 2. 4 datasheet u .com
parallel i/o ports MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 45-16 freescale semiconductor 45.3 port block diagram figure 45-21 shows the functional block diagram. figure 45-21. port functional operation pin pdat x default input in1 default input in2 to ded in1 to ded in2 from ded out2 pdat x read 0 1 0 1 ppar & psor & pdir ppar & psor & pdir open drain control en podr 0 latch from ded out1 psor 1 0 1 pdat x write to/from internal bus register name 0 1 description ppar x general purpose dedicated port pin assignment psor x dedicated 1 dedicated 2 special operation pdir x input output direction 1 1 bidirectional signals must be programmed as inputs (pdir = 0). podr x regular open drain pdat x 01data read pdir ppar 4 datasheet u .com
parallel i/o ports MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 45-17 45.4 port pin functions each pin can operate as a general-purpose i/ o pin or as a dedicated input or output pin. 45.4.1 general-purpose i/o pins each one of the port pins is inde pendently configured as a genera l-purpose i/o pin if the corresponding port pin assignment register (ppar) bit is cleared. each pin is configured as a dedi cated on-chip peripheral pin if the corresponding ppar bit is set.when the port pin is c onfigured as a general-purpose i/o pin, the signal direction for that pin is dete rmined by the corresponding control bit in the port data direction register (pdir). the port i/o pin is c onfigured as an input if the corresponding pdir bit is cleared; it is configured as an output if the corresponding pdir bit is set. all ppar a nd pdir bits are cleared on total system reset, configuring all port pins as general-purpose input pins. if a port pin is selected as a general-purpose i/o pi n, it can be accessed through the port data register (pdat x ). data written to the pdat x is stored in an output latch. if a port pin is confi gured as an output, the output latch data is gated onto th e port pin. in this case, when pdat x is read, the port pi n itself is read. if a port pin is configured as an input, data written to pdat x is still stored in the output latch, but is prevented from reaching the port pin. in this case, when pdat x is read, the state of the port pin is read. 45.4.2 dedicated pins when a port pin is not configured as a general-purpose i/ o pin, it has a dedicated functionality, as described in the following tables. no te that if an input to a periphera l is not supplied from a pin, a default value is supplied to the on- chip peripheral as listed in the right-most column. note some output functions can be output on 2 different pins. for example, the output for brg5 can come out on both pc13 and pc23. the user can freely configure such functions to be output on two pins at once. however, there is typically no advantage in doing so unless there is a large fanout where it is advantageous to share the load between two pins. many input functions can also come from two different pins; see section 45.5, ?port tables.? 45.5 port tables tables 45-17 through 45-20 describe th e port functionality according to the configuration of the port registers (ppar x , psor x , and pdir x ). each pin can function as a ge neral-purpose i/o, one of two dedicated outputs, or one of two dedicated inputs. as shown in figure 45-22 , some input functions can come from two different pins for flexibility. secondary option programming is relevant only if pr imary option is programme d to the default value. 4 datasheet u .com
parallel i/o ports MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 45-18 freescale semiconductor note in the MPC8555E cpm pio port pinmuxing, fcc2 only has a primary option available for fcc2_txadd r0, fcc2_rxaddr0. there are no secondary options for these signa ls in the cpm pio port pinmuxing. figure 45-22. primary and secondary option programming in the tables below, the default va lue for a primary option is simply a reference to the secondary option. in the secondary option, the programming is relevant only if the primary option is not used for the function. table 45-17 shows the port a pin assignments. table 45-17. port a dedicated pin assignment (ppara = 1) pin pin function psora = 0 psora = 1 pdira = 1 (output) pdira = 0 (input) default input pdira = 1 (output) pdira = 0 (input, or i/o if specified) default input pa 3 1 fcc1: txenb utopia master fcc1: txenb utopia slave gnd fcc1: col mii gnd pa 3 0 fcc1: txclav utopia slave fcc1: txclav utopia master fcc1: txclav0 mphy, master, direct polling gnd fcc1: rts fcc1: crs mii gnd pa 2 9 fcc1: txsoc utopia fcc1: tx_er mii pa 2 8 fcc1: rxenb utopia master fcc1: rxenb utopia slave gnd fcc1: tx_en mii/rmii pa 2 7 fcc1: rxsoc utopia gnd fcc1: rx_dv mii fcc1: crs_dv rmii gnd mux mux pin pd19 pin pc25 gnd ppard[19] == 1 & pparc[25] == 1 & psord[19] == 0 & pdird[19] == 0 psord[25] == 1 & pdird[25] == 0 primary option secondary option pc25 pd19 0 1 0 1 for spisel for spisel to spisel 4 datasheet u .com
parallel i/o ports MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 45-19 pa 2 6 fcc1: rxclav utopia slave fcc1: rxclav utopia master fcc1: rxclav0 mphy, master, direct polling gnd fcc1: rx_er mii/rmii gnd pa 2 5 fcc1: txd[0] utopia 8 msnum[2] 1 pa 2 4 fcc1: txd[1] utopia 8 msnum[3] 1 pa 2 3 fcc1: txd[2] utopia 8 pa 2 2 fcc1: txd[3] utopia 8 pa 2 1 fcc1: txd[4] utopia 8 fcc1: txd[3] mii/hdlc nibble pa 2 0 fcc1: txd[5] utopia 8 fcc1: txd[2] mii/hdlc nibble pa 1 9 fcc1: txd[6] utopia 8 fcc1: txd[1] mii/hdlc nibble fcc1: txd[1] rmii dibit pa 1 8 fcc1: txd[7] utopia 8 fcc1: txd[0] mii/hdlc nibble fcc1: txd[0] rmii dibit fcc1: txd hdlc/transp table 45-17. port a dedicated pin assignment (ppara = 1) (continued) pin pin function psora = 0 psora = 1 pdira = 1 (output) pdira = 0 (input) default input pdira = 1 (output) pdira = 0 (input, or i/o if specified) default input 4 datasheet u .com
parallel i/o ports MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 45-20 freescale semiconductor pa 1 7 fcc1: rxd[7] utopia 8 fcc1: rxd[0] mii/hdlc nibble fcc1: rxd[0] rmii dibit fcc1: rxd[0] hdlc/transp. gnd pa 1 6 fcc1: rxd[6] utopia 8 fcc1: rxd[1] mii/hdlc nibble fcc1: rxd[1] rmii dibit gnd pa 1 5 fcc1: rxd[5] utopia 8 fcc1: rxd[2] mii/hdlc nibble gnd pa 1 4 fcc1: rxd[4] utopia 8 fcc1: rxd[3] mii/hdlc nibble gnd pa 1 3 fcc1: rxd[3] utopia 8 gnd msnum[4] 1 pa 1 2 fcc1: rxd[2] utopia 8 gnd msnum[5] 1 pa 1 1 fcc1: rxd[1] utopia 8 gnd msnum[6] 1 pa 1 0 fcc1: rxd[0] utopia 8 gnd msnum[7] 1 pa 9 smc2: smtxd tdm_c2: l1txd i/o pa 8 smc2: smrxd (primary option) gnd tdm_c2: l1rxd i/o, serial 1 msnum[2?7] is the sub-block code of the peripheral cont roller using sdma; msnum[7] indicates which section, transmit or receive, is active during the transfer. msnum is a field in the smevr and lmevr registers that represents the serial number of the channel that created a data error. see section 27.1.2, ?sdma event registers (smevr, lmevr),? for more information. table 45-17. port a dedicated pin assignment (ppara = 1) (continued) pin pin function psora = 0 psora = 1 pdira = 1 (output) pdira = 0 (input) default input pdira = 1 (output) pdira = 0 (input, or i/o if specified) default input 4 datasheet u .com
parallel i/o ports MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 45-21 table 45-18 shows the port b pin assignments. table 45-18. port b dedicated pin assignment (pparb = 1) pin pin function psorb = 0 psorb = 1 pdirb = 1 (output) pdirb = 0 (input) default input pdirb = 1 (output) pdirb = 0 (input or i/o if specified) default input pb31 fcc2: tx_er mii fcc2: rxsoc utopia gnd pb30 fcc2: txsoc utopia fcc2: rx_dv mii fcc2: crs_dv rmii gnd gnd pb29 fcc2: rxclav utopia slave fcc2: rxclav utopia master fcc2: tx_en mii/rmii gnd pb28 fcc2: rts fcc2: rx_er mii/rmii gnd scc1: txd tdm_c2: l1tsync/grant gnd pb27 fcc2: txd[0] utopia 8 fcc2: col mii gnd tdm_b2: l1txd i/o gnd pb26 fcc2: txd[1] utopia 8 fcc2: crs mii gnd tdm_b2: l1rxd i/o gnd pb25 fcc2: txd[4] utopia 8 fcc2: txd[3] mii/hdlc nibble tdm_b2: l1tsync/grant gnd pb24 fcc2: txd[5] utopia 8 fcc2: txd[2] mii/hdlc nibble tdm_b2: l1rsync gnd pb23 fcc2: txd[6] utopia fcc2: txd[1] mii/hdlc nibble fcc2: txd[1] rmii dibit gnd pb22 fcc2: txd[7] utopia fcc2: txd[0] mii/hdlc nibble fcc2: txd[0] rmii dibit fcc2: txd hdlc/transp. serial gnd 4 datasheet u .com
parallel i/o ports MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 45-22 freescale semiconductor table 45-19 shows the port c pin assignments. pb21 fcc2: rxd[7] utopia 8 fcc2: rxd[0] mii/hdlc nibble fcc2: rxd[0] rmii dibit fcc2: rxd hdlc/transp. serial gnd gnd pb20 fcc2: rxd[6] utopia 8 fcc2: rxd[1] mii/hdlc nibble fcc2: rxd[1] rmii dibit gnd gnd pb19 fcc2: rxd[5] utopia 8 fcc2: rxd[2] mii/hdlc nibble gnd tdm_b2: l1rq pb18 fcc2: rxd[4] utopia 8 fcc2: rxd[3] mii/hdlc nibble gnd tdm_b2: l1clko table 45-19. port c dedicated pin assignment (pparc = 1) pin pin function psorc = 0 psorc = 1 pdirc = 1 (output) pdirc = 0 (input) default input pdirc = 1 (output) pdirc = 0 (input or i/o if specified) default input pc29 brg2: brgo clk3/tin2 clk7 fcc2: txaddr[4] mphy, master scc1: cts gnd pc28 timer2: tout clk4/tin1 clk8 spi: spiclk1 i/o (secondary option) gnd pc27 timer1: tout clk5 gnd brg3: brgo fcc1: rxprty utopia (secondary option) gnd table 45-18. port b dedicated pin assignment (pparb = 1) (continued) pin pin function psorb = 0 psorb = 1 pdirb = 1 (output) pdirb = 0 (input) default input pdirb = 1 (output) pdirb = 0 (input or i/o if specified) default input 4 datasheet u .com
parallel i/o ports MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 45-23 pc26 timer3: tout clk6 gnd fcc2: rxaddr[4] mphy, master brgo1 pc25 clk7/tin4 gnd brg4: brgo spi: spisel 1 (secondary option) vdd pc24 brg1: brgo clk8/tin3 gnd timer4: tout gnd pc23 brg5: brgo clk9 clk13 fcc2: txaddr[3] mphy, master scc1: cd gnd pc22 fcc1: txprty utopia clk10 clk14 pc21 brg6: brgo clk11 clk15 gnd pc20 usb: oe clk12 clk16 fcc2: rxaddr[3] mphy, master pc19 brg7: brgo clk13 gnd fcc2: txaddr[2] mphy, master (secondary option) timer1/2: tgate1 gnd pc18 clk14 gnd timer3/4: tgate2 gnd pc17 brg8: brgo clk15 gnd fcc2: txaddr[0] mphy, master fcc2: txaddr[0] mphy, slave vdd pc16 clk16 gnd fcc2: rxaddr[0] mphy, master fcc2: rxaddr[0] mphy, slave pc15 scc1: cts by pc29 fcc1: txaddr[0] mphy, master fcc1: txaddr[0] mphy, slave gnd pc14 scc1: cd by pc23 fcc1: rxaddr[0] mphy, master fcc1: rxaddr[0] mphy, slave gnd pc13 brg5: brgo fcc1: txaddr[1] mphy, master fcc1: txaddr[1] mphy, slave gnd pc12 vdd fcc1: rxaddr[1] mphy, master fcc1: rxaddr[1] mphy, slave gnd pc11 scc3: cts usb: rp (primary option) by pc8 fcc2: txaddr[1] mphy, master fcc2: txaddr[1] mphy, slave pc10 scc3: cd t usb: rn gnd fcc2: rxaddr[2] mphy, master table 45-19. port c dedicated pin assignment (pparc = 1) (continued) pin pin function psorc = 0 psorc = 1 pdirc = 1 (output) pdirc = 0 (input) default input pdirc = 1 (output) pdirc = 0 (input or i/o if specified) default input 4 datasheet u .com
parallel i/o ports MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 45-24 freescale semiconductor table 45-20 shows the port d pin assignments. pc9 scc4: cts gnd fcc2: txaddr[2] mphy, master (primary option) tdm_a2: l1tsync/grant gnd pc8 scc1: rts scc4: cd gnd si2: l1st1 strobe scc3: cts 1 gnd pc7 fcc1: cts gnd fcc1: txaddr[2] mphy master, multiplexed: polling fcc1: txaddr[2] mphy, slave, multiplexed polling fcc1: txclav1 mphy, master, direct polling gnd pc6 si2: l1st2 strobe fcc1: cd gnd fcc1: rxaddr[2] mphy, master, multiplexed polling fcc1: rxaddr[2] mphy, slave, multiplexed polling) fcc1: rxclav1 mphy, master, direct polling gnd pc5 smc1: smtxd si2: l1st3 strobe fcc2: cts gnd pc4 fcc2: txprty utopia smc1: smrxd gnd si2: l1st4 strobe fcc2: cd gnd pc1 brg6: brgo fcc2: rxprty utopia gnd tdm_a2: l1rq tdm_c2: l1rsync gnd pc0 brg7: brgo gnd tdm_a2: l1clko smc1: smsyn gnd table 45-20. port d dedicated pin assignment (ppard = 1) pin pin function psord = 0 psord = 1 pdird = 1 (output) pdird = 0 (input) default input pdird = 1 (output) pdird = 0 ( input, or i/o if specified) default input pd31 fcc2: txd[3] utopia 8 scc1: rxd gnd vdd pd30 fcc2: txenb utopia master fcc2: txenb utopia slave scc1: txd table 45-19. port c dedicated pin assignment (pparc = 1) (continued) pin pin function psorc = 0 psorc = 1 pdirc = 1 (output) pdirc = 0 (input) default input pdirc = 1 (output) pdirc = 0 (input or i/o if specified) default input 4 datasheet u .com
parallel i/o ports MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor 45-25 pd29 scc1: rts fcc1: rxaddr[3] mphy, master, multiplexed polling fcc1: rxaddr[3] mphy, slave, multiplexed polling fcc1: rxclav2 mphy, master, direct polling gnd pd25 fcc2: txclav utopia, slave scc3: rx/ usb: rxd gnd fcc2: txclav utopia, master pd24 scc3: txd/ usb: tn fcc2: rxenb utopia, master fcc2: rxenb utopia, slave pd23 scc3: rts usb: tp fcc2: rxaddr[1] mphy, master fcc2: rxaddr[1] mphy, slave pd22 fcc2: txd[2] utopia 8 scc4: rxd gnd tdm_a2: l1txd i/o gnd pd21 scc4: txd fcc2: rxd[3] utopia 8 tdm_a2: l1rxd i/o gnd pd20 scc4: rts fcc2: rxd[2] utopia 8 tdm_a2: l1rsync gnd pd19 fcc1: txaddr[4] mphy, master, multiplexed polling fcc1: txaddr[4] mphy, slave, multiplexed polling fcc1: txclav3 mphy, master, direct polling gnd brg1: brgo spi: spisel (primary option) pc25 pd18 fcc1: rxaddr[4] mphy, master, multiplexed polling fcc1: rxaddr[4] mphy, slave, multiplexed polling fcc1: rxclav3 mphy, master, direct polling gnd spi: spiclk i/o (primary option) pc28 pd17 brg2: brgo fcc1: rxprty utopia (primary option) pc27 spi: spimosi i/o vdd pd16 fcc1: txprty utopia spi: spimiso i/o spimo si pd15 tdm_c2: l1rq fcc2: rxd[1] utopia 8 i2c: i2csda i/o vdd table 45-20. port d dedicated pin assignment (ppard = 1) (continued) pin pin function psord = 0 psord = 1 pdird = 1 (output) pdird = 0 (input) default input pdird = 1 (output) pdird = 0 ( input, or i/o if specified) default input 4 datasheet u .com
parallel i/o ports MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 45-26 freescale semiconductor 45.6 interrupts from port c the port c lines associated with cd x and cts x have a mode of operation wher e the pin can be internally connected to the scc/fcc but can also generate in terrupts. port c still de tects changes on the cts and cd pins and asserts the corresponding interrupt reque st, but the scc/fcc simultaneously uses cts and/or cd to automatically control opera tion. this lets the user fully implement protocols v.24, x.21, and x.21 bis (with the assistance of other general-purpose i/o lines). to configure a port c pin as a cts or cd pin that connects to the scc/f cc and generates interrupts, these steps should be followed: 1. write the corresponding pparc bit with a 1 and psorc bit with 0. 2. write the corresponding pdirc bit with a zero. 3. set the siexr bit (in the interrupt controll er) to determine which edges cause interrupts. 4. write the corresponding simr (mas k register) bit with a 1 to allow interrupts to be generated to the core. 5. the pin value can be read at any time using pdatc. note after connecting cts or cd to the scc/fcc, the us er must also choose the normal operation mode in gsmr[diag] to enable and disable scc/fcc transmission and recepti on with these pins. pd14 tdm_c2: l1clko fcc2: rxd[0] utopia 8 i2c: i2cscl i/o gnd pd7 smc2: smsyn gnd fcc1: txaddr[3] mphy, master, multiplexed polling fcc1: txaddr[3] mphy, slave, multiplexed polling fcc1: txclav2 mphy, master, direct polling gnd table 45-20. port d dedicated pin assignment (ppard = 1) (continued) pin pin function psord = 0 psord = 1 pdird = 1 (output) pdird = 0 (input) default input pdird = 1 (output) pdird = 0 ( input, or i/o if specified) default input 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor a-1 appendix a mpc8541e this appendix describes the featur es of the mpc8541e, how it differ s from the MPC8555E, and provides additional material and specifics fo r using this reference manual for th e mpc8541e. it is intended to be used in conjunction with the mpc8541e powerquicc? iii inte grated processor hardware specifications (mpc8541eec). a.1 mpc8541e overview figure a-1 shows the major functional units within the mpc8541e. figure a-1. mpc8541e block diagram i 2 c controller local bus controller 64/32b pci controller 0/32b pci controller dma controller 10/100/1000 mac 10/100/1000 mac mii, gmii, tbi, rtbi, rgmiis serial dma rom i-memory dpram risc engine parallel i/o baud rate generators timers fcc fcc spi i2c serial interfaces miis/rmiis i/os cpm ddr sdram controller cpm controller interrupt 256 kbyte l2 cache/ sram e500 core 32-kbyte l1 i cache 32-kbyte l1 d cache core complex e500 coherency module ocean irqs sdram ddr gpio 32b programmable interrupt controller bus duart security engine 4 datasheet u .com
mpc8541e MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 a-2 freescale semiconductor a.1.1 key features the following lists an overview of the mpc8541e feature set. ? embedded e500 core ? high-performance, 32-bit core that impl ements the embedded category of the power architecture technology ? dual-issue superscalar, 7-stage pipeline design ? 32-kbyte l1 instruction cache and 32-kbyt e l1 data cache with parity protection ? lockable l1 caches?entire cache or on a per-line basis ? separate locking for instructions and data ? single-precisi on floating-point operations ? memory management unit especially designed for embedded applications ? enhanced hardware and software debug support ? dynamic power management ? performance monitor facility ? integrated security engine (sec) the sec is optimized to handle all the algorithms associated with ipsec, ssl/tls, srtp, 802.11i standard, iscsi, and ike proce ssing. the sec contains four crypt o channels, a controller, and a set of crypto execution units (e us). the execution units are: ? public key execution unit (pkeu) supporting the following: ? rsa and diffie-hellman ? programmable field size up to 2048 bits ? elliptic curve cryptography ? f2m and f(p) modes ? programmable field size up to 511 bits ? data encryption standa rd execution unit (deu) ? des, 3des ? two key (k1, k2) or three key (k1, k2, k3) ? ecb and cbc modes for both des and 3des ? advanced encryption standard execution unit (aesu) ? implements the rijndael symmetric-key cipher ? key lengths of 128, 192, and 256 bits ? ecb, cbc, ccm, and counter modes ? arc four execution unit (afeu) ? implements a stream cipher comp atible with the rc4 algorithm ? 40- to 128-bit programmable key ? message digest execution unit (mdeu) ? sha with 160- or 256-bit message digest ? md5 with 128-bit message digest 4 datasheet u .com
mpc8541e MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor a-3 ? hmac with either algorithm ? random number generator (rng) ? four crypto channels, each supporti ng multi-command descriptor chains ? static and/or dynamic assignmen t of crypto execution units th rough an integrated controller ? buffer size of 256 bytes for each execution unit, with flow control for large data sizes ? high-performance risc cpm ? two full-duplex fast communications controllers (fccs) that support th e following protocol: ? ieee802.3 standard/fast ethernet (10/100) ? serial peripheral interface (spi ) support for master or slave ?i 2 c bus controller ? general-purpose parallel ports?16 parallel i/o lines with interrupt capability ? 256 kbytes of on-chip memory ? can act as a 256-k byte level 2 cache ? can act as a 256-kbyte or two 128- kbyte memory-mapped sram arrays ? can be partitioned into 128-k byte l2 cache plus 128-kbyte sram ? full ecc support on a 64-bit bounda ry in both cache and sram modes ? sram operation supports reloca tion and is byte-accessible ? cache mode supports instructi on caching, data caching, or both ? external masters can force data to be allo cated into the cache through programmed memory ranges or special transaction types (stashing) ? eight-way set-associative cache organi zation (1024 sets of 32-byte cache lines) ? supports locking the entire cache or selected lines ? individual line locks set and cleared through instructions or by externally mastered transactions ? global locking and flash clearing done thr ough writes to l2 configuration registers ? instruction and data locks ca n be flash cleared separately ? read and write buffering for internal bus accesses ? address translation and mapping unit (atmu) ? eight local access windows define mappi ng within local 32-bit address space ? inbound and outbound atmus map to larger external address spaces ? three inbound windows plus a c onfiguration window on pci ? four outbound windows plus default translation for pci ? ddr memory controller ? programmable timing supporti ng first generation ddr sdram ? 64-bit data interface, up to 333-mhz data rate ? four banks of memory supported, each up to 1 gbyte 4 datasheet u .com
mpc8541e MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 a-4 freescale semiconductor ? dram chip configurations from 64 mb its to 1 gbit with x8/x16 data ports ? full ecc support ? page mode support (up to 16 simultaneous open pages) ? contiguous or discontiguous memory mapping ? sleep mode support for self refresh ddr sdram ? supports auto refreshing ? on-the-fly power manage ment using cke signal ? registered dimm support ? fast memory access through jtag port ? 2.5-v sstl2 compatible i/o ? programmable interrupt controller (pic) ? programming model is compliant with the openpic architecture ? supports 16 programmable interrupt a nd processor task priority levels ? supports 12 discrete external interrupts ? supports 4 message interrupts with 32-bit messages ? supports connection of an external interrupt controller such as the 8259 programmable interrupt controller ? four global high resolution timers/count ers that can generate interrupts ? supports additional internal interrupt sources ? supports fully nested interrupt delivery ? interrupts can be routed to exte rnal pin for external processing ? interrupts can be routed to the e500 core ?s standard or critical interrupt inputs ? interrupt summary registers allow fa st identification of interrupt source ?two i 2 c controllers (one is c ontained within the cpm, the other is a stand-alone controller which is not part of the cpm) ? two-wire interface ? multiple master support ? master or slave i 2 c mode support ? on-chip digital filtering rejects spikes on the bus ? boot sequencer ? optionally loads configuration data from se rial rom at reset thro ugh the stand-alone i 2 c interface ? can be used to initialize conf iguration registers and/or memory ? supports extended i 2 c addressing mode ? data integrity checked with preamble signature and crc 4 datasheet u .com
mpc8541e MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor a-5 ? duart ? two 4-wire interfaces (rxd, txd, rts , cts ) ? programming model compat ible with the origin al 16450 uart and the pc16550d ? local bus controller (lbc) ? multiplexed 32-bit address and data operating at up to 166 mhz ? eight chip selects support eight external slaves ? up to eight-beat burst transfers ? the 32-, 16-, and 8-bit port sizes are cont rolled by an on-chip memory controller. ? three protocol engines availabl e on a per chip select basis: ? general-purpose chip select machine (gpcm) ? three user-programmable machines (upms) ? dedicated single-data-rate sdram controller ? parity support ? default boot rom chip select with co nfigurable bus width (8, 16, or 32 bits) ? two three-speed (10/100/1000) ethernet controllers (tsecs) ? dual ieee 802.3, 802.3u, 802.3x, 802.3z, 802.3ac standard compliant controllers ? support for ethernet physical interfaces: ? 10/100/1000 mbps ieee 802.3 standard gmii ? 10/100 mbps ieee 802.3 standard mii ? 10 mbps ieee 802.3 standard mii ? 1000 mbps ieee 802.3z standard tbi ? 10/100/1000 mbps rgmii/rtbi ? full- and half-duplex support ? buffer descriptors are backward comp atible with mpc8260 and mpc860t 10/100 programming models ? 9.6-kbyte jumbo frame support ? rmon statistics support ? 2-kbyte internal transmit and receive fifos ? mii management interface for control and status ? programmable crc ge neration and checking ? ocean switch fabric ? three-port crossbar packet switch ? reorders packets from a source based on priorities ? reorders packets to bypass blocked packets 4 datasheet u .com
mpc8541e MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 a-6 freescale semiconductor ? implements starvation avoidance algorithms ? supports packets with pa yloads of up to 256 bytes ? integrated dma controller ? four-channel controller ? all channels accessible by bot h local and remote masters ? extended dma functions (advanced chaining and striding capability) ? support for scatter and gather transfers ? misaligned transfer capability ? interrupt on completed segm ent, link, list, and error ? supports transfers to or from any local memory or i/o port ? selectable hardware-enfor ced coherency (snoop/no-snoop) ? ability to start and flow control each dma channel from external 3-pin interface ? ability to launch dma from single write transaction ?pci controllers ? pci 2.2 compatible ? one 64-bit or two 32-bit pci ports supported at 16 to 66 mhz ? host and agent mode support, 64- bit pci port can be host or agen t, if two 32-bit ports, only one can be an agent ? 64-bit dual address cycle (dac) support ? supports pci-to-memory and memory-to-pci streaming ? memory prefetching of pci read accesses ? supports posting of processor-to -pci and pci-to -memory writes ? pci 3.3-v compatible ? selectable hardware-enforced coherency ? selectable clock source (sys clk or independent pci_clk) ? power management ? fully static 1.2-v cmos de sign with 3.3- and 2.5-v i/o ? supports power save mode s: doze, nap, and sleep ? employs dynamic power management ? selectable clock source (sys clk or independent pci_clk) ? system performance monitor ? supports eight 32-bit counters that count the occurrence of selected events ? ability to count up to 512 counter-specific events ? supports 64 reference events that can be counted on any of the 8 counters ? supports duration and quant ity threshold counting 4 datasheet u .com
mpc8541e MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor a-7 ? burstiness feature that permits counting of burst events with a programmable time between bursts ? triggering and chaining capability ? ability to generate an interrupt on overflow ? system access port ? uses jtag interface and a tap controller to access entire system memory map ? supports 32-bit accesses to configuration registers ? supports cache-line burst accesses to main memory ? supports large block (4-kbyte) uploads and downloads ? supports continuous bit stre aming of entire block for fast upload and download ? ieee 1149.1 compliant, jtag boundary scan ? 783-pin fc-pbga package the mpc8541e is pin compatible and functionally identical to the MPC8555E except for a reduced protocol set supported and lack of tdm (time division mult iplexers) within the cpm. figure a-2 shows the major functional units of the mpc8541e cpm. the following list summarizes the major cpm features of the mpc854 1e in relation to the MPC8555E: ? the communications processor (cp) is an embedded 32-bit risc c ontroller residing on a separate bus (cpm local bus). with this separate bus, th e cp does not affect the performance of the e500 core. the cp handles the lower-la yer tasks and dma cont rol activities, leaving the e500 core free to handle higher-layer activities. the cp has an instruction set optimized for communications, but that can also be used for general-purpose applicat ions, relieving the system core of small, often repeated tasks. this is functiona lly identical with the MPC8555E. ? two serial dmas (sdmas), one associated with the local bus and one as sociated with the e500 coherency module (ecm), handling transfers simultaneously. this is functionally identical with the MPC8555E. ? two full-duplex, serial fast communications cont rollers (fccs) supporting fa st ethernet. this is functionally identical to the MPC8555E, howev er, the MPC8555E fccs also support atm and hdlc protocols. ? one full-duplex serial peripheral interface (s pi) providing a synchronou s, character-oriented channel that supports a four-wire interface for communication with other microprocessors, peripheral devices such as eepro ms, real-time clocks, a/d convert ers, and isdn devices. this is functionally identical with the MPC8555E. ?i 2 c bus controller providing communication with other i 2 c capable devices. there are two i 2 c controllers on the mpc8541e, this one in the cpm and a separate stand-alone i 2 c controller as well. this is functionally identical with the MPC8555E. 4 datasheet u .com
mpc8541e MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 a-8 freescale semiconductor figure a-2. mpc8541e cpm block diagram a.2 how to use this book for the mpc8541e by using the following mpc8 541e cpm memory map (see table a-1 ) and mpc8541e parallel i/o ports tables (beginning with table a-2 ), and by ignoring those protocols in this reference manual that are not available in the mpc8541e, this reference manua l is directly applic able to the mpc8541e. baud rate generators system bus 2 fccs i 2 c 4 timers parallel i/o ports bus interface sdma dual-port ram communications rom internal bus peripheral bus cpm interrupt controller local bus cpm int processor spi serial interface (si) 4 datasheet u .com
mpc8541e MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor a-9 a.2.1 mpc8541e cpm memory map table a-1 shows the cpm portion of the internal memory map. table a-1. mpc8541e internal memory map address (offset) register access reset section/page cpm dual-port ram 0x8_0000? 0x8_1fff dpram1?dual-port ram r/w ? 21.4/21-28 0x8_2000? 0x8_7fff reserved ? ? ? 0x8_8000? 0x8_9fff dpram2?dual-port ram r/w ? 21.4/21-28 0x8_a000? 0x8_ffff reserved ? ? ? e500 core interface 0x9_0000 cear?cpm error address register r 0x0000_0000 21.2.3.1.1/21-18 0x9_0004 ceer?cpm error event register r/w 0x0000 21.2.3.1.2/21-19 0x9_0006 cemr?cpm error mask register r/w 0x0000 21.2.3.1.3/21-20 sdma 0x9_0050 smaer?system bus address error register r 0x0000_0000 27.1.1/27-2 0x9_0054 reserved ? ? ? 0x9_0058 smevr?system bus event register r/w 0x0000_0000 27.1.2/27-2 0x9_005c smctr?system bus control register r/w 0x3800_0000 27.1.3/27-3 0x9_0060 lmaer?local bus address error register r 0x0000_0000 27.1.1/27-2 0x9_0064 reserved ? ? ? 0x9_0068 lmevr?local bus event register r/w 0x0000_0000 27.1.2/27-2 0x9_006c lmctr?local bus control register r/w 0x3800_0000 27.1.3/27-3 interrupt controller 0x9_0c00 sicr?cpm interrupt configuration register r/w 0x0000_0000 22.5.1.1/22-9 0x9_0c02 reserved ? ? ? 0x9_0c04 sivec?cpm interrupt vector register r/w 0x0000_0000 22.5.1.5/22-14 0x9_0c08 sipnr_h?cpm interrupt pending register (high) r/w 0x0000_0000 22.5.1.3/22-11 0x9_0c0c sipnr_l?cpm interrupt pending register (low) r/w 0x0000_0000 22.5.1.3/22-11 0x9_0c10 reserved ? ? ? 0x9_0c14 scprr_h?cpm interrupt priority register (high) r/w 0x0530_9770 22.5.1.2/22-10 4 datasheet u .com
mpc8541e MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 a-10 freescale semiconductor 0x9_0c18 scprr_l?cpm interrupt priority register (low) r/w 0x0530_9770 22.5.1.2/22-10 0x9_0c1c simr_h?cpm interrupt mask register (high) r/w 0x0000_0000 22.5.1.4/22-12 0x9_0c20 simr_l?cpm interrupt mask register (low) r/w 0x0000_0000 22.5.1.4/22-12 0x9_0c24 siexr?cpm external interrupt control register r/w 0x0000_0000 22.5.1.6/22-15 0x9_0c28? 0x9_0c7f reserved ? ? ? clock 0x9_0c80 sccr?system clock control register r/w 0x0000_0000 25.1/25-2 input/output port 0x9_0d00 pdira?port a data direction register r/w 0x0000_0000 45.2.2.2/45-5 0x9_0d04 ppara?port a pin assignment register r/w 0x0000_0000 45.2.4/45-10 0x9_0d08 psora?port a special options register r/w 0x0000_0000 45.2.5/45-13 0x9_0d0c podra?port a open drain register r/w 0x0000_0000 45.2.1/45-1 0x9_0d10 pdata?port a data register r/w 0x0000_0000 45.2.2/45-4 0x9_0d14? 0x9_0d1f reserved ? ? ? 0x9_0d20 pdirb?port b data direction register r/w 0x0000_0000 45.2.2.2/45-5 0x9_0d24 pparb?port b pin assignment register r/w 0x0000_0000 45.2.4/45-10 0x9_0d28 psorb?port b special options register r/w 0x0000_0000 45.2.5/45-13 0x9_0d2c podrb?port b open drain register r/w 0x0000_0000 45.2.1/45-1 0x9_0d30 pdatb?port b data register r/w 0x0000_0000 45.2.2/45-4 0x9_0d34? 0x9_0d3f reserved ? ? ? 0x9_0d40 pdirc?port c data direction register r/w 0x0000_0000 45.2.2.2/45-5 0x9_0d44 pparc?port c pin assignment register r/w 0x0000_0000 45.2.4/45-10 0x9_0d48 psorc?port c special options register r/w 0x0000_0000 45.2.5/45-13 0x9_0d4c podrc?port c open drain register r/w 0x0000_0000 45.2.1/45-1 0x9_0d50 pdatc?port c data register r/w 0x0000_0000 45.2.2/45-4 0x9_0d54? 0x9_0d5f reserved ? ? ? 0x9_0d60 pdird?port d data direction register r/w 0x0000_0000 45.2.2.2/45-5 0x9_0d64 ppard?port d pin assignment register r/w 0x0000_0000 45.2.4/45-10 0x9_0d68 psord?port d special options register r/w 0x0000_0000 45.2.5/45-13 table a-1. mpc8541e internal memory map (continued) address (offset) register access reset section/page 4 datasheet u .com
mpc8541e MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor a-11 0x9_0d6c podrd?port d open drain register r/w 0x0000_0000 45.2.1/45-1 0x9_0d70 pdatd?port d data register r/w 0x0000_0000 45.2.2/45-4 cpm timers 0x9_0d80 tgcr1?timer 1 and timer 2 global configuration register r/w 0x00 26.2.2/26-3 0x9_0d81 reserved ? ? ? 0x9_0d84 tgcr2?timer 3 and timer 4 global configuration register r/w 0x00 26.2.2/26-3 0x9_0d85? 0x9_0d8f reserved ? ? ? 0x9_0d90 tmr1?timer 1 mode register r/w 0x0000 26.2.3/26-5 0x9_0d92 tmr2?timer 2 mode register r/w 0x0000 26.2.3/26-5 0x9_0d94 trr1?timer 1 reference register r/w 0x0000 26.2.4/26-7 0x9_0d96 trr2?timer 2 reference register r/w 0x0000 26.2.4/26-7 0x9_0d98 tcr1?timer 1 capture register r/w 0x0000 26.2.5/26-7 0x9_0d9a tcr2?timer 2 capture register r/w 0x0000 26.2.5/26-7 0x9_0d9c tcn1?timer 1 counter r/w 0x0000 26.2.6/26-7 0x9_0d9e tcn2?timer 2 counter r/w 0x0000 26.2.6/26-7 0x9_0da0 tmr3?timer 3 mode register r/w 0x0000 26.2.3/26-5 0x9_0da2 tmr4?timer 4 mode register r/w 0x0000 26.2.3/26-5 0x9_0da4 trr3?timer 3 reference register r/w 0x0000 26.2.4/26-7 0x9_0da6 trr4?timer 4 reference register r/w 0x0000 26.2.4/26-7 0x9_0da8 tcr3?timer 3 capture register r/w 0x0000 26.2.5/26-7 0x9_0daa tcr4?timer 4 capture register r/w 0x0000 26.2.5/26-7 0x9_0dac tcn3?timer 3 counter r/w 0x0000 26.2.6/26-7 0x9_0dae tcn4?timer 4 counter r/w 0x0000 26.2.6/26-7 0x9_0db0 ter1?timer 1 event register r/w 0x0000 26.2.7/26-8 0x9_0db2 ter2?timer 2 event register r/w 0x0000 26.2.7/26-8 0x9_0db4 ter3?timer 3 event register r/w 0x0000 26.2.7/26-8 0x9_0db6 ter4?timer 4 event register r/w 0x0000 26.2.7/26-8 0x9_0db8? 0x9_12ff reserved ? ? ? fcc1 0x9_1300 gfmr1?fcc1 general mode register r/w 0x0000_0000 37.2/37-3 table a-1. mpc8541e internal memory map (continued) address (offset) register access reset section/page 4 datasheet u .com
mpc8541e MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 a-12 freescale semiconductor 0x9_1304 fpsmr1?fcc1 protocol-specific mode register r/w 0x0000_0000 (ethernet) 40.18.2/40-20 0x9_1308 ftodr1?fcc1 transmit on demand register r/w 0x0000 37.6/37-8 0x9_130a reserved ? ? ? 0x9_130c fdsr1?fcc1 data synchronization register r/w 0x7e7e 37.5/37-7 0x9_130e reserved ? ? ? 0x9_1310 fcce1?fcc1 event register r/w 0x0000_0000 (ethernet) 40.18.3/40-22 0x9_1312 reserved ? ? ? 0x9_1314 fccm1?fcc1 mask register r/w 0x0000_0000 (ethernet) 40.18.3/40-22 0x9_1316? 0x9_131f reserved ? ? ? fcc2 0x9_1320 gfmr2?fcc2 general mode register r/w 0x0000_0000 37.2/37-3 0x9_1324 fpsmr2?fcc2 protocol-specific mode register r/w 0x0000_0000 (ethernet) 40.18.2/40-20 0x9_1328 ftodr2?fcc2 transmit on -demand register r/w 0x0000 37.6/37-8 0x9_132a reserved ? ? ? 0x9_132c fdsr2?fcc2 data synchronization register r/w 0x7e7e 37.5/37-7 0x9_132e reserved ? ? ? 0x9_1330 fcce2?fcc2 event register r/w 0x0000_0000 (ethernet) 40.18.3/40-22 0x9_1332 reserved ? ? ? 0x9_1334 fccm2?fcc2 mask register r/w 0x0000_0000 (ethernet) 40.18.3/40-22 0x9_1336? 0x9_138c reserved ? 0x00 ? fcc1 (continued) 0x9_1390 gfemr1?general fcc1 expansion mode register r/w 0x00 37.3/37-7 0x9_1391? 0x9_13af reserved ? ? ? fcc2 (continued) 0x9_13b0 gfemr2?general fcc2 ex pansion mode register r/w 0x00 37.3/37-7 table a-1. mpc8541e internal memory map (continued) address (offset) register access reset section/page 4 datasheet u .com
mpc8541e MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor a-13 0x9_13b1? 0x9_15ef reserved ? ? ? brgs 5?8 0x9_15f0 brgc5?brg5 configuration register r/w 0x0000_0000 25.2/25-3 0x9_15f4 brgc6?brg6 configuration register r/w 0x0000_0000 25.2/25-3 0x9_15f8 brgc7?brg7 configuration register r/w 0x0000_0000 25.2/25-3 0x9_15fc brgc8?brg8 configuration register r/w 0x0000_0000 25.2/25-3 0x9_1600? 0x9_185f reserved ? ? ? i 2 c 0x9_1860 i2mod?i 2 c mode register r/w 0x00 44.4.1/44-6 0x9_1861 reserved ? ? ? 0x9_1864 i2add?i 2 c address register r/w 0x00 44.4.2/44-7 0x9_1865 reserved ? ? ? 0x9_1868 ii2brg?i 2 c brg register r/w 0x00 44.4.3/44-7 0x9_1869 reserved ? ? ? 0x9_186c i2com?i 2 c command register r/w 0x00 44.4.5/44-8 0x9_186d reserved ? ? ? 0x9_1870 i2cer?i 2 c event register r/w 0x00 44.4.4/44-7 0x9_1871 reserved ? ? ? 0x9_1874 i2cmr?i 2 c mask register r/w 0x00 44.4.4/44-7 0x9_1875? 0x9_19bf reserved ? ? ? communications processor 0x9_19c0 cpcr?communications processor command register r/w 0x0000_0000 21.3.1/21-24 0x9_19c4 rccr?cp configuration register r/w 0x0000_0000 21.2.6/21-22 0x9_19c8? 0x9_19d5 reserved ? ? ? 0x9_19d6 rter?cp timers event register r/w 0x0000 21.5.4/21-35 0x9_19da rtmr?cp timers mask register r/w 0x0000 21.5.4/21-35 0x9_19dc rtscr?cp time-stamp timer control register r/w 0x0000 21.2.7/21-23 0x9_19de reserved ? ? ? 0x9_19e0 rtsr?cp time-stamp register r/w 0x0000_0000 21.2.8/21-24 table a-1. mpc8541e internal memory map (continued) address (offset) register access reset section/page 4 datasheet u .com
mpc8541e MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 a-14 freescale semiconductor brgs 1?4 0x9_19f0 brgc1?brg1 configuration register r/w 0x0000_0000 25.2/25-3 0x9_19f4 brgc2?brg2 configuration register r/w 0x0000_0000 25.2/25-3 0x9_19f8 brgc3?brg3 configuration register r/w 0x0000_0000 25.2/25-3 0x9_19fc brgc4?brg4 configuration register r/w 0x0000_0000 25.2/25-3 0x9_1a00? 0x9_1a9f reserved ? ? ? spi 0x9_1aa0 spmode?spi mode register r/w 0x0000 43.4.1/43-6 0x9_1aa2 reserved ? ? ? 0x9_1aa6 spie?spi even t register r/w 0x00 43.4.2/43-9 0x9_1aa7 reserved ? ? ? 0x9_1aaa spim?spi mask register r/w 0x00 43.4.2/43-9 0x9_1aab reserved ? ? ? 0x9_1aad spcom?spi command register w 0x00 43.4.3/43-10 0x9_1aa7? 0x9_1b00 reserved ? ? ? cpm mux 0x9_1b02 cmxsi2cr?cpm mux si2 cl ock route register r/w 0x00 24.4.2/24-8 0x9_1b03 reserved ? ? ? 0x9_1b04 cmxfcr?cpm mux fcc clock route register r/w 0x0000_0000 24.4.3/24-8 0x9_1b08? 0x9_1b46 reserved ? ? ? si2 registers 0x9_1b48 si2gmr?si2 global mode register r/w 0x00 23.6.1/23-14 0x9_1b49 reserved ? ? ? 0x9_1b4a si2cmdr?si2 command register r/w 0x00 23.6.4/23-20 0x9_1b4b reserved ? ? ? 0x9_1b4c si2str?si2 status register r/w 0x00 23.6.5/23-21 0x9_1b4d reserved ? ? ? 0x9_1b4e si2rsr?si2 ram shadow address register r/w 0x0000 23.6.3/23-20 0x9_1b50? 0x9_1fff reserved ? ? ? table a-1. mpc8541e internal memory map (continued) address (offset) register access reset section/page 4 datasheet u .com
mpc8541e MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor a-15 a.2.2 mpc8541e parallel i/o port pin assignments the functional design of the mpc8541e parallel i/o ports is identical to the MPC8555E. however, as stated previously, the protocols supported by each device differ, and th e mpc8541e does not support tdms. the following mpc8541e parall el i/o pin assignments are direct replacement tables for those given for the MPC8555E, in section 45.5, ?port tables.? table a-2 shows the mpc8541e port a pin assignments. si2 ram 0x9_2800? 0x9_29ff si2txram?si 2 transmit routing ram ? ? 23.5.3/23-9 0x9_2a00? 0x9_2bff reserved ? ? ? 0x9_2c00? 0x9_2dff si2rxram?si 2 receive routing ram ? ? 23.5.3/23-9 0x9_2e00? 0x9_3fff reserved ? ? ? instruction ram 0xa_0000? 0xa_0fff dual-port ram (instruction ram only) ? ? 21.4/21-28 table a-2. port a dedicated pin assignment (ppara = 1) pin pin function psora = 0 psora = 1 pdira = 1 (output) pdira = 0 (input) default input pdira = 1 (output) pdira = 0 (input, or i/o if specified) default input pa 3 1 g n d fcc1: col mii gnd pa 3 0 g n d fcc1: crs mii gnd pa 2 9 fcc1: tx_er mii pa 2 8 g n d fcc1: tx_en mii/rmii pa 2 7 g n d fcc1: rx_dv mii fcc1: crs_dv rmii gnd pa 2 6 g n d fcc1: rx_er mii/rmii gnd table a-1. mpc8541e internal memory map (continued) address (offset) register access reset section/page 4 datasheet u .com
mpc8541e MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 a-16 freescale semiconductor pa25 msnum[0] 1 pa24 msnum[1] 1 pa 2 3 pa 2 2 pa 2 1 fcc1: txd[3] mii nibble pa 2 0 fcc1: txd[2] mii nibble pa 1 9 fcc1: txd[1] mii nibble fcc1: txd[1] rmii dibit pa 1 8 fcc1: txd[0] mii nibble fcc1: txd[0] rmii dibit pa 1 7 fcc1: rxd[0] mii nibble fcc1: rxd[0] rmii dibit gnd pa 1 6 fcc1: rxd[1] mii nibble fcc1: rxd[1] rmii dibit gnd pa 1 5 fcc1: rxd[2] mii nibble gnd pa 1 4 fcc1: rxd[3] mii nibble gnd pa13 gnd msnum[2] 1 pa12 gnd msnum[3] 1 pa11 gnd msnum[4] 1 pa10 gnd msnum[5] 1 pa 9 pa 8 g n d 1 msnum[0?5] is the sub-block code of the peripheral controller using sdma; msnum[5 ] indicates which section, transmit or receive, is active during the transfer. see section 27.1.2, ?sdma event registers (smevr, lmevr).? table a-2. port a dedicated pin assignment (ppara = 1) (continued) pin pin function psora = 0 psora = 1 pdira = 1 (output) pdira = 0 (input) default input pdira = 1 (output) pdira = 0 (input, or i/o if specified) default input 4 datasheet u .com
mpc8541e MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor a-17 table a-3 shows the mpc8541e port b pin assignments. table a-3. port b dedicated pin assignment (pparb = 1) pin pin function psorb = 0 psorb = 1 pdirb = 1 (output) pdirb = 0 (input) default input pdirb = 1 (output) pdirb = 0 (input or i/o if specified) default input pb31 fcc2: tx_er mii gnd pb30 fcc2: rx_dv mii fcc2: crs_dv rmii gnd gnd pb29 fcc2: tx_en mii/rmii gnd pb28 fcc2: rx_er mii/rmii gnd gnd pb27 fcc2: col mii gnd gnd pb26 fcc2: crs mii gnd gnd pb25 fcc2: txd[3] mii nibble gnd pb24 fcc2: txd[2] mii nibble gnd pb23 fcc2: txd[1] mii nibble fcc2: txd[1] rmii dibit gnd pb22 fcc2: txd[0] mii nibble fcc2: txd[0] rmii dibit gnd pb21 fcc2: rxd[0] mii nibble fcc2: rxd[0] rmii dibit gnd gnd pb20 fcc2: rxd[1] mii nibble fcc2: rxd[1] rmii dibit gnd gnd pb19 fcc2: rxd[2] mii nibble gnd pb18 fcc2: rxd[3] mii nibble gnd 4 datasheet u .com
mpc8541e MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 a-18 freescale semiconductor table a-4 shows the mpc8541e port c pin assignments. table a-4. port c dedicated pin assignment (pparc = 1) pin pin function psorc = 0 psorc = 1 pdirc = 1 (output) pdirc = 0 (input) default input pdirc = 1 (output) pdirc = 0 (input or i/o if specified) default input pc29 brg2: brgo clk3/tin2 clk7 gnd pc28 timer2: tout clk4/tin1 clk8 spi: spiclk1 i/o (secondary option) gnd pc27 timer1: tout clk5 gnd brg3: brgo gnd pc26 timer3: tout clk6 gnd brgo1 pc25 clk7/tin4 gnd brg4: brgo spi: spisel 1 (secondary option) vdd pc24 brg1: brgo clk8/tin3 gnd timer4: tout gnd pc23 brg5: brgo clk9 clk13 gnd pc22 clk10 clk14 pc21 brg6: brgo clk11 clk15 gnd pc20 clk12 clk16 pc19 brg7: brgo clk13 gnd timer1/2: tgate1 gnd pc18 clk14 gnd timer3/4: tgate2 gnd pc17 brg8: brgo clk15 gnd vdd pc16 clk16 gnd pc15 by pc29 gnd pc14 by pc23 gnd pc13 brg5: brgo gnd pc12 vdd gnd pc11 by pc8 pc10 gnd pc9 gnd gnd pc8 gnd si2: l1st1 strobe gnd pc7 gnd gnd pc6 si2: l1st2 strobe gnd gnd 4 datasheet u .com
mpc8541e MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor a-19 table a-5 shows the mpc8541e port d pin assignments. pc5 si2: l1st3 strobe gnd pc4 gnd si2: l1st4 strobe gnd pc1 brg6: brgo gnd gnd pc0 brg7: brgo gnd gnd table a-5. port d dedicated pin assignment (ppard = 1) pin pin function psord = 0 psord = 1 pdird = 1 (output) pdird = 0 (input) default input pdird = 1 (output) pdird = 0 ( input, or i/o if specified) default input pd31 gnd vdd pd30 pd29 gnd pd25 gnd pd24 pd23 pd22 gnd gnd pd21 gnd pd20 gnd pd19 gnd brg1: brgo spi: spisel (primary option) pc25 pd18 gnd spi: spiclk i/o (primary option) pc28 pd17 brg2: brgo pc27 spi: spimosi i/o vdd pd16 spi: spimiso i/o spimosi table a-4. port c dedicated pin assignment (pparc = 1) (continued) pin pin function psorc = 0 psorc = 1 pdirc = 1 (output) pdirc = 0 (input) default input pdirc = 1 (output) pdirc = 0 (input or i/o if specified) default input 4 datasheet u .com
mpc8541e MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 a-20 freescale semiconductor a.2.3 chapter advisory for the mpc8541e the following chapters in this manual do not apply to the mpc8541e and should be ignored: ? chapters 28?33 , concerning sccs ? chapter 34, ?quicc multi-channel controller (qmc)? ? chapter 35, ?universal serial bus controller? ? chapter 36, ?serial manageme nt controllers (smcs)? ? chapters 38 and 39 , concerning fcc protocols not supported on the mpc8541e ? chapters 41 and 42 , concerning atm, which is not supported on the mpc8541e the following chapters refer to implemen tation that differs from the mpc8541e: ? chapter 23, ?serial interface with time-slot assigner? ?there are no time-slot assigners on the mpc8541e, so references to them should be ignored. also, all materi al concerning serial protocols not implemented on the mp c8541e should be ignored. ? chapter 24, ?cpm multiplexing? ?all material concerning serial protocols not implemented on the mpc8541e should be ignored. ? chapter 37, ?fast communications controllers (fccs)? ?the only protocol supported on the mpc8541e fccs is fast ethernet. references to all other protocols in this chapter should be ignored. users may find that chapter 40, ?cpm fast ethernet controller,? contains everything needed to implement fast ethernet on the fccs. pd15 i2c: i2csda i/o vdd pd14 i2c: i2cscl i/o gnd pd7 gnd gnd table a-5. port d dedicated pin assignment (ppard = 1) (continued) pin pin function psord = 0 psord = 1 pdird = 1 (output) pdird = 0 (input) default input pdird = 1 (output) pdird = 0 ( input, or i/o if specified) default input 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor b-1 appendix b revision history this appendix provides a list of the major differences between the MPC8555E powerquicc? iii integrated processor reference manual , revision 0 through revision 2 . b.1 changes from revision 1 to revision 2 major changes to the MPC8555E powerquicc? iii integr ated processor reference manual , from revision 1 to revision 2 are as follows: section, page changes book updated references to powerpc, book e, aim, eis, etc. technology. chapter 1, 1-1 replace all the paragraphs on page 1-1 with the following: freescale semiconductor's mpc 8555e powerquicc? iii integrat ed communications processor includes a wide range of adva nced freescale technologies, m odular cores, and peripherals. leveraging freescale's system-o n-chip (soc) powerquicc iii platform architecture, the MPC8555E combines the powerful book e e500 co re and communications peripheral technology to balance processor performanc e with i/o system th roughput. the processor is designed to offer clock speeds scaling from 533 mhz to 1 ghz. this chapter provides a high-level description of feat ures and functionality of the MPC8555E and mpc8541e integrated communications processors. it is written from the perspective of the MPC8555E, which is the superset device. for specifics on how to use this manual for the mpc8541e, see appendix a, ?mpc8541e.? 1.1 introduction freescale's MPC8555E device integrates two pr ocessing blocks: a high-performance e500 core that implements the power archite cture? definition of the book e instruction-set architecture and a risc-based communications processor modu le (cpm) that supports a wide range of communications peripherals. th is innovative architecture is designed to reduce power consumption and offer a more balanced appro ach to processing than traditional processor architectures. the cpm offloads low-level pe ripheral communications tasks, enabling the embedded e500 core to manage high-level processing tasks. the MPC8555E device's high level of integration helps simplify board de sign and enhances system-level bandwidth and performance. in addition to the e500 core and cpm, the MPC8555E f eatures an integrated security engine, a double data rate sdram (ddr sdram) memory contro ller, dual gigabit ethernet controllers, a four-channel dma controller, dual asynchronous receiver/transmitt ers (duart), and a 64-bit pci controller that can also serve as two 32-bit pci ports. dual on-chip pci support provides a cost-effective alternative to separate, discre te pci bridges and chipsets for i/o-intensive 4 datasheet u .com
revision history MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 b-2 freescale semiconductor applications that require multip le pci interfaces. in addition to these features, the MPC8555E provides a local bus controller and i 2 c support. the MPC8555E processor features a security engine that supports des, 3des, md-5, sha-1, aes, and arc-4 encryption algorithms, as well as offering a public key accelerator and on-chip random number generator. this em bedded security core is deri ved from freescal e's security coprocessor product line and of fers the same direct-memory acce ss (dma) and para llel processing capabilities, as well as the ability to perform single-pass encryption and authentication as required by widely used security protocols, such as ipsec and 802.11i. integrated security makes the MPC8555E an optimal communications processor solution for applicat ions that require security features in concert with high perf ormance and low system-level cost. 1.3.1, 1-10 replace the second bullet with the following: ? implements additional instructions, regi sters, and interrupts defined by apus. the spe provides an extensive instruct ion set for 64-bit vector integer, single-precision floating-point, and fractional operations. the spfp apu provides scalar (32-bit) single-prec ision floating-point instructions. note the spe apu and spfp apu functi onality will be implemented in all powerquicc iii devices. ho wever, these instructions will not be supported in devices subs equent to powerquicc iii. freescale strongly recommends that use of these instructions be confined to libraries and device drivers. customer software that uses spe or spfp apu instructions at the assembly level or that uses spe intrinsics will re quire rewriting for upward compatibility with next-gen eration powerquicc devices. freescale offers a libcfsl_e 500 library that uses spe apu instructions. freescale will also provide libraries to support next-generation po werquicc devices. 1.3.3, 1-16 in the first bullet, replace th e first sentence with the following: two full-duplex, serial fast communica tions controllers (fccs) supporting atm (155 mbps) protocol through two utopia level ii interfaces. 2.2.3.2, 2-6 in figure 2-2, the bit field ends at 15, this should be changed to 31. 2.3.1, 2-10 insert the following new secti on 2.3.1 and, subsequently, renumber existing sections. 2.3.1 accessing ccsr memory from the e500 core when the local e500 processor is used to c onfigure ccsr space, the ccsr memory space should typically be marked as cache-inhibited and guarded. in addition, many configuration registers af fect accesses to other memory regions; therefore, writes to these registers must be guaranteed to have taken effect before accesses are made to the associated memory regions. 4 datasheet u .com
revision history MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor b-3 to guarantee that the results of any sequence of writes to configuration registers are in effect, the final configuration re gister write should be chased by a read of the same register, and that should be followed by a sync instruction. then, acce sses can safely be made to memory regions affected by the configuration register write. 2.4, 2-56 in table 2-9, replace the offset 0xe_0000 row with the following: 3.1, 3-1 in figure 3-1, lsdamux is incorrectl y shown muxed with lgpl5. there is no lsdamux signal; lgpl5 should appear by itself. 3.2, 3-16 in table 3-3, lsdamux is incorrec tly shown muxed with lgpl5. there is no lsdamux signal; lgpl5 should appear by itself. 4.4.2, 4-10 correct the first sentence of the note associated with se quence step four to read as follows: if the jtag signals are not used, trst may be tied active; however, it is recommended that trst not remain asserted after negation of hreset . modify the second paragraph of the note as follows: there is no need to assert the sreset signal when hreset is asserted. if sreset is asserted on negation of hreset , the por sequence will be paused after the e500 core pll is locked and be fore the e500 reset is negated. the por sequence will be resumed when s reset is negated. 4.4.3, 4-11 replace the second paragraph with the following: all por configuration signals have internal pull-up resistor s so that if the desired setting is high, there is no need fo r a pull-up resistor on the board. 4.4.3.10, 4-18 replace the third sentence with the following: note that the value latched on this si gnal during por is accessible through the memory-mapped pordevsr (por devi ce status register) described in section 18.4.1.1, ?por pll status register (porpllsr).? 5.1.1, 5-3 replace the second paragraph of the note with the following: freescale semiconductor offers a libcfsl_e 500 library that uses spe instructions. freescale will also provide libraries to support ne xt-generation powerquicc devices. 5.2, 5-5 replace table 5-1 with the following: 5.6, 5-18 in figure 5-6, remove dvc1 and dvc2 registers. 0xe_0000 porpllsr?por pll ratio status register r 0x00 nn _ n 1 nn 18.4.1.1/18-4 MPC8555E revision core revision processor version register (pvr) system version register (svr) 1.1 2.0 0x8020_0020 0x8079-0011 (MPC8555E) 0x8071-0011 (mpc8555) 0x807a-0011 (mpc8541e) 0x8072-0011 (mpc8541) 4 datasheet u .com
revision history MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 b-4 freescale semiconductor 5-14, 5-32 in table 5-8, replace the last two se ntences in the descri ption of spe and spfp apus with the following: freescale offers a libcfsl_ e500 library that uses spe apu instructi ons. freescale will also provide libraries to suppor t next-generation po werquicc devices. in table 5-8, the description of hid1 fields should appear as follows: 6.1.1, 6-2 in figure 6-1, remove dvc1 and dvc2 registers. 6.5.4, 6-14 in figure 6-9, correct the system versi on register reset value to read as follows: 0x8079_0011 (for MPC8555E) / 0x807a_0011 (for mpc8541e) 0x8071_0011 (for mpc8555) / 0x8072_0011 (for mpc8541) 6.7.2.4, 6-22 remove mcsr[47] (gl_ci) from fi gure 6-26 and table 6-12. this bit is not supported. hid1 implementation pll_mode. set to 01 pll_cfg. powerquicc iii devices support the following: 0001_00 ratio of 2:1 0001_01 ratio of 5:2 (2.5:1) 0001_10 ratio of 3:1 0001_11 ratio of 7:2 (3.5:1) nexen, r1dpe, r2dpe, mpxtt, mshars, sshar, ats, and mid are not implemented on powerquicc iii devices, abe must be set to ensure that cache and tlb management instructions operate properly on the l2 cache. please refer to the description of hid1[rfxe] in sect ion 6.10.2, ?hardware implem entation-dependent register 1 (hid1).? if rfxe is 0, conditions t hat cause the assertion of core_fault_in cannot directly cause the e500 to generate a machine check; however, powerquicc iii devices must be configured to detect and enable such conditions. the following describes how error bits should be configured: ? ecm mapping errors: eeer[laee] mu st be set. see section 8.2.1.4, ?e cm error enable register (eeer).? ? l2 multiple-bit ecc errors: l2errdis[mbeccdis] must be cleared to ensure that error can be detected. l2errinten[mbeccinten] must be set. see section 7.3.1.5, ?l2 error registers.? ? ddr multiple-bit ecc errors. err_disable[mbed] and err_int_en[mbee] must be zero and ddr_sdram_cfg[ecc_en] must be one to ensure that an interrupt is generated. see section 9.4.1, ?register descriptions.? ? pci. the appropriate parity detect and master-abort bits in err_dr must be cleared and the corresponding enable bits in err_en must be set to ensure that an interrupt is generated. ? local bus controller parity errors. ltedr[pard] must be cleared and lteir[pari] mu st be set to ensure that an parity errors can generate an interrupt. see sectio n 13.3.1.11, ?transfer error check disable register (ltedr),? and section 13.3.1.12, ?transfer e rror interrupt enable register (lteir).? 4 datasheet u .com
revision history MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor b-5 6.10.2, 6-26 please replace the descri ption of hid1[rfxe] in table 6-19 with the following: 6.13.1.1, 6-42 in table 6-32, change the following dbcr0[rst] 1x description to read as follows: 1x causes a hard reset if msr[de] and dbcr0[idm] ar e set. always cleared on subsequent cycle. this causes a hard reset to the core only. 7.3.1.5.2, 7-16 in figure 7-17, ?l2 er ror detect register (l2errd et),? bit 0, mull2err, is incorrectly shown as read only. the field should be w1c, like the other fields in this register. 9.4.1.7, 9-16 in table 9-12, the description for re fint, change the reference in the last sentence to section 18.5.1.5.3. table 6-19. hid1 field descriptions bits name description 46 rfxe read fault exception enable. enables the core to internally generate a machine check interrupt when core_fault_in is asserted. depending on the value of msr[me], this result s in either a machine check interrupt or a checkstop. 0 assertion of core_fault_in cannot cause a machine check. the core do es not execute any instructions from a faulty instruction fetch and does not execute any load in structions that get their data from a faulty data fetch. on the e500v2, if these instructions are eventually requ ired by the sequential programming model (that is, they are not in a speculative execution path), the e500v2 sta lls until an asynchronous inte rrupt is taken. the e500v1 does not stall when faulty instructions or data are received, as described in the following note. note: the e500v1 does not stall when faulty instructions or da ta are received. instead, it continues processing with faulty instructions or data. the only reliable way to prev ent such behavior is to set rfxe, which causes a machine check before the faulty instructions or data are used. to avoi d the use of faulty instructions or data and to have good error determination, software must set rfxe and program th e pic to interrupt the processor when errors occur. as a result, software must deal with multiple in terrupts for the same fundamental problem. 1 assertion of core_fault_in causes a machine check if msr[me] = 1 or a checkstop if msr[me] = 0. the core_fault_in signal is asserted to the core when logic outside of the core has a problem delivering good data to the core. for example, the front-side l2 cache asserts core_fault_in when an ecc error occurs and ecc is enabled. as a second example, it is asserted when t here is a master abort on a pci transaction. see ?proper reporting of bus faults,? in the core complex bus chapter of the powerpc e500 core family reference manual . the rfxe bit provides flexibility in error recovery. typically, devices outside of the core have some way other than the assertion of core_fault_in to signal the core that an error occurred. usually, this is done by channeling interrupt requests through a programmable inte rrupt controller (pic) to the core. in these cases, the assertion of core_fault_in is used only to prevent the core from using bad data bef ore receiving an interrupt from the pic (for example, an external or critical input interrupt). possible combin ations of rfxe and pic configuration are as follows: ? rfxe = 0 and the pic is configured to interrupt the processor. in this configuration, the assertion of core_fault_in does not trigger a machine check interrupt. the core does not use the faulty instruct ions or data and may stall. the pic interrupts the core so that error recovery can beg in. this configuration allows the core to query the pic and the rest of the system for more information about t he cause of the interrupt, and generally provides the best error recovery capabilities. ? rfxe = 1 and the pic is not configured to interrupt th e processor. this configuration provides quick error detection without the overhead of config uring the pic. when the pic is not configured, setting rfxe avoids stalling the core when core_fault_in is asserted. determination of the root cause of the problem may be somewhat more difficult than it would be if the pic were enabled. ? rfxe = 1 and the pic is configured to interrupt the processor. in this conf iguration, the core may receive two interrupts for the same fundamental error. the two interr upts may occur in any order, which may complicate error handling. therefore, this is usually not an interesting configuration for a single-core device. this may, however, be an interesting configuration for multi-core devices in which the pic may steer interrupts to a processor other than the one that attempted to fetch the faulty data. ? rfxe = 0 and the pic is not configured to interrupt the processor. this is not a re commended configuration. the processor may stall indefinitely due to an unreported error. 4 datasheet u .com
revision history MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 b-6 freescale semiconductor 9.4.1.8, 9-16 add the following note after the first paragraph: note the ddr_sdram_clk_cntl[ss_en] default value out of reset is 0 and this must be set to a 1 for proper operation. 10.1.3, 10-4 in table 10-1, change the description for the second bulleted item of the reset core interrupt type to read as follows: ? core_hreset_req. internal signal to the device, output from core, input to the platform?caused by writing to the co re dbcr0[rst]. th is condition is additionally qualified with msr[de] and dbcr0[idm] bits. note that assertion of this si gnal causes a hard reset of the core only. 10.2.2, 10-8 in table 10-5, remove the sentence, ?t he timing requirements for edge-sensitive interrupts can be found in the MPC8555E powerquicc? iii integrated processor hardware specifications .? that timing is not pr ovided in the hardware specifications. 11.3.1.2, 11-6 correct the following i2cfdr[fdr] va lues (scl clock fre quency divider ratios) in table 11-5 (all other fdr va lue definitions remain unchanged): fdr: divider (decimal): fdr: divider (decimal): 0x00 384 0x20 256 0x01 416 0x21 288 0x02 480 0x22 320 0x03 576 0x23 352 0x04 640 0x24 384 0x05 704 0x25 448 0x06 832 0x26 512 0x07 1024 0x27 576 11.4.1.2, 11-12 replace the last sentence of the first paragraph with the following: an i 2 c device cannot be master and slave at th e same time; if this is attempted, the results are boundedly undefined. 11.4.5, 11-17 add the following after the fi rst sentence in the first paragraph: the boot sequencer accesses the i 2 c serial rom at an interface frequency designated by the default value of the i2cfdr[fdr] field, 0x2c, which corresponds to a divider of 1280. see section 11.3.2.1, ?i 2 c frequency divider register (i2cfdr),? for addi tional details of the i2cfdr. 4 datasheet u .com
revision history MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor b-7 12.3.1.3, 12-7 table 12-8, and the text that introduces it, should be replaced with the following: table 12-8 shows baud rate when the i nput clock is at certain frequencie s. note that because only integer values can be used as divisors, the actual baud rate differs sl ightly from the desired (target) baud rate; for this reason, both target and actual baud rates are given, along with the percentage of error. also in this section, the te xt between table 12-8 and the end of the section should be removed. 13.1.2, 13-2 correct the first sub-bullet under primar y bullet, ?memory cont roller with eight memory banks? to read as follows: ? 32-bit address decoding with mask 13.3.1.2.1, 13-12 correct the first two sentences of the first paragraph to read as follows: the address mask field of the option registers (or n [am]) mask up to 17 corresponding br n [ba] fields. the 15 lsbs of th e 32-bit internal address do not participate in bank address matchi ng in selecting a bank for access. 13.3.1.2.1, 13-12 remove the left-most column of table 13-5. 13.3.1.10, 13-25 in the second paragraph, add the follow ing sentence to the end of the paragraph: note that lteatr[v] bit has to be clear ed to register subsequent errors in ltesr. table 12-8. baud rate examples target baud rate (decimal) divisor input clock (ccb) frequency (mhz) actual baud rate (decimal) percent error (decimal) decimal hex 9,600 1736 6c8 266 9600.61444 0.0064 19,200 868 364 266 19,201.22888 0.0064 38,400 434 1b2 266 38,402.45776 0.0064 56,000 298 12a 266 55,928.41163 0.1280 128,000 130 82 266 128,205.12821 0.1600 256,000 65 41 266 256,410.25641 0.1600 9,600 2170 87a 333 9600.61444 0.0064 19,200 1085 43d 333 19,201.22888 0.0064 38,400 543 21f 333 38,367.09638 0.0858 56,000 372 174 333 56,003.58423 0.0064 128,000 163 a3 333 127,811.86094 0.1472 256,000 81 51 333 257,201.64609 0.4672 9,600 3472 d90 533 9600.61444 0.0064 19,200 1736 6c8 533 19,201.22888 0.0064 38,400 868 364 533 38,402.45776 0.0064 56,000 595 253 533 56,022.40896 0.0400 128,000 260 104 533 128,205.12821 0.1600 256,000 130 82 533 256,410.25641 0.1600 4 datasheet u .com
revision history MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 b-8 freescale semiconductor 13.3.1.13, 13-28 replace the last sentence of th e first paragraph with the following: after lteatr[v] has been set, software must clear this bit to allow lbc error registers to update follow ing any subsequent errors. 13.3.1.13, 13-28 in figure 13-16 and ta ble 13-19, remove register fi eld lteatr[xa] and change bits 28?29 to be ?reserved?. 13.3.1.14, 13-29 in table 13-20, correct the ltear[a] field description to read as follows: transaction address for the error. hold s the 32-bit address of the transaction resulting in an error. 13.3.1.16, 13-31 in table 13-22, add the following not e to the description of lcrr[clkdiv]: it is critical that no transactions ar e being executed via the local bus while clkdiv is being modified. as such, prior to modificati on, the user must ensure that code is not executi ng out of the local bus. on ce lcrr[clkdiv] is written, the register should be read, and th en an isync should be executed. 13.4, 13-33 in figure 13-20, correct the label for th e arrow in the upper left corner to read: ?32-bit system address?. 13.4.1.1, 13-33 correct the third sentence of th e first paragraph to read as follows: addresses are decoded by comparing the 17 msbs of the address, masked by or n [am], with the base address for each bank (br n [ba]). 13.4.1.7, 13-37 replace the last sentence of th e first paragraph with the following: setting ltedr[bmd] disables bus m onitor error checking (that is, the ltesr[bm] bit is not set by a bus monito r time-out); however, the bus monitor is still active and can generate a up m exception (as noted in section 13.4.4.1.4, ?exception requests?) or terminate a gpcm access. 13.4.2.2.3, 13-44 the title of figure 13-26 lists the or n timing parameters incorrectly; csnt applies only to write trans actions, ehtr only to reads. the figure is also truncated and shows incorrect timing for lbctl. replace the figure and title with the following: 4 datasheet u .com
revision history MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor b-9 figure 13-26. gpcm relaxed timing read (xacs = 0, acs = 1x, scy = 1, ehtr = 0, trlx = 1) 13.4.2.4, 13-50 in table 13-27, remove fields br0[xba] and or0[xam]. 13.4.3.1, 13-50 replace the last sentence of th e first paragraph with the following: note that address signals a[2:0] of th e sdram connect dir ectly to la[27:29], address signal a10 connects to the lbcs dedicated lsda10 signal, while the remaining address bits (except a 10) are latched from lad[20:26]. 13.4.4.2, 13-65 remove the third paragraph, begi nning with ?note that the upm memory...?. add the following note to the end of this section: note in order to enforce proper ordering be tween updates to the mxmr register and the dummy accesses to the upm memory region, two rules must be followed: 1. since the result of any update to th e mxmr register must be in effect before the dummy read or write to the upm region, a write to mxmr should be followed immedi ately by a read of mxmr. 2. the upm memory region should have the same mmu settings as the memory region containing the mxmr configuration register; both should be mapped by the mmu as c ache-inhibited and guarded. this prevents the e500 core from re-ord ering a read of the upm memory around the read of mxmr. once the programming of the upm array is complete, the mmu setting for the asso ciated address range can be set to the proper mode for nor mal operation, such as cacheable and copyback. 13.5.4.3.3, 13-94 in table 13-39, remove fields br n [xba] and or n [xam]. lclk lad lale lcs n lbctl a latched address ta loe address read data acs = 10 acs = 11 address scy = 1, trlx = 1 4 datasheet u .com
revision history MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 b-10 freescale semiconductor 13.5.4.3.5, 13-95 in table 13-43, remove fields br n [xba] and or n [xam]. 14.2, 14-7 change the fifth element of the second bullet item in the tsec features list to read: ? 10/100 mbps rgmii 14.5.3.2.1, 14-32 in table 14-12, modify the fi fo_pause_ctrl[tfc_pause_en] field description to read as follows: tfc_pause enable. this bit enables the ability to transmit a pause control frame by setting the tctrl[tfc_pause] bit. th is bit is cleared at reset but should always be set during initialization as undefined behavior results during normal operation when left cleared. 0 pause control frame tran smission disabled (default, but must be set during initialization). 1 pause control frame transmission enabled. 14.5.3.9.1, 14-91 in table 14-96, correct attr[elcwt] and attr[bdlwt ] field values of 11 to be ?reserved?. 14.5.4.2, 14-93 in figure 14-100 and tabl e 14-99, correct default reset values of control register fields an enable, full duplex, and speed_1 to all be zero. 14.5.4.6, 14-99 in figure 14-104, correct the reset value of the tbi anex register to be 0000_0000_0000_0100. 14.6.1.1, 14-105 in figure 14-110, superscript the ?1? on the ec_mdc and ecc_mdio lines. 14.6.1.2, 14-106 in figure 14-111, remove tsec n _col signal, since it is not used for a gmii interface. 14.6.1.2, 14-106 in figure 14-111, make the following changes: the third line from the top, ?transmi t nibble data,? should be changed to ?transmit data.? the sixth line from the top, ?tra nsmit clock,? should be removed. the seventh line from the top, ?receive nibble data,? should be changed to ?receive data.? superscript the ?1? on the ec_mdc and ecc_mdio lines. 14.6.1.3, 14-107 in figure 14-112, superscript the ?1? on the ec_mdc and ecc_mdio lines. 14.6.1.4, 14-108 in figure 14-113, superscript the ?1? on the ec_mdc and ecc_mdio lines. 14.6.1.5, 14-109 in figure 14-114, superscript the ?1? on the ec_mdc and ecc_mdio lines. 15.4.1.3, 15-30 add the following para graph after the bulleted list: note that when operating the dma in chai ning mode, the regist er byte count field, bcr[bc], must be initialized to zero before enabling the pause feature. in chaining modes, the channel does not pa use for descriptor fetch transfer. 4 datasheet u .com
revision history MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor b-11 15.4.1.3, 15-30 add the following sentence after th e second sentence of the third paragraph: note, however, that write data for a paus ed transfer may not have reached the target interface when so indicated. 15.5, 15-39 replace figure 15-25 with the following: 16.3.1.3, 16-15 add the following note after the first paragraph: note pci1 and pci2 can also be used as possible target interfaces for pci inbound atmus, mapping from one pci to th e other. however, it is illegal for pci1 to use pci1 as a target, or for pci2 to use pci2 for a target. 16.3.1.2.4, 16-25 in figure 16-9, remove s_d from bit 1. this bit is reserved and should have a value of ?0?. ocean local-dma tdms ddr sdram bus ddr sdram controller dpram i-memory cpm serial interface mphy miis/ i/os fcc fcc scc scc/usb scc smc smc spi i 2 c time slot assigner e500 core l2-cache parallel i/o baud rate generators timers local bus controller system-dma 64/32b pci controller ext dma pins cpm interrupt controller i 2 c dma (4-channel) controller boot sequencer register and control pci bus local bus risc e500 coherency module mcm serial dma open pic duart serial in/out rom rmiis utopia 0/32b pci controller pci bus 10/100/1000 mac 10/100/1000 mac mii, gmii, tbi, rtbi, rgmiis 4 datasheet u .com
revision history MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 b-12 freescale semiconductor 16.3.1.3.4, 16-30 in table 16-14, add the following targets to the piwar n [tgi] field description: 0000 pci1 0001 pci2 16.3.2.3, 16-42 in table 16-26, modified th e description for bit 2 to read: indicates whether this pci controller is c onfigured as a master . for pci1, the reset state of this bit depends on whether pci1 is configured in host mode (bus master = 1) or agent mode (bus master = 0). 0 disables the ability to generate pci accesses 1 enables this pci controller to behave as a pci bus master note that the bus master bi t in the pci bus command regi ster should be set before attempting an outbound configuration access. 16.3.2.17, 16-53 the register described in this sect ion should be called pci bus minimum grant (min gnt) register; its single field is mingnt. (the fi eld description is unchanged.) 16.4.2.8.2, 16-68 replace the following bulleted item: ? the 16-clock latency timer has expire d, and the first data phase has not begun. with: ? the 32-clock latency timer has expire d, and the first data phase has not begun. 16.4.2.11.3, 16-76 replace the second to the last sentence of the first paragraph with the following: when the MPC8555E is in agent lock m ode, it retries all externally-generated pci/x configuration cycles until the ac l bit in the pci bus function register (0x44) is cleared. 16.4.2.11.4, 16-77 in table 16-50, correc t the table h eading from ?ad n used in iidsel? to ?ad n used in idsel?. 16.4.2.11.4, 16-77 in table 16-50, separate entr ies for device number 0 and devices 1?9. add the following table footnote relate d to idsel used for device number 0: 1 no external configuration transaction ta kes place; rather, internal registers are accessed. in addition, insert the following table foot note related to idsel used for device numbers 1?9: 2 no idsel line asserted. type0 configurat ion transaction is run, but ends with a master abort since no device responds. finally, renumber previ ous footnote accordingly. 16.5.1.3, 16-85 insert the following se ntence after the first sentence: the purpose of this mode is to allow in itial configuration on the post by the local processor before opening the port to be further configured by the external host. 16.5.3, 16-85 remove this section, as there is no support for rapidio on this device. 4 datasheet u .com
revision history MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor b-13 17.1, 17-3 replace figure 17-1 with the following: 17.2, 17-11 in table 17-2, the ?offset? values for deu, aesu, and mdeu modules show incorrect ranges. replace the rows with the following: 17.4.2.6, 17-43 in table 17-19, replace the row for bit 61 with the following: 17.4.2.7, 17-45 in table 17-20, replace the row for bit 61 with the following: 17.4.3.2.1, 17-48 in table 17-21, replace the row for bits 53?55 with the following: 0x3_2000?0x3_2fff deu des/3des execut ion unit crypto eu 17.4.2/17-33 0x3_4000?0x3_4fff aesu aes exec ution unit 17.4.6/17-67 0x3_6000?0x3_6fff mdeu message diges t execution unit 17.4.4/17-51 61 ifo input fifo overflow. the deu input fifo has been pushed while full. 0 no error detected 1 input fifo has overflowed note: when operating as a master, the deu implements flow -control, and fifo size is not a limit to data input. when operated as a target, the deu cannot accept fifo inputs larger than 512 bytes without overflowing. 61 ifo input fifo overflow error. the de u input fifo has been pushed while full. 0 input fifo overflow error enabled 1 input fifo overflow error disabled note: when operating as a master, the deu implements flow -control, and fifo size is not a limit to data input. when operated as a target, the deu cannot accept fifo inputs larger than 512 bytes without overflowing. 53?55 burst size the afeu implements flow control to allow la rger than fifo-sized blocks of data to be processed with a single key/context. the afeu si gnals to the channel that burst size amount of data is available to be pushed to or pulled from the fifo. note: the inclusion of this field in the afeumr is to avoid confusing a user who may read this register in debug mode. burst size should not be written directly to the afeu. e500 core e500 security engine (sec) coherency module communications processor module (cpm) ddr memory controller tsec tsec 4 datasheet u .com
revision history MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 b-14 freescale semiconductor 17.4.4.1, 17-57 in table 17-26, replace the row for bits 53?55 with the following: 17.4.5.1, 17-67 replace the fourth sentence in th e first paragraph, with the following: rngmr also reflects the value of bur st size, which is loaded by the crypto-channel during norma l operation with the rng as an initiator. 17.4.5.1, 17-68 in table 17-33, replace the row for bits 53?55 with the following: 17.4.5.4, 17-70 in table 17-35, change bit 62 from ?r eserved? to ?id? and replace the row with the following: 17.4.6.6, 17-80 in table 17-42, replace the row for bit 61 with the following: 17.5.1.2, 17-93?17-94 in tables 17-47 and 17-48, replace th e rows for 0x7 and 0x8 with the following: 17.5.1.2, 17-95 in table 17-49, correct the followi ng crypto-channel state value definitions: 0x16 trans_request_read_multi_eu_in 0x18 trans_request_read 0x1f trans_request_write_snoopout 0x21 trans_request_write 53?55 burst size the mdeu implements flow control to allow la rger than fifo-sized blocks of data to be processed with a single key/context. the mdeu signals to t he channel that a burst size amount of data is available to be pushed to the fifo. note: the inclusion of this field in the mdeumr is to avoid confusing a user who may read this register in debug mode. burst size should not be written directly to the mdeu. 53?55 burst size the rng implements flow control to allow larger than fifo-sized blocks of data to be processed with a single key/context. the rng signals to the cryp to-channel that a burst size amount of data is available to be pulled from the fifo. note: the inclusion of this field in the rngmr is to av oid confusing a user who may read this register in debug mode. burst size should not be written directly to the rng. bits name description 62 id interrupt done. this status bit reflects t he state of the done interrupt signal, as sampled by the controller interrupt status register (section 14.6.2.2, ?interrupt st atus register (isr)?). 0 rng is not signaling done 1 rng is signaling done 61 ifo input fifo overflow. the aesu input fifo has be en pushed while full. 0 no error detected 1 input fifo has overflowed note: when operating as a master, the aesu implements flow-control, and fifo size is not a limit to data input. when operated as a target, the aesu cannot accept fifo inputs larger than 512 bytes without overflowing. 0x7 request_bytes_data_trans 0x8 request_bytes_data_trans_done 4 datasheet u .com
revision history MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor b-15 17.5.1.4, 17-98 replace the fourth paragraph and fifth paragraphs with the following: the fetch address is written into the fi fo only if the write includes the least significant byte (bits 56?63). writing a fetc h address of zero to the fetch fifo causes the channel to generate an error and to stop. the fetch fifo can hold up to 24 descriptor pointers at a time . when the end of the current descriptor is r eached, the descriptor pointed to by the next location in the fetch fifo will be read to launch th e next descriptor. writing a descriptor pointer to the fetch fifo while the fifo is full will result in a single overflow interrupt to advise the user that the desc riptor pointer was not successfully written to the fetch fifo. the channel will con tinue processing and software can check the fetch fifo counter in the crypto-ch annel pointer status register before attempting to re-enqueue the descriptor poi nter. if a second descriptor pointer is written to the fetch fifo before the si ngle overflow error is cleared, the channel will generate a double overflow error in terrupt and stop processing descriptors. the channel can be restarted by setting the continue bit in the crypto-channel configuration register, or completely rese t by writing the reset bit in the same register. 17.6.2.1?17.6.2.3, 17-103?17-105 in figures 17-64, 17-65, and 17-66, ch ange bit 47 to ?reserved?. 17.6.2.5, 17-108 in table 17-56, add the followi ng warning text to the mcr[swr] field description: warning: certain sec interrupts are not fu lly cleared by writing this bit. if sec interrupts are pending, it is recommended th at the user set this bit twice (two consecutive writes) to completely reset the sec. 18.4, 18-4 in table 18-3, replace the offset 0xe_0000 row with the following: 18.4.1.1, 18-5 in table 18-1, change the read (r) value of bits 9, 23, and 25, to 1. 18.4.1.11, 18-15 in figure 18-11 and table 18-14, correct ly document bit field 11 as ?reserved?. 18.4.1.11, 18-16 in table 18-14, correct the last sent ence of the asserted state description for devdisr[e500] to read as follows: instruction fetching is stopped, snooping is disabled, and clocks are shut down to all functional units of the core, including the timer facilities. 18.4.1.15, 18-20 in figure 18-15 and tabl e 18-18, correct the system vers ion register reset value to read: 0x8079_0011 (for MPC8555E) / 0x807a_0011 (for mpc8541e) 0x8071_0011 (for mpc8555) / 0x8072_0011 (for mpc8541) 0xe_0000 porpllsr?por pll ratio status register r 0x00 nn _ n 1 nn 18.4.1.1/18-4 4 datasheet u .com
revision history MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 b-16 freescale semiconductor 18.5.1.6, 18-26 replace the second paragraph with the following: these register fields and their functi onal relationship are shown in section 6.10.1, ?hardware implementation-dependent re gister 0 (hid0),? and section 6.5.1, ?machine state register (msr).? the e500 reference manual has details on accessing these power management control bits. 18.5.1.7, 18-28 in figure 18-19, correct the input of the nor gate which dr ives internal signal core_tben, formerly noted as being driv en by ?devdisr[tb]?, to be noted as being driven by ?devdisr[tb] or [e500]?. 19.4.7, 19-22 in table 19-10, insert a centered header row labeled ?tsec1 dma events? directly between rows for events ?recei ve fifo above 3/4? and ?dma reads?. 20.4.1, 20-27 in table 20-26, add target ids for ?pci 2? (with a hex value of 01) and ?security? (with a hex value of 07). 21.1.1, 21-7?21-8 in table 21-1, remove rese rved registers between each fcce n and fccm n at offsets 0x9_1312 and 0x9_1332. 21.1.1, 21-11?21-12 in table 21-1, add reserved registers between each scce n and sccm n at offsets 0x9_1a12, 0x9_1a52, and 0x9_1a72. 21.2.9, 21-24 in table 21-2, replace the row for ?ram base + 0x8af0? with the following: 21.3.1, 21-25?21-26 in figure 21-9, change bits 18?25 fr om ??? to ?mcn,? change bits 26?27 from ??? to ?ep.? in table 21-9, replace the rows for bits 18?25 and 26?27 with the following: 21.4, 21-29 replace the first bullet with the following: ? 4 kbytes of instruction ram to st ore a microcode package of up to 1k instructions 21.4, 21-31 in figure 21-12, replace bd/data in banks #5 and #6 with parameter ram. 21.4.2, 21-33 in table 21-13, change the size of pages 13?16 (address 0x8c00) from 1280 to 1024. ram base + 0x8af0 rev_num hword microcode revision number 0x00e8 18?25 mcn in fcc protocols, this field c ontains the protocol code as follows: 0x00 hdlc 0x0a atm 0x0c ethernet 0x0f transparent 26?27 ep endpoint: logical pipe number (only in usb) 00 endpoint 0 01 endpoint 1 10 endpoint 2 11 endpoint 3 4 datasheet u .com
revision history MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor b-17 24.1, 24-3 after the features li st, add the following note: note in fcc2 utopia master or slav e mode only, clk13, clk14, brg 5, brg6, and brg7 are available. 30.13, 30-19?30-23 in figures 30-10, 30-11, 30-14, and 30-16, change pow er supply voltage from 5 v to 3.3 v. 35.5.1, 35-10 replace the two paragraphs following figure 35-5 and replace table 35-3 with the following sections and table: 35.5.1.1 packet-level interface if usep1[rte] is 0, the usb host controller uses a packet-lev el interface to comm unicate with the user. each transmit packet is prepared in a buf fer and referenced by a txbd as described in section 35.6.3, ?usb transmit buffer descriptor (tx bd) for host.? ea ch receive packet is stored in a buffer referenced by a rxbd as described in section 35.6.1, ?usb rece ive buffer descriptor (rx bd) for host and function.? a setup or out transaction requi res at least two txbds, one for the token and one or more for the data pack et. an in transaction requires one txbd for the token and one or more rxbds for the data packet . tokens are not checked for validity and are transmitted as is. the user is responsible fo r token validity as we ll as crc5 generation. 35.5.1.2 transaction-level interface if usep1[rte] is 1, the usb host controller us es a transaction-level interface to communicate with the user. each transaction uses one trdb as described in section 35.6.4, ?usb transaction buffer descriptor (trbd) for host.? the usb host controller generate s the token based on the tok field in the trbd. for setup and out tran sactions, the trbd points to a single buffer containing the data packet to be transmitted. for in transacti ons, the trbd points to a single buffer which is used for the receive data packet. 4 datasheet u .com
revision history MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 b-18 freescale semiconductor table 35-3. usb tokens token description out packet-level interface tra nsaction-level interface transmission begins when the usb host controller fetches a txbd containing an out token and a data txbd and loads them to the host fifo. the token and data are transmitted and a handshake is expected. if a handshake is not received within the expected time interval, the usb controller clears txbd[r] of data bd, sets the txbd[to] indication and generates a txe1 interrupt. when stall or nak is received within the expected time interval, the usb controller clears txbd[r] of data bd, sets the txbd[stall] or txbd[nak] indication and generates a txe1 interrupt. when ack is received within the expected time interval, the usb controller clears txbd[r] of data bd, and generates an interrupt if txbd[i] = 1. no indication is set. the token txbd[r] is cleared right after the out token transmission. transmission begins when the usb host controller fetches a trbd with the tok field indicating an out transaction. the token is generated and then the data packet from the buffer is transmitted and a handshake is expected. if a handshake is not received within the expected time interval, the usb controller clears trbd[r], sets the trbd[to] indication and generates a txe1 interrupt. when stall or nak is received within the expected time interval, the usb controller clears trbd[r], sets the trbd[stall] or trbd[nak] indication and generates a txe1 interrupt. when ack is received within the expected time interval, the usb controller clears trbd[r], and generates a txb interrupt if trbd[i] = 1.no indication is set. usb out transaction token data handshake received by host indication on txbd/trbd out sent by host none to ack none nak nak stall stall 4 datasheet u .com
revision history MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor b-19 in packet-level interface tra nsaction-level interface transmission begins when the usb host controller fetches a txbd containing an in token and loads the token to fifo. after the in token is transmitted the usb host controller waits for reception of data within expected time interval. on reception of a valid data pid an rxbd is fetched. the received data and data pid are stored in receive fifo. if rxbd[e] is set pid and data will be moved to the buffer. while receiving the data the usb host controller calculates crc16, performs bit un-stuffing. on end of reception calculated crc is compared to received and octet alignment is checked, rxbd[e] is cleared, rxbd[pid] is set according to received data pid and error indications are set if required: rxbd[cr] for failed crc check, rxbd[no] for non-octet sized data and rxbd[ab] if bit stuffing error occurred. if no valid data pid or no data at all received during the expected time interval a to indication in the token txbd is set. transmission begins when the usb host controller fetches a trbd with the tok field indicating an in transaction. after the in token is generated and transmitted, the usb host controller waits for reception of data within the expected time interval. the received data packet is stored in buffer reference by the trbd. while receiving the data the usb host controller calculates crc16 and performs bit un-stuffing. at end of the packet, the calculated crc is compared to the received value and octet alignment is checked, trbd[r] is cleared, trbd[pid] is set accord ing to the received data pid and error indications are set if required: trbd[cr] for failed crc check, trbd[no] for non-octet sized data and trbd[ab] if bit stuffing error occurred. if any of the above errors are reported, trbd[rxer] is also se t, and a txe1 interrupt is generated. if no valid data pid or no data at all received during the expected time interval, a trbd[to] is set and a txe1 interrupt is generated. if no errors occurred and trbd[i] is set, a txb interrupt is generated to indicate successful completion of the transaction. usb in transaction token data transmitted by function handshake generated by host indication on bd in received correctly ack rxbd[e]/trbd[r] is cleared received corrupted none rxbd[cr]/trbd[cr} or rxbd[ab]/trbd[ab] or rxbd[no]/trbd[no] none none txbd[to]/trbd[to] setup the format of setup transactions is similar to out bu t uses a setup rather than an out pid. a setup token is recognized only by a control endpoint. when a setup token is received, setup reception begins. the usb controller fetches the next bd associat ed with the endpoint; if it is empty, t he controller starts transferring the incoming packet to the buffer. when the buffer is full, the usb controller clears rxbd[e] and generates an interrupt if rxbd[i] = 1. if the incomi ng packet is larger than the buffer, the usb controller fetches the next bd and, if it is empty, continues transferring the rest of th e packet to this buffer. the entire data packet including the data0 pid is written to the receive buffers. if the pa cket was received without crc or bit stuff errors, an ack handshake is sent to the host. if an error occurs, no han dshake packet is returned and error status bits are set in the last rxbd associated with this packet. start of frame (sof) when an sof packet is received, the usb controller issu es a sof maskable interrupt and the frame number entry in the parameter ram is updated. preamble (pre) the pre token signals the hub that a low-speed transaction is about to occur. the pre token is read only by the hub. the usb controller ignores the pre token function in function mode. table 35-3. usb tokens (continued) token description 4 datasheet u .com
revision history MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 b-20 freescale semiconductor 35.5.2, 35-12 replace section 35.5.2 with the following: 35.5.2 sof transmission for usb host controller the following section describes the mechanism used by the usb host controller to support the automatic transmission of sof tokens. this mechanism is enabled by setting usmod[sfte]. sof packets should be transmitted every 1 ms. si nce the time interval between two sof packets must be more precise than could be accomplished by software, a hardware timer is used to assert an interrupt to the cp. when the interrupt is se rviced by the cp, it prepar es a sof token and loads it to the host endpoint. once the sof token is loaded to the fifo, it is tr ansmitted like any other packet. before each sof transmission, the software shoul d prepare a value for the frame number and crc5 to be transmitted in sof t oken and place it in the parameter ram (for further details please refer to section 35.5.5, ?frame number (frame_n ).? one possible implementation would be to use the sof interrupt (see sect ion 35.5.7.5, ?usb event register (u sber)?) to prepare the frame number for the next sof packet. the sft interrupt should not be used for this purpose since it is generated before the sof pack et is actually transmitted. the application software shoul d also guarantee that the usb host has completed all pending transactions prior to the 1 ms tick, so that the tran smit fifo is empty at th is point. the current value of the sof timer may be read at any time to synchronize the soft ware with the usb frames. see section 35.5.7.8, ?usb start of frame t imer (ussft)? for more information. 35.5.4, 35-15 in table 35-5, replace the row for offset 0x1e with the following: 35.5.6, 35-17 table 35-8, replace the row for bit 6 with the following: 35.5.7.1, 35-17 in figure 35-11, change bi t 4 from ?reserved? to ?sfte?. in table 35-9, replace the row for bits 2?4 with the following: 0x1e himmr 16 bits when using the transaction-based in terface in host mode, this field must be programmed to {ccsrbar[0:11], 0x9}. otherwise, this field is unused. 6 dtb data bus indicator 0 use system bus for sdma operation 1 use local bus for sdma operation 2?3 ? reserved, should be cleared. 4 sfte start-of-frame timer enable. setting this bit enables the start-of-fra me timer and automatic sof transmission. see section 35.5.7.8, ?usb start of frame timer (ussft),? and section 35.5.2, ?sof transmission for usb host controller,? for more information. 0 sof timer is disabled 1 sof timer is enabled note: when sfte is 1, the pc21 pin cannot be used as cp_int since the cp interrupt is used internally for generating the sof packet. 4 datasheet u .com
revision history MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor b-21 35.5.7.4, 35-20 in figure 35-14, change bits 2 and 3 from ?reserved? to ?isft? and ?dsft?, respectively. in table 35-12, replace the row for bits 2?5 with the following: 35.5.7.5, 35-21 in figure 35-15, change bit 5 from ?reserved? to ?sft?. in table 35-13, replace the row for bits 0?5 with the following: 35.5.7.8, 35-22 insert the following section after secti on 35.5.7.7, and subseque ntly, renumber the tables and figures that follow: 35.5.7.8 usb start of frame timer (ussft) when enabled by usmod[sfte], the ussft contains the current time with in the frame with a resolution of one bit time. when the value of us sft wraps from 11,999 to 0, a cp interrupt is asserted to trigger the transmission of a sof packet, and usber[sft] is set. the ussft may be read at any time. table 35-15 describes ussft fields. 2 isft increment start-of-frame ti me. setting the isft bit incremen ts the start-of-frame time by one. this bit could be used to synchronize the usb frames to an external timing source. 3 dsft decrement start-of-frame time. setting the ds ft bit decrements the start-of-frame time by one. this bit could be used to synchronize the usb frames to an external timing source. 4?5 ? reserved, should be cleared. 0?4 ? reserved, should be cleared. 5 sft the start-of-frame timer (uss ft[sft]) wrapped from 11,999 to 0. 012 15 field ? sft reset 0010_1110_1101_1000 r/w r addr 0x_1b78 figure 35-17. usb start of frame timer (ussft) table 35-15. ussft fields bits name description 0?1 ? reserved, should be cleared. 2?15 sft start-of-frame time. this field contains the number of bit times since the last sof trigger. note that the actual sof transmission occurs slightly later. 4 datasheet u .com
revision history MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 b-22 freescale semiconductor 35.6.1, 35-24 replace the paragraph above figure 35-18 with the following: the rxbd is identical for both the host mode (when using the packet-level interface) and the function mode. there are no rxbds in host mode when using the transaction-level interface. 35.6.3, 35-28 before the first paragra ph, add the following paragraph: the txbd described in this section is us ed when the packet-level interface is active. see section 35.5.1.1, ?packet-leve l interface,? for mo re information. 35.6.3, 35-30 after section 35.6.3, add the following section: 35.6.4 usb transaction buffer descriptor (trbd) for host the trbd described in this section is used when the transaction-level interface is active. see section 35.5.1.2, ?transaction-level in terface,? for more information. data to be transmitted with the usb to the cp by is arranged in buffers referenced by the trbd ring. the first word of the trbd c ontains status and control bits. table 35-18 describes usb trbd fields. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 offset + 0x0 r ? wi ltccnflsppid rxer nak stal to un bov offset + 0x2 data length offset + 0x4 data buffer pointer offset + 0x6 offset + 0x8 tok ? iso ? endp addr offset + 0xa reserved figure 35-20. usb transaction buffer descriptor (trbd) 1,2 1 entries in boldface must be initialized by the user. 2 all fields should be prepared by the user before transmission. table 35-18. usb host trbd fields offset bits name description 0x00 0 r ready 0 the data buffer associated with this bd is not ready for transmission. the user is free to manipulate this bd or its associated data buffer. the cp clears this bit after the buffer has been transmitted or after an error condition is encountered. 1 the data buffer, which has been prepared for transmission by the user, has not been transmitted or is currently being transmitted. no fields of this bd may be written by the user once this bit is set. 1 ? reserved, should be cleared. 4 datasheet u .com
revision history MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor b-23 2 w wrap (final bd in table) 0 this is not the last bd in the trbd table. 1 this is the last bd in the trbd table. after this buffer has been used, the cp will send data using the first bd in the table (the bd pointed to by tbase). the number of trbds in this table is programmable, and is determined only by the trbd[w] and the overall space constraints of the dual-port ram. 3 i interrupt 0 no interrupt is generated after this buffer has been serviced. 1 the txb bit in the event register is set when this buffer is serviced. txb can cause an interrupt if it is enabled. 4 l last this bit should always be 1 since each trbd represents an entire transaction. 5 tc transmit crc. append crc to transmitted data packet. 0 transmit end-of-packet after the last data byte. this setting can be used for testing purposes to send a bad crc after the data. 1 transmit the crc sequence after the last data byte. 6 cnf transmit confirmation. this bit should always be set to 1 to obtain confirmation for each transaction. 7 lsp low-speed transaction. 0 this transaction is with the host or a full-speed device. 1 this transaction is with a low-speed device. transmit a pre packet before the token. 8?9 pid packet id. for out/setup transactions, this field is prepared by the user with the following values: 0x do not append pid to the data packet. 10 transmit data0 pid before sending the data packet. 11 transmit data1 pid before sending the data packet. for in transactions, this field is provided by the usb host controller with the following values: 00 buffer contains data0 packet. 01 buffer contains data1 packet. 10 rxer 1 receive error. this bit indicates that an error was detected while receiving the data packet of an in transaction. if rxer is 1, bits 11?15 have a different meaning as explained below. 11 nak/no 1 rxer = 0: nak received. indicates that the endpoint has responded with a nak handshake (out transaction). the packet was received error-free; however, the endpoint could not accept it. rxer = 1: rx non-octet aligned packet. a pack et that contained a number of bits not exactly divisible by eight was received. written by the usb controller after the received data has been placed into the associated data buffer. 12 stal/ab 1 rxer = 0: stall received. indicates th at the endpoint has responded with a stall handshake (out transaction). the endpoint needs attention through the control pipe. rxer = 1: frame aborted. bit stuff error occu rred during reception. written by the usb controller after the received data has been placed into the associated data buffer. table 35-18. usb host trbd fields (continued) offset bits name description 4 datasheet u .com
revision history MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 b-24 freescale semiconductor 13 to/cr 1 rxer = 0: time out. indica tes that the endpoint failed to acknowledge the token (in transaction) or the data packet (out/setup transaction). rxer = 1: crc error. this frame contains a crc error. the received crc bytes are always written to the receive buffer. written by the usb controller after the received data has been placed into the associated data buffer. 14 un/ov 1 rxer = 0: underrun. indicates that t he usb encountered a transmit fifo underrun condition while sending the data packet (out/setup transaction). rxer = 1: overrun. an internal receive fifo overrun occurred during reception. written by the usb controller after the received data has been placed into the associated data buffer. 15 bov 1 buffer overflow. in transaction s only. indicates that the number of received bytes is larger than the buffer size as provided in the data length field. 0x02 0?15 data length for out/setup transactions, the user prepares th is field with the numb er of bytes to be sent from the data buffer. it will not be modified by the cp. for in transactions, the user prepares this field with the size of the data buffer, which must be divisible by 4. the cp will return the actual number of bytes written to the data buffer. if the number of received bytes, including the 2- byte crc, is larger than the data buffer, the bov bit will be set by the cp. 0x04 0?31 data buffer pointer the data buffer pointer. the buffer may reside in either internal or external memory. for out/setup transactions, this points to the buffer containing the data packet to transmit. it may have any alignment. for in transac tions, this points to the buffer into which the data packet should be received, the pointer must be divisible by 4. 0x08 0?1 tok token type this field determines the type of token to be transmitted and the type of transaction. 00 setup 01 out 10 in 11 reserved 2 ? reserved, should be cleared. 3 iso isochronous this bit indicates that the transaction is isochronous, so no handshake is required. 0 bulk/control/interrupt. the hands hake packet is automatically expected or generated by the usb host controller. 1 isochronous. no handshake packets are expected or generated. this bit actually controls the value that is written to usep1[tm] before processing this transaction. 5 ? reserved, should be cleared. 5?8 endp endpoint this field indicates the endpoint number to be included in the token. 9?15 addr address this field indicates the device address to be included in the token. 0x0a 0?15 ? reserved, should be cleared. 1 written by the usb controller after it finishes sending or receiving the associated data buffer. table 35-18. usb host trbd fields (continued) offset bits name description 4 datasheet u .com
revision history MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor b-25 35.8, 35-31 add the following row to the end of table 35-19: 35.9, 35-31 insert the following sections after section 35.8: 35.9 usb function controller initialization example the following is an example in itialization sequence for the usb controller operating in function mode. it can be used to setup two function endpoints to fill transmit fifos so th at data is ready for transmission when an in token is received from the usb. the toke ns can be generated using a usb traffic generator. 1. program cmxscr to provide a 48 mhz clock to the usb controller. 2. program the port registers to select us brxd, usbrxp, usbrxn, usbtxp, usbtxn, and usboe . 3. clear frame_n. 4. write (dpram+0x500) to ep1ptr, and (dpram +0x520) to ep2ptr to set up the endpoint pointers. 5. write 0xbc80_0004 to dpram+0x20 to set up the txbd[status and control, data length] fields of endpoint 1. 6. write dpram+0x200 to dpram+0x24 to set up the txbd[buffer pointer] field of endpoint 1. 7. write 0xbcc0_0004 to dpram+0x28 to set up the txbd[status and control, data length] fields of endpoint 2. 8. write dpram+0x210 to dpram+0x2c to set up the txbd[buffer pointer] field of endpoint 2. 9. write 0xcafe_cafe to dpram+0x200 to set up the endpoint 1 tx data pattern. 10. write 0xface_face to dpram+0x210 to set up the endpoint 2 tx data pattern. 11. write 0x0000_0020 to dpram+0x500 to set up the rbase and tbase fields of the endpoint 1 parameter ram. 12. write 0x1818_0100 to dpram+0x504 to set up the rfcr, tfcr, and mrbl r fields of the endpoint 1 parameter ram. 13. write 0x0000_0020 to dpram+0x508 to set up the rbp tr and tbptr fields of the endpoint 1 parameter ram. 14. clear the tstate field of the endpoint 1 parameter ram. 15. write 0x0008_0028 to dpram+0x520 to set up th e rbase and tbase fields of the endpoint 2 parameter ram. 16. write 0x1818_0100 to dpram+0x524 to set up the rfcr, tfcr, and mrbl r fields of the endpoint 2 parameter ram. 17. write 0x0008_0028 to dpram+0x528 to set up th e rbptr and tbptr fields of the endpoint 2 parameter ram. buffer overflow for usb host mode packet-level interface only. if the received data packet is larger than the allocated buffer, the remaining data is discarded, and trbd[bov] is set. the txe1 interrupt bit is set. 4 datasheet u .com
revision history MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 b-26 freescale semiconductor 18. clear the tstate field of the endpoint 2 parameter ram. 19. write 0x0000 to usep1: endpoint number 0, cont rol transfer, one packet only, and normal handshake. 20. write 0x7200 to usep2: endpoint number 7, bul k transfer, one packet only, and normal handshake. 21.write 0x00 to the usmod for full-speed 12 mbps function endpoint mode and disable the usb. 22. write 0x05 to the usad for slave address 5. 23. set usmod[en] to enable the usb controller. 24. write 0x80 to uscom to start fi lling the tx fifo with endpoint 1 data ready for transmission when an in token is received. 25. write 0x81 to uscom to start fi lling the tx fifo with endpoint 2 data ready for transmission when an in token is received. 26. generate an in token to a ddress 5, endpoint number 0, control. 27. generate an in token to address 5, endpoint number 7, bulk. 35.10 programming the usb host controller (packet-level) the MPC8555E implementation of a usb host uses the endpoint re presented by usep1 to control the host transmission and recepti on. the other endpoints ar e typically not used, except for testing purposes (loopback). programming the usb contro ller to act as host is similar to configuring an endpoint for function operation. a general outline of how to program the host contro ller follows. (a more detailed example can be found in section 35.10.1, ?usb ho st controller initialization example.?) ? set the host bit in the mode register (usbmo d[host] = 1) to configure the controller as a host. ? set the multi-frame bit in the endpoint confi guration register (usep1 [mf] = 1) to allow setup/out tokens and data0/data1 pa ckets to be sent back-to-back. ? prepare tokens in separate bds. ? using software, append the crc5 as part of the transmitted data be cause the cpm does not support automatic crc5 generation. ? clock the usb host controller as a high speed function (48-mhz reference clock). ? for low-speed transactions with an external hub, set txbd[lsp] in the token?s bd. this causes the usb host controller to genera te a preamble (pre token) at full speed before changing the transmit rate to low speed and sending the data packet. after completion of the transaction, the host returns to full-speed operation. note th at lsp should be set only for token bds. 4 datasheet u .com
revision history MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor b-27 35.10.1 usb host controller initialization example the following is a local loopback example initia lization sequence for the usb controller operating as a host. it can be used to se t up the host endpoint and one functi on endpoint to demonstrate an in token transaction. 1. program cmxscr to provide a 48 mhz clock to the usb controller. 2. program the port registers to select us brxd, usbrxp, usbrxn, usbtxp, usbtxn, and usboe . 3. write (dpram+0x500) to ep1ptr, (dpram+ 0x520) to ep2ptr to set up the endpoint pointers. 4. write 0x0000_0020 to dpram+0x500 to set up the rbase and tbase fields of the host endpoint parameter ram. 5. write 0x1818_0100 to dpram+0x504 to set up the rfcr, tfcr, and mrbl r fields of the host endpoint parameter ram. 6. write 0x0000_0020 to dpram+0x508 to set up the rbptr and tbptr fields of the host endpoint parameter ram. 7. clear the tstate field of th e host endpoint parameter ram. 8. write 0x0008_0028 to dpram+0x520 to set up the rb ase and tbase fields of the endpoint 2 parameter ram. 9. write 0x1818_0100 to dpram+0x524 to set up the rfcr, tfcr, and mrbl r fields of the endpoint 2 parameter ram. 10. write 0x0008_0028 to dpram+0x528 to set up the rbp tr and tbptr fields of the endpoint 2 parameter ram. 11. clear the tstate field of the endpoint 2 parameter ram. 12. write 0xb000_0000 to dpram+0x00 to set up the rxbd[status and control, data length] fields of the host endpoint. 13. write dpram+0x100 to dpram+0x04 to set up the rxbd[buffer pointer] field of the host endpoint. 14. write 0xb800_0003 to dpram+0x20 to set up the tx bd[status and contro l, data length] fields of the host endpoint. 15. write dpram+0x200 to dpram+0x24 to set up the txbd[buffer pointer] field of the host endpoint. 16. write 0xbc80_0003 to dpram+0x28 to set up the txbd[status and control, data length] fields of the function endpoint. 17. write dpram+0x210 to dpram+0x2c to set up the txbd[buffer pointer] field of the function endpoint. 18. write 0x698560 to dpram+0x200 to set up the host endpoint tx data pattern. this pattern consists of the in token and the crc5. 19. write 0xabcd_1234 to dpram+0x210 to set up the function endpoint tx data pattern. 20. write 0x0020 to usep1 for the host: non-isochr onous transfer, multi-packet, packet-level interface. 4 datasheet u .com
revision history MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 b-28 freescale semiconductor 21. write 0x1100 to usep2 for the function: interrupt transfer, one packet only. 22. write 0x06 to usmod for full-speed 12 mbps signaling, local loopback configuration (test and host modes set), and disable the usb. 23. write 0x05 to the usad for slave address 5. 24. set usmod[en] to enable the usb controller. 25. write 0x81 to the uscom to start filling the tx fifo with endpoint 2 data to be ready for transmission when an in token is received. 26. write 0x80 to the uscom to st art transmitting the in token. the expected result s are as follows: ? txbd[status and control] of th e host endpoint should contain 0x3800. ? txbd[data length] of the hos t endpoint should contain 0x0003. ? txbd[status and control] of endpoint 2 should contain 0x3c80. ? txbd[data length] of e ndpoint 2 should contain 0x0003. ? rxbd[status and control] of th e host endpoint should contain 0x3c00. ? rxbd[data length] of the hos t endpoint should contain 0x0005. ? the receive buffer of the host e ndpoint should contain 0xabcd_122b, 0x42xx_xxxx. 35.11 programming the usb host controller (transaction-level) the MPC8555E implementation of a usb host uses the endpoint repr esented by usep1 to control the host transmission a nd reception. the other e ndpoints are typically not used, except for testing purposes (loopback). programming the usb controller to act as host is similar to conf iguring an endpoint for function operation. a general outline of how to program th e host controller follows. (a more detailed example can be found in section 35.11.1, ?usb host controller initialization example.?) ? set the host bit in the mode register (usbmo d[host] = 1) to configure the controller as a host. ? set the multi-frame bit in the endpoint confi guration register (usep1 [mf] = 1) to allow setup/out tokens and data0/data1 pa ckets to be sent back-to-back. ? set usep1[rte] to enable the transaction-level interface. ? clock the usb host controller as a high speed function (48-mhz reference clock). ? for low-speed transactions with an extern al hub, set trbd[lsp]. this causes the usb host controller to generate a preamble (pre token) at full spee d before changing the transmit rate to low speed and sending the token. after comple tion of the transaction, the host returns to full-speed operation. 4 datasheet u .com
revision history MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor b-29 35.11.1 usb host controller initialization example the following is a local loopback example initia lization sequence for the usb controller operating as a host. it can be used to set up the host endpoi nt and one function endpoint to demonstrate an in token transaction. 1. program cmxscr to provide a 48 mhz clock to the usb controller. 2. program the port registers to select us brxd, usbrxp, usbrxn, usbtxp, usbtxn, and usboe . 3. write (dpram+0x500) to ep1ptr, (dpram+ 0x520) to ep2ptr to set up the endpoint pointers. 4. write 0x0020 to dpram+0x502 to set up the tb ase field of the host endpoint parameter ram. 5. write 0x1818 to dpram+0x504 to set up the rfcr and tfcr fields of the host endpoint parameter ram. 6. write 0x0020 to dpram+0x50a to set up the tbptr field of the host endpoint parameter ram. 7. clear the tstate field of th e host endpoint parameter ram. 8. initialize the himmr field of the host endpoint parameter ram. 9. write 0x0008_0028 to dpram+0x520 to set up the rb ase and tbase fields of the endpoint 2 parameter ram. 10. write 0x1818_0100 to dpram+0x524 to set up the rfcr, tfcr, and mrbl r fields of the endpoint 2 parameter ram. 11. write 0x0008_0028 to dpram+0x528 to set up the rbptr and tbptr fiel ds of the endpoint 2 parameter ram. 12. clear the tstate field of the endpoint 2 parameter ram. 13. write 0xb800_0040 to dpram+0x20 to set up the tr bd[status and control, data length] fields of the host endpoint. 14. write dpram+0x100 to dpram+0x24 to set up th e trbd[buffer pointer] field of the host endpoint. 15. write 0x8085 to dpram+0x28 to set up the trbd token fields of the host endpoint. 16. write 0xbc80_0003 to dpram+0x28 to set up the txbd[status and control, data length] fields of the function endpoint. 17. write dpram+0x210 to dpram+0x2c to set up the txbd[buffer pointer] field of the function endpoint. 18. write 0xabcd_1234 to dpram+0x210 to set up the function endpoint tx data pattern. 19. write 0x0030 to usep1 for the host: non-isochronous transfer, multi-pack et, transaction-level interface. 20. write 0x1100 to usep2 for the function: interrupt transfer, one packet only. 21. write 0x06 to usmod for full-speed 12 mbps signaling, local loopback configuration (test and host modes set), and disable the usb. 22. write 0x05 to the usad for slave address 5. 4 datasheet u .com
revision history MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 b-30 freescale semiconductor 23. set usmod[en] to enable the usb controller. 24. write 0x81 to the uscom to start filling the tx fifo with endpoint 2 data to be ready for transmission when an in token is received. 25. write 0x80 to the uscom to st art transmitting the in token. the expected results are as follows: ? trbd[status and control] of th e host endpoint should contain 0x3800. ? trbd[data length] of the host endpoint should contain 0x0005. ? txbd[status and control] of endpoint 2 should contain 0x3c80. ? txbd[data length] of e ndpoint 2 should contain 0x0003. ? the receive buffer of the host e ndpoint should contain 0xabcd_122b, 0x42xx_xxxx. 37.8, 37-12 in table 37-4, replace the rows for offset 0x00 and 0x02 with the following: 41.1, 41-1 change the first bullet to read as follows: full duplex segmentation and reassembly at 155 mbps 41.10.1, 41-38 in table 41-11, replace the rows for offsets 0x40, 0x42, and 0x44 with the following: 41.10.l.3, 41-41 figure 41-24, change bit 2 to read glb. 0x00 riptr hword receive internal temporary data pointer. us ed by microcode as a temporary buffer for data. user to specify only the lowest 16 bits of the dpra m address offset calculated from the value in ccsrbar. must be 32-byte aligned and the size of the internal buffer must be 32 bytes, unless it is stated otherwise in the protocol specification. 0x02 tiptr hword transmit internal temporary data pointer. used by microcode as a temporary buffer for data. user to specify only the lowest 16 bits of the dpra m address offset calculated from the value in ccsrbar. must be 32-byte aligned and the size of the internal buffer must be 32 bytes, unless it is stated otherwise in the protocol specification. 0x40 rcell_tmp_base hword rx cell temporary base address. points to a total of 64 bytes reserved dual-port ram area used by the cp. should be 64-byte aligned. user to specify only the lowest 16 bits of the dpram address o ffset calculated from the value in ccsrbar. 0x42 tcell_tmp_base hword tx cell temporary base address. points to total of 64 bytes reserved dual-port ram area used by the cp. should be 64-byte aligned. user to specify only the lowest 16 bits of the dpram address o ffset calculated from the value in ccsrbar. 0x44 udc_tmp_base hword udc mode only. points to a total of 64 bytes reserved dual-port ram area used by the cp. should be 64-byte aligned. user to specify only the lowest 16 bits of the dpram address offset calculated from the value in ccsrbar. 4 datasheet u .com
revision history MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor b-31 41.10.l.3, 41-41 table 41-13, replace the rows fo r bits 0?5, 6, and 7 with the following: 41.10.2.2, 41-45 table 41-15, replace the rows fo r bits 6 and 7 with the following: 41.10.2.3, 41-52 table 41-20, replace the rows fo r bits 6 and 7 with the following: 41.14, 41-95 table 41-50, replace the row for bit 5 with the following: 0?1 ? reserved, should be cleared. 2 ? global. asserting gbl enables snooping of connection tables. gbl should not be asserted if any of the related dmas will access the local bus. 3?5 ? reserved, should be cleared. 6 alb address look up bus for cam or address compression tables 0 reside on the system bus. 1 reside on the local bus. 7 ctb external connection tables bus 0 reside on the system bus. 1 reside on the local bus 0x00 6 dtb data buffers bus 0 data buffers reside on the system bus. 1 data buffers reside on the local bus 7 bib bd, interrupt queues, free buffer pool and external srts logic bus 0 reside on the system bus. 1 reside on the local bus. 0x00 6 dtb data buffer bus 0 reside on the system bus. 1 reside on the local bus. 7 bib bd, interrupt queue and external srts logic bus 0 reside on the system bus. 1 reside on the local bus. note: when using aal5, aal1 ces in udc mode, bds and data should be placed on the same bus (tct[dtb] = tct[bib]). 0x86 5 ctb connection tables bus. used for external channels only 0 external connection tables reside on the system bus. 1 external connection tables reside on the local bus. 4 datasheet u .com
revision history MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 b-32 freescale semiconductor 42.5, 42-36 table 42-13, replace the rows for offsets 0x40, 0x42, and 0x44 with the following: 45.5, 45-18 after the second paragraph in section 45.5, add the following note: note in the MPC8555E cpm pio port pinmuxing, fcc2 only has a primary option available for fcc2_txadd r0, fcc2_rxaddr0. there are no secondary options for these signa ls in the cpm pio port pinmuxing. 0x40 rcell_tmp_base hword rx cell temporary base address. po ints to a total of 64 bytes reserved dual-port ram area used by the cp. should be 64-byte aligned. user to specify only the lowest 16 bits of the dpram address offset calculated from the value in ccsrbar. 0x42 tcell_tmp_base hword tx cell temporary base addres s. points to total of 64 bytes reserved dual-port ram area used by the cp. should be 64-byte aligned. user to specify only the lowest 16 bits of the dpram address offset calculated from the value in ccsrbar. 0x44 udc_tmp_base hword udc mode only. points to a total of 32 bytes reserved dual-port ram area used by the cp. should be 64-byte aligned. user to specify only the lowest 16 bits of the dpram address offset calculated from the value in ccsrbar. 4 datasheet u .com
revision history MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor b-33 b.2 changes from revision 0 to revision 1 major changes to the MPC8555E powerquicc? iii integr ated processor reference manual , from revision 0 to revision 1 are as follows: section, page changes 1.3.16, 1-23 change the second paragraph to read as follows: ?six differential clock pairs are generate d for ddr drams. dlls are used in the local bus memory controller (lbc ) to generate two clock outputs.? 2.4, 2-18 in table 2-9, correct the reset va lue for the i2cdfsrr register to be 0x10. 2.4, 2-27 in table 2-9, add the following rows under the tsec1 fifo control and status registers section: 2.4, 2-27 in table 2-9, correct the reset va lue for the ostbd register to be 0x0800_0000. 2.4, 2-28 in table 2-9, correct the maccfg1 register from having r/w, r access to r/w access. 2.4, 2-30 in table 2-9, correct the car1 and ca r2 registers from having r access to r/w access. 2.4, 2-31 in table 2-9, correct the attr and attreli registers from having r access to r/w access. 2.4, 2-37 in table 2-9, correct the offset for the reserved addresses afte r the eoi register to be 0x4_00c0?0x4_0ff0. 2.4, 2-54 in table 2-9, correct the reset va lue for the gpindr register to be 0x nnnn _0000. 2.4, 2-55 in table 2-9, remove ddrdllcr designation at memory location 0xe_0e10. 2.4, 2-56 in table 2-9, correct the name of th e register with offset 0xe_1094 from pmlcb5 to pmlcb8. 3.1, 3-3 and 3-4 in figure 3-1 and table 3-1, re move memory interface signals, ?msync_in,? and ?msync_out.? 3.1, 3-12 in table 3-2, remove memory interface signals, ?msync_in,? and ?msync_out.? chapters 4, 16, 18, 20 throughout all applicable chapters, corr ectly state the debug mode source id (formerly documented to be visible on si gnals pci_ad[63:59]) to be visible on signals pci_ad[62:58]. 0x2_404c fifo_pause_ctrl?fifo pause control register r/w 0x0000_0000 14.5.3.2.1/14-30 0x2_4050? 0x2_4088 reserved r 0x0000_0000 ? 4 datasheet u .com
revision history MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 b-34 freescale semiconductor 4.2.2, 4-3 in table 4-3, correct the last sentence of the sysclk descri ption to read as follows: ?the ccb clock, in turn, feeds the pll in the e500 core and the dll that creates the local bus memory clocks.? 4.4.2, 4-10 correct the ninth step to read as follows: ?9. the internal hard reset to the e500 core is negated and soft resets are negated to the dll and other remaining i/o blocks. the dll begins to lock.? 4.4.3.3, 4-14 in table 4-11, change the third functional signal used to define boot rom location (formerly, ?lwe_b[3]?) to read ?lwe [3]?. 4.4.4.1, 4-22 replace the last sentence of th e first paragraph with the following: ?the ccb clock also feeds the pll in the e500 core and the dll that creates clocks for the local bus memory controller.? 4.4.4.1, 4-23 replace figure 4-6, ?clock subsys tem block diagram,? with the following figure: 4 datasheet u .com
revision history MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor b-35 4.4.4.3, 4-25 in figure 4-7, replace the sentence: ?watchdog timer events based on one of the 64 tb bits selected by tcr[wp] concatenated with the eis-defi ned tcr[wpext] (wp||wpext).? with the following sentence: ?watchdog timer events based on one of the 64 tb bits select ed by concatenating tcr[wpext] with the eis-de fined tcr[wp] (wpext||wp).? 4.4.4.3, 4-25 in figure 4-7, replace the sentence: ?fixed-interval timer events based on one of the 64 tb bits selected by tcr[fp] concatenated with the eis-de fined tcr[fpext] (fp||fpext).? with the following sentence: core pll platform pll dll lsync_in lsync_out lclk0 lclk1 core_clk e500 core ccb_clk to rest of the device sysclk ccb_clk cfg_sys_pll[0:3] cfg_core_pll[0:1] 2 4 lbc pci1 pll pci2 pll pci 2 pci 1 pci1_clk cfg_pci1_clk cfg_pci2_clk pci2_clk 2 n dram mck[0:5] mck [0:5] 6 6 ddr controller clock control 4 datasheet u .com
revision history MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 b-36 freescale semiconductor ?fixed-interval timer events based on one of the 64 tb bits selected by concatenating tcr[fpext] with th e eis-defined tcr[fp] (fpext||fp).? 6.6.1, 6-14 in table 6-8, change the desc ription of tcr[wrc] as follows: 01 if msr[me] = 0, the second timeout is ignored. if msr[me] = 1, a machine check condition occurs on a second timeout of the watchdog timer, and if hid0[emcp] = 1, the machine check interrupt is generated. 6.6.1, 6-14 in table 6-8, change the second senten ce of the description for bits 32?33 of the tcr register to the following: wpext[0?3] || wp[0?1] = 0b00_ 0000 selects tbu[32] (the msb of the tb) wpext[0?3] || wp[0?1] = 0b11_1111 select s tbl[63] (the lsb of the tb) 6.6.1, 6-15 in table 6-8, change the second senten ce of the description for bits 38?39 of the tcr register to the following: fpext[0?3] || fp[0?1] = 0b00_0000 selects tbu[32] (the msb of the tb) fpext[0?3] || fp[0?1] = 0b11_1111 selects tbl[63] (the lsb of the tb) 6.7.2.4, 6-22 in table 6-12, change th e bit range ?43?46? to ?36?46?. 4 datasheet u .com
revision history MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor b-37 6.10.2, 6-27 in table 6-17, replace the descript ion of hid1[rfxe] with the following: 6.11.3, 6-30 in table 6-20, describe bits 34?38 as ?reserved, should be cleared,? as is properly expressed in figure 6-35. disregard descript ions associated with bits 34, 35, or 36 in table 6-20. 6.12.5.3, 6-37 in table 6-28, describe bits 52?56 as ?reserved for implementation-specific use?. 7.3.1.1, 7-8 in table 7-2, change the description for bit 1 from ?accesses to memory-mapped sram are unaffected...? to ?data in memory-mapped sram regions is unaffected...? 7.3.1.5.2, 7-16 in table 7-12, change the bit descri ptions for bits 27 and 31 of the l2errdet register as follows: bit 27, tparerr: add the following text: ?note that if an l2 cache tag parity error occurs on an attempt to write a new line, the l2 cache must be flash invalidated. l2 functionality is not gua ranteed if flash invalidation is not performed after a tag parity error.? bit 31, l2cfgerr: add the foll owing text to the 1st line of description, ?reports read fault exception enable. controls whether assertion of core_fault_in causes a machine check interrupt. the assertion of core_fault_in can result from an l2 multibit ecc error. it can also occur fo r a system error if logic on the integrated device signals a fault for nonfatal errors (read da ta is corrupt (or zero), but the bus transaction can complete without corrupting other system state, maki ng it unnecessary to take a machine check (for example, a master abort of a pci transaction). 0 assertion of core_fault_in cannot cause a machine check. rfxe should be le ft clear if an interrupt is to be reported by the integrated device through int or c_int for this condition. if rfxe = 0, it is important that t he integrated device generates an interrupt if core_fault_in is asserted. if core_fault_in is asserted, any data on the ccb is dropped, stalli ng the load/store unit and eventually causing the e500 pipeline either to stall until an interrupt occurs (t ypically generated by the programmable interrupt controller (pic) in response to the fault) or to continue proc essing with bad data until the interrupt occurs. because core_fault_in cannot cause a machine check, if rfxe is 0, it is critical that the system be configured to generate the appropriate interrupt. it is also possible to hang the processor (requiring a hard reset to recover) if a guarded load hits in the l2 cache and gets an uncorrectable ecc error. because of this, avoi d defining memory as cacheable but guarded. if this combination is required, rfxe must be enabled, in which case an error causes both a machine check interrupt and an external interrupt when a bus fault condition is detect ed unless interrupts are masked for all sources of bus faults, such as dram ecc errors, pci parity errors, local bus parity errors, and others. rfxe must also be set if software requir es that code execution stop immediately when a bus fault occurs rather than continuing with the bad data until the interrupt arrives. ag ain, this results in both a machine check interrupt and an external interrupt when a bus fault is detected, unless all possible sources for bus fault have their interrupts masked. the machine check interrupt can then re-enable normal interrupts and wait for the interrupt due to the fault to be received before returning from the machine check. 1 a machine check can occur due to assertion of core_fault_in . if msr[me] = 1 and a fault is signaled, a machine check interrupt occurs. if msr[me] = 0 and a fault is signaled, a checkstop occurs. note that if rfxe is set and another mechanism is configur ed to generate an interrupt in response to assertion of core_fault_in , the same event causes two interrupts, the machine check enabled by setting rfxe and the interrupt triggered by the on-chip peripheral or other block; ther efore, rfxe should be set only if no other mechanism is configured to generate an interrupt for this case. note that the l2 cache detects any assertion of core_fault_in and ensures that the l2 cach e is not corrupted when data is dropped for this type of transaction. 4 datasheet u .com
revision history MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 b-38 freescale semiconductor inconsistencies between the l2siz, l2bl ksz, and l2sram settings of the l2 control register (l2ctl).? 7.7.4, 7-26 add the following note after the second paragraph: note there is a scenario in which a lock cl ear operation appears to fail to clear a lock in the l2 cache. this occurs only when the attempt to set the lock results in a bus error (for example, pci returns an error condition). assume the following scenario: 1. the e500 attempts to set a lock in the l2 cache (by executing a dcbtls or icbtls instruction with ct = 1) . the line is not alread y present in the cache, so it must be read from external memory. this read encounters an error which, depending on the chip configuratio n, will be reported to the core (probably as an interrupt). 2. at (or near) the same time, a cache external write to the same cache line is being mastered by the ecm. 3. very soon after the cache external write, a transaction to clear the lock occurs. this can be caused by the processor executing a dcblc or icblc instruction with ct = 1, or by the ec m mastering a lock clear transaction. if this scenario occurs within a tight timing window, the cache line may unexpectedly remain locked at the end of the sequence. the interrupt handler may want to clear the erroneously remaining lock in this case. 7.9, 7-29 add new section 7.9.2, ?flash inva lidation of l2 cache? as follows: the l2 cache may be completely invalidated by setting the l2i bit of the l2 control register (l2ctl). note that no data is lost in this process because the l2 cache is a write-through cache and contai ns no modified data. flash invalidation of the cache is necessary when the cache is initially enabled and may be necessary to recover from some error conditi ons such as a tag parity error. the invalidation process requ ires several cycles to complete. the l2i bit remains set during this procedure and is then cleared automatical ly when the procedure is complete. the l2 cache controller issues retries for all transactions on the e500 core complex bus (ccb) while the flash invalidation process is in progress. note that the contents of memory-mappe d sram regions of the data array are unaffected by a flash invalidation of the l2 cache regions of the array.? 7.10, 7-33 add new section 7.10, ?initializati on/application information,? with the following sections: section 7.10.1, ?initialization,? with new subsections section 7.9.1.1, ?l2 cache initializa tion,? and section 7.9.1.2, ?memory-mapped sram initialization.? 4 datasheet u .com
revision history MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor b-39 7.9.1.1 l2 cache initialization after power-on reset, the valid bits in the l2 cache status array are in random states. therefore, it is necessary to pe rform a flash invalidate operation before using the array as an l2 cache. this is done by writing a 1 to th e l2i bit of the l2 control register (l2ctl). th is can be done before or simultaneously with the write that enables the l2 cache. that is, the l2e and l2i bits of l2ctl can be set simultaneously. the l2i bit clears auto matically, so no further writes are necessary. 7.9.1.2 memory-mapped sram initialization after power-on reset, the contents of th e data and ecc arrays and are random, so all sram data must be initialized before it is read. if the cache is initialized by the core or any other device that uses sub-cacheline transactions, ecc error checking should be disabled during the initialization pr ocess to avoid false ecc errors generated during the read-modify-w rite process used for sub-cacheline writes to the sram array. this is done by setting the multi- and single-bit ecc error disable bits of the l2 error disable register (l 2errdis[mbeccdis, sbeccdis]). see section 7.3.1.9 .2, ?error control and capt ure registers.? if the array is initialized by a dma engine us ing cache-line writes, then ecc checking can remain enabled during the initialization process. also, add new section 7.10.2, ?managing errors,? with subsections section 7.10.2.1, ?ecc errors,? and secti on 7.10.2.2, ?tag parity errors.? 7.10.2.1 ecc errors an individual soft error that causes a single- or multi- bit ecc error can be cleared from the l2 array simply by executing a dcbf instruction for the address captured in the l2erraddr register. this will inva lidate the line in the l2 cache. when the load that caused the ecc error is perf ormed again, the data wi ll be re-allocated into the l2 with ecc bits set properly again. if the threshold for single bit errors se t in the l2errctl register is exceeded, then the l2 cache should be flash invalida ted to clear out all single-bit errors. note that no data is lost by executing dcbf instructions or flash invalidate operations because the l2 cache is writ e-through and contains no modified data. 7.10.2.2 tag parity errors a tag parity error must be fixed by flas h invalidating the l2 cache. note that executing a dcbf instruction for the address that cau sed the error to be reported is not sufficient because a tag parity error is seen as an l2 miss and does not cause invalidation of the bad tag. proper l2 opera tion cannot be guaranteed if an l2 tag parity error is not repaired by a fl ash invalidation of the entire array. 9.1, 9-1 remove the last sentence of the first paragraph. 4 datasheet u .com
revision history MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 b-40 freescale semiconductor 9.1, 9-2 replace figure 9-1, ?ddr memory cont roller simplified block diagram,? with the following: 9.3.1, 9-4 in table 9-1, remove si gnals msync_in and msync_out. 9.3.2.2, 9-8 in table 9-4, remove si gnals msync_in and msync_out. 9.3.2.2, 9-8 in table 9-4, correct the ?mcke? signal name to read ?mcke[0:1]?. also, change the first full sentence of the mcke[0:1] signal description to read: ?two identical output signals (each hereafter referred to simply as mcke) used as the clock enable to one or more sdrams.? 9.3.2.2, 9-8 correct timing description of mck signals to read as follows: ?source synchronous configur ation as defined by the ddr_sdram_clk_cntl register de termines timing relationship.? 9.4.1.4, 9-13 in table 9-9, replace all instances of |caslat| with . address from ddr sdram data from data from ddr sdram data signals rmw ecc request from row physical bank, fifo sdram address open row address en en data qualifiers clocks to error ma[0:14] mba[0:1] mcs [0:3] mcas mras mwe mdm[0:8] mcke[0:1] mdqs[0:8] mdq[0:63] mecc[0:7] mck[0:5] decode control open logical bank, row ta b l e control dram input staging queue memory array memory control master master sdram master management mck [0:5] ecm ecc delay chain error signals sdram control clock control caslat 4 datasheet u .com
revision history MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor b-41 9.4.1.8, 9-14 correct the ddr_sdram_clk_cntl[ ss_en] field description to read as follows: ?source synchronous enable. this bitfield must be set during initialization. see section 9.6.1, ?ddr sdram initia lization sequence,? for details. 0 reserved 1 the address and command are se nt to the ddr sdrams source synchronously.? 9.4.1.5, 9-15 in table 9-10, change the setting of the mbee bit in the ddr_sdram_cfg[ecc_en] description to read as follows: ?ecc enable. note that uncorrectable re ad errors may cause the assertion of core_fault_in, which causes the core to generate a machine ch eck interrupt unless it is disabled (by clearing hid1[rfxe]). if rfxe is ze ro and this error occurs, err_disable[mbed] must be zero and err_int_en[mb ee] and ecc_en must be one to ensure an interrupt is generated. see section 6.10.2, ?hardware implementation-dependent register 1 (hid1).? 0 no ecc errors are reported. no ecc interrupts are generated. 1 ecc is enabled.? 9.4.1.7, 9-16 in table 9-12, add the fo llowing last se ntence to the ddr_sdram_interval[refin t] field description: ?note that refint must be set to a non- zero value in order fo r the ddr to enter sleep mode. see section 17.5.1.5.3, ?sleep mode,? for additional details.? 9.4.1.16, 9-22 change the setting of mbee bit in the err_disable[mb ed] description to read as follows: multiple-bit ecc error disable 0 multiple-bit ecc errors are detected if ddr_sdra m_cfg[ecc_en] is set. they are reported if err_int_en[mbee] is set. note that uncorrectable read errors cause the assertion of core_fault_in , which causes the core to generate a machine check interrupt, unless it is di sabled (by clearing hid1[rfxe]). if rfxe is zero and this error occurs, mbed must be zero and err_int_en[mbee] and ecc_en must be one to ensure that an interrupt is generated. 1 multiple-bit ecc errors ar e not detected or reported. 9.4.1.17, 9-23 change the setting of the mbee bit in the err_in t_en[mbee] description to read as follows: ?multiple-bit ecc erro r interrupt enable. note that uncorrectable re ad errors may cause the assertion of core_fault_in , which causes the core to generate a machine check interrupt, unless it is disabled (by clearing hid1[r fxe]). if rfxe is zero and this error occurs, err_disable[ mbed] must be zero and mbee and 4 datasheet u .com
revision history MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 b-42 freescale semiconductor ddr_sdram_cfg[ecc_en] must be set to ensure that an interrupt is generated. for more informat ion, see section 6.10.2, ?hardware implementation-dependent register 1 (hid1).? 0 multiple-bit ecc errors cannot generate interrupts. 1 multiple-bit ecc errors generate interrupts.? 9.5, 9-26 replaced figure 9-22, ?ddr memory controller block diagram,? with the following figure: 9.5, 9-27 remove figure 9-23, ?controller dll timing loop.? 9.5.1.1, 9-31 delete the second-to-la st paragraph, whose fi rst sentence starts with the words, ?if a disabled bank...?. 9.5.4, 9-36 in the last paragraph, change the phras e, ?see figure 9-27 for a single-beat read operation,? to read ?see figure 9-27 fo r a back-to-back burst read operation,?. 9.5.4?9.5.8, 9-36?9-40 in all burst examples, re-number the data beats in the figures to be d0, d1, d2, d3, d0, d1, d2, d3. address decode request from master input staging queue physical bank, logical bank, row row open address control ddr sdram memory array: ma[0:14] mbaa[0:1] debug signals: msrcid[0:4] mdval ddr sdram memory control: mcs [0:3] mcas mras mwe mdm[0:8] mcke[0:1] data strobes: mdqs[0:8] data signals: mdq[0:63] mecc[0:7] address from master sdram control row open ta b l e delay chain neg dq ecc error signals dq dq ecc rmw ecm to error management data from sdram data from master en en clocks: mck [0:5] mck[0:5] dram fifo pos fifo clock control 4 datasheet u .com
revision history MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor b-43 9.5.4.1, 9-37 remove the second bulleted item. 9.5.4.1, 9-37 replace the third bulleted item (forme rly the fourth; see above item) with the following: ?pcb traces for ddr clock signals should be short, all on the sa me layer, and of equal length and loading.? 9.5.4, 9-37 change the title of figure 9-29 to ?ddr sdram burst write timing?acttorw = 4?. 9.5.6, 9-39 change the last sentence of this sect ion to read ?figure 9-32 shows the registered ddr sdram dimm back-to-back burst write timing.? 9.5.8, 9-40 replace the existing figure 9-33 with the figure below: 9.5.9, 9-41 in the paragraph preceding section 9.5.9.1, change the reference to ?two sets of auto refresh commands...? to read ?three sets of auto refresh commands...?. also, change the reference to ?...commands are also staggered in two groups...? to read ?... commands are also staggered in three groups...? 9.5.9.1, 9-42 in figure 9-34, remove the a nnotation of ?0 or 3? in clock 12. 9.5.9.2, 9-42 after the second paragra ph, add the following paragraph: ?all open pages are precharged before self refresh mode is entered.? acttorw row col sdram clock mcs mcas ma[13:0] mwe mras 00 mdq[0:63] mdqs mdm[0:7] 1/4 delay col mdq[0:63] mdqs mdm[0:7] 1/2 delay 01 2345 67 89101112 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 00 4 datasheet u .com
revision history MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 b-44 freescale semiconductor also, correct the last sentence of the fifth paragraph to read: ?this mode is controlled with ddr_sdram_cfg[dyn_pwr].? 9.5.10, 9-44 replace the third and fourth sentences of this section with ?i f ecc is enabled for a sub-doubleword write transaction, a full read-modify-write is performed to properly update ecc bits. if ecc is di sabled then no read-modify-write is required for sub-doubleword writes, and th e data masks (mdm[0:8]) are used to prevent writing unwanted data to sdram.? 9.5.12, 9-46 add the following sentences before the second-to-last sentence of the second paragraph: ?this read-modify-write operation is perform ed as an atomic transaction in the ddr controller. the write command is then issued 3-5 memory clocks after the completion of the read, dependi ng on various system parameters.? 9.5.13, 9-48 in the last paragraph, de lete the three sentences that start and end with, ?for all memory select errors...? and ?...to show the transaction is not real.? 9.6.1, 9-49 replace the first para graph with the following: ?after configuration of al l parameters is complete, system software must set ddr_sdram_clk_cntl[ss_en] and ddr_sdram_cfg[mem_en] to properly enable the memory interface. note that 200 s must elapse after the memory clocks are stable (that is, initial ization is complete of all clock related configuration registers) before mem_en can be set, so a delay loop in the initialization code may be ne cessary if software is enabling the memory controller. after mem_en has been set, the ddr me mory controller automatically performs jedec-compliant initialization sequence to initialize memories according to the information in the sdmoce and esdmode fields of the ddr_sdram_mode register. the initia lization sequence is as follows:? after the numbered list, a dd the following sentence: ?note that the ba0 and ba1 bi ts are automatically driven appropriately during the mode register set commands.? then the final sentence should be changed to, ?after this automatic initialization is complete the memory array is ready for access and the memory controller begins processing memory transactions as they arrive.? 10.2.2, 10-7 in table 10-5, delete the last sent ence in the timing/ negation section for irq[0:11] signals about edge-sensitive interrupts. 10.3.7, 10-36 in table 10-35, correct the who am i register name from ?whoami0? to ?whoami.? 10.4.1, 10-41 add the following new para graph after the first paragraph: ?note that the ipr, is, and irr are intern al registers that ar e not accessible to the programmer.? 4 datasheet u .com
revision history MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor b-45 11.3, 11-4 in table 11-3, correct the i2cdfsrr reset value to be 0x10. 11.4.5.2, 11-18 insert the following sentence after th e polynomial used for crc calculation in the fourth paragraph: ?crc values are calculated using the above polynomial with a start value of 0xffff_ffff and an xor with 0x0000_0000.? 12.3.1.9, 12-15 in table 12-16, change the second sent ence of the asserted (?1?) description for the ulsr[bi] to read: ?a break condition is expected to last at least two character lengths and a new character is not loaded until sin returns to the mark state (logic 1) and a valid start is detected.? 13.1.3.1, 13-3 change the third sentence of the first paragraph to read: ?in addition to establishing the frequency of the extern al local bus clock, clkdiv also affects the resolution of signal timing shifts in gpcm mode, and the interpretation of upm array words in upm mode.? 13.1.3.1, 13-4 in the last sentence, cha nge ?lclk[0:3]? to ?lclk[0:2].? 13.2, 13-6, 13-7, and 13-9 in table 13, change all instances of ?ras? to ?ras ? and all instances of cas to cas . 13.3.1.2.3, 13-16 and 13-17 in table 13-7, table 13-8, figure 13-4, and figure 13-5, change bits 17?18 to reserved. 13.4.3.7.3, 13-55 in the section titl e, change ?cas? to ?cas ?. 13.4.4, 13-61 insert the following footnote associat ed with the word ?signals? in the second sentence of the section: ?if the lgpl4/lgta/lupwait/lpbse signa l is used as both an input and an output, a weak pullup is requi red. refer to the hardware specification for details regarding termination options . ? 13.4.4.2, 13-65 add the following third paragraph: ?note that the upm memory region must be cache-inhibited or write-through (the mmu page must have the i or w bit set) during the time that the upm array is being written. if the memory is to be cacheable and/or copy- back, the mmu must be set accordingly after th e upm array is initialized.? 14.5.2, 14-14 in table 14-3, add the following as the first row under the tsec1 fifo control and status registers section: 14.5.2, 14-15 in table 14-3, correct the reset value for the ostbd register to 0x0800_0000. 0x2_404c fifo_pause_ctrl?fifo pause contro l register r/w 0x0000_0000 14.5.3.2.1/14-30 4 datasheet u .com
revision history MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 b-46 freescale semiconductor 14.5.2, 14-16 in table 14-3, correct the maccfg1 register from having r/w, r access to r/w access. 14.5.2, 14-16 in table 14-3, correct the ifstat re gister from having r access to r/w access. 14.5.2, 14-18 in table 14-3, correct the car1 and ca r2 registers from ha ving r access to r/w access. 14.5.2, 14-19 in table 14-3, correct the attr and attreli registers from having r access to r/w access. 14.5.3.1.1, 14-21 in table 14-4, correct the ievent[rxc ] bitfield description to read as follows: ?receive control interrupt. a control frame was received. if maccfg1[rx_flow] is set, a pause op eration is performed lasting for the duration specified in the received paus e control frame and beginning when the frame was received. 0 control frame not received 1 control frame received? 14.5.3.1.3, 14-24 and14-25 undocument bit fields txedis , crl/xdadis, and xfundis. 14.5.3.1.7, 14-28 remove bit field dm actrl[tod] from figure 14- 12 and table 14-10. this bit position (29) is now reserved. 14.5.3.2.1, 14-30 insert the following section as the first subsection of section 14.5.3.2: 14.5.3.2.1 fifo pause control register (fifo_pause_ctrl) fifo_pause_ctrl, shown in figure 14- 14, is writable by the user to configure the properties of the tsec fifo. 0 15 r0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset 0000_0000_0000_0000 16 29 30 31 r0 0 0 0 0 0 0 0 0 0 0 0 0 0 tfc_pause_en 0 w reset 0000_0000_0000_0000 offset tsec1:0x2_404c; tsec2:0x2_504c figure 14-14. fifo_pause_ctrl register definition 4 datasheet u .com
revision history MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor b-47 table 14-12 describes the fields of the fifo_pause_ctrl register. 14.5.3.3.1, 14-33 in table 14-15, replace the bitfield description of tctrl[tfc_pause] with the following: ?transmit flow control pause frame. use th is bit to transmit a pause frame. to transmit a flow control pause frame, first set fifo_pause_ctrl[tfc_pause_en]. next, set maccfg1[gts]. if tfc_pause is then set, the mac stops transmission of data frames after the current transmission completes. the gtsc interrupt in the ievent register is asserted. with transmission of data frames stopped, the mac transmits a mac control pause frame with the duration va lue obtained from the ptv register. the txc interrupt occurs after sending the cont rol pause frame. next, the mac clears tfc_pause and resumes transm itting data frames. note th at if the transmitter is paused due to user assertion of gts or reception of a pause frame, the mac may still transmit a mac control pause frame. 0 no outstanding pause fram e transmission request. 1 pause frame transmission requested.? 14.5.3.4.2, 14-41 replace figure 14-27 with the following figure: 14.5.3.6.1, 14-49 in table 14-32, add the following sentence to the maccfg1[rx_en] field description: ?if set, prior to clearing this bit, se t dmactrl[grs] then confirm subsequent occurrence of the graceful receive st op interrupt (ievent[grsc] is set).? table 14-12. fifo_pause_ctrl field descriptions bits name description 0?29 ? reserved 30 tfc_pause_en tfc_pause enable. this bit enables th e ability to transmit a pause control frame by setting the tctrl[tfc_pause] bit. this bit is cleared at reset. 0 pause control frame transmission disabled. 1 pause control frame transmission enabled. 31 ? reserved 0789 31 r0 0000000 qhlt 00000000000000000000000 w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_4304; tsec2:0x2_5304 4 datasheet u .com
revision history MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 b-48 freescale semiconductor 14.5.3.6.1, 14-49 in table 14-32, add the following sentence to the maccfg1[tx_en] field description: ?if set, prior to clearing this bit, se t dmactrl[gts] then confirm subsequent occurrence of the graceful transmit stop interrupt (ievent[gtsc] is set).? 14.5.3.6.6, 14-53 in table 14-37, clarify the bit descript ion of the mgmt clock select field of the miimcfg register so that instead of c oncluding with ?... di vided by eight.? the third sentence concludes with ?... divided first by eight and then further divided by the following value:?. 14.5.3.6.8, 14-55 in table 14-39, replace ?(0 is reserved)? with the following: ?at least one phy address is reserved for the tbi phy address as programmed in the tbipa register (section 14.5.3.1.8, ?tbi physical a ddress register (tbipa),? figure 14-13). the default of the tbi phy address is 0x00. the user must be sure to assign a physi cal address to the tbi so as to not conflict with the external phy physical address as discussed in the register initialization steps in section 14.7, ?initialization/ application information.? 14.5.3.6.12, 14-56 and 14-56 delete the first sentence and repla ce figure 14-45 with the following figure (exposing the link fail status field): 14.5.3.7.44, 14-80 correct the first sentence to read: ?carry register bits are clear ed when written with a one.? 14.5.3.7.45, 14-82 correct the first sentence to read: ?carry register bits are clear ed when written with a one.? 14.5.3.7.47, 14-83 in figure 14-94, change bit 30 to be ?reserved?. 14.6.2.2, 14-110 insert the following step between steps 3 and (formerly) 4: ?4. wait for a period of 9.6 kbytes wort h of data on the interface (~8 ms worst case).? 14.6.2.2, 14-111 correct step 11 of the graceful reset pro cedure to read: ?11. set wwr and wop bits in dmactrl register? 14.6.2.3, 14-111 replace the second paragraph with the following: ?if the user has a frame ready to transm it, a transmit-on-demand function may be emulated while in polling mode by using th e graceful-transmit-st op feature. first, clear the imask[gtscen] bi t to mask the graceful-transmit-stop complete 0 21 22 23 28 31 r 000000000000000000000 0 excess defer 0 0000 link fail 00 0 w reset 0000_0000_0000_0000_0000_0000_0000_0000 offset tsec1:0x2_453c; tsec2:0x2_553c 4 datasheet u .com
revision history MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor b-49 interrupt. next set, then immediately clear the dmactrl[gts] bit. clear the resulting ievent[gtsc] bit. finally, the imask[gtscen] bit may be set once again.? 14.6.2.3, 14-112 insert the following se ntence between the third and (f ormerly) fourth sentences of the sixth paragraph: ?the pause duration is defined by the received pause control frame and begins when the frame wa s first received.? 14.6.2.6.4, 14-116 add the following section after section 14.6.2.6.3: 14.6.2.6.3 crc computation examples there are many algorithms for calculating the crc value of a number. refer to the rfc 3309 standard, which can be found at http://www.faqs.org/rfcs/rfc3309.html, to compute the crc value for the purposes of tsec. the rfc 3309 algorit hm uses the follo wing polynomial to calculate the crc value: x32+x26+x23+x22+x16+x12+x11+x1 0+x8+x7+x5+x4+x2+x1+x0 or 0x04c11db7. given a destination mac address of da=01000ccccccc, the algorithm results in a crc remainder value of 0xa29f4bbc. bit-reversing the low-orde r byte of the crc value (0 xbc) yields br_crc = 0x3d = 0b00111101 the high-order 3-bits of the new br_crc value are used to select which 32-bit register (of the 8) to use. this example maps the da to register 1. high-order 3 bits of br _crc: ho_crc = 0b001 = 1 the low-order 5 bits are used to select which bit to set in the given re gister (with a value of 0 setting 0x8000_0000 and 31 setting 0x0000_0001). therefore, the example da maps to bit 29 of register 1. low-order 5 bits of br_crc: lo_crc = 0b11101 = 29 therefore, gaddr1 is ored with the value 0x0000_0004. additional calculated examples follow: example 1: ? destination mac address: da = 01005e000128 ? crc remainder value: crc = 0x821d6cd3 ? bit-reversed least-significant byt e of crc value: br_crc = 0xcb = 0b11001011 ? high-order 3 bits of br _crc: ho_crc = 0b110 = 6 ? low-order 5 bits of br_crc: lo_crc = 0b01011 = 11 ? gaddr6 = 0x0010_0000 4 datasheet u .com
revision history MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 b-50 freescale semiconductor example 2: ? destination mac address: da = 0004f0604f10 ? crc remainder value: crc = 0x1f5a66b5 ? bit-reversed least-significant byt e of crc value: br_crc = 0xad = 0b10101101 ? high-order 3 bits of br _crc: ho_crc = 0b101 = 5 ? low-order 5 bits of br_crc: lo_crc = 0b01101 = 13 ? gaddr5 = 0x0004_0000 14.6.2.8, 14-118 in table 14-115, correct the rxc description to read as follows: ?receive control: a control frame wa s received. as soon as the transmitter finishes sending the current frame, a pa use operation is performed lasting for the duration specified in the received paus e control frame and beginning when the frame was first received.? 14.6.3, 14- 122between the second and third paragraph, add the following: ?the status field of the bd is 16-bit fi eld, as is the length field. the data buffer pointer is a 32-bit field. therefore, the bds should be accessed with the following c structure: typedef unsigned short uint_16; /* choose 16-bit native type */ typedef unsigned int uint_32; /* choose 32-bit native type */ typedef struct bd_struct { uint_16 flags; uint_16 length; uint_32 bufptr; };? 14.7.1.1, 14-131 in table 14-123, add the following step immediately fo llowing the optional dmactrl initialization step: 14.7.1.2, 14-134 in table 14-126, add the following step immediately fo llowing the optional dmactrl initialization step: 14.7.1.3, 14-138 in table 14-129, add the following step immediately fo llowing the optional dmactrl initialization step: initialize fifo_pause_ctrl, fifo_pause_ctrl[0000_0000_0000_0000_0000_0000_0000_0010] initialize fifo_pause_ctrl, fifo_pause_ctrl[0000_0000_0000_0000_0000_0000_0000_0010] initialize fifo_pause_ctrl, fifo_pause_ctrl[0000_0000_0000_0000_0000_0000_0000_0010] 4 datasheet u .com
revision history MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor b-51 14.7.1.4, 14-142 in table 14-132, add the following step immediately fo llowing the optional dmactrl initialization step: 14.7.1.5, 14-146 in table 14-135, add the following step immediately fo llowing the optional dmactrl initialization step: 15.2.2, 15-6 and 15.4.1.3, 15-29 in the third bullet of the list of signals defined for the external control interface, clarify that the falling edge of dma_dreq sets mrn[cs] and for dma_ddone with the following: dma_ddone assertion indicates that the dma engine has completed the transfer. srn[cb] is clear. note, however, that write data may still be queued at the target interface or in the process of transfer on an external interface. 15.3.1, 15-6 in table 15-4, add the following me mory locations and designate them as ?reserved?: 0x2_112c 0x2_1148?0x2_117c 0x2_11ac 0x2_11c8?0x2_11fc 0x2_122c 0x2_1248?0x2_127c 0x2_12ac 0x2_12c8?0x2_12fc 15.3.2.10, 15-20 in figure 15-15, correct the offset value for clsdar2 to 0x2_1234. 15.3.2.11, 15-20 in figure 15-16, correct the offset value for the nlsdar n ?dma 2 next list descriptor address register to 0x2_123c. 15.4.1.1.1, 15-25 change step 1 in the sequence to rea d, ?poll the channel stat e (see table 15-19) to confirm that the specific dma channel is idle.? 15.4.1.1.2, 15-25 change step 1 in the sequence to rea d, ?poll the channel stat e (see table 15-19) to confirm that the specific dma channel is idle.? 15.4.1.1.3, 15-26 change step 2 in the sequence to rea d, ?poll the channel stat e (see table 15-19) to confirm that the specific dma channel is idle.? 15.4.1.1.4, 15-27 change step 3 in the sequence to rea d, ?poll the channel stat e (see table 15-19) to confirm that the specific dma channel is idle.? initialize fifo_pause_ctrl, fifo_pause_ctrl[0000_0000_0000_0000_0000_0000_0000_0010] initialize fifo_pause_ctrl, fifo_pause_ctrl[0000_0000_0000_0000_0000_0000_0000_0010] 4 datasheet u .com
revision history MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 b-52 freescale semiconductor 15.4.1.2.3, 15-28 change step 2 in the sequence to rea d, ?poll the channel stat e (see table 15-19) to confirm that the specific dma channel is idle.? 15.4.1.2.4, 15-28 change step 3 in the sequence to rea d, ?poll the channel stat e (see table 15-19) to confirm that the specific dma channel is idle.? 15.4.1.3, 15-30 replace figure 15-20 with the follow ing, showing more flexible negation of dreq : 16.3.1.2, 16-21 add the following sentence to the end of the third paragraph: ?note that outbound translation windows mu st not overlap the configuration access registers.? 16.3.1.2.4, 16-25 in figure 16-9, add a footnote to en field (bit 0) that states, ?for powar0, translation is always enabled. the enable field (en) may be r ead and written, but the value is ignored.? 16.3.1.4, 16-32 insert the following between the fourth and fifth paragraphs: ?if a data parity error occurs during an inbound configuration write access, the error is reported and captured. however, the erroneous data is written to the register specified in the tr ansaction. therefore, pci da ta parity error recovery routines must include reinitialization of th e pci configuration re gister if the error occurred during a configuration write.? 16.3.1.4.7, 16-38 add the following sentence before figure 16-21: ?note that for inbound reads that have data parity errors , only the address (err_addr and err_ex t_addr) and attributes (err_attrib) are captured. the data is not captured.? 16.3.1.4.8, 16-38 add the following sentence before figure 16-21: ?note that for inbound reads that have data parity errors , only the address (err_addr and err_ex t_addr) and attributes (err_attrib) are captured. the data is not captured.? dreq clock dack ddone transfer start transfer in progress transfer done transfer start transfer pause transfer restart emp_en 4 datasheet u .com
revision history MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor b-53 16.3.2.19, 16-53 in table 16-45, change the desc ription for bit 0 to read as follows: ?pci agent/host. read-only. indicates the reset value of the pci host/agent configuration signal, lwe2 . 0 pci interface is in host mode 1 pci interface is in agent mode? 16.4.2.11.2?16.4.2.11.3, 16-73?16-75 replace the existing sections with the following: 16.4.2.11.2 accessing the pci c onfiguration space in host mode to access the configuration space, a 32-bi t value must be written to the pci cfg_addr register that specifies the target pci bus, the target device on that bus, and the configuration register to be accessed within that de vice. note that the bus master bit in the mpc855 5e pci bus command register must be set before an outbound configuration access is attemp ted. device 0 on pci bus 0 is the MPC8555E itself; thus, device 0, bus 0 is used to access the internal pci configuration header. when the MPC8555E detects an access to pci cfg_data, it checks the enable flag and the device number in the pci cfg_addr register. if the enable bit is set, and the device number is not 0b1_1111, the MPC8555E performs a configuration cycle translation functi on and runs a configuration-read or configuration-write transact ion on the pci bus. if the bus number corresponds to the local pci bus (bus number = 0x00) , the MPC8555E performs a type 0 configuration cycle translatio n. if the bus number indicat es a remote pci bus (that is, nonlocal), the MPC8555E performs a t ype 1 configuration cycle translation. the device number 0b1_1111 is used fo r performing interrupt-acknowledge and special-cycle transactions. see sectio n 16.4.2.12, ?other bus transactions,? for more information. see section 16.3.1.1.1, ?pci conf iguration address regist er (cfg_addr),? for details on pci cfg_addr and sect ion 16.3.1.1.2, ?pci configuration data register (cfg_data),? for details on pci cfg_data. note that because a ll pci registers are intrinsically little-endian, in the following examples, the data in the configuration re gister is shown in little-endian order. powerpc processor accesses to the pc i cfg_data register should use the load/store with byte-reversed instructions . external pci masters that use the local address map to access confi guration space do not need to reverse bytes since byte lane redirection from the little-end ian pci bus is performed internally. example: configuration sequence, 4-byte data read from the revision id/standard programming interface/subclass code/class c ode registers at a ddress offset 0x08 of the pci configuration header (device 0 on the pci bus 0 is the MPC8555E itself). 4 datasheet u .com
revision history MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 b-54 freescale semiconductor initial values: r0 contains 0x8000_0008 r1 contains ccsrbar + 0x0_8000 (address of pci cfg_addr register) r2 contains ccsrbar + 0x0_8004 (address of pci cfg_data register) r3 contains 0xffff_ffff register at 0x08 contains 0x0b20_0002 (0x0b to 0x08) code sequence: stw r0, 0 (r1) lwbrx r3, 0 (r2) results: address ccsrbar + 0x0_8000 contains 0x8000_0008 register r3 contains 0x0b20_0002 example: configuration sequence, 4-byte data write to pci register at address offset 0x14 of device 1 on pci bus 0. initial values: r0 contains 0x8000_0814 r1 contains ccsrbar + 0x0_8000 (address of pci cfg_addr register) r2 contains ccsrbar + 0x0_8004 (address of pci cfg_data register) r3 contains 0x1122_3344 register at 0x14 contains 0xffff_ffff (0x17 to 0x14) code sequence: stw r0, 0 (r1)// update pci cfg_addr register to point to //register offset 0x14 of device 1. stwbrx r3, 0 (r2) results: address ccsrbar + 0x0_8000 contains 0x8000_0814 register at 0x14 contains 0x1122_3344 (0x17 to 0x14) example: configuration sequence, 2-byte data write to pci register at address offset 0x1c of device 1 on pci bus 0. initial values: r0 contains 0x8000_081c r1 contains ccsrbar + 0x0_8000 r2 contains ccsrbar + 0x0_8004 r3 contains 0xddcc_bbaa register at 0x1c contains 0xffff_ffff (0x1f to 0x1c) code sequence: stw r0, 0 (r1) sthbrx r3, 0 (r2) results: address ccsrbar + 0x0_8000 contains 0x8000_081c register at 0x1c contains 0xffff_bbaa (0x1f to 0x1c) 16.4.2.11.3 pci configuration in agent and agent lock modes in general, agents should not access the c onfiguration space of other external pci devices. configuration of agents is a func tion usually reserved for the host. when the MPC8555E is in agent mode, it re sponds to remote host-generated pci configuration cycles. this occurs when a configur ation command is decoded along with the idsel input signal being asserted. when the MPC8555E is in 4 datasheet u .com
revision history MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor b-55 agent lock mode, it retries all externally -generated pci confi guration cycles until the acl bit in the pci bus function regi ster (0x44) is set. see section 16.5.1, ?power-on reset configuration modes,? for more information. in either agent or agent lock mode, access to the internal pci configuration header by the processor core is handled as described in section 16.4.2.11.2, ?accessing the pci configuration space in host mode,? using devi ce = 0 and bus = 0 in pci cfg_addr to indicate the internal pci header. 17.3.4, 17-23 and 24 in figure 17-6 and table 17-8, cha nge the bitfield ?n? to be bit position 23 (formerly 24). subsequently, describe b it positions 24 thro ugh 31 as ?reserved.? 18.4, 18-4 in table 18-3, change the reset va lue of the gpindr register to be 0x nnnn _0000. 18.4, 18-4 in table 18-3, remove the second-to-last row former ly describing the ddr dll control register (ddrdllcr). 18.4.1.9, 18-12 in figure 18-9, change the reset value of the gpindr register to be nnnn _ nnnn_nnnn_nnnn_ 0000_0000_0000_0000. 18.4.1.14, 18-19 in table 18-17, change the bit ranges ?32?47? to ? 0?15? and ?48?63? to ?16?31?. 18.4.1.17, 18-20 remove section 18.4.1.17, ?ddr dll control regist er (ddrdllcr).? 18.5.1.5.3, 18-25 add the following sentence to the end of the first paragraph: ?note that the ddr controller does not shut down unless ddr_sdram_interval[refint] is set to a non-zero value. see section 9.4.1.7, ?ddr sdram in terval configuration (ddr_sdram_interval),? for details.? 19.3.1, 19-4 in table 19-1, correct the name of the register with offset 0xe_1094 from pmlcb5 to pmlcb8. 20.1, 20-2 in figure 20-1, remove pc i interface to trace buffer. 20.3.1.2, 20-14 change the last sentence in the firs t paragraph to, ?note that the transaction address is qualified with the bits described in section 20.3.1.3, ?watchpoint monitor address mask register (wma mr),? before being compared with wmar. note also that the contents of wmar are not qualified with wmamr.? 20.3.1.3, 20-15 change the last part of the first senten ce to be ?...contains th e mask that is applied to a transaction address before th e address is compared with wmar.? 20.3.2.2, 20-20 in the first sentence, replace ?tbcr[amd]? with ?tbcr0[amd]?. also, replace the last sentence of the first paragraph with the following, ?the transaction address is qualified with the bits de scribed in section 20.3.2.3, ?trace buffer address mask register (tbamr),? befo re being compared with tbar. note that the contents of tbar ar e not qualified with tbamr.? 20.3.2.2, 20-20 change the last part of the first senten ce to be ?...contains th e mask that is applied to a transaction address before th e address is compared with tbar.? 4 datasheet u .com
revision history MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 b-56 freescale semiconductor 20.3.2.2, 20-21 in the last sentence of the fi rst paragraph, replace ?tbcr[tmd]? with ?tbcr0[tmd]?. 20.4.6.1, 20-31 and 20-32 change all instances of ?trsel? and ?trs el1? to ?ifsel? a nd all instances of ?tbcr? to ?tbcr1?. 21.3.1, 21-26 in table 21-9, delete ?refer to table 13-7? in the sbc field description. 21.3.1.1, 21-27 in table 21-10, replace footnote 1 with ?see sbc for fcc1 and fcc2, table 21-9?. 24.4.1, 24-6 in table 24-2, change the name of bits 6?7 to read ?mad4?m ad3?. also, replace the description with the following: master address output pin x connection. note that the address indexes are relative to fcc1; see figure 24-5. these bits determine the number of atm phys supported by fcc1 and fcc2. 00 fcc1 supports 7 phys; fcc2 supports 31 phys 01 fcc1 supports 15 phys; fcc2 supports 15 phys 10 reserved 11 fcc1 supports 31 phys; fcc2 supports 7 phys 23.6.1, 23-17 in figure 23-10, change the offset (addr) for si2gmr from ?0x9_1b28? to ?0x9_1b48?. 24.4.1, 24-7 in figure 24-5, correct the pin name fo r fcc1 utopia rx address rxaddr[3] = pd9 to rxaddr[3] = pd29. 24.4.1, 24-7 in figure 24-5, correct the pin name fo r fcc2 utopia rx address rxaddr[1] = pc23 to rxaddr[1] = pd23. 26.1, 26-2 replace the first three bullets with the following: ? the maximum input clock is the inte rnal cpm clock which is the core complex bus (ccb) clock divided by 3. ? maximum period of 2.6 seconds (at 100 mhz) ? 10-ns resolution (at 100 mhz) 26.2, 26-2 replace the first two bullets with: ? internal cpm clock (ccb/3) ? internal cpm clock divided by 16 (ccb/48) also, replace the first four sentence s of the following paragraph with: ?the internal cpm clock is generated in the cpm cloc k synthesizer and defaults to the ccb clock frequency divided by 3. the user can either choose that frequency or the frequency divided by 16 as the input to the prescaler of each timer.? 4 datasheet u .com
revision history MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor b-57 also, replace the last two sentences of the next paragraph with, ?the best resolution of the timer is one clock cycle (10 ns at 100 mhz). the maximum period (when the reference value is al l ones) is 268,435,456 cycles (2.6 seconds at 100 mhz).? 26.2, 26-3 replace the note toward the bottom of the page with, ?tgate x is internally synchronized to the internal cpm cloc k. after the falli ng edge of tgate x is recognized, the counter begins counting after one intern al cpm clock cycle when working with the internal clock.? 41.11, 41-82 add the following clarifyi ng note after the second paragraph: note ensure that the transmit intqs and the receive intqs are programmed as separate queues. 43.5, 43-12 in table 43-5, replace im mr with ccsrbar in footnote 1. 44.5, 44-12 in table 44-6, replace im mr with ccsrbar in footnote 1. 4 datasheet u .com
revision history MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 b-58 freescale semiconductor 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor glossary-1 glossary the glossary contains an alphabetical list of terms, phrases, and abbr eviations used in this reference manual. a architecture. a detailed specification of requireme nts for a processor or computer system. it does not specify details of how the processor or computer system must be implemented; instead it provides a template for a family of compatible implementations . atomic access. a bus access that attempts to be part of a read-write operation to the same address uninterrupted by any other access to that address (the term refers to the fact that the transacti ons are indivisible). the power architecture technology implements atomic accesses through the lwarx / stwcx. instruction pair. autobaud. the process of determining a serial data rate by timing the wi dth of a single bit. b beat. a single state on the bus interface that may extend across multiple bus cycles. a transaction can be composed of multiple address or data beats . big-endian. a byte-ordering method in memory where the address n of a word corresponds to the most-significant byte . in an addressed me mory word, the bytes are ordered (left to right) 0, 1, 2, 3, with 0 being the most-significant byte . see little endian . boundedly undefined. a characteristic of certain operat ion results that are not rigidly prescribed by the power architecture technology. boundedly-undefined results for a given operation may vary among im plementations and between execution attempts in the same implementation. although the architecture does not prescribe the exact behavior for when results are allowed to be boundedly undefined, the results of ex ecuting instructions in contexts where results are allowed to be boundedly undefined ar e constrained to ones that could have been achieved by executing an arbitrary sequence of defined instructions, in valid form, starting in the state the machine was in before attempting to execute the given instruction. breakpoint. a programmable event that forces the core to take a breakpoint exception. burst. a multiple-beat data transfer whose total size is typically e qual to a cache block. bus clock. clock that causes the bus state transitions. 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 glossary-2 freescale semiconductor bus master. the owner of the address or data bus; th e device that initia tes or requests the transaction. c cache. high-speed memory containing recently acc essed data or instructions (subset of main memory). cache block. a small region of contiguous memory that is copied from memory into a cache . the size of a cache block may vary among processors; the maximum block size is one page . in power architecture processors, cache coherency is maintained on a cache-block basis. note that the term ?cache block? is often used interchangeably with ?cache line.? cache coherency. an attribute wherein an accurate and common view of memory is provided to all devices that share the same memory system. caches are coherent if a processor performing a read from its cach e is supplied with data corresponding to the most recent value written to me mory or to another processor?s cache. cache flush. an operation that removes from a cache any data from a specified address range. this operation ensures that any modi fied data within the specified address range is written back to main memory. this operation is generated typically by a data cache block flush ( dcbf ) instruction. caching-inhibited. a memory update policy in which the cache is bypassed and the load or store is performed to or from main memory. cast out. a cache block that must be written to memory when a cache miss causes a cache block to be replaced. changed bit. one of two page history bits found in each page table entry (pte). the processor sets the changed bit if any store is performed into the page . see also page access history bits and referenced bit . clean. an operation that causes a cache block to be written to memory , if modified, and then left in a valid, unmodified state in the cache. clear. to cause a bit or bit field to re gister a value of zero. see also set . context synchronization. an operation that ensures that all instructions in execution complete past the point where they can produce an exception , that all instructions in execution complete in the context in which they began execution, and that all subsequent instructions are fetched and executed in the new context. context synchronization may result from execut ing specific instructions (such as isync or rfi ) or when certain events occur (such as an exception). copy-back operation. a cache operation in which a cache line is copied back to memory to enforce cache coherency. copy-back operations consist of snoop push-out operations and cache cast-out operations. 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor glossary-3 d direct-mapped cache. a cache in which each main memory address can appear in only one location within the cache; operates more quickly when the memory request is a cache hit. double data rate. memory that allows data transfers at the start and end of a clock cycle. thereby doubling the data rate. e effective address (ea). the 32-bit address specified for a load, store, or an instruction fetch. this address is then submitted to the mmu for translation to either a physical memory address or an i/o address. exclusive state. mei state (e) in which only one caching de vice contains data that is also in system memory. f fetch. retrieving instructions from either the cache or main memory and placing them into the instruction queue. flush. an operation that causes a cache block to be invalidated and th e data, if modified, to be written to memory. frame-check sequence (fcs). specifies the standard 32-bit cyclic redundancy check (crc) obtained using the standard ccit t-crc polynomial on all fields except the preamble, sfd, and crc. g general-purpose register (gpr). any of the 32 registers in the general-purpose register file. these registers provide the source operands and de stination results for all integer data manipulation instructions. inte ger load instructions move data from memory to gprs and store instructi ons move data from gprs to memory. gigabit media-independent interface (gmii) sublayer. sublayer that provides a standard interface between the mac laye r and the physical layer for 1000-mbps operation. it isolates the mac layer an d the physical layer, enabling the mac layer to be used with various im plementations of the physical layer. guarded. the guarded attribute pertains to out-of-order execution. when a page is designated as guarded, instructions a nd data cannot be accessed out-of-order. h harvard architecture. an architectural model featuri ng separate caches and other memory management resources for instructions and data. i illegal instructions. a class of instructions that are not implemented for a particular processor. these include in structions not defi ned by the architecture. in addition, for 32-bit implementations , instructions that are defined only for 64-bit implementations are considered to be illegal instructions. for 64-bit implementations instructions that are de fined only for 32-bit implementations are considered to be illegal instructions. 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 glossary-4 freescale semiconductor implementation. a particular processor that conforms to the architecture, but may differ from other architecture-comp liant implementations for example in design, feature set, and implementation of optional features. inbound atmu windows. mappings that perform address tr anslation from the external address space to the local addr ess space, attach attributes and transaction types to the transaction, and map the tran saction to its target interface. in-order. an aspect of an operation that adheres to a sequential model. an operation is said to be performed in-order if, at the ti me that it is performed, it is known to be required by the sequential execution model. integer unit. an execution unit in the core responsib le for executing integer instructions. inter-packet gap. the gap between the end of one et hernet packet and the beginning of the next transmitted packet. instruction latency. the total number of clock cycles n ecessary to execute an instruction and make ready the results of that instruction. k kill. an operation that causes a cache block to be invalidated wit hout writing any modified data to memory. l l2 cache. level-2 cache. see secondary cache . latency. the number of clock cycles necessary to execute an instruction and make ready the results of that execution for a subsequent instruction. least-significant bit (lsb). the bit of least value in an address, register, field, data element, or instruction encoding. least-significant byte (lsb). the byte of least value in an ad dress, register, data element, or instruction encoding. little-endian. a byte-ordering method in memory where the address n of a word corresponds to the least-significant byte . in an addressed me mory word, the bytes are ordered (left to right) 3, 2, 1, 0, with 3 being the most-significant byte . see big endian . local access window. mapping used to translate a region of memory to a particular target interface, such as the ddr sdram contro ller or the pci controller. the local memory map is defined by a set of eigh t local access windows. the size of each window can be configured fr om 4 kbytes to 2 gbytes. m media access control (mac) sublayer. sublayer that provides a logical connection between the mac and its peer station. its primary respons ibility is to initialize, control, and manage the connection with the peer station. 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor glossary-5 media-independent interface (mii) sublayer. sublayer that provides a standard interface between the mac layer a nd the physical laye r for 10/100-mbps operations. it isolates the mac layer a nd the physical layer, enabling the mac layer to be used with various im plementations of the physical layer. medium-dependent interface (mdi) sublayer. sublayer that define s different connector types for different physical media and pmd devices. memory access ordering. the specific order in which th e processor performs load and store memory accesses and the order in which those accesses complete. memory-mapped accesses. accesses whose addresses use the page or block address translation mechanisms provided by the mm u and that occur externally with the bus protocol defined for memory. memory coherency. an aspect of caching in which it is ensured th at an accurate view of memory is provided to all devi ces that share system memory. memory consistency. refers to agreement of levels of memory with respect to a single processor and system memory (for exampl e, on-chip cache, secondary cache, and system memory). memory management unit (mmu). the functional unit that is capable of translating an effective (logical) address to a physical addre ss, providing protection mechanisms, and defining caching methods. modified/exclusive /invalid (mei). cache coherency protocol used to manage caches on different devices that share a memory system. note that the powerpc architecture does not specify the implementation of a me i protocol to ensure cache coherency. modified state. mei state (m) in which one, and only one, caching device has the valid data for that address. the data at this address in external memory is not valid. most-significant bit (msb). the highest-order bit in an addres s, registers, data element, or instruction encoding. most-significant byte (msb). the highest-order byte in an address, registers, data element, or instruction encoding. n nan. an abbreviation for not a number; a sym bolic entity encoded in floating-point format. there are two types of na ns?signaling nans and quiet nans. no-op. no-operation. a single-cycle ope ration that does not affect registers or generate bus activity. 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 glossary-6 freescale semiconductor o ocean. (on-chip network) non-bloc king crossbar switch fabric . enables full duplex port connections at 128gb/s c oncurrent throughput and independent per port transaction queuing and flow control. pe rmits high bandwidth, high performance, as well as the execution of multiple data transactions. outbound atmu windows. mappings that perform addres s translations from local 32-bit address space to the a ddress spaces of pci, which may be much larger than the local space. outbound atmu windows also map attributes su ch as transaction type or priority level. p packet. a unit of binary data that can be rout ed through a network. sometimes packet is used to refer to the frame plus the pr eamble and start frame delimiter (sfd). page. a region in memory. the oea defines a page as a 4-kbyt e area of memory aligned on a 4-kbyte boundary. page access history bits. the changed and referenced bits in the pte keep track of the access history within the page. the refe renced bit is set by the mmu whenever the page is accessed for a read or write operation. the changed bit is set when the page is stored into. see changed bit and referenced bit . page fault. a page fault is a condition that occurs when the processor attempts to access a memory location that does not reside within a page not currently resident in physical memory . a page fault exception conditi on occurs when a matching, valid page table entry (pte[v] = 1) cannot be located. page table. a table in memory is comprised of page table entries , or ptes. it is further organized into eight ptes per pteg (page table entry group). the number of ptegs in the page table depends on the size of the page table (as specified in the sdr1 register). page table entry (pte). data structures containing information used to translate effective address to physical address on a 4- kbyte page basis. a pte consists of 8 bytes of information in a 32-bit proces sor and 16 bytes of informa tion in a 64-bit processor. physical coding sublayer (pcs). sublayer responsible for encoding and decoding data stream to and from the mac sublayer . medium (1000basex) 8b/10b coding is used for fiber. medium (1000baset) 8b1q coding is used for unshielded twisted pair (utp). 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor glossary-7 physical medium attachment (pma) sublayer. sublayer responsible for serializing code groups into a bit stream suit able for serial b it-oriented physical devices (serdes) and vice versa. synchronizatio n is also performed for proper data decoding in this sublayer. the pma sits between the pc s and the pmd sublayers. for fiber medium (1000basex) the in terface on the pmd side of the pma is a one-bit 1250 mhz signal, while on the pma?s pcs side the interface is a ten-bit interface (tbi) at 125 mhz. the tbi is an alternative to the gmii interface. if the tbi is used the gigabit ethernet controller must be capable of performing the pcs function. for utp medium, the pmd interfac e side of the pma consists of four pair of 62.5-mhz pam5 encoded signals , while the pcs side provides the 1250-mbps input to a 8b1q4 pcs. physical medium depe ndent (pmd) sublayer. sublayer responsible for signal transmission. the typical pm d functionality includes am plifier, modulation, and wave shaping. different pmd de vices may support different media. physical memory. the actual memory that can be ac cessed through the system?s memory bus. pipelining. a technique that breaks operations, such as instruction processing or bus transactions, into smaller distinct stages or tenures (respectively) so that a subsequent operation can begin before the previous one has completed. primary opcode. the most-significant 6 bits (bits 0?5) of the instruction encoding that identifies the type of instruction. program order. the order of instructions in an exec uting program. more specifically, this term is used to refer to the original orde r in which program inst ructions are fetched into the instruction queue from the cache. protection boundary. a boundary between protection domains . protection domain. a protection domain is a segment, a virtual page, a bat area, or a range of unmapped effective addresses. it is defined only when the appropriate relocate bit in the msr (ir or dr) is 1. q quad word. a group of 16 contiguous locations star ting at an address divisible by 16. quiesce. to come to rest. the proce ssor is said to quiesce when an exception is taken or a sync instruction is executed. the instruction stream is stopped at the decode stage and executing instructions ar e allowed to complete to create a cont rolled context for instructions that may be affected by out-of-order, parallel execution. see context synchronization . r ra. the r a instruction field is used to specify a gp r to be used as a s ource or destination. rb. the r b instruction field is used to speci fy a gpr to be used as a source. 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 glossary-8 freescale semiconductor rd. the r d instruction field is used to specify a gpr to be used as a destination. rs. the r s instruction field is used to spec ify a gpr to be used as a source. record bit. bit 31 (or the rc bit) in the instructi on encoding. when it is set, updates the condition register (cr) to refl ect the result of the operation. reconciliation sublayer. sublayer that maps the termi nology and commands used in the mac layer into electrical formats appropr iate for the physical layer entities. reduced instruction set computing (risc). an architecture characterized by fixed-length instructions with nonoverlapping functionali ty and by a separate set of load and store instructions that perform memory accesses. referenced bit. one of two page history bits found in each page table entry . the processor sets the referenced bit whenever the page is acces sed for a read or write. see also page access history bits . reservation. the processor establishes a reservation on a cache block of memory space when it executes an lwarx instruction to read a me mory semaphore into a gpr. reservation station. a buffer between the dispatch and execute stages that allows instructions to be dispatched even though the results of instructions on which the dispatched instruction may depend are not available. s secondary cache. a cache memory that is typically larger and has a longer access time than the primary cache. a secondary cach e may be shared by multiple devices. also referred to as l2, or level-2, cache. set ( v ) . to write a nonzero valu e to a bit or bit fi eld; the opposite of clear . the term ?set? may also be used to generally descri be the updating of a bit or bit field. set ( n ) . a subdivision of a cache . cacheable data can be stored in a given location in one of the sets, typically corresponding to its lower-order address bits. because several memory locations can map to the same loca tion, cached data is typically placed in the set whose cache block corresponding to that address was used least recently. see set-associative . set-associative. aspect of cache organization in whic h the cache space is divided into sections, called sets . the cache controller associates a particular main memory address with the contents of a partic ular set, or region, within the cache. slave. the device addressed by a master device. the slave is identified in the address tenure and is responsible for supplying or latching the requested data for the master during the data tenure. snooping. monitoring addresses driven by a bus master to detect the need for coherency actions. 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor glossary-9 snoop push. response to a snooped transaction that hits a modified cache block. the cache block is written to memory a nd made available to the snooping device. stall. an occurrence when an instruction cannot proceed to the next stage. sticky bit. a bit that when set must be cleared explicitly. superscalar machine. a machine that can issue multiple instructions concurrently from a conventional linear instruction stream. supervisor mode. the privileged operation state of a processor. in supervisor mode, software, typically the operating system, can access all control registers and can access the supervisor memory space, among other privileged operations. synchronization. a process to ensure that operations occur strictly in order . see context synchronization . system memory. the physical memory available to a processor. t tenure. the period of bus mastership . there can be separate ad dress bus tenures and data bus tenures. throughput. the measure of the number of instruct ions that are processed per clock cycle. time-division multiplex (tdm). a single serial channel used by several channels taking turns. transaction. a complete exchange between two bus devices. a transaction is typically comprised of an address te nure and one or more data tenures, which may overlap or occur separately from the address tenure. a transaction may be minimally comprised of an address tenure only. transfer termination. signal that refers to both signals that acknow ledge the transfer of individual beats (of both single-beat tran sfer and individual beats of a burst transfer) and to signals that mark the end of the tenure. translation lookaside buffer (tlb). a cache that holds recently-used page table entries . u user mode. the operating state of a processor used typically by application software. in user mode, software can access only certa in control register s and can access only user memory space. no privileged operations can be performed. also referred to as problem state. 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 glossary-10 freescale semiconductor v virtual address. an intermediate address used in the translation of an effective address to a physical address. virtual memory. the address space created using the memory management facilities of the processor. program access to virtual memory is possible only when it coincides with physical memory . w way. a location in the cache that holds a cache block, its tags, and status bits. word. a 32-bit data element. write-back. a cache memory update policy in which processor write cycles are directly written only to the cache. external me mory is updated only indirectly, for example, when a modified cache block is cast out to make room for newer data. write-through. a cache memory update policy in whic h all processor write cycles are written to both the cache and memory. 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor index 1-1 index 1 register index (memory-mapped registers) a aesuicr (sec aesu interrupt control register), 17-73 aesuisr (sec aesu interrupt status register), 17-72 aesuksr (sec aesu key size register), 17-69 aesumr (sec aesu mode register), 17-67 aesurcr (sec aesu reset co ntrol register), 17-70 aesusr (sec aesu status register), 17-71 afeu context memory pointer registers, 17-51 afeu context memory registers, 17-50 afeudsr (sec afeu contex t/data size register), 17-44 afeuemr (sec afeu end of message register), 17-50 afeuicfr (sec afeu interrupt control register), 17-48 afeuisr (sec afeu interrupt status register), 17-47 afeuk0?1 (sec afeu ke y registers 0-1), 17-51 afeuksr (sec afeu key size register), 17-43 afeumr (sec afeu mode register), 17-42 afeurcr (sec afeu reset co ntrol register), 17-45 afeusr (sec afeu status register), 17-46 altcar (alternate configuratio n attribute address register), 4-6 altcbar (alternate configuration base address register), 4-6 ana (tsec an advertisem ent register), 14-90 anlpanp (tsec an link partner ability next page register), 14-95 anlpbpa (tsec an link partner base page ability register), 14-92 annpt (tsec an next page transmit register), 14-94 attr (tsec attribute register), 14-85 attreli (tsec attribute extract length and extract index register), 14-87 b bcr n (dma 0-3 byte count registers), 15-17 bptr (boot page translation register), 4-7 br n (lbc base registers 0?7), 13-10 c cam1 (tsec carry mask register 1), 14-82 cam2 (tsec carry mask register 2), 14-83 capture_address (ddr memo ry error address capture register), 9-23 capture_attributes (ddr memory error attributes capture register), 9-22 capture_data_hi (ddr memory data path read capture high register), 9-19 capture_data_lo (ddr memory data path read capture low register), 9-19 capture_ecc (ddr memory data path read capture ecc register), 9-20 car1 (tsec carry register 1), 14-79 car2 (tsec carry register 2), 14-80 cccr (sec crypto-channel conf iguration regi ster), 17-81 ccidr (current context id register), 20-22 ccpsr (sec crypto-channel pointer status register), 17-83 ccsrbar (configuration, control, and status registers base address register), 4-4?4-5 cdpr (sec crypto-channel current descriptor pointer register), 17-89 cfg_addr (pci/x configurati on address register), 16-17 cfg_data (pci/x configurat ion data register), 16-18 cisr0 (pic critical interrupt summary register 0), 10-26 cisr1 (pic critical interrupt summary register 1), 10-26 clkocr (clock out sel ect register), 18-19 clndar n (dma 0?3 current link descriptor address registers), 15-12 clsdar n (dma 0?3 current list-alternate base descriptor address registers), 15-18 cr (tsec control register), 14-88 crbptr (tsec current receive buffer descriptor pointer register), 14-42 cs n bnds (ddr chip select 0?3 bounds registers), 9-9 cs n config (ddr chip select 0?3 configuration registers), 9-10 ctbptr (tsec current transmit buffer descriptor pointer register), 14-35 ctpr0 (pic per-cpu processo r current task priority) also mapped as global ctpr, 10-38 d dar n (dma 0?3 destination address registers), 15-16 data_err_inject_hi (ddr memory data path error injection mask high register), 9-17 data_err_inject_lo (ddr memory data path error injection mask low register), 9-17 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 index 1-2 freescale semiconductor e?i index 1 register index (memory-mapped registers) datr n (dma 0?3 destination attributes registers), 15-16 ddr_sdram_cfg (ddr sdram control configuration register), 9-13 ddr_sdram_interval (ddr sdram interval configuration register), 9-15 ddr_sdram_mode (ddr sdram mode configuration register), 9-14 deudsr (sec deu data size register), 17-35 deueug (sec deu eu-go register), 17-41 deuicr (sec deu interrupt control register), 17-39 deuisr (sec deu interrupt status register), 17-38 deuiv (sec deu iv register), 17-41 deuk1?3 (sec deu key registers 1?3), 17-41 deuksr (sec deu key size register), 17-34 deumr (sec deu mode register), 17-33 deurcr (sec deu reset control register), 17-36 deusr (sec deu status register), 17-37 devdisr (device disable control), 18-14 dgsr (dma general status register), 15-21 dmactrl (tsec dma control register), 14-27 dsr n (dma 0?3 destination stride registers), 15-20 e ecc_err_inject (ddr memory data path error injection mask ecc register), 9-18 ecntrl (tsec ethernet control register), 14-25 edis (tsec error disabled register), 14-24 eeadr (ecm error address capture register), 8-7 eeatr (ecm error attributes capture register), 8-6 eebacr (ecm ccb address conf iguration register), 8-3 eebpcr (ecm ccb port config uration register), 8-4 eedr (ecm error det ect register), 8-4 eeer (ecm error enab le register), 8-5 eidr n (pic external interrupt destination registers 0?11), 10-31 eivpr n (pic external interrupt vector/priority registers 0?11), 10-30 eoi0 (pic per-cpu processor end of interrupt register) also mapped as global eoi, 10-40 err_addr (pci/x error address capture register), 16-33 err_attrib (pci/x error attributes register), 16-32 err_cap_dr (pci/x error captu re disable register), 16-30 err_detect (ddr memory error detect register), 9-20 err_dh (pci/x error data hi gh capture register), 16-34 err_disable (ddr memory er ror disable register), 9-21 err_dl (pci/x error data low capture register), 16-33 err_dr (pci/x error detect register), 16-29 err_en (pci/x error enable register), 16-31 err_ext_addr (pci/x erro r extended address capture register), 16-33 err_int_en (ddr memory error interrupt enable register), 9-22 err_sbe (ddr single-bit ecc memory error management register), 9-24 exst (tsec extended status register), 14-96 f fifo_tx_starve (tsec fifo tr ansmit starve register), 14-31 fifo_tx_starve_shutoff (tsec fifo transmit starve shutoff register), 14-31 fifo_tx_thr (tsec fifo transmit threshold register), 14-30 frr (pic feature reporting register), 10-15 g gaddr n (tsec group address registers 0?7), 14-85 gas_timr (pci/x gasket timer register), 16-35 gcr (pic global configuration register), 10-15 gpindr (general-purpose in put data register), 18-12 gpiocr (gpio control register), 18-10 gpoutdr (general-purpose outp ut data register), 18-11 gpporcr (general-pur pose por configuration register), 18-9 gtbcr n (pic global timer 0?3 base count registers), 10-20 gtccr n (pic global timer 0?3 current count registers), 10-19 gtdr n (pic global timer 0?3 destination registers), 10-21 gtvpr n (pic global timer 0?3 vector/priority registers), 10-20 h hafdup (tsec half-duplex register), 14-50 i i2cadr (i 2 c address register), 11-5 i2ccr (i 2 c control register), 11-7 i2cdfsrr (i 2 c digital filter sampling rate register), 11-11 i2cdr (i 2 c data register), 11-10 i2cfdr (i 2 c frequency divider register), 11-6 i2csr (i 2 c status register), 11-9 iack0 (pic per-cpu proces sor interrupt acknowledge register) also mapped as global iack, 10-39 iaddr n (tsec individual address registers 0?7), 14-84 icr (sec interrupt clear register), 17-95 id (sec id register), 17-97 ievent (tsec interrupt event register), 14-19 4 datasheet u .com
index 1 register index (memory-mapped registers) j?m MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor index 1-3 ifstat (tsec interface status register), 14-56 iidpr n (pic internal interrupt destination registers 0?31), 10-33 iivpr n (pic internal interrupt vector/priority registers 0?31), 10-32 imask (tsec interrupt mask register), 14-22 imr (sec interrupt mask register), 17-93 int_ack (pci/x interrupt acknowledge register), 16-19 ipgifg (tsec inter-packet ga p/inter-frame gap register), 14-49 ipidr n (pic per-cpu interprocessor interrupt dispatch registers 0?3), 10-37 ipivpr n (pic ipi vector/priority registers 0?3), 10-17 irqsr0 (pic irq_out summary register 0), 10-24 irqsr1 (pic irq_out summary register 1), 10-25 isr (sec interrupt status register), 17-94 j jd (tsec jitter diagnostics register), 14-97 l l2captdatahi (l2 error capture data high register), 7-14, 7-15 l2captdatalo (l2 error capture data low register), 7-14, 7-15 l2captecc (l2 error syndrom e register), 7-12, 7-15 l2cewar n (l2 cache external write address registers 0?3), 7-10 l2cewcr n (l2 cache external write control registers 0?3), 7-10 l2ctl (l2 control register), 7-7 l2erraddr (l2 error address cap ture register), 7-14, 7-19 l2errattr (l2 error attributes capture register), 7-14, 7-18 l2errctl (l2 error control register), 7-14, 7-20 l2errdet (l2 error detect register), 7-14, 7-16 l2errdis (l2 error disable register), 7-14, 7-17 l2errinjctl (l2 error injecti on mask control register), 7-12, 7-14 l2errinjhi (l2 error injection mask high register), 7-12, 7-13 l2errinjlo (l2 error injection mask low register), 7-12, 7-13 l2errinten (l2 error interrupt enable register), 7-14, 7-17 l2srbar n (l2 memory-mapped sram base address registers 0?1), 7-11 lawar n (local access window 0?7 at tributes registers), 2-6 lawbar n (local access window 0?7 base address registers), 2-5 lbcr (lbc configurati on register), 13-29 lbdllcr (lbc dll control register), 18-20 lcrr (lbc clock ratio register), 13-31 lsdmr (lbc sdram mode register), 13-21 lsrt (lbc sdram refresh timer), 13-24 ltear (lbc transfer error address register), 13-29 lteatr (lbc transfer error at tributes register), 13-28 ltedr (lbc transfer error disable register), 13-26 lteir (lbc transfer error interrupt register), 13-27 ltesr (lbc transfer error status register), 13-25 lurt (upm refresh timer), 13-23 m maccfg1 (tsec mac configuration register 1), 14-47 maccfg2 (tsec mac configuration register 2), 14-48 macstnaddr1 (tsec station address part 1 register), 14-56 macstnaddr2 (tsec station address part 2 register), 14-57 mar (upm address register), 13-17 maxfrm (tsec maximum frame length register), 14-51 mcpsumr (machine check su mmary register), 18-17 mcr (sec master control register), 17-98 mdeu context registers, 17-59 mdeu key registers, 17-60 mdeudsr (sec mdeu data size register), 17-54 mdeueug (sec mdeu eu-go register), 17-58 mdeuicr (sec mdeu interrupt control register), 17-57 mdeuisr (sec mdeu interrupt status register), 17-56 mdeuksr (sec mdeu key size register), 17-53 mdeumr (sec mdeu mode register), 17-51 mdeurcr (sec mdeu reset control register), 17-54 mdeusr (sec mdeu status register), 17-55 mdr (upm data register), 13-21 mer (pic message enable register), 10-29 midr n (pic messaging interrupt destination registers 0?3), 10-35 miimadd (tsec mii management address register), 14-53 miimcfg (tsec mii management configuration register), 14-52 miimcom (tsec mii management command register), 14-53 miimcon (tsec mii management control register), 14-54 miimind (tsec mii management indicator register), 14-55 miimstat (tsec mii management status register), 14-55 minflr (tsec minimum fram e length register), 14-26 mivpr n (pic messaging interrupt vector/priority registers 0?3), 10-34 mrblr (tsec maximum receive buffer length register), 14-42 mr n (dma 0?3 mode registers), 15-9 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 index 1-4 freescale semiconductor n?r index 1 register index (memory-mapped registers) mrtpr (lbc memory refresh timer prescaler register), 13-20 msgr n (pic message registers 0?3), 10-28 msr (pic message status register), 10-29 mxmr (lbc upm a?c mode registers), 13-18?13-20 n nlndar n (dma 0?3 next link descriptor address registers), 15-17 nlsdar n (dma 0-3 next list descriptor address register), 15-19 o orn (lbc options registers 0?7), 13-12?13-17 ostbd (tsec out-of-sequence txbd register), 14-36 ostbdp (tsec out-of-sequence tx data buffer pointer register), 14-38 p pci configuration header registers see general index, 16-35 pcidr (programmed context id register), 20-22 pir (pic processor initialization register), 10-16 pitar n (pci/x inbound translation address registers 1?3), 16-24 piwar n (pci/x inbound window attributes registers 1?3), 16-26 piwbar n (pci/x inbound window base address registers 1?3), 16-25 piwbear n (pci/x inbound window base extended address registers 1?3), 16-26 pkeuabsr (sec pkeu ab size register), 17-26 pkeudsr (sec pkeu data size register), 17-27 pkeueug (sec pkeu eu-go register), 17-32 pkeuicr (sec pkeu interrupt control register), 17-31 pkeuisr (sec pkeu interrupt status register), 17-30 pkeuksr (sec pkeu key size register), 17-26 pkeumr (sec pkeu mode register), 17-25 pkeurcr (sec pkeu reset co ntrol register), 17-28 pkeusr (sec pkeu status register), 17-29 pmc n (performance monitor counters 0?8), 19-9 pmgc0 (performance monitor global control register 0), 19-5 pmlca0 (performance monitor lo cal control register a 0), 19-6 pmlcan (performance monitor local control registers a 1?8), 19-6 pmlcb0 (performance monitor local control register b 0), 19-7 pmlcb n (performance monitor lo cal control registers b 1?8), 19-8 pmnmr0 (pic performance monitor 0?3 mask registers (lower)), 10-27 pmnmr1 (pic performance monitor 0?3 mask registers (upper)), 10-28 pmuxcr (alternate function signal multiplex control), 18-13 porbmsr (por boot mode status register), 4-13, 4-14, 18-5 pordbgmsr (por debug mode status register), 4-18, 4-19, 18-8 pordevsr (por i/o device status register), 4-15, 4-16, 4-17, 4-18, 18-7, b-3 porimpscr (por i/o impedance status and control register), 4-17, 18-6 porpllsr (por pll ratio status register), 4-11, 4-12, 18-4 potar n (pci/x outbound translation address registers 0?4), 16-20 potear n (pci/x outbound translation extended address registers 0?4), 16-20 powar n (pci/x outbound window attributes registers 0?4), 16-22 powbar n (pci/x outbound window base address registers 0?4), 16-21 powmgtcsr (power management status and control register), 18-16 ptv (tsec pause time value register), 14-26 pvr (processor version register), 18-18 r raln (tsec receive alignm ent error counter), 14-65 rbase (tsec receive descriptor base address register), 14-44 rbca (tsec receive broadcast packet counter register), 14-63 rbdlen (tsec rxbd data length register), 14-40 rbptr (tsec receive buffer de scriptor pointer register), 14-43 rbyt (tsec receive byte counter), 14-61 rcde (tsec receive code erro r counter register), 14-66 rcse (tsec receive carrier sens e error counter register), 14-67 rctrl (tsec receive cont rol register), 14-39 rdrp (tsec receive dropped packet counter register), 14-69 rflr (tsec receive frame lengt h error counter register), 14-66 rfrg (tsec receive fragment s counter register), 14-68 rjbr (tsec receive jabber counter register), 14-69 4 datasheet u .com
index 1 register index (memory-mapped registers) s?u MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor index 1-5 rmca (tsec receive multicas t packet counter), 14-63 rngdsr (sec rng data size register), 17-62 rngeug (sec rng eu-go register), 17-66 rngicr (sec rng interrupt control register), 17-65 rngisr (sec rng interrupt status register), 17-64 rngmr (sec rng mode register), 17-61 rngrcr (sec rng reset control register), 17-63 rngsr (sec rng status register), 17-63 rovr (tsec receive oversi ze packet counter), 14-68 rpkt (tsec receive packet counter), 14-62 rstat (tsec receive status register), 14-40 rund (tsec receive undersize packet counter register), 14-67 rxcf (tsec receive control fram e packet counter register), 14-64 rxic (tsec receive interrup t coalescing configuration register), 14-41 rxpf (tsec receive pause fram e packet counter register), 14-64 rxuo (tsec receive unknown opcode packet counter register), 14-65 s sar n (dma 0?3 source address registers), 15-15 satr n (dma 0?3 source attributes registers), 15-14 sr (tsec status register), 14-89 sr n (dma 0?3 status registers), 15-11 ssr n (dma 0?3 source stride registers), 15-19 svr (pic spurious vector register), 10-18 svr (system version register), 18-19 t tbacr (trace buffer access control register), 20-20 tbadhr (trace buffer access data high register), 20-21 tbadr (trace buffer access data register), 20-21 tbamr (trace buffer address mask register), 20-18 tbar (trace buffer address register), 20-18 tbase (tsec transmit descriptor base address register), 14-36 tbca (tsec transmit broadcast packet counter register), 14-71 tbcr n (trace buffer control registers 0?1), 20-15 tbdlen (tsec txbd data length register), 14-34 tbicon (tsec tbi control register), 14-98 tbipa (tsec tbi physical address register), 14-28 tbptr (tsec transmit buffer descriptor pointer register), 14-35 tbsr (trace buffer status register), 20-19 tbtmr (trace buffer transact ion mask register), 20-18 tbyt (tsec transmit byte counter register), 14-70 tcr (pic timer control register), 10-22 tctrl (tsec transmit control register), 14-32 tdfr (tsec transmit deferr al packet counter), 14-72 tdrp (tsec drop frame c ounter register), 14-76 tedf (tsec transmit excessive deferral packet counter register), 14-73 tfcs (tsec transmit fcs error counter register), 14-77 tfrg (tsec transmit fragmen t counter register), 14-79 tfrr (pic timer frequency reporting register), 10-19 timing_cfg_1 (ddr sdram timing configuration register 1), 9-11 timing_cfg_2 (ddr sdram timing configuration register 2), 9-12 tjbr (tsec jabber frame c ounter register), 14-76 tmca (tsec transmit multicast packet counter register), 14-71 tncl (tsec transmit total collision counter register), 14-75 tosr (trigger output source register), 20-23 tovr (tsec transmit oversi ze frame counter register), 14-78 tpkt (tsec transmit packet counter register), 14-70 tr127 (tsec transmit and r eceive 65- to 127-byte frame counter register), 14-58 tr1k (tsec transmit and recei ve 512- to 1023-byte frame counter register), 14-60 tr255 (tsec transmit and recei ve 128- to 255-byte frame counter register), 14-59 tr511 (tsec transmit and recei ve 256- to 511-byte frame counter register), 14-59 tr64 (tsec transmit and recei ve 64-byte frame counter register), 14-58 trmax (tsec transmit and receive 1024- to 1518-byte frame counter register), 14-60 trmgv (tsec transmit and receive 1519- to 1522-byte vlan frame counter register), 14-61 tscl (tsec transmit single collision packet counter register), 14-73 tstat (tsec transmit status register), 14-33 tund (tsec transmit undersi ze frame counter register), 14-78 txcf (tsec transmit control fr ame counter register), 14-77 txcl (tsec excessive collisio n packet counter register), 14-75 txic (tsec transmit interrup t coalescing configuration register), 14-34 txpf (tsec transmit pause cont rol frame counter register), 14-72 u uafr n (duart alternate functi on registers 0?1), 12-17 udlb n (duart divisor least significant byte registers 0?1), 12-7 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 index 1-6 freescale semiconductor v?w index 1 register index (memory-mapped registers) udmb n (duart divisor most significant byte registers 0?1), 12-7 udsr n (duart dma status registers 0?1), 12-6, 12-18 ufcr n (duart fifo control registers 0?1), 12-11 uier (duart interrupt en able register), 12-9 uiir n (duart interrupt id registers 0?1), 12-9 ulcr n (duart line control registers 0?1), 12-12 ulsr n (duart line status registers 0?1), 12-14 umcr n (duart modem control registers 0?1), 12-14 umsr n (duart modem status registers 0?1), 12-16 urbr n (duart receiver buffer registers 0?1), 12-2, 12-6 uscr n (duart scratch registers 0?1), 12-17 uthr n (duart transmitter holdin g registers 0?1), 12-2, 12-6 v vir (pic vendor id register), 10-16 w whoami0 (pic per-cpu who am i register?p0) also mapped as global whoami, 10-39 wmamr (watchpoint monitor addr ess mask register), 20-13 wmar (watchpoint monitor address register), 20-12 wmcr n (watchpoint monitor control registers 0?1), 20-10 wmsr (watchpoint monitor status register), 20-15 wmtmr (watchpoint monitor tr ansaction mask register), 20-13 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor index 2-1 index 2 general index a accumulator (acc), 6-46 address maps addressing on pci bus, 16-54 device address map overview, 1-20 address mask (lbc), 13-12 address multiplexing (lbc sdram), 13-51 address translation and mapping units (atmus) inbound windows, 2-8 illegal interactions between inbound atmus and local access windows, 2-8 pci/pci-x?4 windows, 2-8 pci?4 windows, 16-23 local access windows, 2-3?2-8 see also local access windows outbound windows, 2-8 pci?4 windows, 16-19 processing across the ocean fabric, 1-22 addressing pci bus addressing, 16-55 configuration space, 16-55 i/o space, 16-55 memory space, 16-54 advanced encryption standa rd execution unit (aesu), 17-67?17-80 see also data encryption standard execution unit (deu) see also security engine (sec) alignment, byte (pci), 16-56 application examples pin configurations, 1-24 arbitration i 2 c interface arbitration control, 11-15 loss of arbitration?forcing of slave mode, 11-23 procedure for arbitration, 11-15 arbitration (pci ), 16-5, 16-49 arc four execution unit (afeu), 17-42?17-51 context memory, 17-50 fifos, 17-51 see also security engine (sec) asleep (global utilities asleep) signal, 18-2, 18-24 atmus, see address translation and mapping units b baud-rate generator (brg) memory map, 2-46, a-13 bbear (branch buffer address register), see e500 core, registers bbtar (branch buffer target address register), see e500 core, registers block diagrams communications processor module (cpm), 1-13, a-8 ddr controller, 9-1, 9-24 debug modes, watchpoint m onitor, and trace buffer, 20-1 dma controller, 15-1 duart, 12-2 e500 coherency module (ecm), 8-1 i 2 c interface, 11-1 interrupt controller (pic), 10-1, 10-41 l2 cache/sram, 7-1 local bus contro ller (lbc), 13-1 pci controller, 16-1 performance monitor, 19-2 tsec, 14-5 boot mode cpu holdoff (por), 4-14, 8-4 por status register (porbmsr), 18-5 boot page translation, 4-7 boot rom location (por), 4-12 boot sequencer boot holdoff mode (por), 4-14, 8-4 boot page translation, 4-7 i 2 c interface, 11-2, 11-17?11-19 overview, 1-17, 4-8 por configuration, 4-14 bucsr (branch unit control and status register), see e500 core, registers buffer descriptors see tsec, buffer descriptors burst operations (pci) see pci controller, bus protocol bus operations pci, see pci controller, bus protocol byte alignment (pci), 16-56 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 index 2-2 freescale semiconductor c?d index 2 general index c chaining performance monitor events, 19-25 ckstp_in (global utilities checkstop in) signal, 18-2 ckstp_out (global utilities checkstop out) signal, 18-3 clk_out (global utilities clock out) signal, 18-3, 18-19 clocks clock out (clk_out), see global utilities ddr clock distribution, 9-36 device clock signals summary, 4-2 see also signals, clock device clocking operation, 4-21?4-23 ccb (platform) clock, 4-21 ethernet clocks, 4-22 overview, 1-20 system clock/pci clock, 4-21 i 2 c clock stretching, 11-17 clock synchronization, 11-16 input synchronization and digital filter, 11-16 lbc bus clocks and clock ratios, 13-3 clock ratio register (lcrr), 13-31 pci clocking, 16-52, 16-57 por settings e500 core pll ratio, 4-12 system/ccb pll ratio, 4-11 tsec inputs and outputs, 14-10 management clock out (ec_mdc), 14-52 coherency rules l2 cache, 7-22 commands pci, see pci controller communications processor (cp) memory map, a-13 communications processor module (cpm) block diagram, 1-13, a-8 communications protocol table, 1-24 compatibility issues, 1-23 data processing overview, 1-20 external interrupts on port c and sleep mode, 10-3, 18-24 overview, 1-13 performance, 1-24 see also cpm index timers memory map, 2-43, a-11 configuration ddr, 9-9?9-16, 9-27 ecm ccb address configuration register (eebacr), 8-3 ccb port configuration re gister (eebpcr), 8-4 lbc configuration register (lbcr), 13-29 sdram configurations supported, 13-49 pci configuration cycles, 16-65 configuration space header, 16-65 host accessing pci config uration space, 16-67, b-49 pic global configuration register, 10-15 por, see power-on-reset (por) tsec interfaces, 14-126?14-144 configuration space pci addressing, 16-55 configuration, c ontrol, and status accessing ccsr memory from external masters, 2-10 accessing ccsrs, 4-4 alternate configuration sp ace (altbar and altcar), 4-5 boot page translation, 4-7 ccsr and communications processor module (cpm), 2-13 ccsr memory map, 2-8?2-14 ccsrbar update guidelines, 4-4 memory map/register definition, 4-3 organization of ccsr memory, 2-10 context id registers, 20-22?20-23 conventions notational, cxiv cpm mux memory map, 2-50, a-14 cr (condition register), see e500 core, registers crypto-channel registers, 17-81?17-91 csrr0?1 (critical save/restore registers 0?1), see e500 core, registers ctr (count register), see e500 core, registers cts , see duart_cts [0:1] d dac n (data address comp are registers 1?2), see e500 core, registers data cache, see l2 cache/sram data encryption standard execution unit (deu), 17-33 fifos, 17-42 see also security engine (sec) data processing with the e500 coherency module (ecm), 1-23 dbcr n (debug control register 0?2), see e500 core, registers dbsr (debug status register), see e500 core, registers ddr controller address signal mappings, 9-4 block diagram, 9-1, 9-24 4 datasheet u .com
index 2 general index d?d MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor index 2-3 clock distribution, 9-36 configuration, example, 9-27 data beat ordering, 9-42 debug mode signal selection (por), 4-19 source and target id, 20-24 error checking and co rrecting (ecc), 9-44 testing ecc with error injection, 9-17?9-18 error handling, 9-19, 9-46 features, 9-2 functional description, 9-24 initialization/application information, 9-46 interrupts, 9-22 memory map, 9-8 modes of operation, 9-3 overview, 1-16 page mode and logical bank retention, 9-43 performance monitor events, 19-15 register descriptions, 9-9 by acronym, see register index configuration registers, 9-9?9-16 error handling registers, 9-19?9-24 error injection regi sters, 9-17?9-18 sdram operation, 9-29 address multiplexing, 9-30 initialization sequence, 9-47 jedec standard inte rface commands, 9-31 mode-set command timing, 9-37 organizations supported, 9-29 refresh operation, 9-39 power-saving modes, 9-41 timing, 9-40 registered dimm mode, 9-38 timing, 9-33 write timing adjustments, 9-38 self-refresh in sleep mode, 9-42 signals summary, 9-3 see also signals, ddr dear (data exception address register), see e500 core, registers debug modes and watchpoint monitor signals summary, 20-5 see also signals, debug and watchpoint monitor/trace buffer block diagram, 20-1 ddr signal selection (por) ecc pins used for debug, 4-19 ddr source id debug modes, 20-24 source id on debug signals, 20-26 source id on ecc pins, 20-26 ddr/lbc signal selection (por), 4-19 e500 core registers, 6-39?6-44 features, 20-2 functional description, 20-24 lbc source id debug mode, 13-4, 20-4, 20-24 memory map/register definition, 20-10 modes of operation (set at por), 20-3 overview, 20-1 pci/pci-x debug configuration (por), 4-18 source id debug mode, 20-24 performance monitor events, 19-24 por status (global utilities), 18-8 ready negation, 4-2 software debug context id registers, 20-22 trace buffer, see trace buffer watchpoint, see watchpoint monitor dec (decrementer register), see e500 core, registers decar (decrementer auto -reload register), see e500 core, registers delay-locked loops (dlls) lbc dll control, 18-20 dma channel 2 and 3 signal select, 18-13 dma controller block diagram, 15-1 channel operation, 15-22 bandwidth control, 15-29 channel abort, 15-28 channel state, 15-29 stride size and distance, 15-29 descriptor formats, 15-30 error handling, 15-30 features, 15-2 functional description, 15-22 interrupts, 15-9?15-12, 15-14, 15-18, 15-21, 15-30 limitations and restrictions, 15-33 memory map/register definition, 15-6 modes of operation, 15-2 basic mode transfer, 15-23 basic chaining mode, 15-24 basic chaining single-write start mode, 15-25 basic direct mode, 15-23 basic direct single-write start mode, 15-23 channel continue mode for cascading transfer chains, 15-28 basic channel continue mode, 15-28 extended mode, 15-28 extended dma mode transfer, 15-25 extended chaining mode, 15-25 extended chaining single-write start mode, 15-26 extended direct mode, 15-25 extended direct single-write start mode, 15-25 external control mode transfer, 15-26 overview, 1-19, 15-2 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 index 2-4 freescale semiconductor e?e index 2 general index performance monitor events, 19-17 register descriptions, 15-8?15-22 by acronym, see register index signal select?channel 2 and 3, 18-13, 18-29 signals summary, 15-4 see also signals, dma controller system considerations, 15-34 unusual scenarios, 15-36 dma to configuration and control registers, 15-37 dma to duart, 15-37 dma to e500 core, 15-36 dma to ethernet, 15-36 dma to i2c, 15-37 transfer interfaces, 15-30 dma_dack [0:3] (dma acknowledge) signals, 15-6 dma_ddone [0:3] (dma done) signals, 15-6 dma_dreq [0:3] (dma request) signals, 15-5 doze mode, 1-19, 18-23 see also global utilities, power management duart asynchronous communication bits, 12-1 parity bit, 12-21 start bit, 12-20 stop bit, 12-21 baud-rate generator logic, 12-21 block diagram, 12-2 divisor latch access bit (ulcrn[dlab]), 12-4, 12-12 error handling, 12-22 framing error, 12-9, 12-15, 12-21, 12-22 overrun error, 12-22 parity error, 12-22 errors detected, 12-2 features, 12-1 functional description, 12-19 initialization/application information, 12-24 interrupts interrupt control logic, 12-23 interrupt enable and control registers, 12-9?12-11 memory map/register definition, 12-4 modes of operation, 12-2 dma mode selection, 12-23 fifo mode, 12-22 interrupts, 12-23 local loopback mode, 12-22 overview, 1-17, 12-1 pc16450 uart compatibility, 12-1 performance monitor events, 19-24 register descriptions, 12-4, 12-6?12-19 by acronym, see register index uart0 register offsets, 12-4 uart1 register offsets, 12-4 serial interface data format, 12-2 serial interface operation, 12-20?12-21 data transfer, 12-21 start bit, 12-20 stop bit, 12-21 transaction protocol example, 12-20 signals summary, 12-3 see also signals, duart e e500 coherency module (ecm) block diagram, 8-1 ccb arbiter, 8-8 ccb interface, 8-8 configuration ccb address configuration register (eebacr), 8-3 ccb port configuration re gister (eebpcr), 8-4 error handling error handling registers, 8-4?8-7 features, 8-2 functional description, 8-7 global data multiplexor, 8-8 i/o arbiter, 8-7 initialization/application information, 8-9 interrupts ecm error enable re gister (eeer), 8-5 memory map/register definition, 8-2 overview, 1-16, 8-1 performance monitor events, 19-17 register descriptions, 8-3 by acronym, see register index transaction queue, 8-8 e500 core boot mode (por), 4-14 branch operations registers, 6-9?6-11 branch target buffer (btb) registers, 6-23?6-25 computational operations registers, 6-8?6-9 debug registers, 6-39?6-44 hardware implementation-dependent registers (hid0?1), 6-25?6-28 interrupts registers, 6-17?6-22 sources, 10-3 l1 caches registers, 6-28?6-32 memory management unit (mmu) registers, 6-32?6-39 mmu assist registers (mas0?mas4, mas6), 6-34?6-38 overview, 1-9 4 datasheet u .com
index 2 general index e?e MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor index 2-5 performance monitor registers, 6-47?6-50 processor control registers, 6-11?6-14 registers bbear (branch buffer address register), 6-23 bbtar (branch buffer target address register), 6-23 bucsr (branch unit control and status register), 6-24 cr (condition register), 6-9 csrr0?1 (critical save/res tore registers 0?1), 6-17 ctr (count register), 6-11 dac n (data address compar e registers 1?2), 6-44 dbcr n (debug control register 0?2), 6-39?6-42 dbsr (debug status register), 6-42 dear (data exception address register 0), 6-18 dec (decrementer register), 6-16 decar (decrementer auto-r eload register), 6-17 esr (exception syndrome register), 6-19 gprs (general-purpose registers), 6-8 hid0?1 (hardware implementation-dependent registers 0?1), 6-25 iac n (instruction address co mpare registers 1?2), 6-44 ivor n (interrupt vector of fset registers), 6-18 ivpr (interrupt vector prefix register), 6-18 l1cfg0?1 (l1 cache configuration registers 0?1), 6-30 l1csr0?1 (l1 cache status an d control registers 0?1), 6-28 lr (link register), 6-11 mas0?mas6 (mmu assist registers 0?6), 6-34?6-39 mcar (machine check address register), 6-21 mcsr (machine check syndrome register), 6-21 mcsrr0?1 (machine check save /restore registers 0?1), 6-20 mmucfg (mmu configuration register), 6-32 mmucsr0 (mmu control and status register 0), 6-32 msr (machine state register), 6-11 pid n (process id registers 0?2), 6-32 pir (processor id register), 6-13 pmc n (performance monitor counter registers 0?3), 6-50 pmgc0 (performance monitor global control register 0), 6-48 pmlca n (performance monitor lo cal control registers a0?a3), 6-48 pmlcb n (performance monitor lo cal control registers b0?b3), 6-49 pvr (processor version register), 6-13 spefscr (signal processing and embedded floating-point status and control register), 6-44 sprg n (software-use registers 0?7), 6-22 srr0?1 (save/restore registers 0?1), 6-17 svr (system version register), 6-14 tbl (time base lower register), 6-16 tbu (time base upper register), 6-16 tcr (timer control register), 6-14 tlb0cfg (tlb0 configuration register), 6-33 tlb1cfg (tlb1 configuration register), 6-34 tsr (timer status register), 6-15 upmc n (user performance monitor counter registers 0?3), 6-50 upmgc0 (user performance monitor global control register 0), 6-48 upmlca n (user performance mo nitor local control registers a0?a3), 6-48 upmlcb n (user performance monitor local control registers b0?b3), 6-49 usprg0 (user software-use register 0), 6-22 xer (integer exception register), 6-8 signal processing engine (spe) registers, 6-44 software-use sprs, 6-22 time base rtc (real time clock) signal options, 4-3, 4-22 timer registers, 6-14?6-17 ec_gtx_clk125 (tsec gigabit transmit 125-mhz source) signals, 14-10 ec_mdc (tsec management data clock) signals, 14-10 ec_mdio (tsec management data input/output) signals, 14-10 error handling ddr, 9-19?9-24, 9-46 dma, 15-30 duart, 12-2, 12-22 framing error, 12-9, 12-15, 12-21, 12-22 overrun error, 12-22 parity error, 12-22 ecm error handling registers, 8-4?8-7 i 2 c interface boot sequencer mode, 11-17, 11-18 l2 cache/sram, 7-33 error handling registers, 7-12 error injection, 7-12 lbc transfer error regi sters, 13-25?13-29 pci address/data parity, 16-61, 16-72, 16-73 reporting, 16-73 perr and serr signals, 16-73 target-initiated termination, 16-60 retry transactions, 16-60 target-abort, 16-60 target-disconnect, 16-60 tsec, 14-119?14-120 esr (exception syndrome register), see e500 core, registers 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 index 2-6 freescale semiconductor f?i index 2 general index external system configuration por (lad[0:31]) status, 4-20, 18-9 external writes, see l2 cache/sram, stashing f features, overview of device features, 1-2 fec controller clocks operation, 4-22 g general-purpose i/o (pci and tsec2) see global utilities global utilities clock out clk_out signal, 18-3, 18-19 clock out control register (clkocr), 18-19 overview, 18-2 cpm external interrupts interrupts on port c and sleep mode, 18-24 dma signal multiplex control register (pmuxcr), 18-13, 18-29 features, 18-1 functional description, 18-21 general-purpose i/o signals (pci and tsec2), 18-1 control register (gpiocr), 18-10 input data register (gpindr), 18-12 operation of, 18-28 output data register (gpoutdr), 18-11 interrupt and local bus signal multiplexing, 18-1, 18-13 operation, 18-29 interrupts and power manage ment, 10-3, 18-24, 18-27 lbc dll control register (lbdllcr), 18-20 machine check summary sources of mcp (mcpsumr), 18-17 memory map/register definition, 18-3 overview, 18-1 por configuration boot mode status register (porbmsr), 18-5 debug mode status register (pordbgmsr), 18-8 device status regist er (pordevsr), 18-7 i/o impedance status register (porimpscr), 18-6 lad[0:31] external system configuration (gpporcr), 4-20, 18-9 pll status register (porpllsr), 18-4 see also power-on reset (por) power management and interrupts, 10- 3, 18-24, 18-27 and snooping, 18-27 block disable (devdisr), 18-14, 18-23 ckstp_in and core_stopped mode, 18-22 core and device control bits, 18-24 core and device modes, 18-21 cpm external interrupts and sleep, 18-24 device mode control and status register (powmgtcsr), 18-16 doze mode, 18-23 dynamic power management, 18-23 features, 18-1 functional description, 18-21 nap mode, 18-24 power-down sequence, 18-25 sleep mode, 18-24, 18-28 software considerations, 18-28 processor version register (pvr), 18-18 register descriptions, 18-4 by acronym, see register index signals summary, 18-2 see also signals, global utilities snooping and power management, 18-27 system version register (svr), 18-19 gpcm (lbc general-purpose ch ip-select machine), 13-37 see also local bus controller (lbc) gprs (general-pur pose registers), see e500 core, registers h hash table algorithm, see tsec, hash function hid0?1 (hardware implementati on-dependent registers 0?1), see e500 core, registers host/agent configuration (por) pci, 4-13 hreset (hard reset) signal, 4-2, 4-8 hreset_req (hard reset request) signal, 4-2, 11-17, 11-18 i i/o impedance lbc and pci/pci-x signals control and status register (global utilities), 18-6 pci/pci-x interface (por), 4-17 i/o requirements, 18-28 i/o space pci addressing, 16-55 i 2 c controller overview, 1-17 i 2 c interface arbitration arbitration control, 11-15 loss of arbitration?forcing of slave mode, 11-23 procedure for arbitration, 11-15 block diagram, 11-1 boot sequencer por configuration, 4-14 4 datasheet u .com
index 2 general index i?i MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor index 2-7 boot sequencer mode, 11-2, 11-17?11-19 error condition behavior, 11-17, 11-18 calling address match condition, 11-6 clock control, 11-16 clock stretching, 11-17 clock synchronization, 11-16 input synchronization and digital filter, 11-16 master mode, 11-16 slave mode, 11-16 data transfer, 11-13 error handling boot sequencer mode, 11-17, 11-18 features, 11-2 frequency divider frequency divider register (i2cfdr), 11-6 functional description, 11-11 handshaking, 11-16 implementation details, 11-13 address compare, 11-15 control transfer, 11-14 transaction monitoring, 11-13 initialization/application information, 11-20?11-24 boot sequencer mode, see i 2 c interface, boot sequencer mode generation of scl when sda low, 11-22 initialization sequence, 11-20 post-transfer software response, 11-21 repeated start generation, 11-22 start generation, 11-12, 11-21 stop generation, 11-13, 11-22 interrupts calling address match condition, 11-6 flowchart for interrupt service routine, 11-23 interrupt after transfer, 11-21 interrupt enable bit (i2ccr[mien]), 11-8 interrupt on start, 11-21 interrupt pending status bit (i2csr[mif]), 11-10 interrupt-driven byte-to-byte transfers, 11-2 read of last byte, 11-22 slave mode interrupt service routine guidelines, 11-22 for slave transmitte r routine, 11-23 loss of arbitration, 11-23 memory map/register definition, 11-4 modes of operation, 11-2 boot sequencer mode, 11-2, 11-17?11-19 interrupt-driven byte-to-byte data transfer, 11-2 master mode, 11-2 slave mode, 11-2 overview, 11-2 register descriptions, 11-5 by acronym, see register index signals summary, 11-3 see also signals, i 2 c transaction protocol, 11-11 handshaking, 11-16 repeated start condition, 11-3, 11-13 slave address transmission, 11-12 start condition, 11-2, 11-12, 11-21 stop condition, 11-3, 11-13, 11-22 i 2 c memory map, 2-46, a-13 iac n (instruction address compare registers 1?2), see e500 core, registers initialization ddr (initialization and application information), 9-46 ecm (initialization and application information), 8-9 i 2 c interface (initialization and application in formation), 11-20?11-24 boot sequencer mode, see i 2 c interface, boot sequencer mode generation of scl when sda low, 11-22 initialization sequence, 11-20 post-transfer software response, 11-21 repeated start generation, 11-22 start generation, 11-12, 11-21 stop generation, 11-13, 11-22 l2 cache/sram, 7-33?7-34 lbc (initialization and application information), 13-81?13-117 lbc sdram power-on initialization, 13-49 pci (initialization and ap plication information), 16-75?16-77 pic (initialization and appl ication information), 10-45 tsec (initialization and application information), 14-126?14-144 see also tsec, configuration watchpoint monitor an d trace buffer, 20-29 input/output port memory map, 2-42, a-10 intel pc133 sdram commands (lbc), 13-50 interrupt controller (pic) block diagram, 10-1, 10-41 configuration (global), 10-15 cpm interrupts and sleep mode, 10-3, 18-24 critical interrupts, 10-6, 10-24, 10-26, 10-31 destination (interrupt routing), 10-31 critical interrupt to core, 10-6 external interrupt to core, 10-6 irq_out, 10-6 see also e500 core, critical interrupts end of interrupt (eoi), 10-40, 10-43 external interrupts routed to critical interrupt (cint), 10-26 routed to irq_out, 10-25 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 index 2-8 freescale semiconductor j?j index 2 general index features, 10-3 flow (interrupt processing), 10-41 functional description, 10-41 global timers, 10-18, 10-44 cascading of timers, 10-22, 10-24 clocking of timers, 10-19, 10-23 rtc (real time clock) signal options, 4-3, 4-22, 10-22, 10-23 initialization/application information, 10-45 interrupt acknowledge (iac k) signaling, 10-39, 10-43 interrupt routing (mixed mode), 10-6, 10-41 interrupt source priorities, 10-42 memory map/register definition, 10-8 messaging interrupts, 10-25, 10-26, 10-44 modes of operation, 10-4, 10-16 mixed mode, 10-4 pass-through mode (to support external interrupt controllers), 10-5 nesting of interrupts, 10-43 overview, 1-17, 10-1 performance monitor events, 19-19 power management (wake up conditions), 10-3 processor core inte rrupt sources, 10-3 critical interrupt ( cint ) sources, 10-24 processor current task priority, 10-43 programming guidelines, 10-45 changing interrupt source configuration, 10-47 register descriptions, 10-14 by acronym, see register index, 10-14 global registers, 10-14?10-18 global timer registers, 10-18?10-24 interrupt source configuration registers, 10-19?10-22, 10-30?10-36 message registers, 10-28?10-30 non-accessible registers in-service register (isr), 10-41 interrupt pending register (ipr), 10-41 interrupt request register (irr), 10-41 per-cpu registers, 10-36?10-40 performance monitor mask registers, 10-27?10-28 summary registers, 10-24?10-26 reset of pic, 10-16, 10-45 reset processor from software, 10-16, 10-44 signals summary, 10-7 see also signals, pic simultaneous interrupts, priorities, 10-43 sources of interrupts, 10-5 internal (to pic) interrupt destinations, 10-25, 10-26 internal (to pic) interrupt sources, 10-6 spurious vector generation, 10-18, 10-44 vendor identification, 10-16 interrupts ddr, 9-22 dma, 15-9?15-12, 15-14, 15-18, 15-21, 15-30 duart interrupt control logic, 12-23 interrupt enable and cont rol registers, 12-9?12-11 e500 core registers, 6-17?6-22 ecm interrupt register (ecm error enable register?eeer), 8-5 i 2 c interface calling address match condition, 11-6 flowchart for interrupt service routine, 11-23 interrupt after transfer, 11-21 interrupt enable bi t (i2ccr[mien]), 11-8 interrupt on start, 11-21 interrupt pending status bit (i2csr[mif]), 11-10 interrupt-driven byte-to-byte transfers, 11-2 read of last byte, 11-22 slave mode interrupt servi ce routine guidelines, 11-22 for slave transmitte r routine, 11-23 loss of arbitration, 11-23 irq[9:11] signal select, 18-13, 18-29 lbc interrupt register, 13-27 pci error enable register, 16-31 performance monitor (pic), 19-19 power management and interrupts (global utilities), 10-3, 18-24, 18-27 sec, 17-91 channel done, 17-91 channel error, 17-91 see also interrupt controller (pic) tsec, 14-116?14-118 interrupt registers, 14-19?14-24 irq[0:11] (interrupt request 0?11) signals, 10-7 irq[9:11] signal select global utilities, 18-13 irq_out (interrupt request out) signal, 10-8, 10-24 ivor n (interrupt vector offset registers), see e500 core, registers ivpr (interrupt vector prefix register), see e500 core, registers j jedec sdram comma nds (lbc), 13-50 jtag test access port signals summary, 20-5 see also signals, jtag, 20-5 4 datasheet u .com
index 2 general index l?l MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor index 2-9 l l1cfg0?1 (l1 cache config uration registers 0?1), see e500 core, registers l1csr0?1 (l1 cache status an d control registers 0?1), see e500 core, registers l2 cache/sram allocation of lines, 7-27 block diagram, 7-1 coherency rules, 7-22 configuration and organization, 7-3 error handling ecc errors, 7-33 tag parity errors, 7-34 error handling registers, 7-12 error injection, 7-12 external writes, see stashing flash clearing, instructio n and data locks, 7-25 initialization/application information, 7-33?7-34 invalidation, 7-29 locking clearing locks on selected lines, 7-25 entire, 7-24 programmed memory ranges, 7-24 selected lines, 7-24 with stale data, 7-26 memory map/register definition, 7-6 memory-mapped sram coherency rules, 7-23 memory-mapped windows, 2-4 operation, 7-28 organization, 7-3 overview, 1-14, 7-1 performance monitor events, 19-24 plru bit update considerations, 7-27 register descriptions, 7-7?7-20 replacement policy, 7-26 sram features, 7-2 stashing, 7-20 state transitions, 7-29 due to core-initiated transactions, 7-29 due to system-initiat ed transactions, 7-32 timing, 7-21 la[27:31] (lbc non-multiplexed address) signals, 13-7 lad[0:31] (lbc multiplexed a ddress/data) signals, 13-7 lale (lbc external address latch enable) signal, 13-5, 13-33 lbctl (lbc data buffer control) signal, 13-7, 13-36 lbs [0:3] (lbc upm byte select) signals, 13-6 lck[0:2] (lbc clock) signals, 13-8 lcke (lbc clock en able) signal, 13-7 lcs [0:7] (lbc chip select) signals, 13-5 lcs [5:7] signal select global utilities, 18-13 lcs0 (lbc chip select 0) signal, 13-48 ldp[0:3] (lbc data parity) signals, 13-7, 13-36 lgpl0 (lbc gp line 0) signal, 13-6 lgpl1 (lbc gp line 1) signal, 13-6 lgpl2 (lbc gp line 2) signal, 13-6 lgpl3 (lbc gp line 3) signal, 13-6 lgpl4 (lbc gp line 4) signal, 13-6 lgpl5 (lbc gp line 5) signal, 13-7 lgta (lbc gpcm transfer acknowledge) signal, 13-6, 13-47 local access windows, 2-3?2-8 atmus, see address translation and mapping units (atmus) configuring local access windows, 2-7 distinguishing local access wi ndows from other mapping functions, 2-7 illegal interactions between inbound atmus an d local access windows, 2-8 between local access windows and ddr sdram chip selects, 2-7 l2 cache/sram window interactions, 2-4 precedence if overlapping among themselves, 2-7 precedence if overlapping with l2 cache/sram windows, 2-4 registers, 2-5?2-6 by acronym, see register index local address map, 1-20 see also local access windows local bus controller (lbc) address and address space checking, 13-33 address mask field?option registers, 13-12 atomic bus operations, 13-36 block diagram, 13-1 boot chip-select operation, 13-48 bus monitor, 13-37 bus turnaround, 13-84 additional address phases (upm cycles), 13-85 address following read, 13-84 read data following address, 13-84 read-modify-write cy cle (parity), 13-85 clocks and clock ratios, 13-3 clock ratio regist er (lcrr), 13-31 configuration lbc configuration regi ster (lbcr), 13-29 debug mode signal selection (por), 4-19 source and target id, 20-4, 20-24 dll control (global utilities), 18-20 dsp hosts (interface to), 13-100 msc8101 hdi16 interface, 13-100 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 index 2-10 freescale semiconductor l?l index 2 general index msc8102 dsi interface, 13-104 ti tms320cxxxx interface, 13-114 error handling transfer error registers, 13-25?13-29 external access termination (lgta ), 13-47 features, 13-2 functional description, 13-32 general-purpose chip-select machine (gpcm), 13-37 chip-select and write enab le negation timing, 13-43 chip-select assert ion timing, 13-42 extended hold time on read accesses, 13-46 gpcm mode registers, 13-13 output enable timing, 13-45 programmable wait state configuration, 13-42 relaxed timing, 13-43 timing configuration, 13-38 initialization/application information, 13-81?13-117 interrupts transfer error interrupt enab le register (lteir), 13-27 lcs [5:7] signal select, 18-13, 18-29 memory map/register definition, 13-8 memory refresh timer prescaler, 13-20 modes of operation, 13-3 bus clock and clock ratios, 13-3 gpcm mode, registers, 13-13 power-down mode, 13-4 sdram mode, registers, 13-16 source id debug mode, 13-4 upm mode, registers, 13-15 output hold configuration (por), 4-20 overview, 1-18, 13-2 parity generation and checking, 13-36, 13-97 performance monitor events, 19-23 peripherals, 13-81 gpcm timing, 13-83 hierarchy for very high speeds, 13-82 hierarchy on the local bus, 13-82 multiplexed addr ess/data, 13-81 port sizes, 13-85 register descriptions, 13-10 by acronym, see register index sdram interface, 13-49?13-59, 13-87 address multiplexing, 13-51 basic capabilities, 13-87 commands (intel pc133 and jedec), 13-50 configurations supported, 13-49 device-specific parameters, 13-52 limitations, 13-88?13-97 maximum sdram supported, 13-88 page hit checking, 13-51 page management, 13-51 parity support, 13-97 power-on initialization, 13-49 refresh, 13-58 sdram mode registers, 13-16, 13-21 timing, 13-55 activate-to-read/write interval, 13-53 cas latency, 13-54 external buffers, 13-55 mode-set commands, 13-58 precharge-to-activate interval, 13-53 refresh recovery, 13-55 refresh timing, 13-59 write recovery, 13-54 transactions, 13-58 signals summary, 13-4 see also signals, lbc upm interfaces, 13-59?13-80 block diagram, 13-60 example interface, 13-75 extended hold time (reads), 13-74 programming the upms, 13-63 ram array, 13-66 address multiplexing, 13-72 byte select signal timing, 13-70 chip select signal timing, 13-69 data timing, 13-72 general purpose signal timing, 13-71 lgpl [0:5] timing (last), 13-73 loop control, 13-71 ram word definition, 13-66 redo, 13-71 wait mechanism (waen), 13-73 signal timing, 13-65 synchronous upwait (early transfer acknowledge), 13-74 upm mode registers, 13-15, 13-17 upm requests, 13-60 exception requests, 13-63 memory access requests, 13-61 refresh timer requests, 13-62 software requests, 13-62 zbt sram interface, 13-98 loe (lbc gpcm output enable) signal, 13-6 lpbse (lbc parity byte select) signal, 13-6 lr (link register), see e500 core, registers lsda10 (lbc sdram a10) signal, 13-6 lsdcas (lbc sdram cas ) signal, 13-6 lsddqm[0:3] (lbc sdram data mask) signal, 13-6 lsdras (lbc sdram ras ) signal, 13-6 lsdwe (lbc sdram write enable) signal, 13-6 4 datasheet u .com
index 2 general index m?p MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor index 2-11 lsync_in (lbc pll synchronization in) signal, 13-8 lsync_out (lbc pll synchronization out) signal, 13-8 lwe [0:3] (lbc gpcm write enable) signals, 13-6 m ma[0:14] (ddr address bus) signals, 9-6 mac functionality see tsec, mac functionality machine check mcp (processor machine check) signal, 10-8 mcp summary register (mcpsumr), 18-17 sreset (soft reset) signal, 4-8 mas0?mas6 (mmu assist registers 0?6), see e500 core, registers mba[0:1] (ddr logical bank address) signals, 9-6 mcar (machine check address register), see e500 core, registers mcas (ddr column address strobe) signal, 9-6 mck [0:5] (ddr clock output complement) signals, 9-8 mck[0:5] (ddr clock output) signals, 9-8 mcke (ddr clock enable) signal, 9-8 mcp (processor machine check) signal, 10-8 mcs [0:3] (ddr chip select) signals, 9-7 mcsr (machine check syndrome register), see e500 core, registers mcsrr0?1 (machine check save /restore registers 0?1), see e500 core, registers mdm[0:8] (ddr sdram data output mask) signals, 9-7 mdq[0:8] (ddr data bus strobe) signals, 9-5, 9-26 mdval (ddr/lbc debug mode data valid) signal, 4-19, 13-8, 20-3, 20-7 mecc[0:5] (ddr error correctin g code) signals as debug, 20-3, 20-7 mecc[0:7] (ddr error correctin g code) signals, 4-19, 9-6 memory maps brgs, a-13, 2-46 ccsr memory, 2-4 accessing ccsr memory from external masters, 2-10 ccsr and communications processor module (cpm), 2-13 ccsr map, complete list of memory-mapped registers (by offset), 2-14 ccsr organization, 2-10 ccsr registers, 2-8?2-14 device-specific utilities, 2-13 general utilities registers, 2-11 programmable interrupt controller (pic) space, 2-12 configuration, control, and status registers, 4-3 ddr controller, 9-8 illegal interaction between local access windows and ddr sdram chip selects, 2-7 debug, watchpoint, and tr ace buffer registers, 20-10 device memory map address translatio n and mapping, 2-3 overview and example, 2-1 dma, 15-6 duart, 12-4 ecm, 8-2 global utilities, 18-3 i 2 c, 11-4 interrupt controller (pic), 10-8 l2 cache/sram, 7-6 lbc, 13-8 pci, 16-14 performance monitor, 19-3 tsec, 14-13 memory space pci addressing, 16-54 memory target queue performance monitor events, 19-16 memory unit, see l2 cache/sram message digest execution unit (mdeu), 17-51?17-61 fifos, 17-60 see also security engine (sec) message interrupts, see interrupt controller (pic), message interrupts mmucfg (mmu configuration register), see e500 core, registers mmucsr0 (mmu control and status register 0), see e500 core, registers mras (ddr row address strobe) signal, 9-7 msr (machine state register), see e500 core, registers msrcid[0:4] (ddr/lbc debug source id) signals, 4-19, 13-8, 20-3, 20-7 mwe (ddr write enable) signal, 9-7 n nap mode, 1-19, 18-24 see also global utilities, power management o ocean switch fabric, 1-20 on-chip memory as l2 cache, 1-15 as memory-mapped sram, 1-15 see also l2 cache/sram output hold see power-on reset (por), configuration p page hit checking (lbc sdram), 13-51 page management (lbc sdram), 13-51 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 index 2-12 freescale semiconductor p?p index 2 general index pci controller 64-/32-bit bus, 16-5, 16-6 address bus decoding, 16-54 address translation and mapping unit (atmu) inbound windows (4), 16-23 outbound windows (4), 16-19 arbiter configuration (por), 16-5, 16-6 block diagram, 16-1 burst operations cache wrap mode, 16-54 linear incremen ting, 16-54 bus arbitration, 16-5, 16-49 bus protocol, 16-52 burst operation, 16-52 command encodings, 16-53 clocking, 16-52, 16-57 commands command register, 16-37, 16-66 encodings, 16-53 interrupt-acknowledge transactions, 16-71 special-cycle, 16-71 configuration cycles, 16-65, 16-66 configuration space addressing, 16-55 host access example, 16-67 error handling, 16-73 address/data parity , 16-61, 16-72, 16-73 detection and reporting, 16-72 reporting perr and serr signals, 16-73 target-initiated termination, 16-60 retry transactions, 16-60 target-abort, 16-60 target-disconnect, 16-60 features, 16-4 functional description, 16-49 i/o space addressing, 16-55 initialization/application information, 16-75?16-77 initiator/master operation, 16-3 interrupts error enable register, 16-31 latency timer, 16-42, 16-61, 16-66 memory map/register definition, 16-14 memory space addressing, 16-54 modes of operation, 16-4 agent configuration lock mode, 16-76 agent mode, 16-76 cache wrap mode, 16-54 host mode, 16-76 linear incremen ting, 16-54 overview, 16-2 por configuration, 16-75, 16-76 power management special-cycle operations, 16-71 register descriptions configuration header regi sters, 16-35?16-49, 16-66 32-bit memory base address register, 16-43 64-bit high memory base address register, 16-44 64-bit low memory base address register, 16-44 arbiter configuration register (pbacr), 16-48 base address registers, 16-42?16-45 base class code register, 16-41 bus function register (pbfr), 16-48 bus status register, 16-38, 16-56, 16-60 cache line size register, 16-41 capabilities pointer register, 16-46 command register, 16-37, 16-66 configuration and status register base address (pcsrbar), 16-42 device id register, 16-37, 16-45 interrupt line register, 16-46 interrupt pin register, 16-46 latency timer register, 16-42 maximum grant (max gnt) register, 16-47 maximum latency (max lat) register, 16-47 programming interface register, 16-40 revision id register, 16-40 subclass code register, 16-41 vendor id register, 16-36, 16-45 memory-mapped registers, 16-14 atmu inbound registers, 16-23?16-28 atmu outbound registers, 16-19?16-23 by acronym, see register index configuration access registers, 16-17?16-19 error management registers, 16-28?16-34 signals summary, 16-7 see also signals, pci target/slave operation, 16-4 target-abort termination, 16-60 target-disconnect cycles, 16-3, 16-60 target-initiated termination target-abort error, 16-60 target-disconnect, 16-3, 16-60 transactions fast back-to-back transactions, 16-63 interrupt-acknowledge transactions, 16-71 read transactions, 16-57 retry transactions, 16-60 special-cycle transactions, 16-71 timing diagrams, 16-57 transaction termination, 16-59 bus status register, termination status, 16-61 completion, 16-60 master-abort termination, 16-60 4 datasheet u .com
index 2 general index p?p MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor index 2-13 master-initiated, 16-59 target-initiated, 16-60, 16-61 timeout, 16-60 write transactions, 16-57, 16-58 turnaround cycle, 16-56 pci local bus specification configuration registers see pci controller, registers pci/pci-x controller address translation and mapping unit (atmu) inbound windows (4), 2-8 arbiter configuration (por), 4-18 configuration space addressing host access example, b-49 data bus width (por), 4-17 debug configuration (por), 4-18 debug mode source and target id (pci_ad[63:59]), 20-24 host/agent configuration (por), 4-13 i/o impedance (por), 4-17 output hold configuration (por), 4-19 overview, 1-19 performance monitor events common events, 19-19 pci-specific events, 19-20 pci_ack64 (pci 64-bit transaction acknowledge) signal, 16-8 pci_ad[47:40] signals as gp i/o, see global utilities, general-purpose i/o signals pci_ad[63:0] (pci address/da ta bus) signals, 16-8, 16-55 pci_ad[63:59] (high-order pci address) signals as debug, 20-3, 20-7 pci_c/be [7:0] (pci command/byte enable) signals, 16-9, 16-53, 16-55, 16-56, 16-73 pci_devsel (pci device select) signal, 16-9, 16-55 pci_frame (pci frame) signal, 16-9, 16-52 pci_gnt [4:0] (pci bus grant) signals, 16-10, 16-49 pci_idsel (pci initialization device) signal, 16-10 pci_irdy (pci initiator ready) signal, 16-10, 16-52 pci_par (pci parity) signal, 16-11, 16-72 pci_par64 (pci upper dword parity) signal, 16-11 pci_perr (pci parity error) signal, 16-12 pci_req [4:0] (pci bus request) signals, 16-12, 16-49 pci_req64 (pci 64-bit transaction request) signal, 16-12 pci_serr (pci system error) signal, 16-13, 16-73 pci_stop (pci stop) signal, 16-13, 16-56 pci_trdy (pci target ready) signal, 16-13, 16-52 pci_trdy (target ready) signal, 16-59 performance monitor (device) block diagram, 19-2 burstiness, 19-13, 19-26 control registers, 19-5?19-9 counters (pmcn) chaining, 19-12 registers, 19-9 triggering, 19-12 event counting, 19-10 events, 19-15?19-25 chaining, 19-25 ddr controller, 19-15 debug, 19-24 dma controller, 19-17 duart, 19-24 e500 coherency module (ecm), 19-17 interrupt controller (pic), 19-19 l2 cache/sram, 19-24 local bus controll er (lbc), 19-23 memory target queue, 19-16 pci/pci-x common events, 19-19 pci-specific events, 19-20 tsec1, 19-20, 19-21 tsec2, 19-22 events triggered by watchpoint monitor, 20-27 examples, 19-25 burstiness event, 19-13 burstiness event counting, 19-26 simple event counting, 19-25, 19-26 threshold event counting, 19-26 triggering event counting, 19-25, 19-26 external signals, 19-3 features, 19-3 functional description, 19-10 interrupts, 19-10 interrupts (from pic) to generate events, 10-27 masking interrupts (from pic), 10-27 memory map/register definition, 19-3 overflow indication on trig_out, 20-24 overview, 19-1 threshold events, 19-11 phase-locked loops (plls) por status (global utilities), 18-4 pid n (process id re gisters 0?2), see e500 core, registers pir (processor id register), see e500 core, registers pmc n (performance monitor counter registers 0?3), see e500 core, registers pmgc0 (performance monitor gl obal control register 0), see e500 core, registers pmlca n (performance monitor lo cal control registers a0?a3), see e500 core, registers pmlcb n (performance monitor lo cal control registers b0?b3), see e500 core, registers 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 index 2-14 freescale semiconductor r?r index 2 general index power management block disable block disable control (devdisr), 18-14, 18-23 lbc, 13-4 ddr interface, 9-41 device low-power modes, 18-21?18-28 control and status register (powmgtcsr), 18-16 ready negation, 4-2 interrupts that cause wake-up, 10-3 overview, 1-19 pci special-cycle operations, 16-71 see also global utilities, power management power-on reset (por) configuration boot rom location, 4-12 boot sequencer configuration, 4-14 clock e500 core pll ratio, 4-12 system/ccb pll ratio, 4-11 cpu boot configuration, 4-14 ddr debug mode (ecc pins used for debug), 4-19, 20-3 general-purpose (external system) configuration?lad[0:31] (gpporcr), 4-20 host/agent configuration (pci), 4-13 memory debug select (ddr or lbc), 4-19, 20-3 output hold lbc output hold, 4-20 pci/pci-x output hold, 4-19 pci data bus width, 4-17 pci debug configuration, 4-18, 20-3 pci i/o impedance, 4-17 pci, modes of operation, 16-75, 16-76 pci/pci-x arbiter configuration, 4-18 tsec data width, 4-15 tsec1 protocol, 4-15 tsec2 protocol, 4-16 configuration reporting global utilities, 18-4, 18-5, 18-6, 18-7, 18-8, 18-9 debug modes summary, 20-3 hard reset, 4-8 output signal states during reset, 3-15 reset configuration signals, 3-13 sequence of events, 4-9 and ready signal, 4-2, 4-10 processor version (pvr), 18-18 protocols pci, see pci contoller, bus protocol public key execution unit (pkeu), 17-24?17-33 parameter memory a, 17-32 parameter memory b, 17-32 parameter memory e, 17-33 parameter memory n, 17-33 see also security engine (sec) pvr (processor version register), see e500 core, registers r random number generator (rng), 17-61?17-66 fifo, 17-66 see also security engine (sec) ready signal, 4-2, 4-10, 20-23, 20-24 registers by acronym (memory-mapped registers) see register index configuration, control, and status, 2-8?2-14, 4-3 device-specific utilities, 2-13 general utilities, 2-11 programmable interr upt controller (pic) space, 2-12 context id, 20-22?20-23 crypto-channel general, 17-81, 17-91 ddr configuration registers, 9-9?9-16 error handling registers, 9-19?9-24 error injection registers, 9-17?9-18 e500 core, see e500 core, registers ecm, 8-3 global utilities, 18-4 por boot mode status, 18-5 por debug mode status, 18-8 por device status, 18-7 por external system configuration, 18-9 por i/o impedance status, 18-6 por pll status, 18-4 i 2 c interface, 11-5 l2 cache/sram registers, 7-6?7-20 lbc, 13-10 dll control, 18-20 local access window registers attributes registers (lawar0?lawar7), 2-6 base address registers (lawbar0?lawbar7), 2-5 pci configuration header regi sters, 16-35?16-49, 16-66 32-bit memory base address register, 16-43 64-bit high memory base address register, 16-44 64-bit low memory base address register, 16-44 arbiter configuration register (pbacr), 16-48 base address registers, 16-42?16-45 base class code register, 16-41 bus function register (pbfr), 16-48 bus status register, 16-38, 16-56, 16-60 cache line size register, 16-41 4 datasheet u .com
index 2 general index s?s MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor index 2-15 capabilities pointer register, 16-46 command register, 16-37, 16-66 configuration and status register base address (pcsrbar), 16-42 device id register, 16-37, 16-45 interrupt line register, 16-46 interrupt pin register, 16-46 latency timer register, 16-42 maximum grant (max gnt) register, 16-47 maximum latency (max lat) register, 16-47 programming interface register, 16-40 revision id register, 16-40 subclass code register, 16-41 vendor id, 16-36, 16-45 memory-mapped registers atmu inbound registers, 16-23?16-28 atmu outbound registers, 16-19?16-23 configuration access re gisters, 16-17?16-19 error management registers, 16-28?16-34 performance monitor, descriptions, 19-3 pic, 10-14 global registers, 10-14?10-18 global timer registers, 10-18?10-24 interrupt source configuration registers, 10-19?10-22, 10-30?10-36 message registers, 10-28?10-30 non-accessible registers in-service register (isr), 10-41 interrupt pending register (ipr), 10-41 interrupt request register (irr), 10-41 per-cpu registers, 10-36?10-40 performance monitor mask registers, 10-27?10-28 summary registers, 10-24?10-26 processor version register (pvr), 18-18 sec aesu registers, 17-67?17-80 afeu registers, 17-42?17-51 eu assignment status, 17-92 fetch fifo, 17-90 id, 17-97 interrupt, 17-93?17-97 master control, 17-98 medu registers, 17-51?17-61 pkeu registers, 17-24?17-33 rng registers, 17-61?17-66 system version register (svr), 18-19 trace buffer, 20-15?20-21 trigger out source register, 20-23 tsec fifo control and status registers, 14-29?14-32 general control and status registers, 14-19?14-29 hash function registers, 14-84?14-85 mac registers, 14-44?14-57 mib registers, 14-58?14-84 receive control and status registers, 14-39?14-44 ten-bit interface (tbi) registers, 14-87?14-99 transmit control and status registers, 14-32?14-39 watchpoint monitor, 20-10?20-15 reset core reset through pic register, 10-16, 10-44 hard reset actions, 4-8 operations, 4-8 power-on reset (por) configuration, see power-on reset (por), configuration sequence of events, 4-9 signals summary, 4-1 see also signals, reset soft reset actions, 4-8 rtc (real time clock) signal, 4- 3, 4-22, 10-22, 10-23, 18-25 rts , see duart_rts [0:1] s scc memory map, 2-47 scl (i 2 c serial clock) signal, 11-3, 11-4 sda (i 2 c serial data) signal, 11-3, 11-4 sdram interface (lbc), 13-49?13-59 see also local bus controller (lbc), sdram interface security engine (sec) advanced encryption standa rd execution unit (aesu), 17-67?17-80 arc four execution unit (afeu), 17-42?17-51 context memory, 17-50 channel reset, 17-92 data encryption standard execution unit (deu), 17-33 descriptor structure, 17-15 fetch fifo register, 17-90 initiator write, 17-102 interrupts, 17-91 channel done, 17-91 channel error, 17-91 registers, 17-93?17-97 message digest execution unit (mdeu), 17-51?17-61 multiple channels and eu arbitration, 17-99 multiple eu assignment, 17-99 public key execution unit (pkeu), 17-24?17-33 random number generator (rng), 17-61?17-66 registers controller registers, 17-92 crypto-channel registers, 17-81?17-91 id register, 17-97 status registers, 17-55, 17-63, 17-71 sec controller eu access, 17-99 eu assignment status register, 17-92 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 index 2-16 freescale semiconductor s?s index 2 general index slave accesses, 17-102 snapshot arbiters, 17-101 serial data/clock, see i 2 c interface, 11-1 si memory map, 2-50 signals clock rtc (real time clock), 4-3, 4-22, 10-22, 10-23, 18-25 sysclk (system clock input), 4-3 complete signal listing alphabetical reference, 3-8 configuration signals, sampled at por, 3-13 see also power-on reset (por) figure showing groupings, 3-1 output signal states at power-on reset, 3-15 reference by functional block, 3-3 ddr ma[0:14] (address bus), 9-6 mba[0:1] (logical bank address), 9-6 mcas (column address strobe), 9-6 mck [0:5] (ddr clock output complements), 9-8 mck[0:5] (ddr clock outputs), 9-8 mcke (ddr clock enable), 9-8 mcs [0:3] (chip selects), 9-7 mdm[0:8] (sdram data output mask), 9-7 mdqs[0:8] (data bus strobes), 9-5, 9-26 mdval (debug mode data valid), 4-19, 20-3, 20-7 mecc[0:5] (error correcting code) as debug signals, 20-3, 20-7 mecc[0:7] (error correcting code), 4-19 mecc[0:7] (error correcting codes), 9-6 mras (row address strobe), 9-7 msrcid[0:4] (debug source id), 4-19, 20-3, 20-7 mwe (write enable), 9-7 dma dma_dack [0:3] (dma acknowledge), 15-6 dma_ddone [0:3] (dma done), 15-6 dma_dreq [0:3] (dma request), 15-5 duart uart_cts [0:1] (duart clear to send), 12-1, 12-3, 12-4 uart_rts [0:1] (duart request to send), 12-1, 12-3, 12-4 uart_sin [0:1] (duart transmitter serial data in), 12-2, 12-3 uart_sout [0:1] (duart transmitter serial data out), 12-2, 12-3, 12-4 global utilities asleep, 18-2, 18-24 ckstp_in (checkstop in), 18-2 ckstp_out (checkstop out), 18-3 clk_out, 18-3, 18-19 i 2 c scl (serial clock), 11-3, 11-4 sda (serial data), 11-3, 11-4 jtag tck (jtag test clock), 20-8 tdi (jtag test data input), 20-8 tdo (jtag test data output), 20-9 tms (jtag test mode select), 20-9 trst (jtag test reset), 20-9 lbc la[27:31] (non-multiplexed address), 13-7 lad[0:31] (multiplexed address/data), 13-7 lale (external address latch enable), 13-5, 13-33 lbctl (data buffer control), 13-7, 13-36 lbs [0:3] (upm byte select), 13-6 lck[0:2] (clock), 13-8 lcke (clock enable), 13-7 lcs [0:7] (chip select), 13-5 lcs0 (lbc chip select 0), 13-48 ldp[0:3] (data parity), 13-7, 13-36 lgpl0 (gp line 0), 13-6 lgpl1 (gp line 1), 13-6 lgpl2 (gp line 2), 13-6 lgpl3 (gp line 3), 13-6 lgpl4 (gp line 4), 13-6 lgpl5 (gp line 5), 13-7 lgta (gpcm transfer acknowledge), 13-6, 13-47 loe (gpcm output enable), 13-6 lpbse (parity byte select), 13-6 lsda10 (sdram a10), 13-6 lsdcas (sdram cas ), 13-6 lsddqm[0:3] (sdram data mask), 13-6 lsdras (sdram ras ), 13-6 lsdwe (sdram write enable), 13-6 lsync_in (pll synchronization in), 13-8 lsync_out (pll synchronization out), 13-8 lwe [0:3] (gpcm write enable), 13-6 mdval (debug mode data va lid), 4-19, 13-8, 20-3, 20-7 msrcid[0:4] (debug source id), 4-19, 13-8, 20-3, 20-7 ta (data transfer acknowledge), 13-35 upwait (upm wait), 13-6, 13-60 other test_sel (factory test), 20-6, 20-9 therm[0:1] (thermal resistor access), 20-9 pci pci_ack64 (64-bit transaction acknowledge), 16-8 pci_ad[63:0] (address/data bus), 16-8, 16-55 pci_c/be [7:0] (command/byte enable), 16-9, 16-53, 16-55, 16-56, 16-73 pci_devsel (device select), 16-9, 16-55 pci_frame (frame), 16-9, 16-52 pci_gnt [4:0] (bus gran t), 16-10, 16-49 4 datasheet u .com
index 2 general index t?t MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor index 2-17 pci_idsel (initiali zation device), 16-10 pci_irdy (initiator ready), 16-10, 16-52 pci_par (parity), 16-11, 16-72 pci_par64 (upper dword parity), 16-11 pci_perr (parity error), 16-12 pci_req [4:0] (bus request), 16-12, 16-49 pci_req64 [4:0] (64-bit transaction request), 16-12 pci_serr (system erro r), 16-13, 16-73 pci_stop (stop), 16-13, 16-56 pci_trdy (target ready), 16-13, 16-52 pci/pci-x pci_ad[63:59] (high-order pci address) as debug signals, 20-3, 20-7 pic irq[0:11], 10-7 irq_out , 10-8, 10-24 mcp , 10-8 ude , 10-8 reset hreset (hard reset), 4-2, 4-8 hreset_req (hard reset request), 4-2, 11-17, 11-18 ready, 4-2, 20-23, 20-24 sreset (soft reset), 4-2, 4-8 tsec ec_gtx_clk125 (tsec gigabit transmit 125 mhz source), 14-10 ec_mdc (tsec management data clock), 14-10 ec_mdio (tsec management data input/output), 14-10 tsec n _col (tsec 1?2 collision input), 14-10 tsec n _crs (tsec 1?2 carrier sense input), 14-10 tsec n _gtx_clk (tsec 1?2 gigabit transmit clock), 14-10 tsec n _rx_clk (tsec 1?2 receive clock), 14-10 tsec n _rx_dv (tsec 1?2 receive data valid), 14-11 tsec n _rx_er (tsec 1?2 r eceive error), 14-11 tsec n _rxd[7:0] (tsec 1?2 r eceive data in), 14-11 tsec n _tx_clk (tsec 1?2 transmit clock in), 14-11 tsec n _tx_en (tsec 1?2 transmit data valid in), 14-12 tsec n _tx_er (tsec 1?2 transmit error in), 14-12 tsec n _txd[7:0] (tsec 1?2 transmit data out), 14-12 watchpoint monitor trig_in (watchpoint trigger in), 20-8, 20-12, 20-17 trig_out (watchpoint trigger out), 20-8, 20-23 sleep mode, 1-19, 18-24, 18-28 see also global utilities, power management smc memory map, 2-49 snooping power management and snooping (global utilities), 18-27 soft reset and reconfiguring for tsec, 14-108 spefscr (signal processing and embedded floating-point status and cont rol register), see e500 core, registers spi memory map, 2-49, a-14 sprg n (software-use registers 0?7), see e500 core, registers sram, see l2 cache/sram, 7-22 sreset (soft reset) signal, 4-2, 4-8 srr0?1 (save/restore registers 0?1), see e500 core, registers stashing, see l2 cache/sram, stashing, 7-20 svr (system version register), see e500 core, registers sysclk (system clock input) signal, 4-3 system version (svr), 18-19 t ta (lbc data transfer acknowledge) signal, 13-35 target-disconnect, see pci controller tbl (time base lower register), see e500 core, registers tbu (time base upper register), see e500 core, registers tck (jtag test clock) signal, 20-8 tcr (timer control register), see e500 core, registers tdi (jtag test data input) signal, 20-8 tdo (jtag test data output) signal, 20-9 termination pci, termination of pci transactions, 16-59 test interface, see jtag test access port test_sel (factory test) signal, 20-6, 20-9 therm[0:1] (thermal resist or access) signals, 20-9 three-speed ethernet controller, see tsec timing diagrams pci transactions tlb0cfg (tlb0 configuration register), see e500 core, registers tlb1cfg (tlb1 configuration register), see e500 core, registers tms (jtag test mode select) signal, 20-9 trace buffer and watchpoint monitor, block diagram, 20-1 as a second watchpoint monitor, 20-27 functional description, 20-27?20-29 initialization, 20-29 modes of triggering and arming, 20-4 overview, 20-1 register descriptions, 20-15?20-21 by acronym, see register index see also watchpoint monitor, 20-4 traced data formats relative to tbcr1[ifsel] ddr trace buffer entry, 20-28 ecm trace buffer entry, 20-28 pci trace buffer entry, 20-29 transactions pci see pci controller, transactions trig_in (watchpoint trigger in) signal, 20-8, 20-12, 20-17 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 index 2-18 freescale semiconductor t?t index 2 general index trig_out (watchpoint trigger out) signal, 20-8, 20-23 trst (jtag test reset) signal, 20-9 tsec block diagram, 14-5 buffer descriptors, 14-120 receive buffer descriptor (rxbd), 14-123 transmit data buffer descriptor (txbd), 14-121 clocks inputs and outputs, 14-10 management clock out (ec_mdc), 14-52 operation, 4-22 configuration of interfaces, 14-126 gmii interface mode, 14-129 mii interface mode, 14-126 rgmii interface mode, 14-137 rtbi interface mode, 14-140 tbi interface mode, 14-133 data width (por), 4-15 error handling, 14-119?14-120 features, 14-7 functional description, 14-99 gigabit ethernet channel operation, 14-107 flow control, 14-115 frame reception, 14-110 frame recognition, 14-112 destination address recognition, 14-112 frame transmission, 14-109 initialization sequence, 14-107 hardware controlled initialization, 14-107 user initialization, 14-107 inter-packet gap time, 14-118 interrupt handling, 14-116?14-118 hash function hash table algorithm, 14-114 hash table effectiveness, 14-114 registers, 14-84 initialization/application information, 14-126?14-144 see also tsec, configuration interrupts, 14-116 interrupt coalescing, 14-117 by frame count threshold, 14-117 by timer threshold, 14-117 interrupt registers, 14-19?14-24 mac functionality, 14-44?14-57 configuration, 14-44 csma/cd controlling, 14-44 packet collis ions, 14-45 packet flow, 14-45 phy link control, 14-46 registers, 14-46 memory map/register definition, 14-12 detailed memory map, 14-13?14-19 top level module map, 14-13 tsec2 controller offsets, 14-19 modes of operation, 14-8 10 mbps and 100 mbps mii operation, 14-8 1000 mbps gmii and tbi operation, 14-8 address recognition options, 14-8 full and half-duplex operation, 14-8 internal and external loop back, 14-118 rmon support, 14-111 overview, 1-18, 14-6 performance monitor events tsec1, 19-20, 19-21 tsec2, 19-22 physical interface connections, 14-99 gigabit media-independen t interface (gmii), 14-100 media-independent in terface (mii), 14-100 reduced gigabit media-independent interface (rgmii), 14-101 reduced ten-bit interface (rtbi), 14-103 ten-bit interface (tbi), 14-102 register descriptions, 14-19 by acronym, see register index, 14-19 fifo control and status registers, 14-29?14-32 general control and status registers, 14-19?14-29 hash function registers, 14-84?14-85 mac registers, 14-44?14-57 mib registers, 14-58?14-84 receive control and status registers, 14-39?14-44 ten-bit interface (tbi) registers, 14-87?14-99 transmit control and status registers, 14-32?14-39 signals, 14-9?14-12 see also signals, tsec soft reset and reconfiguring procedure, 14-108 tbi mii registers, see tsec, register descriptions tsec1 protocol (por), 4-15 tsec2 protocol (por), 4-16 tsec2 signals as gp i/o, see global utilities, general-purpose i/o signals tsec n _col (tsec 1?2 collision input) signals, 14-10 tsec n _crs (tsec 1?2 carrier sense input) signals, 14-10 tsec n _gtx_clk (tsec 1?2 gigabit transmit clock) signals, 14-10 tsec n _rx_clk (tsec 1?2 receive clock) signals, 14-10 tsec n _rx_dv (tsec 1?2 receive data valid) signals, 14-11 tsec n _rx_er (tsec 1?2 receive error) signals, 14-11 tsec n _rxd[7:0] (tsec 1?2 receive data in) signals, 14-11 tsec n _tx_clk (tsec 1?2 transmit clock in) signals, 14-11 tsec n _tx_en (tsec 1?2 transmit data valid in) signals, 14-12 tsec n _tx_er (tsec 1?2 transmit error in) signals, 14-12 4 datasheet u .com
index 2 general index u?z MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor index 2-19 tsec n _txd[7:0] (tsec 1?2 transmit data out) signals, 14-12 tsr (timer status register), see e500 core, registers u uart_cts [0:1] (duart clear to send) signals, 12-1, 12-3, 12-4 uart_rts [0:1] (duart request to send) signals, 12-1, 12-3, 12-4 uart_sin [0:1] (duart transmitt er serial data in) signals, 12-2, 12-3 uart_sout [0:1] (duart transmitter serial data out) signals, 12-2, 12-3, 12-4 ude (unconditional debug event) signal, 10-8 universal asynchronous receiver/transmitter, see duart universal serial bus (usb) controller host mode sof transmission, 35-12, b-18 tokens, 35-10 upmc n (user performance monitor counter registers 0?3), see e500 core, registers upmgc0 (user performance monitor global control register 0), see e500 core, registers upmlca n (user performance monito r local control registers a0?a3), see e500 core, registers upmlcb n (user performance monitor local control registers b0?b3), see e500 core, registers upwait (lbc upm wait) signal, 13-6, 13-60 usprg0 (user software-use register 0), see e500 core, registers w watchpoint monitor and trace buffer, block diagram, 20-1 functional description, 20-26?20-27 initialization, 20-29 modes of triggering and arming, 20-4 overview, 20-1 performance monitor events, 20-27 register descriptions, 20-10?20-15 by acronym, see register index second wm by usi ng trace buffer, 20-27 see also trace buffer, 20-4 signals summary, 20-5 see also signals, watchpoint, 20-5 x xer (integer exception register), see e500 core, registers z zbt sram interface (lbc), 13-98 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 index 2-20 freescale semiconductor z?z index 2 general index 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor index 3-1 index 3 cpm index a aal2 exceptions, 42-37 features, 42-2 introduction, 42-1 parameter ram, 42-34 receiver, 42-19 aal2 rx data structures, 42-22 cid mapping tables and rxqds, 42-26 cps rx queue descriptors, 42-26 cps switch rx queue descriptor, 42-28 receive connection tables, 42-23 sssar receive buffer descriptor, 42-32 sssar rx queue descriptor, 42-30 switch receive/transmit buf fer descriptor (rxbd), 42-29 aal2 switching, 42-21 figure, 42-22 cid mapping process, 42-21 mapping of phy | vp | vc | cid, 42-20 overview, 42-19 sublayer structure, 42-2 switching example, 42-2 transmitter, 42-4 aal2 tx data structures, 42-9 cps buffer structure, 42-14 cps tx queue descriptor, 42-12 sssar transmit buffer descriptor, 42-18 sssar tx queue descriptor, 42-16 no-stf mode, 42-8 overview, 42-4 partial fill mode (pfm), 42-7 transmit priority mechanism, 42-5 fixed priority, 42-6 flow, 42-7 round robin priority, 42-5 flow, 42-6 user-defined cells in aal2, 42-37 accessing dual-port ram, 21-29 alignment non-octet alignment data, 34-37 appletalk mode gsmr, 33-3 programming example, 33-3 psmr, 33-4 todr, 33-4 atm controller aal1 sequence number pr otection table, 41-75 aal n rxbd, 41-6, 41-67 aal n txbd, 41-4, 41-72 abr flow control, 41-8, 41-19 address compression, 41-14 atm layer statistics, 41-33 atm memory structure, 41-35 atm pace control (apc) unit atm service types, 41-8 configuration, 41-96 data structures, 41-59 modes, 41-8 overview, 41-8 parameter tables, 41-60 priority table, 41-61 scheduling mechanism, 41-9 scheduling tables, 41-61 traffic type, 41-11 ubr+ traffic, 41-12 vbr traffic, 41-11 atm transmit command, 41-88 atm-to-tdm interworking, 41-33 buffer descriptors, 41-62 exceptions, 41-77 external rate mode, 41-6 fcce, 41-86 fccm, 41-86 features list, 41-1 fpsmr, 41-84 ftirr x , 41-87 gfmr register, 41-83 global mode entry (gmode), 41-38 internal rate mode, 41-6 interrupt queues, 41-77 maximum performance configuration, 41-95 oam performance monitoring, 41-29, 41-58 oam support, 41-27 operations and maintenance (oam) support, 41-27 overview, 41-4 parameter ram, 41-35 performance monitoring, 41-8 performance, maximum (configuration), 41-95 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 index 3-2 freescale semiconductor b?b index 3 cpm index programming model, 41-83 receive connection table (rct) aal n protocol-specific rcts, 41-43?41-47 atm channel code, 41-40 overview, 41-39 raw cell queue, 41-18 rct entry format, 41-41 registers, 41-83 rxbd, 41-67 rxbd extension, 41-71 transmit connection table (tct) aal n protocol-specific tcts, 41-51, 41-51?41-53 atm channel code, 41-40 overview, 41-39 tct entry format, 41-48 transmit connection table extension (tcte) abr protocol-specific, 41-56 atm channel code, 41-40 overview, 41-39 ubr+ protocol-specific, 41-55 vbr protocol-specific, 41-54 transmit rate modes, 41-6 txbd, 41-72 txbd extension, 41-75 udc extended address mode, 41-33 uead_offset determination, 41-37 uni statistics table, 41-76 user-defined cells (udc) extended address mode, 41-33 overview, 41-32 rxbd extension (aal5/aal1), 41-71 txbd extension (aal5/aal1), 41-75 user-defined rxbd extension (aal5/aal1), 41-71 user-defined txbd extension (aal5/aal1), 41-75 utopia interface, 41-79 vci filtering, 41-38 vci/vpi address lookup, 41-13 vc-level address compression tables (vclt), 41-17 vp-level address compression table (vplt), 41-16 b baud-rate generator (brg) memory map, 21-9 baud-rate generators, 25-1 autobaud operation on a uart, 25-5 uart baud rate examples, 25-5 baud-rate generators (brgs) i 2 c controller brgclk, 44-2 bdle (scc bisync dle) register, 31-7 bisync mode commands, 31-4 control character recognition, 31-5 error handling, 31-9 frame reception, 31-3 frame transmission, 31-2 frames, classes, 31-1 memory map, 31-3 overview, 31-1 parameter ram, 31-3 programming the controller, 31-16 receiving synchronizat ion sequence, 31-8 rxbd, 31-11 sending synchronization sequence, 31-8 txbd, 31-12 block diagrams cascaded mode, 26-3 communications processor (cp), 21-17 communications proces sor module (cpm), 21-3 cpm multiplexing logic (cmx), 24-2 dpll receiver, 28-20 dual-port ram, 21-29 fast ethernet, 40-2 fcc overview, 37-3 i 2 c controller, 44-1 parallel i/o ports, 45-16 scc block diagram, 28-2 serial interface, 23-1 serial peripheral interface (spi), 43-1 timers, 26-1 brgclk, 44-2 bsync (bisync sync) register, 31-7 buffer descriptors, 28-10 at m c o n t r o l l e r receive, 41-63, 41-67 transmit, 41-62, 41-72 bisync mode, 31-11 buffer descriptor tables, 34-6 data buffer pointer, 34-6 fast communications controllers (fccs) fast ethernet mode receive, 40-25 transmit, 40-27 hdlc mode receive, 38-9 transmit, 38-12 overview receive, 37-9 transmit, 37-9 gci mode monitor channel, 36-32 4 datasheet u .com
index 3 cpm index c?c MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor index 3-3 hdlc mode, 30-8 i 2 c controller receive, 44-12 transmit, 44-13 placement, 34-39 rxbd, 34-35 serial management controllers (smcs), 36-4 serial peripheral interface (spi) buffer descriptor ring, 35-22 receive, 43-14 receive buffer descriptor, 35-24 transmit, 43-15 transparent mode serial communications co ntrollers (sccs), 32-8 serial management controllers (smcs), 36-26 txbd, 34-38 uart mode serial communications co ntrollers (sccs), 29-14 serial management controllers (smcs), 36-14 byte stuffing, 31-1 c cascaded mode, 26-3 channel channel addressing capability, 34-1 channel pointers mcbase, 34-5 rbase, 34-5 tbase, 34-5 time slot assignment, 34-5 tsatrx, 34-10 tsattx, 34-11 channel-specific parameters, 34-15 channel-specific transparent parameters, 34-19 interrupt processing flow, 34-34 interrupt table entry, 34-31 circular interrupt table, external memory, 34-28 clocking and pin functions, 35-2 clocks sccr, 25-2 cmxfcr (cmx fcc clock route register), 24-8 cmxscr (cmx scc clock route register), 24-10 cmxsi2cr (cmx si2 clock route register), 24-8 cmxsmr (cmx smc clock route register), 24-13 cmxuar (cmx utopia address register), 24-5 commands atm transmit command, 41-88 fast communications controllers (fccs) ethernet mode receive commands, 40-13 transmit commands, 40-12 hdlc mode receive commands, 38-6 transmit commands, 38-5 i 2 c controller, 44-11 receive, 34-28 serial peripheral interface (spi), 43-12 transmit, 34-27 communications processor module (cpm) block diagram, 21-3 command set command descriptions, 21-27 command execution latency, 21-28 command register example, 21-28 cpcr, 21-24 opcodes, 21-26 overview, 21-24 communications processor (cp) block diagram, 21-17 execution from ram, 21-21 features list, 21-16 memory map, 21-10 microcode execution from ram, 21-21 microcode revision number, 21-24 peripheral interface, 21-20 rccr, 21-22 rev_num, 21-24 rtscr, 21-23 rtsr, 21-24 dual-port ram accessing dual-port ram, 21-29 block diagram, 21-29 buffer descriptors, 21-31 memory map, 21-29, 21-30 overview, 21-28 parameter ram, 21-31 features list, 21-1 overview, cpm, 21-1 resetting registers and parameters for all channels, 21-25 risc timer tables cp loading tracking, 21-37 features list, 21-32 initializing risc timer tables, 21-35 interrupt handling, 21-36 overview, 21-32 parameter ram, 21-33 ram usage, 21-33 rter, 21-35 rtmr, 21-35 scan algorithm, 21-37 set timer command, 21-35 table entries, 21-35 timer counts, comparing, 21-37 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 index 3-4 freescale semiconductor d?f index 3 cpm index tm_cmd, 21-34 tracking cp loading, 21-37 timers memory map, 21-6 cpcr (cp command register), 21-24 cpcr (cpm command register), 35-32 cpm multiplexing logic (cmx) block diagram, 24-2 cpm mux memory map, 21-14 d digital phase-locked loop (dpll) operation, 28-20 disabling receiver/tr ansmitter, 34-41 dsr (data synchronization register) overview, 28-8 uart mode, 29-10 dual-port ram accessing dual-port ram, 21-29 block diagram, 21-29 buffer descriptors, 21-31 memory map, 21-29, 21-30 overview, 21-28 parameter ram, 21-31 e echo mode, 34-3 errors global error events, 34-29 ethernet mode fast communications controller (fcc) address recognition, 40-15 block diagram, 40-2 cam interface, 40-8 collision handling, 40-18 connecting to the mpc8260, 40-4 error handling, 40-19 fcce, 40-22 fccm, 40-22 features list, 40-2 fpsmr, 40-20 frame reception, 40-6 frame transmission, 40-5 hash table algorithm, 40-17 hash table effectiveness, 40-17 interpacket gap time, 40-18 interrupt events, 40-24 loopback mode, 40-18 parameter ram, 40-9 programming model, 40-12 registers, 40-19 rmon support, 40-13 rxbd, 40-25 txbd, 40-27 ethernet mode register, fpsmr, 40-21 exceptions channel interrupt processing flow, 34-34 interrupt table entry, 34-31 overview, 34-28 txb, 34-39 f fast communications controllers (fccs) block diagram, 37-3 disabling fccs, 37-19 fast ethernet mode address recognition, 40-15 block diagram, 40-2 cam interface, 40-8 collision handling, 40-18 connecting to the mpc8260, 40-4 error handling, 40-19 fcce, 40-22 fccm, 40-22 features list, 40-2 fpsmr, 40-20 frame reception, 40-6 frame transmission, 40-5 hash table algorithm, 40-17 hash table effectiveness, 40-17 interpacket gap time, 40-18 interrupt events, 40-24 loopback mode, 40-18 parameter ram, 40-9 programming model, 40-12 registers, 40-19 rmon support, 40-13 rxbd, 40-25 txbd, 40-27 fcce x , 37-13 fccm x , 37-14 fccs x , 37-14 fcr x , 37-12 fdsr x , 37-7 fpsmr x , 37-7 ftodr x , 37-8 gfmr x , 37-3 hdlc mode bit stuffing, 38-1 error control, 38-1 error handling, 38-6 fcce, 38-14 fccm, 38-14 fccs, 38-16 4 datasheet u .com
index 3 cpm index g?h MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor index 3-5 features list, 38-1 fpsmr, 38-8 frame reception, 38-3 frame transmission, 38-2 overview, 38-1 parameter ram, 38-3 programming model, 38-5 receive commands, 38-6 reception errors, 38-7 rxbd, 38-9 transmission errors, 38-6 transmit commands, 38-5 txbd, 38-12 initialization, 37-14 interrupt handling, 37-15 interrupts, 37-13 parameter ram, 37-10 rxbd, 37-9 saving power, 37-21 switching protocols, 37-21 timing control, 37-16 transparent mode features list, 39-1 receive operation, 39-2 synchronization achieving, 39-2 example, 39-4 external signals, 39-3 in-line pattern, 39-2 transmit operation, 39-2 txbd, 37-9 fcce register atm, 41-86 ethernet, 40-22 fcc overview, 37-13 hdlc mode, 38-14 fccm register atm, 41-86 ethernet, 40-22 fcc overview, 37-14 hdlc mode, 38-14 fccs (fcc status) register, 37-14, 38-16 fcr x (function code registers), 37-12 fdsr x (fcc data synchronization registers), 37-7 features summary, list, 34-2 features lists atm controller, 41-1 communications processor (cp), 21-16 communications proces sor module (cpm), 21-1 cpm multiplexing, 24-2 fast communications controllers (fccs) fast ethernet, 40-2 hdlc mode, 38-1 transparent mode, 39-1 hdlc bus controller, 30-16 i 2 c controller, 44-2 parallel i/o ports, 45-1 risc timer tables, 21-32 serial communications controllers (sccs) bisync mode, 31-2 general list, 28-2 hdlc mode, 30-1 transparent mode, 32-1 uart mode, 29-2 serial interface, 23-2 serial management controllers (smcs) general list, 36-2 transparent mode, 36-20 uart mode, 36-11 uart mode, features not supported, 36-10 serial peripheral interface (spi), 43-1 siu interrupt controller, 22-1 timers, 26-1 fpsmr register ethernet, 40-20 hdlc mode, 38-8 protocol-specific mode, 37-7 ftirr x (fcc transmit internal rate registers), 41-87 ftodr x (fcc transmit-on-demand registers), 37-8 g gci activation and deactivation, 23-28 programming, 23-28 support, 23-26 gfmr (general fcc mode register), 37-3, 41-83 global error events description, 34-29 restart, 34-30, 34-41 global multi-channel parameters, 34-6 global overrun, 34-30 global underrun, 34-30 gsmr (general scc mode register) appletalk mode, 33-3 hdlc bus protocol, programming, 30-19 overview, 28-3 gsmr_h, 41-90, 41- 91, 41-92, 41-93 h hdlc mode accessing the bus, 30-16 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 index 3-6 freescale semiconductor i?m index 3 cpm index bus controller, 30-14 collision detection, 30-14, 30-17 commands, 30-5 delayed rts mode, 30-18 error handling, 30-6 fast communications controllers (fccs) bit stuffing, 38-1 error control, 38-1 error handling, 38-6 fcce, 38-14 fccm, 38-14 fccs, 38-16 features list, 38-1 fpsmr, 38-8 frame reception, 38-3 frame transmission, 38-2 overview, 38-1 parameter ram, 38-3 programming model, 38-5 receive commands, 38-6 reception errors, 38-7 rxbd, 38-9 transmission errors, 38-6 transmit commands, 38-5 txbd, 38-12 features list, 30-1 gsmr, hdlc bus protocol programming, 30-19 multi-master bus configuration, 30-15 overview, 30-1 parameter ram, 30-3 performance, increasing, 30-17 programming the controller, 30-4 psmr, 30-7 rxbd, 30-8 single-master bus configuration, 30-16 txbd, 30-11 using the tsa, 30-19 i i2add (i 2 c address) register, 44-7 i2brg (i 2 c baud rate generator) register, 44-7 i 2 c controller block diagram, 44-1 brgclk, 44-2 clocking and pin functions, 44-2 commands, 44-11 features list, 44-2 loopback testing, 44-4 master read (slave write), 44-4 master write (slave read), 44-3 multi-master considerations, 44-5 parameter ram, 44-9 programming model, 44-6 registers, 44-6 rxbd, 44-12 slave read (master write), 44-3 slave write (master read), 44-4 transfers, 44-2 txbd, 44-13 i2c memory map, 21-9 i2cer (i 2 c event register), 44-7 i2cmr (i 2 c mask register), 44-7 i2com (i 2 c command) register, 44-8 i2mod (i 2 c mode) register, 44-6 idl interface programming, 23-25 support, 23-22 input/output port memory map, 21-5 interrupt table entry, 34-31 interrupts atm interrupt queues, 41-77 risc timer tables interrupt handling, 21-36 scc interrupt handling, 28-15 inverted signals, 34-3 l loopback mode, 23-6, 34-3 m memory circular interrupt table, external memory, 34-28 internal memory structures mpc860mh, 34-40 memory structure, 34-4 memory map brgs, 21-9 cp, 21-10 cpm mux, 21-14 cpm timers, 21-6 i2c, 21-9 input/output port, 21-5 scc, 21-10 siu, 21-4 smc, 21-13 spi, 21-14 memory maps serial communications controllers (sccs) bisync mode, 31-3 hdlc mode, 30-3 serial management controllers (smcs) gci mode, 36-30 4 datasheet u .com
index 3 cpm index n?p MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor index 3-7 transparent mode, 36-6 uart mode, 36-6 microcode revision number, 21-24 modes atm controller apc modes, 41-8 external rate mode, 41-6 internal rate mode, 41-6 transmit rate modes, 41-6 bisync mode, 31-1 cascaded mode, 26-3 echo mode, 36-1 hdlc mode, 30-1 hunt mode, 29-9 loopback mode, 36-1 nmsi mode, synchronization, 32-3 scc appletalk mode, 33-1 serial interface (si) echo mode, 23-6 serial peripheral interface (spi) master mode, 43-3 transparent mode overview, 39-1 serial communications co ntrollers (sccs), 32-1 serial management controllers (smcs), 36-20 uart mode serial communications co ntrollers (sccs), 29-1 serial management controllers (smcs), 36-10 multi-channel parameters and scc base, 34-4 n nmsi (non-multiplexed serial interface) configuration, 24-3 smc nmsi connection, r eceive and transmit, 36-2 synchronization in nmsi mode, transparent operation, 32-3 nonmulitplexed serial interface (nmsi) mode, 34-2 o operations digital phase-locked loop (dpll) operation, 28-20 smc buffer descriptor, 36-4 transparent operation, nm si sychronization, 32-3 p parallel i/o ports block diagram, 45-16 features, 45-1 overview, 45-18 pdat x , 45-4 pdir x , 45-7 podr x , 45-1 port c interrupts, 45-26 port pin functions, 45-17 ppar, 45-10 programming options, 45-18 psor x , 45-13 registers, 45-1 parameter ram atm controller, 41-35 fast communications controllers (fccs) fast ethernet mode, 40-9 hdlc mode, 38-3 overview, 37-10 hdlc mode, 30-3 i 2 c controller, 44-9 serial communica tions controllers (sccs), 28-12 all protocols, 28-12 base addresses, 28-13 bisync mode, 31-3 uart mode, 29-3 serial management controllers (smcs) gci mode, 36-30 overview, 36-5, 36-30 transparent mode, 36-6 uart mode, 36-6 serial peripheral interface (spi) memory map, 35-12 serial peripheral interface (spi), 43-10 usb controller, 35-12 parameters channel-specific parameters, 34-15 hdlc parameters, 34-15 ram usage over several sccs, 34-40 transparent parameters, 34-19 pdat x (port data) registers, 45-4 pdir x (port data direction registers), 45-7 podr x (port open-drain registers), 45-1 pointers channel pointers mcbase, 34-5 rbase, 34-5 tbase, 34-5 time slot assignment, 34-5 tsatrx, 34-10 tsattx, 34-11 data buffer, 34-6 table pointers time slot assignment, 34-5 power consumption fccs, 37-21 sccs, 28-24 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 index 3-8 freescale semiconductor q?r index 3 cpm index ppar (port pin assignment register), 45-10 programming examples serial communications controllers (sccs) gsmr (general scc mode register) appletalk mode, 33-3 hdlc bus protocol, 30-19 psmr (protocol-specific mode register) appletalk mode, 33-4 todr (transmit-on-demand register) appletalk mode, 33-4 transparent mode nmsi programming example, 36-29 programming model, 35-16 promiscuous mode, see transparent mode promiscuous operation, 39-1 psmr (protocol-specific mode register) appletalk mode, 33-4 bisync mode, 31-9 hdlc bus protocol, programming, 30-19 hdlc mode, 30-7 overview, 28-8 transparent mode, 32-8 uart mode, 29-12 psmr, ethernet mode register, 40-21 psor x (port special options registers), 45-13 q quicc multi-channel controller (qmc) channel addressing capability, 34-1 commands, 34-27 features list, 34-2 global parameters, 34-6 initialization, 34-40 protocol, 34-1 ram usage over several sccs, 34-40 routing table changes, 34-3 r ram channel-specific parameters, 34-15 spi parameter ram memory map, 35-12 rccr (risc controller config uration register), 21-22 registers appletalk mode gsmr, 33-3 psmr, 33-4 todr, 33-4 atm controller fcce, 41-86 fccm, 41-86 fpsmr (fcc protocol-specific mode register), 41-84 ftirr x , 41-87 gfmr register, 41-83 bisync mode bdle, 31-7 bsync, 31-7 psmr, 31-9 scce, 31-14 sccm, 31-14 sccs, 31-15 communications processor (cp) rccr, 21-22 rtscr, 21-23 rtsr, 21-24 communications processor module (cpm) cpcr, 21-24 cpm multiplexing cmxfcr, 24-8 cmxscr, 24-10 cmxsi2cr, 24-8 cmxsmr, 24-13 cmxuar, 24-5 dsr overview, 28-8 uart mode, 29-10 ethernet mode, 40-21 fast communications controllers (fccs) fast ethernet mode fcce, 40-22 fccm, 40-22 fpsmr, 40-20 fcce, 38-14 fcce x , 37-13 fccm x , 37-14 fccs, 38-16 fccs x , 37-14 fcr x , 37-12 fdsr x , 37-7 fpsmr, 38-8 fpsmr x , 37-7 ftodr x , 37-8 gfmr x , 37-3 hdlc mode fccm, 38-14 interrupts, 37-13 timing control, 37-16 gsmr appletalk mode, 33-3 overview, 28-3 hdlc mode chamr, 34-16 intmsk, 34-18 psmr, 30-7 4 datasheet u .com
index 3 cpm index r?r MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor index 3-9 rstate, 34-19 scce, 30-12 sccm, 30-12 sccs, 30-13 tstate, 34-18 i 2 c controller i2add, 44-7 i2brg, 44-7 i2cer, 44-7 i2cmr, 44-7 i2com, 44-8 i2mod, 44-6 parallel i/o ports pdat x , 45-4 pdir x , 45-7 podr x , 45-1 ppar, 45-10 psor x , 45-13 psmr appletalk mode, 33-4 bisync mode, 31-9 overview, 28-8 transparent mode, 32-8 uart mode, 29-12 rfcr, 28-14 risc timer tables rter, 21-35 rtmr, 21-35 tm_cmd, 21-34 scce, 34-30 bisync mode, 31-14 transparent mode, 32-11 uart mode, 29-18 sccm bisync mode, 31-14 transparent mode, 32-11 uart mode, 29-18 sccs bisync mode, 31-15 transparent mode, 32-12 uart mode, 29-20 serial interface (si) si x cmdr, 23-20 si x gmr, 23-14 si x mr, 23-14 si x rsr, 23-20 si x str, 23-21 serial management controllers gci mode smce, 36-34 smcm, 36-34 smcmrs, 36-2 transparent mode smce, 36-28 smcm, 36-28 uart mode rxbd, 36-14 smce, 36-18 smcm, 36-18 txbd, 36-17 serial management controllers (smcs) gci mode rxbd, 36-33 txbd, 36-34 serial peripheral interface (spi) spcom, 43-10 spie, 43-9 spim, 43-9 spmode, 43-6 spmode, 35-17 system interface unit (siu) scprr_h, 22-10 scprr_l, 22-10 sicr, 22-9 siexr, 22-15 simr_h, 22-12 simr_l, 22-13 sipnr_h, 22-11 sipnr_l, 22-12 sivec, 22-14 tfcr, 28-14 timers tcn, 26-7 tcr, 26-7 ter, 26-8 tgcr, 26-3 tmr, 26-5 trr, 26-7 todr, 28-9 appletalk mode, 33-4 toseq, 29-9 transparent mode chamr, 34-21 intmsk, 34-23 psmr, 32-8 rstate, 34-26 scce, 32-11 sccm, 32-11 sccs, 32-12 trnsync, 34-23 tstate, 34-22 uart mode dsr, 29-10 psmr, 29-12 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 index 3-10 freescale semiconductor s?s index 3 cpm index scce, 29-18 sccm, 29-18 sccs, 29-20 toseq, 29-9 usb controller cpcr, 35-32 reset receiver reset sequence, scc, 28-24 resetting registers and parameters for all channels, 21-25 transmitter reset sequence, scc, 28-24 rfcr (rx buffer function code register) overview, 28-14 risc microcontroller, see communications processor module (cpm), communications processor (cp) risc timer tables cp loading tracking, 21-37 features list, 21-32 initializing risc timer tables, 21-35 interrupt handling, 21-36 overview, 21-32 parameter ram, 21-33 ram usage, 21-33 rter, 21-35 rtmr, 21-35 scan algorithm, 21-37 set timer command, 21-35 table entries, 21-35 timer counts, comparing, 21-37 tm_cmd, 21-34 tracking cp loading, 21-37 rter (risc timer event register), 21-35 rtmr (risc timer mask register), 21-35 rtscr (risc time-stamp control register), 21-23 rtsr (risc time-stamp register), 21-24 s scc base parameters, 34-4 changing qmc routing tables, 34-3 global multi-channel parameters, 34-4, 34-6 multiple assignment tables, 34-12 ram usage over several sccs, 34-40 scc memory map, 21-10 scce (scc event) register bisync mode, 31-14 hdlc mode, 30-12 transparent mode, 32-11 uart mode, 29-18 sccm (scc mask) register bisync mode, 31-14 hdlc mode, 30-12 transparent mode, 32-11 uart mode, 29-18 sccs (scc status) register bisync mode, 31-15 hdlc mode, 30-13 transparent mode, 32-12 uart mode, 29-20 scit programming, 23-29 scprr_h (cpm high interrup t priority register), 22-10 scprr_l (cpm low interrupt priority register), 22-10 sdma channels programming model, 27-2 registers, 27-2 serial communications controllers (sccs) appletalk mode connecting to appletalk, 33-2 operating localtalk frame, 33-1 overview, 33-1 programming example, 30-19 programming the controller, 33-3 bisync mode commands, 31-4 control character recognition, 31-5 error handling, 31-9 frame reception, 31-3 frame transmission, 31-2 frames, classes, 31-1 memory map, 31-3 overview, 31-1 parameter ram, 31-3 programming the controller, 31-16 receiving synchronizat ion sequence, 31-8 rxbd, 31-11 sending synchronization sequence, 31-8 txbd, 31-12 buffer descriptors, 28-10 controlling scc timing, 28-16 dpll operation, 28-20 features, 28-2 hdlc mode accessing the bus, 30-16 bus controller, 30-14 collision detection, 30-14, 30-17 commands, 30-5 delayed rts mode, 30-18 error handling, 30-6 features list, 30-1 gsmr, hdlc bus protocol programming, 30-19 interrupts, 30-13 memory map, 30-3 multi-master bus configuration, 30-15 overview, 30-1 4 datasheet u .com
index 3 cpm index s?s MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor index 3-11 parameter ram, 30-3 performance, increasing, 30-17 programming the controller, 30-4 psmr, 30-7 rxbd, 30-8 single-master bus configuration, 30-16 txbd, 30-11 using the tsa, 30-19 initialization, 28-15 interrupt handling, 28-15 parameter ram, 28-12 reconfiguration, 28-23 reset sequence, 28-24 switching protocols, 28-24 transparent mode achieving synchronization, 32-3 commands, 32-6 dsr receiver sync pattern lengths, 32-3 end of frame detection, 32-5 error handling, 32-7 frame reception, 32-2 frame transmission, 32-2 inherent synchronization, 32-5 in-line synchronization, 32-5 overview, 32-1 rxbd, 32-8 synchronization signals, 32-3 synchronization, user-controlled, 32-5 transmit synchronization, 32-3 txbd, 32-10 uart mode commands, 29-5 control character insertion, 29-9 data handling, character and message-based, 29-5 error reporting, 29-5 features list, 29-2 fractional stop bits, 29-10 handling errors, 29-11 hunt mode, 29-9 normal asynchronous mode, 29-2 overview, 29-1 parameter ram, 29-3 rxbd, 29-14 s-records loader a pplication, 29-21 status reporting, 29-5 synchronous mode, 29-3 txbd, 29-17 serial interface (si) enabling connections, 23-6 features, 23-2 gci support, 23-26 idl bus implementation programming the idl, 23-25 idl interface support, 23-22 overview, 23-3 programming gci, 23-28 programming ram entries, 23-9 ram programming example, 23-11 registers, 23-14 si ram, 23-7 serial management controllers (smcs) buffer descriptors, overview, 36-4 disabling smcs on-the-fly, 36-8 disabling the receiver, 36-9 disabling the transmitter, 36-9 enabling the receiver, 36-9 enabling the transmitter, 36-9 features list, 36-2 gci mode c/i channel handling the smc, 36-31 reception process, 36-31 rxbd, 36-33 transmission process, 36-31 txbd, 36-34 commands, 36-32 monitor channel reception process, 36-31 rxbd, 36-32 transmission process, 36-31 txbd, 36-33 overview, 36-30 parameter ram, 36-30 memory structure, 36-5 mode selection, 36-2 nmsi connection, recei ve and transmit, 36-2 parameter ram gci mode, 36-30 overview, 36-5, 36-30 transparent mode, 36-6 uart mode, 36-6 power, saving, 36-10 programming the controller, 36-11 protocol switching, 36-9 reinitializing the receiver, 36-9 reinitializing the transmitter, 36-9 selecting modes, 36-2 sending a break, 36-12 sending a preamble, 36-13 switching protocols, 36-9 transparent mode features list, 36-20 overview, 36-20 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 index 3-12 freescale semiconductor s?s index 3 cpm index parameter ram, 36-6 reception process, 36-21 rxbd, 36-26 txbd, 36-27 uart mode character mode, 36-11 commands, 36-12 data handling, 36-11 error handling, 36-13 features list, 36-11 features not supported by smcs, 36-10 frame format, 36-10 message-oriented mode, 36-11 overview, 36-10 parameter ram, 36-6 programming example, 36-19 reception process, 36-11 rxbd, 36-14 transmission process, 36-11 txbd, 36-17 serial peripheral interface (spi) block diagram, 43-1 buffer descriptor ring, 35-22 clocking and pin functions, 35-2, 43-2 commands, 43-12 configuring the spi, 43-2 features list, 43-1 interrupt handling, 43-18 master mode, 35-5, 35-8, 43-3 maximum receive buffer length (mrblr), 43-11 multi-master operation, 43-4 parameter ram, 43-10 programming example master, 43-16 slave, 43-17 programming model, 35-16, 43-6 receive buffer descriptor, 35-24 rxbd, 43-14 slave, 35-2 slave mode, 43-4 spcom, 43-10 spi block diagram, 35-4, 35-8 spie, 43-9 spim, 43-9 spisel, 35-24, 35-25 spmode, 43-6 txbd, 43-15 sicr (siu interrupt configur ation register), 22-9, 24-5 siexr (siu external interr upt control register), 22-15 signals spisel, 35-24, 35-25 signals, inverted, 34-3 sipmr_h (siu high interrup t mask register), 22-12 sipmr_l (siu low interrupt mask register), 22-13 sipnr_h (siu high interrupt pending register), 22-11 sipnr_l (siu low interrupt pending register), 22-12 sivec (siu interrupt vector register), 22-14 smc memory map, 21-13 smce (smc event) register gci mode, 36-34 transparent mode, 36-28 uart mode, 36-18 smcm (smc mask) register gci mode, 36-34 transparent mode, 36-28 uart mode, 36-18 smcmrs (smc mode registers), 36-2 spcom, 35-19 spcom (spi command) register, 43-10 spi spisel, 35-25 spi memory map, 21-14 spie, 35-20 spie (spi event) register, 43-9 spim (spi mask) register, 43-9 spmode, 35-17 spmode (spi mode) register, 43-6 synchronization, 34-3 system interface unit (siu) add flexibility to cpm interrupt priorities, 22-4 encoding the interrupt vector, 22-6 fcc relative priority, 22-5 highest priority interrupt, 22-5 interrupt controller features list, 22-1 interrupt priorities, flexibility, 22-4 interrupt source priorities, 22-2 interrupt vector calculation, 22-6 interrupt vector encoding, 22-6 interrupt vector generation, 22-6 masking interrupt sources, 22-5 mcc relative priority, 22-5 memory map, 21-4 port c interrupts, 22-8 programming model, 22-9 registers, 22-9 scc relative priority, 22-5 scprr_h, 22-10 scprr_l, 22-10 sicr, 22-9 siexr, 22-15 simr_h, 22-12, 22-13 sipnr_h, 22-11 sipnr_l, 22-12 sivec, 22-14 4 datasheet u .com
index 3 cpm index t?u MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 freescale semiconductor index 3-13 t tcn (timer counter registers), 26-7 tcr (timer capture registers), 26-7 ter (timer event registers), 26-8 tfcr (tx buffer function code register) overview, 28-14 tgcr (timer global configuration registers), 26-3 timers block diagram, 26-1 bus monitoring, 26-3 cascaded mode block diagram, 26-3 features, 26-1 general-purpose units, 26-2 pulse measurement, 26-3 time-slot assigner (tsa) connecting to the tsa, 23-6 overview, 34-2 pointers, 34-5 synchronization in transparent mode, 32-5 tsa tables 32 channels over 2 scc, 34-13 64 channels over 2 sccs, 34-14 64-channel common rx/tx mapping, 34-12 timing scc timing, controlling, 28-16 tm_cmd (risc timer command) register, 21-34 tmr (timer mode registers), 26-5 todr (transmit-on-de mand register), 28-9 appletalk mode, 33-4 toseq (transmit out-of-sequence) register, 29-9 transparent mode achieving synchronization, 32-3 commands, 32-6 dsr receiver sync pattern lengths, 32-3 end of frame detection, 32-5 error handling, 32-7 fast communications controllers (fccs) features list, 39-1 receive operation, 39-2 synchronization achieving, 39-2 example, 39-4 external signals, 39-3 in-line pattern, 39-2 transmit operation, 39-2 frame reception, 32-2 frame transmission, 32-2 inherent synchronization, 32-5 in-line synchronization, 32-5 overview, 32-1 rxbd, 32-8 serial management controllers (smcs) features list, 36-20 overview, 36-20 parameter ram, 36-6 reception process, 36-21 synchronization signals, 32-3 synchronization, user-controlled, 32-5 transmit synchronization, 32-3 txbd, 32-10 trr (timer reference registers), 26-7 u uart mode commands, 29-5 control character insertion, 29-9 data handling, character and message-based, 29-5 error reporting, 29-5 features list, 29-2 fractional stop bits, 29-10 handling errors, 29-11 hunt mode, 29-9 normal asynchronous mode, 29-2 overview, 29-1 parameter ram, 29-3 rxbd, 29-14 serial management controllers character mode, 36-11 commands, 36-12 data handling, 36-11 error handling, 36-13 features list, 36-11 features not supported by smcs, 36-10 frame format, 36-10 message-oriented mode, 36-11 overview, 36-10 parameter ram, 36-6 programming example, 36-19 reception process, 36-11 rxbd, 36-14 transmission process, 36-11 txbd, 36-17 s-records loader application, 29-21 status reporting, 29-5 synchronous mode, 29-3 txbd, 29-17 universal serial bus (usb) controller commands, 35-32 endpoint parameter block, 35-13 error handling, 35-33 parameter ram, 35-12 tokens, 35-6 transmission errors, 35-33 utopia interface, 41-79 4 datasheet u .com
MPC8555E powerquicc? iii integrated proc essor family reference manual, rev. 2 index 3-14 freescale semiconductor u?u index 3 cpm index 4 datasheet u .com
part i? overview i overview 1 memory map 2 signal descriptions 3 reset, clocking, and initialization 4 part ii? e500 core complex and l2 cache ii core complex overview 5 core register summary 6 l2 look-aside cache/sram 7 part iii? memory, security, and i/o interfaces iii e500 coherency module 8 ddr memory controller 9 programmable interrupt controller 10 i 2 c interface 11 duart 12 local bus controller 13 three-speed ethernet controllers 14 dma controller 15 pci bus interface 16 security engine (sec) 2.0 17 part iv? global functions and debug iv global utilities 18 performance monitor 19 debug features and watchpoint facility 20 4 datasheet u .com
i part i? overview 1 overview 2 memory map 3 signal descriptions 4 reset, clocking, and initialization ii part ii? e500 core complex and l2 cache 5 core complex overview 6 core register summary 7 l2 look-aside cache/sram iii part iii? memory, security, and i/o interfaces 8 e500 coherency module 9 ddr memory controller 10 programmable interrupt controller 11 i 2 c interface 12 duart 13 local bus controller 14 three-speed ethernet controllers 15 dma controller 16 pci bus interface 17 security engine (sec) 2.0 iv part iv? global functions and debug 18 global utilities 19 performance monitor 20 debug features and watchpoint facility 4 datasheet u .com
part v? cpm features v communications proce ssor module overview 21 cpm interrupt controller 22 serial interface with time-slot assigner 23 cpm multiplexing 24 baud-rate generators (brgs) 25 cpm timers 26 sdma channels 27 serial communications controllers (sccs) 28 scc uart mode 29 scc hdlc mode 30 scc bisync mode 31 scc transparent mode 32 scc appletalk mode 33 quicc multi-channel controller (qmc) 34 universal serial bus controller 35 serial management controllers (smcs) 36 fast communications controllers (fccs) 37 fcc hdlc controller 38 fcc transparent controller 39 cpm fast ethernet controller 40 atm controller 41 at m a a l 2 42 serial peripheral interface (spi) 43 i 2 c controller 44 parallel i/o ports 45 appendix a?mpc8541e a appendix b?revision history b glossary glo index 1 register index (memory-mapped registers) reg index 2 general index ind index 3 cpm index cpm 4 datasheet u .com
v part v?cpm features 21 communications processor module overview 22 cpm interrupt controller 23 serial interface with time-slot assigner 24 cpm multiplexing 25 baud-rate generators (brgs) 26 cpm timers 27 sdma channels 28 serial communications controllers (sccs) 29 scc uart mode 30 scc hdlc mode 31 scc bisync mode 32 scc transparent mode 33 scc appletalk mode 34 quicc multi-channel controller (qmc) 35 universal serial bus controller 36 serial management controllers (smcs) 37 fast communications controllers (fccs) 38 fcc hdlc controller 39 fcc transparent controller 40 cpm fast ethernet controller 41 atm controller 42 atm aal2 43 serial peripheral interface (spi) 44 i 2 c controller 45 parallel i/o ports a appendix a?mpc8541e b appendix b?revision history glo glossary reg index 1 register index (memory-mapped registers) ind index 2 general index cpm index 3 cpm index 4 datasheet u .com

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